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mlx_nvconfig.c
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1 /*
2  * Copyright (C) 2015 Mellanox Technologies Ltd.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  */
19 
20 FILE_LICENCE ( GPL2_OR_LATER );
21 
22 #include "../../mlx_lib/mlx_nvconfig/mlx_nvconfig.h"
23 #include "../../include/public/mlx_memory.h"
24 #include "../../include/public/mlx_bail.h"
25 
26 #define TlvMappingEntry( _tlv_type, _real_tlv_type, _class_code, _fw_reset_needed) { \
27  .tlv_type = _tlv_type, \
28  .real_tlv_type = _real_tlv_type, \
29  .class_code = _class_code, \
30  .fw_reset_needed = _fw_reset_needed, \
31  }
32 
70  TlvMappingEntry(0, 0, 0, 0),
71 };
72 
73 static
76  IN mlx_utils *utils,
78  )
79 {
80 #define WARM_REBOOT_RESET ((mlx_uint64)0x1 << 38)
82  mlx_uint32 reg_status;
84  mlx_uint8 index = 0;
85  mlx_boolean reset_needed = FALSE;
86 
87  for (index = 0 ; nvconfig_tlv_mapping[index].tlv_type != 0 ; index++) {
90  }
91  }
92 
93  if (reset_needed == FALSE) {
94  goto no_fw_reset_needed;
95  }
96  status = mlx_reg_access(utils, REG_ID_MFRL, REG_ACCESS_WRITE, &mfrl, sizeof(mfrl),
97  &reg_status);
98  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
99 
100  if (reg_status != 0) {
101  MLX_DEBUG_ERROR(utils,"nvconfig_set_fw_reset_level failed with status = %d\n", reg_status);
102  status = MLX_FAILED;
103  goto reg_err;
104  }
105 reg_err:
106 no_fw_reset_needed:
107  return status;
108 }
109 
110 
111 static
117  )
118 {
119  mlx_uint8 index = 0;
120  for ( ; nvconfig_tlv_mapping[index].tlv_type != 0 ; index ++) {
124  return MLX_SUCCESS;
125  }
126  }
127  return MLX_NOT_FOUND;
128 }
129 static
130 void
132  IN mlx_uint8 port,
136  )
137 {
138  switch (class_code) {
142  break;
146  break;
151  break;
152  }
153 }
156  IN mlx_utils *utils,
157  IN mlx_uint8 port,
159  OUT mlx_boolean *read_supported,
160  OUT mlx_boolean *write_supported
161  )
162 {
164  struct nvconfig_nvqc nvqc;
165  mlx_uint32 reg_status;
166  NVRAM_CLASS_CODE class_code;
167  mlx_uint16 real_tlv_type;
168 
169  if (utils == NULL || read_supported == NULL || write_supported == NULL) {
171  goto bad_param;
172  }
173 
174  status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
175  MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
176 
177  mlx_memory_set(utils, &nvqc, 0, sizeof(nvqc));
178  nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nvqc.tlv_type);
179 
180  status = mlx_reg_access(utils, REG_ID_NVQC, REG_ACCESS_READ, &nvqc, sizeof(nvqc),
181  &reg_status);
182  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
183  if (reg_status != 0) {
184  MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
185  status = MLX_FAILED;
186  goto reg_err;
187  }
188  *read_supported = nvqc.support_rd;
189  *write_supported = nvqc.support_wr;
190 reg_err:
191 tlv_not_supported:
192 bad_param:
193  return status;
194 }
195 
198  IN mlx_utils *utils,
199  IN mlx_uint8 port,
201  )
202 {
204  struct nvconfig_header nv_header;
205  mlx_uint32 reg_status;
206  NVRAM_CLASS_CODE class_code;
207  mlx_uint16 real_tlv_type;
208 
209  if (utils == NULL) {
211  goto bad_param;
212  }
213 
214  status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
215  MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
216 
217  mlx_memory_set(utils, &nv_header, 0, sizeof(nv_header));
218  nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nv_header.tlv_type);
219 
220  status = mlx_reg_access(utils, REG_ID_NVDI, REG_ACCESS_WRITE, &nv_header, sizeof(nv_header),
221  &reg_status);
222  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
223  if (reg_status != 0) {
224  MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
225  status = MLX_FAILED;
226  goto reg_err;
227  }
228 reg_err:
229 tlv_not_supported:
230 bad_param:
231  return status;
232 }
233 
236  IN mlx_utils *utils,
237  IN mlx_uint8 port,
239  IN REG_ACCESS_OPT opt,
240  IN mlx_size data_size,
241  IN NV_DEFAULT_OPT def_en,
245  )
246 {
248  struct nvconfig_nvda nvda;
249  mlx_uint32 reg_status;
250  mlx_uint32 real_size_to_read;
252  NVRAM_CLASS_CODE class_code;
253  mlx_uint16 real_tlv_type;
254  mlx_size data_size_align_to_dword;
255 
256  if (utils == NULL || data == NULL || data_size > NVCONFIG_MAX_TLV_SIZE) {
258  goto bad_param;
259  }
260 
261  status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
262  MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
263 
264  data_size_align_to_dword = ((data_size + 3) / sizeof(mlx_uint32)) * sizeof(mlx_uint32);
265  mlx_memory_set(utils, &nvda, 0, sizeof(nvda));
266  nvda.nv_header.length = data_size_align_to_dword;
267  nvda.nv_header.access_mode = def_en;
268  nvda.nv_header.version = *version;
269  nvda.nv_header.writer_id = writer_id;
270 
271  nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nvda.nv_header.tlv_type);
272 
273  mlx_memory_cpy(utils, nvda.data, data, data_size);
274  for (index = 0 ; index * 4 < NVCONFIG_MAX_TLV_SIZE ; index++) {
275  mlx_memory_be32_to_cpu(utils,(((mlx_uint32 *)nvda.data)[index]), ((mlx_uint32 *)nvda.data) + index);
276  }
277  status = mlx_reg_access(utils, REG_ID_NVDA, opt, &nvda,
278  data_size_align_to_dword + sizeof(nvda.nv_header), &reg_status);
279  MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
280  if (reg_status != 0) {
281  MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
282  status = MLX_FAILED;
283  goto reg_err;
284  }
285  for (index = 0 ; index * 4 < NVCONFIG_MAX_TLV_SIZE ; index++) {
286  mlx_memory_cpu_to_be32(utils,(((mlx_uint32 *)nvda.data)[index]), ((mlx_uint32 *)nvda.data) + index);
287  }
288  if (opt == REG_ACCESS_READ) {
289  real_size_to_read = (nvda.nv_header.length > data_size) ? data_size :
290  nvda.nv_header.length;
291  mlx_memory_cpy(utils, data, nvda.data, real_size_to_read);
292  *version = nvda.nv_header.version;
293  } else {
294  nvconfig_set_fw_reset_level(utils, tlv_type);
295  }
296 reg_err:
297 tlv_not_supported:
298 bad_param:
299  return status;
300 }
301 
302 
uint8_t mlx_boolean
struct nvconfig_tlv_type_per_port per_port
Definition: mlx_nvconfig.h:71
#define REG_ID_MFRL
struct nvconfig_tlv_type_global global
Definition: mlx_nvconfig.h:73
mlx_status mlx_memory_cpu_to_be32(IN mlx_utils *utils, IN mlx_uint32 source, IN mlx_uint32 *destination)
Definition: mlx_memory.c:207
mlx_uint32 access_mode
Definition: mlx_nvconfig.h:95
static mlx_status nvconfig_get_tlv_type_and_class(IN mlx_uint16 tlv_type, OUT mlx_uint16 *real_tlv_type, OUT NVRAM_CLASS_CODE *class_code)
Definition: mlx_nvconfig.c:113
#define MLX_INVALID_PARAMETER
#define REG_ID_NVDI
#define REG_ID_NVQC
mlx_boolean fw_reset_needed
Definition: mlx_nvconfig.h:67
mlx_uint8 data[NVCONFIG_MAX_TLV_SIZE]
Definition: mlx_nvconfig.h:116
struct nvconfig_tlv_type_per_host per_host
Definition: mlx_nvconfig.h:72
REG_ACCESS_OPT
FILE_LICENCE(GPL2_OR_LATER)
static void nvconfig_fill_tlv_type(IN mlx_uint8 port, IN NVRAM_CLASS_CODE class_code, IN mlx_uint16 tlv_type, OUT union nvconfig_tlv_type *nvconfig_tlv_type)
Definition: mlx_nvconfig.c:131
mlx_status nvconfig_nvdata_invalidate(IN mlx_utils *utils, IN mlx_uint8 port, IN mlx_uint16 tlv_type)
Definition: mlx_nvconfig.c:197
uint8_t status
Status.
Definition: ena.h:16
uint32_t mlx_uint32
#define WARM_REBOOT_RESET
union nvconfig_tlv_type tlv_type
Definition: mlx_nvconfig.h:105
mlx_status mlx_memory_set(IN mlx_utils *utils, IN mlx_void *block, IN mlx_int32 value, IN mlx_size size)
Definition: mlx_memory.c:171
u8 port
Port number.
Definition: CIB_PRM.h:31
mlx_uint32 writer_id
Definition: mlx_nvconfig.h:92
u32 version
Version number.
Definition: ath9k_hw.c:1983
#define OUT
Definition: mlx_utils.h:29
#define MLX_NOT_FOUND
mlx_uint32 support_rd
Definition: mlx_nvconfig.h:80
NVRAM_CLASS_CODE class_code
Definition: mlx_nvconfig.h:66
mlx_uint16 real_tlv_type
Definition: mlx_nvconfig.h:65
static mlx_status nvconfig_set_fw_reset_level(IN mlx_utils *utils, IN mlx_uint16 tlv_type)
Definition: mlx_nvconfig.c:75
#define MLX_SUCCESS
mlx_uint32 version
Definition: mlx_nvconfig.h:91
size_t mlx_size
#define REG_ID_NVDA
#define MLX_FAILED
#define TRUE
Definition: tlan.h:46
uint16_t mlx_uint16
void mlx_void
#define IN
Definition: mlx_utils.h:28
#define NVCONFIG_MAX_TLV_SIZE
Definition: mlx_nvconfig.h:112
uint8_t mlx_uint8
mlx_status mlx_memory_cpy(IN mlx_utils *utils, OUT mlx_void *destination_buffer, IN mlx_void *source_buffer, IN mlx_size length)
Definition: mlx_memory.c:189
union nvconfig_tlv_type tlv_type
Definition: mlx_nvconfig.h:78
#define TlvMappingEntry(_tlv_type, _real_tlv_type, _class_code, _fw_reset_needed)
Definition: mlx_nvconfig.c:26
#define MLX_DEBUG_ERROR(...)
Definition: mlx_logging.h:29
#define FALSE
Definition: tlan.h:45
NV_DEFAULT_OPT
Definition: mlx_nvconfig.h:39
int mlx_status
struct nvconfig_header nv_header
Definition: mlx_nvconfig.h:115
mlx_status mlx_memory_be32_to_cpu(IN mlx_utils *utils, IN mlx_uint32 source, IN mlx_uint32 *destination)
Definition: mlx_memory.c:224
mlx_status mlx_reg_access(IN mlx_utils *utils, IN mlx_uint16 reg_id, IN REG_ACCESS_OPT reg_opt, IN OUT mlx_void *reg_data, IN mlx_size reg_size, OUT mlx_uint32 *reg_status)
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
uint64_t mlx_uint64
NVRAM_CLASS_CODE
Definition: mlx_nvconfig.h:28
#define MLX_CHECK_STATUS(id, status, label, message)
Definition: mlx_bail.h:37
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
mlx_status nvconfig_query_capability(IN mlx_utils *utils, IN mlx_uint8 port, IN mlx_uint16 tlv_type, OUT mlx_boolean *read_supported, OUT mlx_boolean *write_supported)
Definition: mlx_nvconfig.c:155
NVDA_WRITER_ID
Definition: mlx_nvconfig.h:34
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
mlx_status nvconfig_nvdata_access(IN mlx_utils *utils, IN mlx_uint8 port, IN mlx_uint16 tlv_type, IN REG_ACCESS_OPT opt, IN mlx_size data_size, IN NV_DEFAULT_OPT def_en, IN NVDA_WRITER_ID writer_id, IN OUT mlx_uint8 *version, IN OUT mlx_void *data)
Definition: mlx_nvconfig.c:235
mlx_uint32 support_wr
Definition: mlx_nvconfig.h:81
mlx_uint32 length
Definition: mlx_nvconfig.h:89