iPXE
jme.c
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00001 /*
00002  * JMicron JMC2x0 series PCIe Ethernet gPXE Device Driver
00003  *
00004  * Copyright 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
00005  *
00006  * This program is free software; you can redistribute it and/or modify
00007  * it under the terms of the GNU General Public License as published by
00008  * the Free Software Foundation; either version 2 of the License.
00009  *
00010  * This program is distributed in the hope that it will be useful,
00011  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00012  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013  * GNU General Public License for more details.
00014  *
00015  * You should have received a copy of the GNU General Public License
00016  * along with this program; if not, write to the Free Software
00017  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00018  * 02110-1301, USA.
00019  *
00020  */
00021 FILE_LICENCE ( GPL2_OR_LATER );
00022 
00023 #include <stdint.h>
00024 #include <stdlib.h>
00025 #include <stdio.h>
00026 #include <string.h>
00027 #include <ipxe/io.h>
00028 #include <errno.h>
00029 #include <unistd.h>
00030 #include <byteswap.h>
00031 #include <ipxe/pci.h>
00032 #include <ipxe/if_ether.h>
00033 #include <ipxe/ethernet.h>
00034 #include <ipxe/iobuf.h>
00035 #include <ipxe/netdevice.h>
00036 #include <ipxe/malloc.h>
00037 #include <mii.h>
00038 #include "jme.h"
00039 
00040 static int
00041 jme_mdio_read(struct net_device *netdev, int phy, int reg)
00042 {
00043         struct jme_adapter *jme = netdev->priv;
00044         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
00045 
00046 read_again:
00047         jwrite32(jme, JME_SMI, SMI_OP_REQ |
00048                                 smi_phy_addr(phy) |
00049                                 smi_reg_addr(reg));
00050 
00051         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
00052                 udelay(20);
00053                 val = jread32(jme, JME_SMI);
00054                 if ((val & SMI_OP_REQ) == 0)
00055                         break;
00056         }
00057 
00058         if (i == 0) {
00059                 DBG("phy(%d) read timeout : %d\n", phy, reg);
00060                 return 0;
00061         }
00062 
00063         if (again--)
00064                 goto read_again;
00065 
00066         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
00067 }
00068 
00069 static void
00070 jme_mdio_write(struct net_device *netdev,
00071                                 int phy, int reg, int val)
00072 {
00073         struct jme_adapter *jme = netdev->priv;
00074         int i;
00075 
00076         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
00077                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
00078                 smi_phy_addr(phy) | smi_reg_addr(reg));
00079 
00080         wmb();
00081         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
00082                 udelay(20);
00083                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
00084                         break;
00085         }
00086 
00087         if (i == 0)
00088                 DBG("phy(%d) write timeout : %d\n", phy, reg);
00089 
00090         return;
00091 }
00092 
00093 static void
00094 jme_reset_phy_processor(struct jme_adapter *jme)
00095 {
00096         u32 val;
00097 
00098         jme_mdio_write(jme->mii_if.dev,
00099                         jme->mii_if.phy_id,
00100                         MII_ADVERTISE, ADVERTISE_ALL |
00101                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
00102 
00103         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
00104                 jme_mdio_write(jme->mii_if.dev,
00105                                 jme->mii_if.phy_id,
00106                                 MII_CTRL1000,
00107                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
00108 
00109         val = jme_mdio_read(jme->mii_if.dev,
00110                                 jme->mii_if.phy_id,
00111                                 MII_BMCR);
00112 
00113         jme_mdio_write(jme->mii_if.dev,
00114                         jme->mii_if.phy_id,
00115                         MII_BMCR, val | BMCR_RESET);
00116 
00117         return;
00118 }
00119 
00120 static void
00121 jme_phy_init(struct jme_adapter *jme)
00122 {
00123         u16 reg26;
00124 
00125         reg26 = jme_mdio_read(jme->mii_if.dev, jme->mii_if.phy_id, 26);
00126         jme_mdio_write(jme->mii_if.dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
00127 }
00128 
00129 static void
00130 jme_set_phyfifoa(struct jme_adapter *jme)
00131 {
00132         jme_mdio_write(jme->mii_if.dev, jme->mii_if.phy_id, 27, 0x0004);
00133 }
00134 
00135 static void
00136 jme_set_phyfifob(struct jme_adapter *jme)
00137 {
00138         jme_mdio_write(jme->mii_if.dev, jme->mii_if.phy_id, 27, 0x0000);
00139 }
00140 
00141 static void
00142 jme_phy_off(struct jme_adapter *jme)
00143 {
00144         jme_mdio_write(jme->mii_if.dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
00145 }
00146 
00147 static void
00148 jme_restart_an(struct jme_adapter *jme)
00149 {
00150         uint32_t bmcr;
00151 
00152         bmcr = jme_mdio_read(jme->mii_if.dev, jme->mii_if.phy_id, MII_BMCR);
00153         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
00154         jme_mdio_write(jme->mii_if.dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
00155 }
00156 
00157 static void
00158 jme_reset_ghc_speed(struct jme_adapter *jme)
00159 {
00160         jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
00161         jwrite32(jme, JME_GHC, jme->reg_ghc);
00162 }
00163 
00164 static void
00165 jme_start_irq(struct jme_adapter *jme)
00166 {
00167         /*
00168          * Enable Interrupts
00169          */
00170         jwrite32(jme, JME_IENS, INTR_ENABLE);
00171 }
00172 
00173 static void
00174 jme_stop_irq(struct jme_adapter *jme)
00175 {
00176         /*
00177          * Disable Interrupts
00178          */
00179         jwrite32f(jme, JME_IENC, INTR_ENABLE);
00180 }
00181 
00182 static void
00183 jme_setup_wakeup_frame(struct jme_adapter *jme,
00184                 u32 *mask, u32 crc, int fnr)
00185 {
00186         int i;
00187 
00188         /*
00189          * Setup CRC pattern
00190          */
00191         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
00192         wmb();
00193         jwrite32(jme, JME_WFODP, crc);
00194         wmb();
00195 
00196         /*
00197          * Setup Mask
00198          */
00199         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
00200                 jwrite32(jme, JME_WFOI,
00201                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
00202                                 (fnr & WFOI_FRAME_SEL));
00203                 wmb();
00204                 jwrite32(jme, JME_WFODP, mask[i]);
00205                 wmb();
00206         }
00207 }
00208 
00209 static void
00210 jme_reset_mac_processor(struct jme_adapter *jme)
00211 {
00212         u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
00213         u32 crc = 0xCDCDCDCD;
00214         int i;
00215 
00216         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
00217         udelay(2);
00218         jwrite32(jme, JME_GHC, jme->reg_ghc);
00219 
00220         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
00221         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
00222         jwrite32(jme, JME_RXQDC, 0x00000000);
00223         jwrite32(jme, JME_RXNDA, 0x00000000);
00224         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
00225         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
00226         jwrite32(jme, JME_TXQDC, 0x00000000);
00227         jwrite32(jme, JME_TXNDA, 0x00000000);
00228 
00229         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
00230         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
00231         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
00232                 jme_setup_wakeup_frame(jme, mask, crc, i);
00233         jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
00234         jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
00235 }
00236 
00237 static void
00238 jme_free_tx_buffers(struct jme_adapter *jme)
00239 {
00240         struct jme_ring *txring = &jme->txring;
00241         struct io_buffer *txbi;
00242         unsigned int i;
00243 
00244         for (i = 0; i < jme->tx_ring_size; ++i) {
00245                 txbi = txring->bufinf[i];
00246                 if (txbi) {
00247                         netdev_tx_complete_err(jme->mii_if.dev,
00248                                         txbi, -ENOLINK);
00249                         txring->bufinf[i] = NULL;
00250                 }
00251         }
00252 }
00253 
00254 static void
00255 jme_free_tx_resources(struct jme_adapter *jme)
00256 {
00257         struct jme_ring *txring = &jme->txring;
00258 
00259         if (txring->desc) {
00260                 if (txring->bufinf) {
00261                         memset(txring->bufinf, 0,
00262                                 sizeof(struct io_buffer *) * jme->tx_ring_size);
00263                         free(txring->bufinf);
00264                 }
00265                 free_dma(txring->desc, jme->tx_ring_size * TX_DESC_SIZE);
00266                 txring->desc            = NULL;
00267                 txring->dma             = 0;
00268                 txring->bufinf          = NULL;
00269         }
00270         txring->next_to_use     = 0;
00271         txring->next_to_clean   = 0;
00272         txring->nr_free         = 0;
00273 }
00274 
00275 static int
00276 jme_alloc_tx_resources(struct jme_adapter *jme)
00277 {
00278         struct jme_ring *txring = &jme->txring;
00279 
00280         txring->desc = malloc_dma(jme->tx_ring_size * TX_DESC_SIZE,
00281                                         RING_DESC_ALIGN);
00282         if (!txring->desc) {
00283                 DBG("Can not allocate transmit ring descriptors.\n");
00284                 goto err_out;
00285         }
00286 
00287         /*
00288          * 16 Bytes align
00289          */
00290         txring->dma             = virt_to_bus(txring->desc);
00291         txring->bufinf          = malloc(sizeof(struct io_buffer *) *
00292                                         jme->tx_ring_size);
00293         if (!(txring->bufinf)) {
00294                 DBG("Can not allocate transmit buffer info.\n");
00295                 goto err_out;
00296         }
00297 
00298         /*
00299          * Initialize Transmit Buffer Pointers
00300          */
00301         memset(txring->bufinf, 0,
00302                 sizeof(struct io_buffer *) * jme->tx_ring_size);
00303 
00304         return 0;
00305 
00306 err_out:
00307         jme_free_tx_resources(jme);
00308         return -ENOMEM;
00309 }
00310 
00311 static void
00312 jme_init_tx_ring(struct jme_adapter *jme)
00313 {
00314         struct jme_ring *txring = &jme->txring;
00315 
00316         txring->next_to_clean   = 0;
00317         txring->next_to_use     = 0;
00318         txring->nr_free         = jme->tx_ring_size;
00319 
00320         /*
00321          * Initialize Transmit Descriptors
00322          */
00323         memset(txring->desc, 0, jme->tx_ring_size * TX_DESC_SIZE);
00324         jme_free_tx_buffers(jme);
00325 }
00326 
00327 static void
00328 jme_enable_tx_engine(struct jme_adapter *jme)
00329 {
00330         /*
00331          * Select Queue 0
00332          */
00333         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
00334         wmb();
00335 
00336         /*
00337          * Setup TX Queue 0 DMA Bass Address
00338          */
00339         jwrite32(jme, JME_TXDBA_LO, (uint64_t)jme->txring.dma & 0xFFFFFFFFUL);
00340         jwrite32(jme, JME_TXDBA_HI, (uint64_t)(jme->txring.dma) >> 32);
00341         jwrite32(jme, JME_TXNDA, (uint64_t)jme->txring.dma & 0xFFFFFFFFUL);
00342 
00343         /*
00344          * Setup TX Descptor Count
00345          */
00346         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
00347 
00348         /*
00349          * Enable TX Engine
00350          */
00351         wmb();
00352         jwrite32(jme, JME_TXCS, jme->reg_txcs |
00353                                 TXCS_SELECT_QUEUE0 |
00354                                 TXCS_ENABLE);
00355 
00356 }
00357 
00358 static void
00359 jme_disable_tx_engine(struct jme_adapter *jme)
00360 {
00361         int i;
00362         u32 val;
00363 
00364         /*
00365          * Disable TX Engine
00366          */
00367         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
00368         wmb();
00369 
00370         val = jread32(jme, JME_TXCS);
00371         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
00372                 mdelay(1);
00373                 val = jread32(jme, JME_TXCS);
00374                 rmb();
00375         }
00376 
00377         if (!i)
00378                 DBG("Disable TX engine timeout.\n");
00379 }
00380 
00381 
00382 static void
00383 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
00384 {
00385         struct jme_ring *rxring = &jme->rxring;
00386         register struct rxdesc *rxdesc = rxring->desc;
00387         struct io_buffer *rxbi = rxring->bufinf[i];
00388         uint64_t mapping;
00389 
00390         rxdesc += i;
00391         mapping = virt_to_bus(rxbi->data);
00392 
00393         rxdesc->dw[0] = 0;
00394         rxdesc->dw[1] = 0;
00395         rxdesc->desc1.bufaddrh  = cpu_to_le32(mapping >> 32);
00396         rxdesc->desc1.bufaddrl  = cpu_to_le32(mapping & 0xFFFFFFFFUL);
00397         rxdesc->desc1.datalen   = cpu_to_le16(RX_ALLOC_LEN);
00398         wmb();
00399         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
00400 }
00401 
00402 static int
00403 jme_make_new_rx_buf(struct io_buffer **rxbip)
00404 {
00405         struct io_buffer *inbuf;
00406 
00407         /*
00408          * IOB_ALIGN == 2048
00409          */
00410         inbuf = alloc_iob(RX_ALLOC_LEN);
00411         if (!inbuf) {
00412                 DBG("Allocate receive iob error.\n");
00413                 return -ENOMEM;
00414         }
00415         *rxbip = inbuf;
00416 
00417         return 0;
00418 }
00419 
00420 static void
00421 jme_free_rx_buf(struct jme_adapter *jme, int i)
00422 {
00423         struct jme_ring *rxring = &jme->rxring;
00424         struct io_buffer *rxbi = rxring->bufinf[i];
00425 
00426         if (rxbi) {
00427                 free_iob(rxbi);
00428                 rxring->bufinf[i] = NULL;
00429         }
00430 }
00431 
00432 static void
00433 jme_free_rx_resources(struct jme_adapter *jme)
00434 {
00435         unsigned int i;
00436         struct jme_ring *rxring = &jme->rxring;
00437 
00438         if (rxring->desc) {
00439                 if (rxring->bufinf) {
00440                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
00441                                 jme_free_rx_buf(jme, i);
00442                         free(rxring->bufinf);
00443                 }
00444 
00445                 free_dma(rxring->desc, jme->rx_ring_size * RX_DESC_SIZE);
00446                 rxring->desc     = NULL;
00447                 rxring->dma      = 0;
00448                 rxring->bufinf   = NULL;
00449         }
00450         rxring->next_to_fill = 0;
00451         rxring->next_to_clean = 0;
00452 }
00453 
00454 static int
00455 jme_alloc_rx_resources(struct jme_adapter *jme)
00456 {
00457         unsigned int i;
00458         struct jme_ring *rxring = &jme->rxring;
00459         struct io_buffer **bufinf;
00460 
00461         rxring->desc = malloc_dma(jme->rx_ring_size * RX_DESC_SIZE,
00462                         RING_DESC_ALIGN);
00463         if (!rxring->desc) {
00464                 DBG("Can not allocate receive ring descriptors.\n");
00465                 goto err_out;
00466         }
00467 
00468         /*
00469          * 16 Bytes align
00470          */
00471         rxring->dma             = virt_to_bus(rxring->desc);
00472         rxring->bufinf          = malloc(sizeof(struct io_buffer *) *
00473                                         jme->rx_ring_size);
00474         if (!(rxring->bufinf)) {
00475                 DBG("Can not allocate receive buffer info.\n");
00476                 goto err_out;
00477         }
00478 
00479         /*
00480          * Initiallize Receive Buffer Pointers
00481          */
00482         bufinf = rxring->bufinf;
00483         memset(bufinf, 0, sizeof(struct io_buffer *) * jme->rx_ring_size);
00484         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
00485                 if (jme_make_new_rx_buf(bufinf))
00486                         goto err_out;
00487                 ++bufinf;
00488         }
00489 
00490         return 0;
00491 
00492 err_out:
00493         jme_free_rx_resources(jme);
00494         return -ENOMEM;
00495 }
00496 
00497 static void
00498 jme_init_rx_ring(struct jme_adapter *jme)
00499 {
00500         unsigned int i;
00501         struct jme_ring *rxring = &jme->rxring;
00502 
00503         for (i = 0 ; i < jme->rx_ring_size ; ++i)
00504                 jme_set_clean_rxdesc(jme, i);
00505 
00506         rxring->next_to_fill = 0;
00507         rxring->next_to_clean = 0;
00508 }
00509 
00510 static void
00511 jme_set_multi(struct jme_adapter *jme)
00512 {
00513         /*
00514          * Just receive all kind of packet for new.
00515          */
00516         jme->reg_rxmcs |= RXMCS_ALLFRAME | RXMCS_BRDFRAME | RXMCS_UNIFRAME;
00517         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
00518 }
00519 
00520 static void
00521 jme_enable_rx_engine(struct jme_adapter *jme)
00522 {
00523         /*
00524          * Select Queue 0
00525          */
00526         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
00527                                 RXCS_QUEUESEL_Q0);
00528         wmb();
00529 
00530         /*
00531          * Setup RX DMA Bass Address
00532          */
00533         jwrite32(jme, JME_RXDBA_LO, (uint64_t)(jme->rxring.dma) & 0xFFFFFFFFUL);
00534         jwrite32(jme, JME_RXDBA_HI, (uint64_t)(jme->rxring.dma) >> 32);
00535         jwrite32(jme, JME_RXNDA, (uint64_t)(jme->rxring.dma) & 0xFFFFFFFFUL);
00536 
00537         /*
00538          * Setup RX Descriptor Count
00539          */
00540         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
00541 
00542         /*
00543          * Setup Unicast Filter
00544          */
00545         jme_set_multi(jme);
00546 
00547         /*
00548          * Enable RX Engine
00549          */
00550         wmb();
00551         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
00552                                 RXCS_QUEUESEL_Q0 |
00553                                 RXCS_ENABLE |
00554                                 RXCS_QST);
00555 }
00556 
00557 static void
00558 jme_restart_rx_engine(struct jme_adapter *jme)
00559 {
00560         /*
00561          * Start RX Engine
00562          */
00563         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
00564                                 RXCS_QUEUESEL_Q0 |
00565                                 RXCS_ENABLE |
00566                                 RXCS_QST);
00567 }
00568 
00569 static void
00570 jme_disable_rx_engine(struct jme_adapter *jme)
00571 {
00572         int i;
00573         u32 val;
00574 
00575         /*
00576          * Disable RX Engine
00577          */
00578         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
00579         wmb();
00580 
00581         val = jread32(jme, JME_RXCS);
00582         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
00583                 mdelay(1);
00584                 val = jread32(jme, JME_RXCS);
00585                 rmb();
00586         }
00587 
00588         if (!i)
00589                 DBG("Disable RX engine timeout.\n");
00590 
00591 }
00592 
00593 static void
00594 jme_refill_rx_ring(struct jme_adapter *jme, int curhole)
00595 {
00596         struct jme_ring *rxring = &jme->rxring;
00597         int i = rxring->next_to_fill;
00598         struct io_buffer **bufinf = rxring->bufinf;
00599         int mask = jme->rx_ring_mask;
00600         int limit = jme->rx_ring_size;
00601 
00602         while (limit--) {
00603                 if (!bufinf[i]) {
00604                         if (jme_make_new_rx_buf(bufinf + i))
00605                                 break;
00606                         jme_set_clean_rxdesc(jme, i);
00607                 }
00608                 if (i == curhole)
00609                         limit = 0;
00610                 i = (i + 1) & mask;
00611         }
00612         rxring->next_to_fill = i;
00613 }
00614 
00615 static void
00616 jme_alloc_and_feed_iob(struct jme_adapter *jme, int idx)
00617 {
00618         struct jme_ring *rxring = &jme->rxring;
00619         struct rxdesc *rxdesc = rxring->desc;
00620         struct io_buffer *rxbi = rxring->bufinf[idx];
00621         struct net_device *netdev = jme->mii_if.dev;
00622         int framesize;
00623 
00624         rxdesc += idx;
00625 
00626         framesize = le16_to_cpu(rxdesc->descwb.framesize);
00627         iob_put(rxbi, framesize);
00628         netdev_rx(netdev, rxbi);
00629 
00630         rxring->bufinf[idx] = NULL;
00631         jme_refill_rx_ring(jme, idx);
00632 }
00633 
00634 static void
00635 jme_process_receive(struct jme_adapter *jme)
00636 {
00637         struct jme_ring *rxring = &jme->rxring;
00638         struct rxdesc *rxdesc = rxring->desc;
00639         struct net_device *netdev = jme->mii_if.dev;
00640         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
00641         unsigned int limit = jme->rx_ring_size;
00642 
00643         i = rxring->next_to_clean;
00644         rxdesc += i;
00645         while (rxring->bufinf[i] &&
00646                 !(rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) &&
00647                 (rxdesc->descwb.desccnt & RXWBDCNT_WBCPL) &&
00648                 limit--) {
00649 
00650                 rmb();
00651                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
00652                 DBG2("Cleaning rx desc=%d, cnt=%d\n", i, desccnt);
00653 
00654                 if (desccnt > 1 || rxdesc->descwb.errstat & RXWBERR_ALLERR) {
00655                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
00656                                 jme_set_clean_rxdesc(jme, j);
00657                                 j = (j + 1) & (mask);
00658                         }
00659                         DBG("Dropped packet due to ");
00660                         if (desccnt > 1)
00661                                 DBG("long packet.(%d descriptors)\n", desccnt);
00662                         else
00663                                 DBG("Packet error.\n");
00664                         netdev_rx_err(netdev, NULL, -EINVAL);
00665                 } else {
00666                         jme_alloc_and_feed_iob(jme, i);
00667                 }
00668 
00669                 i = (i + desccnt) & (mask);
00670                 rxdesc = rxring->desc;
00671                 rxdesc += i;
00672         }
00673         rxring->next_to_clean = i;
00674 
00675         return;
00676 }
00677 
00678 static void
00679 jme_set_custom_macaddr(struct net_device *netdev)
00680 {
00681         struct jme_adapter *jme = netdev->priv;
00682         uint8_t *addr = netdev->ll_addr;
00683         u32 val;
00684 
00685         val = (addr[3] & 0xff) << 24 |
00686               (addr[2] & 0xff) << 16 |
00687               (addr[1] & 0xff) <<  8 |
00688               (addr[0] & 0xff);
00689         jwrite32(jme, JME_RXUMA_LO, val);
00690         val = (addr[5] & 0xff) << 8 |
00691               (addr[4] & 0xff);
00692         jwrite32(jme, JME_RXUMA_HI, val);
00693 }
00694 
00695 /**
00696  * Open NIC
00697  *
00698  * @v netdev            Net device
00699  * @ret rc              Return status code
00700  */
00701 static int
00702 jme_open(struct net_device *netdev)
00703 {
00704         struct jme_adapter *jme = netdev->priv;
00705         int rc;
00706 
00707         /*
00708          * Allocate receive resources
00709          */
00710         rc = jme_alloc_rx_resources(jme);
00711         if (rc) {
00712                 DBG("Allocate receive resources error.\n");
00713                 goto nomem_out;
00714         }
00715 
00716         /*
00717          * Allocate transmit resources
00718          */
00719         rc = jme_alloc_tx_resources(jme);
00720         if (rc) {
00721                 DBG("Allocate transmit resources error.\n");
00722                 goto free_rx_resources_out;
00723         }
00724 
00725         jme_set_custom_macaddr(netdev);
00726         jme_reset_phy_processor(jme);
00727         jme_restart_an(jme);
00728 
00729         return 0;
00730 
00731 free_rx_resources_out:
00732         jme_free_rx_resources(jme);
00733 nomem_out:
00734         return rc;
00735 }
00736 
00737 /**
00738  * Close NIC
00739  *
00740  * @v netdev            Net device
00741  */
00742 static void
00743 jme_close(struct net_device *netdev)
00744 {
00745         struct jme_adapter *jme = netdev->priv;
00746 
00747         jme_free_tx_resources(jme);
00748         jme_free_rx_resources(jme);
00749         jme_reset_mac_processor(jme);
00750         jme->phylink = 0;
00751         jme_phy_off(jme);
00752         netdev_link_down(netdev);
00753 }
00754 
00755 static int
00756 jme_alloc_txdesc(struct jme_adapter *jme)
00757 {
00758         struct jme_ring *txring = &jme->txring;
00759         int idx;
00760 
00761         idx = txring->next_to_use;
00762         if (txring->nr_free < 1)
00763                 return -1;
00764         --(txring->nr_free);
00765         txring->next_to_use = (txring->next_to_use + 1) & jme->tx_ring_mask;
00766 
00767         return idx;
00768 }
00769 
00770 static void
00771 jme_fill_tx_desc(struct jme_adapter *jme, struct io_buffer *iob, int idx)
00772 {
00773         struct jme_ring *txring = &jme->txring;
00774         struct txdesc *txdesc = txring->desc;
00775         uint16_t len = iob_len(iob);
00776         unsigned long int mapping;
00777 
00778         txdesc += idx;
00779         mapping = virt_to_bus(iob->data);
00780         DBG2("TX buffer address: %p(%08lx+%x)\n",
00781                         iob->data, mapping, len);
00782         txdesc->dw[0] = 0;
00783         txdesc->dw[1] = 0;
00784         txdesc->dw[2] = 0;
00785         txdesc->dw[3] = 0;
00786         txdesc->desc1.datalen   = cpu_to_le16(len);
00787         txdesc->desc1.pktsize   = cpu_to_le16(len);
00788         txdesc->desc1.bufaddr   = cpu_to_le32(mapping);
00789         /*
00790          * Set OWN bit at final.
00791          * When kernel transmit faster than NIC.
00792          * And NIC trying to send this descriptor before we tell
00793          * it to start sending this TX queue.
00794          * Other fields are already filled correctly.
00795          */
00796         wmb();
00797         txdesc->desc1.flags = TXFLAG_OWN | TXFLAG_INT;
00798         /*
00799          * Set tx buffer info after telling NIC to send
00800          * For better tx_clean timing
00801          */
00802         wmb();
00803         txring->bufinf[idx] = iob;
00804 }
00805 
00806 /**
00807  * Transmit packet
00808  *
00809  * @v netdev    Network device
00810  * @v iobuf     I/O buffer
00811  * @ret rc      Return status code
00812  */
00813 static int
00814 jme_transmit(struct net_device *netdev, struct io_buffer *iobuf)
00815 {
00816         struct jme_adapter *jme = netdev->priv;
00817         int idx;
00818 
00819         idx = jme_alloc_txdesc(jme);
00820         if (idx < 0) {
00821                 /*
00822                  * Pause transmit queue somehow if possible.
00823                  */
00824                 DBG("TX ring full!\n");
00825                 return -EOVERFLOW;
00826         }
00827 
00828         jme_fill_tx_desc(jme, iobuf, idx);
00829 
00830         jwrite32(jme, JME_TXCS, jme->reg_txcs |
00831                                 TXCS_SELECT_QUEUE0 |
00832                                 TXCS_QUEUE0S |
00833                                 TXCS_ENABLE);
00834         DBG2("xmit: idx=%d\n", idx);
00835 
00836         return 0;
00837 }
00838 
00839 static int
00840 jme_check_link(struct net_device *netdev, int testonly)
00841 {
00842         struct jme_adapter *jme = netdev->priv;
00843         u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, gpreg1;
00844         int rc = 0;
00845 
00846         phylink = jread32(jme, JME_PHY_LINK);
00847 
00848         if (phylink & PHY_LINK_UP) {
00849                 /*
00850                  * Keep polling for speed/duplex resolve complete
00851                  */
00852                 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
00853                         --cnt) {
00854 
00855                         udelay(1);
00856                         phylink = jread32(jme, JME_PHY_LINK);
00857                 }
00858                 if (!cnt)
00859                         DBG("Waiting speed resolve timeout.\n");
00860 
00861                 if (jme->phylink == phylink) {
00862                         rc = 1;
00863                         goto out;
00864                 }
00865                 if (testonly)
00866                         goto out;
00867 
00868                 jme->phylink = phylink;
00869 
00870                 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
00871                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
00872                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
00873                 switch (phylink & PHY_LINK_SPEED_MASK) {
00874                 case PHY_LINK_SPEED_10M:
00875                         ghc |= GHC_SPEED_10M |
00876                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
00877                         break;
00878                 case PHY_LINK_SPEED_100M:
00879                         ghc |= GHC_SPEED_100M |
00880                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
00881                         break;
00882                 case PHY_LINK_SPEED_1000M:
00883                         ghc |= GHC_SPEED_1000M |
00884                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
00885                         break;
00886                 default:
00887                         break;
00888                 }
00889 
00890                 if (phylink & PHY_LINK_DUPLEX) {
00891                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
00892                         ghc |= GHC_DPX;
00893                 } else {
00894                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
00895                                                 TXMCS_BACKOFF |
00896                                                 TXMCS_CARRIERSENSE |
00897                                                 TXMCS_COLLISION);
00898                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
00899                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
00900                                 TXTRHD_TXREN |
00901                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
00902                 }
00903 
00904                 gpreg1 = GPREG1_DEFAULT;
00905                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
00906                         if (!(phylink & PHY_LINK_DUPLEX))
00907                                 gpreg1 |= GPREG1_HALFMODEPATCH;
00908                         switch (phylink & PHY_LINK_SPEED_MASK) {
00909                         case PHY_LINK_SPEED_10M:
00910                                 jme_set_phyfifoa(jme);
00911                                 gpreg1 |= GPREG1_RSSPATCH;
00912                                 break;
00913                         case PHY_LINK_SPEED_100M:
00914                                 jme_set_phyfifob(jme);
00915                                 gpreg1 |= GPREG1_RSSPATCH;
00916                                 break;
00917                         case PHY_LINK_SPEED_1000M:
00918                                 jme_set_phyfifoa(jme);
00919                                 break;
00920                         default:
00921                                 break;
00922                         }
00923                 }
00924 
00925                 jwrite32(jme, JME_GPREG1, gpreg1);
00926                 jwrite32(jme, JME_GHC, ghc);
00927                 jme->reg_ghc = ghc;
00928 
00929                 DBG("Link is up at %d Mbps, %s-Duplex, MDI%s.\n",
00930                     ((phylink & PHY_LINK_SPEED_MASK)
00931                              == PHY_LINK_SPEED_1000M) ? 1000 :
00932                     ((phylink & PHY_LINK_SPEED_MASK)
00933                              == PHY_LINK_SPEED_100M)  ? 100  : 10,
00934                     (phylink & PHY_LINK_DUPLEX) ? "Full" : "Half",
00935                     (phylink & PHY_LINK_MDI_STAT) ? "-X" : "");
00936                 netdev_link_up(netdev);
00937         } else {
00938                 if (testonly)
00939                         goto out;
00940 
00941                 DBG("Link is down.\n");
00942                 jme->phylink = 0;
00943                 netdev_link_down(netdev);
00944         }
00945 
00946 out:
00947         return rc;
00948 }
00949 
00950 static void
00951 jme_link_change(struct net_device *netdev)
00952 {
00953         struct jme_adapter *jme = netdev->priv;
00954 
00955         /*
00956          * Do nothing if the link status did not change.
00957          */
00958         if (jme_check_link(netdev, 1))
00959                 return;
00960 
00961         if (netdev_link_ok(netdev)) {
00962                 netdev_link_down(netdev);
00963                 jme_disable_rx_engine(jme);
00964                 jme_disable_tx_engine(jme);
00965                 jme_reset_ghc_speed(jme);
00966                 jme_reset_mac_processor(jme);
00967         }
00968 
00969         jme_check_link(netdev, 0);
00970         if (netdev_link_ok(netdev)) {
00971                 jme_init_rx_ring(jme);
00972                 jme_enable_rx_engine(jme);
00973                 jme_init_tx_ring(jme);
00974                 jme_enable_tx_engine(jme);
00975         }
00976 
00977         return;
00978 }
00979 
00980 static void
00981 jme_tx_clean(struct jme_adapter *jme)
00982 {
00983         struct jme_ring *txring = &jme->txring;
00984         struct txdesc *txdesc = txring->desc;
00985         struct io_buffer *txbi;
00986         struct net_device *netdev = jme->mii_if.dev;
00987         int i, cnt = 0, max, err, mask;
00988 
00989         max = jme->tx_ring_size - txring->nr_free;
00990         mask = jme->tx_ring_mask;
00991 
00992         for (i = txring->next_to_clean ; cnt < max ; ++cnt) {
00993 
00994                 txbi = txring->bufinf[i];
00995 
00996                 if (txbi && !(txdesc[i].descwb.flags & TXWBFLAG_OWN)) {
00997                         DBG2("TX clean address: %08lx(%08lx+%zx)\n",
00998                                         (unsigned long)txbi->data,
00999                                         virt_to_bus(txbi->data),
01000                                         iob_len(txbi));
01001                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
01002                         if (err)
01003                                 netdev_tx_complete_err(netdev, txbi, -EIO);
01004                         else
01005                                 netdev_tx_complete(netdev, txbi);
01006                         txring->bufinf[i] = NULL;
01007                 } else {
01008                         break;
01009                 }
01010 
01011                 i = (i + 1) & mask;
01012         }
01013 
01014         DBG2("txclean: next %d\n", i);
01015         txring->next_to_clean = i;
01016         txring->nr_free += cnt;
01017 }
01018 /**
01019  * Poll for received packets
01020  *
01021  * @v netdev    Network device
01022  */
01023 static void
01024 jme_poll(struct net_device *netdev)
01025 {
01026         struct jme_adapter *jme = netdev->priv;
01027         u32 intrstat;
01028 
01029         intrstat = jread32(jme, JME_IEVE);
01030 
01031         /*
01032          * Check if any actions needs to perform.
01033          */
01034         if ((intrstat & INTR_ENABLE) == 0)
01035                 return;
01036 
01037         /*
01038          * Check if the device still exist
01039          */
01040         if (intrstat == ~((typeof(intrstat))0))
01041                 return;
01042 
01043         DBG2("intrstat 0x%08x\n", intrstat);
01044         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
01045                 DBG2("Link changed\n");
01046                 jme_link_change(netdev);
01047 
01048                 /*
01049                  * Clear all interrupt status
01050                  */
01051                 jwrite32(jme, JME_IEVE, intrstat);
01052 
01053                 /*
01054                  * Link change event is critical
01055                  * all other events are ignored
01056                  */
01057                 return;
01058         }
01059 
01060         /*
01061          * Process transmission complete first to free more memory.
01062          */
01063         if (intrstat & INTR_TX0) {
01064                 DBG2("Packet transmit complete\n");
01065                 jme_tx_clean(jme);
01066                 jwrite32(jme, JME_IEVE, intrstat & INTR_TX0);
01067         }
01068 
01069         if (intrstat & (INTR_RX0 | INTR_RX0EMP)) {
01070                 DBG2("Packet received\n");
01071                 jme_process_receive(jme);
01072                 jwrite32(jme, JME_IEVE,
01073                         intrstat & (INTR_RX0 | INTR_RX0EMP));
01074                 if (intrstat & INTR_RX0EMP)
01075                         jme_restart_rx_engine(jme);
01076         }
01077 
01078         /*
01079          * Clean all other interrupt status
01080          */
01081         jwrite32(jme, JME_IEVE,
01082                 intrstat & ~(INTR_RX0 | INTR_RX0EMP | INTR_TX0));
01083 }
01084 
01085 /**
01086  * Enable/disable interrupts
01087  *
01088  * @v netdev    Network device
01089  * @v enable    Interrupts should be enabled
01090  */
01091 static void
01092 jme_irq(struct net_device *netdev, int enable)
01093 {
01094         struct jme_adapter *jme = netdev->priv;
01095 
01096         DBG("jme interrupts %s\n", (enable ? "enabled" : "disabled"));
01097         if (enable)
01098                 jme_start_irq(jme);
01099         else
01100                 jme_stop_irq(jme);
01101 }
01102 
01103 /** JME net device operations */
01104 static struct net_device_operations jme_operations = {
01105         .open           = jme_open,
01106         .close          = jme_close,
01107         .transmit       = jme_transmit,
01108         .poll           = jme_poll,
01109         .irq            = jme_irq,
01110 };
01111 
01112 static void
01113 jme_check_hw_ver(struct jme_adapter *jme)
01114 {
01115         u32 chipmode;
01116 
01117         chipmode = jread32(jme, JME_CHIPMODE);
01118 
01119         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
01120         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
01121 }
01122 
01123 static int
01124 jme_reload_eeprom(struct jme_adapter *jme)
01125 {
01126         u32 val;
01127         int i;
01128 
01129         val = jread32(jme, JME_SMBCSR);
01130 
01131         if (val & SMBCSR_EEPROMD) {
01132                 val |= SMBCSR_CNACK;
01133                 jwrite32(jme, JME_SMBCSR, val);
01134                 val |= SMBCSR_RELOAD;
01135                 jwrite32(jme, JME_SMBCSR, val);
01136                 mdelay(12);
01137 
01138                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
01139                         mdelay(1);
01140                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
01141                                 break;
01142                 }
01143 
01144                 if (i == 0) {
01145                         DBG("eeprom reload timeout\n");
01146                         return -EIO;
01147                 }
01148         }
01149 
01150         return 0;
01151 }
01152 
01153 static void
01154 jme_load_macaddr(struct net_device *netdev)
01155 {
01156         struct jme_adapter *jme = netdev_priv(netdev);
01157         unsigned char macaddr[6];
01158         u32 val;
01159 
01160         val = jread32(jme, JME_RXUMA_LO);
01161         macaddr[0] = (val >>  0) & 0xFF;
01162         macaddr[1] = (val >>  8) & 0xFF;
01163         macaddr[2] = (val >> 16) & 0xFF;
01164         macaddr[3] = (val >> 24) & 0xFF;
01165         val = jread32(jme, JME_RXUMA_HI);
01166         macaddr[4] = (val >>  0) & 0xFF;
01167         macaddr[5] = (val >>  8) & 0xFF;
01168         memcpy(netdev->hw_addr, macaddr, 6);
01169 }
01170 
01171 /**
01172  * Probe PCI device
01173  *
01174  * @v pci       PCI device
01175  * @v id        PCI ID
01176  * @ret rc      Return status code
01177  */
01178 static int
01179 jme_probe(struct pci_device *pci)
01180 {
01181         struct net_device *netdev;
01182         struct jme_adapter *jme;
01183         int rc;
01184         uint8_t mrrs;
01185 
01186         /* Allocate net device */
01187         netdev = alloc_etherdev(sizeof(*jme));
01188         if (!netdev)
01189                 return -ENOMEM;
01190         netdev_init(netdev, &jme_operations);
01191         jme = netdev->priv;
01192         pci_set_drvdata(pci, netdev);
01193         netdev->dev = &pci->dev;
01194         jme->regs = ioremap(pci->membase, JME_REGS_SIZE);
01195         if (!(jme->regs)) {
01196                 DBG("Mapping PCI resource region error.\n");
01197                 rc = -ENOMEM;
01198                 goto err_out;
01199         }
01200         jme->reg_ghc = 0;
01201         jme->reg_rxcs = RXCS_DEFAULT;
01202         jme->reg_rxmcs = RXMCS_DEFAULT;
01203         jme->phylink = 0;
01204         jme->pdev = pci;
01205         jme->mii_if.dev = netdev;
01206         jme->mii_if.phy_id = 1;
01207         jme->mii_if.mdio_read = jme_mdio_read;
01208         jme->mii_if.mdio_write = jme_mdio_write;
01209         jme->rx_ring_size = 1 << 4;
01210         jme->rx_ring_mask = jme->rx_ring_size - 1;
01211         jme->tx_ring_size = 1 << 4;
01212         jme->tx_ring_mask = jme->tx_ring_size - 1;
01213 
01214         /* Fix up PCI device */
01215         adjust_pci_device(pci);
01216 
01217         /*
01218          * Get Max Read Req Size from PCI Config Space
01219          */
01220         pci_read_config_byte(pci, PCI_DCSR_MRRS, &mrrs);
01221         mrrs &= PCI_DCSR_MRRS_MASK;
01222         switch (mrrs) {
01223         case MRRS_128B:
01224                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
01225                 break;
01226         case MRRS_256B:
01227                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
01228                 break;
01229         default:
01230                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
01231                 break;
01232         };
01233 
01234         /*
01235          * Get basic hardware info.
01236          */
01237         jme_check_hw_ver(jme);
01238         if (pci->device == PCI_DEVICE_ID_JMICRON_JMC250)
01239                 jme->mii_if.supports_gmii = 1;
01240         else
01241                 jme->mii_if.supports_gmii = 0;
01242 
01243         /*
01244          * Initialize PHY
01245          */
01246         jme_set_phyfifoa(jme);
01247         jme_phy_init(jme);
01248 
01249         /*
01250          * Bring down phy before interface is opened.
01251          */
01252         jme_phy_off(jme);
01253 
01254         /*
01255          * Reset MAC processor and reload EEPROM for MAC Address
01256          */
01257         jme_reset_mac_processor(jme);
01258         rc = jme_reload_eeprom(jme);
01259         if (rc) {
01260                 DBG("Reload eeprom for reading MAC Address error.\n");
01261                 goto err_unmap;
01262         }
01263         jme_load_macaddr(netdev);
01264 
01265         /* Register network device */
01266         if ((rc = register_netdev(netdev)) != 0) {
01267                 DBG("Register net_device error.\n");
01268                 goto err_unmap;
01269         }
01270 
01271         return 0;
01272 
01273 err_unmap:
01274         iounmap(jme->regs);
01275 err_out:
01276         netdev_nullify(netdev);
01277         netdev_put(netdev);
01278         return rc;
01279 }
01280 
01281 /**
01282  * Remove PCI device
01283  *
01284  * @v pci       PCI device
01285  */
01286 static void
01287 jme_remove(struct pci_device *pci)
01288 {
01289         struct net_device *netdev = pci_get_drvdata(pci);
01290         struct jme_adapter *jme = netdev->priv;
01291 
01292         iounmap(jme->regs);
01293         unregister_netdev(netdev);
01294         netdev_nullify(netdev);
01295         netdev_put(netdev);
01296 }
01297 
01298 static struct pci_device_id jm_nics[] = {
01299 PCI_ROM(0x197b, 0x0250, "jme",  "JMicron Gigabit Ethernet", 0),
01300 PCI_ROM(0x197b, 0x0260, "jmfe", "JMicron Fast Ethernet",    0),
01301 };
01302 
01303 struct pci_driver jme_driver __pci_driver = {
01304         .ids = jm_nics,
01305         .id_count = ( sizeof ( jm_nics ) / sizeof ( jm_nics[0] ) ),
01306         .probe = jme_probe,
01307         .remove = jme_remove,
01308 };
01309