23 #define AR_DescId 0xffff0000 24 #define AR_DescId_S 16 25 #define AR_CtrlStat 0x00004000 26 #define AR_CtrlStat_S 14 27 #define AR_TxRxDesc 0x00008000 28 #define AR_TxRxDesc_S 15 29 #define AR_TxQcuNum 0x00000f00 30 #define AR_TxQcuNum_S 8 32 #define AR_BufLen 0x0fff0000 33 #define AR_BufLen_S 16 35 #define AR_TxDescId 0xffff0000 36 #define AR_TxDescId_S 16 37 #define AR_TxPtrChkSum 0x0000ffff 39 #define AR_LowRxChain 0x00004000 41 #define AR_Not_Sounding 0x20000000 44 #define AR_PAPRDChainMask 0x00000e00 45 #define AR_PAPRDChainMask_S 9 47 #define MAP_ISR_S2_CST 6 48 #define MAP_ISR_S2_GTT 6 49 #define MAP_ISR_S2_TIM 3 50 #define MAP_ISR_S2_CABEND 0 51 #define MAP_ISR_S2_DTIMSYNC 7 52 #define MAP_ISR_S2_DTIM 7 53 #define MAP_ISR_S2_TSFOOR 4 54 #define MAP_ISR_S2_BB_WATCHDOG 6 56 #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
uint8_t size
Entry size (in 32-bit words)
void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, u32 ts_paddr_start, u8 size)
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, void *buf_addr)
void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, enum ath9k_rx_qtype qtype)
struct ar9003_rxs __attribute__((packed, aligned(4)))