iPXE
Data Structures | Macros | Enumerations | Functions | Variables
hw.h File Reference
#include <errno.h>
#include "mac.h"
#include "ani.h"
#include "eeprom.h"
#include "calib.h"
#include "reg.h"
#include "phy.h"
#include "../regd.h"

Go to the source code of this file.

Data Structures

struct  ath9k_hw_capabilities
 
struct  ath9k_ops_config
 
struct  ath9k_hw_cal_data
 
struct  ath9k_channel
 
struct  ath9k_beacon_state
 
struct  chan_centers
 
struct  ath9k_hw_version
 
struct  ath_gen_timer_configuration
 
struct  ath_gen_timer
 
struct  ath_gen_timer_table
 
struct  ath_hw_antcomb_conf
 
struct  ath_hw_radar_conf
 struct ath_hw_radar_conf - radar detection initialization parameters More...
 
struct  ath_hw_private_ops
 struct ath_hw_private_ops - callbacks used internally by hardware code More...
 
struct  ath_hw_ops
 struct ath_hw_ops - callbacks used by hardware code and driver code More...
 
struct  ath_nf_limits
 
struct  ath_hw
 
struct  ath_bus_ops
 

Macros

#define ERRFILE   ERRFILE_ath9k
 
#define ATHEROS_VENDOR_ID   0x168c
 
#define AR5416_DEVID_PCI   0x0023
 
#define AR5416_DEVID_PCIE   0x0024
 
#define AR9160_DEVID_PCI   0x0027
 
#define AR9280_DEVID_PCI   0x0029
 
#define AR9280_DEVID_PCIE   0x002a
 
#define AR9285_DEVID_PCIE   0x002b
 
#define AR2427_DEVID_PCIE   0x002c
 
#define AR9287_DEVID_PCI   0x002d
 
#define AR9287_DEVID_PCIE   0x002e
 
#define AR9300_DEVID_PCIE   0x0030
 
#define AR9300_DEVID_AR9340   0x0031
 
#define AR9300_DEVID_AR9485_PCIE   0x0032
 
#define AR5416_AR9100_DEVID   0x000b
 
#define AR_SUBVENDOR_ID_NOG   0x0e11
 
#define AR_SUBVENDOR_ID_NEW_A   0x7065
 
#define AR5416_MAGIC   0x19641014
 
#define AR9280_COEX2WIRE_SUBSYSID   0x309b
 
#define AT9285_COEX3WIRE_SA_SUBSYSID   0x30aa
 
#define AT9285_COEX3WIRE_DA_SUBSYSID   0x30ab
 
#define AR9300_NUM_BT_WEIGHTS   4
 
#define AR9300_NUM_WLAN_WEIGHTS   4
 
#define ATH_AMPDU_LIMIT_MAX   (64 * 1024 - 1)
 
#define ATH_DEFAULT_NOISE_FLOOR   -95
 
#define ATH9K_RSSI_BAD   -128
 
#define ATH9K_NUM_CHANNELS   38
 
#define REG_WRITE(_ah, _reg, _val)   (_ah)->reg_ops.write((_ah), (_val), (_reg))
 
#define REG_READ(_ah, _reg)   (_ah)->reg_ops.read((_ah), (_reg))
 
#define REG_READ_MULTI(_ah, _addr, _val, _cnt)   (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
 
#define REG_RMW(_ah, _reg, _set, _clr)   (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
 
#define ENABLE_REGWRITE_BUFFER(_ah)
 
#define REGWRITE_BUFFER_FLUSH(_ah)
 
#define SM(_v, _f)   (((_v) << _f##_S) & _f)
 
#define MS(_v, _f)   (((_v) & _f) >> _f##_S)
 
#define REG_RMW_FIELD(_a, _r, _f, _v)   REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
 
#define REG_READ_FIELD(_a, _r, _f)   (((REG_READ(_a, _r) & _f) >> _f##_S))
 
#define REG_SET_BIT(_a, _r, _f)   REG_RMW(_a, _r, (_f), 0)
 
#define REG_CLR_BIT(_a, _r, _f)   REG_RMW(_a, _r, 0, (_f))
 
#define DO_DELAY(x)
 
#define REG_WRITE_ARRAY(iniarray, column, regWr)   ath9k_hw_write_array(ah, iniarray, column, &(regWr))
 
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT   0
 
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED   1
 
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED   2
 
#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME   3
 
#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL   4
 
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED   5
 
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED   6
 
#define AR_GPIOD_MASK   0x00001FFF
 
#define AR_GPIO_BIT(_gpio)   (1 << (_gpio))
 
#define BASE_ACTIVATE_DELAY   100
 
#define RTC_PLL_SETTLE_DELAY   (AR_SREV_9340(ah) ? 1000 : 100)
 
#define COEF_SCALE_S   24
 
#define HT40_CHANNEL_CENTER_SHIFT   10
 
#define ATH9K_ANTENNA0_CHAINMASK   0x1
 
#define ATH9K_ANTENNA1_CHAINMASK   0x2
 
#define ATH9K_NUM_DMA_DEBUG_REGS   8
 
#define ATH9K_NUM_QUEUES   10
 
#define MAX_RATE_POWER   63
 
#define AH_WAIT_TIMEOUT   100000 /* (us) */
 
#define AH_TSF_WRITE_TIMEOUT   100 /* (us) */
 
#define AH_TIME_QUANTUM   10
 
#define AR_KEYTABLE_SIZE   128
 
#define POWER_UP_TIME   10000
 
#define SPUR_RSSI_THRESH   40
 
#define CAB_TIMEOUT_VAL   10
 
#define BEACON_TIMEOUT_VAL   10
 
#define MIN_BEACON_TIMEOUT_VAL   1
 
#define SLEEP_SLOP   3
 
#define INIT_CONFIG_STATUS   0x00000000
 
#define INIT_RSSI_THR   0x00000700
 
#define INIT_BCON_CNTRL_REG   0x00000000
 
#define TU_TO_USEC(_tu)   ((_tu) << 10)
 
#define ATH9K_HW_RX_HP_QDEPTH   16
 
#define ATH9K_HW_RX_LP_QDEPTH   128
 
#define PAPRD_GAIN_TABLE_ENTRIES   32
 
#define PAPRD_TABLE_SZ   24
 
#define SPUR_DISABLE   0
 
#define SPUR_ENABLE_IOCTL   1
 
#define SPUR_ENABLE_EEPROM   2
 
#define AR_SPUR_5413_1   1640
 
#define AR_SPUR_5413_2   1200
 
#define AR_NO_SPUR   0x8000
 
#define AR_BASE_FREQ_2GHZ   2300
 
#define AR_BASE_FREQ_5GHZ   4900
 
#define AR_SPUR_FEEQ_BOUND_HT40   19
 
#define AR_SPUR_FEEQ_BOUND_HT20   10
 
#define CHANNEL_CW_INT   0x00002
 
#define CHANNEL_CCK   0x00020
 
#define CHANNEL_OFDM   0x00040
 
#define CHANNEL_2GHZ   0x00080
 
#define CHANNEL_5GHZ   0x00100
 
#define CHANNEL_PASSIVE   0x00200
 
#define CHANNEL_DYN   0x00400
 
#define CHANNEL_HALF   0x04000
 
#define CHANNEL_QUARTER   0x08000
 
#define CHANNEL_HT20   0x10000
 
#define CHANNEL_HT40PLUS   0x20000
 
#define CHANNEL_HT40MINUS   0x40000
 
#define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)
 
#define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)
 
#define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)
 
#define CHANNEL_G_HT20   (CHANNEL_2GHZ|CHANNEL_HT20)
 
#define CHANNEL_A_HT20   (CHANNEL_5GHZ|CHANNEL_HT20)
 
#define CHANNEL_G_HT40PLUS   (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 
#define CHANNEL_G_HT40MINUS   (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 
#define CHANNEL_A_HT40PLUS   (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 
#define CHANNEL_A_HT40MINUS   (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 
#define CHANNEL_ALL
 
#define IS_CHAN_G(_c)
 
#define IS_CHAN_OFDM(_c)   (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 
#define IS_CHAN_5GHZ(_c)   (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 
#define IS_CHAN_2GHZ(_c)   (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 
#define IS_CHAN_HALF_RATE(_c)   (((_c)->channelFlags & CHANNEL_HALF) != 0)
 
#define IS_CHAN_QUARTER_RATE(_c)   (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
 
#define IS_CHAN_B(_c)   ((_c)->chanmode == CHANNEL_B)
 
#define IS_CHAN_HT20(_c)
 
#define IS_CHAN_HT40(_c)
 
#define IS_CHAN_HT(_c)   (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 
#define ATH9K_BEACON_PERIOD   0x0000ffff
 
#define ATH9K_TSFOOR_THRESHOLD   0x00004240 /* 16k us */
 
#define ATH_MAX_GEN_TIMER   16
 
#define AR_GENTMR_BIT(_index)   (1 << (_index))
 
#define debruijn32   0x077CB531U
 
#define AH_USE_EEPROM   0x1
 
#define AH_UNPLUGGED   0x2 /* The card has been physically removed. */
 
#define totalPowerMeasI   meas0.unsign
 
#define totalPowerMeasQ   meas1.unsign
 
#define totalIqCorrMeas   meas2.sign
 
#define totalAdcIOddPhase   meas0.unsign
 
#define totalAdcIEvenPhase   meas1.unsign
 
#define totalAdcQOddPhase   meas2.unsign
 
#define totalAdcQEvenPhase   meas3.unsign
 
#define totalAdcDcOffsetIOddPhase   meas0.sign
 
#define totalAdcDcOffsetIEvenPhase   meas1.sign
 
#define totalAdcDcOffsetQOddPhase   meas2.sign
 
#define totalAdcDcOffsetQEvenPhase   meas3.sign
 
#define ATH_PCIE_CAP_LINK_CTRL   0x70
 
#define ATH_PCIE_CAP_LINK_L0S   1
 
#define ATH_PCIE_CAP_LINK_L1   2
 
#define ATH9K_CLOCK_RATE_CCK   22
 
#define ATH9K_CLOCK_RATE_5GHZ_OFDM   40
 
#define ATH9K_CLOCK_RATE_2GHZ_OFDM   44
 
#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM   44
 

Enumerations

enum  ath_hw_txq_subtype { ATH_TXQ_AC_BE = 0 }
 
enum  ath_ini_subsys { ATH_INI_PRE = 0, ATH_INI_CORE, ATH_INI_POST, ATH_INI_NUM_SPLIT }
 
enum  ath9k_hw_caps {
  ATH9K_HW_CAP_HT = BIT(0), ATH9K_HW_CAP_RFSILENT = BIT(1), ATH9K_HW_CAP_CST = BIT(2), ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
  ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), ATH9K_HW_CAP_EDMA = BIT(6), ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), ATH9K_HW_CAP_LDPC = BIT(8),
  ATH9K_HW_CAP_FASTCLOCK = BIT(9), ATH9K_HW_CAP_SGI_20 = BIT(10), ATH9K_HW_CAP_PAPRD = BIT(11), ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
  ATH9K_HW_CAP_2GHZ = BIT(13), ATH9K_HW_CAP_5GHZ = BIT(14), ATH9K_HW_CAP_APM = BIT(15)
}
 
enum  ath9k_int {
  ATH9K_INT_RX = 0x00000001, ATH9K_INT_RXDESC = 0x00000002, ATH9K_INT_RXHP = 0x00000001, ATH9K_INT_RXLP = 0x00000002,
  ATH9K_INT_RXNOFRM = 0x00000008, ATH9K_INT_RXEOL = 0x00000010, ATH9K_INT_RXORN = 0x00000020, ATH9K_INT_TX = 0x00000040,
  ATH9K_INT_TXDESC = 0x00000080, ATH9K_INT_TIM_TIMER = 0x00000100, ATH9K_INT_BB_WATCHDOG = 0x00000400, ATH9K_INT_TXURN = 0x00000800,
  ATH9K_INT_MIB = 0x00001000, ATH9K_INT_RXPHY = 0x00004000, ATH9K_INT_RXKCM = 0x00008000, ATH9K_INT_SWBA = 0x00010000,
  ATH9K_INT_BMISS = 0x00040000, ATH9K_INT_BNR = 0x00100000, ATH9K_INT_TIM = 0x00200000, ATH9K_INT_DTIM = 0x00400000,
  ATH9K_INT_DTIMSYNC = 0x00800000, ATH9K_INT_GPIO = 0x01000000, ATH9K_INT_CABEND = 0x02000000, ATH9K_INT_TSFOOR = 0x04000000,
  ATH9K_INT_GENTIMER = 0x08000000, ATH9K_INT_CST = 0x10000000, ATH9K_INT_GTT = 0x20000000, ATH9K_INT_FATAL = 0x40000000,
  ATH9K_INT_GLOBAL = 0x80000000, ATH9K_INT_BMISC, ATH9K_INT_COMMON, ATH9K_INT_NOCARD = 0xffffffff
}
 
enum  ath9k_power_mode { ATH9K_PM_AWAKE = 0, ATH9K_PM_FULL_SLEEP, ATH9K_PM_NETWORK_SLEEP, ATH9K_PM_UNDEFINED }
 
enum  ath9k_tp_scale {
  ATH9K_TP_SCALE_MAX = 0, ATH9K_TP_SCALE_50, ATH9K_TP_SCALE_25, ATH9K_TP_SCALE_12,
  ATH9K_TP_SCALE_MIN
}
 
enum  ser_reg_mode { SER_REG_MODE_OFF = 0, SER_REG_MODE_ON = 1, SER_REG_MODE_AUTO = 2 }
 
enum  ath9k_rx_qtype { ATH9K_RX_QUEUE_HP, ATH9K_RX_QUEUE_LP, ATH9K_RX_QUEUE_MAX }
 
enum  { ATH9K_RESET_POWER_ON, ATH9K_RESET_WARM, ATH9K_RESET_COLD }
 

Functions

 FILE_LICENCE (BSD2)
 
static struct ath_commonath9k_hw_common (struct ath_hw *ah)
 
static struct ath_regulatoryath9k_hw_regulatory (struct ath_hw *ah)
 
static struct ath_hw_private_opsath9k_hw_private_ops (struct ath_hw *ah)
 
static struct ath_hw_opsath9k_hw_ops (struct ath_hw *ah)
 
static u8 get_streams (int mask)
 
const char * ath9k_hw_probe (u16 vendorid, u16 devid)
 
void ath9k_hw_deinit (struct ath_hw *ah)
 
int ath9k_hw_init (struct ath_hw *ah)
 
int ath9k_hw_reset (struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
 
int ath9k_hw_fill_cap_info (struct ath_hw *ah)
 
u32 ath9k_regd_get_ctl (struct ath_regulatory *reg, struct ath9k_channel *chan)
 
void ath9k_hw_cfg_gpio_input (struct ath_hw *ah, u32 gpio)
 
u32 ath9k_hw_gpio_get (struct ath_hw *ah, u32 gpio)
 
void ath9k_hw_cfg_output (struct ath_hw *ah, u32 gpio, u32 ah_signal_type)
 
void ath9k_hw_set_gpio (struct ath_hw *ah, u32 gpio, u32 val)
 
u32 ath9k_hw_getdefantenna (struct ath_hw *ah)
 
void ath9k_hw_setantenna (struct ath_hw *ah, u32 antenna)
 
int ath9k_hw_wait (struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 
void ath9k_hw_write_array (struct ath_hw *ah, struct ar5416IniArray *array, int column, unsigned int *writecnt)
 
u32 ath9k_hw_reverse_bits (u32 val, u32 n)
 
u16 ath9k_hw_computetxtime (struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, int shortPreamble)
 
void ath9k_hw_get_channel_centers (struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers)
 
u32 ath9k_hw_getrxfilter (struct ath_hw *ah)
 
void ath9k_hw_setrxfilter (struct ath_hw *ah, u32 bits)
 
int ath9k_hw_phy_disable (struct ath_hw *ah)
 
int ath9k_hw_disable (struct ath_hw *ah)
 
void ath9k_hw_set_txpowerlimit (struct ath_hw *ah, u32 limit, int test)
 
void ath9k_hw_setopmode (struct ath_hw *ah)
 
void ath9k_hw_setmcastfilter (struct ath_hw *ah, u32 filter0, u32 filter1)
 
void ath9k_hw_setbssidmask (struct ath_hw *ah)
 
void ath9k_hw_write_associd (struct ath_hw *ah)
 
void ath9k_hw_init_global_settings (struct ath_hw *ah)
 
u32 ar9003_get_pll_sqsum_dvc (struct ath_hw *ah)
 
void ath9k_hw_set11nmac2040 (struct ath_hw *ah)
 
int ath9k_hw_check_alive (struct ath_hw *ah)
 
int ath9k_hw_setpower (struct ath_hw *ah, enum ath9k_power_mode mode)
 
void ath9k_hw_name (struct ath_hw *ah, char *hw_name, size_t len)
 
void ath9k_hw_htc_resetinit (struct ath_hw *ah)
 
void ath9k_hw_get_delta_slope_vals (struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
 
void ar9002_hw_cck_chan14_spread (struct ath_hw *ah)
 
int ar9002_hw_rf_claim (struct ath_hw *ah)
 
void ar9002_hw_enable_async_fifo (struct ath_hw *ah)
 
void ar9002_hw_update_async_fifo (struct ath_hw *ah)
 
void ar9002_hw_enable_wep_aggregation (struct ath_hw *ah)
 
void ar9003_hw_disable_phy_restart (struct ath_hw *ah)
 
void ar5008_hw_attach_phy_ops (struct ath_hw *ah)
 
void ar9002_hw_attach_phy_ops (struct ath_hw *ah)
 
void ar9003_hw_attach_phy_ops (struct ath_hw *ah)
 
void ar9002_hw_attach_calib_ops (struct ath_hw *ah)
 
void ar9003_hw_attach_calib_ops (struct ath_hw *ah)
 
void ar9002_hw_attach_ops (struct ath_hw *ah)
 
void ar9003_hw_attach_ops (struct ath_hw *ah)
 
void ar9002_hw_load_ani_reg (struct ath_hw *ah, struct ath9k_channel *chan)
 
void ath9k_ani_reset (struct ath_hw *ah, int is_scanning)
 
void ath9k_hw_proc_mib_event (struct ath_hw *ah)
 
void ath9k_hw_ani_monitor (struct ath_hw *ah, struct ath9k_channel *chan)
 

Variables

int modparam_force_new_ani
 

Macro Definition Documentation

◆ ERRFILE

#define ERRFILE   ERRFILE_ath9k

Definition at line 38 of file hw.h.

◆ ATHEROS_VENDOR_ID

#define ATHEROS_VENDOR_ID   0x168c

Definition at line 40 of file hw.h.

◆ AR5416_DEVID_PCI

#define AR5416_DEVID_PCI   0x0023

Definition at line 42 of file hw.h.

◆ AR5416_DEVID_PCIE

#define AR5416_DEVID_PCIE   0x0024

Definition at line 43 of file hw.h.

◆ AR9160_DEVID_PCI

#define AR9160_DEVID_PCI   0x0027

Definition at line 44 of file hw.h.

◆ AR9280_DEVID_PCI

#define AR9280_DEVID_PCI   0x0029

Definition at line 45 of file hw.h.

◆ AR9280_DEVID_PCIE

#define AR9280_DEVID_PCIE   0x002a

Definition at line 46 of file hw.h.

◆ AR9285_DEVID_PCIE

#define AR9285_DEVID_PCIE   0x002b

Definition at line 47 of file hw.h.

◆ AR2427_DEVID_PCIE

#define AR2427_DEVID_PCIE   0x002c

Definition at line 48 of file hw.h.

◆ AR9287_DEVID_PCI

#define AR9287_DEVID_PCI   0x002d

Definition at line 49 of file hw.h.

◆ AR9287_DEVID_PCIE

#define AR9287_DEVID_PCIE   0x002e

Definition at line 50 of file hw.h.

◆ AR9300_DEVID_PCIE

#define AR9300_DEVID_PCIE   0x0030

Definition at line 51 of file hw.h.

◆ AR9300_DEVID_AR9340

#define AR9300_DEVID_AR9340   0x0031

Definition at line 52 of file hw.h.

◆ AR9300_DEVID_AR9485_PCIE

#define AR9300_DEVID_AR9485_PCIE   0x0032

Definition at line 53 of file hw.h.

◆ AR5416_AR9100_DEVID

#define AR5416_AR9100_DEVID   0x000b

Definition at line 55 of file hw.h.

◆ AR_SUBVENDOR_ID_NOG

#define AR_SUBVENDOR_ID_NOG   0x0e11

Definition at line 57 of file hw.h.

◆ AR_SUBVENDOR_ID_NEW_A

#define AR_SUBVENDOR_ID_NEW_A   0x7065

Definition at line 58 of file hw.h.

◆ AR5416_MAGIC

#define AR5416_MAGIC   0x19641014

Definition at line 59 of file hw.h.

◆ AR9280_COEX2WIRE_SUBSYSID

#define AR9280_COEX2WIRE_SUBSYSID   0x309b

Definition at line 61 of file hw.h.

◆ AT9285_COEX3WIRE_SA_SUBSYSID

#define AT9285_COEX3WIRE_SA_SUBSYSID   0x30aa

Definition at line 62 of file hw.h.

◆ AT9285_COEX3WIRE_DA_SUBSYSID

#define AT9285_COEX3WIRE_DA_SUBSYSID   0x30ab

Definition at line 63 of file hw.h.

◆ AR9300_NUM_BT_WEIGHTS

#define AR9300_NUM_BT_WEIGHTS   4

Definition at line 65 of file hw.h.

◆ AR9300_NUM_WLAN_WEIGHTS

#define AR9300_NUM_WLAN_WEIGHTS   4

Definition at line 66 of file hw.h.

◆ ATH_AMPDU_LIMIT_MAX

#define ATH_AMPDU_LIMIT_MAX   (64 * 1024 - 1)

Definition at line 68 of file hw.h.

◆ ATH_DEFAULT_NOISE_FLOOR

#define ATH_DEFAULT_NOISE_FLOOR   -95

Definition at line 70 of file hw.h.

◆ ATH9K_RSSI_BAD

#define ATH9K_RSSI_BAD   -128

Definition at line 72 of file hw.h.

◆ ATH9K_NUM_CHANNELS

#define ATH9K_NUM_CHANNELS   38

Definition at line 74 of file hw.h.

◆ REG_WRITE

#define REG_WRITE (   _ah,
  _reg,
  _val 
)    (_ah)->reg_ops.write((_ah), (_val), (_reg))

Definition at line 77 of file hw.h.

◆ REG_READ

#define REG_READ (   _ah,
  _reg 
)    (_ah)->reg_ops.read((_ah), (_reg))

Definition at line 80 of file hw.h.

◆ REG_READ_MULTI

#define REG_READ_MULTI (   _ah,
  _addr,
  _val,
  _cnt 
)    (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))

Definition at line 83 of file hw.h.

◆ REG_RMW

#define REG_RMW (   _ah,
  _reg,
  _set,
  _clr 
)    (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))

Definition at line 86 of file hw.h.

◆ ENABLE_REGWRITE_BUFFER

#define ENABLE_REGWRITE_BUFFER (   _ah)
Value:
do { \
if ((_ah)->reg_ops.enable_write_buffer) \
(_ah)->reg_ops.enable_write_buffer((_ah)); \
} while (0)

Definition at line 89 of file hw.h.

◆ REGWRITE_BUFFER_FLUSH

#define REGWRITE_BUFFER_FLUSH (   _ah)
Value:
do { \
if ((_ah)->reg_ops.write_flush) \
(_ah)->reg_ops.write_flush((_ah)); \
} while (0)

Definition at line 95 of file hw.h.

◆ SM

#define SM (   _v,
  _f 
)    (((_v) << _f##_S) & _f)

Definition at line 101 of file hw.h.

◆ MS

#define MS (   _v,
  _f 
)    (((_v) & _f) >> _f##_S)

Definition at line 102 of file hw.h.

◆ REG_RMW_FIELD

#define REG_RMW_FIELD (   _a,
  _r,
  _f,
  _v 
)    REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))

Definition at line 103 of file hw.h.

◆ REG_READ_FIELD

#define REG_READ_FIELD (   _a,
  _r,
  _f 
)    (((REG_READ(_a, _r) & _f) >> _f##_S))

Definition at line 105 of file hw.h.

◆ REG_SET_BIT

#define REG_SET_BIT (   _a,
  _r,
  _f 
)    REG_RMW(_a, _r, (_f), 0)

Definition at line 107 of file hw.h.

◆ REG_CLR_BIT

#define REG_CLR_BIT (   _a,
  _r,
  _f 
)    REG_RMW(_a, _r, 0, (_f))

Definition at line 109 of file hw.h.

◆ DO_DELAY

#define DO_DELAY (   x)
Value:
do { \
if (((++(x) % 64) == 0) && \
(ath9k_hw_common(ah)->bus_ops->ath_bus_type \
!= ATH_USB)) \
udelay(1); \
} while (0)
Definition: ath.h:127
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
uint8_t ah
Definition: registers.h:85

Definition at line 112 of file hw.h.

◆ REG_WRITE_ARRAY

#define REG_WRITE_ARRAY (   iniarray,
  column,
  regWr 
)    ath9k_hw_write_array(ah, iniarray, column, &(regWr))

Definition at line 119 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_OUTPUT

#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT   0

Definition at line 122 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED

#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED   1

Definition at line 123 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED

#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED   2

Definition at line 124 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_TX_FRAME

#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME   3

Definition at line 125 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL

#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL   4

Definition at line 126 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED

#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED   5

Definition at line 127 of file hw.h.

◆ AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED

#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED   6

Definition at line 128 of file hw.h.

◆ AR_GPIOD_MASK

#define AR_GPIOD_MASK   0x00001FFF

Definition at line 130 of file hw.h.

◆ AR_GPIO_BIT

#define AR_GPIO_BIT (   _gpio)    (1 << (_gpio))

Definition at line 131 of file hw.h.

◆ BASE_ACTIVATE_DELAY

#define BASE_ACTIVATE_DELAY   100

Definition at line 133 of file hw.h.

◆ RTC_PLL_SETTLE_DELAY

#define RTC_PLL_SETTLE_DELAY   (AR_SREV_9340(ah) ? 1000 : 100)

Definition at line 134 of file hw.h.

◆ COEF_SCALE_S

#define COEF_SCALE_S   24

Definition at line 135 of file hw.h.

◆ HT40_CHANNEL_CENTER_SHIFT

#define HT40_CHANNEL_CENTER_SHIFT   10

Definition at line 136 of file hw.h.

◆ ATH9K_ANTENNA0_CHAINMASK

#define ATH9K_ANTENNA0_CHAINMASK   0x1

Definition at line 138 of file hw.h.

◆ ATH9K_ANTENNA1_CHAINMASK

#define ATH9K_ANTENNA1_CHAINMASK   0x2

Definition at line 139 of file hw.h.

◆ ATH9K_NUM_DMA_DEBUG_REGS

#define ATH9K_NUM_DMA_DEBUG_REGS   8

Definition at line 141 of file hw.h.

◆ ATH9K_NUM_QUEUES

#define ATH9K_NUM_QUEUES   10

Definition at line 142 of file hw.h.

◆ MAX_RATE_POWER

#define MAX_RATE_POWER   63

Definition at line 144 of file hw.h.

◆ AH_WAIT_TIMEOUT

#define AH_WAIT_TIMEOUT   100000 /* (us) */

Definition at line 145 of file hw.h.

◆ AH_TSF_WRITE_TIMEOUT

#define AH_TSF_WRITE_TIMEOUT   100 /* (us) */

Definition at line 146 of file hw.h.

◆ AH_TIME_QUANTUM

#define AH_TIME_QUANTUM   10

Definition at line 147 of file hw.h.

◆ AR_KEYTABLE_SIZE

#define AR_KEYTABLE_SIZE   128

Definition at line 148 of file hw.h.

◆ POWER_UP_TIME

#define POWER_UP_TIME   10000

Definition at line 149 of file hw.h.

◆ SPUR_RSSI_THRESH

#define SPUR_RSSI_THRESH   40

Definition at line 150 of file hw.h.

◆ CAB_TIMEOUT_VAL

#define CAB_TIMEOUT_VAL   10

Definition at line 152 of file hw.h.

◆ BEACON_TIMEOUT_VAL

#define BEACON_TIMEOUT_VAL   10

Definition at line 153 of file hw.h.

◆ MIN_BEACON_TIMEOUT_VAL

#define MIN_BEACON_TIMEOUT_VAL   1

Definition at line 154 of file hw.h.

◆ SLEEP_SLOP

#define SLEEP_SLOP   3

Definition at line 155 of file hw.h.

◆ INIT_CONFIG_STATUS

#define INIT_CONFIG_STATUS   0x00000000

Definition at line 157 of file hw.h.

◆ INIT_RSSI_THR

#define INIT_RSSI_THR   0x00000700

Definition at line 158 of file hw.h.

◆ INIT_BCON_CNTRL_REG

#define INIT_BCON_CNTRL_REG   0x00000000

Definition at line 159 of file hw.h.

◆ TU_TO_USEC

#define TU_TO_USEC (   _tu)    ((_tu) << 10)

Definition at line 161 of file hw.h.

◆ ATH9K_HW_RX_HP_QDEPTH

#define ATH9K_HW_RX_HP_QDEPTH   16

Definition at line 163 of file hw.h.

◆ ATH9K_HW_RX_LP_QDEPTH

#define ATH9K_HW_RX_LP_QDEPTH   128

Definition at line 164 of file hw.h.

◆ PAPRD_GAIN_TABLE_ENTRIES

#define PAPRD_GAIN_TABLE_ENTRIES   32

Definition at line 166 of file hw.h.

◆ PAPRD_TABLE_SZ

#define PAPRD_TABLE_SZ   24

Definition at line 167 of file hw.h.

◆ SPUR_DISABLE

#define SPUR_DISABLE   0

Definition at line 235 of file hw.h.

◆ SPUR_ENABLE_IOCTL

#define SPUR_ENABLE_IOCTL   1

Definition at line 236 of file hw.h.

◆ SPUR_ENABLE_EEPROM

#define SPUR_ENABLE_EEPROM   2

Definition at line 237 of file hw.h.

◆ AR_SPUR_5413_1

#define AR_SPUR_5413_1   1640

Definition at line 238 of file hw.h.

◆ AR_SPUR_5413_2

#define AR_SPUR_5413_2   1200

Definition at line 239 of file hw.h.

◆ AR_NO_SPUR

#define AR_NO_SPUR   0x8000

Definition at line 240 of file hw.h.

◆ AR_BASE_FREQ_2GHZ

#define AR_BASE_FREQ_2GHZ   2300

Definition at line 241 of file hw.h.

◆ AR_BASE_FREQ_5GHZ

#define AR_BASE_FREQ_5GHZ   4900

Definition at line 242 of file hw.h.

◆ AR_SPUR_FEEQ_BOUND_HT40

#define AR_SPUR_FEEQ_BOUND_HT40   19

Definition at line 243 of file hw.h.

◆ AR_SPUR_FEEQ_BOUND_HT20

#define AR_SPUR_FEEQ_BOUND_HT20   10

Definition at line 244 of file hw.h.

◆ CHANNEL_CW_INT

#define CHANNEL_CW_INT   0x00002

Definition at line 301 of file hw.h.

◆ CHANNEL_CCK

#define CHANNEL_CCK   0x00020

Definition at line 302 of file hw.h.

◆ CHANNEL_OFDM

#define CHANNEL_OFDM   0x00040

Definition at line 303 of file hw.h.

◆ CHANNEL_2GHZ

#define CHANNEL_2GHZ   0x00080

Definition at line 304 of file hw.h.

◆ CHANNEL_5GHZ

#define CHANNEL_5GHZ   0x00100

Definition at line 305 of file hw.h.

◆ CHANNEL_PASSIVE

#define CHANNEL_PASSIVE   0x00200

Definition at line 306 of file hw.h.

◆ CHANNEL_DYN

#define CHANNEL_DYN   0x00400

Definition at line 307 of file hw.h.

◆ CHANNEL_HALF

#define CHANNEL_HALF   0x04000

Definition at line 308 of file hw.h.

◆ CHANNEL_QUARTER

#define CHANNEL_QUARTER   0x08000

Definition at line 309 of file hw.h.

◆ CHANNEL_HT20

#define CHANNEL_HT20   0x10000

Definition at line 310 of file hw.h.

◆ CHANNEL_HT40PLUS

#define CHANNEL_HT40PLUS   0x20000

Definition at line 311 of file hw.h.

◆ CHANNEL_HT40MINUS

#define CHANNEL_HT40MINUS   0x40000

Definition at line 312 of file hw.h.

◆ CHANNEL_A

#define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)

Definition at line 314 of file hw.h.

◆ CHANNEL_B

#define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)

Definition at line 315 of file hw.h.

◆ CHANNEL_G

#define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)

Definition at line 316 of file hw.h.

◆ CHANNEL_G_HT20

#define CHANNEL_G_HT20   (CHANNEL_2GHZ|CHANNEL_HT20)

Definition at line 317 of file hw.h.

◆ CHANNEL_A_HT20

#define CHANNEL_A_HT20   (CHANNEL_5GHZ|CHANNEL_HT20)

Definition at line 318 of file hw.h.

◆ CHANNEL_G_HT40PLUS

#define CHANNEL_G_HT40PLUS   (CHANNEL_2GHZ|CHANNEL_HT40PLUS)

Definition at line 319 of file hw.h.

◆ CHANNEL_G_HT40MINUS

#define CHANNEL_G_HT40MINUS   (CHANNEL_2GHZ|CHANNEL_HT40MINUS)

Definition at line 320 of file hw.h.

◆ CHANNEL_A_HT40PLUS

#define CHANNEL_A_HT40PLUS   (CHANNEL_5GHZ|CHANNEL_HT40PLUS)

Definition at line 321 of file hw.h.

◆ CHANNEL_A_HT40MINUS

#define CHANNEL_A_HT40MINUS   (CHANNEL_5GHZ|CHANNEL_HT40MINUS)

Definition at line 322 of file hw.h.

◆ CHANNEL_ALL

#define CHANNEL_ALL
Value:
CHANNEL_CCK| \
CHANNEL_2GHZ | \
CHANNEL_5GHZ | \
CHANNEL_HT20 | \
CHANNEL_HT40PLUS | \
CHANNEL_HT40MINUS)
#define CHANNEL_OFDM
Definition: hw.h:303

Definition at line 323 of file hw.h.

◆ IS_CHAN_G

#define IS_CHAN_G (   _c)
Value:
((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
(((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
u32 channelFlags
Definition: hw.h:350
#define CHANNEL_G
Definition: hw.h:316
#define CHANNEL_G_HT20
Definition: hw.h:317
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
#define CHANNEL_G_HT40MINUS
Definition: hw.h:320

Definition at line 355 of file hw.h.

◆ IS_CHAN_OFDM

#define IS_CHAN_OFDM (   _c)    (((_c)->channelFlags & CHANNEL_OFDM) != 0)

Definition at line 359 of file hw.h.

◆ IS_CHAN_5GHZ

#define IS_CHAN_5GHZ (   _c)    (((_c)->channelFlags & CHANNEL_5GHZ) != 0)

Definition at line 360 of file hw.h.

◆ IS_CHAN_2GHZ

#define IS_CHAN_2GHZ (   _c)    (((_c)->channelFlags & CHANNEL_2GHZ) != 0)

Definition at line 361 of file hw.h.

◆ IS_CHAN_HALF_RATE

#define IS_CHAN_HALF_RATE (   _c)    (((_c)->channelFlags & CHANNEL_HALF) != 0)

Definition at line 362 of file hw.h.

◆ IS_CHAN_QUARTER_RATE

#define IS_CHAN_QUARTER_RATE (   _c)    (((_c)->channelFlags & CHANNEL_QUARTER) != 0)

Definition at line 363 of file hw.h.

◆ IS_CHAN_A_FAST_CLOCK

#define IS_CHAN_A_FAST_CLOCK (   _ah,
  _c 
)
Value:
((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
u32 channelFlags
Definition: hw.h:350
#define CHANNEL_5GHZ
Definition: hw.h:305

Definition at line 364 of file hw.h.

◆ IS_CHAN_B

#define IS_CHAN_B (   _c)    ((_c)->chanmode == CHANNEL_B)

Definition at line 369 of file hw.h.

◆ IS_CHAN_HT20

#define IS_CHAN_HT20 (   _c)
Value:
(((_c)->chanmode == CHANNEL_A_HT20) || \
u32 chanmode
Definition: hw.h:351
#define CHANNEL_A_HT20
Definition: hw.h:318
#define CHANNEL_G_HT20
Definition: hw.h:317

Definition at line 370 of file hw.h.

◆ IS_CHAN_HT40

#define IS_CHAN_HT40 (   _c)
Value:
(((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
u32 chanmode
Definition: hw.h:351
#define CHANNEL_A_HT40MINUS
Definition: hw.h:322
#define CHANNEL_A_HT40PLUS
Definition: hw.h:321
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
#define CHANNEL_G_HT40MINUS
Definition: hw.h:320

Definition at line 372 of file hw.h.

◆ IS_CHAN_HT

#define IS_CHAN_HT (   _c)    (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))

Definition at line 376 of file hw.h.

◆ ATH9K_BEACON_PERIOD

#define ATH9K_BEACON_PERIOD   0x0000ffff

Definition at line 409 of file hw.h.

◆ ATH9K_TSFOOR_THRESHOLD

#define ATH9K_TSFOOR_THRESHOLD   0x00004240 /* 16k us */

Definition at line 410 of file hw.h.

◆ ATH_MAX_GEN_TIMER

#define ATH_MAX_GEN_TIMER   16

Definition at line 448 of file hw.h.

◆ AR_GENTMR_BIT

#define AR_GENTMR_BIT (   _index)    (1 << (_index))

Definition at line 450 of file hw.h.

◆ debruijn32

#define debruijn32   0x077CB531U

Definition at line 456 of file hw.h.

◆ AH_USE_EEPROM

#define AH_USE_EEPROM   0x1

Definition at line 653 of file hw.h.

◆ AH_UNPLUGGED

#define AH_UNPLUGGED   0x2 /* The card has been physically removed. */

Definition at line 654 of file hw.h.

◆ totalPowerMeasI

#define totalPowerMeasI   meas0.unsign

Definition at line 719 of file hw.h.

◆ totalPowerMeasQ

#define totalPowerMeasQ   meas1.unsign

Definition at line 720 of file hw.h.

◆ totalIqCorrMeas

#define totalIqCorrMeas   meas2.sign

Definition at line 721 of file hw.h.

◆ totalAdcIOddPhase

#define totalAdcIOddPhase   meas0.unsign

Definition at line 722 of file hw.h.

◆ totalAdcIEvenPhase

#define totalAdcIEvenPhase   meas1.unsign

Definition at line 723 of file hw.h.

◆ totalAdcQOddPhase

#define totalAdcQOddPhase   meas2.unsign

Definition at line 724 of file hw.h.

◆ totalAdcQEvenPhase

#define totalAdcQEvenPhase   meas3.unsign

Definition at line 725 of file hw.h.

◆ totalAdcDcOffsetIOddPhase

#define totalAdcDcOffsetIOddPhase   meas0.sign

Definition at line 726 of file hw.h.

◆ totalAdcDcOffsetIEvenPhase

#define totalAdcDcOffsetIEvenPhase   meas1.sign

Definition at line 727 of file hw.h.

◆ totalAdcDcOffsetQOddPhase

#define totalAdcDcOffsetQOddPhase   meas2.sign

Definition at line 728 of file hw.h.

◆ totalAdcDcOffsetQEvenPhase

#define totalAdcDcOffsetQEvenPhase   meas3.sign

Definition at line 729 of file hw.h.

◆ ATH_PCIE_CAP_LINK_CTRL

#define ATH_PCIE_CAP_LINK_CTRL   0x70

Definition at line 988 of file hw.h.

◆ ATH_PCIE_CAP_LINK_L0S

#define ATH_PCIE_CAP_LINK_L0S   1

Definition at line 989 of file hw.h.

◆ ATH_PCIE_CAP_LINK_L1

#define ATH_PCIE_CAP_LINK_L1   2

Definition at line 990 of file hw.h.

◆ ATH9K_CLOCK_RATE_CCK

#define ATH9K_CLOCK_RATE_CCK   22

Definition at line 992 of file hw.h.

◆ ATH9K_CLOCK_RATE_5GHZ_OFDM

#define ATH9K_CLOCK_RATE_5GHZ_OFDM   40

Definition at line 993 of file hw.h.

◆ ATH9K_CLOCK_RATE_2GHZ_OFDM

#define ATH9K_CLOCK_RATE_2GHZ_OFDM   44

Definition at line 994 of file hw.h.

◆ ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM

#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM   44

Definition at line 995 of file hw.h.

Enumeration Type Documentation

◆ ath_hw_txq_subtype

Enumerator
ATH_TXQ_AC_BE 

Definition at line 169 of file hw.h.

169  {
170  ATH_TXQ_AC_BE = 0,
171 };

◆ ath_ini_subsys

Enumerator
ATH_INI_PRE 
ATH_INI_CORE 
ATH_INI_POST 
ATH_INI_NUM_SPLIT 

Definition at line 173 of file hw.h.

173  {
174  ATH_INI_PRE = 0,
175  ATH_INI_CORE,
176  ATH_INI_POST,
178 };

◆ ath9k_hw_caps

Enumerator
ATH9K_HW_CAP_HT 
ATH9K_HW_CAP_RFSILENT 
ATH9K_HW_CAP_CST 
ATH9K_HW_CAP_AUTOSLEEP 
ATH9K_HW_CAP_4KB_SPLITTRANS 
ATH9K_HW_CAP_EDMA 
ATH9K_HW_CAP_RAC_SUPPORTED 
ATH9K_HW_CAP_LDPC 
ATH9K_HW_CAP_FASTCLOCK 
ATH9K_HW_CAP_SGI_20 
ATH9K_HW_CAP_PAPRD 
ATH9K_HW_CAP_ANT_DIV_COMB 
ATH9K_HW_CAP_2GHZ 
ATH9K_HW_CAP_5GHZ 
ATH9K_HW_CAP_APM 

Definition at line 180 of file hw.h.

◆ ath9k_int

enum ath9k_int
Enumerator
ATH9K_INT_RX 
ATH9K_INT_RXDESC 
ATH9K_INT_RXHP 
ATH9K_INT_RXLP 
ATH9K_INT_RXNOFRM 
ATH9K_INT_RXEOL 
ATH9K_INT_RXORN 
ATH9K_INT_TX 
ATH9K_INT_TXDESC 
ATH9K_INT_TIM_TIMER 
ATH9K_INT_BB_WATCHDOG 
ATH9K_INT_TXURN 
ATH9K_INT_MIB 
ATH9K_INT_RXPHY 
ATH9K_INT_RXKCM 
ATH9K_INT_SWBA 
ATH9K_INT_BMISS 
ATH9K_INT_BNR 
ATH9K_INT_TIM 
ATH9K_INT_DTIM 
ATH9K_INT_DTIMSYNC 
ATH9K_INT_GPIO 
ATH9K_INT_CABEND 
ATH9K_INT_TSFOOR 
ATH9K_INT_GENTIMER 
ATH9K_INT_CST 
ATH9K_INT_GTT 
ATH9K_INT_FATAL 
ATH9K_INT_GLOBAL 
ATH9K_INT_BMISC 
ATH9K_INT_COMMON 
ATH9K_INT_NOCARD 

Definition at line 251 of file hw.h.

251  {
252  ATH9K_INT_RX = 0x00000001,
253  ATH9K_INT_RXDESC = 0x00000002,
254  ATH9K_INT_RXHP = 0x00000001,
255  ATH9K_INT_RXLP = 0x00000002,
256  ATH9K_INT_RXNOFRM = 0x00000008,
257  ATH9K_INT_RXEOL = 0x00000010,
258  ATH9K_INT_RXORN = 0x00000020,
259  ATH9K_INT_TX = 0x00000040,
260  ATH9K_INT_TXDESC = 0x00000080,
261  ATH9K_INT_TIM_TIMER = 0x00000100,
262  ATH9K_INT_BB_WATCHDOG = 0x00000400,
263  ATH9K_INT_TXURN = 0x00000800,
264  ATH9K_INT_MIB = 0x00001000,
265  ATH9K_INT_RXPHY = 0x00004000,
266  ATH9K_INT_RXKCM = 0x00008000,
267  ATH9K_INT_SWBA = 0x00010000,
268  ATH9K_INT_BMISS = 0x00040000,
269  ATH9K_INT_BNR = 0x00100000,
270  ATH9K_INT_TIM = 0x00200000,
271  ATH9K_INT_DTIM = 0x00400000,
272  ATH9K_INT_DTIMSYNC = 0x00800000,
273  ATH9K_INT_GPIO = 0x01000000,
274  ATH9K_INT_CABEND = 0x02000000,
275  ATH9K_INT_TSFOOR = 0x04000000,
276  ATH9K_INT_GENTIMER = 0x08000000,
277  ATH9K_INT_CST = 0x10000000,
278  ATH9K_INT_GTT = 0x20000000,
279  ATH9K_INT_FATAL = 0x40000000,
280  ATH9K_INT_GLOBAL = 0x80000000,
292  ATH9K_INT_MIB |
298  ATH9K_INT_NOCARD = 0xffffffff
299 };

◆ ath9k_power_mode

Enumerator
ATH9K_PM_AWAKE 
ATH9K_PM_FULL_SLEEP 
ATH9K_PM_NETWORK_SLEEP 
ATH9K_PM_UNDEFINED 

Definition at line 378 of file hw.h.

◆ ath9k_tp_scale

Enumerator
ATH9K_TP_SCALE_MAX 
ATH9K_TP_SCALE_50 
ATH9K_TP_SCALE_25 
ATH9K_TP_SCALE_12 
ATH9K_TP_SCALE_MIN 

Definition at line 385 of file hw.h.

◆ ser_reg_mode

Enumerator
SER_REG_MODE_OFF 
SER_REG_MODE_ON 
SER_REG_MODE_AUTO 

Definition at line 393 of file hw.h.

393  {
394  SER_REG_MODE_OFF = 0,
395  SER_REG_MODE_ON = 1,
396  SER_REG_MODE_AUTO = 2,
397 };

◆ ath9k_rx_qtype

Enumerator
ATH9K_RX_QUEUE_HP 
ATH9K_RX_QUEUE_LP 
ATH9K_RX_QUEUE_MAX 

Definition at line 399 of file hw.h.

◆ anonymous enum

anonymous enum
Enumerator
ATH9K_RESET_POWER_ON 
ATH9K_RESET_WARM 
ATH9K_RESET_COLD 

Definition at line 427 of file hw.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( BSD2  )

◆ ath9k_hw_common()

static struct ath_common* ath9k_hw_common ( struct ath_hw ah)
inlinestatic

◆ ath9k_hw_regulatory()

static struct ath_regulatory* ath9k_hw_regulatory ( struct ath_hw ah)
inlinestatic

◆ ath9k_hw_private_ops()

static struct ath_hw_private_ops* ath9k_hw_private_ops ( struct ath_hw ah)
inlinestatic

◆ ath9k_hw_ops()

static struct ath_hw_ops* ath9k_hw_ops ( struct ath_hw ah)
inlinestatic

◆ get_streams()

static u8 get_streams ( int  mask)
inlinestatic

Definition at line 889 of file hw.h.

890 {
891  return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
892 }
#define BIT(nr)
Definition: ath.h:32

References BIT.

◆ ath9k_hw_probe()

const char* ath9k_hw_probe ( u16  vendorid,
u16  devid 
)

◆ ath9k_hw_deinit()

void ath9k_hw_deinit ( struct ath_hw ah)

Definition at line 850 of file ath9k_hw.c.

851 {
852  struct ath_common *common = ath9k_hw_common(ah);
853 
854  if (common->state < ATH_HW_INITIALIZED)
855  goto free_hw;
856 
858 
859 free_hw:
861 }
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
static void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
Definition: hw-ops.h:162
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
uint8_t ah
Definition: registers.h:85

References ah, ath9k_hw_common(), ath9k_hw_rf_free_ext_banks(), ath9k_hw_setpower(), ATH9K_PM_FULL_SLEEP, ATH_HW_INITIALIZED, and common.

Referenced by ath9k_deinit_softc(), and ath9k_init_softc().

◆ ath9k_hw_init()

int ath9k_hw_init ( struct ath_hw ah)

Definition at line 569 of file ath9k_hw.c.

570 {
571  int ret;
572  struct ath_common *common = ath9k_hw_common(ah);
573 
574  /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
575  switch (ah->hw_version.devid) {
576  case AR5416_DEVID_PCI:
577  case AR5416_DEVID_PCIE:
578  case AR5416_AR9100_DEVID:
579  case AR9160_DEVID_PCI:
580  case AR9280_DEVID_PCI:
581  case AR9280_DEVID_PCIE:
582  case AR9285_DEVID_PCIE:
583  case AR9287_DEVID_PCI:
584  case AR9287_DEVID_PCIE:
585  case AR2427_DEVID_PCIE:
586  case AR9300_DEVID_PCIE:
588  case AR9300_DEVID_AR9340:
589  break;
590  default:
591  if (common->bus_ops->ath_bus_type == ATH_USB)
592  break;
593  DBG("ath9k: Hardware device ID 0x%04x not supported\n",
594  ah->hw_version.devid);
595  return -EOPNOTSUPP;
596  }
597 
598  ret = __ath9k_hw_init(ah);
599  if (ret) {
600  DBG("ath9k: "
601  "Unable to initialize hardware; initialization status: %d\n",
602  ret);
603  return ret;
604  }
605 
606  return 0;
607 }
#define AR5416_AR9100_DEVID
Definition: hw.h:55
#define AR5416_DEVID_PCIE
Definition: hw.h:43
#define AR9300_DEVID_AR9485_PCIE
Definition: hw.h:53
Definition: ath.h:127
#define AR9300_DEVID_PCIE
Definition: hw.h:51
#define AR9287_DEVID_PCI
Definition: hw.h:49
static int __ath9k_hw_init(struct ath_hw *ah)
Definition: ath9k_hw.c:450
#define EOPNOTSUPP
Operation not supported on socket.
Definition: errno.h:604
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR9280_DEVID_PCIE
Definition: hw.h:46
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR9287_DEVID_PCIE
Definition: hw.h:50
#define AR9160_DEVID_PCI
Definition: hw.h:44
#define AR9280_DEVID_PCI
Definition: hw.h:45
uint8_t ah
Definition: registers.h:85
#define AR9300_DEVID_AR9340
Definition: hw.h:52
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR2427_DEVID_PCIE
Definition: hw.h:48
#define AR9285_DEVID_PCIE
Definition: hw.h:47
#define AR5416_DEVID_PCI
Definition: hw.h:42

References __ath9k_hw_init(), ah, AR2427_DEVID_PCIE, AR5416_AR9100_DEVID, AR5416_DEVID_PCI, AR5416_DEVID_PCIE, AR9160_DEVID_PCI, AR9280_DEVID_PCI, AR9280_DEVID_PCIE, AR9285_DEVID_PCIE, AR9287_DEVID_PCI, AR9287_DEVID_PCIE, AR9300_DEVID_AR9340, AR9300_DEVID_AR9485_PCIE, AR9300_DEVID_PCIE, ath9k_hw_common(), ATH_USB, common, DBG, and EOPNOTSUPP.

Referenced by ath9k_init_softc().

◆ ath9k_hw_reset()

int ath9k_hw_reset ( struct ath_hw ah,
struct ath9k_channel chan,
struct ath9k_hw_cal_data caldata,
int  bChannelChange 
)

Definition at line 1216 of file ath9k_hw.c.

1218 {
1219  struct ath_common *common = ath9k_hw_common(ah);
1220  u32 saveLedState;
1221  struct ath9k_channel *curchan = ah->curchan;
1222  u32 saveDefAntenna;
1223  u32 macStaId1;
1224  int i, r;
1225 
1226  ah->txchainmask = common->tx_chainmask;
1227  ah->rxchainmask = common->rx_chainmask;
1228 
1230  return -EIO;
1231 
1232  if (curchan && !ah->chip_fullsleep)
1233  ath9k_hw_getnf(ah, curchan);
1234 
1235  ah->caldata = caldata;
1236  if (caldata &&
1237  (chan->channel != caldata->channel ||
1238  (chan->channelFlags & ~CHANNEL_CW_INT) !=
1239  (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1240  /* Operating channel changed, reset channel calibration data */
1241  memset(caldata, 0, sizeof(*caldata));
1243  }
1244 
1245  if (bChannelChange &&
1246  (ah->chip_fullsleep != 1) &&
1247  (ah->curchan != NULL) &&
1248  (chan->channel != ah->curchan->channel) &&
1249  ((chan->channelFlags & CHANNEL_ALL) ==
1250  (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1251  (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1252 
1254  ath9k_hw_loadnf(ah, ah->curchan);
1256  if (AR_SREV_9271(ah))
1258  return 0;
1259  }
1260  }
1261 
1262  saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1263  if (saveDefAntenna == 0)
1264  saveDefAntenna = 1;
1265 
1267 
1268  saveLedState = REG_READ(ah, AR_CFG_LED) &
1271 
1273 
1274  ah->paprd_table_write_done = 0;
1275 
1276  /* Only required on the first reset */
1277  if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1278  REG_WRITE(ah,
1281  udelay(50);
1282  }
1283 
1284  if (!ath9k_hw_chip_reset(ah, chan)) {
1285  DBG("ath9k: Chip reset failed\n");
1286  return -EINVAL;
1287  }
1288 
1289  /* Only required on the first reset */
1290  if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1291  ah->htc_reset_init = 0;
1292  REG_WRITE(ah,
1295  udelay(50);
1296  }
1297 
1300 
1303 
1305  if (r)
1306  return r;
1307 
1308  /* Setup MFP options for CCMP */
1310  /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1311  * frames when constructing CCMP AAD. */
1313  0xc7ff);
1314  ah->sw_mgmt_crypto = 0;
1315  } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1316  /* Disable hardware crypto for management frames */
1321  ah->sw_mgmt_crypto = 1;
1322  } else
1323  ah->sw_mgmt_crypto = 1;
1324 
1325  if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1327 
1329  ah->eep_ops->set_board_values(ah, chan);
1330 
1332 
1335  | macStaId1
1337  | (ah->config.
1338  ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1339  | ah->sta_id1_defaults);
1341  REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1343  REG_WRITE(ah, AR_ISR, ~0);
1345 
1347 
1349 
1351  if (r)
1352  return r;
1353 
1355 
1357 
1358  for (i = 0; i < AR_NUM_DCU; i++)
1359  REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1360 
1362 
1363  ah->intr_txqs = 0;
1364  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1366 
1369 
1370  if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1371  ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1372 
1374 
1375  if (!AR_SREV_9300_20_OR_LATER(ah)) {
1378  }
1379 
1381 
1383 
1384  REG_WRITE(ah, AR_OBS, 8);
1385 
1386  if (ah->config.rx_intr_mitigation) {
1389  }
1390 
1391  if (ah->config.tx_intr_mitigation) {
1394  }
1395 
1397 
1398  if (!ath9k_hw_init_cal(ah, chan))
1399  return -EIO;
1400 
1402 
1404  REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1405 
1407 
1408  /*
1409  * For big endian systems turn on swapping for descriptors
1410  */
1411  if (AR_SREV_9100(ah)) {
1412  u32 mask;
1413  mask = REG_READ(ah, AR_CFG);
1414  if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1415  DBG2("ath9k: "
1416  "CFG Byte Swap Set 0x%x\n", mask);
1417  } else {
1418  mask =
1420  REG_WRITE(ah, AR_CFG, mask);
1421  DBG2("ath9k: "
1422  "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1423  }
1424  } else {
1425  if (common->bus_ops->ath_bus_type == ATH_USB) {
1426  /* Configure AR9271 target WLAN */
1427  if (AR_SREV_9271(ah))
1429  else
1431  }
1432 #if __BYTE_ORDER == __BIG_ENDIAN
1433  else if (AR_SREV_9340(ah))
1435  else
1437 #endif
1438  }
1439 
1442  }
1443 
1445 
1446  return 0;
1447 }
int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:283
#define AR_CFG_LED_MODE_SEL
Definition: reg.h:663
#define EINVAL
Invalid argument.
Definition: errno.h:428
u16 channel
Definition: hw.h:333
void ath9k_hw_write_associd(struct ath_hw *ah)
Definition: ath9k_hw.c:1964
#define AR_AES_MUTE_MASK1_FC_MGMT
Definition: reg.h:1858
#define AR_TIMT_LAST
Definition: reg.h:59
void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
#define INIT_RSSI_THR
Definition: hw.h:158
#define AR_AES_MUTE_MASK1
Definition: reg.h:1855
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define AR_CFG_LED_ASSOC_CTL
Definition: reg.h:677
#define AR_RIMT_LAST
Definition: reg.h:65
#define AR_TIMT
Definition: reg.h:58
#define INIT_CONFIG_STATUS
Definition: hw.h:157
#define CHANNEL_ALL
Definition: ath5k.h:647
void ath9k_hw_init_global_settings(struct ath_hw *ah)
Definition: ath9k_hw.c:812
static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
Definition: ath9k_hw.c:55
void ath9k_hw_start_nfcal(struct ath_hw *ah, int update)
Definition: ath9k_calib.c:206
#define IS_CHAN_OFDM(_c)
Definition: hw.h:359
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_STA_ID1_ACKCTS_6MB
Definition: reg.h:1443
void ath_hw_setbssidmask(struct ath_common *common)
ath_hw_set_bssid_mask - filter out bssids we listen
Definition: ath_hw.c:120
static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
Definition: hw-ops.h:212
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_OBS
Definition: reg.h:1094
#define AR_CFG_SWRB
Definition: reg.h:35
struct net80211_channel * chan
Definition: hw.h:347
#define AR_NUM_DCU
Definition: reg.h:483
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_RIMT
Definition: reg.h:64
#define AR_CFG_LED
Definition: reg.h:654
static u32 get_unaligned_le32(const void *p)
Definition: ath.h:87
Definition: ath.h:127
#define AR_STA_ID1
Definition: reg.h:1432
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
void ar9002_hw_update_async_fifo(struct ath_hw *ah)
#define AR_STA_ID1_BASE_RATE_11B
Definition: reg.h:1444
#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
Definition: reg.h:1831
#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
Definition: reg.h:1832
static int ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:258
#define AR_PCU_MISC_MODE2
Definition: reg.h:1830
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_calib.c:224
#define AR_CFG_SWRD
Definition: reg.h:34
#define AR_CFG_SCLK_32KHZ
Definition: reg.h:660
#define AR_STA_ID1_PRESERVE_SEQNUM
Definition: reg.h:1448
#define CHANNEL_CW_INT
Definition: ath5k.h:628
#define AR_SREV_9340(_ah)
Definition: reg.h:878
#define AR9271_RADIO_RF_RST
Definition: reg.h:1428
static void ath9k_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:180
static u16 get_unaligned_le16(const void *p)
Definition: ath.h:83
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah)
Definition: ath9k_hw.c:725
#define AR_SREV_9280(_ah)
Definition: reg.h:822
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1783
static void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:148
static void ath9k_hw_set_operating_mode(struct ath_hw *ah)
Definition: ath9k_hw.c:954
#define AR_STA_ID0
Definition: reg.h:1431
#define AR_STA_ID1_RTS_USE_DEF
Definition: reg.h:1442
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_TIMT_FIRST
Definition: reg.h:61
#define AR_CFG_SWRG
Definition: reg.h:36
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR_GPIO_JTAG_DISABLE
Definition: reg.h:1057
static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:192
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static void ath9k_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:217
static int ath9k_hw_channel_change(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:1128
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_CFG_SWTD
Definition: reg.h:32
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
static int ath9k_hw_rf_set_freq(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw-ops.h:142
static void ath9k_hw_restore_chainmask(struct ath_hw *ah)
Definition: hw-ops.h:233
#define AR_CFG_SWTB
Definition: reg.h:33
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_RSSI_THR
Definition: reg.h:1468
#define AR_GPIO_INPUT_EN_VAL
Definition: reg.h:1040
#define EIO
Input/output error.
Definition: errno.h:433
#define AR_RIMT_FIRST
Definition: reg.h:67
#define AR_SREV_9271(_ah)
Definition: reg.h:853
static void ath9k_hw_set_dma(struct ath_hw *ah)
Definition: ath9k_hw.c:885
u32 channelFlags
Definition: hw.h:334
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
#define AR_CFG_LED_BLINK_THRESH_SEL
Definition: reg.h:686
#define AR_ISR
Definition: reg.h:171
static int ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:1109
int ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_calib.c:346
uint8_t ah
Definition: registers.h:85
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
#define AR9271_GATE_MAC_CTL
Definition: reg.h:1429
#define AR_DEF_ANTENNA
Definition: reg.h:1534
static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
Definition: ath9k_hw.c:1175
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_CFG
Definition: reg.h:31
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define AR9271_RESET_POWER_DOWN_CONTROL
Definition: reg.h:1427
#define AR_DQCUMASK(_i)
Definition: reg.h:505
uint32_t u32
Definition: stdint.h:23
static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Definition: ath9k_hw.c:68
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define DBG2(...)
Definition: compiler.h:515
#define AR_CFG_LED_BLINK_SLOW
Definition: reg.h:683
void * memset(void *dest, int character, size_t len) __nonnull
void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:53
#define IS_CHAN_HT(_c)
Definition: hw.h:376
void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_calib.c:384

References ah, ar9002_hw_enable_async_fifo(), ar9002_hw_enable_wep_aggregation(), ar9002_hw_load_ani_reg(), ar9002_hw_update_async_fifo(), ar9003_hw_disable_phy_restart(), AR9271_GATE_MAC_CTL, AR9271_RADIO_RF_RST, AR9271_RESET_POWER_DOWN_CONTROL, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, AR_CFG, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, AR_CFG_LED_BLINK_SLOW, AR_CFG_LED_BLINK_THRESH_SEL, AR_CFG_LED_MODE_SEL, AR_CFG_SCLK_32KHZ, AR_CFG_SWRB, AR_CFG_SWRD, AR_CFG_SWRG, AR_CFG_SWTB, AR_CFG_SWTD, AR_DEF_ANTENNA, AR_DEVID_7010, AR_DQCUMASK, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE, AR_ISR, AR_NUM_DCU, AR_OBS, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE, AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT, AR_RIMT, AR_RIMT_FIRST, AR_RIMT_LAST, AR_RSSI_THR, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20_OR_LATER, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, AR_STA_ID0, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB, AR_STA_ID1_BASE_RATE_11B, AR_STA_ID1_PRESERVE_SEQNUM, AR_STA_ID1_RTS_USE_DEF, AR_TIMT, AR_TIMT_FIRST, AR_TIMT_LAST, ath9k_hw_ani_cache_ini_regs(), ath9k_hw_apply_gpio_override(), ATH9K_HW_CAP_RFSILENT, ath9k_hw_cfg_gpio_input(), ath9k_hw_channel_change(), ath9k_hw_chip_reset(), ath9k_hw_common(), ath9k_hw_getnf(), ath9k_hw_init_bb(), ath9k_hw_init_cal(), ath9k_hw_init_global_settings(), ath9k_hw_init_interrupt_masks(), ath9k_hw_loadnf(), ath9k_hw_mark_phy_inactive(), ath9k_hw_process_ini(), ath9k_hw_resettxqueue(), ath9k_hw_restore_chainmask(), ath9k_hw_rf_set_freq(), ath9k_hw_set_clockrate(), ath9k_hw_set_delta_slope(), ath9k_hw_set_dma(), ath9k_hw_set_operating_mode(), ath9k_hw_setpower(), ath9k_hw_spur_mitigate_freq(), ath9k_hw_start_nfcal(), ath9k_hw_write_associd(), ath9k_init_nfcal_hist_buffer(), ATH9K_NUM_TX_QUEUES, ATH9K_PM_AWAKE, ath_hw_setbssidmask(), ATH_USB, ath9k_channel::chan, ath9k_hw_cal_data::channel, CHANNEL_ALL, CHANNEL_CW_INT, ath9k_hw_cal_data::channelFlags, common, DBG, DBG2, EINVAL, EIO, ENABLE_REGWRITE_BUFFER, get_unaligned_le16(), get_unaligned_le32(), INIT_CONFIG_STATUS, INIT_RSSI_THR, IS_CHAN_HT, IS_CHAN_OFDM, memset(), NULL, r, REG_CLR_BIT, REG_READ, REG_RMW, REG_RMW_FIELD, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, and udelay().

Referenced by ath9k_start(), ath_radio_disable(), ath_reset(), and ath_set_channel().

◆ ath9k_hw_fill_cap_info()

int ath9k_hw_fill_cap_info ( struct ath_hw ah)

Definition at line 1569 of file ath9k_hw.c.

1570 {
1571  struct ath9k_hw_capabilities *pCap = &ah->caps;
1572  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1573  struct ath_common *common = ath9k_hw_common(ah);
1574 
1575  u16 eeval;
1576  u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1577 
1578  eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1579  regulatory->current_rd = eeval;
1580 
1581  eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1583  eeval |= AR9285_RDEXT_DEFAULT;
1584  regulatory->current_rd_ext = eeval;
1585 
1586  if (ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1587  if (regulatory->current_rd == 0x64 ||
1588  regulatory->current_rd == 0x65)
1589  regulatory->current_rd += 5;
1590  else if (regulatory->current_rd == 0x41)
1591  regulatory->current_rd = 0x43;
1592  DBG2("ath9k: "
1593  "regdomain mapped to 0x%x\n", regulatory->current_rd);
1594  }
1595 
1596  eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1597  if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1598  DBG("ath9k: "
1599  "no band has been marked as supported in EEPROM\n");
1600  return -EINVAL;
1601  }
1602 
1603  if (eeval & AR5416_OPFLAGS_11A)
1604  pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1605 
1606  if (eeval & AR5416_OPFLAGS_11G)
1607  pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1608 
1609  pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1610  /*
1611  * For AR9271 we will temporarilly uses the rx chainmax as read from
1612  * the EEPROM.
1613  */
1614  if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1615  !(eeval & AR5416_OPFLAGS_11A) &&
1616  !(AR_SREV_9271(ah)))
1617  /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1618  pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1619  else if (AR_SREV_9100(ah))
1620  pCap->rx_chainmask = 0x7;
1621  else
1622  /* Use rx_chainmask from EEPROM. */
1623  pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1624 
1625  ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1626 
1627  /* enable key search for every frame in an aggregate */
1629  ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1630 
1631  common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1632 
1633  pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1634 
1635  if (AR_SREV_9271(ah))
1637  else if (AR_DEVID_7010(ah))
1639  else if (AR_SREV_9285_12_OR_LATER(ah))
1641  else if (AR_SREV_9280_20_OR_LATER(ah))
1643  else
1644  pCap->num_gpio_pins = AR_NUM_GPIO;
1645 
1647  pCap->hw_caps |= ATH9K_HW_CAP_CST;
1649  } else {
1650  pCap->rts_aggr_limit = (8 * 1024);
1651  }
1652 
1653  ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1654  if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1655  ah->rfkill_gpio =
1656  MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1657  ah->rfkill_polarity =
1658  MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1659 
1660  pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1661  }
1662 
1663  pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1664 
1665  if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1667  else
1669 
1672  if (!AR_SREV_9485(ah))
1673  pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1674 
1677  pCap->rx_status_len = sizeof(struct ar9003_rxs);
1678  pCap->tx_desc_len = sizeof(struct ar9003_txc);
1679  pCap->txs_len = sizeof(struct ar9003_txs);
1680  if (!ah->config.paprd_disable &&
1681  ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1682  pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1683  } else {
1684  pCap->tx_desc_len = sizeof(struct ath_desc);
1685  if (AR_SREV_9280_20(ah) &&
1686  ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1688  ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1690  }
1691 
1694 
1696  ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1697 
1699  pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1700 
1701  if (AR_SREV_9285(ah))
1702  if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1703  ant_div_ctl1 =
1704  ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1705  if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1707  }
1709  if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1710  pCap->hw_caps |= ATH9K_HW_CAP_APM;
1711  }
1712 
1713 
1714  if (AR_SREV_9485(ah)) {
1715  ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1716  /*
1717  * enable the diversity-combining algorithm only when
1718  * both enable_lna_div and enable_fast_div are set
1719  * Table for Diversity
1720  * ant_div_alt_lnaconf bit 0-1
1721  * ant_div_main_lnaconf bit 2-3
1722  * ant_div_alt_gaintb bit 4
1723  * ant_div_main_gaintb bit 5
1724  * enable_ant_div_lnadiv bit 6
1725  * enable_ant_fast_div bit 7
1726  */
1727  if ((ant_div_ctl1 >> 0x6) == 0x3)
1729  }
1730 
1731  if (AR_SREV_9485_10(ah)) {
1732  pCap->pcie_lcr_extsync_en = 1;
1733  pCap->pcie_lcr_offset = 0x80;
1734  }
1735 
1736  tx_chainmask = pCap->tx_chainmask;
1737  rx_chainmask = pCap->rx_chainmask;
1738  while (tx_chainmask || rx_chainmask) {
1739  if (tx_chainmask & BIT(0))
1740  pCap->max_txchains++;
1741  if (rx_chainmask & BIT(0))
1742  pCap->max_rxchains++;
1743 
1744  tx_chainmask >>= 1;
1745  rx_chainmask >>= 1;
1746  }
1747 
1748  return 0;
1749 }
uint16_t u16
Definition: stdint.h:21
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR_PCU_MIC_NEW_LOC_ENA
Definition: reg.h:1642
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
struct ath_regulatory regulatory
Definition: ath.h:222
#define AR_NUM_GPIO
Definition: reg.h:986
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
u16 rts_aggr_limit
Definition: hw.h:200
#define MS(_v, _f)
Definition: hw.h:102
#define AR9285_NUM_GPIO
Definition: reg.h:988
#define AR_SREV_9485(_ah)
Definition: reg.h:867
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_SREV_9485_10(_ah)
Definition: reg.h:869
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define ATH9K_HW_RX_LP_QDEPTH
Definition: hw.h:164
int pcie_lcr_extsync_en
Definition: hw.h:212
#define EEP_RFSILENT_POLARITY
Definition: eeprom.h:118
Definition: mac.h:240
#define AR_SUBVENDOR_ID_NEW_A
Definition: hw.h:58
#define AR_ENT_OTP
Definition: reg.h:1107
#define AR_SREV_9280_20(_ah)
Definition: reg.h:826
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
u16 current_rd_ext
Definition: ath.h:142
#define EEP_RFSILENT_GPIO_SEL
Definition: eeprom.h:120
#define AR5416_EEP_MINOR_VER_16
Definition: eeprom.h:137
#define AR5416_OPFLAGS_11A
Definition: eeprom.h:123
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
u16 current_rd
Definition: ath.h:141
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1802
#define AR9271_NUM_GPIO
Definition: reg.h:990
#define AR_SREV_9280(_ah)
Definition: reg.h:822
u8 tx_chainmask
Definition: ath.h:209
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define EEP_RFSILENT_ENABLED
Definition: eeprom.h:116
struct ib_cm_common common
Definition: ib_mad.h:11
#define REG_READ(_ah, _reg)
Definition: hw.h:80
u8 rx_chainmask
Definition: ath.h:210
#define AR7010_NUM_GPIO
Definition: reg.h:992
#define AR5416_OPFLAGS_11G
Definition: eeprom.h:124
#define ATH9K_HW_RX_HP_QDEPTH
Definition: hw.h:163
#define BIT(nr)
Definition: ath.h:32
#define ATH_AMPDU_LIMIT_MAX
Definition: hw.h:68
#define AR928X_NUM_GPIO
Definition: reg.h:987
u16 pcie_lcr_offset
Definition: hw.h:211
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85
#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH
Definition: reg.h:1653
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
uint8_t u8
Definition: stdint.h:19
#define AR5416_DEVID_PCI
Definition: hw.h:42
#define AR9285_RDEXT_DEFAULT
Definition: eeprom.h:99
#define DBG2(...)
Definition: compiler.h:515
if(natsemi->flags &NATSEMI_64BIT) return 1

References ah, AR5416_DEVID_PCI, AR5416_EEP_MINOR_VER_16, AR5416_OPFLAGS_11A, AR5416_OPFLAGS_11G, AR7010_NUM_GPIO, AR9271_NUM_GPIO, AR9285_NUM_GPIO, AR9285_RDEXT_DEFAULT, AR928X_NUM_GPIO, AR_DEVID_7010, AR_ENT_OTP, AR_NUM_GPIO, AR_PCU_ALWAYS_PERFORM_KEYSEARCH, AR_PCU_MIC_NEW_LOC_ENA, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20, AR_SREV_9280_20_OR_LATER, AR_SREV_9285, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, AR_SREV_9300_20_OR_LATER, AR_SREV_9485, AR_SREV_9485_10, AR_SUBVENDOR_ID_NEW_A, ATH9K_HW_CAP_2GHZ, ATH9K_HW_CAP_4KB_SPLITTRANS, ATH9K_HW_CAP_5GHZ, ATH9K_HW_CAP_ANT_DIV_COMB, ATH9K_HW_CAP_APM, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_HW_CAP_CST, ATH9K_HW_CAP_FASTCLOCK, ATH9K_HW_CAP_HT, ATH9K_HW_CAP_LDPC, ATH9K_HW_CAP_PAPRD, ATH9K_HW_CAP_RAC_SUPPORTED, ATH9K_HW_CAP_RFSILENT, ATH9K_HW_CAP_SGI_20, ath9k_hw_common(), ath9k_hw_gpio_get(), ath9k_hw_regulatory(), ATH9K_HW_RX_HP_QDEPTH, ATH9K_HW_RX_LP_QDEPTH, ATH_AMPDU_LIMIT_MAX, ATH_CRYPT_CAP_CIPHER_AESCCM, BIT, common, ath_regulatory::current_rd, ath_regulatory::current_rd_ext, DBG, DBG2, EEP_ANT_DIV_CTL1, EEP_CHAIN_MASK_REDUCE, EEP_FSTCLK_5G, EEP_MINOR_REV, EEP_MODAL_VER, EEP_OP_MODE, EEP_PAPRD, EEP_REG_0, EEP_REG_1, EEP_RF_SILENT, EEP_RFSILENT_ENABLED, EEP_RFSILENT_GPIO_SEL, EEP_RFSILENT_POLARITY, EEP_RX_MASK, EEP_TX_MASK, EINVAL, ath9k_hw_capabilities::hw_caps, if(), ath9k_hw_capabilities::max_rxchains, ath9k_hw_capabilities::max_txchains, MS, ath9k_hw_capabilities::num_gpio_pins, ath9k_hw_capabilities::pcie_lcr_extsync_en, ath9k_hw_capabilities::pcie_lcr_offset, REG_READ, ath_common::regulatory, ath9k_hw_capabilities::rts_aggr_limit, ath9k_hw_capabilities::rx_chainmask, ath_common::rx_chainmask, ath9k_hw_capabilities::rx_hp_qdepth, ath9k_hw_capabilities::rx_lp_qdepth, ath9k_hw_capabilities::rx_status_len, ath9k_hw_capabilities::tx_chainmask, ath_common::tx_chainmask, ath9k_hw_capabilities::tx_desc_len, and ath9k_hw_capabilities::txs_len.

Referenced by __ath9k_hw_init().

◆ ath9k_regd_get_ctl()

u32 ath9k_regd_get_ctl ( struct ath_regulatory reg,
struct ath9k_channel chan 
)

Definition at line 867 of file ath9k_hw.c.

868 {
869  u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
870 
871  if (IS_CHAN_B(chan))
872  ctl |= CTL_11B;
873  else if (IS_CHAN_G(chan))
874  ctl |= CTL_11G;
875  else
876  ctl |= CTL_11A;
877 
878  return ctl;
879 }
#define IS_CHAN_B(_c)
Definition: ath5k.h:658
struct net80211_channel * chan
Definition: hw.h:347
static unsigned int unsigned int reg
Definition: intel.h:245
u8 band
The band with which this channel is associated.
Definition: net80211.h:388
#define CTL_11A
Definition: eeprom.h:70
#define CTL_11G
Definition: eeprom.h:72
#define IS_CHAN_G(_c)
Definition: hw.h:355
#define CTL_11B
Definition: eeprom.h:71
u32 ath_regd_get_band_ctl(struct ath_regulatory *reg, int band)
Definition: ath_regd.c:584
uint32_t u32
Definition: stdint.h:23

References ath_regd_get_band_ctl(), net80211_channel::band, ath9k_channel::chan, CTL_11A, CTL_11B, CTL_11G, IS_CHAN_B, IS_CHAN_G, and reg.

Referenced by ar5008_hw_process_ini(), ar9003_hw_process_ini(), ath9k_hw_channel_change(), and ath9k_hw_set_txpowerlimit().

◆ ath9k_hw_cfg_gpio_input()

void ath9k_hw_cfg_gpio_input ( struct ath_hw ah,
u32  gpio 
)

Definition at line 1783 of file ath9k_hw.c.

1784 {
1785  u32 gpio_shift;
1786 
1787  if (AR_DEVID_7010(ah)) {
1788  gpio_shift = gpio;
1790  (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
1791  (AR7010_GPIO_OE_MASK << gpio_shift));
1792  return;
1793  }
1794 
1795  gpio_shift = gpio << 1;
1796  REG_RMW(ah,
1798  (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
1799  (AR_GPIO_OE_OUT_DRV << gpio_shift));
1800 }
#define AR7010_GPIO_OE_AS_INPUT
Definition: reg.h:1023
#define AR7010_GPIO_OE_MASK
Definition: reg.h:1021
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_GPIO_OE_OUT_DRV_NO
Definition: reg.h:1015
#define AR_GPIO_OE_OUT_DRV
Definition: reg.h:1014
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85
#define AR_GPIO_OE_OUT
Definition: reg.h:1012
#define AR7010_GPIO_OE
Definition: reg.h:1020
uint32_t u32
Definition: stdint.h:23

References ah, AR7010_GPIO_OE, AR7010_GPIO_OE_AS_INPUT, AR7010_GPIO_OE_MASK, AR_DEVID_7010, AR_GPIO_OE_OUT, AR_GPIO_OE_OUT_DRV, AR_GPIO_OE_OUT_DRV_NO, gpio, and REG_RMW.

Referenced by ath9k_hw_reset(), and ath_radio_disable().

◆ ath9k_hw_gpio_get()

u32 ath9k_hw_gpio_get ( struct ath_hw ah,
u32  gpio 
)

Definition at line 1802 of file ath9k_hw.c.

1803 {
1804 #define MS_REG_READ(x, y) \
1805  (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
1806 
1807  if (gpio >= ah->caps.num_gpio_pins)
1808  return 0xffffffff;
1809 
1810  if (AR_DEVID_7010(ah)) {
1811  u32 val;
1813  return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
1814  } else if (AR_SREV_9300_20_OR_LATER(ah))
1816  AR_GPIO_BIT(gpio)) != 0;
1817  else if (AR_SREV_9271(ah))
1818  return MS_REG_READ(AR9271, gpio) != 0;
1819  else if (AR_SREV_9287_11_OR_LATER(ah))
1820  return MS_REG_READ(AR9287, gpio) != 0;
1821  else if (AR_SREV_9285_12_OR_LATER(ah))
1822  return MS_REG_READ(AR9285, gpio) != 0;
1823  else if (AR_SREV_9280_20_OR_LATER(ah))
1824  return MS_REG_READ(AR928X, gpio) != 0;
1825  else
1826  return MS_REG_READ(AR, gpio) != 0;
1827 }
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define MS(_v, _f)
Definition: hw.h:102
#define AR_GPIO_BIT(_gpio)
Definition: hw.h:131
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
#define AR_GPIO_IN
Definition: reg.h:1008
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define MS_REG_READ(x, y)
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define AR7010_GPIO_IN_VAL
Definition: reg.h:1005
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
#define AR9300_GPIO_IN_VAL
Definition: reg.h:1009
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define AR7010_GPIO_IN
Definition: reg.h:1024

References ah, AR7010_GPIO_IN, AR7010_GPIO_IN_VAL, AR9300_GPIO_IN_VAL, AR_DEVID_7010, AR_GPIO_BIT, AR_GPIO_IN, AR_SREV_9271, AR_SREV_9280_20_OR_LATER, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, AR_SREV_9300_20_OR_LATER, gpio, MS, MS_REG_READ, REG_READ, and val.

Referenced by ath9k_hw_fill_cap_info().

◆ ath9k_hw_cfg_output()

void ath9k_hw_cfg_output ( struct ath_hw ah,
u32  gpio,
u32  ah_signal_type 
)

Definition at line 1829 of file ath9k_hw.c.

1831 {
1832  u32 gpio_shift;
1833 
1834  if (AR_DEVID_7010(ah)) {
1835  gpio_shift = gpio;
1837  (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
1838  (AR7010_GPIO_OE_MASK << gpio_shift));
1839  return;
1840  }
1841 
1842  ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
1843  gpio_shift = 2 * gpio;
1844  REG_RMW(ah,
1846  (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
1847  (AR_GPIO_OE_OUT_DRV << gpio_shift));
1848 }
#define AR_GPIO_OE_OUT_DRV_ALL
Definition: reg.h:1018
#define AR7010_GPIO_OE_MASK
Definition: reg.h:1021
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_GPIO_OE_OUT_DRV
Definition: reg.h:1014
#define AR7010_GPIO_OE_AS_OUTPUT
Definition: reg.h:1022
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85
#define AR_GPIO_OE_OUT
Definition: reg.h:1012
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
Definition: ath9k_hw.c:1755
#define AR7010_GPIO_OE
Definition: reg.h:1020
uint32_t u32
Definition: stdint.h:23

References ah, AR7010_GPIO_OE, AR7010_GPIO_OE_AS_OUTPUT, AR7010_GPIO_OE_MASK, AR_DEVID_7010, AR_GPIO_OE_OUT, AR_GPIO_OE_OUT_DRV, AR_GPIO_OE_OUT_DRV_ALL, ath9k_hw_gpio_cfg_output_mux(), gpio, and REG_RMW.

Referenced by ath9k_hw_apply_gpio_override().

◆ ath9k_hw_set_gpio()

void ath9k_hw_set_gpio ( struct ath_hw ah,
u32  gpio,
u32  val 
)

Definition at line 1850 of file ath9k_hw.c.

1851 {
1852  if (AR_DEVID_7010(ah)) {
1853  val = val ? 0 : 1;
1854  REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
1855  AR_GPIO_BIT(gpio));
1856  return;
1857  }
1858 
1859  if (AR_SREV_9271(ah))
1860  val = ~val;
1861 
1862  REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
1863  AR_GPIO_BIT(gpio));
1864 }
#define AR_GPIO_BIT(_gpio)
Definition: hw.h:131
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
pseudo_bit_t gpio[0x00001]
Definition: arbel.h:30
#define AR_GPIO_IN_OUT
Definition: reg.h:994
#define AR7010_GPIO_OUT
Definition: reg.h:1025
void __asmcall int val
Definition: setjmp.h:28
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_DEVID_7010(_ah)
Definition: reg.h:891
uint8_t ah
Definition: registers.h:85

References ah, AR7010_GPIO_OUT, AR_DEVID_7010, AR_GPIO_BIT, AR_GPIO_IN_OUT, AR_SREV_9271, gpio, REG_RMW, and val.

Referenced by ath9k_hw_apply_gpio_override(), and ath_radio_disable().

◆ ath9k_hw_getdefantenna()

u32 ath9k_hw_getdefantenna ( struct ath_hw ah)

Definition at line 1866 of file ath9k_hw.c.

1867 {
1868  return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
1869 }
#define REG_READ(_ah, _reg)
Definition: hw.h:80
uint8_t ah
Definition: registers.h:85
#define AR_DEF_ANTENNA
Definition: reg.h:1534

References ah, AR_DEF_ANTENNA, and REG_READ.

Referenced by ath9k_init_misc().

◆ ath9k_hw_setantenna()

void ath9k_hw_setantenna ( struct ath_hw ah,
u32  antenna 
)

Definition at line 1871 of file ath9k_hw.c.

1872 {
1873  REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
1874 }
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_DEF_ANTENNA
Definition: reg.h:1534

References ah, AR_DEF_ANTENNA, and REG_WRITE.

Referenced by ath_setdefantenna().

◆ ath9k_hw_wait()

int ath9k_hw_wait ( struct ath_hw ah,
u32  reg,
u32  mask,
u32  val,
u32  timeout 
)

Definition at line 93 of file ath9k_hw.c.

94 {
95  unsigned int i;
96 
97  for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
98  if ((REG_READ(ah, reg) & mask) == val)
99  return 1;
100 
102  }
103 
104  DBG("ath9k: "
105  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
106  timeout, reg, REG_READ(ah, reg), mask, val);
107 
108  return 0;
109 }
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static unsigned int unsigned int reg
Definition: intel.h:245
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define AH_TIME_QUANTUM
Definition: hw.h:147
uint8_t ah
Definition: registers.h:85
void timeout(int)
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References ah, AH_TIME_QUANTUM, DBG, reg, REG_READ, timeout(), udelay(), and val.

Referenced by ar5008_hw_rfbus_req(), ar9002_hw_init_cal(), ar9003_hw_init_cal(), ar9003_hw_rfbus_req(), ar9003_hw_tx_iq_cal_run(), ar9285_hw_cl_cal(), ar9300_otp_read_word(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_setrxabort(), and ath_pci_eeprom_read().

◆ ath9k_hw_write_array()

void ath9k_hw_write_array ( struct ath_hw ah,
struct ar5416IniArray array,
int  column,
unsigned int *  writecnt 
)

Definition at line 111 of file ath9k_hw.c.

113 {
114  unsigned int r;
115 
117  for (r = 0; r < array->ia_rows; r++) {
118  REG_WRITE(ah, INI_RA(array, r, 0),
119  INI_RA(array, r, column));
120  DO_DELAY(*writecnt);
121  }
123 }
#define DO_DELAY(x)
Definition: hw.h:112
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
uint32_t array
Array number.
Definition: edd.h:30
uint32_t column[4]
Viewed as an array of four-byte columns.
Definition: aes.h:14
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:53

References ah, array, column, DO_DELAY, ENABLE_REGWRITE_BUFFER, INI_RA, r, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

◆ ath9k_hw_reverse_bits()

u32 ath9k_hw_reverse_bits ( u32  val,
u32  n 
)

Definition at line 125 of file ath9k_hw.c.

126 {
127  u32 retval;
128  unsigned int i;
129 
130  for (i = 0, retval = 0; i < n; i++) {
131  retval = (retval << 1) | (val & 1);
132  val >>= 1;
133  }
134  return retval;
135 }
void __asmcall int val
Definition: setjmp.h:28
unsigned long retval
Definition: xen.h:45
unsigned int n
Definition: entropy.h:159
uint32_t u32
Definition: stdint.h:23

References n, retval, and val.

Referenced by ar5008_hw_force_bias(), ar5008_hw_phy_modify_rx_buffer(), ar5008_hw_set_channel(), and ar9002_hw_get_radiorev().

◆ ath9k_hw_computetxtime()

u16 ath9k_hw_computetxtime ( struct ath_hw ah,
u8  phy,
int  kbps,
u32  frameLen,
u16  rateix,
int  shortPreamble 
)

Definition at line 137 of file ath9k_hw.c.

141 {
142  u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
143 
144  if (kbps == 0)
145  return 0;
146 
147  switch (phy) {
148  case CHANNEL_CCK:
149  phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
150  if (shortPreamble)
151  phyTime >>= 1;
152  numBits = frameLen << 3;
153  txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154  break;
155  case CHANNEL_OFDM:
156  if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
157  bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158  numBits = OFDM_PLCP_BITS + (frameLen << 3);
159  numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160  txTime = OFDM_SIFS_TIME_QUARTER
162  + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
163  } else if (ah->curchan &&
164  IS_CHAN_HALF_RATE(ah->curchan)) {
165  bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166  numBits = OFDM_PLCP_BITS + (frameLen << 3);
167  numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168  txTime = OFDM_SIFS_TIME_HALF +
170  + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171  } else {
172  bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173  numBits = OFDM_PLCP_BITS + (frameLen << 3);
174  numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176  + (numSymbols * OFDM_SYMBOL_TIME);
177  }
178  break;
179  default:
180  DBG("ath9k: "
181  "Unknown phy %d (rate ix %d)\n", phy, rateix);
182  txTime = 0;
183  break;
184  }
185 
186  return txTime;
187 }
#define OFDM_SYMBOL_TIME_QUARTER
Definition: mac.h:68
#define OFDM_SIFS_TIME_HALF
Definition: mac.h:60
#define OFDM_SIFS_TIME
Definition: mac.h:55
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:362
#define OFDM_SIFS_TIME_QUARTER
Definition: mac.h:65
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:363
#define CHANNEL_CCK
Definition: ath5k.h:630
#define OFDM_PREAMBLE_TIME
Definition: mac.h:56
#define OFDM_PREAMBLE_TIME_HALF
Definition: mac.h:61
#define CHANNEL_OFDM
Definition: ath5k.h:631
#define OFDM_PLCP_BITS
Definition: ath9k_xmit.c:26
#define CCK_PREAMBLE_BITS
Definition: mac.h:52
#define CCK_SIFS_TIME
Definition: mac.h:51
#define OFDM_PREAMBLE_TIME_QUARTER
Definition: mac.h:66
#define OFDM_SYMBOL_TIME_HALF
Definition: mac.h:63
#define CCK_PLCP_BITS
Definition: mac.h:53
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define OFDM_SYMBOL_TIME
Definition: mac.h:58
uint32_t u32
Definition: stdint.h:23
#define DIV_ROUND_UP(n, d)
Definition: ath.h:29

References ah, CCK_PLCP_BITS, CCK_PREAMBLE_BITS, CCK_SIFS_TIME, CHANNEL_CCK, CHANNEL_OFDM, DBG, DIV_ROUND_UP, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, OFDM_PLCP_BITS, OFDM_PREAMBLE_TIME, OFDM_PREAMBLE_TIME_HALF, OFDM_PREAMBLE_TIME_QUARTER, OFDM_SIFS_TIME, OFDM_SIFS_TIME_HALF, OFDM_SIFS_TIME_QUARTER, OFDM_SYMBOL_TIME, OFDM_SYMBOL_TIME_HALF, and OFDM_SYMBOL_TIME_QUARTER.

Referenced by ath_buf_set_rate().

◆ ath9k_hw_get_channel_centers()

void ath9k_hw_get_channel_centers ( struct ath_hw ah,
struct ath9k_channel chan,
struct chan_centers centers 
)

◆ ath9k_hw_getrxfilter()

u32 ath9k_hw_getrxfilter ( struct ath_hw ah)

Definition at line 1880 of file ath9k_hw.c.

1881 {
1883  u32 phybits = REG_READ(ah, AR_PHY_ERR);
1884 
1885  if (phybits & AR_PHY_ERR_RADAR)
1889 
1890  return bits;
1891 }
#define AR_PHY_ERR_RADAR
Definition: reg.h:1630
#define AR_PHY_ERR_CCK_TIMING
Definition: reg.h:1632
#define AR_RX_FILTER
Definition: reg.h:1490
#define AR_PHY_ERR
Definition: reg.h:1627
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static volatile void * bits
Definition: bitops.h:27
uint8_t ah
Definition: registers.h:85
#define AR_PHY_ERR_OFDM_TIMING
Definition: reg.h:1631
uint32_t u32
Definition: stdint.h:23

References ah, AR_PHY_ERR, AR_PHY_ERR_CCK_TIMING, AR_PHY_ERR_OFDM_TIMING, AR_PHY_ERR_RADAR, AR_RX_FILTER, ATH9K_RX_FILTER_PHYERR, ATH9K_RX_FILTER_PHYRADAR, bits, and REG_READ.

Referenced by ath9k_ani_reset_old(), and ath_calcrxfilter().

◆ ath9k_hw_setrxfilter()

void ath9k_hw_setrxfilter ( struct ath_hw ah,
u32  bits 
)

Definition at line 1893 of file ath9k_hw.c.

1894 {
1895  u32 phybits;
1896 
1898 
1900 
1901  phybits = 0;
1903  phybits |= AR_PHY_ERR_RADAR;
1906  REG_WRITE(ah, AR_PHY_ERR, phybits);
1907 
1908  if (phybits)
1910  else
1912 
1914 }
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_PHY_ERR_RADAR
Definition: reg.h:1630
#define AR_PHY_ERR_CCK_TIMING
Definition: reg.h:1632
#define AR_RX_FILTER
Definition: reg.h:1490
#define AR_RXCFG
Definition: reg.h:99
#define AR_RXCFG_ZLFDMA
Definition: reg.h:101
#define AR_PHY_ERR
Definition: reg.h:1627
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
static volatile void * bits
Definition: bitops.h:27
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_PHY_ERR_OFDM_TIMING
Definition: reg.h:1631
uint32_t u32
Definition: stdint.h:23
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89

References ah, AR_PHY_ERR, AR_PHY_ERR_CCK_TIMING, AR_PHY_ERR_OFDM_TIMING, AR_PHY_ERR_RADAR, AR_RX_FILTER, AR_RXCFG, AR_RXCFG_ZLFDMA, ATH9K_RX_FILTER_PHYERR, ATH9K_RX_FILTER_PHYRADAR, bits, ENABLE_REGWRITE_BUFFER, REG_CLR_BIT, REG_SET_BIT, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

Referenced by ath9k_ani_reset_old(), ath_opmode_init(), and ath_stoprecv().

◆ ath9k_hw_phy_disable()

int ath9k_hw_phy_disable ( struct ath_hw ah)

Definition at line 1916 of file ath9k_hw.c.

1917 {
1919  return 0;
1920 
1922  return 1;
1923 }
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:621
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
uint8_t ah
Definition: registers.h:85
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ATH9K_RESET_WARM, and NULL.

Referenced by ath9k_stop(), and ath_radio_disable().

◆ ath9k_hw_disable()

int ath9k_hw_disable ( struct ath_hw ah)

Definition at line 1925 of file ath9k_hw.c.

1926 {
1928  return 0;
1929 
1931  return 0;
1932 
1934  return 1;
1935 }
static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_hw.c:621
static int ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Definition: ath9k_hw.c:1088
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532
uint8_t ah
Definition: registers.h:85
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ath9k_hw_setpower(), ATH9K_PM_AWAKE, ATH9K_RESET_COLD, and NULL.

Referenced by ath9k_stop().

◆ ath9k_hw_set_txpowerlimit()

void ath9k_hw_set_txpowerlimit ( struct ath_hw ah,
u32  limit,
int  test 
)

Definition at line 1937 of file ath9k_hw.c.

1938 {
1939  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1940  struct ath9k_channel *chan = ah->curchan;
1941  struct net80211_channel *channel = chan->chan;
1942 
1943  regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
1944 
1945  ah->eep_ops->set_txpower(ah, chan,
1946  ath9k_regd_get_ctl(regulatory, chan),
1947  0,
1948  channel->maxpower * 2,
1950  (u32) regulatory->power_limit), test);
1951 }
#define min(x, y)
Definition: ath.h:34
struct net80211_channel * chan
Definition: hw.h:347
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:867
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
int16_t power_limit
Definition: ath.h:143
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
uint16_t limit
Limit.
Definition: librm.h:250
An 802.11 RF channel.
Definition: net80211.h:385
uint8_t ah
Definition: registers.h:85
static int test
Definition: epic100.c:73
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23

References ah, ath9k_hw_regulatory(), ath9k_regd_get_ctl(), ath9k_channel::chan, channel, limit, MAX_RATE_POWER, min, ath_regulatory::power_limit, and test.

Referenced by ath9k_cmn_update_txpow(), and ath9k_init_band_txpower().

◆ ath9k_hw_setopmode()

void ath9k_hw_setopmode ( struct ath_hw ah)

Definition at line 1953 of file ath9k_hw.c.

1954 {
1956 }
static void ath9k_hw_set_operating_mode(struct ath_hw *ah)
Definition: ath9k_hw.c:954
uint8_t ah
Definition: registers.h:85

References ah, and ath9k_hw_set_operating_mode().

Referenced by ath_opmode_init().

◆ ath9k_hw_setmcastfilter()

void ath9k_hw_setmcastfilter ( struct ath_hw ah,
u32  filter0,
u32  filter1 
)

Definition at line 1958 of file ath9k_hw.c.

1959 {
1960  REG_WRITE(ah, AR_MCAST_FIL0, filter0);
1961  REG_WRITE(ah, AR_MCAST_FIL1, filter1);
1962 }
#define AR_MCAST_FIL1
Definition: reg.h:1493
#define AR_MCAST_FIL0
Definition: reg.h:1492
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85

References ah, AR_MCAST_FIL0, AR_MCAST_FIL1, and REG_WRITE.

Referenced by ath_opmode_init().

◆ ath9k_hw_setbssidmask()

void ath9k_hw_setbssidmask ( struct ath_hw ah)

◆ ath9k_hw_write_associd()

void ath9k_hw_write_associd ( struct ath_hw ah)

Definition at line 1964 of file ath9k_hw.c.

1965 {
1966  struct ath_common *common = ath9k_hw_common(ah);
1967 
1969  REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
1970  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
1971 }
static u32 get_unaligned_le32(const void *p)
Definition: ath.h:87
static u16 get_unaligned_le16(const void *p)
Definition: ath.h:83
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define AR_BSS_ID1
Definition: reg.h:1453
struct ib_cm_common common
Definition: ib_mad.h:11
#define AR_BSS_ID1_AID_S
Definition: reg.h:1456
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_BSS_ID0
Definition: reg.h:1452

References ah, AR_BSS_ID0, AR_BSS_ID1, AR_BSS_ID1_AID_S, ath9k_hw_common(), common, get_unaligned_le16(), get_unaligned_le32(), and REG_WRITE.

Referenced by ath9k_bss_iter(), ath9k_config_bss(), and ath9k_hw_reset().

◆ ath9k_hw_init_global_settings()

void ath9k_hw_init_global_settings ( struct ath_hw ah)

Definition at line 812 of file ath9k_hw.c.

813 {
814  int acktimeout;
815  int slottime;
816  int sifstime;
817 
818  DBG2("ath9k: ah->misc_mode 0x%x\n",
819  ah->misc_mode);
820 
821  if (ah->misc_mode != 0)
822  REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
823 
824  if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_5GHZ)
825  sifstime = 16;
826  else
827  sifstime = 10;
828 
829  /* As defined by IEEE 802.11-2007 17.3.8.6 */
830  slottime = ah->slottime + 3 * ah->coverage_class;
831  acktimeout = slottime + sifstime;
832 
833  /*
834  * Workaround for early ACK timeouts, add an offset to match the
835  * initval's 64us ack timeout value.
836  * This was initially only meant to work around an issue with delayed
837  * BA frames in some implementations, but it has been found to fix ACK
838  * timeout issues in other cases as well.
839  */
840  if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_2GHZ)
841  acktimeout += 64 - sifstime - ah->slottime;
842 
843  ath9k_hw_setslottime(ah, ah->slottime);
844  ath9k_hw_set_ack_timeout(ah, acktimeout);
845  ath9k_hw_set_cts_timeout(ah, acktimeout);
846  if (ah->globaltxtimeout != (u32) -1)
847  ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
848 }
static int ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Definition: ath9k_hw.c:798
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Definition: ath9k_hw.c:784
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Definition: ath9k_hw.c:777
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45
static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
Definition: ath9k_hw.c:791
#define AR_PCU_MISC
Definition: reg.h:1640
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
Definition: net80211.h:47
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define DBG2(...)
Definition: compiler.h:515

References ah, AR_PCU_MISC, ath9k_hw_set_ack_timeout(), ath9k_hw_set_cts_timeout(), ath9k_hw_set_global_txtimeout(), ath9k_hw_setslottime(), DBG2, NET80211_BAND_2GHZ, NET80211_BAND_5GHZ, and REG_SET_BIT.

Referenced by ath9k_bss_info_changed(), and ath9k_hw_reset().

◆ ar9003_get_pll_sqsum_dvc()

u32 ar9003_get_pll_sqsum_dvc ( struct ath_hw ah)

Definition at line 609 of file ath9k_hw.c.

610 {
612  udelay(100);
614 
615  while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
616  udelay(100);
617 
618  return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
619 }
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define PLL4
Definition: reg.h:1191
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define PLL3_DO_MEAS_MASK
Definition: reg.h:1190
#define PLL3
Definition: reg.h:1189
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
uint8_t ah
Definition: registers.h:85
#define PLL4_MEAS_DONE
Definition: reg.h:1192
#define SQSUM_DVC_MASK
Definition: reg.h:1193

References ah, PLL3, PLL3_DO_MEAS_MASK, PLL4, PLL4_MEAS_DONE, REG_CLR_BIT, REG_READ, REG_SET_BIT, SQSUM_DVC_MASK, and udelay().

Referenced by ath_hw_pll_work().

◆ ath9k_hw_set11nmac2040()

void ath9k_hw_set11nmac2040 ( struct ath_hw ah)

Definition at line 1973 of file ath9k_hw.c.

1974 {
1975  u32 macmode;
1976 
1977  macmode = 0;
1978 
1979  REG_WRITE(ah, AR_2040_MODE, macmode);
1980 }
#define AR_2040_MODE
Definition: reg.h:1817
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR_2040_MODE, and REG_WRITE.

Referenced by ar5008_hw_set_channel_regs(), and ar9003_hw_set_channel_regs().

◆ ath9k_hw_check_alive()

int ath9k_hw_check_alive ( struct ath_hw ah)

Definition at line 1189 of file ath9k_hw.c.

1190 {
1191  int count = 50;
1192  u32 reg;
1193 
1195  return 1;
1196 
1197  do {
1199 
1200  if ((reg & 0x7E7FFFEF) == 0x00702400)
1201  continue;
1202 
1203  switch (reg & 0x7E000B00) {
1204  case 0x1E000000:
1205  case 0x52000B00:
1206  case 0x18000B00:
1207  continue;
1208  default:
1209  return 1;
1210  }
1211  } while (count-- > 0);
1212 
1213  return 0;
1214 }
#define AR_OBS_BUS_1
Definition: reg.h:1558
static unsigned int unsigned int reg
Definition: intel.h:245
#define AR_SREV_9285_12_OR_LATER(_ah)
Definition: reg.h:831
#define REG_READ(_ah, _reg)
Definition: hw.h:80
uint16_t count
Number of entries.
Definition: ena.h:22
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR_OBS_BUS_1, AR_SREV_9285_12_OR_LATER, count, reg, and REG_READ.

Referenced by ath_hw_check(), and ath_set_channel().

◆ ath9k_hw_setpower()

int ath9k_hw_setpower ( struct ath_hw ah,
enum ath9k_power_mode  mode 
)

Definition at line 1532 of file ath9k_hw.c.

1533 {
1534  int status = 1, setChip = 1;
1535  static const char *modes[] = {
1536  "AWAKE",
1537  "FULL-SLEEP",
1538  "NETWORK SLEEP",
1539  "UNDEFINED"
1540  };
1541 
1542  if (ah->power_mode == mode)
1543  return status;
1544 
1545  DBG2("ath9k: %s -> %s\n",
1546  modes[ah->power_mode], modes[mode]);
1547 
1548  switch (mode) {
1549  case ATH9K_PM_AWAKE:
1550  status = ath9k_hw_set_power_awake(ah, setChip);
1551  break;
1552  case ATH9K_PM_FULL_SLEEP:
1553  ath9k_set_power_sleep(ah, setChip);
1554  ah->chip_fullsleep = 1;
1555  break;
1556  default:
1557  DBG("ath9k: Unknown power mode %d\n", mode);
1558  return 0;
1559  }
1560  ah->power_mode = mode;
1561 
1562  return status;
1563 }
uint8_t status
Status.
Definition: ena.h:16
static int ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Definition: ath9k_hw.c:1482
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Definition: ath9k_hw.c:1457
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define DBG2(...)
Definition: compiler.h:515

References ah, ath9k_hw_set_power_awake(), ATH9K_PM_AWAKE, ATH9K_PM_FULL_SLEEP, ath9k_set_power_sleep(), DBG, DBG2, and status.

Referenced by __ath9k_hw_init(), ath9k_hw_chip_reset(), ath9k_hw_deinit(), ath9k_hw_disable(), ath9k_hw_reset(), and ath9k_setpower().

◆ ath9k_hw_name()

void ath9k_hw_name ( struct ath_hw ah,
char *  hw_name,
size_t  len 
)

Definition at line 2045 of file ath9k_hw.c.

2046 {
2047  int used;
2048 
2049  /* chipsets >= AR9280 are single-chip */
2051  used = snprintf(hw_name, len,
2052  "Atheros AR%s Rev:%x",
2053  ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2054  ah->hw_version.macRev);
2055  }
2056  else {
2057  used = snprintf(hw_name, len,
2058  "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2059  ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2060  ah->hw_version.macRev,
2061  ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2063  ah->hw_version.phyRev);
2064  }
2065 
2066  hw_name[used] = '\0';
2067 }
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
static const char * ath9k_hw_mac_bb_name(u32 mac_bb_version)
Definition: ath9k_hw.c:2015
static const char * ath9k_hw_rf_name(u16 rf_version)
Definition: ath9k_hw.c:2032
uint32_t len
Length.
Definition: ena.h:14
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
uint8_t ah
Definition: registers.h:85
#define AR_RADIO_SREV_MAJOR
Definition: reg.h:895

References ah, AR_RADIO_SREV_MAJOR, AR_SREV_9280_20_OR_LATER, ath9k_hw_mac_bb_name(), ath9k_hw_rf_name(), len, and snprintf().

Referenced by ath_pci_probe().

◆ ath9k_hw_htc_resetinit()

void ath9k_hw_htc_resetinit ( struct ath_hw ah)

◆ ath9k_hw_get_delta_slope_vals()

void ath9k_hw_get_delta_slope_vals ( struct ath_hw ah,
u32  coef_scaled,
u32 coef_mantissa,
u32 coef_exponent 
)

◆ ar9002_hw_cck_chan14_spread()

void ar9002_hw_cck_chan14_spread ( struct ath_hw ah)

Definition at line 188 of file ath9k_ar9002_hw.c.

189 {
191  INIT_INI_ARRAY(&ah->iniCckfirNormal,
194  2);
195  INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
198  2);
199  }
200 }
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
static __unused const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2]
#define INIT_INI_ARRAY(iniarray, array, rows, columns)
Definition: calib.h:39
uint8_t ah
Definition: registers.h:85
static __unused const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2]

References ah, ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, ar9287Common_normal_cck_fir_coeff_9287_1_1, AR_SREV_9287_11_OR_LATER, ARRAY_SIZE, and INIT_INI_ARRAY.

Referenced by __ath9k_hw_init().

◆ ar9002_hw_rf_claim()

int ar9002_hw_rf_claim ( struct ath_hw ah)

Definition at line 464 of file ath9k_ar9002_hw.c.

465 {
466  u32 val;
467 
468  REG_WRITE(ah, AR_PHY(0), 0x00000007);
469 
471  switch (val & AR_RADIO_SREV_MAJOR) {
472  case 0:
474  break;
479  break;
480  default:
481  DBG("ath9k: "
482  "Radio Chip Rev 0x%02X not supported\n",
484  return -EOPNOTSUPP;
485  }
486 
487  ah->hw_version.analog5GhzRev = val;
488 
489  return 0;
490 }
#define AR_PHY(_n)
Definition: phy.h:27
#define AR_RAD5133_SREV_MAJOR
Definition: reg.h:896
#define AR_RAD5122_SREV_MAJOR
Definition: reg.h:898
static int ar9002_hw_get_radiorev(struct ath_hw *ah)
#define AR_RAD2122_SREV_MAJOR
Definition: reg.h:899
#define AR_RAD2133_SREV_MAJOR
Definition: reg.h:897
#define EOPNOTSUPP
Operation not supported on socket.
Definition: errno.h:604
void __asmcall int val
Definition: setjmp.h:28
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_RADIO_SREV_MAJOR
Definition: reg.h:895
uint32_t u32
Definition: stdint.h:23

References ah, ar9002_hw_get_radiorev(), AR_PHY, AR_RAD2122_SREV_MAJOR, AR_RAD2133_SREV_MAJOR, AR_RAD5122_SREV_MAJOR, AR_RAD5133_SREV_MAJOR, AR_RADIO_SREV_MAJOR, DBG, EOPNOTSUPP, REG_WRITE, and val.

Referenced by ath9k_hw_post_init().

◆ ar9002_hw_enable_async_fifo()

void ar9002_hw_enable_async_fifo ( struct ath_hw ah)

Definition at line 492 of file ath9k_ar9002_hw.c.

493 {
502  }
503 }
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_PHY_MODE_ASYNCFIFO
Definition: ar9002_phy.h:397
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_MAC_PCU_ASYNC_FIFO_REG3
Definition: reg.h:1845
#define AR_SREV_9287_13_OR_LATER(_ah)
Definition: reg.h:848
uint8_t ah
Definition: registers.h:85
#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
Definition: reg.h:1846
#define AR_PHY_MODE
Definition: ar9002_phy.h:396
#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
Definition: reg.h:1847

References ah, AR_MAC_PCU_ASYNC_FIFO_REG3, AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL, AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO, AR_SREV_9287_13_OR_LATER, REG_CLR_BIT, and REG_SET_BIT.

Referenced by ath9k_hw_reset().

◆ ar9002_hw_update_async_fifo()

void ar9002_hw_update_async_fifo ( struct ath_hw ah)

Definition at line 512 of file ath9k_ar9002_hw.c.

513 {
521 
524 
529  }
530 }
#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR
Definition: reg.h:626
#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR
Definition: reg.h:1466
#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR
Definition: reg.h:621
#define AR_D_GBL_IFS_SIFS
Definition: reg.h:603
#define AR_AHB_MODE
Definition: reg.h:901
#define AR_AHB_CUSTOM_BURST_EN
Definition: reg.h:910
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_TIME_OUT
Definition: reg.h:1461
#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR
Definition: reg.h:605
#define AR_USEC
Definition: reg.h:1476
#define AR_D_GBL_IFS_EIFS
Definition: reg.h:623
#define AR_MAC_PCU_LOGIC_ANALYZER
Definition: reg.h:1813
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_USEC_ASYNC_FIFO_DUR
Definition: reg.h:1482
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_SREV_9287_13_OR_LATER(_ah)
Definition: reg.h:848
uint8_t ah
Definition: registers.h:85
#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
Definition: reg.h:1814
#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
Definition: reg.h:912
#define AR_D_GBL_IFS_SLOT
Definition: reg.h:618

References ah, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL, AR_AHB_CUSTOM_BURST_EN, AR_AHB_MODE, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768, AR_SREV_9287_13_OR_LATER, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR, AR_USEC, AR_USEC_ASYNC_FIFO_DUR, REG_RMW_FIELD, REG_SET_BIT, and REG_WRITE.

Referenced by ath9k_hw_reset().

◆ ar9002_hw_enable_wep_aggregation()

void ar9002_hw_enable_wep_aggregation ( struct ath_hw ah)

Definition at line 536 of file ath9k_ar9002_hw.c.

537 {
541  }
542 }
#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP
Definition: reg.h:1840
#define AR_PCU_MISC_MODE2
Definition: reg.h:1830
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
#define AR_SREV_9287_13_OR_LATER(_ah)
Definition: reg.h:848
uint8_t ah
Definition: registers.h:85

References ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP, AR_SREV_9287_13_OR_LATER, and REG_SET_BIT.

Referenced by ath9k_hw_reset().

◆ ar9003_hw_disable_phy_restart()

void ar9003_hw_disable_phy_restart ( struct ath_hw ah)

Definition at line 1270 of file ath9k_ar9003_phy.c.

1271 {
1272  u32 val;
1273 
1275  val &= ~AR_PHY_RESTART_ENA;
1276 
1278 }
#define AR_PHY_RESTART
Definition: ar9002_phy.h:264
#define AR_PHY_RESTART_ENA
Definition: ar9003_phy.h:409
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, AR_PHY_RESTART, AR_PHY_RESTART_ENA, REG_READ, REG_WRITE, and val.

Referenced by ath9k_hw_reset().

◆ ar5008_hw_attach_phy_ops()

void ar5008_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 1618 of file ath9k_ar5008_phy.c.

1619 {
1620  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1621  static const u32 ar5416_cca_regs[6] = {
1622  AR_PHY_CCA,
1628  };
1629 
1630  priv_ops->rf_set_freq = ar5008_hw_set_channel;
1632 
1635  priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1637  priv_ops->init_bb = ar5008_hw_init_bb;
1638  priv_ops->process_ini = ar5008_hw_process_ini;
1639  priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1642  priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1643  priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1645  priv_ops->set_diversity = ar5008_set_diversity;
1646  priv_ops->do_getnf = ar5008_hw_do_getnf;
1648 
1649  if (modparam_force_new_ani) {
1652  } else
1654 
1655  if (AR_SREV_9100(ah))
1657  else if (AR_SREV_9160_10_OR_LATER(ah))
1659  else
1661 
1664  memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1665 }
void(* set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:577
static int ar5008_hw_ani_control_new(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
#define AR_PHY_CH1_CCA
Definition: ar9002_phy.h:569
void(* init_bb)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:571
static int ar5008_hw_rfbus_req(struct ath_hw *ah)
void(* rf_free_ext_banks)(struct ath_hw *ah)
Definition: hw.h:566
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
int(* rf_alloc_ext_banks)(struct ath_hw *ah)
Definition: hw.h:565
static void ar5008_restore_chainmask(struct ath_hw *ah)
void(* rfbus_done)(struct ath_hw *ah)
Definition: hw.h:579
static int ar5008_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
static void ar5008_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_SREV_9100(ah)
Definition: reg.h:810
static void ar5008_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
void(* mark_phy_inactive)(struct ath_hw *ah)
Definition: hw.h:576
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:331
static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
void * memcpy(void *dest, const void *src, size_t len) __nonnull
int(* process_ini)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:573
static int ar5008_hw_ani_control_old(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios @ah: atheros hardware ...
int(* set_rf_regs)(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
Definition: hw.h:567
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:591
static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers @ah: atheros hardware strut...
static int ar5008_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming @ah: atheros hardware s...
#define AR_PHY_CH2_EXT_CCA
Definition: ar9002_phy.h:585
static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
#define AR_PHY_CH1_EXT_CCA
Definition: ar9002_phy.h:579
static void ar5008_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
static void ar5008_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios @ah: atheros hardware s...
#define AR_PHY_CH2_CCA
Definition: ar9002_phy.h:575
static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
void(* set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:575
void(* set_diversity)(struct ath_hw *ah, int value)
Definition: hw.h:581
#define AR_PHY_CCA
Definition: ar9002_phy.h:129
int(* rfbus_req)(struct ath_hw *ah)
Definition: hw.h:578
int modparam_force_new_ani
static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
int(* ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: hw.h:584
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
static void ar5008_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
void(* set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:570
uint8_t ah
Definition: registers.h:85
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
#define AR_SREV_9160_10_OR_LATER(_ah)
Definition: reg.h:817
void(* set_radar_params)(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: hw.h:587
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
void(* restore_chainmask)(struct ath_hw *ah)
Definition: hw.h:580
static void ar5008_hw_rfbus_done(struct ath_hw *ah)
uint32_t u32
Definition: stdint.h:23
static void ar5008_hw_set_radar_params(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
static void ar5008_set_diversity(struct ath_hw *ah, int value)

References ah, ath_hw_private_ops::ani_cache_ini_regs, ath_hw_private_ops::ani_control, ar5008_hw_ani_cache_ini_regs(), ar5008_hw_ani_control_new(), ar5008_hw_ani_control_old(), ar5008_hw_compute_pll_control(), ar5008_hw_do_getnf(), ar5008_hw_init_bb(), ar5008_hw_mark_phy_inactive(), ar5008_hw_process_ini(), ar5008_hw_rf_alloc_ext_banks(), ar5008_hw_rf_free_ext_banks(), ar5008_hw_rfbus_done(), ar5008_hw_rfbus_req(), ar5008_hw_set_channel(), ar5008_hw_set_channel_regs(), ar5008_hw_set_delta_slope(), ar5008_hw_set_nf_limits(), ar5008_hw_set_radar_conf(), ar5008_hw_set_radar_params(), ar5008_hw_set_rf_regs(), ar5008_hw_set_rfmode(), ar5008_hw_spur_mitigate(), ar5008_restore_chainmask(), ar5008_set_diversity(), ar9100_hw_compute_pll_control(), ar9160_hw_compute_pll_control(), AR_PHY_CCA, AR_PHY_CH1_CCA, AR_PHY_CH1_EXT_CCA, AR_PHY_CH2_CCA, AR_PHY_CH2_EXT_CCA, AR_PHY_EXT_CCA, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, ath_hw_private_ops::init_bb, ath_hw_private_ops::mark_phy_inactive, memcpy(), modparam_force_new_ani, ath_hw_private_ops::process_ini, ath_hw_private_ops::restore_chainmask, ath_hw_private_ops::rf_alloc_ext_banks, ath_hw_private_ops::rf_free_ext_banks, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::rfbus_done, ath_hw_private_ops::rfbus_req, ath_hw_private_ops::set_channel_regs, ath_hw_private_ops::set_delta_slope, ath_hw_private_ops::set_diversity, ath_hw_private_ops::set_radar_params, ath_hw_private_ops::set_rf_regs, ath_hw_private_ops::set_rfmode, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9002_hw_attach_ops().

◆ ar9002_hw_attach_phy_ops()

void ar9002_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 561 of file ath9k_ar9002_phy.c.

562 {
563  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
564  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
565 
566  priv_ops->set_rf_regs = NULL;
567  priv_ops->rf_alloc_ext_banks = NULL;
568  priv_ops->rf_free_ext_banks = NULL;
571  priv_ops->olc_init = ar9002_olc_init;
573  priv_ops->do_getnf = ar9002_hw_do_getnf;
574 
577 
579 }
void(* rf_free_ext_banks)(struct ath_hw *ah)
Definition: hw.h:566
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
int(* rf_alloc_ext_banks)(struct ath_hw *ah)
Definition: hw.h:565
static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, struct ath9k_channel *chan)
void(* olc_init)(struct ath_hw *ah)
Definition: hw.h:574
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
void(* antdiv_comb_conf_set)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:641
static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
DOC: Programming Atheros 802.11n analog front end radios.
static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
static void ar9002_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
int(* set_rf_regs)(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
Definition: hw.h:567
static void ar9002_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
ar9002_hw_spur_mitigate - convert baseband spur frequency @ah: atheros hardware structure @chan:
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
static void ar9002_olc_init(struct ath_hw *ah)
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
void(* antdiv_comb_conf_get)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:639
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
uint8_t ah
Definition: registers.h:85
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9002_hw_antdiv_comb_conf_get(), ar9002_hw_antdiv_comb_conf_set(), ar9002_hw_compute_pll_control(), ar9002_hw_do_getnf(), ar9002_hw_set_channel(), ar9002_hw_set_nf_limits(), ar9002_hw_spur_mitigate(), ar9002_olc_init(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, NULL, ath_hw_private_ops::olc_init, ath_hw_private_ops::rf_alloc_ext_banks, ath_hw_private_ops::rf_free_ext_banks, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::set_rf_regs, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9002_hw_attach_ops().

◆ ar9003_hw_attach_phy_ops()

void ar9003_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 1232 of file ath9k_ar9003_phy.c.

1233 {
1234  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1235  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1236  static const u32 ar9300_cca_regs[6] = {
1237  AR_PHY_CCA_0,
1238  AR_PHY_CCA_1,
1239  AR_PHY_CCA_2,
1243  };
1244 
1245  priv_ops->rf_set_freq = ar9003_hw_set_channel;
1249  priv_ops->init_bb = ar9003_hw_init_bb;
1250  priv_ops->process_ini = ar9003_hw_process_ini;
1251  priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1254  priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1255  priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1257  priv_ops->ani_control = ar9003_hw_ani_control;
1258  priv_ops->do_getnf = ar9003_hw_do_getnf;
1261 
1264 
1267  memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1268 }
void(* set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:577
static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
void(* init_bb)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:571
static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
static void ar9003_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
static void ar9003_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
void(* rfbus_done)(struct ath_hw *ah)
Definition: hw.h:579
static void ar9003_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
#define AR_PHY_EXT_CCA_1
Definition: ar9003_phy.h:802
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
static void ar9003_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
void(* antdiv_comb_conf_set)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:641
void(* mark_phy_inactive)(struct ath_hw *ah)
Definition: hw.h:576
static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:331
void * memcpy(void *dest, const void *src, size_t len) __nonnull
int(* process_ini)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:573
static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:591
static void ar9003_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
static void ar9003_hw_rfbus_done(struct ath_hw *ah)
static int ar9003_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
static void ar9003_hw_set_diversity(struct ath_hw *ah, int value)
#define AR_PHY_CCA_1
Definition: ar9003_phy.h:823
static int ar9003_hw_rfbus_req(struct ath_hw *ah)
static int ar9003_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
void(* set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:575
void(* set_diversity)(struct ath_hw *ah, int value)
Definition: hw.h:581
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
int(* rfbus_req)(struct ath_hw *ah)
Definition: hw.h:578
int(* ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: hw.h:584
void(* antdiv_comb_conf_get)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:639
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
void(* set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:570
uint8_t ah
Definition: registers.h:85
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
void(* set_radar_params)(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: hw.h:587
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
static void ar9003_hw_set_radar_params(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
#define AR_PHY_EXT_CCA_2
Definition: ar9003_phy.h:858
uint32_t u32
Definition: stdint.h:23
#define AR_PHY_CCA_2
Definition: ar9003_phy.h:878
#define AR_PHY_CCA_0
Definition: ar9003_phy.h:260
static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
ar9003_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan:

References ah, ath_hw_private_ops::ani_cache_ini_regs, ath_hw_private_ops::ani_control, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ani_control(), ar9003_hw_antdiv_comb_conf_get(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_compute_pll_control(), ar9003_hw_do_getnf(), ar9003_hw_init_bb(), ar9003_hw_mark_phy_inactive(), ar9003_hw_process_ini(), ar9003_hw_rfbus_done(), ar9003_hw_rfbus_req(), ar9003_hw_set_channel(), ar9003_hw_set_channel_regs(), ar9003_hw_set_delta_slope(), ar9003_hw_set_diversity(), ar9003_hw_set_nf_limits(), ar9003_hw_set_radar_conf(), ar9003_hw_set_radar_params(), ar9003_hw_set_rfmode(), ar9003_hw_spur_mitigate(), AR_PHY_CCA_0, AR_PHY_CCA_1, AR_PHY_CCA_2, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_1, AR_PHY_EXT_CCA_2, ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, ath_hw_private_ops::init_bb, ath_hw_private_ops::mark_phy_inactive, memcpy(), ath_hw_private_ops::process_ini, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::rfbus_done, ath_hw_private_ops::rfbus_req, ath_hw_private_ops::set_channel_regs, ath_hw_private_ops::set_delta_slope, ath_hw_private_ops::set_diversity, ath_hw_private_ops::set_radar_params, ath_hw_private_ops::set_rfmode, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9003_hw_attach_ops().

◆ ar9002_hw_attach_calib_ops()

void ar9002_hw_attach_calib_ops ( struct ath_hw ah)

Definition at line 987 of file ath9k_ar9002_calib.c.

988 {
989  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
990  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
991 
993  priv_ops->init_cal = ar9002_hw_init_cal;
995 
997 }
static int ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
void(* init_cal_settings)(struct ath_hw *ah)
Definition: hw.h:552
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
static void ar9002_hw_setup_calibration(struct ath_hw *ah, struct ath9k_cal_list *currCal)
void(* setup_calibration)(struct ath_hw *ah, struct ath9k_cal_list *currCal)
Definition: hw.h:557
static int ar9002_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
int(* calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
Definition: hw.h:610
static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
int(* init_cal)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:553

References ah, ar9002_hw_calibrate(), ar9002_hw_init_cal(), ar9002_hw_init_cal_settings(), ar9002_hw_setup_calibration(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_ops::calibrate, ath_hw_private_ops::init_cal, ath_hw_private_ops::init_cal_settings, and ath_hw_private_ops::setup_calibration.

Referenced by ar9002_hw_attach_ops().

◆ ar9003_hw_attach_calib_ops()

void ar9003_hw_attach_calib_ops ( struct ath_hw ah)

Definition at line 922 of file ath9k_ar9003_calib.c.

923 {
924  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
925  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
926 
928  priv_ops->init_cal = ar9003_hw_init_cal;
930 
932 }
static void ar9003_hw_setup_calibration(struct ath_hw *ah, struct ath9k_cal_list *currCal)
void(* init_cal_settings)(struct ath_hw *ah)
Definition: hw.h:552
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
void(* setup_calibration)(struct ath_hw *ah, struct ath9k_cal_list *currCal)
Definition: hw.h:557
static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
int(* calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
Definition: hw.h:610
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
static int ar9003_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
static int ar9003_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan __unused)
int(* init_cal)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:553

References ah, ar9003_hw_calibrate(), ar9003_hw_init_cal(), ar9003_hw_init_cal_settings(), ar9003_hw_setup_calibration(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_ops::calibrate, ath_hw_private_ops::init_cal, ath_hw_private_ops::init_cal_settings, and ath_hw_private_ops::setup_calibration.

Referenced by ar9003_hw_attach_ops().

◆ ar9002_hw_attach_ops()

void ar9002_hw_attach_ops ( struct ath_hw ah)

Definition at line 545 of file ath9k_ar9002_hw.c.

546 {
547  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
548  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
549 
552 
554 
558 
561 }
void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
void(* init_mode_regs)(struct ath_hw *ah)
Definition: hw.h:555
static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
void(* config_pci_powersave)(struct ath_hw *ah, int restore, int power_off)
Definition: hw.h:604
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition: hw.h:556
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
static void ar9002_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
void ar9002_hw_attach_phy_ops(struct ath_hw *ah)

References ah, ar5008_hw_attach_phy_ops(), ar9002_hw_attach_calib_ops(), ar9002_hw_attach_mac_ops(), ar9002_hw_attach_phy_ops(), ar9002_hw_configpcipowersave(), ar9002_hw_init_mode_gain_regs(), ar9002_hw_init_mode_regs(), AR_SREV_9280_20_OR_LATER, ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_ops::config_pci_powersave, ath_hw_private_ops::init_mode_gain_regs, and ath_hw_private_ops::init_mode_regs.

Referenced by ath9k_hw_attach_ops().

◆ ar9003_hw_attach_ops()

void ar9003_hw_attach_ops ( struct ath_hw ah)

Definition at line 396 of file ath9k_ar9003_hw.c.

397 {
398  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
399  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
400 
403 
405 
409 }
static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
static void ar9003_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
void(* init_mode_regs)(struct ath_hw *ah)
Definition: hw.h:555
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
void(* config_pci_powersave)(struct ath_hw *ah, int restore, int power_off)
Definition: hw.h:604
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition: hw.h:556
void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879

References ah, ar9003_hw_attach_calib_ops(), ar9003_hw_attach_mac_ops(), ar9003_hw_attach_phy_ops(), ar9003_hw_configpcipowersave(), ar9003_hw_init_mode_gain_regs(), ar9003_hw_init_mode_regs(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_ops::config_pci_powersave, ath_hw_private_ops::init_mode_gain_regs, and ath_hw_private_ops::init_mode_regs.

Referenced by ath9k_hw_attach_ops().

◆ ar9002_hw_load_ani_reg()

void ar9002_hw_load_ani_reg ( struct ath_hw ah,
struct ath9k_channel chan 
)

Definition at line 563 of file ath9k_ar9002_hw.c.

564 {
565  u32 modesIndex;
566  unsigned int i;
567 
568  switch (chan->chanmode) {
569  case CHANNEL_A:
570  case CHANNEL_A_HT20:
571  modesIndex = 1;
572  break;
573  case CHANNEL_A_HT40PLUS:
574  case CHANNEL_A_HT40MINUS:
575  modesIndex = 2;
576  break;
577  case CHANNEL_G:
578  case CHANNEL_G_HT20:
579  case CHANNEL_B:
580  modesIndex = 4;
581  break;
582  case CHANNEL_G_HT40PLUS:
583  case CHANNEL_G_HT40MINUS:
584  modesIndex = 3;
585  break;
586 
587  default:
588  return;
589  }
590 
592 
593  for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
594  u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
595  u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
596  u32 val_orig;
597 
598  if (reg == AR_PHY_CCK_DETECT) {
599  val_orig = REG_READ(ah, reg);
602 
603  REG_WRITE(ah, reg, val|val_orig);
604  } else
605  REG_WRITE(ah, reg, val);
606  }
607 
609 }
u32 chanmode
Definition: hw.h:351
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define CHANNEL_A_HT40MINUS
Definition: hw.h:322
#define CHANNEL_A
Definition: ath5k.h:638
#define CHANNEL_G
Definition: ath5k.h:640
#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK
Definition: ar9002_phy.h:414
#define CHANNEL_A_HT20
Definition: hw.h:318
static unsigned int unsigned int reg
Definition: intel.h:245
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:413
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void __asmcall int val
Definition: setjmp.h:28
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define CHANNEL_A_HT40PLUS
Definition: hw.h:321
uint8_t ah
Definition: registers.h:85
#define CHANNEL_G_HT20
Definition: hw.h:317
#define CHANNEL_B
Definition: ath5k.h:639
#define CHANNEL_G_HT40PLUS
Definition: hw.h:319
#define CHANNEL_G_HT40MINUS
Definition: hw.h:320
uint32_t u32
Definition: stdint.h:23
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89

References ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, ath9k_channel::chanmode, CHANNEL_A, CHANNEL_A_HT20, CHANNEL_A_HT40MINUS, CHANNEL_A_HT40PLUS, CHANNEL_B, CHANNEL_G, CHANNEL_G_HT20, CHANNEL_G_HT40MINUS, CHANNEL_G_HT40PLUS, ENABLE_REGWRITE_BUFFER, INI_RA, reg, REG_READ, REG_WRITE, REGWRITE_BUFFER_FLUSH, and val.

Referenced by ath9k_hw_reset().

◆ ath9k_ani_reset()

void ath9k_ani_reset ( struct ath_hw ah,
int  is_scanning 
)

Definition at line 466 of file ath9k_ani.c.

467 {
468  struct ar5416AniState *aniState = &ah->curchan->ani;
469  struct ath9k_channel *chan = ah->curchan;
470 
471  if (!DO_ANI(ah))
472  return;
473 
474  if (!use_new_ani(ah))
475  return ath9k_ani_reset_old(ah);
476 
477  ah->stats.ast_ani_reset++;
478 
479  /* always allow mode (on/off) to be controlled */
480  ah->ani_function |= ATH9K_ANI_MODE;
481 
482  if (is_scanning) {
483  /*
484  * If we're scanning or in AP mode, the defaults (ini)
485  * should be in place. For an AP we assume the historical
486  * levels for this channel are probably outdated so start
487  * from defaults instead.
488  */
489  if (aniState->ofdmNoiseImmunityLevel !=
491  aniState->cckNoiseImmunityLevel !=
493  DBG("ath9k: "
494  "Restore defaults: chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
495  chan->channel,
496  chan->channelFlags,
497  is_scanning,
498  aniState->ofdmNoiseImmunityLevel,
499  aniState->cckNoiseImmunityLevel);
500 
503  }
504  } else {
505  /*
506  * restore historical levels for this channel
507  */
508  DBG2("ath9k: "
509  "Restore history: chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
510  chan->channel,
511  chan->channelFlags,
512  is_scanning,
513  aniState->ofdmNoiseImmunityLevel,
514  aniState->cckNoiseImmunityLevel);
515 
517  aniState->ofdmNoiseImmunityLevel);
519  aniState->cckNoiseImmunityLevel);
520  }
521 
522  /*
523  * enable phy counters if hw supports or if not, enable phy
524  * interrupts (so we can count each one)
525  */
527 
529 
532 
534 }
static void ath9k_hw_set_cck_nil(struct ath_hw *ah, uint8_t immunityLevel)
Definition: ath9k_ani.c:296
#define AR_PHY_ERR_MASK_2
Definition: reg.h:1670
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define ATH9K_ANI_OFDM_DEF_LEVEL
Definition: ath9k_ani.c:57
#define AR_PHY_ERR_CCK_TIMING
Definition: reg.h:1632
u8 cckNoiseImmunityLevel
Definition: ani.h:123
#define ATH9K_ANI_CCK_DEF_LEVEL
Definition: ath9k_ani.c:105
struct net80211_channel * chan
Definition: hw.h:347
#define DO_ANI(ah)
Definition: ani.h:27
static void ath9k_ani_restart(struct ath_hw *ah)
Definition: ath9k_ani.c:123
static int use_new_ani(struct ath_hw *ah)
Definition: ath9k_ani.c:108
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_ERR_MASK_1
Definition: reg.h:1666
uint8_t ah
Definition: registers.h:85
static void ath9k_ani_reset_old(struct ath_hw *ah)
Definition: ath9k_ani.c:424
#define AR_PHY_ERR_OFDM_TIMING
Definition: reg.h:1631
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
Definition: ath9k_ani.c:244
u8 ofdmNoiseImmunityLevel
Definition: ani.h:122
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
#define DBG2(...)
Definition: compiler.h:515

References ah, AR_PHY_ERR_CCK_TIMING, AR_PHY_ERR_MASK_1, AR_PHY_ERR_MASK_2, AR_PHY_ERR_OFDM_TIMING, ATH9K_ANI_CCK_DEF_LEVEL, ATH9K_ANI_MODE, ATH9K_ANI_OFDM_DEF_LEVEL, ath9k_ani_reset_old(), ath9k_ani_restart(), ath9k_hw_set_cck_nil(), ath9k_hw_set_ofdm_nil(), ar5416AniState::cckNoiseImmunityLevel, ath9k_channel::chan, DBG, DBG2, DO_ANI, ENABLE_REGWRITE_BUFFER, ar5416AniState::ofdmNoiseImmunityLevel, REG_WRITE, REGWRITE_BUFFER_FLUSH, and use_new_ani().

Referenced by ath9k_hw_startpcureceive().

◆ ath9k_hw_proc_mib_event()

void ath9k_hw_proc_mib_event ( struct ath_hw ah)

◆ ath9k_hw_ani_monitor()

void ath9k_hw_ani_monitor ( struct ath_hw ah,
struct ath9k_channel chan 
)

Variable Documentation

◆ modparam_force_new_ani

int modparam_force_new_ani

Definition at line 28 of file ath9k_ar9002_hw.c.

Referenced by ar5008_hw_attach_phy_ops(), and use_new_ani().