iPXE
Macros | Functions
ath5k_desc.c File Reference
#include "ath5k.h"
#include "reg.h"
#include "base.h"

Go to the source code of this file.

Macros

#define FCS_LEN   4
 
#define _TX_FLAGS(_c, _flag)
 
#define _TX_FLAGS(_c, _flag)
 

Functions

 FILE_LICENCE (MIT)
 
static int ath5k_hw_setup_2word_tx_desc (struct ath5k_hw *ah, struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0, unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate __unused, unsigned int rtscts_duration)
 
static int ath5k_hw_setup_4word_tx_desc (struct ath5k_hw *ah, struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused, enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, unsigned int rtscts_duration)
 
static int ath5k_hw_proc_2word_tx_status (struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 
static int ath5k_hw_proc_4word_tx_status (struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 
static int ath5k_hw_setup_rx_desc (struct ath5k_hw *ah __unused, struct ath5k_desc *desc, u32 size, unsigned int flags)
 
static int ath5k_hw_proc_5210_rx_status (struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_rx_status *rs)
 
static int ath5k_hw_proc_5212_rx_status (struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_rx_status *rs)
 
int ath5k_hw_init_desc_functions (struct ath5k_hw *ah)
 

Macro Definition Documentation

◆ FCS_LEN

#define FCS_LEN   4

Definition at line 36 of file ath5k_desc.c.

◆ _TX_FLAGS [1/2]

#define _TX_FLAGS (   _c,
  _flag 
)
Value:
if (flags & AR5K_TXDESC_##_flag) { \
tx_ctl->tx_control_##_c |= \
AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
}
uint8_t flags
Flags.
Definition: ena.h:18

◆ _TX_FLAGS [2/2]

#define _TX_FLAGS (   _c,
  _flag 
)
Value:
if (flags & AR5K_TXDESC_##_flag) { \
tx_ctl->tx_control_##_c |= \
AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
}
uint8_t flags
Flags.
Definition: ena.h:18

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( MIT  )

◆ ath5k_hw_setup_2word_tx_desc()

static int ath5k_hw_setup_2word_tx_desc ( struct ath5k_hw ah,
struct ath5k_desc desc,
unsigned int  pkt_len,
unsigned int  hdr_len,
enum ath5k_pkt_type  type,
unsigned int tx_power  __unused,
unsigned int  tx_rate0,
unsigned int  tx_tries0,
unsigned int key_index  __unused,
unsigned int  antenna_mode,
unsigned int  flags,
unsigned int rtscts_rate  __unused,
unsigned int  rtscts_duration 
)
static

Definition at line 42 of file ath5k_desc.c.

47 {
48  u32 frame_type;
49  struct ath5k_hw_2w_tx_ctl *tx_ctl;
50  unsigned int frame_len;
51 
52  tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
53 
54  /*
55  * Validate input
56  * - Zero retries don't make sense.
57  * - A zero rate will put the HW into a mode where it continously sends
58  * noise on the channel, so it is important to avoid this.
59  */
60  if (tx_tries0 == 0) {
61  DBG("ath5k: zero retries\n");
62  return -EINVAL;
63  }
64  if (tx_rate0 == 0) {
65  DBG("ath5k: zero rate\n");
66  return -EINVAL;
67  }
68 
69  /* Clear descriptor */
70  memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
71 
72  /* Setup control descriptor */
73 
74  /* Verify and set frame length */
75 
76  frame_len = pkt_len + FCS_LEN;
77 
78  if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
79  return -EINVAL;
80 
82 
83  /* Verify and set buffer length */
84 
85  if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
86  return -EINVAL;
87 
89 
90  /*
91  * Verify and set header length
92  * XXX: I only found that on 5210 code, does it work on 5211 ?
93  */
94  if (ah->ah_version == AR5K_AR5210) {
95  if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
96  return -EINVAL;
99  }
100 
101  /*Diferences between 5210-5211*/
102  if (ah->ah_version == AR5K_AR5210) {
103  switch (type) {
107  break;
108  case AR5K_PKT_TYPE_PIFS:
110  break;
111  default:
112  frame_type = type /*<< 2 ?*/;
113  break;
114  }
115 
116  tx_ctl->tx_control_0 |=
119 
120  } else {
121  tx_ctl->tx_control_0 |=
123  AR5K_REG_SM(antenna_mode,
125  tx_ctl->tx_control_1 |=
127  }
128 #define _TX_FLAGS(_c, _flag) \
129  if (flags & AR5K_TXDESC_##_flag) { \
130  tx_ctl->tx_control_##_c |= \
131  AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
132  }
133 
134  _TX_FLAGS(0, CLRDMASK);
135  _TX_FLAGS(0, VEOL);
136  _TX_FLAGS(0, INTREQ);
137  _TX_FLAGS(0, RTSENA);
138  _TX_FLAGS(1, NOACK);
139 
140 #undef _TX_FLAGS
141 
142  /*
143  * RTS/CTS Duration [5210 ?]
144  */
145  if ((ah->ah_version == AR5K_AR5210) &&
147  tx_ctl->tx_control_1 |= rtscts_duration &
149 
150  return 0;
151 }
#define AR5K_2W_TX_DESC_CTL1_BUF_LEN
Definition: desc.h:158
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS
Definition: desc.h:179
struct ath5k_hw_2w_tx_ctl tx_ctl
Definition: desc.h:286
union ath5k_desc::@18 ud
uint8_t type
Type.
Definition: ena.h:16
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE
Definition: desc.h:169
#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE
Definition: desc.h:143
#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE
Definition: desc.h:137
#define _TX_FLAGS(_c, _flag)
#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION
Definition: desc.h:172
#define AR5K_TXDESC_RTSENA
Definition: desc.h:328
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY
Definition: desc.h:178
u32 tx_control_1
Definition: desc.h:130
#define FCS_LEN
Definition: ath5k_desc.c:36
struct ath5k_hw_2w_tx_ctl tx_ctl
Definition: desc.h:129
u32 tx_control_0
Definition: desc.h:129
struct ath5k_hw_5210_tx_desc ds_tx5210
Definition: desc.h:318
#define AR5K_TXDESC_CTSENA
Definition: desc.h:329
#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT
Definition: desc.h:148
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN
Definition: desc.h:134
#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN
Definition: desc.h:135
uint32_t u32
Definition: stdint.h:23
void * memset(void *dest, int character, size_t len) __nonnull
#define AR5K_REG_SM(_val, _flags)
Definition: ath5k.h:84
uint8_t flags
Flags.
Definition: ena.h:18

References _TX_FLAGS, ah, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT, AR5K_2W_TX_DESC_CTL0_FRAME_LEN, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE, AR5K_2W_TX_DESC_CTL0_HEADER_LEN, AR5K_2W_TX_DESC_CTL0_XMIT_RATE, AR5K_2W_TX_DESC_CTL1_BUF_LEN, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE, AR5K_2W_TX_DESC_CTL1_RTS_DURATION, AR5K_AR5210, AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY, AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS, AR5K_PKT_TYPE_BEACON, AR5K_PKT_TYPE_PIFS, AR5K_PKT_TYPE_PROBE_RESP, AR5K_REG_SM, AR5K_TXDESC_CTSENA, AR5K_TXDESC_RTSENA, DBG, ath5k_desc::ds_tx5210, EINVAL, FCS_LEN, flags, memset(), ath5k_hw_2w_tx_ctl::tx_control_0, ath5k_hw_2w_tx_ctl::tx_control_1, ath5k_hw_5210_tx_desc::tx_ctl, tx_ctl, type, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_setup_4word_tx_desc()

static int ath5k_hw_setup_4word_tx_desc ( struct ath5k_hw ah,
struct ath5k_desc desc,
unsigned int  pkt_len,
unsigned int hdr_len  __unused,
enum ath5k_pkt_type  type,
unsigned int  tx_power,
unsigned int  tx_rate0,
unsigned int  tx_tries0,
unsigned int key_index  __unused,
unsigned int  antenna_mode,
unsigned int  flags,
unsigned int  rtscts_rate,
unsigned int  rtscts_duration 
)
static

Definition at line 156 of file ath5k_desc.c.

163 {
164  struct ath5k_hw_4w_tx_ctl *tx_ctl;
165  unsigned int frame_len;
166 
167  tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
168 
169  /*
170  * Validate input
171  * - Zero retries don't make sense.
172  * - A zero rate will put the HW into a mode where it continously sends
173  * noise on the channel, so it is important to avoid this.
174  */
175  if (tx_tries0 == 0) {
176  DBG("ath5k: zero retries\n");
177  return -EINVAL;
178  }
179  if (tx_rate0 == 0) {
180  DBG("ath5k: zero rate\n");
181  return -EINVAL;
182  }
183 
184  tx_power += ah->ah_txpower.txp_offset;
185  if (tx_power > AR5K_TUNE_MAX_TXPOWER)
186  tx_power = AR5K_TUNE_MAX_TXPOWER;
187 
188  /* Clear descriptor */
189  memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
190 
191  /* Setup control descriptor */
192 
193  /* Verify and set frame length */
194 
195  frame_len = pkt_len + FCS_LEN;
196 
197  if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
198  return -EINVAL;
199 
201 
202  /* Verify and set buffer length */
203 
204  if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
205  return -EINVAL;
206 
208 
209  tx_ctl->tx_control_0 |=
214  tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
216  tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
217 
218 #define _TX_FLAGS(_c, _flag) \
219  if (flags & AR5K_TXDESC_##_flag) { \
220  tx_ctl->tx_control_##_c |= \
221  AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
222  }
223 
224  _TX_FLAGS(0, CLRDMASK);
225  _TX_FLAGS(0, VEOL);
226  _TX_FLAGS(0, INTREQ);
227  _TX_FLAGS(0, RTSENA);
228  _TX_FLAGS(0, CTSENA);
229  _TX_FLAGS(1, NOACK);
230 
231 #undef _TX_FLAGS
232 
233  /*
234  * RTS/CTS
235  */
237  if ((flags & AR5K_TXDESC_RTSENA) &&
239  return -EINVAL;
240  tx_ctl->tx_control_2 |= rtscts_duration &
242  tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
244  }
245 
246  return 0;
247 }
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE
Definition: desc.h:149
union ath5k_desc::@18 ud
uint8_t type
Type.
Definition: ena.h:16
struct ath5k_hw_5212_tx_desc ds_tx5212
Definition: desc.h:319
#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN
Definition: desc.h:131
#define _TX_FLAGS(_c, _flag)
#define AR5K_TXDESC_RTSENA
Definition: desc.h:328
u32 tx_control_1
Definition: desc.h:130
#define FCS_LEN
Definition: ath5k_desc.c:36
struct ath5k_hw_2w_tx_ctl tx_ctl
Definition: desc.h:129
#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE
Definition: desc.h:181
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0
Definition: desc.h:174
u32 tx_control_0
Definition: desc.h:129
struct ath5k_hw_4w_tx_ctl tx_ctl
Definition: desc.h:294
#define AR5K_TUNE_HWTXTRIES
Definition: ath5k.h:195
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER
Definition: desc.h:132
#define AR5K_4W_TX_DESC_CTL1_BUF_LEN
Definition: desc.h:145
#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION
Definition: desc.h:161
#define AR5K_TXDESC_CTSENA
Definition: desc.h:329
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0
Definition: desc.h:163
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT
Definition: desc.h:137
#define AR5K_TUNE_MAX_TXPOWER
Definition: ath5k.h:191
void * memset(void *dest, int character, size_t len) __nonnull
#define AR5K_REG_SM(_val, _flags)
Definition: ath5k.h:84
uint8_t flags
Flags.
Definition: ena.h:18

References _TX_FLAGS, ah, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT, AR5K_4W_TX_DESC_CTL0_FRAME_LEN, AR5K_4W_TX_DESC_CTL0_XMIT_POWER, AR5K_4W_TX_DESC_CTL1_BUF_LEN, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE, AR5K_4W_TX_DESC_CTL2_RTS_DURATION, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0, AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE, AR5K_4W_TX_DESC_CTL3_XMIT_RATE0, AR5K_REG_SM, AR5K_TUNE_HWTXTRIES, AR5K_TUNE_MAX_TXPOWER, AR5K_TXDESC_CTSENA, AR5K_TXDESC_RTSENA, DBG, ath5k_desc::ds_tx5212, EINVAL, FCS_LEN, flags, memset(), ath5k_hw_2w_tx_ctl::tx_control_0, ath5k_hw_2w_tx_ctl::tx_control_1, tx_ctl, ath5k_hw_5212_tx_desc::tx_ctl, type, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_proc_2word_tx_status()

static int ath5k_hw_proc_2word_tx_status ( struct ath5k_hw *ah  __unused,
struct ath5k_desc desc,
struct ath5k_tx_status ts 
)
static

Definition at line 252 of file ath5k_desc.c.

254 {
255  struct ath5k_hw_2w_tx_ctl *tx_ctl;
256  struct ath5k_hw_tx_status *tx_status;
257 
258  tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
259  tx_status = &desc->ud.ds_tx5210.tx_stat;
260 
261  /* No frame has been send or error */
262  if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
263  return -EINPROGRESS;
264 
265  /*
266  * Get descriptor status
267  */
268  ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
270  ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
272  ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
274  /*TODO: ts->ts_virtcol + test*/
275  ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
277  ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
279  ts->ts_antenna = 1;
280  ts->ts_status = 0;
283  ts->ts_retry[0] = ts->ts_longretry;
284  ts->ts_final_idx = 0;
285 
286  if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
287  if (tx_status->tx_status_0 &
290 
292  ts->ts_status |= AR5K_TXERR_FIFO;
293 
295  ts->ts_status |= AR5K_TXERR_FILT;
296  }
297 
298  return 0;
299 }
struct ath5k_hw_2w_tx_ctl tx_ctl
Definition: desc.h:286
u8 ts_retry[4]
Definition: ath5k.h:421
union ath5k_desc::@18 ud
#define AR5K_TXERR_FILT
Definition: ath5k.h:432
#define AR5K_DESC_TX_STATUS1_SEQ_NUM
Definition: desc.h:273
#define AR5K_DESC_TX_STATUS0_FILTERED
Definition: desc.h:253
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT
Definition: desc.h:264
#define AR5K_TXERR_FIFO
Definition: ath5k.h:433
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE
Definition: desc.h:137
#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN
Definition: desc.h:252
u16 ts_tstamp
Definition: ath5k.h:418
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH
Definition: desc.h:275
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP
Definition: desc.h:268
#define AR5K_TXERR_XRETRY
Definition: ath5k.h:431
u8 ts_rate[4]
Definition: ath5k.h:420
#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES
Definition: desc.h:251
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
struct ath5k_hw_2w_tx_ctl tx_ctl
Definition: desc.h:129
#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK
Definition: desc.h:250
u32 tx_control_0
Definition: desc.h:129
u8 ts_longretry
Definition: ath5k.h:425
struct ath5k_hw_5210_tx_desc ds_tx5210
Definition: desc.h:318
u16 ts_seqnum
Definition: ath5k.h:417
u8 ts_shortretry
Definition: ath5k.h:424
u8 ts_final_idx
Definition: ath5k.h:422
struct ath5k_hw_tx_status tx_stat
Definition: desc.h:287
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT
Definition: desc.h:258
#define AR5K_DESC_TX_STATUS1_DONE
Definition: desc.h:272

References AR5K_2W_TX_DESC_CTL0_XMIT_RATE, AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES, AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN, AR5K_DESC_TX_STATUS0_FILTERED, AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK, AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT, AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP, AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT, AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH, AR5K_DESC_TX_STATUS1_DONE, AR5K_DESC_TX_STATUS1_SEQ_NUM, AR5K_REG_MS, AR5K_TXERR_FIFO, AR5K_TXERR_FILT, AR5K_TXERR_XRETRY, ath5k_desc::ds_tx5210, EINPROGRESS, ath5k_tx_status::ts_antenna, ath5k_tx_status::ts_final_idx, ath5k_tx_status::ts_longretry, ath5k_tx_status::ts_rate, ath5k_tx_status::ts_retry, ath5k_tx_status::ts_rssi, ath5k_tx_status::ts_seqnum, ath5k_tx_status::ts_shortretry, ath5k_tx_status::ts_status, ath5k_tx_status::ts_tstamp, ath5k_hw_2w_tx_ctl::tx_control_0, tx_ctl, ath5k_hw_5210_tx_desc::tx_ctl, ath5k_hw_5210_tx_desc::tx_stat, ath5k_hw_tx_status::tx_status_0, ath5k_hw_tx_status::tx_status_1, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_proc_4word_tx_status()

static int ath5k_hw_proc_4word_tx_status ( struct ath5k_hw *ah  __unused,
struct ath5k_desc desc,
struct ath5k_tx_status ts 
)
static

Definition at line 304 of file ath5k_desc.c.

306 {
307  struct ath5k_hw_4w_tx_ctl *tx_ctl;
308  struct ath5k_hw_tx_status *tx_status;
309 
310  tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
311  tx_status = &desc->ud.ds_tx5212.tx_stat;
312 
313  /* No frame has been send or error */
314  if (!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE))
315  return -EINPROGRESS;
316 
317  /*
318  * Get descriptor status
319  */
320  ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
322  ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
324  ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
326  ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
328  ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
330  ts->ts_antenna = (tx_status->tx_status_1 &
332  ts->ts_status = 0;
333 
334  ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
336 
337  ts->ts_retry[0] = ts->ts_longretry;
338  ts->ts_rate[0] = tx_ctl->tx_control_3 &
340 
341  /* TX error */
342  if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
343  if (tx_status->tx_status_0 &
346 
348  ts->ts_status |= AR5K_TXERR_FIFO;
349 
351  ts->ts_status |= AR5K_TXERR_FILT;
352  }
353 
354  return 0;
355 }
u8 ts_retry[4]
Definition: ath5k.h:421
union ath5k_desc::@18 ud
#define AR5K_TXERR_FILT
Definition: ath5k.h:432
struct ath5k_hw_5212_tx_desc ds_tx5212
Definition: desc.h:319
#define AR5K_DESC_TX_STATUS1_SEQ_NUM
Definition: desc.h:273
#define AR5K_DESC_TX_STATUS0_FILTERED
Definition: desc.h:253
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT
Definition: desc.h:264
struct ath5k_hw_tx_status tx_stat
Definition: desc.h:295
#define AR5K_TXERR_FIFO
Definition: ath5k.h:433
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN
Definition: desc.h:252
u16 ts_tstamp
Definition: ath5k.h:418
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH
Definition: desc.h:275
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP
Definition: desc.h:268
#define AR5K_TXERR_XRETRY
Definition: ath5k.h:431
u8 ts_rate[4]
Definition: ath5k.h:420
#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES
Definition: desc.h:251
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
struct ath5k_hw_2w_tx_ctl tx_ctl
Definition: desc.h:129
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0
Definition: desc.h:174
#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA
Definition: desc.h:280
#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK
Definition: desc.h:250
u8 ts_longretry
Definition: ath5k.h:425
struct ath5k_hw_4w_tx_ctl tx_ctl
Definition: desc.h:294
u16 ts_seqnum
Definition: ath5k.h:417
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX
Definition: desc.h:277
u8 ts_shortretry
Definition: ath5k.h:424
u8 ts_final_idx
Definition: ath5k.h:422
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT
Definition: desc.h:258
#define AR5K_DESC_TX_STATUS1_DONE
Definition: desc.h:272

References AR5K_4W_TX_DESC_CTL3_XMIT_RATE0, AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES, AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN, AR5K_DESC_TX_STATUS0_FILTERED, AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK, AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT, AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP, AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT, AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH, AR5K_DESC_TX_STATUS1_DONE, AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX, AR5K_DESC_TX_STATUS1_SEQ_NUM, AR5K_DESC_TX_STATUS1_XMIT_ANTENNA, AR5K_REG_MS, AR5K_TXERR_FIFO, AR5K_TXERR_FILT, AR5K_TXERR_XRETRY, ath5k_desc::ds_tx5212, EINPROGRESS, ath5k_tx_status::ts_antenna, ath5k_tx_status::ts_final_idx, ath5k_tx_status::ts_longretry, ath5k_tx_status::ts_rate, ath5k_tx_status::ts_retry, ath5k_tx_status::ts_rssi, ath5k_tx_status::ts_seqnum, ath5k_tx_status::ts_shortretry, ath5k_tx_status::ts_status, ath5k_tx_status::ts_tstamp, ath5k_hw_5212_tx_desc::tx_ctl, tx_ctl, ath5k_hw_5212_tx_desc::tx_stat, ath5k_hw_tx_status::tx_status_0, ath5k_hw_tx_status::tx_status_1, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_setup_rx_desc()

static int ath5k_hw_setup_rx_desc ( struct ath5k_hw *ah  __unused,
struct ath5k_desc desc,
u32  size,
unsigned int  flags 
)
static

Definition at line 364 of file ath5k_desc.c.

367 {
368  struct ath5k_hw_rx_ctl *rx_ctl;
369 
370  rx_ctl = &desc->ud.ds_rx.rx_ctl;
371 
372  /*
373  * Clear the descriptor
374  * If we don't clean the status descriptor,
375  * while scanning we get too many results,
376  * most of them virtual, after some secs
377  * of scanning system hangs. M.F.
378  */
379  memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
380 
381  /* Setup descriptor */
383  if (rx_ctl->rx_control_1 != size)
384  return -EINVAL;
385 
388 
389  return 0;
390 }
#define EINVAL
Invalid argument.
Definition: errno.h:428
struct ath5k_hw_rx_ctl rx_ctl
Definition: desc.h:302
#define AR5K_RXDESC_INTREQ
Definition: desc.h:324
union ath5k_desc::@18 ud
struct ath5k_hw_all_rx_desc ds_rx
Definition: desc.h:320
struct ath5k_hw_rx_ctl rx_ctl
Definition: desc.h:129
#define AR5K_DESC_RX_CTL1_INTREQ
Definition: desc.h:37
u32 rx_control_1
Definition: desc.h:29
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
#define AR5K_DESC_RX_CTL1_BUF_LEN
Definition: desc.h:36
void * memset(void *dest, int character, size_t len) __nonnull
uint8_t flags
Flags.
Definition: ena.h:18

References AR5K_DESC_RX_CTL1_BUF_LEN, AR5K_DESC_RX_CTL1_INTREQ, AR5K_RXDESC_INTREQ, ath5k_desc::ds_rx, EINVAL, flags, memset(), ath5k_hw_rx_ctl::rx_control_1, ath5k_hw_all_rx_desc::rx_ctl, rx_ctl, size, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_proc_5210_rx_status()

static int ath5k_hw_proc_5210_rx_status ( struct ath5k_hw *ah  __unused,
struct ath5k_desc desc,
struct ath5k_rx_status rs 
)
static

Definition at line 395 of file ath5k_desc.c.

397 {
398  struct ath5k_hw_rx_status *rx_status;
399 
400  rx_status = &desc->ud.ds_rx.u.rx_stat;
401 
402  /* No frame received / not ready */
403  if (!(rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE))
404  return -EINPROGRESS;
405 
406  /*
407  * Frame receive status
408  */
409  rs->rs_datalen = rx_status->rx_status_0 &
411  rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
413  rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
415  rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
417  rs->rs_more = !!(rx_status->rx_status_0 &
419  /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
420  rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
422  rs->rs_status = 0;
423  rs->rs_phyerr = 0;
425 
426  /*
427  * Receive/descriptor errors
428  */
429  if (!(rx_status->rx_status_1 &
431  if (rx_status->rx_status_1 &
433  rs->rs_status |= AR5K_RXERR_CRC;
434 
435  if (rx_status->rx_status_1 &
437  rs->rs_status |= AR5K_RXERR_FIFO;
438 
439  if (rx_status->rx_status_1 &
441  rs->rs_status |= AR5K_RXERR_PHY;
442  rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
444  }
445 
446  if (rx_status->rx_status_1 &
449  }
450 
451  return 0;
452 }
#define AR5K_RXERR_PHY
Definition: ath5k.h:580
#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR
Definition: desc.h:64
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL
Definition: desc.h:54
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA
Definition: desc.h:56
union ath5k_desc::@18 ud
#define AR5K_RXERR_FIFO
Definition: ath5k.h:581
u16 rs_tstamp
Definition: ath5k.h:569
#define AR5K_RXERR_CRC
Definition: ath5k.h:579
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
struct ath5k_hw_all_rx_desc ds_rx
Definition: desc.h:320
#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE
Definition: desc.h:52
#define AR5K_RXERR_DECRYPT
Definition: ath5k.h:582
#define AR5K_RXKEYIX_INVALID
Definition: ath5k.h:584
#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR
Definition: desc.h:62
struct ath5k_hw_rx_status rx_stat
Definition: desc.h:304
#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN
Definition: desc.h:63
#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN
Definition: desc.h:50
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK
Definition: desc.h:61
union ath5k_hw_all_rx_desc::@16 u
u32 rx_status_0
Definition: desc.h:44
#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP
Definition: desc.h:70
#define AR5K_5210_RX_DESC_STATUS0_MORE
Definition: desc.h:51
u32 rx_status_1
Definition: desc.h:45
#define AR5K_5210_RX_DESC_STATUS1_DONE
Definition: desc.h:60
u16 rs_datalen
Definition: ath5k.h:568
#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR
Definition: desc.h:65

References AR5K_5210_RX_DESC_STATUS0_DATA_LEN, AR5K_5210_RX_DESC_STATUS0_MORE, AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA, AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE, AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL, AR5K_5210_RX_DESC_STATUS1_CRC_ERROR, AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR, AR5K_5210_RX_DESC_STATUS1_DONE, AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN, AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK, AR5K_5210_RX_DESC_STATUS1_PHY_ERROR, AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP, AR5K_REG_MS, AR5K_RXERR_CRC, AR5K_RXERR_DECRYPT, AR5K_RXERR_FIFO, AR5K_RXERR_PHY, AR5K_RXKEYIX_INVALID, ath5k_desc::ds_rx, EINPROGRESS, ath5k_rx_status::rs_antenna, ath5k_rx_status::rs_datalen, ath5k_rx_status::rs_keyix, ath5k_rx_status::rs_more, ath5k_rx_status::rs_phyerr, ath5k_rx_status::rs_rate, ath5k_rx_status::rs_rssi, ath5k_rx_status::rs_status, ath5k_rx_status::rs_tstamp, ath5k_hw_all_rx_desc::rx_stat, ath5k_hw_rx_status::rx_status_0, ath5k_hw_rx_status::rx_status_1, ath5k_hw_all_rx_desc::u, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_proc_5212_rx_status()

static int ath5k_hw_proc_5212_rx_status ( struct ath5k_hw *ah  __unused,
struct ath5k_desc desc,
struct ath5k_rx_status rs 
)
static

Definition at line 457 of file ath5k_desc.c.

459 {
460  struct ath5k_hw_rx_status *rx_status;
461  struct ath5k_hw_rx_error *rx_err;
462 
463  rx_status = &desc->ud.ds_rx.u.rx_stat;
464 
465  /* Overlay on error */
466  rx_err = &desc->ud.ds_rx.u.rx_err;
467 
468  /* No frame received / not ready */
469  if (!(rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE))
470  return -EINPROGRESS;
471 
472  /*
473  * Frame receive status
474  */
475  rs->rs_datalen = rx_status->rx_status_0 &
477  rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
479  rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
481  rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
483  rs->rs_more = !!(rx_status->rx_status_0 &
485  rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
487  rs->rs_status = 0;
488  rs->rs_phyerr = 0;
490 
491  /*
492  * Receive/descriptor errors
493  */
494  if (!(rx_status->rx_status_1 &
496  if (rx_status->rx_status_1 &
498  rs->rs_status |= AR5K_RXERR_CRC;
499 
500  if (rx_status->rx_status_1 &
502  rs->rs_status |= AR5K_RXERR_PHY;
505  }
506 
507  if (rx_status->rx_status_1 &
510 
511  if (rx_status->rx_status_1 &
513  rs->rs_status |= AR5K_RXERR_MIC;
514  }
515 
516  return 0;
517 }
#define AR5K_RXERR_PHY
Definition: ath5k.h:580
#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR
Definition: desc.h:92
u32 rx_error_1
Definition: desc.h:105
struct ath5k_hw_rx_error rx_err
Definition: desc.h:132
#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP
Definition: desc.h:96
#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK
Definition: desc.h:88
union ath5k_desc::@18 ud
u16 rs_tstamp
Definition: ath5k.h:569
#define AR5K_RXERR_CRC
Definition: ath5k.h:579
#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR
Definition: desc.h:90
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
struct ath5k_hw_all_rx_desc ds_rx
Definition: desc.h:320
#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR
Definition: desc.h:89
#define AR5K_RXERR_DECRYPT
Definition: ath5k.h:582
#define AR5K_RXKEYIX_INVALID
Definition: ath5k.h:584
#define AR5K_RXERR_MIC
Definition: ath5k.h:583
struct ath5k_hw_rx_error rx_err
Definition: desc.h:305
struct ath5k_hw_rx_status rx_stat
Definition: desc.h:304
#define AR5K_5212_RX_DESC_STATUS0_MORE
Definition: desc.h:77
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE
Definition: desc.h:79
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
union ath5k_hw_all_rx_desc::@16 u
#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN
Definition: desc.h:76
u32 rx_status_0
Definition: desc.h:44
#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR
Definition: desc.h:91
#define AR5K_5212_RX_DESC_STATUS1_DONE
Definition: desc.h:87
u32 rx_status_1
Definition: desc.h:45
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA
Definition: desc.h:83
#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL
Definition: desc.h:81
#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE
Definition: desc.h:112
u16 rs_datalen
Definition: ath5k.h:568

References AR5K_5212_RX_DESC_STATUS0_DATA_LEN, AR5K_5212_RX_DESC_STATUS0_MORE, AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA, AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE, AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL, AR5K_5212_RX_DESC_STATUS1_CRC_ERROR, AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR, AR5K_5212_RX_DESC_STATUS1_DONE, AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK, AR5K_5212_RX_DESC_STATUS1_MIC_ERROR, AR5K_5212_RX_DESC_STATUS1_PHY_ERROR, AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP, AR5K_REG_MS, AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE, AR5K_RXERR_CRC, AR5K_RXERR_DECRYPT, AR5K_RXERR_MIC, AR5K_RXERR_PHY, AR5K_RXKEYIX_INVALID, ath5k_desc::ds_rx, EINPROGRESS, ath5k_rx_status::rs_antenna, ath5k_rx_status::rs_datalen, ath5k_rx_status::rs_keyix, ath5k_rx_status::rs_more, ath5k_rx_status::rs_phyerr, ath5k_rx_status::rs_rate, ath5k_rx_status::rs_rssi, ath5k_rx_status::rs_status, ath5k_rx_status::rs_tstamp, ath5k_hw_all_rx_desc::rx_err, rx_err, ath5k_hw_rx_error::rx_error_1, ath5k_hw_all_rx_desc::rx_stat, ath5k_hw_rx_status::rx_status_0, ath5k_hw_rx_status::rx_status_1, ath5k_hw_all_rx_desc::u, and ath5k_desc::ud.

Referenced by ath5k_hw_init_desc_functions().

◆ ath5k_hw_init_desc_functions()

int ath5k_hw_init_desc_functions ( struct ath5k_hw ah)

Definition at line 522 of file ath5k_desc.c.

523 {
524 
525  if (ah->ah_version != AR5K_AR5210 &&
526  ah->ah_version != AR5K_AR5211 &&
527  ah->ah_version != AR5K_AR5212)
528  return -ENOTSUP;
529 
530  if (ah->ah_version == AR5K_AR5212) {
531  ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
532  ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
533  ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
534  } else {
535  ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
536  ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
537  ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
538  }
539 
540  if (ah->ah_version == AR5K_AR5212)
541  ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
542  else if (ah->ah_version <= AR5K_AR5211)
543  ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
544 
545  return 0;
546 }
static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type, unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0, unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate __unused, unsigned int rtscts_duration)
Definition: ath5k_desc.c:42
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_rx_status *rs)
Definition: ath5k_desc.c:395
static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused, enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0, unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate, unsigned int rtscts_duration)
Definition: ath5k_desc.c:156
static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_rx_status *rs)
Definition: ath5k_desc.c:457
static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_tx_status *ts)
Definition: ath5k_desc.c:304
uint8_t ah
Definition: registers.h:85
static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah __unused, struct ath5k_desc *desc, struct ath5k_tx_status *ts)
Definition: ath5k_desc.c:252
static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah __unused, struct ath5k_desc *desc, u32 size, unsigned int flags)
Definition: ath5k_desc.c:364

References ah, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, ath5k_hw_proc_2word_tx_status(), ath5k_hw_proc_4word_tx_status(), ath5k_hw_proc_5210_rx_status(), ath5k_hw_proc_5212_rx_status(), ath5k_hw_setup_2word_tx_desc(), ath5k_hw_setup_4word_tx_desc(), ath5k_hw_setup_rx_desc(), and ENOTSUP.

Referenced by ath5k_hw_attach().