74 for (i = 1000; i > 0 &&
79 return i ? 0 : -
EBUSY;
423 *interrupt_mask =
data;
435 *interrupt_mask =
data;
552 old_mask =
ah->ah_imr;
621 ah->ah_imr = new_mask;
int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
#define EBUSY
Device or resource busy.
int ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
ath5k_hw_is_intr_pending - Check if we have pending interrupts
u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
#define AR5K_SISR2_CAB_TIMEOUT
#define AR5K_REG_MS(_val, _flags)
#define AR5K_QUIET_CTL2_QT_DUR
ath5k_hw_get_isr - Get interrupt status
uint32_t pending
Pending events.
#define AR5K_REG_WRITE_Q(ah, _reg, _queue)
#define AR5K_QCU_STS_FRMPENDCNT
#define AR5K_SISR3_QCBRURN
#define AR5K_SISR1_QCU_TXEOL
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
#define AR5K_QUIET_CTL2_QT_PER
#define AR5K_ISR_RXDOPPLER
#define AR5K_TUNE_MIN_TX_FIFO_THRES
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
#define AR5K_SISR2_DTIM_SYNC
#define AR5K_SISR1_QCU_TXERR
#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH
int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
ath5k_hw_stop_rx_dma - Stop DMA receive
int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase)
ath5k_hw_update_tx_triglevel - Update tx trigger level
#define ENODEV
No such device.
u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
ath5k_hw_get_rxdp - Get RX Descriptor's address
int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
#define AR5K_IMR_RXDOPPLER
void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
ath5k_hw_start_rx_dma - Start DMA receive
void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
ath5k_hw_set_rxdp - Set RX Descriptor's address
#define AR5K_QUIET_CTL1_QT_EN
#define AR5K_SISR2_QCU_TXURN
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
#define AR5K_QUEUE_STATUS(_q)
#define AR5K_DIAG_SW_5211
int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
#define AR5K_REG_READ_Q(ah, _reg, _queue)
#define AR5K_TXCFG_TXFULL
int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
#define EIO
Input/output error.
uint8_t data[48]
Additional event data.
#define AR5K_SISR2_BCN_TIMEOUT
#define AR5K_QUIET_CTL1_NEXT_QT_TSF
#define AR5K_SISR0_QCU_TXDESC
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
#define AR5K_SISR3_QCBRORN
#define AR5K_QUEUE_TXDP(_q)
#define AR5K_TUNE_MAX_TX_FIFO_THRES
#define AR5K_TSF_L32_5211
enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
ath5k_hw_set_imr - Set interrupt mask
#define AR5K_SIMR2_QCU_TXURN
struct bofm_section_header done
ath5k_int
enum ath5k_int - Hardware interrupt masks helpers
#define AR5K_SISR0_QCU_TXOK
if(natsemi->flags &NATSEMI_64BIT) return 1
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
#define AR5K_REG_SM(_val, _flags)