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Functions | |
FILE_LICENCE (MIT) | |
void | ath5k_hw_start_rx_dma (struct ath5k_hw *ah) |
ath5k_hw_start_rx_dma - Start DMA receive More... | |
int | ath5k_hw_stop_rx_dma (struct ath5k_hw *ah) |
ath5k_hw_stop_rx_dma - Stop DMA receive More... | |
u32 | ath5k_hw_get_rxdp (struct ath5k_hw *ah) |
ath5k_hw_get_rxdp - Get RX Descriptor's address More... | |
void | ath5k_hw_set_rxdp (struct ath5k_hw *ah, u32 phys_addr) |
ath5k_hw_set_rxdp - Set RX Descriptor's address More... | |
int | ath5k_hw_start_tx_dma (struct ath5k_hw *ah, unsigned int queue) |
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue More... | |
int | ath5k_hw_stop_tx_dma (struct ath5k_hw *ah, unsigned int queue) |
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue More... | |
u32 | ath5k_hw_get_txdp (struct ath5k_hw *ah, unsigned int queue) |
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue More... | |
int | ath5k_hw_set_txdp (struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) |
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue More... | |
int | ath5k_hw_update_tx_triglevel (struct ath5k_hw *ah, int increase) |
ath5k_hw_update_tx_triglevel - Update tx trigger level More... | |
int | ath5k_hw_is_intr_pending (struct ath5k_hw *ah) |
ath5k_hw_is_intr_pending - Check if we have pending interrupts More... | |
int | ath5k_hw_get_isr (struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) |
enum ath5k_int | ath5k_hw_set_imr (struct ath5k_hw *ah, enum ath5k_int new_mask) |
ath5k_hw_set_imr - Set interrupt mask More... | |
FILE_LICENCE | ( | MIT | ) |
void ath5k_hw_start_rx_dma | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_start_rx_dma - Start DMA receive
@ah: The &struct ath5k_hw
Definition at line 54 of file ath5k_dma.c.
References ah, AR5K_CR, AR5K_CR_RXE, ath5k_hw_reg_read(), and ath5k_hw_reg_write().
Referenced by ath5k_rx_start().
int ath5k_hw_stop_rx_dma | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_stop_rx_dma - Stop DMA receive
@ah: The &struct ath5k_hw
Definition at line 65 of file ath5k_dma.c.
References ah, AR5K_CR, AR5K_CR_RXD, AR5K_CR_RXE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, and udelay().
Referenced by ath5k_rx_stop().
ath5k_hw_get_rxdp - Get RX Descriptor's address
@ah: The &struct ath5k_hw
XXX: Is RXDP read and clear ?
Definition at line 89 of file ath5k_dma.c.
References ah, AR5K_RXDP, and ath5k_hw_reg_read().
ath5k_hw_set_rxdp - Set RX Descriptor's address
@ah: The &struct ath5k_hw @phys_addr: RX descriptor address
XXX: Should we check if rx is enabled before setting rxdp ?
Definition at line 102 of file ath5k_dma.c.
References ah, AR5K_RXDP, and ath5k_hw_reg_write().
Referenced by ath5k_rx_start().
int ath5k_hw_start_tx_dma | ( | struct ath5k_hw * | ah, |
unsigned int | queue | ||
) |
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Start DMA transmit for a specific queue and since 5210 doesn't have QCU/DCU, set up queue parameters for 5210 here based on queue type (one queue for normal data and one queue for beacons). For queue setup on newer chips check out qcu.c. Returns -EINVAL if queue number is out of range or if queue is already disabled.
NOTE: Must be called after setting up tx control descriptor for that queue (see below).
Definition at line 127 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_QCU_TXD, AR5K_QCU_TXE, AR5K_REG_READ_Q, AR5K_REG_WRITE_Q, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EIO, and queue.
Referenced by ath5k_txbuf_setup().
int ath5k_hw_stop_tx_dma | ( | struct ath5k_hw * | ah, |
unsigned int | queue | ||
) |
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Stop DMA transmit on a specific hw queue and drain queue so we don't have any pending frames. Returns -EBUSY if we still have pending frames, -EINVAL if queue number is out of range.
Definition at line 167 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_CHANEL_IDLE_HIGH, AR5K_QCU_STS_FRMPENDCNT, AR5K_QCU_TXD, AR5K_QUEUE_STATUS, AR5K_QUIET_CTL1, AR5K_QUIET_CTL1_NEXT_QT_TSF, AR5K_QUIET_CTL1_QT_EN, AR5K_QUIET_CTL2, AR5K_QUIET_CTL2_QT_DUR, AR5K_QUIET_CTL2_QT_PER, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SREV_AR2414, AR5K_TSF_L32_5211, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, EIO, pending, queue, and udelay().
Referenced by ath5k_txq_cleanup().
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Get TX descriptor's address for a specific queue. For 5210 we ignore the queue number and use tx queue type since we only have 2 queues. We use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just read the corresponding TXDP register.
XXX: Is TXDP read and clear ?
Definition at line 261 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QUEUE_TXDP, ath5k_hw_reg_read(), and queue.
Referenced by ath5k_txq_cleanup().
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
@ah: The &struct ath5k_hw @queue: The hw queue number
Set TX descriptor's address for a specific queue. For 5210 we ignore the queue number and we use tx queue type since we only have 2 queues so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just set the corresponding TXDP register. Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still active.
Definition at line 292 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QCU_TXE, AR5K_QUEUE_TXDP, AR5K_REG_READ_Q, ath5k_hw_reg_write(), EIO, and queue.
Referenced by ath5k_txbuf_setup().
int ath5k_hw_update_tx_triglevel | ( | struct ath5k_hw * | ah, |
int | increase | ||
) |
ath5k_hw_update_tx_triglevel - Update tx trigger level
@ah: The &struct ath5k_hw @increase: Flag to force increase of trigger level
This function increases/decreases the tx trigger level for the tx fifo buffer (aka FIFO threshold) that is used to indicate when PCU flushes the buffer and transmits it's data. Lowering this results sending small frames more quickly but can lead to tx underruns, raising it a lot can result other problems (i think bmiss is related). Right now we start with the lowest possible (64Bytes) and if we get tx underrun we increase it using the increase flag. Returns -EIO if we have have reached maximum/minimum.
XXX: Link this with tx DMA size ? XXX: Use it to save interrupts ? TODO: Needs testing, i think it's related to bmiss...
Definition at line 339 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_INT_GLOBAL, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TRIG_LVL, AR5K_TUNE_MAX_TX_FIFO_THRES, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_TXCFG, AR5K_TXCFG_TXFULL, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_set_imr(), done, EIO, and imr.
Referenced by ath5k_poll().
int ath5k_hw_is_intr_pending | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_is_intr_pending - Check if we have pending interrupts
@ah: The &struct ath5k_hw
Check if we have pending interrupts to process. Returns 1 if we have pending interrupts and 0 if we haven't.
Definition at line 391 of file ath5k_dma.c.
References ah, AR5K_INTPEND, and ath5k_hw_reg_read().
Referenced by ath5k_poll().
Definition at line 412 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_NOCARD, AR5K_INT_QCBRORN, AR5K_INT_QCBRURN, AR5K_INT_QTRIG, AR5K_INT_RX_DOPPLER, AR5K_INT_TIM, AR5K_ISR, AR5K_ISR_BCNMISC, AR5K_ISR_BNR, AR5K_ISR_DPERR, AR5K_ISR_HIUERR, AR5K_ISR_MCABT, AR5K_ISR_QCBRORN, AR5K_ISR_QCBRURN, AR5K_ISR_QTRIG, AR5K_ISR_RXDOPPLER, AR5K_ISR_SSERR, AR5K_ISR_TIM, AR5K_ISR_TXDESC, AR5K_ISR_TXEOL, AR5K_ISR_TXERR, AR5K_ISR_TXOK, AR5K_ISR_TXURN, AR5K_RAC_PISR, AR5K_RAC_SISR0, AR5K_RAC_SISR1, AR5K_RAC_SISR2, AR5K_RAC_SISR3, AR5K_RAC_SISR4, AR5K_REG_MS, AR5K_SISR0_QCU_TXDESC, AR5K_SISR0_QCU_TXOK, AR5K_SISR1_QCU_TXEOL, AR5K_SISR1_QCU_TXERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DPERR, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_MCABT, AR5K_SISR2_QCU_TXURN, AR5K_SISR2_SSERR, AR5K_SISR2_TIM, AR5K_SISR3_QCBRORN, AR5K_SISR3_QCBRURN, AR5K_SISR4_QTRIG, ath5k_hw_reg_read(), data, ENODEV, and if().
Referenced by ath5k_poll().
ath5k_hw_set_imr - Set interrupt mask
@ah: The &struct ath5k_hw @new_mask: The new interrupt mask to be set
Set the interrupt mask in hw to save interrupts. We do that by mapping ath5k_int bits to hw-specific bits to remove abstraction and writing Interrupt Mask Register.
Definition at line 548 of file ath5k_dma.c.
References ah, AR5K_AR5210, AR5K_IER, AR5K_IER_DISABLE, AR5K_IMR, AR5K_IMR_DPERR, AR5K_IMR_HIUERR, AR5K_IMR_MCABT, AR5K_IMR_RXDOPPLER, AR5K_IMR_SSERR, AR5K_IMR_TIM, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_GLOBAL, AR5K_INT_RX_DOPPLER, AR5K_INT_RXNOFRM, AR5K_INT_TIM, AR5K_PIMR, AR5K_RXNOFRM, AR5K_SIMR2, AR5K_SIMR2_DPERR, AR5K_SIMR2_MCABT, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR2_SSERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_TIM, ath5k_hw_reg_read(), and ath5k_hw_reg_write().
Referenced by ath5k_hw_reset(), ath5k_hw_update_tx_triglevel(), ath5k_irq(), ath5k_reset(), and ath5k_stop_hw().