iPXE
eepro.c
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1 #ifdef ALLMULTI
2 #error multicast support is not yet implemented
3 #endif
4 /**************************************************************************
5 Etherboot - BOOTP/TFTP Bootstrap Program
6 Intel EEPRO/10 NIC driver for Etherboot
7 Adapted from Linux eepro.c from kernel 2.2.17
8 
9 This board accepts a 32 pin EEPROM (29C256), however a test with a
10 27C010 shows that this EPROM also works in the socket, but it's not clear
11 how repeatably. The two top address pins appear to be held low, thus
12 the bottom 32kB of the 27C010 is visible in the CPU's address space.
13 To be sure you could put 4 copies of the code in the 27C010, then
14 it doesn't matter whether the extra lines are held low or high, just
15 hopefully not floating as CMOS chips don't like floating inputs.
16 
17 Be careful with seating the EPROM as the socket on my board actually
18 has 34 pins, the top row of 2 are not used.
19 ***************************************************************************/
20 
21 /*
22 
23  timlegge 2005-05-18 remove the relocation changes cards that
24  write directly to the hardware don't need it
25 */
26 
27 /*
28  * This program is free software; you can redistribute it and/or
29  * modify it under the terms of the GNU General Public License as
30  * published by the Free Software Foundation; either version 2 of the
31  * License, or (at your option) any later version.
32  *
33  * This program is distributed in the hope that it will be useful, but
34  * WITHOUT ANY WARRANTY; without even the implied warranty of
35  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
36  * General Public License for more details.
37  *
38  * You should have received a copy of the GNU General Public License
39  * along with this program; if not, write to the Free Software
40  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
41  * 02110-1301, USA.
42  */
43 
44 FILE_LICENCE ( GPL2_OR_LATER );
45 
46 #include "etherboot.h"
47 #include <errno.h>
48 #include "nic.h"
49 #include <ipxe/isa.h>
50 #include <ipxe/ethernet.h>
51 
52 /* Different 82595 chips */
53 #define LAN595 0
54 #define LAN595TX 1
55 #define LAN595FX 2
56 #define LAN595FX_10ISA 3
57 
58 #define SLOW_DOWN inb(0x80);
59 
60 /* The station (ethernet) address prefix, used for IDing the board. */
61 #define SA_ADDR0 0x00 /* Etherexpress Pro/10 */
62 #define SA_ADDR1 0xaa
63 #define SA_ADDR2 0x00
64 
65 #define GetBit(x,y) ((x & (1<<y))>>y)
66 
67 /* EEPROM Word 0: */
68 #define ee_PnP 0 /* Plug 'n Play enable bit */
69 #define ee_Word1 1 /* Word 1? */
70 #define ee_BusWidth 2 /* 8/16 bit */
71 #define ee_FlashAddr 3 /* Flash Address */
72 #define ee_FlashMask 0x7 /* Mask */
73 #define ee_AutoIO 6 /* */
74 #define ee_reserved0 7 /* =0! */
75 #define ee_Flash 8 /* Flash there? */
76 #define ee_AutoNeg 9 /* Auto Negotiation enabled? */
77 #define ee_IO0 10 /* IO Address LSB */
78 #define ee_IO0Mask 0x /*...*/
79 #define ee_IO1 15 /* IO MSB */
80 
81 /* EEPROM Word 1: */
82 #define ee_IntSel 0 /* Interrupt */
83 #define ee_IntMask 0x7
84 #define ee_LI 3 /* Link Integrity 0= enabled */
85 #define ee_PC 4 /* Polarity Correction 0= enabled */
86 #define ee_TPE_AUI 5 /* PortSelection 1=TPE */
87 #define ee_Jabber 6 /* Jabber prevention 0= enabled */
88 #define ee_AutoPort 7 /* Auto Port Selection 1= Disabled */
89 #define ee_SMOUT 8 /* SMout Pin Control 0= Input */
90 #define ee_PROM 9 /* Flash EPROM / PROM 0=Flash */
91 #define ee_reserved1 10 /* .. 12 =0! */
92 #define ee_AltReady 13 /* Alternate Ready, 0=normal */
93 #define ee_reserved2 14 /* =0! */
94 #define ee_Duplex 15
95 
96 /* Word2,3,4: */
97 #define ee_IA5 0 /*bit start for individual Addr Byte 5 */
98 #define ee_IA4 8 /*bit start for individual Addr Byte 5 */
99 #define ee_IA3 0 /*bit start for individual Addr Byte 5 */
100 #define ee_IA2 8 /*bit start for individual Addr Byte 5 */
101 #define ee_IA1 0 /*bit start for individual Addr Byte 5 */
102 #define ee_IA0 8 /*bit start for individual Addr Byte 5 */
103 
104 /* Word 5: */
105 #define ee_BNC_TPE 0 /* 0=TPE */
106 #define ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */
107 #define ee_BootTypeMask 0x3
108 #define ee_NumConn 3 /* Number of Connections 0= One or Two */
109 #define ee_FlashSock 4 /* Presence of Flash Socket 0= Present */
110 #define ee_PortTPE 5
111 #define ee_PortBNC 6
112 #define ee_PortAUI 7
113 #define ee_PowerMgt 10 /* 0= disabled */
114 #define ee_CP 13 /* Concurrent Processing */
115 #define ee_CPMask 0x7
116 
117 /* Word 6: */
118 #define ee_Stepping 0 /* Stepping info */
119 #define ee_StepMask 0x0F
120 #define ee_BoardID 4 /* Manucaturer Board ID, reserved */
121 #define ee_BoardMask 0x0FFF
122 
123 /* Word 7: */
124 #define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */
125 #define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */
126 
127 /*..*/
128 #define ee_SIZE 0x40 /* total EEprom Size */
129 #define ee_Checksum 0xBABA /* initial and final value for adding checksum */
130 
131 
132 /* Card identification via EEprom: */
133 #define ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */
134 #define ee_addr_id 0x11 /* Word offset for Card ID */
135 #define ee_addr_SN 0x12 /* Serial Number */
136 #define ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */
137 
138 
139 #define ee_vendor_intel0 0x25 /* Vendor ID Intel */
140 #define ee_vendor_intel1 0xD4
141 #define ee_id_eepro10p0 0x10 /* ID for eepro/10+ */
142 #define ee_id_eepro10p1 0x31
143 
144 /* now this section could be used by both boards: the oldies and the ee10:
145  * ee10 uses tx buffer before of rx buffer and the oldies the inverse.
146  * (aris)
147  */
148 #define RAM_SIZE 0x8000
149 
150 #define RCV_HEADER 8
151 #define RCV_DEFAULT_RAM 0x6000
152 #define RCV_RAM rcv_ram
153 
154 static unsigned rcv_ram = RCV_DEFAULT_RAM;
155 
156 #define XMT_HEADER 8
157 #define XMT_RAM (RAM_SIZE - RCV_RAM)
158 
159 #define XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE)
160 
161 #define RCV_LOWER_LIMIT (rcv_start >> 8)
162 #define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8)
163 #define XMT_LOWER_LIMIT (XMT_START >> 8)
164 #define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8)
165 
166 #define RCV_START_PRO 0x00
167 #define RCV_START_10 XMT_RAM
168  /* by default the old driver */
169 static unsigned rcv_start = RCV_START_PRO;
170 
171 #define RCV_DONE 0x0008
172 #define RX_OK 0x2000
173 #define RX_ERROR 0x0d81
174 
175 #define TX_DONE_BIT 0x0080
176 #define CHAIN_BIT 0x8000
177 #define XMT_STATUS 0x02
178 #define XMT_CHAIN 0x04
179 #define XMT_COUNT 0x06
180 
181 #define BANK0_SELECT 0x00
182 #define BANK1_SELECT 0x40
183 #define BANK2_SELECT 0x80
184 
185 /* Bank 0 registers */
186 #define COMMAND_REG 0x00 /* Register 0 */
187 #define MC_SETUP 0x03
188 #define XMT_CMD 0x04
189 #define DIAGNOSE_CMD 0x07
190 #define RCV_ENABLE_CMD 0x08
191 #define RCV_DISABLE_CMD 0x0a
192 #define STOP_RCV_CMD 0x0b
193 #define RESET_CMD 0x0e
194 #define POWER_DOWN_CMD 0x18
195 #define RESUME_XMT_CMD 0x1c
196 #define SEL_RESET_CMD 0x1e
197 #define STATUS_REG 0x01 /* Register 1 */
198 #define RX_INT 0x02
199 #define TX_INT 0x04
200 #define EXEC_STATUS 0x30
201 #define ID_REG 0x02 /* Register 2 */
202 #define R_ROBIN_BITS 0xc0 /* round robin counter */
203 #define ID_REG_MASK 0x2c
204 #define ID_REG_SIG 0x24
205 #define AUTO_ENABLE 0x10
206 #define INT_MASK_REG 0x03 /* Register 3 */
207 #define RX_STOP_MASK 0x01
208 #define RX_MASK 0x02
209 #define TX_MASK 0x04
210 #define EXEC_MASK 0x08
211 #define ALL_MASK 0x0f
212 #define IO_32_BIT 0x10
213 #define RCV_BAR 0x04 /* The following are word (16-bit) registers */
214 #define RCV_STOP 0x06
215 
216 #define XMT_BAR_PRO 0x0a
217 #define XMT_BAR_10 0x0b
218 static unsigned xmt_bar = XMT_BAR_PRO;
219 
220 #define HOST_ADDRESS_REG 0x0c
221 #define IO_PORT 0x0e
222 #define IO_PORT_32_BIT 0x0c
223 
224 /* Bank 1 registers */
225 #define REG1 0x01
226 #define WORD_WIDTH 0x02
227 #define INT_ENABLE 0x80
228 #define INT_NO_REG 0x02
229 #define RCV_LOWER_LIMIT_REG 0x08
230 #define RCV_UPPER_LIMIT_REG 0x09
231 
232 #define XMT_LOWER_LIMIT_REG_PRO 0x0a
233 #define XMT_UPPER_LIMIT_REG_PRO 0x0b
234 #define XMT_LOWER_LIMIT_REG_10 0x0b
235 #define XMT_UPPER_LIMIT_REG_10 0x0a
238 
239 /* Bank 2 registers */
240 #define XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */
241 #define XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */
242 #define RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */
243 #define REG2 0x02
244 #define PRMSC_Mode 0x01
245 #define Multi_IA 0x20
246 #define REG3 0x03
247 #define TPE_BIT 0x04
248 #define BNC_BIT 0x20
249 #define REG13 0x0d
250 #define FDX 0x00
251 #define A_N_ENABLE 0x02
252 
253 #define I_ADD_REG0 0x04
254 #define I_ADD_REG1 0x05
255 #define I_ADD_REG2 0x06
256 #define I_ADD_REG3 0x07
257 #define I_ADD_REG4 0x08
258 #define I_ADD_REG5 0x09
259 
260 #define EEPROM_REG_PRO 0x0a
261 #define EEPROM_REG_10 0x0b
262 static unsigned eeprom_reg = EEPROM_REG_PRO;
263 
264 #define EESK 0x01
265 #define EECS 0x02
266 #define EEDI 0x04
267 #define EEDO 0x08
268 
269 /* The horrible routine to read a word from the serial EEPROM. */
270 /* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */
271 
272 /* The delay between EEPROM clock transitions. */
273 #define eeprom_delay() { udelay(40); }
274 #define EE_READ_CMD (6 << 6)
275 
276 /* do a full reset; data sheet asks for 250us delay */
277 #define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(255);
278 
279 /* do a nice reset */
280 #define eepro_sel_reset(ioaddr) \
281  do { \
282  outb ( SEL_RESET_CMD, ioaddr ); \
283  (void) SLOW_DOWN; \
284  (void) SLOW_DOWN; \
285  } while (0)
286 
287 /* clear all interrupts */
288 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
289 
290 /* enable rx */
291 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)
292 
293 /* disable rx */
294 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)
295 
296 /* switch bank */
297 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
298 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
299 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
300 
301 static unsigned int rx_start, tx_start;
302 static int tx_last;
303 static unsigned int tx_end;
304 static int eepro = 0;
305 static unsigned int mem_start, mem_end = RCV_DEFAULT_RAM / 1024;
306 
307 /**************************************************************************
308 RESET - Reset adapter
309 ***************************************************************************/
310 static void eepro_reset(struct nic *nic)
311 {
312  int temp_reg, i;
313 
314  /* put the card in its initial state */
315  eepro_sw2bank2(nic->ioaddr); /* be careful, bank2 now */
316  temp_reg = inb(nic->ioaddr + eeprom_reg);
317  DBG("Stepping %d\n", temp_reg >> 5);
318  if (temp_reg & 0x10) /* check the TurnOff Enable bit */
319  outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg);
320  for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */
321  outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i);
322  temp_reg = inb(nic->ioaddr + REG1);
323  /* setup Transmit Chaining and discard bad RCV frames */
326  temp_reg = inb(nic->ioaddr + REG2); /* match broadcast */
327  outb(temp_reg | 0x14, nic->ioaddr + REG2);
328  temp_reg = inb(nic->ioaddr + REG3);
329  outb(temp_reg & 0x3F, nic->ioaddr + REG3); /* clear test mode */
330  /* set the receiving mode */
331  eepro_sw2bank1(nic->ioaddr); /* be careful, bank1 now */
332  /* initialise the RCV and XMT upper and lower limits */
337  eepro_sw2bank0(nic->ioaddr); /* Switch back to bank 0 */
339  /* Initialise RCV */
341  outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
342  /* Make sure 1st poll won't find a valid packet header */
344  outw(0, nic->ioaddr + IO_PORT);
345  /* Intialise XMT */
346  outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
348  tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8);
349  tx_last = 0;
351 }
352 
353 /**************************************************************************
354 POLL - Wait for a frame
355 ***************************************************************************/
356 static int eepro_poll(struct nic *nic, int retrieve)
357 {
358  unsigned int rcv_car = rx_start;
359  unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size;
360 
361  /* return true if there's an ethernet packet ready to read */
362  /* nic->packet should contain data on return */
363  /* nic->packetlen should contain length of data */
364 #if 0
365  if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0)
366  return (0);
367  outb(0x40, nic->ioaddr + STATUS_REG);
368 #endif
369  outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG);
370  rcv_event = inw(nic->ioaddr + IO_PORT);
371  if (rcv_event != RCV_DONE)
372  return (0);
373 
374  /* FIXME: I'm guessing this might not work with this card, since
375  it looks like once a rcv_event is started it must be completed.
376  maybe there's another way. */
377  if ( ! retrieve ) return 1;
378 
379  rcv_status = inw(nic->ioaddr + IO_PORT);
380  rcv_next_frame = inw(nic->ioaddr + IO_PORT);
381  rcv_size = inw(nic->ioaddr + IO_PORT);
382 #if 0
383  printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
384  inb(nic->ioaddr + STATUS_REG));
385 #endif
386  if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) {
387  printf("Receive error %hX\n", rcv_status);
388  return (0);
389  }
390  rcv_size &= 0x3FFF;
391  insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
392 #if 0
393 {
394  int i;
395  for (i = 0; i < 48; i++) {
396  printf("%hhX", nic->packet[i]);
397  putchar(i % 16 == 15 ? '\n' : ' ');
398  }
399 }
400 #endif
401  nic->packetlen = rcv_size;
402  rcv_car = (rx_start + RCV_HEADER + rcv_size);
403  rx_start = rcv_next_frame;
404 /*
405  hex_dump(rcv_car, nic->packetlen);
406 */
407 
408  if (rcv_car == 0)
409  rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
410  outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
411  return (1);
412 }
413 
414 /**************************************************************************
415 TRANSMIT - Transmit a frame
416 ***************************************************************************/
417 static void eepro_transmit(
418  struct nic *nic,
419  const char *d, /* Destination */
420  unsigned int t, /* Type */
421  unsigned int s, /* size */
422  const char *p) /* Packet */
423 {
424  unsigned int status, tx_available, last, end, length;
425  unsigned short type;
426  int boguscount = 20;
427 
428  length = s + ETH_HLEN;
429  if (tx_end > tx_start)
430  tx_available = XMT_RAM - (tx_end - tx_start);
431  else if (tx_end < tx_start)
432  tx_available = tx_start - tx_end;
433  else
434  tx_available = XMT_RAM;
435  assert ( length <= tx_available );
436  last = tx_end;
437  end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
438  if (end >= (XMT_UPPER_LIMIT << 8)) {
439  last = (XMT_LOWER_LIMIT << 8);
440  end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
441  }
444  outw(0, nic->ioaddr + IO_PORT);
445  outw(end, nic->ioaddr + IO_PORT);
447  outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2);
449  type = htons(t);
450  outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2);
451  outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1);
452  /* A dummy read to flush the DRAM write pipeline */
453  status = inw(nic->ioaddr + IO_PORT);
454  outw(last, nic->ioaddr + xmt_bar);
455  outb(XMT_CMD, nic->ioaddr);
456  tx_start = last;
457  tx_last = last;
458  tx_end = end;
459 #if 0
460  printf("%d %d\n", tx_start, tx_end);
461 #endif
462  while (boguscount > 0) {
463  if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
464  udelay(40);
465  boguscount--;
466  continue;
467  }
468  if ((status & 0x2000) == 0) {
469  DBG("Transmit status %hX\n", status);
470  }
471  }
472 }
473 
474 /**************************************************************************
475 DISABLE - Turn off ethernet interface
476 ***************************************************************************/
477 static void eepro_disable ( struct nic *nic, struct isa_device *isa __unused ) {
478  eepro_sw2bank0(nic->ioaddr); /* Switch to bank 0 */
479  /* Flush the Tx and disable Rx */
481  tx_start = tx_end = (XMT_LOWER_LIMIT << 8);
482  tx_last = 0;
483  /* Reset the 82595 */
485 }
486 
487 /**************************************************************************
488 DISABLE - Enable, Disable, or Force interrupts
489 ***************************************************************************/
490 static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused)
491 {
492  switch ( action ) {
493  case DISABLE :
494  break;
495  case ENABLE :
496  break;
497  case FORCE :
498  break;
499  }
500 }
501 
502 static int read_eeprom(uint16_t ioaddr, int location)
503 {
504  int i;
505  unsigned short retval = 0;
506  int ee_addr = ioaddr + eeprom_reg;
507  int read_cmd = location | EE_READ_CMD;
508  int ctrl_val = EECS;
509 
510  if (eepro == LAN595FX_10ISA) {
512  outb(0x00, ioaddr + STATUS_REG);
513  }
515  outb(ctrl_val, ee_addr);
516  /* shift the read command bits out */
517  for (i = 8; i >= 0; i--) {
518  short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
519  outb(outval, ee_addr);
520  outb(outval | EESK, ee_addr); /* EEPROM clock tick */
521  eeprom_delay();
522  outb(outval, ee_addr); /* finish EEPROM clock tick */
523  eeprom_delay();
524  }
525  outb(ctrl_val, ee_addr);
526  for (i = 16; i > 0; i--) {
527  outb(ctrl_val | EESK, ee_addr);
528  eeprom_delay();
529  retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
530  outb(ctrl_val, ee_addr);
531  eeprom_delay();
532  }
533  /* terminate the EEPROM access */
534  ctrl_val &= ~EECS;
535  outb(ctrl_val | EESK, ee_addr);
536  eeprom_delay();
537  outb(ctrl_val, ee_addr);
538  eeprom_delay();
540  return (retval);
541 }
542 
544  int id, counter;
545 
546  id = inb(ioaddr + ID_REG);
547  if ((id & ID_REG_MASK) != ID_REG_SIG)
548  return (0);
549  counter = id & R_ROBIN_BITS;
550  if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
551  return (0);
552  /* yes the 82595 has been found */
553  return (1);
554 }
555 
558  .poll = eepro_poll,
559  .transmit = eepro_transmit,
560  .irq = eepro_irq,
561 
562 };
563 
564 /**************************************************************************
565 PROBE - Look for an adapter, this routine's visible to the outside
566 ***************************************************************************/
567 static int eepro_probe ( struct nic *nic, struct isa_device *isa ) {
568 
569  int i, l_eepro = 0;
570  union {
571  unsigned char caddr[ETH_ALEN];
572  unsigned short saddr[ETH_ALEN/2];
573  } station_addr;
574  const char *name;
575 
576  nic->irqno = 0;
577  nic->ioaddr = isa->ioaddr;
578 
579  station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
580  if ( ( station_addr.saddr[2] == 0x0000 ) ||
581  ( station_addr.saddr[2] == 0xFFFF ) ) {
582  l_eepro = 3;
588  station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
589  }
590  station_addr.saddr[1] = read_eeprom(nic->ioaddr,3);
591  station_addr.saddr[0] = read_eeprom(nic->ioaddr,4);
592  if (l_eepro)
593  name = "Intel EtherExpress 10 ISA";
594  else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) {
595  name = "Intel EtherExpress Pro/10+ ISA";
596  l_eepro = 2;
597  } else if (station_addr.saddr[0] == SA_ADDR1) {
598  name = "Intel EtherExpress Pro/10 ISA";
599  l_eepro = 1;
600  } else {
601  l_eepro = 0;
602  name = "Intel 82595-based LAN card";
603  }
604  station_addr.saddr[0] = bswap_16(station_addr.saddr[0]);
605  station_addr.saddr[1] = bswap_16(station_addr.saddr[1]);
606  station_addr.saddr[2] = bswap_16(station_addr.saddr[2]);
607  for (i = 0; i < ETH_ALEN; i++) {
608  nic->node_addr[i] = station_addr.caddr[i];
609  }
610 
611  DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) );
612 
613  mem_start = RCV_LOWER_LIMIT << 8;
614  if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29)
615  mem_end = RCV_UPPER_LIMIT << 8;
616  else {
617  mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
618  rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
619  }
620  printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
621  GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP");
622 
623  eepro_reset(nic);
624 
625  /* point to NIC specific routines */
627  return 1;
628 }
629 
631  0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360,
632 };
633 
634 ISA_DRIVER ( eepro_driver, eepro_probe_addrs, eepro_probe1,
635  GENERIC_ISAPNP_VENDOR, 0x828a );
636 
637 DRIVER ( "eepro", nic_driver, isa_driver, eepro_driver,
639 
640 ISA_ROM ( "eepro", "Intel Etherexpress Pro/10" );
641 
642 /*
643  * Local variables:
644  * c-basic-offset: 8
645  * c-indent-level: 8
646  * tab-width: 8
647  * End:
648  */
unsigned char irqno
Definition: nic.h:56
uint16_t length
Length.
Definition: intel.h:14
#define XMT_LOWER_LIMIT_REG_10
Definition: eepro.c:234
Definition: nic.h:35
#define eepro_sel_reset(ioaddr)
Definition: eepro.c:280
#define ee_BNC_TPE
Definition: eepro.c:105
const char * name
Definition: ath9k_hw.c:1984
unsigned short uint16_t
Definition: stdint.h:11
uint16_t ioaddr
I/O address.
Definition: isa.h:16
An ISA device.
Definition: isa.h:12
ISA_ROM("eepro", "Intel Etherexpress Pro/10")
#define XMT_LOWER_LIMIT_REG_PRO
Definition: eepro.c:232
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
static unsigned int rx_start
Definition: eepro.c:301
#define outw(data, io_addr)
Definition: io.h:319
Error codes.
uint8_t type
Type.
Definition: ena.h:16
static int read_eeprom(uint16_t ioaddr, int location)
Definition: eepro.c:502
#define eepro_sw2bank2(ioaddr)
Definition: eepro.c:299
void outsw(volatile uint16_t *io_addr, const uint16_t *data, unsigned int count)
Write 16-bit words to I/O-mapped device.
static int tx_last
Definition: eepro.c:302
static void eepro_irq(struct nic *nic __unused, irq_action_t action __unused)
Definition: eepro.c:490
void putchar(int character)
Write a single character to each console device.
Definition: console.c:27
static unsigned eeprom_reg
Definition: eepro.c:262
#define ee_FX_INT2IRQ
Definition: eepro.c:125
#define XMT_Chain_Int
Definition: eepro.c:240
static struct nic_operations eepro_operations
Definition: eepro.c:556
static int eepro_probe(struct nic *nic, struct isa_device *isa)
Definition: eepro.c:567
#define EEPROM_REG_PRO
Definition: eepro.c:260
#define LAN595FX_10ISA
Definition: eepro.c:56
static int eepro_probe1(isa_probe_addr_t ioaddr)
Definition: eepro.c:543
#define RCV_START_10
Definition: eepro.c:167
#define SA_ADDR1
Definition: eepro.c:62
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
#define XMT_CMD
Definition: eepro.c:188
static unsigned int mem_start
Definition: eepro.c:305
#define I_ADD_REG0
Definition: eepro.c:253
#define ID_REG
Definition: eepro.c:201
static unsigned xmt_upper_limit_reg
Definition: eepro.c:237
#define RCV_START_PRO
Definition: eepro.c:166
uint8_t status
Status.
Definition: ena.h:16
#define EEDO
Definition: eepro.c:267
static unsigned long ioaddr
Definition: davicom.c:129
unsigned int ioaddr
Definition: nic.h:55
static unsigned rcv_start
Definition: eepro.c:169
#define ETH_HLEN
Definition: if_ether.h:9
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define EEDI
Definition: eepro.c:266
Ethernet protocol.
#define REG1
Definition: eepro.c:225
#define XMT_BAR_PRO
Definition: eepro.c:216
#define GetBit(x, y)
Definition: eepro.c:65
#define bswap_16(value)
Definition: byteswap.h:58
uint16_t isa_probe_addr_t
Definition: isa.h:31
#define GENERIC_ISAPNP_VENDOR
Definition: isa_ids.h:38
#define ID_REG_SIG
Definition: eepro.c:204
static unsigned int mem_end
Definition: eepro.c:305
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
irq_action_t
Definition: nic.h:34
#define EECS
Definition: eepro.c:265
DRIVER("eepro", nic_driver, isa_driver, eepro_driver, eepro_probe, eepro_disable)
uint8_t id
Request identifier.
Definition: ena.h:12
ISA_DRIVER(eepro_driver, eepro_probe_addrs, eepro_probe1, GENERIC_ISAPNP_VENDOR, 0x828a)
unsigned int packetlen
Definition: nic.h:54
#define XMT_Chain_ErrStop
Definition: eepro.c:241
#define XMT_HEADER
Definition: eepro.c:156
#define RX_OK
Definition: eepro.c:172
static int eepro
Definition: eepro.c:304
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
#define REG2
Definition: eepro.c:243
#define RCV_DEFAULT_RAM
Definition: eepro.c:151
#define XMT_UPPER_LIMIT_REG_PRO
Definition: eepro.c:233
#define R_ROBIN_BITS
Definition: eepro.c:202
static unsigned xmt_lower_limit_reg
Definition: eepro.c:236
#define eepro_sw2bank0(ioaddr)
Definition: eepro.c:297
#define RCV_LOWER_LIMIT
Definition: eepro.c:161
void insw(volatile uint16_t *io_addr, uint16_t *data, unsigned int count)
Read 16-bit words from I/O-mapped device.
#define RCV_BAR
Definition: eepro.c:213
static void eepro_reset(struct nic *nic)
Definition: eepro.c:310
uint8_t inb(volatile uint8_t *io_addr)
Read byte from I/O-mapped device.
#define ETH_ALEN
Definition: if_ether.h:8
#define STATUS_REG
Definition: eepro.c:197
#define IO_PORT
Definition: eepro.c:221
uint32_t last
Length to read in last segment, or zero.
Definition: pccrc.h:30
Definition: nic.h:37
#define eepro_sw2bank1(ioaddr)
Definition: eepro.c:298
Definition: nic.h:49
static unsigned xmt_bar
Definition: eepro.c:218
#define STOP_RCV_CMD
Definition: eepro.c:192
#define XMT_UPPER_LIMIT_REG_10
Definition: eepro.c:235
unsigned long retval
Definition: xen.h:45
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define RCV_DONE
Definition: eepro.c:171
static isa_probe_addr_t eepro_probe_addrs[]
Definition: eepro.c:630
Definition: nic.h:36
#define RX_ERROR
Definition: eepro.c:173
unsigned char * packet
Definition: nic.h:53
#define XMT_UPPER_LIMIT
Definition: eepro.c:164
unsigned char * node_addr
Definition: nic.h:52
#define outb(data, io_addr)
Definition: io.h:309
static unsigned rcv_ram
Definition: eepro.c:154
#define ID_REG_MASK
Definition: eepro.c:203
static void eepro_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
Definition: eepro.c:417
static int eepro_poll(struct nic *nic, int retrieve)
Definition: eepro.c:356
FILE_LICENCE(GPL2_OR_LATER)
#define eeprom_delay()
Definition: eepro.c:273
#define RCV_UPPER_LIMIT
Definition: eepro.c:162
#define EESK
Definition: eepro.c:264
uint32_t end
Ending offset.
Definition: netvsc.h:18
#define RCV_Discard_BadFrame
Definition: eepro.c:242
static unsigned int tx_start
Definition: eepro.c:301
#define RCV_HEADER
Definition: eepro.c:150
An ISA driver.
Definition: isa.h:34
#define XMT_LOWER_LIMIT
Definition: eepro.c:163
static unsigned int tx_end
Definition: eepro.c:303
#define HOST_ADDRESS_REG
Definition: eepro.c:220
#define eepro_clear_int(ioaddr)
Definition: eepro.c:288
#define EEPROM_REG_10
Definition: eepro.c:261
#define XMT_RAM
Definition: eepro.c:157
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
#define RCV_LOWER_LIMIT_REG
Definition: eepro.c:229
#define EE_READ_CMD
Definition: eepro.c:274
#define RCV_STOP
Definition: eepro.c:214
int(* connect)(struct nic *)
Definition: nic.h:63
#define eepro_full_reset(ioaddr)
Definition: eepro.c:277
#define htons(value)
Definition: byteswap.h:135
#define RCV_UPPER_LIMIT_REG
Definition: eepro.c:230
#define eepro_en_rx(ioaddr)
Definition: eepro.c:291
static void eepro_disable(struct nic *nic, struct isa_device *isa __unused)
Definition: eepro.c:477
#define TX_DONE_BIT
Definition: eepro.c:175
#define REG3
Definition: eepro.c:246