iPXE
skge.h
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1/*
2 * Definitions for the new Marvell Yukon / SysKonnect driver.
3 */
4#ifndef _SKGE_H
5#define _SKGE_H
6
7FILE_LICENCE ( GPL2_ONLY );
8
9/* PCI config registers */
10#define PCI_DEV_REG1 0x40
11#define PCI_PHY_COMA 0x8000000
12#define PCI_VIO 0x2000000
13
14#define PCI_DEV_REG2 0x44
15#define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16#define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
17
18#define DRV_NAME "skge"
19#define DRV_VERSION "1.13"
20#define PFX DRV_NAME " "
21
22#define NUM_TX_DESC 8
23#define NUM_RX_DESC 8
24
25/* mdeck used a 16 byte alignment, but datasheet says 8 bytes is sufficient */
26#define SKGE_RING_ALIGN 8
27#define RX_BUF_SIZE 1536
28#define PHY_RETRIES 1000
29
30#define TX_RING_SIZE ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) )
31#define RX_RING_SIZE ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) )
32#define RING_SIZE ( TX_RING_SIZE + RX_RING_SIZE )
33
34#define SKGE_REG_SIZE 0x4000
35
36#define SKGE_EEPROM_MAGIC 0x9933aabb
37
38/* Added for iPXE ------------------ */
39
40/* from ethtool.h */
41#define AUTONEG_DISABLE 0x00
42#define AUTONEG_ENABLE 0x01
43
44#define DUPLEX_HALF 0x00
45#define DUPLEX_FULL 0x01
46
47#define SPEED_10 10
48#define SPEED_100 100
49#define SPEED_1000 1000
50
51#define ADVERTISED_10baseT_Half (1 << 0)
52#define ADVERTISED_10baseT_Full (1 << 1)
53#define ADVERTISED_100baseT_Half (1 << 2)
54#define ADVERTISED_100baseT_Full (1 << 3)
55#define ADVERTISED_1000baseT_Half (1 << 4)
56#define ADVERTISED_1000baseT_Full (1 << 5)
57
58#define SUPPORTED_10baseT_Half (1 << 0)
59#define SUPPORTED_10baseT_Full (1 << 1)
60#define SUPPORTED_100baseT_Half (1 << 2)
61#define SUPPORTED_100baseT_Full (1 << 3)
62#define SUPPORTED_1000baseT_Half (1 << 4)
63#define SUPPORTED_1000baseT_Full (1 << 5)
64#define SUPPORTED_Autoneg (1 << 6)
65#define SUPPORTED_TP (1 << 7)
66#define SUPPORTED_FIBRE (1 << 10)
67
68/* ----------------------------------- */
69
70#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
71 PCI_STATUS_SIG_SYSTEM_ERROR | \
72 PCI_STATUS_REC_MASTER_ABORT | \
73 PCI_STATUS_REC_TARGET_ABORT | \
74 PCI_STATUS_PARITY)
75
76enum csr_regs {
77 B0_RAP = 0x0000,
78 B0_CTST = 0x0004,
79 B0_LED = 0x0006,
80 B0_POWER_CTRL = 0x0007,
81 B0_ISRC = 0x0008,
82 B0_IMSK = 0x000c,
83 B0_HWE_ISRC = 0x0010,
84 B0_HWE_IMSK = 0x0014,
85 B0_SP_ISRC = 0x0018,
86 B0_XM1_IMSK = 0x0020,
87 B0_XM1_ISRC = 0x0028,
88 B0_XM1_PHY_ADDR = 0x0030,
89 B0_XM1_PHY_DATA = 0x0034,
90 B0_XM2_IMSK = 0x0040,
91 B0_XM2_ISRC = 0x0048,
92 B0_XM2_PHY_ADDR = 0x0050,
93 B0_XM2_PHY_DATA = 0x0054,
94 B0_R1_CSR = 0x0060,
95 B0_R2_CSR = 0x0064,
96 B0_XS1_CSR = 0x0068,
97 B0_XA1_CSR = 0x006c,
98 B0_XS2_CSR = 0x0070,
99 B0_XA2_CSR = 0x0074,
100
101 B2_MAC_1 = 0x0100,
102 B2_MAC_2 = 0x0108,
103 B2_MAC_3 = 0x0110,
104 B2_CONN_TYP = 0x0118,
105 B2_PMD_TYP = 0x0119,
106 B2_MAC_CFG = 0x011a,
107 B2_CHIP_ID = 0x011b,
108 B2_E_0 = 0x011c,
109 B2_E_1 = 0x011d,
110 B2_E_2 = 0x011e,
111 B2_E_3 = 0x011f,
112 B2_FAR = 0x0120,
113 B2_FDP = 0x0124,
114 B2_LD_CTRL = 0x0128,
115 B2_LD_TEST = 0x0129,
116 B2_TI_INI = 0x0130,
117 B2_TI_VAL = 0x0134,
118 B2_TI_CTRL = 0x0138,
119 B2_TI_TEST = 0x0139,
120 B2_IRQM_INI = 0x0140,
121 B2_IRQM_VAL = 0x0144,
122 B2_IRQM_CTRL = 0x0148,
123 B2_IRQM_TEST = 0x0149,
124 B2_IRQM_MSK = 0x014c,
125 B2_IRQM_HWE_MSK = 0x0150,
126 B2_TST_CTRL1 = 0x0158,
127 B2_TST_CTRL2 = 0x0159,
128 B2_GP_IO = 0x015c,
129 B2_I2C_CTRL = 0x0160,
130 B2_I2C_DATA = 0x0164,
131 B2_I2C_IRQ = 0x0168,
132 B2_I2C_SW = 0x016c,
133 B2_BSC_INI = 0x0170,
134 B2_BSC_VAL = 0x0174,
135 B2_BSC_CTRL = 0x0178,
136 B2_BSC_STAT = 0x0179,
137 B2_BSC_TST = 0x017a,
138
139 B3_RAM_ADDR = 0x0180,
140 B3_RAM_DATA_LO = 0x0184,
141 B3_RAM_DATA_HI = 0x0188,
142 B3_RI_WTO_R1 = 0x0190,
143 B3_RI_WTO_XA1 = 0x0191,
144 B3_RI_WTO_XS1 = 0x0192,
145 B3_RI_RTO_R1 = 0x0193,
146 B3_RI_RTO_XA1 = 0x0194,
147 B3_RI_RTO_XS1 = 0x0195,
148 B3_RI_WTO_R2 = 0x0196,
149 B3_RI_WTO_XA2 = 0x0197,
150 B3_RI_WTO_XS2 = 0x0198,
151 B3_RI_RTO_R2 = 0x0199,
152 B3_RI_RTO_XA2 = 0x019a,
153 B3_RI_RTO_XS2 = 0x019b,
154 B3_RI_TO_VAL = 0x019c,
155 B3_RI_CTRL = 0x01a0,
156 B3_RI_TEST = 0x01a2,
157 B3_MA_TOINI_RX1 = 0x01b0,
158 B3_MA_TOINI_RX2 = 0x01b1,
159 B3_MA_TOINI_TX1 = 0x01b2,
160 B3_MA_TOINI_TX2 = 0x01b3,
161 B3_MA_TOVAL_RX1 = 0x01b4,
162 B3_MA_TOVAL_RX2 = 0x01b5,
163 B3_MA_TOVAL_TX1 = 0x01b6,
164 B3_MA_TOVAL_TX2 = 0x01b7,
165 B3_MA_TO_CTRL = 0x01b8,
166 B3_MA_TO_TEST = 0x01ba,
167 B3_MA_RCINI_RX1 = 0x01c0,
168 B3_MA_RCINI_RX2 = 0x01c1,
169 B3_MA_RCINI_TX1 = 0x01c2,
170 B3_MA_RCINI_TX2 = 0x01c3,
171 B3_MA_RCVAL_RX1 = 0x01c4,
172 B3_MA_RCVAL_RX2 = 0x01c5,
173 B3_MA_RCVAL_TX1 = 0x01c6,
174 B3_MA_RCVAL_TX2 = 0x01c7,
175 B3_MA_RC_CTRL = 0x01c8,
176 B3_MA_RC_TEST = 0x01ca,
177 B3_PA_TOINI_RX1 = 0x01d0,
178 B3_PA_TOINI_RX2 = 0x01d4,
179 B3_PA_TOINI_TX1 = 0x01d8,
180 B3_PA_TOINI_TX2 = 0x01dc,
181 B3_PA_TOVAL_RX1 = 0x01e0,
182 B3_PA_TOVAL_RX2 = 0x01e4,
183 B3_PA_TOVAL_TX1 = 0x01e8,
184 B3_PA_TOVAL_TX2 = 0x01ec,
185 B3_PA_CTRL = 0x01f0,
186 B3_PA_TEST = 0x01f2,
187};
188
189/* B0_CTST 16 bit Control/Status register */
190enum {
191 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
192 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
193 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
194 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
195 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
196 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
197 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
198 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
199 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
200 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
201 CS_MRST_CLR = 1<<3, /* Clear Master reset */
202 CS_MRST_SET = 1<<2, /* Set Master reset */
203 CS_RST_CLR = 1<<1, /* Clear Software reset */
204 CS_RST_SET = 1, /* Set Software reset */
205
206/* B0_LED 8 Bit LED register */
207/* Bit 7.. 2: reserved */
208 LED_STAT_ON = 1<<1, /* Status LED on */
209 LED_STAT_OFF = 1, /* Status LED off */
210
211/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
212 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
213 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
214 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
215 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
216 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
217 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
218 PC_VCC_ON = 1<<1, /* Switch VCC On */
219 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
220};
221
222/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
223enum {
224 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
225 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
226 /* Bit 30: reserved */
227 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
228 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
229 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
230 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
231 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
232 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
233 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
234 /* IRQ from PHY (YUKON only) */
235 IS_TIMINT = 1<<22, /* IRQ from Timer */
236 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
237 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
238 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
239 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
240/* Receive Queue 1 */
241 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
242 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
243 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
244/* Receive Queue 2 */
245 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
246 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
247 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
248/* Synchronous Transmit Queue 1 */
249 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
250 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
251 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
252/* Asynchronous Transmit Queue 1 */
253 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
254 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
255 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
256/* Synchronous Transmit Queue 2 */
257 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
258 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
259 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
260/* Asynchronous Transmit Queue 2 */
261 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
262 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
263 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
264
265 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
266 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
267
268 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
269 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
270};
271
272
273/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
274enum {
275 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
276 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
277 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
278 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
279 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
280 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
281 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
282 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
283 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
284 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
285 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
286 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
287 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
288 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
289
290 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
291 | IS_RAM_RD_PAR | IS_RAM_WR_PAR
292 | IS_M1_PAR_ERR | IS_M2_PAR_ERR
293 | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
294};
295
296/* B2_TST_CTRL1 8 bit Test Control Register 1 */
297enum {
298 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
299 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
300 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
301 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
302 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
303 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
304 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
305 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
306};
307
308/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
309enum {
310 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
311 /* Bit 3.. 2: reserved */
312 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
313 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
314};
315
316/* B2_CHIP_ID 8 bit Chip Identification Number */
317enum {
318 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
319 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
320 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
321 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
322 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
323 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
324 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
325
326 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
327 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
328};
329
330/* B2_TI_CTRL 8 bit Timer control */
331/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
332enum {
333 TIM_START = 1<<2, /* Start Timer */
334 TIM_STOP = 1<<1, /* Stop Timer */
335 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
336};
337
338/* B2_TI_TEST 8 Bit Timer Test */
339/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
340/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
341enum {
342 TIM_T_ON = 1<<2, /* Test mode on */
343 TIM_T_OFF = 1<<1, /* Test mode off */
344 TIM_T_STEP = 1<<0, /* Test step */
345};
346
347/* B2_GP_IO 32 bit General Purpose I/O Register */
348enum {
349 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
350 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
351 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
352 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
353 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
354 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
355 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
356 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
357 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
358 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
359
360 GP_IO_9 = 1<<9, /* IO_9 pin */
361 GP_IO_8 = 1<<8, /* IO_8 pin */
362 GP_IO_7 = 1<<7, /* IO_7 pin */
363 GP_IO_6 = 1<<6, /* IO_6 pin */
364 GP_IO_5 = 1<<5, /* IO_5 pin */
365 GP_IO_4 = 1<<4, /* IO_4 pin */
366 GP_IO_3 = 1<<3, /* IO_3 pin */
367 GP_IO_2 = 1<<2, /* IO_2 pin */
368 GP_IO_1 = 1<<1, /* IO_1 pin */
369 GP_IO_0 = 1<<0, /* IO_0 pin */
370};
371
372/* Descriptor Bit Definition */
373/* TxCtrl Transmit Buffer Control Field */
374/* RxCtrl Receive Buffer Control Field */
375enum {
376 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
377 BMU_STF = 1<<30, /* Start of Frame */
378 BMU_EOF = 1<<29, /* End of Frame */
379 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
380 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
381 /* TxCtrl specific bits */
382 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
383 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
384 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
385 /* RxCtrl specific bits */
386 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
387 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
388 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
389 /* Bit 23..16: BMU Check Opcodes */
390 BMU_CHECK = 0x55<<16, /* Default BMU check */
391 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
392 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
393 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
394};
395
396/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
397enum {
398 BSC_START = 1<<1, /* Start Blink Source Counter */
399 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
400};
401
402/* B2_BSC_STAT 8 bit Blink Source Counter Status */
403enum {
404 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
405};
406
407/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
408enum {
409 BSC_T_ON = 1<<2, /* Test mode on */
410 BSC_T_OFF = 1<<1, /* Test mode off */
411 BSC_T_STEP = 1<<0, /* Test step */
412};
413
414/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
415 /* Bit 31..19: reserved */
416#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
417/* RAM Interface Registers */
418
419/* B3_RI_CTRL 16 bit RAM Iface Control Register */
420enum {
421 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
422 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
423
424 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
425 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
426};
427
428/* MAC Arbiter Registers */
429/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
430enum {
431 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
432 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
433 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
434 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
435
436};
437
438/* Timeout values */
439#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
440#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
441#define SK_PKT_TO_MAX 0xffff /* Maximum value */
442#define SK_RI_TO_53 36 /* RAM interface timeout */
443
444/* Packet Arbiter Registers */
445/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
446enum {
447 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
448 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
449 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
450 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
451 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
452 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
453 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
454 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
455 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
456 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
457 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
458 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
459 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
460 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
461};
462
463#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
464 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
465
466
467/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
468/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
469/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
470/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
471/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
472
473#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
474
475/* TXA_CTRL 8 bit Tx Arbiter Control Register */
476enum {
477 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
478 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
479 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
480 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
481 TXA_START_RC = 1<<3, /* Start sync Rate Control */
482 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
483 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
484 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
485};
486
487/*
488 * Bank 4 - 5
489 */
490/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
491enum {
492 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
493 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
494 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
495 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
496 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
497 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
498 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
499};
500
501
502enum {
503 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
504 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
505 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
506 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
507 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
508 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
509 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
510 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
511 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
512};
513
514/* Queue Register Offsets, use Q_ADDR() to access */
515enum {
516 B8_Q_REGS = 0x0400, /* base of Queue registers */
517 Q_D = 0x00, /* 8*32 bit Current Descriptor */
518 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
519 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
520 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
521 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
522 Q_BC = 0x30, /* 32 bit Current Byte Counter */
523 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
524 Q_F = 0x38, /* 32 bit Flag Register */
525 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
526 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
527 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
528 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
529 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
530 Q_T2 = 0x40, /* 32 bit Test Register 2 */
531 Q_T3 = 0x44, /* 32 bit Test Register 3 */
532
533};
534#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
535
536/* RAM Buffer Register Offsets */
537enum {
538
539 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
540 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
541 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
542 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
543 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
544 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
545 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
546 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
547 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
548 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
549 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
550 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
551 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
552 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
553};
554
555/* Receive and Transmit Queues */
556enum {
557 Q_R1 = 0x0000, /* Receive Queue 1 */
558 Q_R2 = 0x0080, /* Receive Queue 2 */
559 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
560 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
561 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
562 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
563};
564
565/* Different MAC Types */
566enum {
567 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
568 SK_MAC_GMAC = 1, /* Marvell GMAC */
569};
570
571/* Different PHY Types */
572enum {
573 SK_PHY_XMAC = 0,/* integrated in XMAC II */
574 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
575 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
576 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
577 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
578 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
579};
580
581/* PHY addresses (bits 12..8 of PHY address reg) */
582enum {
583 PHY_ADDR_XMAC = 0<<8,
584 PHY_ADDR_BCOM = 1<<8,
585
586/* GPHY address (bits 15..11 of SMI control reg) */
587 PHY_ADDR_MARV = 0,
588};
589
590#define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
591
592/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
593enum {
594 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
595 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
596
597 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
598 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
599 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
600 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
601 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
602 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
603 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
604 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
605 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
606
607 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
608 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
609 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
610 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
611
612 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
613 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
614 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
615 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
616 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
617};
618
619/* Receive and Transmit MAC FIFO Registers (GENESIS only) */
620/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
621enum {
622 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
623 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
624 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
625 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
626 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
627 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
628 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
629 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
630 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
631 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
632 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
633 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
634 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
635 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
636 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
637};
638
639/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
640enum {
641 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
642
643 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
644 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
645
646 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
647 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
648
649 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
650 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
651 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
652 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
653
654 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
655};
656
657
658/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
659/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
660enum {
661 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
662 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
663 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
664 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
665 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
666 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
667 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
668};
669
670/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
671/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
672enum {
673 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
674 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
675 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
676
677 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
678 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
679 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
680};
681
682/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
683/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
684enum {
685 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
686 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
687 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
688 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
689};
690
691
692/* Link LED Counter Registers (GENESIS only) */
693
694/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
695/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
696/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
697enum {
698 LED_START = 1<<2, /* Start Timer */
699 LED_STOP = 1<<1, /* Stop Timer */
700 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
701};
702
703/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
704/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
705/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
706enum {
707 LED_T_ON = 1<<2, /* LED Counter Test mode On */
708 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
709 LED_T_STEP = 1<<0, /* LED Counter Step */
710};
711
712/* LNK_LED_REG 8 bit Link LED Register */
713enum {
714 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
715 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
716 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
717 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
718 LED_ON = 1<<1, /* switch LED on */
719 LED_OFF = 1<<0, /* switch LED off */
720};
721
722/* Receive GMAC FIFO (YUKON) */
723enum {
724 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
725 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
726 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
727 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
728 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
729 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
730 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
731 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
732 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
733};
734
735
736/* TXA_TEST 8 bit Tx Arbiter Test Register */
737enum {
738 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
739 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
740 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
741 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
742 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
743 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
744};
745
746/* TXA_STAT 8 bit Tx Arbiter Status Register */
747enum {
748 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
749};
750
751
752/* Q_BC 32 bit Current Byte Counter */
753
754/* BMU Control Status Registers */
755/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
756/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
757/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
758/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
759/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
760/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
761/* Q_CSR 32 bit BMU Control/Status Register */
762
763enum {
764 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
765
766 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
767 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
768 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
769 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
770 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
771 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
772 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
773 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
774 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
775 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
776 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
777 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
778 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
779 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
780 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
781 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
782 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
783 CSR_START = 1<<4, /* Start Rx/Tx Queue */
784 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
785 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
786 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
787 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
788};
789
790#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
791 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
792 CSR_TRANS_RST)
793#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
794 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
795 CSR_TRANS_RUN)
796
797/* Q_F 32 bit Flag Register */
798enum {
799 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
800 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
801 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
802 F_WM_REACHED = 1<<25, /* Watermark reached */
803
804 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
805 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
806};
807
808/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
809/* RB_START 32 bit RAM Buffer Start Address */
810/* RB_END 32 bit RAM Buffer End Address */
811/* RB_WP 32 bit RAM Buffer Write Pointer */
812/* RB_RP 32 bit RAM Buffer Read Pointer */
813/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
814/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
815/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
816/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
817/* RB_PC 32 bit RAM Buffer Packet Counter */
818/* RB_LEV 32 bit RAM Buffer Level Register */
819
820#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
821/* RB_TST2 8 bit RAM Buffer Test Register 2 */
822/* RB_TST1 8 bit RAM Buffer Test Register 1 */
823
824/* RB_CTRL 8 bit RAM Buffer Control Register */
825enum {
826 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
827 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
828 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
829 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
830 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
831 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
832};
833
834/* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
835enum {
836 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
837 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
838 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
839 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
840 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
841 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
842 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
843 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
844
845 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
846 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
847 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
848
849 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
850 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
851 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
852 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
853};
854
855/* Counter and Timer constants, for a host clock of 62.5 MHz */
856#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
857#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
858
859#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
860
861#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
862 /* 215 ms at 78.12 MHz */
863
864#define SK_FACT_62 100 /* is given in percent */
865#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
866#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
867
868
869/* Transmit GMAC FIFO (YUKON only) */
870enum {
871 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
872 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
873 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
874
875 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
876 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
877 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
878
879 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
880 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
881 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
882
883 /* Descriptor Poll Timer Registers */
884 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
885 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
886 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
887
888 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
889
890 /* Time Stamp Timer Registers (YUKON only) */
891 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
892 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
893 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
894};
895
896
897enum {
898 LINKLED_OFF = 0x01,
899 LINKLED_ON = 0x02,
900 LINKLED_LINKSYNC_OFF = 0x04,
901 LINKLED_LINKSYNC_ON = 0x08,
902 LINKLED_BLINK_OFF = 0x10,
903 LINKLED_BLINK_ON = 0x20,
904};
905
906/* GMAC and GPHY Control Registers (YUKON only) */
907enum {
908 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
909 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
910 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
911 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
912 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
913
914/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
915
916 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
917
918 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
919 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
920 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
921 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
922 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
923
924/* WOL Pattern Length Registers (YUKON only) */
925
926 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
927 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
928
929/* WOL Pattern Counter Registers (YUKON only) */
930
931 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
932 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
933};
934#define WOL_REGS(port, x) (x + (port)*0x80)
935
936enum {
937 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
938 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
939};
940#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
941
942enum {
943 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
944 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
945 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
946 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
947};
948
949/*
950 * Receive Frame Status Encoding
951 */
952enum {
953 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
954 XMR_FS_LEN_SHIFT = 18,
955 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
956 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
957 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
958 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
959 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
960
961 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
962 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
963 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
964 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
965 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
966 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
967 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
968 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
969 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
970 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
971 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
972 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
973
974/*
975 * XMR_FS_ERR will be set if
976 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
977 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
978 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
979 * XMR_FS_ERR unless the corresponding bit in the Receive Command
980 * Register is set.
981 */
982};
983
984/*
985,* XMAC-PHY Registers, indirect addressed over the XMAC
986 */
987enum {
988 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
989 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
990 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
991 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
992 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
993 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
994 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
995 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
996 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
997
998 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
999 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
1000};
1001/*
1002 * Broadcom-PHY Registers, indirect addressed over XMAC
1003 */
1004enum {
1005 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1006 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1007 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1008 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1009 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1010 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1011 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1012 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1013 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1014 /* Broadcom-specific registers */
1015 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1016 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1017 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1018 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1019 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1020 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1021 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1022 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1023
1024 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1025 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1026 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1027 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1028};
1029
1030/*
1031 * Marvel-PHY Registers, indirect addressed over GMAC
1032 */
1033enum {
1034 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1035 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1036 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1037 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1038 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1039 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1040 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1041 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1042 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1043 /* Marvel-specific registers */
1044 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1045 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1046 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1047 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1048 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1049 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1050 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1051 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1052 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1053 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1054 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1055 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1056 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1057 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1058 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1059 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1060 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1061 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1062
1063/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1064 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1065 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1066 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1067 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1068 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1069};
1070
1071enum {
1072 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1073 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1074 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1075 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1076 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1077 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1078 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1079 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1080 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1081 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1082};
1083
1084enum {
1085 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1086 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1087 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1088};
1089
1090enum {
1091 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1092
1093 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1094 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1095 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
1096 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1097 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1098 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1099 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1100};
1101
1102enum {
1103 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1104 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1105 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1106};
1107
1108/* different Broadcom PHY Ids */
1109enum {
1110 PHY_BCOM_ID1_A1 = 0x6041,
1111 PHY_BCOM_ID1_B2 = 0x6043,
1112 PHY_BCOM_ID1_C0 = 0x6044,
1113 PHY_BCOM_ID1_C5 = 0x6047,
1114};
1115
1116/* different Marvell PHY Ids */
1117enum {
1118 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1119 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1120 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1121 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1122 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1123};
1124
1125/* Advertisement register bits */
1126enum {
1127 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1128 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1129 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1130
1131 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1132 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1133 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1134 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1135 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1136 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1137 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1138 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1139 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1140 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1141 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1142 PHY_AN_100HALF | PHY_AN_100FULL,
1143};
1144
1145/* Xmac Specific */
1146enum {
1147 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1148 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1149 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1150
1151 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1152 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1153 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1154};
1155
1156/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1157enum {
1158 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1159 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1160 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1161 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1162};
1163
1164
1165/***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1166enum {
1167 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1168 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1169};
1170
1171/***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1172enum {
1173 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1174 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1175 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1176 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1177 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1178};
1179
1180/* Remote Fault Bits (PHY_X_AN_RFB) encoding */
1181enum {
1182 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1183 X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
1184 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1185 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1186};
1187
1188/* Broadcom-Specific */
1189/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1190enum {
1191 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1192 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1193 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1194 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1195 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1196 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1197};
1198
1199/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1200/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1201enum {
1202 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1203 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1204 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1205 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1206 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1207 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1208 /* Bit 9..8: reserved */
1209 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1210};
1211
1212/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1213enum {
1214 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1215 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1216 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1217 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1218};
1219
1220/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1221enum {
1222 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1223 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1224 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1225 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1226 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1227 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1228 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1229 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1230 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1231 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1232 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1233 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1234 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1235 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1236 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1237 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1238};
1239
1240/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1241enum {
1242 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1243 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1244 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1245 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1246 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1247 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1248 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1249 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1250 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1251 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1252 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1253 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1254 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1255 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1256};
1257
1258/* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1259/* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1260enum {
1261 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1262
1263 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1264 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1265};
1266
1267
1268/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1269enum {
1270 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1271
1272/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1273 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1274 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1275
1276/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1277 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1278 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1279 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1280 /* Bit 11: reserved */
1281 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1282 /* Bit 9.. 8: reserved */
1283 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1284 /* Bit 6: reserved */
1285 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1286 /* Bit 4: reserved */
1287 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1288};
1289
1290/***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1291enum {
1292 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1293 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1294 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1295 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1296 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1297 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1298 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1299 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1300 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1301 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1302 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1303 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1304 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1305 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1306};
1307#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1308
1309/***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1310/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1311enum {
1312 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1313 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1314 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1315 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1316 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1317 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1318 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1319 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1320 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1321 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1322 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1323 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1324 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1325 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1326 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1327};
1328#define PHY_B_DEF_MSK \
1329 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1330 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1331
1332/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1333enum {
1334 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1335 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1336 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1337 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1338};
1339/*
1340 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1341 */
1342enum {
1343 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1344 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1345};
1346
1347/** Marvell-Specific */
1348enum {
1349 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1350 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1351 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1352
1353 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1354 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1355 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1356 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1357 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1358 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1359 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1360 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1361};
1362
1363/* special defines for FIBER (88E1011S only) */
1364enum {
1365 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1366 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1367 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1368 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1369};
1370
1371/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1372enum {
1373 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1374 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1375 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1376 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1377};
1378
1379/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1380enum {
1381 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1382 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1383 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1384 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1385 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1386 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1387};
1388
1389/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1390enum {
1391 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1392 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1393 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1394 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1395 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1396 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1397 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1398 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1399 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1400 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1401 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1402 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1403};
1404
1405enum {
1406 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1407 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1408};
1409
1410enum {
1411 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1412 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1413 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1414};
1415
1416/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1417enum {
1418 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1419 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1420 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1421 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1422 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1423
1424 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1425 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1426
1427 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1428 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1429};
1430
1431/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1432enum {
1433 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1434 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1435 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1436 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1437 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1438 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1439 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1440 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1441 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1442 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1443 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1444 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1445 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1446 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1447 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1448 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1449};
1450
1451#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1452
1453/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1454enum {
1455 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1456 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1457};
1458
1459enum {
1460 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1461 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1462 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1463 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1464 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1465 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1466 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1467 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1468 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1469 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1470 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1471 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1472
1473 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1474 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1475 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1476
1477 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1478 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1479
1480 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1481};
1482
1483/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1484enum {
1485 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1486 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1487
1488 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1489 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1490 /* (88E1011 only) */
1491 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
1492 /* (88E1011 only) */
1493 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1494 /* (88E1111 only) */
1495 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1496 /* !!! Errata in spec. (1 = disable) */
1497 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1498 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1499 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1500 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1501 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1502 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1503
1504#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1505#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1506#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1507
1508#define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1509 /* 100=5x; 101=6x; 110=7x; 111=8x */
1510enum {
1511 MAC_TX_CLK_0_MHZ = 2,
1512 MAC_TX_CLK_2_5_MHZ = 6,
1513 MAC_TX_CLK_25_MHZ = 7,
1514};
1515
1516/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1517enum {
1518 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1519 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1520 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1521 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1522 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1523 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1524 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1525 /* (88E1111 only) */
1526};
1527#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1528#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1529
1530enum {
1531 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
1532 /* (88E1011 only) */
1533 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1534 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1535 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1536 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1537 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1538};
1539
1540enum {
1541 PULS_NO_STR = 0, /* no pulse stretching */
1542 PULS_21MS = 1, /* 21 ms to 42 ms */
1543 PULS_42MS = 2, /* 42 ms to 84 ms */
1544 PULS_84MS = 3, /* 84 ms to 170 ms */
1545 PULS_170MS = 4, /* 170 ms to 340 ms */
1546 PULS_340MS = 5, /* 340 ms to 670 ms */
1547 PULS_670MS = 6, /* 670 ms to 1.3 s */
1548 PULS_1300MS = 7, /* 1.3 s to 2.7 s */
1549};
1550
1551
1552enum {
1553 BLINK_42MS = 0, /* 42 ms */
1554 BLINK_84MS = 1, /* 84 ms */
1555 BLINK_170MS = 2, /* 170 ms */
1556 BLINK_340MS = 3, /* 340 ms */
1557 BLINK_670MS = 4, /* 670 ms */
1558};
1559
1560/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1561#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1562 /* Bit 13..12: reserved */
1563#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1564#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1565#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1566#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1567#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1568#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1569
1570enum {
1571 MO_LED_NORM = 0,
1572 MO_LED_BLINK = 1,
1573 MO_LED_OFF = 2,
1574 MO_LED_ON = 3,
1575};
1576
1577/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1578enum {
1579 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1580 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1581 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1582 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1583 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
1584};
1585
1586/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1587enum {
1588 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1589 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1590 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1591 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1592 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1593 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1594 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1595 /* (88E1111 only) */
1596 /* Bit 9.. 4: reserved (88E1011 only) */
1597 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1598 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1599 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1600};
1601
1602/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1603enum {
1604 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1605 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1606 /* (88E1111 only) */
1607 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1608 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1609 /* (88E1111 only) */
1610 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1611};
1612
1613/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1614enum {
1615 CABD_STAT_NORMAL= 0,
1616 CABD_STAT_SHORT = 1,
1617 CABD_STAT_OPEN = 2,
1618 CABD_STAT_FAIL = 3,
1619};
1620
1621/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1622/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1623 /* Bit 15..12: reserved (used internally) */
1624enum {
1625 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1626 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1627 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1628};
1629
1630#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1631#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1632#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1633
1634enum {
1635 LED_PAR_CTRL_COLX = 0x00,
1636 LED_PAR_CTRL_ERROR = 0x01,
1637 LED_PAR_CTRL_DUPLEX = 0x02,
1638 LED_PAR_CTRL_DP_COL = 0x03,
1639 LED_PAR_CTRL_SPEED = 0x04,
1640 LED_PAR_CTRL_LINK = 0x05,
1641 LED_PAR_CTRL_TX = 0x06,
1642 LED_PAR_CTRL_RX = 0x07,
1643 LED_PAR_CTRL_ACT = 0x08,
1644 LED_PAR_CTRL_LNK_RX = 0x09,
1645 LED_PAR_CTRL_LNK_AC = 0x0a,
1646 LED_PAR_CTRL_ACT_BL = 0x0b,
1647 LED_PAR_CTRL_TX_BL = 0x0c,
1648 LED_PAR_CTRL_RX_BL = 0x0d,
1649 LED_PAR_CTRL_COL_BL = 0x0e,
1650 LED_PAR_CTRL_INACT = 0x0f
1651};
1652
1653/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1654enum {
1655 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1656 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1657 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1658};
1659
1660
1661/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1662enum {
1663 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1664 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1665 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1666 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1667};
1668
1669#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1670#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1671#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1672#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1673
1674/* GMAC registers */
1675/* Port Registers */
1676enum {
1677 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1678 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1679 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1680 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1681 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1682 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1683 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1684/* Source Address Registers */
1685 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1686 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1687 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1688 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1689 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1690 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1691
1692/* Multicast Address Hash Registers */
1693 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1694 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1695 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1696 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1697
1698/* Interrupt Source Registers */
1699 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1700 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1701 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1702
1703/* Interrupt Mask Registers */
1704 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1705 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1706 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1707
1708/* Serial Management Interface (SMI) Registers */
1709 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1710 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1711 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1712};
1713
1714/* MIB Counters */
1715#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1716#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1717
1718/*
1719 * MIB Counters base address definitions (low word) -
1720 * use offset 4 for access to high word (32 bit r/o)
1721 */
1722enum {
1723 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1724 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1725 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1726 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1727 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1728 /* GM_MIB_CNT_BASE + 40: reserved */
1729 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1730 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1731 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1732 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1733 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1734 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1735 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1736 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1737 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1738 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1739 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1740 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1741 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1742 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1743 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1744 /* GM_MIB_CNT_BASE + 168: reserved */
1745 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1746 /* GM_MIB_CNT_BASE + 184: reserved */
1747 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1748 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1749 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1750 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1751 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1752 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1753 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1754 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1755 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1756 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1757 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1758 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1759 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1760
1761 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1762 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1763 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1764 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1765 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1766 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1767};
1768
1769/* GMAC Bit Definitions */
1770/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1771enum {
1772 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1773 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1774 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1775 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1776 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1777 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1778 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
1779 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
1780
1781 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1782 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1783 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1784 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1785 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1786};
1787
1788/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1789enum {
1790 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1791 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1792 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1793 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1794 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1795 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1796 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1797 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1798 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1799 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1800 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1801 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1802 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1803 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1804 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1805};
1806
1807#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1808#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1809
1810/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1811enum {
1812 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1813 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1814 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1815 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1816};
1817
1818#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1819#define TX_COL_DEF 0x04 /* late collision after 64 byte */
1820
1821/* GM_RX_CTRL 16 bit r/w Receive Control Register */
1822enum {
1823 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1824 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1825 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1826 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1827};
1828
1829/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1830enum {
1831 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1832 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1833 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1834
1835 TX_JAM_LEN_DEF = 0x03,
1836 TX_JAM_IPG_DEF = 0x0b,
1837 TX_IPG_JAM_DEF = 0x1c,
1838};
1839
1840#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1841#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1842#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1843
1844
1845/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1846enum {
1847 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1848 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1849 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1850 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1851 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1852};
1853
1854#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1855#define DATA_BLIND_DEF 0x04
1856
1857#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1858#define IPG_DATA_DEF 0x1e
1859
1860/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1861enum {
1862 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1863 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1864 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1865 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1866 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1867};
1868
1869#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1870#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1871
1872/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1873enum {
1874 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1875 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1876};
1877
1878/* Receive Frame Status Encoding */
1879enum {
1880 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1881 GMR_FS_LEN_SHIFT = 16,
1882 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1883 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1884 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1885 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1886 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1887 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1888 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1889 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1890 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1891 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1892 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1893
1894 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1895 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1896
1897/*
1898 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1899 */
1900 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1901 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1902 GMR_FS_JABBER,
1903/* Rx GMAC FIFO Flush Mask (default) */
1904 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1905 GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
1906};
1907
1908/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1909enum {
1910 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1911 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1912 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1913
1914 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1915 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1916 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1917 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1918 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1919 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1920 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1921 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1922 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1923 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1924 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1925
1926 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1927};
1928
1929
1930/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1931enum {
1932 GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
1933 GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
1934 GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
1935
1936 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1937 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1938 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1939};
1940
1941/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1942enum {
1943 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1944 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1945 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1946};
1947
1948/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1949enum {
1950 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1951 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1952 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1953 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1954 GMC_PAUSE_ON = 1<<3, /* Pause On */
1955 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1956 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1957 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1958};
1959
1960/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1961enum {
1962 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1963 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1964 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1965 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1966 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1967 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1968 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1969 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1970 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1971 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1972 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1973 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1974 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1975 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1976 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1977 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1978 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1979 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1980 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1981 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1982 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1983 /* Bits 7..2: reserved */
1984 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1985 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1986};
1987
1988#define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1989#define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1990#define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1991
1992/* forced speed and duplex mode (don't mix with other ANEG bits) */
1993#define GPC_FRC10MBIT_HALF 0
1994#define GPC_FRC10MBIT_FULL GPC_ANEG_0
1995#define GPC_FRC100MBIT_HALF GPC_ANEG_1
1996#define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1997
1998/* auto-negotiation with limited advertised speeds */
1999/* mix only with master/slave settings (for copper) */
2000#define GPC_ADV_1000_HALF GPC_ANEG_2
2001#define GPC_ADV_1000_FULL GPC_ANEG_3
2002#define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
2003
2004/* master/slave settings */
2005/* only for copper with 1000 Mbps */
2006#define GPC_FORCE_MASTER 0
2007#define GPC_FORCE_SLAVE GPC_ANEG_0
2008#define GPC_PREF_MASTER GPC_ANEG_1
2009#define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
2010
2011/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2012/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2013enum {
2014 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
2015 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
2016 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
2017 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
2018 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
2019 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
2020
2021#define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
2022
2023/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2024 /* Bits 15.. 2: reserved */
2025 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2026 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2027
2028
2029/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2030 WOL_CTL_LINK_CHG_OCC = 1<<15,
2031 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
2032 WOL_CTL_PATTERN_OCC = 1<<13,
2033 WOL_CTL_CLEAR_RESULT = 1<<12,
2034 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2035 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
2036 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
2037 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
2038 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
2039 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
2040 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2041 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
2042 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
2043 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
2044 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
2045 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
2046};
2047
2048#define WOL_CTL_DEFAULT \
2049 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
2050 WOL_CTL_DIS_PME_ON_PATTERN | \
2051 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
2052 WOL_CTL_DIS_LINK_CHG_UNIT | \
2053 WOL_CTL_DIS_PATTERN_UNIT | \
2054 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2055
2056/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2057#define WOL_CTL_PATT_ENA(x) (1 << (x))
2058
2059
2060/* XMAC II registers */
2061enum {
2062 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2063 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2064 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2065 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2066 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2067 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2068 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2069 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2070 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2071 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2072 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2073 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2074 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2075 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2076 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2077 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2078 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2079 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2080 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2081 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2082 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2083 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2084 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2085 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2086 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2087
2088 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2089#define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2090};
2091
2092enum {
2093 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2094 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2095 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2096 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2097 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2098 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2099 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2100 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2101 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2102 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2103 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2104 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2105 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2106 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2107 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2108 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2109 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2110 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2111 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2112 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2113 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2114 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2115 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2116 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2117 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2118 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2119 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2120 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2121 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2122 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2123 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2124 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2125 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2126 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2127 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2128 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2129 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2130 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2131 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2132 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2133 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2134 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2135 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2136 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2137 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2138 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2139 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2140 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2141 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2142 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2143 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2144 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2145 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2146 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2147 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2148 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2149 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2150 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2151 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2152 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2153 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2154 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2155 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2156 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2157 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2158 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2159 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2160 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2161 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2162 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2163 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2164};
2165
2166/* XM_MMU_CMD 16 bit r/w MMU Command Register */
2167enum {
2168 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2169 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2170 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2171 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2172 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2173 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2174 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2175 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2176 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2177 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2178 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2179 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2180};
2181
2182
2183/* XM_TX_CMD 16 bit r/w Transmit Command Register */
2184enum {
2185 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2186 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2187 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2188 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2189 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2190 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2191 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2192};
2193
2194/* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2195#define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2196
2197
2198/* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2199#define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2200
2201
2202/* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2203#define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2204
2205
2206/* XM_RX_CMD 16 bit r/w Receive Command Register */
2207enum {
2208 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2209 /* inrange error packets */
2210 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2211 /* jumbo packets */
2212 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2213 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2214 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2215 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2216 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2217 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2218 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2219};
2220
2221
2222/* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2223enum {
2224 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2225 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2226 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2227 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2228 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2229};
2230
2231
2232/* XM_IMSK 16 bit r/w Interrupt Mask Register */
2233/* XM_ISRC 16 bit r/o Interrupt Status Register */
2234enum {
2235 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2236 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2237 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2238 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2239 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2240 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2241 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2242 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2243 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2244 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2245 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2246 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2247 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2248 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2249 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2250
2251 XM_IMSK_DISABLE = 0xffff,
2252};
2253
2254/* XM_HW_CFG 16 bit r/w Hardware Config Register */
2255enum {
2256 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2257 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2258 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2259};
2260
2261
2262/* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2263/* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2264#define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2265
2266/* XM_TX_THR 16 bit r/w Tx Request Threshold */
2267/* XM_HT_THR 16 bit r/w Host Request Threshold */
2268/* XM_RX_THR 16 bit r/w Rx Request Threshold */
2269#define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2270
2271
2272/* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2273enum {
2274 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2275 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2276 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2277 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2278 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2279 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2280 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2281 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2282 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2283 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2284 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occurred */
2285 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2286 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2287 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2288 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2289};
2290
2291/* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2292/* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2293#define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2294
2295
2296/* XM_DEV_ID 32 bit r/o Device ID Register */
2297#define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2298#define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2299
2300
2301/* XM_MODE 32 bit r/w Mode Register */
2302enum {
2303 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2304 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2305 /* extern generated */
2306 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2307 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2308 /* intern generated */
2309 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2310 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2311 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2312 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2313 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2314 /* intern generated */
2315 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2316 /* intern generated */
2317 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2318 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2319 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2320 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2321 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2322 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2323 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2324 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2325 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2326 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2327 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2328 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2329 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2330 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2331 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2332 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2333 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2334};
2335
2336#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2337#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2338 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2339
2340/* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2341enum {
2342 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2343 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2344 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2345 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2346 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2347 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2348};
2349
2350
2351/* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2352/* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2353enum {
2354 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2355 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2356 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2357 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2358 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2359 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2360 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2361 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2362 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2363 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2364 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2365 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2366 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2367 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2368 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2369 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2370 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2371 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2372 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2373 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2374 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2375 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2376 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2377 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2378 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2379 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2380 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2381 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2382 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2383 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2384};
2385
2386#define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2387
2388/* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2389/* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2390enum {
2391 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2392 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2393 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2394 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2395 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2396 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2397 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2398 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2399 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2400 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2401 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2402 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2403 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2404 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2405 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2406 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2407 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2408 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2409 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2410 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2411 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2412 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2413 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2414 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2415 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2416 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2417};
2418
2419
2420#define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2421
2434
2446
2447struct skge_element {
2448 struct skge_element *next;
2449 void *desc;
2450 struct io_buffer *iob;
2451};
2452
2458
2459
2476
2477enum pause_control {
2478 FLOW_MODE_NONE = 1, /* No Flow-Control */
2479 FLOW_MODE_LOC_SEND = 2, /* Local station sends PAUSE */
2480 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2481 FLOW_MODE_SYM_OR_REM = 4, /* Both stations may send PAUSE or
2482 * just the remote station may send PAUSE
2483 */
2484};
2485
2486enum pause_status {
2487 FLOW_STAT_INDETERMINATED=0, /* indeterminated */
2488 FLOW_STAT_NONE, /* No Flow Control */
2489 FLOW_STAT_REM_SEND, /* Remote Station sends PAUSE */
2490 FLOW_STAT_LOC_SEND, /* Local station sends PAUSE */
2491 FLOW_STAT_SYMMETRIC, /* Both station may send PAUSE */
2492};
2493
2494
2495struct skge_port {
2496 struct skge_hw *hw;
2497 struct net_device *netdev;
2498 int port;
2499
2500 struct skge_ring tx_ring;
2501 struct skge_ring rx_ring;
2502
2503 enum pause_control flow_control;
2504 enum pause_status flow_status;
2505 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2506 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2507 u16 speed; /* SPEED_1000, SPEED_100, ... */
2508 u32 advertising;
2509
2510 void *mem; /* PCI memory for rings */
2511 u32 dma;
2512 int use_xm_link_timer;
2513};
2514
2515
2516/* Register accessor for memory mapped device */
2517static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2518{
2519 return readl(hw->regs + reg);
2520}
2521
2522static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2523{
2524 return readw(hw->regs + reg);
2525}
2526
2527static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2528{
2529 return readb(hw->regs + reg);
2530}
2531
2532static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2533{
2534 writel(val, hw->regs + reg);
2535}
2536
2537static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2538{
2539 writew(val, hw->regs + reg);
2540}
2541
2542static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2543{
2544 writeb(val, hw->regs + reg);
2545}
2546
2547/* MAC Related Registers inside the device. */
2548#define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2549#define SK_XMAC_REG(port, reg) \
2550 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2551
2552static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2553{
2554 u32 v;
2555 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2556 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2557 return v;
2558}
2559
2560static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2561{
2562 return skge_read16(hw, SK_XMAC_REG(port,reg));
2563}
2564
2565static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2566{
2567 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2568 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2569}
2570
2571static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2572{
2573 skge_write16(hw, SK_XMAC_REG(port,r), v);
2574}
2575
2576static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2577 const u8 *hash)
2578{
2579 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2580 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2581 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2582 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2583}
2584
2585static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2586 const u8 *addr)
2587{
2588 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2589 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2590 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2591}
2592
2593#define SK_GMAC_REG(port,reg) \
2594 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2595
2596static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2597{
2598 return skge_read16(hw, SK_GMAC_REG(port,reg));
2599}
2600
2601static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2602{
2603 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2604 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2605}
2606
2607static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2608{
2609 skge_write16(hw, SK_GMAC_REG(port,r), v);
2610}
2611
2612static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2613 const u8 *addr)
2614{
2615 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2616 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2617 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2618}
2619
2620#endif
port
u8 port
Port number.
Definition CIB_PRM.h:3
hash
pseudo_bit_t hash[0x00010]
Definition arbel.h:2
addr
uint32_t addr
Buffer address.
Definition dwmac.h:9
FILE_LICENCE
#define FILE_LICENCE(_licence)
Declare a particular licence as applying to a file.
Definition compiler.h:896
u8
#define u8
Definition igbvf_osdep.h:40
val
void __asmcall int val
Definition setjmp.h:12
r
static const uint8_t r[3][4]
MD4 shift amounts.
Definition md4.c:54
reg
static unsigned int unsigned int reg
Definition myson.h:162
XM_TX_ENC_BYP
@ XM_TX_ENC_BYP
Definition skge.h:2186
XM_TX_AUTO_PAD
@ XM_TX_AUTO_PAD
Definition skge.h:2191
XM_TX_NO_PRE
@ XM_TX_NO_PRE
Definition skge.h:2189
XM_TX_SAM_LINE
@ XM_TX_SAM_LINE
Definition skge.h:2187
XM_TX_BK2BK
@ XM_TX_BK2BK
Definition skge.h:2185
XM_TX_NO_CRC
@ XM_TX_NO_CRC
Definition skge.h:2190
XM_TX_NO_GIG_MD
@ XM_TX_NO_GIG_MD
Definition skge.h:2188
RB_ENA_OP_MD
@ RB_ENA_OP_MD
Definition skge.h:828
RB_ENA_STFWD
@ RB_ENA_STFWD
Definition skge.h:826
RB_RST_SET
@ RB_RST_SET
Definition skge.h:831
RB_DIS_OP_MD
@ RB_DIS_OP_MD
Definition skge.h:829
RB_RST_CLR
@ RB_RST_CLR
Definition skge.h:830
RB_DIS_STFWD
@ RB_DIS_STFWD
Definition skge.h:827
XM_GP_RES_STAT
@ XM_GP_RES_STAT
Definition skge.h:2227
XM_GP_ANIP
@ XM_GP_ANIP
Definition skge.h:2224
XM_GP_RES_MAC
@ XM_GP_RES_MAC
Definition skge.h:2226
XM_GP_INP_ASS
@ XM_GP_INP_ASS
Definition skge.h:2228
XM_GP_FRC_INT
@ XM_GP_FRC_INT
Definition skge.h:2225
PHY_M_DTE_POW_STAT
@ PHY_M_DTE_POW_STAT
Definition skge.h:1598
PHY_M_MODE_MASK
@ PHY_M_MODE_MASK
Definition skge.h:1599
PHY_M_SER_IF_BP_ST
@ PHY_M_SER_IF_BP_ST
Definition skge.h:1592
PHY_M_UNDOC1
@ PHY_M_UNDOC1
Definition skge.h:1597
PHY_M_IRQ_POLARITY
@ PHY_M_IRQ_POLARITY
Definition skge.h:1593
PHY_M_DIS_AUT_MED
@ PHY_M_DIS_AUT_MED
Definition skge.h:1594
PHY_M_FC_RESOLUTION
@ PHY_M_FC_RESOLUTION
Definition skge.h:1590
PHY_M_FC_AUTO_SEL
@ PHY_M_FC_AUTO_SEL
Definition skge.h:1588
PHY_M_FC_AN_REG_ACC
@ PHY_M_FC_AN_REG_ACC
Definition skge.h:1589
PHY_M_SER_IF_AN_BP
@ PHY_M_SER_IF_AN_BP
Definition skge.h:1591
PHY_X_AN_NXT_PG
@ PHY_X_AN_NXT_PG
Definition skge.h:1147
PHY_X_AN_RFB
@ PHY_X_AN_RFB
Definition skge.h:1149
PHY_X_AN_FD
@ PHY_X_AN_FD
Definition skge.h:1153
PHY_X_AN_HD
@ PHY_X_AN_HD
Definition skge.h:1152
PHY_X_AN_PAUSE
@ PHY_X_AN_PAUSE
Definition skge.h:1151
PHY_X_AN_ACK
@ PHY_X_AN_ACK
Definition skge.h:1148
XM_SC_CLR_TXC
@ XM_SC_CLR_TXC
Definition skge.h:2347
XM_SC_SNP_TXC
@ XM_SC_SNP_TXC
Definition skge.h:2343
XM_SC_CP_TXC
@ XM_SC_CP_TXC
Definition skge.h:2345
XM_SC_CP_RXC
@ XM_SC_CP_RXC
Definition skge.h:2344
XM_SC_CLR_RXC
@ XM_SC_CLR_RXC
Definition skge.h:2346
XM_SC_SNP_RXC
@ XM_SC_SNP_RXC
Definition skge.h:2342
pause_status
pause_status
Definition skge.h:2486
FLOW_STAT_INDETERMINATED
@ FLOW_STAT_INDETERMINATED
Definition skge.h:2487
FLOW_STAT_NONE
@ FLOW_STAT_NONE
Definition skge.h:2488
FLOW_STAT_SYMMETRIC
@ FLOW_STAT_SYMMETRIC
Definition skge.h:2491
FLOW_STAT_LOC_SEND
@ FLOW_STAT_LOC_SEND
Definition skge.h:2490
FLOW_STAT_REM_SEND
@ FLOW_STAT_REM_SEND
Definition skge.h:2489
B8_TS1_REGS
@ B8_TS1_REGS
Definition skge.h:507
B7_CFG_SPC
@ B7_CFG_SPC
Definition skge.h:504
B8_TA2_REGS
@ B8_TA2_REGS
Definition skge.h:510
B8_TS2_REGS
@ B8_TS2_REGS
Definition skge.h:509
B16_RAM_REGS
@ B16_RAM_REGS
Definition skge.h:511
B8_RQ1_REGS
@ B8_RQ1_REGS
Definition skge.h:505
B6_EXT_REG
@ B6_EXT_REG
Definition skge.h:503
B8_TA1_REGS
@ B8_TA1_REGS
Definition skge.h:508
B8_RQ2_REGS
@ B8_RQ2_REGS
Definition skge.h:506
xm_outaddr
static void xm_outaddr(const struct skge_hw *hw, int port, int reg, const u8 *addr)
Definition skge.h:2585
PHY_BCOM_ID1_C0
@ PHY_BCOM_ID1_C0
Definition skge.h:1112
PHY_BCOM_ID1_C5
@ PHY_BCOM_ID1_C5
Definition skge.h:1113
PHY_BCOM_ID1_A1
@ PHY_BCOM_ID1_A1
Definition skge.h:1110
PHY_BCOM_ID1_B2
@ PHY_BCOM_ID1_B2
Definition skge.h:1111
TXA_ENA_ARB
@ TXA_ENA_ARB
Definition skge.h:483
TXA_ENA_ALLOC
@ TXA_ENA_ALLOC
Definition skge.h:479
TXA_DIS_FSYNC
@ TXA_DIS_FSYNC
Definition skge.h:478
TXA_STOP_RC
@ TXA_STOP_RC
Definition skge.h:482
TXA_DIS_ALLOC
@ TXA_DIS_ALLOC
Definition skge.h:480
TXA_START_RC
@ TXA_START_RC
Definition skge.h:481
TXA_ENA_FSYNC
@ TXA_ENA_FSYNC
Definition skge.h:477
TXA_DIS_ARB
@ TXA_DIS_ARB
Definition skge.h:484
PHY_BCOM_AUX_CTRL
@ PHY_BCOM_AUX_CTRL
Definition skge.h:1024
PHY_BCOM_STAT
@ PHY_BCOM_STAT
Definition skge.h:1006
PHY_BCOM_AUNE_EXP
@ PHY_BCOM_AUNE_EXP
Definition skge.h:1011
PHY_BCOM_RNO_CTR
@ PHY_BCOM_RNO_CTR
Definition skge.h:1022
PHY_BCOM_INT_MASK
@ PHY_BCOM_INT_MASK
Definition skge.h:1027
PHY_BCOM_EXT_STAT
@ PHY_BCOM_EXT_STAT
Definition skge.h:1017
PHY_BCOM_CTRL
@ PHY_BCOM_CTRL
Definition skge.h:1005
PHY_BCOM_P_EXT_STAT
@ PHY_BCOM_P_EXT_STAT
Definition skge.h:1019
PHY_BCOM_RE_CTR
@ PHY_BCOM_RE_CTR
Definition skge.h:1020
PHY_BCOM_AUX_STAT
@ PHY_BCOM_AUX_STAT
Definition skge.h:1025
PHY_BCOM_ID0
@ PHY_BCOM_ID0
Definition skge.h:1007
PHY_BCOM_ID1
@ PHY_BCOM_ID1
Definition skge.h:1008
PHY_BCOM_1000T_STAT
@ PHY_BCOM_1000T_STAT
Definition skge.h:1016
PHY_BCOM_AUNE_LP
@ PHY_BCOM_AUNE_LP
Definition skge.h:1010
PHY_BCOM_FC_CTR
@ PHY_BCOM_FC_CTR
Definition skge.h:1021
PHY_BCOM_AUNE_ADV
@ PHY_BCOM_AUNE_ADV
Definition skge.h:1009
PHY_BCOM_NEPG
@ PHY_BCOM_NEPG
Definition skge.h:1012
PHY_BCOM_NEPG_LP
@ PHY_BCOM_NEPG_LP
Definition skge.h:1013
PHY_BCOM_1000T_CTRL
@ PHY_BCOM_1000T_CTRL
Definition skge.h:1015
PHY_BCOM_P_EXT_CTRL
@ PHY_BCOM_P_EXT_CTRL
Definition skge.h:1018
PHY_BCOM_INT_STAT
@ PHY_BCOM_INT_STAT
Definition skge.h:1026
skge_write32
static void skge_write32(const struct skge_hw *hw, int reg, u32 val)
Definition skge.h:2532
PHY_B_AN_ASP
@ PHY_B_AN_ASP
Definition skge.h:1263
PHY_B_AN_PC
@ PHY_B_AN_PC
Definition skge.h:1264
PHY_B_AN_RF
@ PHY_B_AN_RF
Definition skge.h:1261
PHY_M_EC_DOWN_S_ENA
@ PHY_M_EC_DOWN_S_ENA
Definition skge.h:1495
PHY_M_EC_ENA_BC_EXT
@ PHY_M_EC_ENA_BC_EXT
Definition skge.h:1485
PHY_M_EC_DTE_D_ENA
@ PHY_M_EC_DTE_D_ENA
Definition skge.h:1500
PHY_M_EC_RX_TIM_CT
@ PHY_M_EC_RX_TIM_CT
Definition skge.h:1497
PHY_M_EC_TRANS_DIS
@ PHY_M_EC_TRANS_DIS
Definition skge.h:1502
PHY_M_EC_FIB_AN_ENA
@ PHY_M_EC_FIB_AN_ENA
Definition skge.h:1499
PHY_M_EC_M_DSC_MSK
@ PHY_M_EC_M_DSC_MSK
Definition skge.h:1489
PHY_M_EC_ENA_LIN_LB
@ PHY_M_EC_ENA_LIN_LB
Definition skge.h:1486
PHY_M_EC_S_DSC_MSK
@ PHY_M_EC_S_DSC_MSK
Definition skge.h:1491
PHY_M_EC_DIS_LINK_P
@ PHY_M_EC_DIS_LINK_P
Definition skge.h:1488
PHY_M_EC_M_DSC_MSK2
@ PHY_M_EC_M_DSC_MSK2
Definition skge.h:1493
PHY_M_EC_MAC_S_MSK
@ PHY_M_EC_MAC_S_MSK
Definition skge.h:1498
PHY_M_EC_TX_TIM_CT
@ PHY_M_EC_TX_TIM_CT
Definition skge.h:1501
PHY_M_LEDC_PULS_MSK
@ PHY_M_LEDC_PULS_MSK
Definition skge.h:1519
PHY_M_LEDC_DP_C_LSB
@ PHY_M_LEDC_DP_C_LSB
Definition skge.h:1522
PHY_M_LEDC_BL_R_MSK
@ PHY_M_LEDC_BL_R_MSK
Definition skge.h:1521
PHY_M_LEDC_TX_C_LSB
@ PHY_M_LEDC_TX_C_LSB
Definition skge.h:1523
PHY_M_LEDC_LK_C_MSK
@ PHY_M_LEDC_LK_C_MSK
Definition skge.h:1524
PHY_M_LEDC_DIS_LED
@ PHY_M_LEDC_DIS_LED
Definition skge.h:1518
PHY_M_LEDC_F_INT
@ PHY_M_LEDC_F_INT
Definition skge.h:1520
gma_write16
static void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
Definition skge.h:2607
BMU_UDP_CHECK
@ BMU_UDP_CHECK
Definition skge.h:392
BMU_BBC
@ BMU_BBC
Definition skge.h:393
BMU_EOF
@ BMU_EOF
Definition skge.h:378
BMU_TCP_CHECK
@ BMU_TCP_CHECK
Definition skge.h:391
BMU_STAT_VAL
@ BMU_STAT_VAL
Definition skge.h:387
BMU_STFWD
@ BMU_STFWD
Definition skge.h:382
BMU_TIST_VAL
@ BMU_TIST_VAL
Definition skge.h:388
BMU_SW
@ BMU_SW
Definition skge.h:384
BMU_OWN
@ BMU_OWN
Definition skge.h:376
BMU_CHECK
@ BMU_CHECK
Definition skge.h:390
BMU_NO_FCS
@ BMU_NO_FCS
Definition skge.h:383
BMU_DEV_0
@ BMU_DEV_0
Definition skge.h:386
BMU_IRQ_EOF
@ BMU_IRQ_EOF
Definition skge.h:380
BMU_IRQ_EOB
@ BMU_IRQ_EOB
Definition skge.h:379
BMU_STF
@ BMU_STF
Definition skge.h:377
GM_SMI_CT_PHY_A_MSK
@ GM_SMI_CT_PHY_A_MSK
Definition skge.h:1862
GM_SMI_CT_OP_RD
@ GM_SMI_CT_OP_RD
Definition skge.h:1864
GM_SMI_CT_REG_A_MSK
@ GM_SMI_CT_REG_A_MSK
Definition skge.h:1863
GM_SMI_CT_BUSY
@ GM_SMI_CT_BUSY
Definition skge.h:1866
GM_SMI_CT_RD_VAL
@ GM_SMI_CT_RD_VAL
Definition skge.h:1865
GM_TX_CTRL
@ GM_TX_CTRL
Definition skge.h:1679
GM_TR_IRQ_SRC
@ GM_TR_IRQ_SRC
Definition skge.h:1701
GM_RX_IRQ_MSK
@ GM_RX_IRQ_MSK
Definition skge.h:1705
GM_SRC_ADDR_2H
@ GM_SRC_ADDR_2H
Definition skge.h:1690
GM_RX_CTRL
@ GM_RX_CTRL
Definition skge.h:1680
GM_MC_ADDR_H1
@ GM_MC_ADDR_H1
Definition skge.h:1693
GM_RX_IRQ_SRC
@ GM_RX_IRQ_SRC
Definition skge.h:1700
GM_SMI_CTRL
@ GM_SMI_CTRL
Definition skge.h:1709
GM_SRC_ADDR_2L
@ GM_SRC_ADDR_2L
Definition skge.h:1688
GM_SRC_ADDR_1H
@ GM_SRC_ADDR_1H
Definition skge.h:1687
GM_SRC_ADDR_1L
@ GM_SRC_ADDR_1L
Definition skge.h:1685
GM_GP_STAT
@ GM_GP_STAT
Definition skge.h:1677
GM_TR_IRQ_MSK
@ GM_TR_IRQ_MSK
Definition skge.h:1706
GM_MC_ADDR_H4
@ GM_MC_ADDR_H4
Definition skge.h:1696
GM_MC_ADDR_H3
@ GM_MC_ADDR_H3
Definition skge.h:1695
GM_TX_IRQ_MSK
@ GM_TX_IRQ_MSK
Definition skge.h:1704
GM_SRC_ADDR_2M
@ GM_SRC_ADDR_2M
Definition skge.h:1689
GM_TX_FLOW_CTRL
@ GM_TX_FLOW_CTRL
Definition skge.h:1681
GM_TX_IRQ_SRC
@ GM_TX_IRQ_SRC
Definition skge.h:1699
GM_MC_ADDR_H2
@ GM_MC_ADDR_H2
Definition skge.h:1694
GM_SRC_ADDR_1M
@ GM_SRC_ADDR_1M
Definition skge.h:1686
GM_PHY_ADDR
@ GM_PHY_ADDR
Definition skge.h:1711
GM_TX_PARAM
@ GM_TX_PARAM
Definition skge.h:1682
GM_SERIAL_MODE
@ GM_SERIAL_MODE
Definition skge.h:1683
GM_GP_CTRL
@ GM_GP_CTRL
Definition skge.h:1678
GM_SMI_DATA
@ GM_SMI_DATA
Definition skge.h:1710
PHY_X_EX_HD
@ PHY_X_EX_HD
Definition skge.h:1168
PHY_X_EX_FD
@ PHY_X_EX_FD
Definition skge.h:1167
GM_TXF_ABO_COL
@ GM_TXF_ABO_COL
Definition skge.h:1763
GM_RXF_MC_OK
@ GM_RXF_MC_OK
Definition skge.h:1726
GM_RXE_FRAG
@ GM_RXE_FRAG
Definition skge.h:1734
GM_RXF_1023B
@ GM_RXF_1023B
Definition skge.h:1739
GM_RXO_OK_LO
@ GM_RXO_OK_LO
Definition skge.h:1729
GM_RXF_MPAUSE
@ GM_RXF_MPAUSE
Definition skge.h:1725
GM_RXF_JAB_PKT
@ GM_RXF_JAB_PKT
Definition skge.h:1743
GM_RXF_SHT
@ GM_RXF_SHT
Definition skge.h:1733
GM_RXF_BC_OK
@ GM_RXF_BC_OK
Definition skge.h:1724
GM_TXF_UC_OK
@ GM_TXF_UC_OK
Definition skge.h:1747
GM_TXE_FIFO_UR
@ GM_TXE_FIFO_UR
Definition skge.h:1766
GM_TXF_MAX_SZ
@ GM_TXF_MAX_SZ
Definition skge.h:1759
GM_RXO_OK_HI
@ GM_RXO_OK_HI
Definition skge.h:1730
GM_TXF_127B
@ GM_TXF_127B
Definition skge.h:1754
GM_TXF_COL
@ GM_TXF_COL
Definition skge.h:1761
GM_TXF_64B
@ GM_TXF_64B
Definition skge.h:1753
GM_RXF_127B
@ GM_RXF_127B
Definition skge.h:1736
GM_TXF_BC_OK
@ GM_TXF_BC_OK
Definition skge.h:1748
GM_RXF_UC_OK
@ GM_RXF_UC_OK
Definition skge.h:1723
GM_TXF_255B
@ GM_TXF_255B
Definition skge.h:1755
GM_RXE_FIFO_OV
@ GM_RXE_FIFO_OV
Definition skge.h:1745
GM_RXF_FCS_ERR
@ GM_RXF_FCS_ERR
Definition skge.h:1727
GM_RXF_MAX_SZ
@ GM_RXF_MAX_SZ
Definition skge.h:1741
GM_RXF_LNG_ERR
@ GM_RXF_LNG_ERR
Definition skge.h:1742
GM_RXF_1518B
@ GM_RXF_1518B
Definition skge.h:1740
GM_TXF_MUL_COL
@ GM_TXF_MUL_COL
Definition skge.h:1764
GM_TXF_1518B
@ GM_TXF_1518B
Definition skge.h:1758
GM_TXO_OK_LO
@ GM_TXO_OK_LO
Definition skge.h:1751
GM_TXF_MPAUSE
@ GM_TXF_MPAUSE
Definition skge.h:1749
GM_TXF_511B
@ GM_TXF_511B
Definition skge.h:1756
GM_TXF_MC_OK
@ GM_TXF_MC_OK
Definition skge.h:1750
GM_RXF_64B
@ GM_RXF_64B
Definition skge.h:1735
GM_TXF_LAT_COL
@ GM_TXF_LAT_COL
Definition skge.h:1762
GM_TXO_OK_HI
@ GM_TXO_OK_HI
Definition skge.h:1752
GM_RXO_ERR_LO
@ GM_RXO_ERR_LO
Definition skge.h:1731
GM_TXF_SNG_COL
@ GM_TXF_SNG_COL
Definition skge.h:1765
GM_RXO_ERR_HI
@ GM_RXO_ERR_HI
Definition skge.h:1732
GM_RXF_255B
@ GM_RXF_255B
Definition skge.h:1737
GM_RXF_511B
@ GM_RXF_511B
Definition skge.h:1738
GM_TXF_1023B
@ GM_TXF_1023B
Definition skge.h:1757
PHY_CT_ISOL
@ PHY_CT_ISOL
Definition skge.h:1077
PHY_CT_LOOP
@ PHY_CT_LOOP
Definition skge.h:1073
PHY_CT_RE_CFG
@ PHY_CT_RE_CFG
Definition skge.h:1078
PHY_CT_SPS_LSB
@ PHY_CT_SPS_LSB
Definition skge.h:1074
PHY_CT_ANE
@ PHY_CT_ANE
Definition skge.h:1075
PHY_CT_COL_TST
@ PHY_CT_COL_TST
Definition skge.h:1080
PHY_CT_DUP_MD
@ PHY_CT_DUP_MD
Definition skge.h:1079
PHY_CT_PDOWN
@ PHY_CT_PDOWN
Definition skge.h:1076
PHY_CT_SPS_MSB
@ PHY_CT_SPS_MSB
Definition skge.h:1081
PHY_CT_RESET
@ PHY_CT_RESET
Definition skge.h:1072
XM_MMU_ENA_RX
@ XM_MMU_ENA_RX
Definition skge.h:2178
XM_MMU_GMII_LOOP
@ XM_MMU_GMII_LOOP
Definition skge.h:2177
XM_MMU_PHY_RDY
@ XM_MMU_PHY_RDY
Definition skge.h:2168
XM_MMU_ENA_TX
@ XM_MMU_ENA_TX
Definition skge.h:2179
XM_MMU_NO_PRE
@ XM_MMU_NO_PRE
Definition skge.h:2174
XM_MMU_SIM_COL
@ XM_MMU_SIM_COL
Definition skge.h:2173
XM_MMU_FRC_COL
@ XM_MMU_FRC_COL
Definition skge.h:2172
XM_MMU_RAT_CTRL
@ XM_MMU_RAT_CTRL
Definition skge.h:2176
XM_MMU_GMII_FD
@ XM_MMU_GMII_FD
Definition skge.h:2175
XM_MMU_IGN_PF
@ XM_MMU_IGN_PF
Definition skge.h:2170
XM_MMU_MAC_LB
@ XM_MMU_MAC_LB
Definition skge.h:2171
XM_MMU_PHY_BUSY
@ XM_MMU_PHY_BUSY
Definition skge.h:2169
GMF_RP_TST_ON
@ GMF_RP_TST_ON
Definition skge.h:1914
GMF_RP_TST_OFF
@ GMF_RP_TST_OFF
Definition skge.h:1915
GMF_WP_STEP
@ GMF_WP_STEP
Definition skge.h:1912
GMF_CLI_RX_FO
@ GMF_CLI_RX_FO
Definition skge.h:1919
RX_GMF_FL_THR_DEF
@ RX_GMF_FL_THR_DEF
Definition skge.h:1926
GMF_RP_STEP
@ GMF_RP_STEP
Definition skge.h:1916
GMF_OPER_OFF
@ GMF_OPER_OFF
Definition skge.h:1922
GMF_RST_CLR
@ GMF_RST_CLR
Definition skge.h:1923
GMF_OPER_ON
@ GMF_OPER_ON
Definition skge.h:1921
GMF_RST_SET
@ GMF_RST_SET
Definition skge.h:1924
GMF_RX_F_FL_OFF
@ GMF_RX_F_FL_OFF
Definition skge.h:1918
GMF_CLI_RX_FC
@ GMF_CLI_RX_FC
Definition skge.h:1920
GMF_WP_TST_OFF
@ GMF_WP_TST_OFF
Definition skge.h:1911
GMF_WP_TST_ON
@ GMF_WP_TST_ON
Definition skge.h:1910
GMF_RX_F_FL_ON
@ GMF_RX_F_FL_ON
Definition skge.h:1917
CFG_CHIP_R_MSK
@ CFG_CHIP_R_MSK
Definition skge.h:310
CFG_SNG_MAC
@ CFG_SNG_MAC
Definition skge.h:313
CFG_DIS_M2_CLK
@ CFG_DIS_M2_CLK
Definition skge.h:312
PHY_X_RS_HD
@ PHY_X_RS_HD
Definition skge.h:1174
PHY_X_RS_PAUSE
@ PHY_X_RS_PAUSE
Definition skge.h:1173
PHY_X_RS_ABLMIS
@ PHY_X_RS_ABLMIS
Definition skge.h:1176
PHY_X_RS_FD
@ PHY_X_RS_FD
Definition skge.h:1175
PHY_X_RS_PAUMIS
@ PHY_X_RS_PAUMIS
Definition skge.h:1177
SK_PHY_MARV_COPPER
@ SK_PHY_MARV_COPPER
Definition skge.h:577
SK_PHY_NAT
@ SK_PHY_NAT
Definition skge.h:576
SK_PHY_BCOM
@ SK_PHY_BCOM
Definition skge.h:574
SK_PHY_LONE
@ SK_PHY_LONE
Definition skge.h:575
SK_PHY_XMAC
@ SK_PHY_XMAC
Definition skge.h:573
SK_PHY_MARV_FIBER
@ SK_PHY_MARV_FIBER
Definition skge.h:578
MA_RST_SET
@ MA_RST_SET
Definition skge.h:434
MA_FOE_ON
@ MA_FOE_ON
Definition skge.h:431
MA_FOE_OFF
@ MA_FOE_OFF
Definition skge.h:432
MA_RST_CLR
@ MA_RST_CLR
Definition skge.h:433
skge_read16
static u16 skge_read16(const struct skge_hw *hw, int reg)
Definition skge.h:2522
RB_END
@ RB_END
Definition skge.h:540
RB_RX_LTPP
@ RB_RX_LTPP
Definition skge.h:544
RB_RX_LTHP
@ RB_RX_LTHP
Definition skge.h:546
RB_RX_UTHP
@ RB_RX_UTHP
Definition skge.h:545
RB_LEV
@ RB_LEV
Definition skge.h:549
RB_RP
@ RB_RP
Definition skge.h:542
RB_TST1
@ RB_TST1
Definition skge.h:551
RB_RX_UTPP
@ RB_RX_UTPP
Definition skge.h:543
RB_CTRL
@ RB_CTRL
Definition skge.h:550
RB_TST2
@ RB_TST2
Definition skge.h:552
RB_WP
@ RB_WP
Definition skge.h:541
RB_START
@ RB_START
Definition skge.h:539
RB_PC
@ RB_PC
Definition skge.h:548
PHY_M_AN_1000X_AHD
@ PHY_M_AN_1000X_AHD
Definition skge.h:1367
PHY_M_AN_1000X_AFD
@ PHY_M_AN_1000X_AFD
Definition skge.h:1368
PHY_M_AN_PC_X
@ PHY_M_AN_PC_X
Definition skge.h:1366
PHY_M_AN_ASP_X
@ PHY_M_AN_ASP_X
Definition skge.h:1365
BSC_STOP
@ BSC_STOP
Definition skge.h:399
BSC_START
@ BSC_START
Definition skge.h:398
MFF_WSP_T_OFF
@ MFF_WSP_T_OFF
Definition skge.h:662
MFF_WSP_T_ON
@ MFF_WSP_T_ON
Definition skge.h:661
MFF_PC_T_OFF
@ MFF_PC_T_OFF
Definition skge.h:666
MFF_PC_T_ON
@ MFF_PC_T_ON
Definition skge.h:665
MFF_WSP_INC
@ MFF_WSP_INC
Definition skge.h:663
MFF_PC_DEC
@ MFF_PC_DEC
Definition skge.h:664
MFF_PC_INC
@ MFF_PC_INC
Definition skge.h:667
xm_read32
static u32 xm_read32(const struct skge_hw *hw, int port, int reg)
Definition skge.h:2552
MFF_WP_T_ON
@ MFF_WP_T_ON
Definition skge.h:673
MFF_RP_T_ON
@ MFF_RP_T_ON
Definition skge.h:677
MFF_WP_T_OFF
@ MFF_WP_T_OFF
Definition skge.h:674
MFF_WP_INC
@ MFF_WP_INC
Definition skge.h:675
MFF_RP_T_OFF
@ MFF_RP_T_OFF
Definition skge.h:678
MFF_RP_DEC
@ MFF_RP_DEC
Definition skge.h:679
XM_HW_GMII_MD
@ XM_HW_GMII_MD
Definition skge.h:2258
XM_HW_GEN_EOP
@ XM_HW_GEN_EOP
Definition skge.h:2256
XM_HW_COM4SIG
@ XM_HW_COM4SIG
Definition skge.h:2257
XM_MD_ENA_BE
@ XM_MD_ENA_BE
Definition skge.h:2331
XM_MD_RX_ERR
@ XM_MD_RX_ERR
Definition skge.h:2326
XM_MD_SPOE_E
@ XM_MD_SPOE_E
Definition skge.h:2304
XM_MD_ENA_REJ
@ XM_MD_ENA_REJ
Definition skge.h:2303
XM_MD_FRF
@ XM_MD_FRF
Definition skge.h:2333
XM_MD_CAA
@ XM_MD_CAA
Definition skge.h:2320
XM_MD_SPOH_I
@ XM_MD_SPOH_I
Definition skge.h:2315
XM_MD_RX_CRCE
@ XM_MD_RX_CRCE
Definition skge.h:2325
XM_MD_CSA
@ XM_MD_CSA
Definition skge.h:2319
XM_MD_RX_IRLE
@ XM_MD_RX_IRLE
Definition skge.h:2323
XM_MD_RX_RUNT
@ XM_MD_RX_RUNT
Definition skge.h:2322
XM_MD_RX_MCTRL
@ XM_MD_RX_MCTRL
Definition skge.h:2321
XM_MD_DIS_MC
@ XM_MD_DIS_MC
Definition skge.h:2328
XM_MD_SPOL_I
@ XM_MD_SPOL_I
Definition skge.h:2313
XM_MD_ATS
@ XM_MD_ATS
Definition skge.h:2312
XM_MD_DIS_UC
@ XM_MD_DIS_UC
Definition skge.h:2327
XM_MD_SPOFF_I
@ XM_MD_SPOFF_I
Definition skge.h:2307
XM_MD_TX_PAUSE
@ XM_MD_TX_PAUSE
Definition skge.h:2311
XM_MD_LE_STW
@ XM_MD_LE_STW
Definition skge.h:2309
XM_MD_FTF
@ XM_MD_FTF
Definition skge.h:2332
XM_MD_TX_REP
@ XM_MD_TX_REP
Definition skge.h:2306
XM_MD_RX_LONG
@ XM_MD_RX_LONG
Definition skge.h:2324
XM_MD_DIS_BC
@ XM_MD_DIS_BC
Definition skge.h:2329
XM_MD_ENA_PROM
@ XM_MD_ENA_PROM
Definition skge.h:2330
XM_MD_CAP
@ XM_MD_CAP
Definition skge.h:2317
XM_MD_TX_CONT
@ XM_MD_TX_CONT
Definition skge.h:2310
XM_MD_ENA_HASH
@ XM_MD_ENA_HASH
Definition skge.h:2318
PULS_1300MS
@ PULS_1300MS
Definition skge.h:1548
PULS_670MS
@ PULS_670MS
Definition skge.h:1547
PULS_42MS
@ PULS_42MS
Definition skge.h:1543
PULS_21MS
@ PULS_21MS
Definition skge.h:1542
PULS_340MS
@ PULS_340MS
Definition skge.h:1546
PULS_NO_STR
@ PULS_NO_STR
Definition skge.h:1541
PULS_84MS
@ PULS_84MS
Definition skge.h:1544
PULS_170MS
@ PULS_170MS
Definition skge.h:1545
LED_T_OFF
@ LED_T_OFF
Definition skge.h:708
LED_T_ON
@ LED_T_ON
Definition skge.h:707
LED_T_STEP
@ LED_T_STEP
Definition skge.h:709
PHY_M_FELP_LED2_MSK
@ PHY_M_FELP_LED2_MSK
Definition skge.h:1625
PHY_M_FELP_LED0_MSK
@ PHY_M_FELP_LED0_MSK
Definition skge.h:1627
PHY_M_FELP_LED1_MSK
@ PHY_M_FELP_LED1_MSK
Definition skge.h:1626
MFF_ENA_LOOPB
@ MFF_ENA_LOOPB
Definition skge.h:649
MFF_ENA_W4E
@ MFF_ENA_W4E
Definition skge.h:646
MFF_DIS_LOOPB
@ MFF_DIS_LOOPB
Definition skge.h:650
MFF_CLR_MAC_RST
@ MFF_CLR_MAC_RST
Definition skge.h:651
MFF_CLR_PERR
@ MFF_CLR_PERR
Definition skge.h:641
MFF_ENA_PKT_REC
@ MFF_ENA_PKT_REC
Definition skge.h:643
MFF_SET_MAC_RST
@ MFF_SET_MAC_RST
Definition skge.h:652
MFF_DIS_W4E
@ MFF_DIS_W4E
Definition skge.h:647
MFF_DIS_PKT_REC
@ MFF_DIS_PKT_REC
Definition skge.h:644
MFF_TX_CTRL_DEF
@ MFF_TX_CTRL_DEF
Definition skge.h:654
PHY_AN_RF
@ PHY_AN_RF
Definition skge.h:1129
PHY_AN_10HALF
@ PHY_AN_10HALF
Definition skge.h:1137
PHY_AN_100FULL
@ PHY_AN_100FULL
Definition skge.h:1134
PHY_AN_CSMA
@ PHY_AN_CSMA
Definition skge.h:1138
PHY_AN_NXT_PG
@ PHY_AN_NXT_PG
Definition skge.h:1127
PHY_AN_100HALF
@ PHY_AN_100HALF
Definition skge.h:1135
PHY_AN_PAUSE_CAP
@ PHY_AN_PAUSE_CAP
Definition skge.h:1132
PHY_AN_FULL
@ PHY_AN_FULL
Definition skge.h:1140
PHY_AN_PAUSE_ASYM
@ PHY_AN_PAUSE_ASYM
Definition skge.h:1131
PHY_AN_ALL
@ PHY_AN_ALL
Definition skge.h:1141
PHY_AN_10FULL
@ PHY_AN_10FULL
Definition skge.h:1136
PHY_AN_100BASE4
@ PHY_AN_100BASE4
Definition skge.h:1133
PHY_AN_ACK
@ PHY_AN_ACK
Definition skge.h:1128
PHY_AN_SEL
@ PHY_AN_SEL
Definition skge.h:1139
XM_RX_LENERR_OK
@ XM_RX_LENERR_OK
Definition skge.h:2208
XM_RX_SELF_RX
@ XM_RX_SELF_RX
Definition skge.h:2215
XM_RX_STRIP_FCS
@ XM_RX_STRIP_FCS
Definition skge.h:2214
XM_RX_TP_MD
@ XM_RX_TP_MD
Definition skge.h:2213
XM_RX_IPG_CAP
@ XM_RX_IPG_CAP
Definition skge.h:2212
XM_RX_DIS_CEXT
@ XM_RX_DIS_CEXT
Definition skge.h:2218
XM_RX_BIG_PK_OK
@ XM_RX_BIG_PK_OK
Definition skge.h:2210
XM_RX_STRIP_PAD
@ XM_RX_STRIP_PAD
Definition skge.h:2217
XM_RX_SAM_LINE
@ XM_RX_SAM_LINE
Definition skge.h:2216
PHY_MARV_INT_MASK
@ PHY_MARV_INT_MASK
Definition skge.h:1049
PHY_MARV_1000T_CTRL
@ PHY_MARV_1000T_CTRL
Definition skge.h:1044
PHY_MARV_ID1
@ PHY_MARV_ID1
Definition skge.h:1037
PHY_MARV_CTRL
@ PHY_MARV_CTRL
Definition skge.h:1034
PHY_MARV_STAT
@ PHY_MARV_STAT
Definition skge.h:1035
PHY_MARV_LED_CTRL
@ PHY_MARV_LED_CTRL
Definition skge.h:1055
PHY_MARV_FE_VCT_TX
@ PHY_MARV_FE_VCT_TX
Definition skge.h:1066
PHY_MARV_PHY_STAT
@ PHY_MARV_PHY_STAT
Definition skge.h:1048
PHY_MARV_INT_STAT
@ PHY_MARV_INT_STAT
Definition skge.h:1050
PHY_MARV_NEPG
@ PHY_MARV_NEPG
Definition skge.h:1041
PHY_MARV_FE_SPEC_2
@ PHY_MARV_FE_SPEC_2
Definition skge.h:1068
PHY_MARV_RXE_CNT
@ PHY_MARV_RXE_CNT
Definition skge.h:1052
PHY_MARV_AUNE_EXP
@ PHY_MARV_AUNE_EXP
Definition skge.h:1040
PHY_MARV_FE_LED_PAR
@ PHY_MARV_FE_LED_PAR
Definition skge.h:1064
PHY_MARV_PHY_CTRL
@ PHY_MARV_PHY_CTRL
Definition skge.h:1047
PHY_MARV_CABLE_DIAG
@ PHY_MARV_CABLE_DIAG
Definition skge.h:1059
PHY_MARV_AUNE_LP
@ PHY_MARV_AUNE_LP
Definition skge.h:1039
PHY_MARV_ID0
@ PHY_MARV_ID0
Definition skge.h:1036
PHY_MARV_EXT_CTRL_2
@ PHY_MARV_EXT_CTRL_2
Definition skge.h:1057
PHY_MARV_AUNE_ADV
@ PHY_MARV_AUNE_ADV
Definition skge.h:1038
PHY_MARV_PAGE_ADDR
@ PHY_MARV_PAGE_ADDR
Definition skge.h:1060
PHY_MARV_LED_OVER
@ PHY_MARV_LED_OVER
Definition skge.h:1056
PHY_MARV_EXT_ADR
@ PHY_MARV_EXT_ADR
Definition skge.h:1053
PHY_MARV_EXT_STAT
@ PHY_MARV_EXT_STAT
Definition skge.h:1046
PHY_MARV_PAGE_DATA
@ PHY_MARV_PAGE_DATA
Definition skge.h:1061
PHY_MARV_FE_LED_SER
@ PHY_MARV_FE_LED_SER
Definition skge.h:1065
PHY_MARV_EXT_P_STAT
@ PHY_MARV_EXT_P_STAT
Definition skge.h:1058
PHY_MARV_PORT_IRQ
@ PHY_MARV_PORT_IRQ
Definition skge.h:1054
PHY_MARV_NEPG_LP
@ PHY_MARV_NEPG_LP
Definition skge.h:1042
PHY_MARV_1000T_STAT
@ PHY_MARV_1000T_STAT
Definition skge.h:1045
PHY_MARV_EXT_CTRL
@ PHY_MARV_EXT_CTRL
Definition skge.h:1051
PHY_MARV_FE_VCT_RX
@ PHY_MARV_FE_VCT_RX
Definition skge.h:1067
LED_BLK_ON
@ LED_BLK_ON
Definition skge.h:714
LED_SYNC_ON
@ LED_SYNC_ON
Definition skge.h:716
LED_ON
@ LED_ON
Definition skge.h:718
LED_BLK_OFF
@ LED_BLK_OFF
Definition skge.h:715
LED_SYNC_OFF
@ LED_SYNC_OFF
Definition skge.h:717
LED_OFF
@ LED_OFF
Definition skge.h:719
XM_TX_HI_WM
@ XM_TX_HI_WM
Definition skge.h:2079
XM_PAUSE_DA
@ XM_PAUSE_DA
Definition skge.h:2082
XM_GP_PORT
@ XM_GP_PORT
Definition skge.h:2074
XM_EXM_START
@ XM_EXM_START
Definition skge.h:2088
XM_HW_CFG
@ XM_HW_CFG
Definition skge.h:2077
XM_CTL_PARA
@ XM_CTL_PARA
Definition skge.h:2083
XM_HT_THR
@ XM_HT_THR
Definition skge.h:2081
XM_TX_IPG
@ XM_TX_IPG
Definition skge.h:2070
XM_TX_CMD
@ XM_TX_CMD
Definition skge.h:2067
XM_TX_STIME
@ XM_TX_STIME
Definition skge.h:2069
XM_TX_RT_LIM
@ XM_TX_RT_LIM
Definition skge.h:2068
XM_MAC_OPCODE
@ XM_MAC_OPCODE
Definition skge.h:2084
XM_ISRC
@ XM_ISRC
Definition skge.h:2076
XM_PHY_DATA
@ XM_PHY_DATA
Definition skge.h:2073
XM_RX_CMD
@ XM_RX_CMD
Definition skge.h:2071
XM_MAC_PTIME
@ XM_MAC_PTIME
Definition skge.h:2085
XM_PHY_ADDR
@ XM_PHY_ADDR
Definition skge.h:2072
XM_BURST
@ XM_BURST
Definition skge.h:2064
XM_1L_VLAN_TAG
@ XM_1L_VLAN_TAG
Definition skge.h:2065
XM_TX_THR
@ XM_TX_THR
Definition skge.h:2080
XM_MMU_CMD
@ XM_MMU_CMD
Definition skge.h:2062
XM_IMSK
@ XM_IMSK
Definition skge.h:2075
XM_TX_LO_WM
@ XM_TX_LO_WM
Definition skge.h:2078
XM_2L_VLAN_TAG
@ XM_2L_VLAN_TAG
Definition skge.h:2066
XM_TX_STAT
@ XM_TX_STAT
Definition skge.h:2086
XM_POFF
@ XM_POFF
Definition skge.h:2063
GM_GPSR_SPEED
@ GM_GPSR_SPEED
Definition skge.h:1772
GM_GPSR_DUPLEX
@ GM_GPSR_DUPLEX
Definition skge.h:1773
GM_GPSR_PHY_ST_CH
@ GM_GPSR_PHY_ST_CH
Definition skge.h:1781
GM_GPSR_FC_RX_DIS
@ GM_GPSR_FC_RX_DIS
Definition skge.h:1784
GM_GPSR_PART_MODE
@ GM_GPSR_PART_MODE
Definition skge.h:1783
GM_GPSR_TX_ACTIVE
@ GM_GPSR_TX_ACTIVE
Definition skge.h:1777
GM_GPSR_LINK_UP
@ GM_GPSR_LINK_UP
Definition skge.h:1775
GM_GPSR_PAUSE
@ GM_GPSR_PAUSE
Definition skge.h:1776
GM_GPSR_LAT_COL
@ GM_GPSR_LAT_COL
Definition skge.h:1779
GM_GPSR_GIG_SPEED
@ GM_GPSR_GIG_SPEED
Definition skge.h:1782
GM_GPSR_EXC_COL
@ GM_GPSR_EXC_COL
Definition skge.h:1778
GM_GPSR_FC_TX_DIS
@ GM_GPSR_FC_TX_DIS
Definition skge.h:1774
GM_GPSR_PROM_EN
@ GM_GPSR_PROM_EN
Definition skge.h:1785
GMC_H_BURST_OFF
@ GMC_H_BURST_OFF
Definition skge.h:1951
GMC_PAUSE_ON
@ GMC_PAUSE_ON
Definition skge.h:1954
GMC_F_LOOPB_ON
@ GMC_F_LOOPB_ON
Definition skge.h:1952
GMC_RST_SET
@ GMC_RST_SET
Definition skge.h:1957
GMC_RST_CLR
@ GMC_RST_CLR
Definition skge.h:1956
GMC_H_BURST_ON
@ GMC_H_BURST_ON
Definition skge.h:1950
GMC_F_LOOPB_OFF
@ GMC_F_LOOPB_OFF
Definition skge.h:1953
GMC_PAUSE_OFF
@ GMC_PAUSE_OFF
Definition skge.h:1955
PHY_B_PEC_INT_DIS
@ PHY_B_PEC_INT_DIS
Definition skge.h:1225
PHY_B_PEC_EX_IPG
@ PHY_B_PEC_EX_IPG
Definition skge.h:1235
PHY_B_PEC_EN_LTR
@ PHY_B_PEC_EN_LTR
Definition skge.h:1232
PHY_B_PEC_LED_ON
@ PHY_B_PEC_LED_ON
Definition skge.h:1233
PHY_B_PEC_3_LED
@ PHY_B_PEC_3_LED
Definition skge.h:1236
PHY_B_PEC_TX_DIS
@ PHY_B_PEC_TX_DIS
Definition skge.h:1224
PHY_B_PEC_BY_SCR
@ PHY_B_PEC_BY_SCR
Definition skge.h:1228
PHY_B_PEC_LED_OFF
@ PHY_B_PEC_LED_OFF
Definition skge.h:1234
PHY_B_PEC_MAC_PHY
@ PHY_B_PEC_MAC_PHY
Definition skge.h:1222
PHY_B_PEC_DIS_CROSS
@ PHY_B_PEC_DIS_CROSS
Definition skge.h:1223
PHY_B_PEC_BY_MLT3
@ PHY_B_PEC_BY_MLT3
Definition skge.h:1229
PHY_B_PEC_HIGH_LA
@ PHY_B_PEC_HIGH_LA
Definition skge.h:1237
PHY_B_PEC_BY_RXA
@ PHY_B_PEC_BY_RXA
Definition skge.h:1230
PHY_B_PEC_BY_45
@ PHY_B_PEC_BY_45
Definition skge.h:1227
PHY_B_PEC_F_INT
@ PHY_B_PEC_F_INT
Definition skge.h:1226
PHY_B_PEC_RES_SCR
@ PHY_B_PEC_RES_SCR
Definition skge.h:1231
LED_PAR_CTRL_ERROR
@ LED_PAR_CTRL_ERROR
Definition skge.h:1636
LED_PAR_CTRL_COLX
@ LED_PAR_CTRL_COLX
Definition skge.h:1635
LED_PAR_CTRL_COL_BL
@ LED_PAR_CTRL_COL_BL
Definition skge.h:1649
LED_PAR_CTRL_SPEED
@ LED_PAR_CTRL_SPEED
Definition skge.h:1639
LED_PAR_CTRL_LINK
@ LED_PAR_CTRL_LINK
Definition skge.h:1640
LED_PAR_CTRL_DUPLEX
@ LED_PAR_CTRL_DUPLEX
Definition skge.h:1637
LED_PAR_CTRL_LNK_AC
@ LED_PAR_CTRL_LNK_AC
Definition skge.h:1645
LED_PAR_CTRL_TX
@ LED_PAR_CTRL_TX
Definition skge.h:1641
LED_PAR_CTRL_ACT_BL
@ LED_PAR_CTRL_ACT_BL
Definition skge.h:1646
LED_PAR_CTRL_RX_BL
@ LED_PAR_CTRL_RX_BL
Definition skge.h:1648
LED_PAR_CTRL_RX
@ LED_PAR_CTRL_RX
Definition skge.h:1642
LED_PAR_CTRL_ACT
@ LED_PAR_CTRL_ACT
Definition skge.h:1643
LED_PAR_CTRL_LNK_RX
@ LED_PAR_CTRL_LNK_RX
Definition skge.h:1644
LED_PAR_CTRL_DP_COL
@ LED_PAR_CTRL_DP_COL
Definition skge.h:1638
LED_PAR_CTRL_INACT
@ LED_PAR_CTRL_INACT
Definition skge.h:1650
LED_PAR_CTRL_TX_BL
@ LED_PAR_CTRL_TX_BL
Definition skge.h:1647
LED_STOP
@ LED_STOP
Definition skge.h:699
LED_START
@ LED_START
Definition skge.h:698
LED_STATE
@ LED_STATE
Definition skge.h:700
PHY_M_EC2_FI_IMPED
@ PHY_M_EC2_FI_IMPED
Definition skge.h:1579
PHY_M_EC2_FO_AM_MSK
@ PHY_M_EC2_FO_AM_MSK
Definition skge.h:1583
PHY_M_EC2_FO_M_CLK
@ PHY_M_EC2_FO_M_CLK
Definition skge.h:1581
PHY_M_EC2_FO_IMPED
@ PHY_M_EC2_FO_IMPED
Definition skge.h:1580
PHY_M_EC2_FO_BOOST
@ PHY_M_EC2_FO_BOOST
Definition skge.h:1582
XM_ST_SGN_COL
@ XM_ST_SGN_COL
Definition skge.h:2288
XM_ST_BYTE_CNT
@ XM_ST_BYTE_CNT
Definition skge.h:2275
XM_ST_MC
@ XM_ST_MC
Definition skge.h:2282
XM_ST_TX_UR
@ XM_ST_TX_UR
Definition skge.h:2284
XM_ST_LAT_COL
@ XM_ST_LAT_COL
Definition skge.h:2286
XM_ST_MUL_COL
@ XM_ST_MUL_COL
Definition skge.h:2287
XM_ST_UC
@ XM_ST_UC
Definition skge.h:2283
XM_ST_BC
@ XM_ST_BC
Definition skge.h:2281
XM_ST_BURST
@ XM_ST_BURST
Definition skge.h:2279
XM_ST_EX_DEF
@ XM_ST_EX_DEF
Definition skge.h:2278
XM_ST_EX_COL
@ XM_ST_EX_COL
Definition skge.h:2277
XM_ST_DEFER
@ XM_ST_DEFER
Definition skge.h:2280
XM_ST_RETRY_CNT
@ XM_ST_RETRY_CNT
Definition skge.h:2276
XM_ST_VALID
@ XM_ST_VALID
Definition skge.h:2274
XM_ST_CS_ERR
@ XM_ST_CS_ERR
Definition skge.h:2285
PHY_M_PC_EN_DET_PLUS
@ PHY_M_PC_EN_DET_PLUS
Definition skge.h:1407
PHY_M_PC_EN_DET
@ PHY_M_PC_EN_DET
Definition skge.h:1406
XMR_127B_OV
@ XMR_127B_OV
Definition skge.h:2358
XMR_MCTRL_OV
@ XMR_MCTRL_OV
Definition skge.h:2376
XMR_BURST
@ XMR_BURST
Definition skge.h:2373
XMR_SHT_ERR_OV
@ XMR_SHT_ERR_OV
Definition skge.h:2366
XMR_INV_MP
@ XMR_INV_MP
Definition skge.h:2375
XMR_CAR_ERR_OV
@ XMR_CAR_ERR_OV
Definition skge.h:2368
XMR_OK_LO_OV
@ XMR_OK_LO_OV
Definition skge.h:2381
XMR_BC_OK_OV
@ XMR_BC_OK_OV
Definition skge.h:2380
XMR_UC_OK_OV
@ XMR_UC_OK_OV
Definition skge.h:2378
XMR_MAX_SZ_OV
@ XMR_MAX_SZ_OV
Definition skge.h:2354
XMR_FIFO_OV
@ XMR_FIFO_OV
Definition skge.h:2370
XMR_INV_MOC
@ XMR_INV_MOC
Definition skge.h:2374
XMR_OK_HI_OV
@ XMR_OK_HI_OV
Definition skge.h:2382
XMR_FRA_ERR_OV
@ XMR_FRA_ERR_OV
Definition skge.h:2371
XMR_UTIL_OV
@ XMR_UTIL_OV
Definition skge.h:2360
XMR_FCS_ERR_OV
@ XMR_FCS_ERR_OV
Definition skge.h:2363
XMR_UTIL_UR
@ XMR_UTIL_UR
Definition skge.h:2361
XMR_SYM_ERR_OV
@ XMR_SYM_ERR_OV
Definition skge.h:2367
XMR_RUNT_OV
@ XMR_RUNT_OV
Definition skge.h:2365
XMR_1023B_OV
@ XMR_1023B_OV
Definition skge.h:2355
XMR_MC_OK_OV
@ XMR_MC_OK_OV
Definition skge.h:2379
XMR_LNG_ERR_OV
@ XMR_LNG_ERR_OV
Definition skge.h:2364
XMR_JAB_PKT_OV
@ XMR_JAB_PKT_OV
Definition skge.h:2369
XMR_255B_OV
@ XMR_255B_OV
Definition skge.h:2357
XMR_CEX_ERR_OV
@ XMR_CEX_ERR_OV
Definition skge.h:2362
XMR_OK_OV
@ XMR_OK_OV
Definition skge.h:2383
XMR_511B_OV
@ XMR_511B_OV
Definition skge.h:2356
XMR_64B_OV
@ XMR_64B_OV
Definition skge.h:2359
XMR_FMISS_OV
@ XMR_FMISS_OV
Definition skge.h:2372
XMR_MPAUSE_OV
@ XMR_MPAUSE_OV
Definition skge.h:2377
PHY_ADDR_XMAC
@ PHY_ADDR_XMAC
Definition skge.h:583
PHY_ADDR_BCOM
@ PHY_ADDR_BCOM
Definition skge.h:584
PHY_ADDR_MARV
@ PHY_ADDR_MARV
Definition skge.h:587
PHY_B_1000S_LRS
@ PHY_B_1000S_LRS
Definition skge.h:1204
PHY_B_1000S_MSR
@ PHY_B_1000S_MSR
Definition skge.h:1203
PHY_B_1000S_MSF
@ PHY_B_1000S_MSF
Definition skge.h:1202
PHY_B_1000S_IEC
@ PHY_B_1000S_IEC
Definition skge.h:1209
PHY_B_1000S_RRS
@ PHY_B_1000S_RRS
Definition skge.h:1205
PHY_B_1000S_LP_FD
@ PHY_B_1000S_LP_FD
Definition skge.h:1206
PHY_B_1000S_LP_HD
@ PHY_B_1000S_LP_HD
Definition skge.h:1207
PHY_M_1000C_AHD
@ PHY_M_1000C_AHD
Definition skge.h:1386
PHY_M_1000C_TEST
@ PHY_M_1000C_TEST
Definition skge.h:1381
PHY_M_1000C_MPD
@ PHY_M_1000C_MPD
Definition skge.h:1384
PHY_M_1000C_MSE
@ PHY_M_1000C_MSE
Definition skge.h:1382
PHY_M_1000C_MSC
@ PHY_M_1000C_MSC
Definition skge.h:1383
PHY_M_1000C_AFD
@ PHY_M_1000C_AFD
Definition skge.h:1385
GMT_ST_CLR_IRQ
@ GMT_ST_CLR_IRQ
Definition skge.h:1945
GMT_ST_START
@ GMT_ST_START
Definition skge.h:1943
GMT_ST_STOP
@ GMT_ST_STOP
Definition skge.h:1944
TX_MFF_CTRL2
@ TX_MFF_CTRL2
Definition skge.h:845
TX_MFF_WAF
@ TX_MFF_WAF
Definition skge.h:843
TX_LED_VAL
@ TX_LED_VAL
Definition skge.h:850
TX_MFF_WSP
@ TX_MFF_WSP
Definition skge.h:838
TX_MFF_WP
@ TX_MFF_WP
Definition skge.h:837
TX_MFF_LEV
@ TX_MFF_LEV
Definition skge.h:841
TX_LED_TST
@ TX_LED_TST
Definition skge.h:852
TX_MFF_TST1
@ TX_MFF_TST1
Definition skge.h:846
TX_MFF_EA
@ TX_MFF_EA
Definition skge.h:836
TX_MFF_PC
@ TX_MFF_PC
Definition skge.h:840
TX_MFF_RP
@ TX_MFF_RP
Definition skge.h:839
TX_MFF_TST2
@ TX_MFF_TST2
Definition skge.h:847
TX_MFF_CTRL1
@ TX_MFF_CTRL1
Definition skge.h:842
TX_LED_CTRL
@ TX_LED_CTRL
Definition skge.h:851
TX_LED_INI
@ TX_LED_INI
Definition skge.h:849
IS_NO_TIST_M1
@ IS_NO_TIST_M1
Definition skge.h:281
IS_M1_PAR_ERR
@ IS_M1_PAR_ERR
Definition skge.h:285
IS_IRQ_TIST_OV
@ IS_IRQ_TIST_OV
Definition skge.h:275
IS_IRQ_STAT
@ IS_IRQ_STAT
Definition skge.h:278
IS_R1_PAR_ERR
@ IS_R1_PAR_ERR
Definition skge.h:287
IS_NO_STAT_M1
@ IS_NO_STAT_M1
Definition skge.h:279
IS_ERR_MSK
@ IS_ERR_MSK
Definition skge.h:290
IS_M2_PAR_ERR
@ IS_M2_PAR_ERR
Definition skge.h:286
IS_IRQ_MST_ERR
@ IS_IRQ_MST_ERR
Definition skge.h:277
IS_RAM_WR_PAR
@ IS_RAM_WR_PAR
Definition skge.h:284
IS_NO_STAT_M2
@ IS_NO_STAT_M2
Definition skge.h:280
IS_NO_TIST_M2
@ IS_NO_TIST_M2
Definition skge.h:282
IS_R2_PAR_ERR
@ IS_R2_PAR_ERR
Definition skge.h:288
IS_RAM_RD_PAR
@ IS_RAM_RD_PAR
Definition skge.h:283
IS_IRQ_SENSOR
@ IS_IRQ_SENSOR
Definition skge.h:276
gma_read32
static u32 gma_read32(const struct skge_hw *hw, int port, int reg)
Definition skge.h:2601
pause_control
pause_control
Definition skge.h:2477
FLOW_MODE_NONE
@ FLOW_MODE_NONE
Definition skge.h:2478
FLOW_MODE_SYMMETRIC
@ FLOW_MODE_SYMMETRIC
Definition skge.h:2480
FLOW_MODE_LOC_SEND
@ FLOW_MODE_LOC_SEND
Definition skge.h:2479
FLOW_MODE_SYM_OR_REM
@ FLOW_MODE_SYM_OR_REM
Definition skge.h:2481
BASE_XMAC_1
@ BASE_XMAC_1
Definition skge.h:943
BASE_XMAC_2
@ BASE_XMAC_2
Definition skge.h:945
BASE_GMAC_1
@ BASE_GMAC_1
Definition skge.h:944
BASE_GMAC_2
@ BASE_GMAC_2
Definition skge.h:946
RX_GMF_EA
@ RX_GMF_EA
Definition skge.h:724
RX_GMF_CTRL_T
@ RX_GMF_CTRL_T
Definition skge.h:726
RX_GMF_AF_THR
@ RX_GMF_AF_THR
Definition skge.h:725
RX_GMF_FL_MSK
@ RX_GMF_FL_MSK
Definition skge.h:727
RX_GMF_FL_THR
@ RX_GMF_FL_THR
Definition skge.h:728
RX_GMF_RP
@ RX_GMF_RP
Definition skge.h:731
RX_GMF_WP
@ RX_GMF_WP
Definition skge.h:729
RX_GMF_WLEV
@ RX_GMF_WLEV
Definition skge.h:730
RX_GMF_RLEV
@ RX_GMF_RLEV
Definition skge.h:732
LINKLED_LINKSYNC_OFF
@ LINKLED_LINKSYNC_OFF
Definition skge.h:900
LINKLED_LINKSYNC_ON
@ LINKLED_LINKSYNC_ON
Definition skge.h:901
LINKLED_BLINK_ON
@ LINKLED_BLINK_ON
Definition skge.h:903
LINKLED_BLINK_OFF
@ LINKLED_BLINK_OFF
Definition skge.h:902
LINKLED_OFF
@ LINKLED_OFF
Definition skge.h:898
LINKLED_ON
@ LINKLED_ON
Definition skge.h:899
xm_read16
static u16 xm_read16(const struct skge_hw *hw, int port, int reg)
Definition skge.h:2560
PHY_ST_REM_FLT
@ PHY_ST_REM_FLT
Definition skge.h:1095
PHY_ST_AN_CAP
@ PHY_ST_AN_CAP
Definition skge.h:1096
PHY_ST_EXT_REG
@ PHY_ST_EXT_REG
Definition skge.h:1099
PHY_ST_PRE_SUP
@ PHY_ST_PRE_SUP
Definition skge.h:1093
PHY_ST_JAB_DET
@ PHY_ST_JAB_DET
Definition skge.h:1098
PHY_ST_AN_OVER
@ PHY_ST_AN_OVER
Definition skge.h:1094
PHY_ST_LSYNC
@ PHY_ST_LSYNC
Definition skge.h:1097
PHY_ST_EXT_ST
@ PHY_ST_EXT_ST
Definition skge.h:1091
PHY_B_P_NO_PAUSE
@ PHY_B_P_NO_PAUSE
Definition skge.h:1334
PHY_B_P_ASYM_MD
@ PHY_B_P_ASYM_MD
Definition skge.h:1336
PHY_B_P_BOTH_MD
@ PHY_B_P_BOTH_MD
Definition skge.h:1337
PHY_B_P_SYM_MD
@ PHY_B_P_SYM_MD
Definition skge.h:1335
csr_regs
csr_regs
Definition skge.h:76
B3_RAM_ADDR
@ B3_RAM_ADDR
Definition skge.h:139
B3_RI_WTO_XA1
@ B3_RI_WTO_XA1
Definition skge.h:143
B0_XM2_ISRC
@ B0_XM2_ISRC
Definition skge.h:91
B0_XM1_PHY_ADDR
@ B0_XM1_PHY_ADDR
Definition skge.h:88
B2_I2C_SW
@ B2_I2C_SW
Definition skge.h:132
B0_XM1_PHY_DATA
@ B0_XM1_PHY_DATA
Definition skge.h:89
B2_MAC_1
@ B2_MAC_1
Definition skge.h:101
B3_MA_RC_TEST
@ B3_MA_RC_TEST
Definition skge.h:176
B2_E_1
@ B2_E_1
Definition skge.h:109
B3_MA_TOINI_RX2
@ B3_MA_TOINI_RX2
Definition skge.h:158
B3_PA_TOINI_TX2
@ B3_PA_TOINI_TX2
Definition skge.h:180
B3_MA_TOVAL_TX2
@ B3_MA_TOVAL_TX2
Definition skge.h:164
B0_XM2_PHY_DATA
@ B0_XM2_PHY_DATA
Definition skge.h:93
B3_RI_RTO_XA2
@ B3_RI_RTO_XA2
Definition skge.h:152
B0_R2_CSR
@ B0_R2_CSR
Definition skge.h:95
B0_IMSK
@ B0_IMSK
Definition skge.h:82
B0_CTST
@ B0_CTST
Definition skge.h:78
B0_XM2_IMSK
@ B0_XM2_IMSK
Definition skge.h:90
B2_LD_CTRL
@ B2_LD_CTRL
Definition skge.h:114
B2_FDP
@ B2_FDP
Definition skge.h:113
B2_IRQM_TEST
@ B2_IRQM_TEST
Definition skge.h:123
B3_MA_TOVAL_RX2
@ B3_MA_TOVAL_RX2
Definition skge.h:162
B3_MA_RC_CTRL
@ B3_MA_RC_CTRL
Definition skge.h:175
B3_RI_WTO_XS1
@ B3_RI_WTO_XS1
Definition skge.h:144
B3_RAM_DATA_HI
@ B3_RAM_DATA_HI
Definition skge.h:141
B3_MA_RCVAL_TX1
@ B3_MA_RCVAL_TX1
Definition skge.h:173
B3_RI_WTO_R2
@ B3_RI_WTO_R2
Definition skge.h:148
B3_RI_RTO_XA1
@ B3_RI_RTO_XA1
Definition skge.h:146
B2_GP_IO
@ B2_GP_IO
Definition skge.h:128
B0_LED
@ B0_LED
Definition skge.h:79
B0_XS1_CSR
@ B0_XS1_CSR
Definition skge.h:96
B0_XM1_ISRC
@ B0_XM1_ISRC
Definition skge.h:87
B0_XS2_CSR
@ B0_XS2_CSR
Definition skge.h:98
B2_MAC_3
@ B2_MAC_3
Definition skge.h:103
B3_RI_RTO_R1
@ B3_RI_RTO_R1
Definition skge.h:145
B2_IRQM_INI
@ B2_IRQM_INI
Definition skge.h:120
B0_XA1_CSR
@ B0_XA1_CSR
Definition skge.h:97
B3_RI_RTO_XS1
@ B3_RI_RTO_XS1
Definition skge.h:147
B2_I2C_IRQ
@ B2_I2C_IRQ
Definition skge.h:131
B3_PA_TOINI_RX1
@ B3_PA_TOINI_RX1
Definition skge.h:177
B3_MA_RCVAL_TX2
@ B3_MA_RCVAL_TX2
Definition skge.h:174
B2_FAR
@ B2_FAR
Definition skge.h:112
B2_LD_TEST
@ B2_LD_TEST
Definition skge.h:115
B3_RI_CTRL
@ B3_RI_CTRL
Definition skge.h:155
B2_IRQM_VAL
@ B2_IRQM_VAL
Definition skge.h:121
B2_TST_CTRL1
@ B2_TST_CTRL1
Definition skge.h:126
B3_MA_TOINI_TX2
@ B3_MA_TOINI_TX2
Definition skge.h:160
B0_XM2_PHY_ADDR
@ B0_XM2_PHY_ADDR
Definition skge.h:92
B2_BSC_VAL
@ B2_BSC_VAL
Definition skge.h:134
B0_XM1_IMSK
@ B0_XM1_IMSK
Definition skge.h:86
B2_E_3
@ B2_E_3
Definition skge.h:111
B2_MAC_CFG
@ B2_MAC_CFG
Definition skge.h:106
B2_E_2
@ B2_E_2
Definition skge.h:110
B0_ISRC
@ B0_ISRC
Definition skge.h:81
B3_PA_TOVAL_TX2
@ B3_PA_TOVAL_TX2
Definition skge.h:184
B2_CONN_TYP
@ B2_CONN_TYP
Definition skge.h:104
B3_RI_WTO_R1
@ B3_RI_WTO_R1
Definition skge.h:142
B3_MA_TOVAL_RX1
@ B3_MA_TOVAL_RX1
Definition skge.h:161
B2_I2C_CTRL
@ B2_I2C_CTRL
Definition skge.h:129
B3_RI_TO_VAL
@ B3_RI_TO_VAL
Definition skge.h:154
B2_TI_VAL
@ B2_TI_VAL
Definition skge.h:117
B0_R1_CSR
@ B0_R1_CSR
Definition skge.h:94
B3_MA_RCINI_TX2
@ B3_MA_RCINI_TX2
Definition skge.h:170
B3_RI_RTO_XS2
@ B3_RI_RTO_XS2
Definition skge.h:153
B2_BSC_CTRL
@ B2_BSC_CTRL
Definition skge.h:135
B0_XA2_CSR
@ B0_XA2_CSR
Definition skge.h:99
B0_SP_ISRC
@ B0_SP_ISRC
Definition skge.h:85
B3_PA_TOVAL_RX1
@ B3_PA_TOVAL_RX1
Definition skge.h:181
B3_RI_TEST
@ B3_RI_TEST
Definition skge.h:156
B2_TI_TEST
@ B2_TI_TEST
Definition skge.h:119
B3_RI_RTO_R2
@ B3_RI_RTO_R2
Definition skge.h:151
B2_MAC_2
@ B2_MAC_2
Definition skge.h:102
B3_MA_TOINI_TX1
@ B3_MA_TOINI_TX1
Definition skge.h:159
B2_IRQM_MSK
@ B2_IRQM_MSK
Definition skge.h:124
B3_MA_TO_CTRL
@ B3_MA_TO_CTRL
Definition skge.h:165
B2_BSC_STAT
@ B2_BSC_STAT
Definition skge.h:136
B3_RI_WTO_XS2
@ B3_RI_WTO_XS2
Definition skge.h:150
B2_CHIP_ID
@ B2_CHIP_ID
Definition skge.h:107
B3_PA_CTRL
@ B3_PA_CTRL
Definition skge.h:185
B3_MA_RCINI_RX1
@ B3_MA_RCINI_RX1
Definition skge.h:167
B2_BSC_TST
@ B2_BSC_TST
Definition skge.h:137
B3_MA_RCVAL_RX2
@ B3_MA_RCVAL_RX2
Definition skge.h:172
B3_MA_TOVAL_TX1
@ B3_MA_TOVAL_TX1
Definition skge.h:163
B2_BSC_INI
@ B2_BSC_INI
Definition skge.h:133
B2_E_0
@ B2_E_0
Definition skge.h:108
B3_MA_TOINI_RX1
@ B3_MA_TOINI_RX1
Definition skge.h:157
B0_POWER_CTRL
@ B0_POWER_CTRL
Definition skge.h:80
B3_PA_TOVAL_RX2
@ B3_PA_TOVAL_RX2
Definition skge.h:182
B3_RI_WTO_XA2
@ B3_RI_WTO_XA2
Definition skge.h:149
B2_TST_CTRL2
@ B2_TST_CTRL2
Definition skge.h:127
B0_RAP
@ B0_RAP
Definition skge.h:77
B2_IRQM_CTRL
@ B2_IRQM_CTRL
Definition skge.h:122
B3_MA_TO_TEST
@ B3_MA_TO_TEST
Definition skge.h:166
B3_MA_RCINI_TX1
@ B3_MA_RCINI_TX1
Definition skge.h:169
B3_PA_TOINI_TX1
@ B3_PA_TOINI_TX1
Definition skge.h:179
B2_TI_INI
@ B2_TI_INI
Definition skge.h:116
B3_MA_RCINI_RX2
@ B3_MA_RCINI_RX2
Definition skge.h:168
B3_RAM_DATA_LO
@ B3_RAM_DATA_LO
Definition skge.h:140
B2_PMD_TYP
@ B2_PMD_TYP
Definition skge.h:105
B2_I2C_DATA
@ B2_I2C_DATA
Definition skge.h:130
B0_HWE_IMSK
@ B0_HWE_IMSK
Definition skge.h:84
B2_IRQM_HWE_MSK
@ B2_IRQM_HWE_MSK
Definition skge.h:125
B3_PA_TEST
@ B3_PA_TEST
Definition skge.h:186
B3_PA_TOINI_RX2
@ B3_PA_TOINI_RX2
Definition skge.h:178
B3_MA_RCVAL_RX1
@ B3_MA_RCVAL_RX1
Definition skge.h:171
B0_HWE_ISRC
@ B0_HWE_ISRC
Definition skge.h:83
B3_PA_TOVAL_TX1
@ B3_PA_TOVAL_TX1
Definition skge.h:183
B2_TI_CTRL
@ B2_TI_CTRL
Definition skge.h:118
PHY_B_IS_LST_CHANGE
@ PHY_B_IS_LST_CHANGE
Definition skge.h:1325
PHY_B_IS_PSE
@ PHY_B_IS_PSE
Definition skge.h:1312
PHY_B_IS_RRS_CHANGE
@ PHY_B_IS_RRS_CHANGE
Definition skge.h:1321
PHY_B_IS_MDXI_SC
@ PHY_B_IS_MDXI_SC
Definition skge.h:1313
PHY_B_IS_LCT
@ PHY_B_IS_LCT
Definition skge.h:1315
PHY_B_IS_LSP_CHANGE
@ PHY_B_IS_LSP_CHANGE
Definition skge.h:1324
PHY_B_IS_NO_HDC
@ PHY_B_IS_NO_HDC
Definition skge.h:1318
PHY_B_IS_NEG_USHDC
@ PHY_B_IS_NEG_USHDC
Definition skge.h:1319
PHY_B_IS_NO_HDCL
@ PHY_B_IS_NO_HDCL
Definition skge.h:1317
PHY_B_IS_LRS_CHANGE
@ PHY_B_IS_LRS_CHANGE
Definition skge.h:1322
PHY_B_IS_DUP_CHANGE
@ PHY_B_IS_DUP_CHANGE
Definition skge.h:1323
PHY_B_IS_HCT
@ PHY_B_IS_HCT
Definition skge.h:1314
PHY_B_IS_CRC_ER
@ PHY_B_IS_CRC_ER
Definition skge.h:1326
PHY_B_IS_AN_PR
@ PHY_B_IS_AN_PR
Definition skge.h:1316
PHY_B_IS_SCR_S_ER
@ PHY_B_IS_SCR_S_ER
Definition skge.h:1320
GMAC_TI_ST_TST
@ GMAC_TI_ST_TST
Definition skge.h:893
TX_GMF_WSP
@ TX_GMF_WSP
Definition skge.h:876
TX_GMF_AE_THR
@ TX_GMF_AE_THR
Definition skge.h:872
TX_GMF_RSTP
@ TX_GMF_RSTP
Definition skge.h:880
TX_GMF_RP
@ TX_GMF_RP
Definition skge.h:879
B28_DPT_CTRL
@ B28_DPT_CTRL
Definition skge.h:886
TX_GMF_WP
@ TX_GMF_WP
Definition skge.h:875
TX_GMF_WLEV
@ TX_GMF_WLEV
Definition skge.h:877
B28_DPT_INI
@ B28_DPT_INI
Definition skge.h:884
B28_DPT_TST
@ B28_DPT_TST
Definition skge.h:888
GMAC_TI_ST_CTRL
@ GMAC_TI_ST_CTRL
Definition skge.h:892
TX_GMF_CTRL_T
@ TX_GMF_CTRL_T
Definition skge.h:873
GMAC_TI_ST_VAL
@ GMAC_TI_ST_VAL
Definition skge.h:891
B28_DPT_VAL
@ B28_DPT_VAL
Definition skge.h:885
TX_GMF_RLEV
@ TX_GMF_RLEV
Definition skge.h:881
TX_GMF_EA
@ TX_GMF_EA
Definition skge.h:871
PHY_M_LEDC_STA0_MSK
@ PHY_M_LEDC_STA0_MSK
Definition skge.h:1666
PHY_M_LEDC_INIT_MSK
@ PHY_M_LEDC_INIT_MSK
Definition skge.h:1664
PHY_M_LEDC_LOS_MSK
@ PHY_M_LEDC_LOS_MSK
Definition skge.h:1663
PHY_M_LEDC_STA1_MSK
@ PHY_M_LEDC_STA1_MSK
Definition skge.h:1665
PHY_B_1000C_TEST
@ PHY_B_1000C_TEST
Definition skge.h:1191
PHY_B_1000C_RD
@ PHY_B_1000C_RD
Definition skge.h:1194
PHY_B_1000C_AFD
@ PHY_B_1000C_AFD
Definition skge.h:1195
PHY_B_1000C_AHD
@ PHY_B_1000C_AHD
Definition skge.h:1196
PHY_B_1000C_MSE
@ PHY_B_1000C_MSE
Definition skge.h:1192
PHY_B_1000C_MSC
@ PHY_B_1000C_MSC
Definition skge.h:1193
WOL_CTL_ENA_MAGIC_PKT_UNIT
@ WOL_CTL_ENA_MAGIC_PKT_UNIT
Definition skge.h:2042
WOL_CTL_DIS_PATTERN_UNIT
@ WOL_CTL_DIS_PATTERN_UNIT
Definition skge.h:2045
GM_IS_RX_COMPL
@ GM_IS_RX_COMPL
Definition skge.h:2019
WOL_CTL_PATTERN_OCC
@ WOL_CTL_PATTERN_OCC
Definition skge.h:2032
GM_IS_RX_FF_OR
@ GM_IS_RX_FF_OR
Definition skge.h:2018
GM_IS_TX_FF_UR
@ GM_IS_TX_FF_UR
Definition skge.h:2016
WOL_CTL_DIS_PME_ON_PATTERN
@ WOL_CTL_DIS_PME_ON_PATTERN
Definition skge.h:2039
WOL_CTL_ENA_PME_ON_LINK_CHG
@ WOL_CTL_ENA_PME_ON_LINK_CHG
Definition skge.h:2034
WOL_CTL_ENA_PME_ON_MAGIC_PKT
@ WOL_CTL_ENA_PME_ON_MAGIC_PKT
Definition skge.h:2036
WOL_CTL_DIS_PME_ON_LINK_CHG
@ WOL_CTL_DIS_PME_ON_LINK_CHG
Definition skge.h:2035
WOL_CTL_LINK_CHG_OCC
@ WOL_CTL_LINK_CHG_OCC
Definition skge.h:2030
GM_IS_TX_COMPL
@ GM_IS_TX_COMPL
Definition skge.h:2017
WOL_CTL_DIS_LINK_CHG_UNIT
@ WOL_CTL_DIS_LINK_CHG_UNIT
Definition skge.h:2041
GM_IS_TX_CO_OV
@ GM_IS_TX_CO_OV
Definition skge.h:2014
GM_IS_RX_CO_OV
@ GM_IS_RX_CO_OV
Definition skge.h:2015
WOL_CTL_DIS_PME_ON_MAGIC_PKT
@ WOL_CTL_DIS_PME_ON_MAGIC_PKT
Definition skge.h:2037
WOL_CTL_MAGIC_PKT_OCC
@ WOL_CTL_MAGIC_PKT_OCC
Definition skge.h:2031
WOL_CTL_ENA_PME_ON_PATTERN
@ WOL_CTL_ENA_PME_ON_PATTERN
Definition skge.h:2038
GMLC_RST_SET
@ GMLC_RST_SET
Definition skge.h:2026
GMLC_RST_CLR
@ GMLC_RST_CLR
Definition skge.h:2025
WOL_CTL_DIS_MAGIC_PKT_UNIT
@ WOL_CTL_DIS_MAGIC_PKT_UNIT
Definition skge.h:2043
WOL_CTL_ENA_LINK_CHG_UNIT
@ WOL_CTL_ENA_LINK_CHG_UNIT
Definition skge.h:2040
WOL_CTL_ENA_PATTERN_UNIT
@ WOL_CTL_ENA_PATTERN_UNIT
Definition skge.h:2044
WOL_CTL_CLEAR_RESULT
@ WOL_CTL_CLEAR_RESULT
Definition skge.h:2033
xm_write32
static void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
Definition skge.h:2565
gma_set_addr
static void gma_set_addr(struct skge_hw *hw, int port, int reg, const u8 *addr)
Definition skge.h:2612
GMF_WSP_STEP
@ GMF_WSP_STEP
Definition skge.h:1934
GMF_CLI_TX_FU
@ GMF_CLI_TX_FU
Definition skge.h:1936
GMF_CLI_TX_PE
@ GMF_CLI_TX_PE
Definition skge.h:1938
GMF_WSP_TST_OFF
@ GMF_WSP_TST_OFF
Definition skge.h:1933
GMF_CLI_TX_FC
@ GMF_CLI_TX_FC
Definition skge.h:1937
GMF_WSP_TST_ON
@ GMF_WSP_TST_ON
Definition skge.h:1932
RX_MFF_LEV
@ RX_MFF_LEV
Definition skge.h:599
RX_MFF_EA
@ RX_MFF_EA
Definition skge.h:594
RX_LED_INI
@ RX_LED_INI
Definition skge.h:607
RX_MFF_TST2
@ RX_MFF_TST2
Definition skge.h:605
RX_MFF_STAT_TO
@ RX_MFF_STAT_TO
Definition skge.h:601
RX_MFF_TIST_TO
@ RX_MFF_TIST_TO
Definition skge.h:602
RX_MFF_RP
@ RX_MFF_RP
Definition skge.h:597
LNK_SYNC_VAL
@ LNK_SYNC_VAL
Definition skge.h:613
LNK_SYNC_INI
@ LNK_SYNC_INI
Definition skge.h:612
RX_LED_TST
@ RX_LED_TST
Definition skge.h:610
RX_LED_CTRL
@ RX_LED_CTRL
Definition skge.h:609
LNK_SYNC_CTRL
@ LNK_SYNC_CTRL
Definition skge.h:614
LNK_LED_REG
@ LNK_LED_REG
Definition skge.h:616
RX_MFF_WP
@ RX_MFF_WP
Definition skge.h:595
LNK_SYNC_TST
@ LNK_SYNC_TST
Definition skge.h:615
RX_MFF_CTRL1
@ RX_MFF_CTRL1
Definition skge.h:600
RX_MFF_CTRL2
@ RX_MFF_CTRL2
Definition skge.h:603
RX_LED_VAL
@ RX_LED_VAL
Definition skge.h:608
RX_MFF_PC
@ RX_MFF_PC
Definition skge.h:598
RX_MFF_TST1
@ RX_MFF_TST1
Definition skge.h:604
gma_read16
static u16 gma_read16(const struct skge_hw *hw, int port, int reg)
Definition skge.h:2596
PHY_B_PES_RX_ER
@ PHY_B_PES_RX_ER
Definition skge.h:1252
PHY_B_PES_RRS
@ PHY_B_PES_RRS
Definition skge.h:1244
PHY_B_PES_LOCK_ER
@ PHY_B_PES_LOCK_ER
Definition skge.h:1254
PHY_B_PES_MLT3_ER
@ PHY_B_PES_MLT3_ER
Definition skge.h:1255
PHY_B_PES_CE_ER
@ PHY_B_PES_CE_ER
Definition skge.h:1249
PHY_B_PES_BAD_ESD
@ PHY_B_PES_BAD_ESD
Definition skge.h:1251
PHY_B_PES_RF
@ PHY_B_PES_RF
Definition skge.h:1248
PHY_B_PES_INT_STAT
@ PHY_B_PES_INT_STAT
Definition skge.h:1243
PHY_B_PES_LS
@ PHY_B_PES_LS
Definition skge.h:1247
PHY_B_PES_LOCKED
@ PHY_B_PES_LOCKED
Definition skge.h:1246
PHY_B_PES_LRS
@ PHY_B_PES_LRS
Definition skge.h:1245
PHY_B_PES_TX_ER
@ PHY_B_PES_TX_ER
Definition skge.h:1253
PHY_B_PES_BAD_SSD
@ PHY_B_PES_BAD_SSD
Definition skge.h:1250
PHY_B_PES_CROSS_STAT
@ PHY_B_PES_CROSS_STAT
Definition skge.h:1242
BSC_SRC
@ BSC_SRC
Definition skge.h:404
PHY_M_PS_DTE_DETECT
@ PHY_M_PS_DTE_DETECT
Definition skge.h:1455
PHY_M_PS_RES_SPEED
@ PHY_M_PS_RES_SPEED
Definition skge.h:1456
GP_DIR_6
@ GP_DIR_6
Definition skge.h:352
GP_DIR_0
@ GP_DIR_0
Definition skge.h:358
GP_IO_1
@ GP_IO_1
Definition skge.h:368
GP_IO_6
@ GP_IO_6
Definition skge.h:363
GP_IO_8
@ GP_IO_8
Definition skge.h:361
GP_IO_9
@ GP_IO_9
Definition skge.h:360
GP_DIR_3
@ GP_DIR_3
Definition skge.h:355
GP_IO_3
@ GP_IO_3
Definition skge.h:366
GP_IO_4
@ GP_IO_4
Definition skge.h:365
GP_IO_2
@ GP_IO_2
Definition skge.h:367
GP_DIR_9
@ GP_DIR_9
Definition skge.h:349
GP_DIR_4
@ GP_DIR_4
Definition skge.h:354
GP_IO_7
@ GP_IO_7
Definition skge.h:362
GP_DIR_7
@ GP_DIR_7
Definition skge.h:351
GP_DIR_5
@ GP_DIR_5
Definition skge.h:353
GP_DIR_1
@ GP_DIR_1
Definition skge.h:357
GP_IO_5
@ GP_IO_5
Definition skge.h:364
GP_DIR_8
@ GP_DIR_8
Definition skge.h:350
GP_DIR_2
@ GP_DIR_2
Definition skge.h:356
GP_IO_0
@ GP_IO_0
Definition skge.h:369
XMT_1023B_OV
@ XMT_1023B_OV
Definition skge.h:2392
XMT_OK_LO_OV
@ XMT_OK_LO_OV
Definition skge.h:2414
XMT_MCTRL_OV
@ XMT_MCTRL_OV
Definition skge.h:2407
XMT_UC_OK_OV
@ XMT_UC_OK_OV
Definition skge.h:2411
XMT_BURST
@ XMT_BURST
Definition skge.h:2409
XMT_MC_OK_OV
@ XMT_MC_OK_OV
Definition skge.h:2412
XMT_DEF
@ XMT_DEF
Definition skge.h:2402
XMT_OK_HI_OV
@ XMT_OK_HI_OV
Definition skge.h:2415
XMT_CS_ERR_OV
@ XMT_CS_ERR_OV
Definition skge.h:2399
XMT_SNG_COL
@ XMT_SNG_COL
Definition skge.h:2406
XMT_OK_OV
@ XMT_OK_OV
Definition skge.h:2416
XMT_ABO_COL_OV
@ XMT_ABO_COL_OV
Definition skge.h:2404
XMT_255B_OV
@ XMT_255B_OV
Definition skge.h:2394
XMT_64B_OV
@ XMT_64B_OV
Definition skge.h:2396
XMT_127B_OV
@ XMT_127B_OV
Definition skge.h:2395
XMT_UTIL_OV
@ XMT_UTIL_OV
Definition skge.h:2397
XMT_MUL_COL_OV
@ XMT_MUL_COL_OV
Definition skge.h:2405
XMT_FIFO_UR_OV
@ XMT_FIFO_UR_OV
Definition skge.h:2400
XMT_LAT_COL_OV
@ XMT_LAT_COL_OV
Definition skge.h:2403
XMT_UTIL_UR
@ XMT_UTIL_UR
Definition skge.h:2398
XMT_LONG
@ XMT_LONG
Definition skge.h:2410
XMT_MAX_SZ_OV
@ XMT_MAX_SZ_OV
Definition skge.h:2391
XMT_511B_OV
@ XMT_511B_OV
Definition skge.h:2393
XMT_EX_DEF_OV
@ XMT_EX_DEF_OV
Definition skge.h:2401
XMT_BC_OK_OV
@ XMT_BC_OK_OV
Definition skge.h:2413
XMT_MPAUSE
@ XMT_MPAUSE
Definition skge.h:2408
PHY_M_IS_SYMB_ERROR
@ PHY_M_IS_SYMB_ERROR
Definition skge.h:1466
PHY_M_IS_AN_COMPL
@ PHY_M_IS_AN_COMPL
Definition skge.h:1464
PHY_M_IS_MDI_CHANGE
@ PHY_M_IS_MDI_CHANGE
Definition skge.h:1469
PHY_M_IS_AN_ERROR
@ PHY_M_IS_AN_ERROR
Definition skge.h:1460
PHY_M_IS_DTE_CHANGE
@ PHY_M_IS_DTE_CHANGE
Definition skge.h:1473
PHY_M_IS_DEF_MSK
@ PHY_M_IS_DEF_MSK
Definition skge.h:1477
PHY_M_IS_FIFO_ERROR
@ PHY_M_IS_FIFO_ERROR
Definition skge.h:1468
PHY_M_IS_LST_CHANGE
@ PHY_M_IS_LST_CHANGE
Definition skge.h:1465
PHY_M_IS_END_CHANGE
@ PHY_M_IS_END_CHANGE
Definition skge.h:1471
PHY_M_IS_DUP_CHANGE
@ PHY_M_IS_DUP_CHANGE
Definition skge.h:1462
PHY_M_IS_AN_MSK
@ PHY_M_IS_AN_MSK
Definition skge.h:1480
PHY_M_IS_JABBER
@ PHY_M_IS_JABBER
Definition skge.h:1475
PHY_M_IS_POL_CHANGE
@ PHY_M_IS_POL_CHANGE
Definition skge.h:1474
PHY_M_IS_AN_PR
@ PHY_M_IS_AN_PR
Definition skge.h:1463
PHY_M_IS_FALSE_CARR
@ PHY_M_IS_FALSE_CARR
Definition skge.h:1467
PHY_M_IS_DOWNSH_DET
@ PHY_M_IS_DOWNSH_DET
Definition skge.h:1470
PHY_M_IS_LSP_CHANGE
@ PHY_M_IS_LSP_CHANGE
Definition skge.h:1461
PHY_I1_MOD_NUM
@ PHY_I1_MOD_NUM
Definition skge.h:1104
PHY_I1_REV_MSK
@ PHY_I1_REV_MSK
Definition skge.h:1105
PHY_I1_OUI_MSK
@ PHY_I1_OUI_MSK
Definition skge.h:1103
xm_write16
static void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
Definition skge.h:2571
GM_RXCR_PASS_FC
@ GM_RXCR_PASS_FC
Definition skge.h:1826
GM_RXCR_MCF_ENA
@ GM_RXCR_MCF_ENA
Definition skge.h:1824
GM_RXCR_CRC_DIS
@ GM_RXCR_CRC_DIS
Definition skge.h:1825
GM_RXCR_UCF_ENA
@ GM_RXCR_UCF_ENA
Definition skge.h:1823
TXA_LIM_T_OFF
@ TXA_LIM_T_OFF
Definition skge.h:742
TXA_INT_T_STEP
@ TXA_INT_T_STEP
Definition skge.h:740
TXA_INT_T_ON
@ TXA_INT_T_ON
Definition skge.h:738
TXA_INT_T_OFF
@ TXA_INT_T_OFF
Definition skge.h:739
TXA_LIM_T_ON
@ TXA_LIM_T_ON
Definition skge.h:741
TXA_LIM_T_STEP
@ TXA_LIM_T_STEP
Definition skge.h:743
F_WATER_MARK
@ F_WATER_MARK
Definition skge.h:805
F_FIFO_LEVEL
@ F_FIFO_LEVEL
Definition skge.h:804
F_EMPTY
@ F_EMPTY
Definition skge.h:800
F_ALM_FULL
@ F_ALM_FULL
Definition skge.h:799
F_FIFO_EOF
@ F_FIFO_EOF
Definition skge.h:801
F_WM_REACHED
@ F_WM_REACHED
Definition skge.h:802
X_RFB_AN_ERR
@ X_RFB_AN_ERR
Definition skge.h:1185
X_RFB_OK
@ X_RFB_OK
Definition skge.h:1182
X_RFB_LF
@ X_RFB_LF
Definition skge.h:1183
X_RFB_OFF
@ X_RFB_OFF
Definition skge.h:1184
RI_RST_SET
@ RI_RST_SET
Definition skge.h:425
RI_CLR_RD_PERR
@ RI_CLR_RD_PERR
Definition skge.h:421
RI_CLR_WR_PERR
@ RI_CLR_WR_PERR
Definition skge.h:422
RI_RST_CLR
@ RI_RST_CLR
Definition skge.h:424
MFF_RST_CLR
@ MFF_RST_CLR
Definition skge.h:687
MFF_RST_SET
@ MFF_RST_SET
Definition skge.h:688
MFF_ENA_OP_MD
@ MFF_ENA_OP_MD
Definition skge.h:685
MFF_DIS_OP_MD
@ MFF_DIS_OP_MD
Definition skge.h:686
PHY_M_LEDC_LINK_MSK
@ PHY_M_LEDC_LINK_MSK
Definition skge.h:1531
PHY_M_LEDC_RX_CTRL
@ PHY_M_LEDC_RX_CTRL
Definition skge.h:1535
PHY_M_LEDC_DP_CTRL
@ PHY_M_LEDC_DP_CTRL
Definition skge.h:1533
PHY_M_LEDC_TX_C_MSB
@ PHY_M_LEDC_TX_C_MSB
Definition skge.h:1537
PHY_M_LEDC_TX_CTRL
@ PHY_M_LEDC_TX_CTRL
Definition skge.h:1536
PHY_M_LEDC_DP_C_MSB
@ PHY_M_LEDC_DP_C_MSB
Definition skge.h:1534
MAC_TX_CLK_0_MHZ
@ MAC_TX_CLK_0_MHZ
Definition skge.h:1511
MAC_TX_CLK_2_5_MHZ
@ MAC_TX_CLK_2_5_MHZ
Definition skge.h:1512
MAC_TX_CLK_25_MHZ
@ MAC_TX_CLK_25_MHZ
Definition skge.h:1513
GM_SMOD_JUMBO_ENA
@ GM_SMOD_JUMBO_ENA
Definition skge.h:1850
GM_SMOD_VLAN_ENA
@ GM_SMOD_VLAN_ENA
Definition skge.h:1849
GM_SMOD_LIMIT_4
@ GM_SMOD_LIMIT_4
Definition skge.h:1848
GM_SMOD_IPG_MSK
@ GM_SMOD_IPG_MSK
Definition skge.h:1851
GM_SMOD_DATABL_MSK
@ GM_SMOD_DATABL_MSK
Definition skge.h:1847
CHIP_ID_YUKON_EC
@ CHIP_ID_YUKON_EC
Definition skge.h:323
CHIP_ID_YUKON_LITE
@ CHIP_ID_YUKON_LITE
Definition skge.h:320
CHIP_ID_GENESIS
@ CHIP_ID_GENESIS
Definition skge.h:318
CHIP_REV_YU_LITE_A1
@ CHIP_REV_YU_LITE_A1
Definition skge.h:326
CHIP_REV_YU_LITE_A3
@ CHIP_REV_YU_LITE_A3
Definition skge.h:327
CHIP_ID_YUKON_XL
@ CHIP_ID_YUKON_XL
Definition skge.h:322
CHIP_ID_YUKON_FE
@ CHIP_ID_YUKON_FE
Definition skge.h:324
CHIP_ID_YUKON
@ CHIP_ID_YUKON
Definition skge.h:319
CHIP_ID_YUKON_LP
@ CHIP_ID_YUKON_LP
Definition skge.h:321
BLINK_340MS
@ BLINK_340MS
Definition skge.h:1556
BLINK_670MS
@ BLINK_670MS
Definition skge.h:1557
BLINK_42MS
@ BLINK_42MS
Definition skge.h:1553
BLINK_170MS
@ BLINK_170MS
Definition skge.h:1555
BLINK_84MS
@ BLINK_84MS
Definition skge.h:1554
PHY_B_AC_DIAG
@ PHY_B_AC_DIAG
Definition skge.h:1287
PHY_B_AC_ER_CTRL
@ PHY_B_AC_ER_CTRL
Definition skge.h:1279
PHY_B_FC_CTR
@ PHY_B_FC_CTR
Definition skge.h:1270
PHY_B_AC_LONG_PACK
@ PHY_B_AC_LONG_PACK
Definition skge.h:1278
PHY_B_AC_TX_TST
@ PHY_B_AC_TX_TST
Definition skge.h:1281
PHY_B_AC_L_SQE
@ PHY_B_AC_L_SQE
Definition skge.h:1277
PHY_B_RC_LOC_MSK
@ PHY_B_RC_LOC_MSK
Definition skge.h:1273
PHY_B_RC_REM_MSK
@ PHY_B_RC_REM_MSK
Definition skge.h:1274
PHY_B_AC_DIS_PM
@ PHY_B_AC_DIS_PM
Definition skge.h:1285
PHY_B_AC_DIS_PRF
@ PHY_B_AC_DIS_PRF
Definition skge.h:1283
WOL_REG_OFFS
@ WOL_REG_OFFS
Definition skge.h:916
GMAC_IRQ_MSK
@ GMAC_IRQ_MSK
Definition skge.h:911
WOL_PATT_LEN_LO
@ WOL_PATT_LEN_LO
Definition skge.h:926
WOL_PATT_CNT_4
@ WOL_PATT_CNT_4
Definition skge.h:932
WOL_MATCH_RES
@ WOL_MATCH_RES
Definition skge.h:920
GPHY_CTRL
@ GPHY_CTRL
Definition skge.h:909
GMAC_IRQ_SRC
@ GMAC_IRQ_SRC
Definition skge.h:910
WOL_CTRL_STAT
@ WOL_CTRL_STAT
Definition skge.h:918
WOL_PATT_RPTR
@ WOL_PATT_RPTR
Definition skge.h:922
WOL_MATCH_CTL
@ WOL_MATCH_CTL
Definition skge.h:919
GMAC_CTRL
@ GMAC_CTRL
Definition skge.h:908
WOL_PATT_CNT_0
@ WOL_PATT_CNT_0
Definition skge.h:931
WOL_MAC_ADDR
@ WOL_MAC_ADDR
Definition skge.h:921
WOL_PATT_LEN_HI
@ WOL_PATT_LEN_HI
Definition skge.h:927
GMAC_LINK_CTRL
@ GMAC_LINK_CTRL
Definition skge.h:912
BSC_T_OFF
@ BSC_T_OFF
Definition skge.h:410
BSC_T_STEP
@ BSC_T_STEP
Definition skge.h:411
BSC_T_ON
@ BSC_T_ON
Definition skge.h:409
WOL_PATT_RAM_1
@ WOL_PATT_RAM_1
Definition skge.h:937
WOL_PATT_RAM_2
@ WOL_PATT_RAM_2
Definition skge.h:938
TXA_PRIO_XS
@ TXA_PRIO_XS
Definition skge.h:748
GM_GPCR_BURST_ENA
@ GM_GPCR_BURST_ENA
Definition skge.h:1794
GM_GPCR_LOOP_ENA
@ GM_GPCR_LOOP_ENA
Definition skge.h:1795
GM_GPCR_AU_SPD_DIS
@ GM_GPCR_AU_SPD_DIS
Definition skge.h:1804
GM_GPCR_TX_ENA
@ GM_GPCR_TX_ENA
Definition skge.h:1792
GM_GPCR_RX_ENA
@ GM_GPCR_RX_ENA
Definition skge.h:1793
GM_GPCR_DUP_FULL
@ GM_GPCR_DUP_FULL
Definition skge.h:1799
GM_GPCR_FL_PASS
@ GM_GPCR_FL_PASS
Definition skge.h:1798
GM_GPCR_SPEED_100
@ GM_GPCR_SPEED_100
Definition skge.h:1801
GM_GPCR_AU_FCT_DIS
@ GM_GPCR_AU_FCT_DIS
Definition skge.h:1803
GM_GPCR_AU_DUP_DIS
@ GM_GPCR_AU_DUP_DIS
Definition skge.h:1802
GM_GPCR_PART_ENA
@ GM_GPCR_PART_ENA
Definition skge.h:1796
GM_GPCR_FC_RX_DIS
@ GM_GPCR_FC_RX_DIS
Definition skge.h:1800
GM_GPCR_GIGS_ENA
@ GM_GPCR_GIGS_ENA
Definition skge.h:1797
GM_GPCR_FC_TX_DIS
@ GM_GPCR_FC_TX_DIS
Definition skge.h:1791
GM_GPCR_PROM_ENA
@ GM_GPCR_PROM_ENA
Definition skge.h:1790
CS_MRST_CLR
@ CS_MRST_CLR
Definition skge.h:201
LED_STAT_ON
@ LED_STAT_ON
Definition skge.h:208
PC_VCC_OFF
@ PC_VCC_OFF
Definition skge.h:219
PC_VCC_ENA
@ PC_VCC_ENA
Definition skge.h:214
PC_VAUX_DIS
@ PC_VAUX_DIS
Definition skge.h:213
PC_VCC_DIS
@ PC_VCC_DIS
Definition skge.h:215
CS_RST_SET
@ CS_RST_SET
Definition skge.h:204
CS_RST_CLR
@ CS_RST_CLR
Definition skge.h:203
PC_VAUX_ON
@ PC_VAUX_ON
Definition skge.h:216
CS_BUS_SLOT_SZ
@ CS_BUS_SLOT_SZ
Definition skge.h:196
CS_VAUX_AVAIL
@ CS_VAUX_AVAIL
Definition skge.h:194
PC_VAUX_OFF
@ PC_VAUX_OFF
Definition skge.h:217
CS_ST_SW_IRQ
@ CS_ST_SW_IRQ
Definition skge.h:197
LED_STAT_OFF
@ LED_STAT_OFF
Definition skge.h:209
PC_VAUX_ENA
@ PC_VAUX_ENA
Definition skge.h:212
PC_VCC_ON
@ PC_VCC_ON
Definition skge.h:218
CS_CLK_RUN_RST
@ CS_CLK_RUN_RST
Definition skge.h:192
CS_BUS_CLOCK
@ CS_BUS_CLOCK
Definition skge.h:195
CS_CL_SW_IRQ
@ CS_CL_SW_IRQ
Definition skge.h:198
CS_MRST_SET
@ CS_MRST_SET
Definition skge.h:202
CS_STOP_MAST
@ CS_STOP_MAST
Definition skge.h:200
CS_CLK_RUN_ENA
@ CS_CLK_RUN_ENA
Definition skge.h:193
CS_CLK_RUN_HOT
@ CS_CLK_RUN_HOT
Definition skge.h:191
CS_STOP_DONE
@ CS_STOP_DONE
Definition skge.h:199
MFF_ENA_PAUSE
@ MFF_ENA_PAUSE
Definition skge.h:628
MFF_DIS_PAUSE
@ MFF_DIS_PAUSE
Definition skge.h:629
MFF_DIS_FLUSH
@ MFF_DIS_FLUSH
Definition skge.h:631
MFF_CLR_INTIST
@ MFF_CLR_INTIST
Definition skge.h:634
MFF_DIS_TIST
@ MFF_DIS_TIST
Definition skge.h:633
MFF_ENA_TIM_PAT
@ MFF_ENA_TIM_PAT
Definition skge.h:624
MFF_ENA_ALM_FUL
@ MFF_ENA_ALM_FUL
Definition skge.h:626
MFF_CLR_INSTAT
@ MFF_CLR_INSTAT
Definition skge.h:635
MFF_ENA_FLUSH
@ MFF_ENA_FLUSH
Definition skge.h:630
MFF_RX_CTRL_DEF
@ MFF_RX_CTRL_DEF
Definition skge.h:636
MFF_ENA_RDY_PAT
@ MFF_ENA_RDY_PAT
Definition skge.h:622
MFF_DIS_TIM_PAT
@ MFF_DIS_TIM_PAT
Definition skge.h:625
MFF_DIS_ALM_FUL
@ MFF_DIS_ALM_FUL
Definition skge.h:627
MFF_ENA_TIST
@ MFF_ENA_TIST
Definition skge.h:632
MFF_DIS_RDY_PAT
@ MFF_DIS_RDY_PAT
Definition skge.h:623
PHY_MARV_ID0_VAL
@ PHY_MARV_ID0_VAL
Definition skge.h:1118
PHY_MARV_ID1_Y2
@ PHY_MARV_ID1_Y2
Definition skge.h:1122
PHY_MARV_ID1_C2
@ PHY_MARV_ID1_C2
Definition skge.h:1121
PHY_MARV_ID1_B0
@ PHY_MARV_ID1_B0
Definition skge.h:1119
PHY_MARV_ID1_B2
@ PHY_MARV_ID1_B2
Definition skge.h:1120
TIM_CLR_IRQ
@ TIM_CLR_IRQ
Definition skge.h:335
TIM_START
@ TIM_START
Definition skge.h:333
TIM_STOP
@ TIM_STOP
Definition skge.h:334
PHY_CT_SP1000
@ PHY_CT_SP1000
Definition skge.h:1085
PHY_CT_SP100
@ PHY_CT_SP100
Definition skge.h:1086
PHY_CT_SP10
@ PHY_CT_SP10
Definition skge.h:1087
TX_JAM_LEN_DEF
@ TX_JAM_LEN_DEF
Definition skge.h:1835
TX_JAM_IPG_DEF
@ TX_JAM_IPG_DEF
Definition skge.h:1836
GM_TXPA_JAMLEN_MSK
@ GM_TXPA_JAMLEN_MSK
Definition skge.h:1831
GM_TXPA_JAMIPG_MSK
@ GM_TXPA_JAMIPG_MSK
Definition skge.h:1832
TX_IPG_JAM_DEF
@ TX_IPG_JAM_DEF
Definition skge.h:1837
GM_TXPA_JAMDAT_MSK
@ GM_TXPA_JAMDAT_MSK
Definition skge.h:1833
PHY_M_PS_SPEED_1000
@ PHY_M_PS_SPEED_1000
Definition skge.h:1434
PHY_M_PS_SPEED_MSK
@ PHY_M_PS_SPEED_MSK
Definition skge.h:1433
PHY_M_PS_FULL_DUP
@ PHY_M_PS_FULL_DUP
Definition skge.h:1437
PHY_M_PS_LINK_UP
@ PHY_M_PS_LINK_UP
Definition skge.h:1440
PHY_M_PS_PAGE_REC
@ PHY_M_PS_PAGE_REC
Definition skge.h:1438
PHY_M_PS_DOWNS_STAT
@ PHY_M_PS_DOWNS_STAT
Definition skge.h:1443
PHY_M_PS_POL_REV
@ PHY_M_PS_POL_REV
Definition skge.h:1447
PHY_M_PS_TX_P_EN
@ PHY_M_PS_TX_P_EN
Definition skge.h:1445
PHY_M_PS_SPEED_100
@ PHY_M_PS_SPEED_100
Definition skge.h:1435
PHY_M_PS_JABBER
@ PHY_M_PS_JABBER
Definition skge.h:1448
PHY_M_PS_SPEED_10
@ PHY_M_PS_SPEED_10
Definition skge.h:1436
PHY_M_PS_RX_P_EN
@ PHY_M_PS_RX_P_EN
Definition skge.h:1446
PHY_M_PS_CABLE_MSK
@ PHY_M_PS_CABLE_MSK
Definition skge.h:1441
PHY_M_PS_MDI_X_STAT
@ PHY_M_PS_MDI_X_STAT
Definition skge.h:1442
PHY_M_PS_ENDET_STAT
@ PHY_M_PS_ENDET_STAT
Definition skge.h:1444
PHY_M_PS_SPDUP_RES
@ PHY_M_PS_SPDUP_RES
Definition skge.h:1439
PHY_M_P_ASYM_MD_X
@ PHY_M_P_ASYM_MD_X
Definition skge.h:1375
PHY_M_P_NO_PAUSE_X
@ PHY_M_P_NO_PAUSE_X
Definition skge.h:1373
PHY_M_P_SYM_MD_X
@ PHY_M_P_SYM_MD_X
Definition skge.h:1374
PHY_M_P_BOTH_MD_X
@ PHY_M_P_BOTH_MD_X
Definition skge.h:1376
skge_write16
static void skge_write16(const struct skge_hw *hw, int reg, u16 val)
Definition skge.h:2537
PHY_X_P_BOTH_MD
@ PHY_X_P_BOTH_MD
Definition skge.h:1161
PHY_X_P_NO_PAUSE
@ PHY_X_P_NO_PAUSE
Definition skge.h:1158
PHY_X_P_SYM_MD
@ PHY_X_P_SYM_MD
Definition skge.h:1159
PHY_X_P_ASYM_MD
@ PHY_X_P_ASYM_MD
Definition skge.h:1160
XMR_FS_MC
@ XMR_FS_MC
Definition skge.h:958
XMR_FS_CAR_ERR
@ XMR_FS_CAR_ERR
Definition skge.h:965
XMR_FS_2L_VLAN
@ XMR_FS_2L_VLAN
Definition skge.h:955
XMR_FS_LNG_ERR
@ XMR_FS_LNG_ERR
Definition skge.h:969
XMR_FS_802_3
@ XMR_FS_802_3
Definition skge.h:963
XMR_FS_BURST
@ XMR_FS_BURST
Definition skge.h:961
XMR_FS_MCTRL
@ XMR_FS_MCTRL
Definition skge.h:972
XMR_FS_BC
@ XMR_FS_BC
Definition skge.h:957
XMR_FS_FCS_ERR
@ XMR_FS_FCS_ERR
Definition skge.h:970
XMR_FS_LEN
@ XMR_FS_LEN
Definition skge.h:953
XMR_FS_CEX_ERR
@ XMR_FS_CEX_ERR
Definition skge.h:962
XMR_FS_LEN_SHIFT
@ XMR_FS_LEN_SHIFT
Definition skge.h:954
XMR_FS_ERR
@ XMR_FS_ERR
Definition skge.h:971
XMR_FS_LEN_ERR
@ XMR_FS_LEN_ERR
Definition skge.h:966
XMR_FS_FRA_ERR
@ XMR_FS_FRA_ERR
Definition skge.h:967
XMR_FS_UC
@ XMR_FS_UC
Definition skge.h:959
XMR_FS_RUNT
@ XMR_FS_RUNT
Definition skge.h:968
XMR_FS_COL_ERR
@ XMR_FS_COL_ERR
Definition skge.h:964
XMR_FS_1_VLAN
@ XMR_FS_1_VLAN
Definition skge.h:956
skge_read32
static u32 skge_read32(const struct skge_hw *hw, int reg)
Definition skge.h:2517
Q_XS2
@ Q_XS2
Definition skge.h:561
Q_XA2
@ Q_XA2
Definition skge.h:562
Q_XS1
@ Q_XS1
Definition skge.h:559
Q_XA1
@ Q_XA1
Definition skge.h:560
Q_R1
@ Q_R1
Definition skge.h:557
Q_R2
@ Q_R2
Definition skge.h:558
GM_TXCR_PAD_DIS
@ GM_TXCR_PAD_DIS
Definition skge.h:1814
GM_TXCR_COL_THR_MSK
@ GM_TXCR_COL_THR_MSK
Definition skge.h:1815
GM_TXCR_CRC_DIS
@ GM_TXCR_CRC_DIS
Definition skge.h:1813
GM_TXCR_FORCE_JAM
@ GM_TXCR_FORCE_JAM
Definition skge.h:1812
PHY_B_ES_X_HD_CAP
@ PHY_B_ES_X_HD_CAP
Definition skge.h:1215
PHY_B_ES_X_FD_CAP
@ PHY_B_ES_X_FD_CAP
Definition skge.h:1214
PHY_B_ES_T_HD_CAP
@ PHY_B_ES_T_HD_CAP
Definition skge.h:1217
PHY_B_ES_T_FD_CAP
@ PHY_B_ES_T_FD_CAP
Definition skge.h:1216
TST_CFG_WRITE_ON
@ TST_CFG_WRITE_ON
Definition skge.h:304
TST_FRC_DPERR_MW
@ TST_FRC_DPERR_MW
Definition skge.h:299
TST_CFG_WRITE_OFF
@ TST_CFG_WRITE_OFF
Definition skge.h:305
TST_FRC_APERR_M
@ TST_FRC_APERR_M
Definition skge.h:302
TST_FRC_APERR_T
@ TST_FRC_APERR_T
Definition skge.h:303
TST_FRC_DPERR_MR
@ TST_FRC_DPERR_MR
Definition skge.h:298
TST_FRC_DPERR_TW
@ TST_FRC_DPERR_TW
Definition skge.h:301
TST_FRC_DPERR_TR
@ TST_FRC_DPERR_TR
Definition skge.h:300
GPC_HWCFG_M_2
@ GPC_HWCFG_M_2
Definition skge.h:1968
GPC_ENA_XC
@ GPC_ENA_XC
Definition skge.h:1972
GPC_DIS_125
@ GPC_DIS_125
Definition skge.h:1973
GPC_75_OHM
@ GPC_75_OHM
Definition skge.h:1964
GPC_INT_POL_HI
@ GPC_INT_POL_HI
Definition skge.h:1963
GPC_ANEG_2
@ GPC_ANEG_2
Definition skge.h:1975
GPC_DIS_SLEEP
@ GPC_DIS_SLEEP
Definition skge.h:1966
GPC_RST_SET
@ GPC_RST_SET
Definition skge.h:1985
GPC_ENA_PAUSE
@ GPC_ENA_PAUSE
Definition skge.h:1977
GPC_SEL_BDT
@ GPC_SEL_BDT
Definition skge.h:1962
GPC_HWCFG_M_0
@ GPC_HWCFG_M_0
Definition skge.h:1970
GPC_PHYADDR_1
@ GPC_PHYADDR_1
Definition skge.h:1981
GPC_HWCFG_M_1
@ GPC_HWCFG_M_1
Definition skge.h:1969
GPC_HWCFG_M_3
@ GPC_HWCFG_M_3
Definition skge.h:1967
GPC_DIS_FC
@ GPC_DIS_FC
Definition skge.h:1965
GPC_PHYADDR_0
@ GPC_PHYADDR_0
Definition skge.h:1982
GPC_ANEG_3
@ GPC_ANEG_3
Definition skge.h:1974
GPC_PHYADDR_2
@ GPC_PHYADDR_2
Definition skge.h:1980
GPC_ANEG_0
@ GPC_ANEG_0
Definition skge.h:1971
GPC_PHYADDR_4
@ GPC_PHYADDR_4
Definition skge.h:1978
GPC_PHYADDR_3
@ GPC_PHYADDR_3
Definition skge.h:1979
GPC_RST_CLR
@ GPC_RST_CLR
Definition skge.h:1984
GPC_ANEG_1
@ GPC_ANEG_1
Definition skge.h:1976
xm_outhash
static void xm_outhash(const struct skge_hw *hw, int port, int reg, const u8 *hash)
Definition skge.h:2576
SK_XMAC_REG
#define SK_XMAC_REG(port, reg)
Definition skge.h:2549
PHY_M_AN_10_HD
@ PHY_M_AN_10_HD
Definition skge.h:1359
PHY_M_AN_10_FD
@ PHY_M_AN_10_FD
Definition skge.h:1358
PHY_M_AN_ACK
@ PHY_M_AN_ACK
Definition skge.h:1350
PHY_M_AN_ASP
@ PHY_M_AN_ASP
Definition skge.h:1353
PHY_M_AN_PC
@ PHY_M_AN_PC
Definition skge.h:1354
PHY_M_AN_RF
@ PHY_M_AN_RF
Definition skge.h:1351
PHY_M_AN_SEL_MSK
@ PHY_M_AN_SEL_MSK
Definition skge.h:1360
PHY_M_AN_100_T4
@ PHY_M_AN_100_T4
Definition skge.h:1355
PHY_M_AN_100_HD
@ PHY_M_AN_100_HD
Definition skge.h:1357
PHY_M_AN_100_FD
@ PHY_M_AN_100_FD
Definition skge.h:1356
PHY_M_AN_NXT_PG
@ PHY_M_AN_NXT_PG
Definition skge.h:1349
skge_write8
static void skge_write8(const struct skge_hw *hw, int reg, u8 val)
Definition skge.h:2542
MO_LED_NORM
@ MO_LED_NORM
Definition skge.h:1571
MO_LED_BLINK
@ MO_LED_BLINK
Definition skge.h:1572
MO_LED_ON
@ MO_LED_ON
Definition skge.h:1574
MO_LED_OFF
@ MO_LED_OFF
Definition skge.h:1573
skge_read8
static u8 skge_read8(const struct skge_hw *hw, int reg)
Definition skge.h:2527
PHY_M_PC_ENA_DTE_DT
@ PHY_M_PC_ENA_DTE_DT
Definition skge.h:1418
PHY_M_PC_SH_TP_SEL
@ PHY_M_PC_SH_TP_SEL
Definition skge.h:1427
PHY_M_PC_DIS_NLP_CK
@ PHY_M_PC_DIS_NLP_CK
Definition skge.h:1420
PHY_M_PC_DIS_SCRAMB
@ PHY_M_PC_DIS_SCRAMB
Definition skge.h:1424
PHY_M_PC_ENA_LIP_NP
@ PHY_M_PC_ENA_LIP_NP
Definition skge.h:1421
PHY_M_PC_DIS_FEFI
@ PHY_M_PC_DIS_FEFI
Definition skge.h:1425
PHY_M_PC_DIS_NLP_GN
@ PHY_M_PC_DIS_NLP_GN
Definition skge.h:1422
PHY_M_PC_ENA_ENE_DT
@ PHY_M_PC_ENA_ENE_DT
Definition skge.h:1419
PHY_M_PC_RX_FD_MSK
@ PHY_M_PC_RX_FD_MSK
Definition skge.h:1428
PHY_M_FESC_DIS_WAIT
@ PHY_M_FESC_DIS_WAIT
Definition skge.h:1655
PHY_M_FESC_ENA_MCLK
@ PHY_M_FESC_ENA_MCLK
Definition skge.h:1656
PHY_M_FESC_SEL_CL_A
@ PHY_M_FESC_SEL_CL_A
Definition skge.h:1657
PHY_B_RES_1000FD
@ PHY_B_RES_1000FD
Definition skge.h:1343
PHY_B_RES_1000HD
@ PHY_B_RES_1000HD
Definition skge.h:1344
TIM_T_OFF
@ TIM_T_OFF
Definition skge.h:343
TIM_T_ON
@ TIM_T_ON
Definition skge.h:342
TIM_T_STEP
@ TIM_T_STEP
Definition skge.h:344
IS_PA_TO_TX1
@ IS_PA_TO_TX1
Definition skge.h:229
IS_IRQ_SW
@ IS_IRQ_SW
Definition skge.h:232
IS_R1_F
@ IS_R1_F
Definition skge.h:242
IS_XA2_F
@ IS_XA2_F
Definition skge.h:262
IS_PA_TO_RX1
@ IS_PA_TO_RX1
Definition skge.h:227
IS_MAC1
@ IS_MAC1
Definition skge.h:236
IS_XA1_B
@ IS_XA1_B
Definition skge.h:253
IS_XA2_B
@ IS_XA2_B
Definition skge.h:261
IS_LNK_SYNC_M2
@ IS_LNK_SYNC_M2
Definition skge.h:239
IS_I2C_READY
@ IS_I2C_READY
Definition skge.h:231
IS_TIMINT
@ IS_TIMINT
Definition skge.h:235
IS_HW_ERR
@ IS_HW_ERR
Definition skge.h:225
IS_PA_TO_TX2
@ IS_PA_TO_TX2
Definition skge.h:230
IS_XA1_F
@ IS_XA1_F
Definition skge.h:254
IS_XS2_B
@ IS_XS2_B
Definition skge.h:257
IS_XS2_C
@ IS_XS2_C
Definition skge.h:259
IS_TO_PORT2
@ IS_TO_PORT2
Definition skge.h:266
IS_MAC2
@ IS_MAC2
Definition skge.h:238
IS_XS1_B
@ IS_XS1_B
Definition skge.h:249
IS_XA1_C
@ IS_XA1_C
Definition skge.h:255
IS_EXT_REG
@ IS_EXT_REG
Definition skge.h:233
IS_ALL_MSK
@ IS_ALL_MSK
Definition skge.h:224
IS_PORT_1
@ IS_PORT_1
Definition skge.h:268
IS_R1_C
@ IS_R1_C
Definition skge.h:243
IS_TO_PORT1
@ IS_TO_PORT1
Definition skge.h:265
IS_XA2_C
@ IS_XA2_C
Definition skge.h:263
IS_XS1_C
@ IS_XS1_C
Definition skge.h:251
IS_R2_F
@ IS_R2_F
Definition skge.h:246
IS_XS2_F
@ IS_XS2_F
Definition skge.h:258
IS_R2_C
@ IS_R2_C
Definition skge.h:247
IS_XS1_F
@ IS_XS1_F
Definition skge.h:250
IS_R1_B
@ IS_R1_B
Definition skge.h:241
IS_R2_B
@ IS_R2_B
Definition skge.h:245
IS_PORT_2
@ IS_PORT_2
Definition skge.h:269
IS_LNK_SYNC_M1
@ IS_LNK_SYNC_M1
Definition skge.h:237
IS_PA_TO_RX2
@ IS_PA_TO_RX2
Definition skge.h:228
GM_PAR_MIB_TST
@ GM_PAR_MIB_TST
Definition skge.h:1875
GM_PAR_MIB_CLR
@ GM_PAR_MIB_CLR
Definition skge.h:1874
PHY_XMAC_CTRL
@ PHY_XMAC_CTRL
Definition skge.h:988
PHY_XMAC_EXT_STAT
@ PHY_XMAC_EXT_STAT
Definition skge.h:998
PHY_XMAC_AUNE_EXP
@ PHY_XMAC_AUNE_EXP
Definition skge.h:994
PHY_XMAC_NEPG_LP
@ PHY_XMAC_NEPG_LP
Definition skge.h:996
PHY_XMAC_AUNE_LP
@ PHY_XMAC_AUNE_LP
Definition skge.h:993
PHY_XMAC_ID1
@ PHY_XMAC_ID1
Definition skge.h:991
PHY_XMAC_NEPG
@ PHY_XMAC_NEPG
Definition skge.h:995
PHY_XMAC_AUNE_ADV
@ PHY_XMAC_AUNE_ADV
Definition skge.h:992
PHY_XMAC_STAT
@ PHY_XMAC_STAT
Definition skge.h:989
PHY_XMAC_ID0
@ PHY_XMAC_ID0
Definition skge.h:990
PHY_XMAC_RES_ABI
@ PHY_XMAC_RES_ABI
Definition skge.h:999
XM_IS_TX_COMP
@ XM_IS_TX_COMP
Definition skge.h:2248
XM_IS_AND
@ XM_IS_AND
Definition skge.h:2242
XM_IS_FRC_INT
@ XM_IS_FRC_INT
Definition skge.h:2237
XM_IS_TX_ABORT
@ XM_IS_TX_ABORT
Definition skge.h:2236
XM_IS_TXF_UR
@ XM_IS_TXF_UR
Definition skge.h:2247
XM_IS_RX_COMP
@ XM_IS_RX_COMP
Definition skge.h:2249
XM_IS_LNK_AE
@ XM_IS_LNK_AE
Definition skge.h:2235
XM_IS_TSC_OV
@ XM_IS_TSC_OV
Definition skge.h:2243
XM_IS_LIPA_RC
@ XM_IS_LIPA_RC
Definition skge.h:2239
XM_IS_RXC_OV
@ XM_IS_RXC_OV
Definition skge.h:2244
XM_IS_TX_PAGE
@ XM_IS_TX_PAGE
Definition skge.h:2241
XM_IS_INP_ASS
@ XM_IS_INP_ASS
Definition skge.h:2238
XM_IS_RXF_OV
@ XM_IS_RXF_OV
Definition skge.h:2246
XM_IS_TXC_OV
@ XM_IS_TXC_OV
Definition skge.h:2245
XM_IS_RX_PAGE
@ XM_IS_RX_PAGE
Definition skge.h:2240
XM_IMSK_DISABLE
@ XM_IMSK_DISABLE
Definition skge.h:2251
PHY_M_PC_ENA_AUTO
@ PHY_M_PC_ENA_AUTO
Definition skge.h:1413
PHY_M_PC_MAN_MDI
@ PHY_M_PC_MAN_MDI
Definition skge.h:1411
PHY_M_PC_MAN_MDIX
@ PHY_M_PC_MAN_MDIX
Definition skge.h:1412
Q_D
@ Q_D
Definition skge.h:517
Q_DA_H
@ Q_DA_H
Definition skge.h:519
Q_CSR
@ Q_CSR
Definition skge.h:523
Q_T1
@ Q_T1
Definition skge.h:525
Q_T1_RD
@ Q_T1_RD
Definition skge.h:528
Q_AC_L
@ Q_AC_L
Definition skge.h:520
Q_T1_WR
@ Q_T1_WR
Definition skge.h:527
Q_DA_L
@ Q_DA_L
Definition skge.h:518
Q_T3
@ Q_T3
Definition skge.h:531
Q_F
@ Q_F
Definition skge.h:524
Q_BC
@ Q_BC
Definition skge.h:522
Q_T2
@ Q_T2
Definition skge.h:530
Q_T1_SV
@ Q_T1_SV
Definition skge.h:529
Q_AC_H
@ Q_AC_H
Definition skge.h:521
B8_Q_REGS
@ B8_Q_REGS
Definition skge.h:516
Q_T1_TR
@ Q_T1_TR
Definition skge.h:526
SK_GMAC_REG
#define SK_GMAC_REG(port, reg)
Definition skge.h:2593
TXA_LIM_VAL
@ TXA_LIM_VAL
Definition skge.h:495
TXA_ITI_INI
@ TXA_ITI_INI
Definition skge.h:492
TXA_CTRL
@ TXA_CTRL
Definition skge.h:496
TXA_TEST
@ TXA_TEST
Definition skge.h:497
TXA_STAT
@ TXA_STAT
Definition skge.h:498
TXA_ITI_VAL
@ TXA_ITI_VAL
Definition skge.h:493
TXA_LIM_INI
@ TXA_LIM_INI
Definition skge.h:494
GMR_FS_RX_OK
@ GMR_FS_RX_OK
Definition skge.h:1887
GMR_FS_MC
@ GMR_FS_MC
Definition skge.h:1885
GMR_FS_RX_FF_OV
@ GMR_FS_RX_FF_OV
Definition skge.h:1895
GMR_FS_LEN
@ GMR_FS_LEN
Definition skge.h:1880
GMR_FS_FRAGMENT
@ GMR_FS_FRAGMENT
Definition skge.h:1892
GMR_FS_LEN_SHIFT
@ GMR_FS_LEN_SHIFT
Definition skge.h:1881
GMR_FS_UN_SIZE
@ GMR_FS_UN_SIZE
Definition skge.h:1884
GMR_FS_VLAN
@ GMR_FS_VLAN
Definition skge.h:1882
GMR_FS_BAD_FC
@ GMR_FS_BAD_FC
Definition skge.h:1889
RX_FF_FL_DEF_MSK
@ RX_FF_FL_DEF_MSK
Definition skge.h:1904
GMR_FS_GOOD_FC
@ GMR_FS_GOOD_FC
Definition skge.h:1888
GMR_FS_LONG_ERR
@ GMR_FS_LONG_ERR
Definition skge.h:1891
GMR_FS_BC
@ GMR_FS_BC
Definition skge.h:1886
GMR_FS_ANY_ERR
@ GMR_FS_ANY_ERR
Definition skge.h:1900
GMR_FS_CRC_ERR
@ GMR_FS_CRC_ERR
Definition skge.h:1894
GMR_FS_MII_ERR
@ GMR_FS_MII_ERR
Definition skge.h:1890
GMR_FS_JABBER
@ GMR_FS_JABBER
Definition skge.h:1883
SK_MAC_XMAC
@ SK_MAC_XMAC
Definition skge.h:567
SK_MAC_GMAC
@ SK_MAC_GMAC
Definition skge.h:568
CSR_HPI_RUN
@ CSR_HPI_RUN
Definition skge.h:770
CSR_FIFO_CLR
@ CSR_FIFO_CLR
Definition skge.h:768
CSR_IRQ_CL_F
@ CSR_IRQ_CL_F
Definition skge.h:786
CSR_SV_IDLE
@ CSR_SV_IDLE
Definition skge.h:764
CSR_DIS_POL
@ CSR_DIS_POL
Definition skge.h:781
CSR_TRANS_RUN
@ CSR_TRANS_RUN
Definition skge.h:778
CSR_START
@ CSR_START
Definition skge.h:783
CSR_DREAD_RST
@ CSR_DREAD_RST
Definition skge.h:775
CSR_DWRITE_RUN
@ CSR_DWRITE_RUN
Definition skge.h:776
CSR_FIFO_SET
@ CSR_FIFO_SET
Definition skge.h:769
CSR_STOP
@ CSR_STOP
Definition skge.h:782
CSR_IRQ_CL_B
@ CSR_IRQ_CL_B
Definition skge.h:785
CSR_ENA_POL
@ CSR_ENA_POL
Definition skge.h:780
CSR_DESC_SET
@ CSR_DESC_SET
Definition skge.h:767
CSR_TRANS_RST
@ CSR_TRANS_RST
Definition skge.h:779
CSR_DWRITE_RST
@ CSR_DWRITE_RST
Definition skge.h:777
CSR_DESC_CLR
@ CSR_DESC_CLR
Definition skge.h:766
CSR_HPI_RST
@ CSR_HPI_RST
Definition skge.h:771
CSR_SV_RST
@ CSR_SV_RST
Definition skge.h:773
CSR_SV_RUN
@ CSR_SV_RUN
Definition skge.h:772
CSR_DREAD_RUN
@ CSR_DREAD_RUN
Definition skge.h:774
CSR_IRQ_CL_C
@ CSR_IRQ_CL_C
Definition skge.h:787
CSR_IRQ_CL_P
@ CSR_IRQ_CL_P
Definition skge.h:784
CABD_STAT_SHORT
@ CABD_STAT_SHORT
Definition skge.h:1616
CABD_STAT_NORMAL
@ CABD_STAT_NORMAL
Definition skge.h:1615
CABD_STAT_OPEN
@ CABD_STAT_OPEN
Definition skge.h:1617
CABD_STAT_FAIL
@ CABD_STAT_FAIL
Definition skge.h:1618
GM_MIB_CNT_BASE
#define GM_MIB_CNT_BASE
Definition skge.h:1715
PA_ENA_TO_TX2
@ PA_ENA_TO_TX2
Definition skge.h:451
PA_RST_SET
@ PA_RST_SET
Definition skge.h:460
PA_CLR_TO_TX2
@ PA_CLR_TO_TX2
Definition skge.h:447
PA_RST_CLR
@ PA_RST_CLR
Definition skge.h:459
PA_ENA_TO_TX1
@ PA_ENA_TO_TX1
Definition skge.h:453
PA_DIS_TO_TX1
@ PA_DIS_TO_TX1
Definition skge.h:454
PA_ENA_TO_RX2
@ PA_ENA_TO_RX2
Definition skge.h:455
PA_CLR_TO_RX1
@ PA_CLR_TO_RX1
Definition skge.h:450
PA_DIS_TO_RX2
@ PA_DIS_TO_RX2
Definition skge.h:456
PA_DIS_TO_TX2
@ PA_DIS_TO_TX2
Definition skge.h:452
PA_DIS_TO_RX1
@ PA_DIS_TO_RX1
Definition skge.h:458
PA_CLR_TO_RX2
@ PA_CLR_TO_RX2
Definition skge.h:449
PA_CLR_TO_TX1
@ PA_CLR_TO_TX1
Definition skge.h:448
PA_ENA_TO_RX1
@ PA_ENA_TO_RX1
Definition skge.h:457
PHY_B_AS_LP_ANAB
@ PHY_B_AS_LP_ANAB
Definition skge.h:1301
PHY_B_AS_ANP_R
@ PHY_B_AS_ANP_R
Definition skge.h:1300
PHY_B_AS_PRT
@ PHY_B_AS_PRT
Definition skge.h:1305
PHY_B_AS_LS
@ PHY_B_AS_LS
Definition skge.h:1303
PHY_B_AS_PDF
@ PHY_B_AS_PDF
Definition skge.h:1298
PHY_B_AS_PRR
@ PHY_B_AS_PRR
Definition skge.h:1304
PHY_B_AS_AN_C
@ PHY_B_AS_AN_C
Definition skge.h:1292
PHY_B_AS_AN_CA
@ PHY_B_AS_AN_CA
Definition skge.h:1293
PHY_B_AS_ANACK_D
@ PHY_B_AS_ANACK_D
Definition skge.h:1294
PHY_B_AS_NPW
@ PHY_B_AS_NPW
Definition skge.h:1296
PHY_B_AS_ANAB_D
@ PHY_B_AS_ANAB_D
Definition skge.h:1295
PHY_B_AS_AN_RES_MSK
@ PHY_B_AS_AN_RES_MSK
Definition skge.h:1297
PHY_B_AS_LP_NPAB
@ PHY_B_AS_LP_NPAB
Definition skge.h:1302
PHY_B_AS_RF
@ PHY_B_AS_RF
Definition skge.h:1299
PHY_M_PC_MAC_POW_UP
@ PHY_M_PC_MAC_POW_UP
Definition skge.h:1399
PHY_M_PC_EN_DET_MSK
@ PHY_M_PC_EN_DET_MSK
Definition skge.h:1395
PHY_M_PC_MDIX_MSK
@ PHY_M_PC_MDIX_MSK
Definition skge.h:1397
PHY_M_PC_RX_FFD_MSK
@ PHY_M_PC_RX_FFD_MSK
Definition skge.h:1392
PHY_M_PC_POL_R_DIS
@ PHY_M_PC_POL_R_DIS
Definition skge.h:1401
PHY_M_PC_SQE_T_ENA
@ PHY_M_PC_SQE_T_ENA
Definition skge.h:1400
PHY_M_PC_TX_FFD_MSK
@ PHY_M_PC_TX_FFD_MSK
Definition skge.h:1391
PHY_M_PC_ASS_CRS_TX
@ PHY_M_PC_ASS_CRS_TX
Definition skge.h:1393
PHY_M_PC_ENA_EXT_D
@ PHY_M_PC_ENA_EXT_D
Definition skge.h:1396
PHY_M_PC_DIS_JABBER
@ PHY_M_PC_DIS_JABBER
Definition skge.h:1402
PHY_M_PC_FL_GOOD
@ PHY_M_PC_FL_GOOD
Definition skge.h:1394
PHY_M_PC_DIS_125CLK
@ PHY_M_PC_DIS_125CLK
Definition skge.h:1398
XM_RXF_511B
@ XM_RXF_511B
Definition skge.h:2161
XM_RXE_CAR_ERR
@ XM_RXE_CAR_ERR
Definition skge.h:2149
XM_TX_CNT_EV
@ XM_TX_CNT_EV
Definition skge.h:2106
XM_RX_EV_MSK
@ XM_RX_EV_MSK
Definition skge.h:2107
XM_RXF_127B
@ XM_RXF_127B
Definition skge.h:2159
XM_TXF_OK
@ XM_TXF_OK
Definition skge.h:2109
XM_TXF_255B
@ XM_TXF_255B
Definition skge.h:2130
XM_DEV_ID
@ XM_DEV_ID
Definition skge.h:2099
XM_RXE_SHT_ERR
@ XM_RXE_SHT_ERR
Definition skge.h:2152
XM_TXF_DEF
@ XM_TXF_DEF
Definition skge.h:2123
XM_RXE_FIFO_OV
@ XM_RXE_FIFO_OV
Definition skge.h:2147
XM_TXF_LONG
@ XM_TXF_LONG
Definition skge.h:2115
XM_TXF_BC_OK
@ XM_TXF_BC_OK
Definition skge.h:2112
XM_RXO_OK_HI
@ XM_RXO_OK_HI
Definition skge.h:2135
XM_TXF_SNG_COL
@ XM_TXF_SNG_COL
Definition skge.h:2119
XM_RXF_FRA_ERR
@ XM_RXF_FRA_ERR
Definition skge.h:2146
XM_TXF_UC_OK
@ XM_TXF_UC_OK
Definition skge.h:2114
XM_TXF_MPAUSE
@ XM_TXF_MPAUSE
Definition skge.h:2117
XM_TXF_127B
@ XM_TXF_127B
Definition skge.h:2129
XM_RXF_255B
@ XM_RXF_255B
Definition skge.h:2160
XM_TXF_MAX_SZ
@ XM_TXF_MAX_SZ
Definition skge.h:2133
XM_RXO_OK_LO
@ XM_RXO_OK_LO
Definition skge.h:2136
XM_TXO_OK_LO
@ XM_TXO_OK_LO
Definition skge.h:2111
XM_TXE_BURST
@ XM_TXE_BURST
Definition skge.h:2116
XM_TXE_FIFO_UR
@ XM_TXE_FIFO_UR
Definition skge.h:2125
XM_TXF_LAT_COL
@ XM_TXF_LAT_COL
Definition skge.h:2122
XM_TXF_MC_OK
@ XM_TXF_MC_OK
Definition skge.h:2113
XM_TXF_MUL_COL
@ XM_TXF_MUL_COL
Definition skge.h:2120
XM_RXF_64B
@ XM_RXF_64B
Definition skge.h:2158
XM_RXF_MPAUSE
@ XM_RXF_MPAUSE
Definition skge.h:2140
XM_RXF_MCTRL
@ XM_RXF_MCTRL
Definition skge.h:2141
XM_TX_EV_MSK
@ XM_TX_EV_MSK
Definition skge.h:2108
XM_TXF_MCTRL
@ XM_TXF_MCTRL
Definition skge.h:2118
XM_TXF_1023B
@ XM_TXF_1023B
Definition skge.h:2132
XM_SA
@ XM_SA
Definition skge.h:2094
XM_TXF_ABO_COL
@ XM_TXF_ABO_COL
Definition skge.h:2121
XM_RXF_CEX_ERR
@ XM_RXF_CEX_ERR
Definition skge.h:2156
XM_RXP_UTIL
@ XM_RXP_UTIL
Definition skge.h:2157
XM_RXF_1023B
@ XM_RXF_1023B
Definition skge.h:2162
XM_LSA
@ XM_LSA
Definition skge.h:2101
XM_RXF_MAX_SZ
@ XM_RXF_MAX_SZ
Definition skge.h:2163
XM_RXF_JAB_PKT
@ XM_RXF_JAB_PKT
Definition skge.h:2148
XM_RXF_MC_OK
@ XM_RXF_MC_OK
Definition skge.h:2138
XM_RXF_UC_OK
@ XM_RXF_UC_OK
Definition skge.h:2139
XM_RXF_LEN_ERR
@ XM_RXF_LEN_ERR
Definition skge.h:2150
XM_MODE
@ XM_MODE
Definition skge.h:2100
XM_SRC_CHK
@ XM_SRC_CHK
Definition skge.h:2093
XM_STAT_CMD
@ XM_STAT_CMD
Definition skge.h:2104
XM_RXF_LNG_ERR
@ XM_RXF_LNG_ERR
Definition skge.h:2154
XM_TXP_UTIL
@ XM_TXP_UTIL
Definition skge.h:2127
XM_RXF_INV_MOC
@ XM_RXF_INV_MOC
Definition skge.h:2143
XM_TXF_511B
@ XM_TXF_511B
Definition skge.h:2131
XM_TXF_64B
@ XM_TXF_64B
Definition skge.h:2128
XM_RXE_BURST
@ XM_RXE_BURST
Definition skge.h:2144
XM_TS_READ
@ XM_TS_READ
Definition skge.h:2102
XM_RXE_RUNT
@ XM_RXE_RUNT
Definition skge.h:2153
XM_RXF_OK
@ XM_RXF_OK
Definition skge.h:2134
XM_TXE_CS_ERR
@ XM_TXE_CS_ERR
Definition skge.h:2126
XM_RXF_BC_OK
@ XM_RXF_BC_OK
Definition skge.h:2137
XM_HSM
@ XM_HSM
Definition skge.h:2095
XM_RXE_SYM_ERR
@ XM_RXE_SYM_ERR
Definition skge.h:2151
XM_RXE_FMISS
@ XM_RXE_FMISS
Definition skge.h:2145
XM_TXO_OK_HI
@ XM_TXO_OK_HI
Definition skge.h:2110
XM_TS_LOAD
@ XM_TS_LOAD
Definition skge.h:2103
XM_TXF_EX_DEF
@ XM_TXF_EX_DEF
Definition skge.h:2124
XM_RX_THR
@ XM_RX_THR
Definition skge.h:2098
XM_RXF_FCS_ERR
@ XM_RXF_FCS_ERR
Definition skge.h:2155
XM_RX_CNT_EV
@ XM_RX_CNT_EV
Definition skge.h:2105
XM_RX_HI_WM
@ XM_RX_HI_WM
Definition skge.h:2097
XM_RX_LO_WM
@ XM_RX_LO_WM
Definition skge.h:2096
XM_RXF_INV_MP
@ XM_RXF_INV_MP
Definition skge.h:2142
PHY_M_CABD_STAT_MSK
@ PHY_M_CABD_STAT_MSK
Definition skge.h:1607
PHY_M_CABD_AMPL_MSK
@ PHY_M_CABD_AMPL_MSK
Definition skge.h:1608
PHY_M_CABD_DIST_MSK
@ PHY_M_CABD_DIST_MSK
Definition skge.h:1610
PHY_M_CABD_DIS_WAIT
@ PHY_M_CABD_DIS_WAIT
Definition skge.h:1605
PHY_M_CABD_ENA_TEST
@ PHY_M_CABD_ENA_TEST
Definition skge.h:1604
hw
Definition hw.c:16
io_buffer
A persistent I/O buffer.
Definition iobuf.h:38
net_device
A network device.
Definition netdevice.h:353
pci_device
A PCI device.
Definition pci.h:211
skge_element
Definition skge.h:2447
skge_element::next
struct skge_element * next
Definition skge.h:2448
skge_element::desc
void * desc
Definition skge.h:2449
skge_element::iob
struct io_buffer * iob
Definition skge.h:2450
skge_hw
Definition skge.h:2460
skge_hw::copper
u8 copper
Definition skge.h:2468
skge_hw::chip_id
u8 chip_id
Definition skge.h:2466
skge_hw::pdev
struct pci_device * pdev
Definition skge.h:2462
skge_hw::ram_offset
u32 ram_offset
Definition skge.h:2473
skge_hw::dev
struct net_device * dev[2]
Definition skge.h:2464
skge_hw::phy_addr
u16 phy_addr
Definition skge.h:2474
skge_hw::ram_size
u32 ram_size
Definition skge.h:2472
skge_hw::ports
u8 ports
Definition skge.h:2469
skge_hw::phy_type
u8 phy_type
Definition skge.h:2470
skge_hw::chip_rev
u8 chip_rev
Definition skge.h:2467
skge_hw::regs
unsigned long regs
Definition skge.h:2461
skge_hw::intr_mask
u32 intr_mask
Definition skge.h:2463
skge_port
Definition skge.h:2495
skge_port::hw
struct skge_hw * hw
Definition skge.h:2496
skge_port::advertising
u32 advertising
Definition skge.h:2508
skge_port::netdev
struct net_device * netdev
Definition skge.h:2497
skge_port::use_xm_link_timer
int use_xm_link_timer
Definition skge.h:2512
skge_port::flow_status
enum pause_status flow_status
Definition skge.h:2504
skge_port::port
int port
Definition skge.h:2498
skge_port::mem
void * mem
Definition skge.h:2510
skge_port::speed
u16 speed
Definition skge.h:2507
skge_port::dma
u32 dma
Definition skge.h:2511
skge_port::tx_ring
struct skge_ring tx_ring
Definition skge.h:2500
skge_port::autoneg
u8 autoneg
Definition skge.h:2505
skge_port::duplex
u8 duplex
Definition skge.h:2506
skge_port::flow_control
enum pause_control flow_control
Definition skge.h:2503
skge_port::rx_ring
struct skge_ring rx_ring
Definition skge.h:2501
skge_ring
Definition skge.h:2453
skge_ring::start
struct skge_element * start
Definition skge.h:2456
skge_ring::to_clean
struct skge_element * to_clean
Definition skge.h:2454
skge_ring::to_use
struct skge_element * to_use
Definition skge.h:2455
skge_rx_desc
Definition skge.h:2422
skge_rx_desc::timestamp
u32 timestamp
Definition skge.h:2428
skge_rx_desc::control
u32 control
Definition skge.h:2423
skge_rx_desc::csum2
u16 csum2
Definition skge.h:2429
skge_rx_desc::csum1
u16 csum1
Definition skge.h:2430
skge_rx_desc::csum2_start
u16 csum2_start
Definition skge.h:2431
skge_rx_desc::csum1_start
u16 csum1_start
Definition skge.h:2432
skge_rx_desc::status
u32 status
Definition skge.h:2427
skge_rx_desc::dma_lo
u32 dma_lo
Definition skge.h:2425
skge_rx_desc::dma_hi
u32 dma_hi
Definition skge.h:2426
skge_rx_desc::next_offset
u32 next_offset
Definition skge.h:2424
skge_tx_desc
Definition skge.h:2435
skge_tx_desc::rsvd
u32 rsvd
Definition skge.h:2444
skge_tx_desc::csum_write
u16 csum_write
Definition skge.h:2442
skge_tx_desc::csum_start
u16 csum_start
Definition skge.h:2443
skge_tx_desc::status
u32 status
Definition skge.h:2440
skge_tx_desc::csum_offs
u32 csum_offs
Definition skge.h:2441
skge_tx_desc::dma_hi
u32 dma_hi
Definition skge.h:2439
skge_tx_desc::next_offset
u32 next_offset
Definition skge.h:2437
skge_tx_desc::dma_lo
u32 dma_lo
Definition skge.h:2438
skge_tx_desc::control
u32 control
Definition skge.h:2436
u16
#define u16
Definition vga.h:20
u32
#define u32
Definition vga.h:21
readl
#define readl
Definition w89c840.c:157
writel
#define writel
Definition w89c840.c:160
writew
#define writew
Definition w89c840.c:159
readb
#define readb
Definition w89c840.c:155
writeb
#define writeb
Definition w89c840.c:158
readw
#define readw
Definition w89c840.c:156
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