iPXE
Data Structures | Macros | Enumerations | Functions
skge.h File Reference

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Data Structures

struct  skge_rx_desc
 
struct  skge_tx_desc
 
struct  skge_element
 
struct  skge_ring
 
struct  skge_hw
 
struct  skge_port
 

Macros

#define PCI_DEV_REG1   0x40
 
#define PCI_PHY_COMA   0x8000000
 
#define PCI_VIO   0x2000000
 
#define PCI_DEV_REG2   0x44
 
#define PCI_VPD_ROM_SZ   7L<<14 /* VPD ROM size 0=256, 1=512, ... */
 
#define PCI_REV_DESC   1<<2 /* Reverse Descriptor bytes */
 
#define DRV_NAME   "skge"
 
#define DRV_VERSION   "1.13"
 
#define PFX   DRV_NAME " "
 
#define NUM_TX_DESC   8
 
#define NUM_RX_DESC   8
 
#define SKGE_RING_ALIGN   8
 
#define RX_BUF_SIZE   1536
 
#define PHY_RETRIES   1000
 
#define TX_RING_SIZE   ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) )
 
#define RX_RING_SIZE   ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) )
 
#define RING_SIZE   ( TX_RING_SIZE + RX_RING_SIZE )
 
#define SKGE_REG_SIZE   0x4000
 
#define SKGE_EEPROM_MAGIC   0x9933aabb
 
#define AUTONEG_DISABLE   0x00
 
#define AUTONEG_ENABLE   0x01
 
#define DUPLEX_HALF   0x00
 
#define DUPLEX_FULL   0x01
 
#define SPEED_10   10
 
#define SPEED_100   100
 
#define SPEED_1000   1000
 
#define ADVERTISED_10baseT_Half   (1 << 0)
 
#define ADVERTISED_10baseT_Full   (1 << 1)
 
#define ADVERTISED_100baseT_Half   (1 << 2)
 
#define ADVERTISED_100baseT_Full   (1 << 3)
 
#define ADVERTISED_1000baseT_Half   (1 << 4)
 
#define ADVERTISED_1000baseT_Full   (1 << 5)
 
#define SUPPORTED_10baseT_Half   (1 << 0)
 
#define SUPPORTED_10baseT_Full   (1 << 1)
 
#define SUPPORTED_100baseT_Half   (1 << 2)
 
#define SUPPORTED_100baseT_Full   (1 << 3)
 
#define SUPPORTED_1000baseT_Half   (1 << 4)
 
#define SUPPORTED_1000baseT_Full   (1 << 5)
 
#define SUPPORTED_Autoneg   (1 << 6)
 
#define SUPPORTED_TP   (1 << 7)
 
#define SUPPORTED_FIBRE   (1 << 10)
 
#define PCI_STATUS_ERROR_BITS
 
#define RAM_ADR_RAN   0x0007ffffL /* Bit 18.. 0: RAM Address Range */
 
#define SK_MAC_TO_53   72 /* MAC arbiter timeout */
 
#define SK_PKT_TO_53   0x2000 /* Packet arbiter timeout */
 
#define SK_PKT_TO_MAX   0xffff /* Maximum value */
 
#define SK_RI_TO_53   36 /* RAM interface timeout */
 
#define PA_ENA_TO_ALL
 
#define TXA_MAX_VAL   0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
 
#define Q_ADDR(reg, offs)   (B8_Q_REGS + (reg) + (offs))
 
#define RB_ADDR(offs, queue)   ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
 
#define CSR_SET_RESET
 
#define CSR_CLR_RESET
 
#define RB_MSK   0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
 
#define SK_XMIT_DUR   0x002faf08UL /* 50 ms */
 
#define SK_BLK_DUR   0x01dcd650UL /* 500 ms */
 
#define SK_DPOLL_DEF   0x00ee6b28UL /* 250 ms at 62.5 MHz */
 
#define SK_DPOLL_MAX   0x00ffffffUL /* 268 ms at 62.5 MHz */
 
#define SK_FACT_62   100 /* is given in percent */
 
#define SK_FACT_53   85 /* on GENESIS: 53.12 MHz */
 
#define SK_FACT_78   125 /* on YUKON: 78.12 MHz */
 
#define WOL_REGS(port, x)   (x + (port)*0x80)
 
#define WOL_PATT_RAM_BASE(port)   (WOL_PATT_RAM_1 + (port)*0x400)
 
#define PHY_B_AS_PAUSE_MSK   (PHY_B_AS_PRR | PHY_B_AS_PRT)
 
#define PHY_B_DEF_MSK
 
#define PHY_M_PS_PAUSE_MSK   (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
 
#define PHY_M_EC_M_DSC(x)   ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
 
#define PHY_M_EC_S_DSC(x)   ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
 
#define PHY_M_EC_MAC_S(x)   ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
 
#define PHY_M_EC_M_DSC_2(x)   ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
 
#define PHY_M_LED_PULS_DUR(x)   (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
 
#define PHY_M_LED_BLINK_RT(x)   (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
 
#define PHY_M_LED_MO_SGMII(x)   ((x)<<14) /* Bit 15..14: SGMII AN Timer */
 
#define PHY_M_LED_MO_DUP(x)   ((x)<<10) /* Bit 11..10: Duplex */
 
#define PHY_M_LED_MO_10(x)   ((x)<<8) /* Bit 9.. 8: Link 10 */
 
#define PHY_M_LED_MO_100(x)   ((x)<<6) /* Bit 7.. 6: Link 100 */
 
#define PHY_M_LED_MO_1000(x)   ((x)<<4) /* Bit 5.. 4: Link 1000 */
 
#define PHY_M_LED_MO_RX(x)   ((x)<<2) /* Bit 3.. 2: Rx */
 
#define PHY_M_LED_MO_TX(x)   ((x)<<0) /* Bit 1.. 0: Tx */
 
#define PHY_M_FELP_LED2_CTRL(x)   (((x)<<8) & PHY_M_FELP_LED2_MSK)
 
#define PHY_M_FELP_LED1_CTRL(x)   (((x)<<4) & PHY_M_FELP_LED1_MSK)
 
#define PHY_M_FELP_LED0_CTRL(x)   (((x)<<0) & PHY_M_FELP_LED0_MSK)
 
#define PHY_M_LEDC_LOS_CTRL(x)   (((x)<<12) & PHY_M_LEDC_LOS_MSK)
 
#define PHY_M_LEDC_INIT_CTRL(x)   (((x)<<8) & PHY_M_LEDC_INIT_MSK)
 
#define PHY_M_LEDC_STA1_CTRL(x)   (((x)<<4) & PHY_M_LEDC_STA1_MSK)
 
#define PHY_M_LEDC_STA0_CTRL(x)   (((x)<<0) & PHY_M_LEDC_STA0_MSK)
 
#define GM_MIB_CNT_BASE   0x0100 /* Base Address of MIB Counters */
 
#define GM_MIB_CNT_SIZE   44 /* Number of MIB Counters */
 
#define GM_GPCR_SPEED_1000   (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
 
#define GM_GPCR_AU_ALL_DIS   (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
 
#define TX_COL_THR(x)   (((x)<<10) & GM_TXCR_COL_THR_MSK)
 
#define TX_COL_DEF   0x04 /* late collision after 64 byte */
 
#define TX_JAM_LEN_VAL(x)   (((x)<<14) & GM_TXPA_JAMLEN_MSK)
 
#define TX_JAM_IPG_VAL(x)   (((x)<<9) & GM_TXPA_JAMIPG_MSK)
 
#define TX_IPG_JAM_DATA(x)   (((x)<<4) & GM_TXPA_JAMDAT_MSK)
 
#define DATA_BLIND_VAL(x)   (((x)<<11) & GM_SMOD_DATABL_MSK)
 
#define DATA_BLIND_DEF   0x04
 
#define IPG_DATA_VAL(x)   (x & GM_SMOD_IPG_MSK)
 
#define IPG_DATA_DEF   0x1e
 
#define GM_SMI_CT_PHY_AD(x)   (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
 
#define GM_SMI_CT_REG_AD(x)   (((x)<<6) & GM_SMI_CT_REG_A_MSK)
 
#define GPC_HWCFG_GMII_COP   (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
 
#define GPC_HWCFG_GMII_FIB   (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
 
#define GPC_ANEG_ADV_ALL_M   (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
 
#define GPC_FRC10MBIT_HALF   0
 
#define GPC_FRC10MBIT_FULL   GPC_ANEG_0
 
#define GPC_FRC100MBIT_HALF   GPC_ANEG_1
 
#define GPC_FRC100MBIT_FULL   (GPC_ANEG_0 | GPC_ANEG_1)
 
#define GPC_ADV_1000_HALF   GPC_ANEG_2
 
#define GPC_ADV_1000_FULL   GPC_ANEG_3
 
#define GPC_ADV_ALL   (GPC_ANEG_2 | GPC_ANEG_3)
 
#define GPC_FORCE_MASTER   0
 
#define GPC_FORCE_SLAVE   GPC_ANEG_0
 
#define GPC_PREF_MASTER   GPC_ANEG_1
 
#define GPC_PREF_SLAVE   (GPC_ANEG_1 | GPC_ANEG_0)
 
#define GMAC_DEF_MSK   (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
 
#define WOL_CTL_DEFAULT
 
#define WOL_CTL_PATT_ENA(x)   (1 << (x))
 
#define XM_EXM(reg)   (XM_EXM_START + ((reg) << 3))
 
#define XM_RT_LIM_MSK   0x1f /* Bit 4..0: Tx Retry Limit */
 
#define XM_STIME_MSK   0x7f /* Bit 6..0: Tx Slottime bits */
 
#define XM_IPG_MSK   0xff /* Bit 7..0: IPG value bits */
 
#define XM_TX_WM_MSK   0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
 
#define XM_THR_MSK   0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
 
#define XM_RX_WM_MSK   0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
 
#define XM_DEV_OUI   (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
 
#define XM_DEV_REV   (0x07L << 5) /* Bit 7..5: Chip Rev Num */
 
#define XM_PAUSE_MODE   (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
 
#define XM_DEF_MODE
 
#define XMR_DEF_MSK   (XMR_OK_LO_OV | XMR_OK_HI_OV)
 
#define XMT_DEF_MSK   (XMT_OK_LO_OV | XMT_OK_HI_OV)
 
#define SK_REG(port, reg)   (((port)<<7)+(u16)(reg))
 
#define SK_XMAC_REG(port, reg)   ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
 
#define SK_GMAC_REG(port, reg)   (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
 

Enumerations

enum  csr_regs {
  B0_RAP = 0x0000, B0_CTST = 0x0004, B0_LED = 0x0006, B0_POWER_CTRL = 0x0007,
  B0_ISRC = 0x0008, B0_IMSK = 0x000c, B0_HWE_ISRC = 0x0010, B0_HWE_IMSK = 0x0014,
  B0_SP_ISRC = 0x0018, B0_XM1_IMSK = 0x0020, B0_XM1_ISRC = 0x0028, B0_XM1_PHY_ADDR = 0x0030,
  B0_XM1_PHY_DATA = 0x0034, B0_XM2_IMSK = 0x0040, B0_XM2_ISRC = 0x0048, B0_XM2_PHY_ADDR = 0x0050,
  B0_XM2_PHY_DATA = 0x0054, B0_R1_CSR = 0x0060, B0_R2_CSR = 0x0064, B0_XS1_CSR = 0x0068,
  B0_XA1_CSR = 0x006c, B0_XS2_CSR = 0x0070, B0_XA2_CSR = 0x0074, B2_MAC_1 = 0x0100,
  B2_MAC_2 = 0x0108, B2_MAC_3 = 0x0110, B2_CONN_TYP = 0x0118, B2_PMD_TYP = 0x0119,
  B2_MAC_CFG = 0x011a, B2_CHIP_ID = 0x011b, B2_E_0 = 0x011c, B2_E_1 = 0x011d,
  B2_E_2 = 0x011e, B2_E_3 = 0x011f, B2_FAR = 0x0120, B2_FDP = 0x0124,
  B2_LD_CTRL = 0x0128, B2_LD_TEST = 0x0129, B2_TI_INI = 0x0130, B2_TI_VAL = 0x0134,
  B2_TI_CTRL = 0x0138, B2_TI_TEST = 0x0139, B2_IRQM_INI = 0x0140, B2_IRQM_VAL = 0x0144,
  B2_IRQM_CTRL = 0x0148, B2_IRQM_TEST = 0x0149, B2_IRQM_MSK = 0x014c, B2_IRQM_HWE_MSK = 0x0150,
  B2_TST_CTRL1 = 0x0158, B2_TST_CTRL2 = 0x0159, B2_GP_IO = 0x015c, B2_I2C_CTRL = 0x0160,
  B2_I2C_DATA = 0x0164, B2_I2C_IRQ = 0x0168, B2_I2C_SW = 0x016c, B2_BSC_INI = 0x0170,
  B2_BSC_VAL = 0x0174, B2_BSC_CTRL = 0x0178, B2_BSC_STAT = 0x0179, B2_BSC_TST = 0x017a,
  B3_RAM_ADDR = 0x0180, B3_RAM_DATA_LO = 0x0184, B3_RAM_DATA_HI = 0x0188, B3_RI_WTO_R1 = 0x0190,
  B3_RI_WTO_XA1 = 0x0191, B3_RI_WTO_XS1 = 0x0192, B3_RI_RTO_R1 = 0x0193, B3_RI_RTO_XA1 = 0x0194,
  B3_RI_RTO_XS1 = 0x0195, B3_RI_WTO_R2 = 0x0196, B3_RI_WTO_XA2 = 0x0197, B3_RI_WTO_XS2 = 0x0198,
  B3_RI_RTO_R2 = 0x0199, B3_RI_RTO_XA2 = 0x019a, B3_RI_RTO_XS2 = 0x019b, B3_RI_TO_VAL = 0x019c,
  B3_RI_CTRL = 0x01a0, B3_RI_TEST = 0x01a2, B3_MA_TOINI_RX1 = 0x01b0, B3_MA_TOINI_RX2 = 0x01b1,
  B3_MA_TOINI_TX1 = 0x01b2, B3_MA_TOINI_TX2 = 0x01b3, B3_MA_TOVAL_RX1 = 0x01b4, B3_MA_TOVAL_RX2 = 0x01b5,
  B3_MA_TOVAL_TX1 = 0x01b6, B3_MA_TOVAL_TX2 = 0x01b7, B3_MA_TO_CTRL = 0x01b8, B3_MA_TO_TEST = 0x01ba,
  B3_MA_RCINI_RX1 = 0x01c0, B3_MA_RCINI_RX2 = 0x01c1, B3_MA_RCINI_TX1 = 0x01c2, B3_MA_RCINI_TX2 = 0x01c3,
  B3_MA_RCVAL_RX1 = 0x01c4, B3_MA_RCVAL_RX2 = 0x01c5, B3_MA_RCVAL_TX1 = 0x01c6, B3_MA_RCVAL_TX2 = 0x01c7,
  B3_MA_RC_CTRL = 0x01c8, B3_MA_RC_TEST = 0x01ca, B3_PA_TOINI_RX1 = 0x01d0, B3_PA_TOINI_RX2 = 0x01d4,
  B3_PA_TOINI_TX1 = 0x01d8, B3_PA_TOINI_TX2 = 0x01dc, B3_PA_TOVAL_RX1 = 0x01e0, B3_PA_TOVAL_RX2 = 0x01e4,
  B3_PA_TOVAL_TX1 = 0x01e8, B3_PA_TOVAL_TX2 = 0x01ec, B3_PA_CTRL = 0x01f0, B3_PA_TEST = 0x01f2,
  B0_RAP = 0x0000, B0_CTST = 0x0004, B0_Y2LED = 0x0005, B0_POWER_CTRL = 0x0007,
  B0_ISRC = 0x0008, B0_IMSK = 0x000c, B0_HWE_ISRC = 0x0010, B0_HWE_IMSK = 0x0014,
  B0_Y2_SP_ISRC2 = 0x001c, B0_Y2_SP_ISRC3 = 0x0020, B0_Y2_SP_EISR = 0x0024, B0_Y2_SP_LISR = 0x0028,
  B0_Y2_SP_ICR = 0x002c, B2_MAC_1 = 0x0100, B2_MAC_2 = 0x0108, B2_MAC_3 = 0x0110,
  B2_CONN_TYP = 0x0118, B2_PMD_TYP = 0x0119, B2_MAC_CFG = 0x011a, B2_CHIP_ID = 0x011b,
  B2_E_0 = 0x011c, B2_Y2_CLK_GATE = 0x011d, B2_Y2_HW_RES = 0x011e, B2_E_3 = 0x011f,
  B2_Y2_CLK_CTRL = 0x0120, B2_TI_INI = 0x0130, B2_TI_VAL = 0x0134, B2_TI_CTRL = 0x0138,
  B2_TI_TEST = 0x0139, B2_TST_CTRL1 = 0x0158, B2_TST_CTRL2 = 0x0159, B2_GP_IO = 0x015c,
  B2_I2C_CTRL = 0x0160, B2_I2C_DATA = 0x0164, B2_I2C_IRQ = 0x0168, B2_I2C_SW = 0x016c,
  B3_RAM_ADDR = 0x0180, B3_RAM_DATA_LO = 0x0184, B3_RAM_DATA_HI = 0x0188, B3_RI_WTO_R1 = 0x0190,
  B3_RI_WTO_XA1 = 0x0191, B3_RI_WTO_XS1 = 0x0192, B3_RI_RTO_R1 = 0x0193, B3_RI_RTO_XA1 = 0x0194,
  B3_RI_RTO_XS1 = 0x0195, B3_RI_WTO_R2 = 0x0196, B3_RI_WTO_XA2 = 0x0197, B3_RI_WTO_XS2 = 0x0198,
  B3_RI_RTO_R2 = 0x0199, B3_RI_RTO_XA2 = 0x019a, B3_RI_RTO_XS2 = 0x019b, B3_RI_TO_VAL = 0x019c,
  B3_RI_CTRL = 0x01a0, B3_RI_TEST = 0x01a2, B3_MA_TOINI_RX1 = 0x01b0, B3_MA_TOINI_RX2 = 0x01b1,
  B3_MA_TOINI_TX1 = 0x01b2, B3_MA_TOINI_TX2 = 0x01b3, B3_MA_TOVAL_RX1 = 0x01b4, B3_MA_TOVAL_RX2 = 0x01b5,
  B3_MA_TOVAL_TX1 = 0x01b6, B3_MA_TOVAL_TX2 = 0x01b7, B3_MA_TO_CTRL = 0x01b8, B3_MA_TO_TEST = 0x01ba,
  B3_MA_RCINI_RX1 = 0x01c0, B3_MA_RCINI_RX2 = 0x01c1, B3_MA_RCINI_TX1 = 0x01c2, B3_MA_RCINI_TX2 = 0x01c3,
  B3_MA_RCVAL_RX1 = 0x01c4, B3_MA_RCVAL_RX2 = 0x01c5, B3_MA_RCVAL_TX1 = 0x01c6, B3_MA_RCVAL_TX2 = 0x01c7,
  B3_MA_RC_CTRL = 0x01c8, B3_MA_RC_TEST = 0x01ca, B3_PA_TOINI_RX1 = 0x01d0, B3_PA_TOINI_RX2 = 0x01d4,
  B3_PA_TOINI_TX1 = 0x01d8, B3_PA_TOINI_TX2 = 0x01dc, B3_PA_TOVAL_RX1 = 0x01e0, B3_PA_TOVAL_RX2 = 0x01e4,
  B3_PA_TOVAL_TX1 = 0x01e8, B3_PA_TOVAL_TX2 = 0x01ec, B3_PA_CTRL = 0x01f0, B3_PA_TEST = 0x01f2,
  Y2_CFG_SPC = 0x1c00, Y2_CFG_AER = 0x1d00
}
 
enum  {
  CS_CLK_RUN_HOT = 1<<13, CS_CLK_RUN_RST = 1<<12, CS_CLK_RUN_ENA = 1<<11, CS_VAUX_AVAIL = 1<<10,
  CS_BUS_CLOCK = 1<<9, CS_BUS_SLOT_SZ = 1<<8, CS_ST_SW_IRQ = 1<<7, CS_CL_SW_IRQ = 1<<6,
  CS_STOP_DONE = 1<<5, CS_STOP_MAST = 1<<4, CS_MRST_CLR = 1<<3, CS_MRST_SET = 1<<2,
  CS_RST_CLR = 1<<1, CS_RST_SET = 1, LED_STAT_ON = 1<<1, LED_STAT_OFF = 1,
  PC_VAUX_ENA = 1<<7, PC_VAUX_DIS = 1<<6, PC_VCC_ENA = 1<<5, PC_VCC_DIS = 1<<4,
  PC_VAUX_ON = 1<<3, PC_VAUX_OFF = 1<<2, PC_VCC_ON = 1<<1, PC_VCC_OFF = 1<<0
}
 
enum  {
  IS_ALL_MSK = 0xbffffffful, IS_HW_ERR = 1<<31, IS_PA_TO_RX1 = 1<<29, IS_PA_TO_RX2 = 1<<28,
  IS_PA_TO_TX1 = 1<<27, IS_PA_TO_TX2 = 1<<26, IS_I2C_READY = 1<<25, IS_IRQ_SW = 1<<24,
  IS_EXT_REG = 1<<23, IS_TIMINT = 1<<22, IS_MAC1 = 1<<21, IS_LNK_SYNC_M1 = 1<<20,
  IS_MAC2 = 1<<19, IS_LNK_SYNC_M2 = 1<<18, IS_R1_B = 1<<17, IS_R1_F = 1<<16,
  IS_R1_C = 1<<15, IS_R2_B = 1<<14, IS_R2_F = 1<<13, IS_R2_C = 1<<12,
  IS_XS1_B = 1<<11, IS_XS1_F = 1<<10, IS_XS1_C = 1<<9, IS_XA1_B = 1<<8,
  IS_XA1_F = 1<<7, IS_XA1_C = 1<<6, IS_XS2_B = 1<<5, IS_XS2_F = 1<<4,
  IS_XS2_C = 1<<3, IS_XA2_B = 1<<2, IS_XA2_F = 1<<1, IS_XA2_C = 1<<0,
  IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1, IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2, IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1, IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2
}
 
enum  {
  IS_IRQ_TIST_OV = 1<<13, IS_IRQ_SENSOR = 1<<12, IS_IRQ_MST_ERR = 1<<11, IS_IRQ_STAT = 1<<10,
  IS_NO_STAT_M1 = 1<<9, IS_NO_STAT_M2 = 1<<8, IS_NO_TIST_M1 = 1<<7, IS_NO_TIST_M2 = 1<<6,
  IS_RAM_RD_PAR = 1<<5, IS_RAM_WR_PAR = 1<<4, IS_M1_PAR_ERR = 1<<3, IS_M2_PAR_ERR = 1<<2,
  IS_R1_PAR_ERR = 1<<1, IS_R2_PAR_ERR = 1<<0, IS_ERR_MSK
}
 
enum  {
  TST_FRC_DPERR_MR = 1<<7, TST_FRC_DPERR_MW = 1<<6, TST_FRC_DPERR_TR = 1<<5, TST_FRC_DPERR_TW = 1<<4,
  TST_FRC_APERR_M = 1<<3, TST_FRC_APERR_T = 1<<2, TST_CFG_WRITE_ON = 1<<1, TST_CFG_WRITE_OFF = 1<<0
}
 
enum  { CFG_CHIP_R_MSK = 0xf<<4, CFG_DIS_M2_CLK = 1<<1, CFG_SNG_MAC = 1<<0 }
 
enum  {
  CHIP_ID_GENESIS = 0x0a, CHIP_ID_YUKON = 0xb0, CHIP_ID_YUKON_LITE = 0xb1, CHIP_ID_YUKON_LP = 0xb2,
  CHIP_ID_YUKON_XL = 0xb3, CHIP_ID_YUKON_EC = 0xb6, CHIP_ID_YUKON_FE = 0xb7, CHIP_REV_YU_LITE_A1 = 3,
  CHIP_REV_YU_LITE_A3 = 7
}
 
enum  { TIM_START = 1<<2, TIM_STOP = 1<<1, TIM_CLR_IRQ = 1<<0 }
 
enum  { TIM_T_ON = 1<<2, TIM_T_OFF = 1<<1, TIM_T_STEP = 1<<0 }
 
enum  {
  GP_DIR_9 = 1<<25, GP_DIR_8 = 1<<24, GP_DIR_7 = 1<<23, GP_DIR_6 = 1<<22,
  GP_DIR_5 = 1<<21, GP_DIR_4 = 1<<20, GP_DIR_3 = 1<<19, GP_DIR_2 = 1<<18,
  GP_DIR_1 = 1<<17, GP_DIR_0 = 1<<16, GP_IO_9 = 1<<9, GP_IO_8 = 1<<8,
  GP_IO_7 = 1<<7, GP_IO_6 = 1<<6, GP_IO_5 = 1<<5, GP_IO_4 = 1<<4,
  GP_IO_3 = 1<<3, GP_IO_2 = 1<<2, GP_IO_1 = 1<<1, GP_IO_0 = 1<<0
}
 
enum  {
  BMU_OWN = 1<<31, BMU_STF = 1<<30, BMU_EOF = 1<<29, BMU_IRQ_EOB = 1<<28,
  BMU_IRQ_EOF = 1<<27, BMU_STFWD = 1<<26, BMU_NO_FCS = 1<<25, BMU_SW = 1<<24,
  BMU_DEV_0 = 1<<26, BMU_STAT_VAL = 1<<25, BMU_TIST_VAL = 1<<24, BMU_CHECK = 0x55<<16,
  BMU_TCP_CHECK = 0x56<<16, BMU_UDP_CHECK = 0x57<<16, BMU_BBC = 0xffffL
}
 
enum  { BSC_START = 1<<1, BSC_STOP = 1<<0 }
 
enum  { BSC_SRC = 1<<0 }
 
enum  { BSC_T_ON = 1<<2, BSC_T_OFF = 1<<1, BSC_T_STEP = 1<<0 }
 
enum  { RI_CLR_RD_PERR = 1<<9, RI_CLR_WR_PERR = 1<<8, RI_RST_CLR = 1<<1, RI_RST_SET = 1<<0 }
 
enum  { MA_FOE_ON = 1<<3, MA_FOE_OFF = 1<<2, MA_RST_CLR = 1<<1, MA_RST_SET = 1<<0 }
 
enum  {
  PA_CLR_TO_TX2 = 1<<13, PA_CLR_TO_TX1 = 1<<12, PA_CLR_TO_RX2 = 1<<11, PA_CLR_TO_RX1 = 1<<10,
  PA_ENA_TO_TX2 = 1<<9, PA_DIS_TO_TX2 = 1<<8, PA_ENA_TO_TX1 = 1<<7, PA_DIS_TO_TX1 = 1<<6,
  PA_ENA_TO_RX2 = 1<<5, PA_DIS_TO_RX2 = 1<<4, PA_ENA_TO_RX1 = 1<<3, PA_DIS_TO_RX1 = 1<<2,
  PA_RST_CLR = 1<<1, PA_RST_SET = 1<<0
}
 
enum  {
  TXA_ENA_FSYNC = 1<<7, TXA_DIS_FSYNC = 1<<6, TXA_ENA_ALLOC = 1<<5, TXA_DIS_ALLOC = 1<<4,
  TXA_START_RC = 1<<3, TXA_STOP_RC = 1<<2, TXA_ENA_ARB = 1<<1, TXA_DIS_ARB = 1<<0
}
 
enum  {
  TXA_ITI_INI = 0x0200, TXA_ITI_VAL = 0x0204, TXA_LIM_INI = 0x0208, TXA_LIM_VAL = 0x020c,
  TXA_CTRL = 0x0210, TXA_TEST = 0x0211, TXA_STAT = 0x0212
}
 
enum  {
  B6_EXT_REG = 0x0300, B7_CFG_SPC = 0x0380, B8_RQ1_REGS = 0x0400, B8_RQ2_REGS = 0x0480,
  B8_TS1_REGS = 0x0600, B8_TA1_REGS = 0x0680, B8_TS2_REGS = 0x0700, B8_TA2_REGS = 0x0780,
  B16_RAM_REGS = 0x0800
}
 
enum  {
  B8_Q_REGS = 0x0400, Q_D = 0x00, Q_DA_L = 0x20, Q_DA_H = 0x24,
  Q_AC_L = 0x28, Q_AC_H = 0x2c, Q_BC = 0x30, Q_CSR = 0x34,
  Q_F = 0x38, Q_T1 = 0x3c, Q_T1_TR = 0x3c, Q_T1_WR = 0x3d,
  Q_T1_RD = 0x3e, Q_T1_SV = 0x3f, Q_T2 = 0x40, Q_T3 = 0x44
}
 
enum  {
  RB_START = 0x00, RB_END = 0x04, RB_WP = 0x08, RB_RP = 0x0c,
  RB_RX_UTPP = 0x10, RB_RX_LTPP = 0x14, RB_RX_UTHP = 0x18, RB_RX_LTHP = 0x1c,
  RB_PC = 0x20, RB_LEV = 0x24, RB_CTRL = 0x28, RB_TST1 = 0x29,
  RB_TST2 = 0x2a
}
 
enum  {
  Q_R1 = 0x0000, Q_R2 = 0x0080, Q_XS1 = 0x0200, Q_XA1 = 0x0280,
  Q_XS2 = 0x0300, Q_XA2 = 0x0380
}
 
enum  { SK_MAC_XMAC = 0, SK_MAC_GMAC = 1 }
 
enum  {
  SK_PHY_XMAC = 0, SK_PHY_BCOM = 1, SK_PHY_LONE = 2, SK_PHY_NAT = 3,
  SK_PHY_MARV_COPPER = 4, SK_PHY_MARV_FIBER = 5
}
 
enum  { PHY_ADDR_XMAC = 0<<8, PHY_ADDR_BCOM = 1<<8, PHY_ADDR_MARV = 0 }
 
enum  {
  RX_MFF_EA = 0x0c00, RX_MFF_WP = 0x0c04, RX_MFF_RP = 0x0c0c, RX_MFF_PC = 0x0c10,
  RX_MFF_LEV = 0x0c14, RX_MFF_CTRL1 = 0x0c18, RX_MFF_STAT_TO = 0x0c1a, RX_MFF_TIST_TO = 0x0c1b,
  RX_MFF_CTRL2 = 0x0c1c, RX_MFF_TST1 = 0x0c1d, RX_MFF_TST2 = 0x0c1e, RX_LED_INI = 0x0c20,
  RX_LED_VAL = 0x0c24, RX_LED_CTRL = 0x0c28, RX_LED_TST = 0x0c29, LNK_SYNC_INI = 0x0c30,
  LNK_SYNC_VAL = 0x0c34, LNK_SYNC_CTRL = 0x0c38, LNK_SYNC_TST = 0x0c39, LNK_LED_REG = 0x0c3c
}
 
enum  {
  MFF_ENA_RDY_PAT = 1<<13, MFF_DIS_RDY_PAT = 1<<12, MFF_ENA_TIM_PAT = 1<<11, MFF_DIS_TIM_PAT = 1<<10,
  MFF_ENA_ALM_FUL = 1<<9, MFF_DIS_ALM_FUL = 1<<8, MFF_ENA_PAUSE = 1<<7, MFF_DIS_PAUSE = 1<<6,
  MFF_ENA_FLUSH = 1<<5, MFF_DIS_FLUSH = 1<<4, MFF_ENA_TIST = 1<<3, MFF_DIS_TIST = 1<<2,
  MFF_CLR_INTIST = 1<<1, MFF_CLR_INSTAT = 1<<0, MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT
}
 
enum  {
  MFF_CLR_PERR = 1<<15, MFF_ENA_PKT_REC = 1<<13, MFF_DIS_PKT_REC = 1<<12, MFF_ENA_W4E = 1<<7,
  MFF_DIS_W4E = 1<<6, MFF_ENA_LOOPB = 1<<3, MFF_DIS_LOOPB = 1<<2, MFF_CLR_MAC_RST = 1<<1,
  MFF_SET_MAC_RST = 1<<0, MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH
}
 
enum  {
  MFF_WSP_T_ON = 1<<6, MFF_WSP_T_OFF = 1<<5, MFF_WSP_INC = 1<<4, MFF_PC_DEC = 1<<3,
  MFF_PC_T_ON = 1<<2, MFF_PC_T_OFF = 1<<1, MFF_PC_INC = 1<<0
}
 
enum  {
  MFF_WP_T_ON = 1<<6, MFF_WP_T_OFF = 1<<5, MFF_WP_INC = 1<<4, MFF_RP_T_ON = 1<<2,
  MFF_RP_T_OFF = 1<<1, MFF_RP_DEC = 1<<0
}
 
enum  { MFF_ENA_OP_MD = 1<<3, MFF_DIS_OP_MD = 1<<2, MFF_RST_CLR = 1<<1, MFF_RST_SET = 1<<0 }
 
enum  { LED_START = 1<<2, LED_STOP = 1<<1, LED_STATE = 1<<0 }
 
enum  { LED_T_ON = 1<<2, LED_T_OFF = 1<<1, LED_T_STEP = 1<<0 }
 
enum  {
  LED_BLK_ON = 1<<5, LED_BLK_OFF = 1<<4, LED_SYNC_ON = 1<<3, LED_SYNC_OFF = 1<<2,
  LED_ON = 1<<1, LED_OFF = 1<<0
}
 
enum  {
  RX_GMF_EA = 0x0c40, RX_GMF_AF_THR = 0x0c44, RX_GMF_CTRL_T = 0x0c48, RX_GMF_FL_MSK = 0x0c4c,
  RX_GMF_FL_THR = 0x0c50, RX_GMF_WP = 0x0c60, RX_GMF_WLEV = 0x0c68, RX_GMF_RP = 0x0c70,
  RX_GMF_RLEV = 0x0c78
}
 
enum  {
  TXA_INT_T_ON = 1<<5, TXA_INT_T_OFF = 1<<4, TXA_INT_T_STEP = 1<<3, TXA_LIM_T_ON = 1<<2,
  TXA_LIM_T_OFF = 1<<1, TXA_LIM_T_STEP = 1<<0
}
 
enum  { TXA_PRIO_XS = 1<<0 }
 
enum  {
  CSR_SV_IDLE = 1<<24, CSR_DESC_CLR = 1<<21, CSR_DESC_SET = 1<<20, CSR_FIFO_CLR = 1<<19,
  CSR_FIFO_SET = 1<<18, CSR_HPI_RUN = 1<<17, CSR_HPI_RST = 1<<16, CSR_SV_RUN = 1<<15,
  CSR_SV_RST = 1<<14, CSR_DREAD_RUN = 1<<13, CSR_DREAD_RST = 1<<12, CSR_DWRITE_RUN = 1<<11,
  CSR_DWRITE_RST = 1<<10, CSR_TRANS_RUN = 1<<9, CSR_TRANS_RST = 1<<8, CSR_ENA_POL = 1<<7,
  CSR_DIS_POL = 1<<6, CSR_STOP = 1<<5, CSR_START = 1<<4, CSR_IRQ_CL_P = 1<<3,
  CSR_IRQ_CL_B = 1<<2, CSR_IRQ_CL_F = 1<<1, CSR_IRQ_CL_C = 1<<0
}
 
enum  {
  F_ALM_FULL = 1<<27, F_EMPTY = 1<<27, F_FIFO_EOF = 1<<26, F_WM_REACHED = 1<<25,
  F_FIFO_LEVEL = 0x1fL<<16, F_WATER_MARK = 0x0007ffL
}
 
enum  {
  RB_ENA_STFWD = 1<<5, RB_DIS_STFWD = 1<<4, RB_ENA_OP_MD = 1<<3, RB_DIS_OP_MD = 1<<2,
  RB_RST_CLR = 1<<1, RB_RST_SET = 1<<0
}
 
enum  {
  TX_MFF_EA = 0x0d00, TX_MFF_WP = 0x0d04, TX_MFF_WSP = 0x0d08, TX_MFF_RP = 0x0d0c,
  TX_MFF_PC = 0x0d10, TX_MFF_LEV = 0x0d14, TX_MFF_CTRL1 = 0x0d18, TX_MFF_WAF = 0x0d1a,
  TX_MFF_CTRL2 = 0x0d1c, TX_MFF_TST1 = 0x0d1d, TX_MFF_TST2 = 0x0d1e, TX_LED_INI = 0x0d20,
  TX_LED_VAL = 0x0d24, TX_LED_CTRL = 0x0d28, TX_LED_TST = 0x0d29
}
 
enum  {
  TX_GMF_EA = 0x0d40, TX_GMF_AE_THR = 0x0d44, TX_GMF_CTRL_T = 0x0d48, TX_GMF_WP = 0x0d60,
  TX_GMF_WSP = 0x0d64, TX_GMF_WLEV = 0x0d68, TX_GMF_RP = 0x0d70, TX_GMF_RSTP = 0x0d74,
  TX_GMF_RLEV = 0x0d78, B28_DPT_INI = 0x0e00, B28_DPT_VAL = 0x0e04, B28_DPT_CTRL = 0x0e08,
  B28_DPT_TST = 0x0e0a, GMAC_TI_ST_VAL = 0x0e14, GMAC_TI_ST_CTRL = 0x0e18, GMAC_TI_ST_TST = 0x0e1a
}
 
enum  {
  LINKLED_OFF = 0x01, LINKLED_ON = 0x02, LINKLED_LINKSYNC_OFF = 0x04, LINKLED_LINKSYNC_ON = 0x08,
  LINKLED_BLINK_OFF = 0x10, LINKLED_BLINK_ON = 0x20
}
 
enum  {
  GMAC_CTRL = 0x0f00, GPHY_CTRL = 0x0f04, GMAC_IRQ_SRC = 0x0f08, GMAC_IRQ_MSK = 0x0f0c,
  GMAC_LINK_CTRL = 0x0f10, WOL_REG_OFFS = 0x20, WOL_CTRL_STAT = 0x0f20, WOL_MATCH_CTL = 0x0f22,
  WOL_MATCH_RES = 0x0f23, WOL_MAC_ADDR = 0x0f24, WOL_PATT_RPTR = 0x0f2c, WOL_PATT_LEN_LO = 0x0f30,
  WOL_PATT_LEN_HI = 0x0f34, WOL_PATT_CNT_0 = 0x0f38, WOL_PATT_CNT_4 = 0x0f3c
}
 
enum  { WOL_PATT_RAM_1 = 0x1000, WOL_PATT_RAM_2 = 0x1400 }
 
enum  { BASE_XMAC_1 = 0x2000, BASE_GMAC_1 = 0x2800, BASE_XMAC_2 = 0x3000, BASE_GMAC_2 = 0x3800 }
 
enum  {
  XMR_FS_LEN = 0x3fff<<18, XMR_FS_LEN_SHIFT = 18, XMR_FS_2L_VLAN = 1<<17, XMR_FS_1_VLAN = 1<<16,
  XMR_FS_BC = 1<<15, XMR_FS_MC = 1<<14, XMR_FS_UC = 1<<13, XMR_FS_BURST = 1<<11,
  XMR_FS_CEX_ERR = 1<<10, XMR_FS_802_3 = 1<<9, XMR_FS_COL_ERR = 1<<8, XMR_FS_CAR_ERR = 1<<7,
  XMR_FS_LEN_ERR = 1<<6, XMR_FS_FRA_ERR = 1<<5, XMR_FS_RUNT = 1<<4, XMR_FS_LNG_ERR = 1<<3,
  XMR_FS_FCS_ERR = 1<<2, XMR_FS_ERR = 1<<1, XMR_FS_MCTRL = 1<<0
}
 
enum  {
  PHY_XMAC_CTRL = 0x00, PHY_XMAC_STAT = 0x01, PHY_XMAC_ID0 = 0x02, PHY_XMAC_ID1 = 0x03,
  PHY_XMAC_AUNE_ADV = 0x04, PHY_XMAC_AUNE_LP = 0x05, PHY_XMAC_AUNE_EXP = 0x06, PHY_XMAC_NEPG = 0x07,
  PHY_XMAC_NEPG_LP = 0x08, PHY_XMAC_EXT_STAT = 0x0f, PHY_XMAC_RES_ABI = 0x10
}
 
enum  {
  PHY_BCOM_CTRL = 0x00, PHY_BCOM_STAT = 0x01, PHY_BCOM_ID0 = 0x02, PHY_BCOM_ID1 = 0x03,
  PHY_BCOM_AUNE_ADV = 0x04, PHY_BCOM_AUNE_LP = 0x05, PHY_BCOM_AUNE_EXP = 0x06, PHY_BCOM_NEPG = 0x07,
  PHY_BCOM_NEPG_LP = 0x08, PHY_BCOM_1000T_CTRL = 0x09, PHY_BCOM_1000T_STAT = 0x0a, PHY_BCOM_EXT_STAT = 0x0f,
  PHY_BCOM_P_EXT_CTRL = 0x10, PHY_BCOM_P_EXT_STAT = 0x11, PHY_BCOM_RE_CTR = 0x12, PHY_BCOM_FC_CTR = 0x13,
  PHY_BCOM_RNO_CTR = 0x14, PHY_BCOM_AUX_CTRL = 0x18, PHY_BCOM_AUX_STAT = 0x19, PHY_BCOM_INT_STAT = 0x1a,
  PHY_BCOM_INT_MASK = 0x1b
}
 
enum  {
  PHY_MARV_CTRL = 0x00, PHY_MARV_STAT = 0x01, PHY_MARV_ID0 = 0x02, PHY_MARV_ID1 = 0x03,
  PHY_MARV_AUNE_ADV = 0x04, PHY_MARV_AUNE_LP = 0x05, PHY_MARV_AUNE_EXP = 0x06, PHY_MARV_NEPG = 0x07,
  PHY_MARV_NEPG_LP = 0x08, PHY_MARV_1000T_CTRL = 0x09, PHY_MARV_1000T_STAT = 0x0a, PHY_MARV_EXT_STAT = 0x0f,
  PHY_MARV_PHY_CTRL = 0x10, PHY_MARV_PHY_STAT = 0x11, PHY_MARV_INT_MASK = 0x12, PHY_MARV_INT_STAT = 0x13,
  PHY_MARV_EXT_CTRL = 0x14, PHY_MARV_RXE_CNT = 0x15, PHY_MARV_EXT_ADR = 0x16, PHY_MARV_PORT_IRQ = 0x17,
  PHY_MARV_LED_CTRL = 0x18, PHY_MARV_LED_OVER = 0x19, PHY_MARV_EXT_CTRL_2 = 0x1a, PHY_MARV_EXT_P_STAT = 0x1b,
  PHY_MARV_CABLE_DIAG = 0x1c, PHY_MARV_PAGE_ADDR = 0x1d, PHY_MARV_PAGE_DATA = 0x1e, PHY_MARV_FE_LED_PAR = 0x16,
  PHY_MARV_FE_LED_SER = 0x17, PHY_MARV_FE_VCT_TX = 0x1a, PHY_MARV_FE_VCT_RX = 0x1b, PHY_MARV_FE_SPEC_2 = 0x1c
}
 
enum  {
  PHY_CT_RESET = 1<<15, PHY_CT_LOOP = 1<<14, PHY_CT_SPS_LSB = 1<<13, PHY_CT_ANE = 1<<12,
  PHY_CT_PDOWN = 1<<11, PHY_CT_ISOL = 1<<10, PHY_CT_RE_CFG = 1<<9, PHY_CT_DUP_MD = 1<<8,
  PHY_CT_COL_TST = 1<<7, PHY_CT_SPS_MSB = 1<<6
}
 
enum  { PHY_CT_SP1000 = PHY_CT_SPS_MSB, PHY_CT_SP100 = PHY_CT_SPS_LSB, PHY_CT_SP10 = 0 }
 
enum  {
  PHY_ST_EXT_ST = 1<<8, PHY_ST_PRE_SUP = 1<<6, PHY_ST_AN_OVER = 1<<5, PHY_ST_REM_FLT = 1<<4,
  PHY_ST_AN_CAP = 1<<3, PHY_ST_LSYNC = 1<<2, PHY_ST_JAB_DET = 1<<1, PHY_ST_EXT_REG = 1<<0
}
 
enum  { PHY_I1_OUI_MSK = 0x3f<<10, PHY_I1_MOD_NUM = 0x3f<<4, PHY_I1_REV_MSK = 0xf }
 
enum  { PHY_BCOM_ID1_A1 = 0x6041, PHY_BCOM_ID1_B2 = 0x6043, PHY_BCOM_ID1_C0 = 0x6044, PHY_BCOM_ID1_C5 = 0x6047 }
 
enum  {
  PHY_MARV_ID0_VAL = 0x0141, PHY_MARV_ID1_B0 = 0x0C23, PHY_MARV_ID1_B2 = 0x0C25, PHY_MARV_ID1_C2 = 0x0CC2,
  PHY_MARV_ID1_Y2 = 0x0C91
}
 
enum  {
  PHY_AN_NXT_PG = 1<<15, PHY_AN_ACK = 1<<14, PHY_AN_RF = 1<<13, PHY_AN_PAUSE_ASYM = 1<<11,
  PHY_AN_PAUSE_CAP = 1<<10, PHY_AN_100BASE4 = 1<<9, PHY_AN_100FULL = 1<<8, PHY_AN_100HALF = 1<<7,
  PHY_AN_10FULL = 1<<6, PHY_AN_10HALF = 1<<5, PHY_AN_CSMA = 1<<0, PHY_AN_SEL = 0x1f,
  PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, PHY_AN_ALL
}
 
enum  {
  PHY_X_AN_NXT_PG = 1<<15, PHY_X_AN_ACK = 1<<14, PHY_X_AN_RFB = 3<<12, PHY_X_AN_PAUSE = 3<<7,
  PHY_X_AN_HD = 1<<6, PHY_X_AN_FD = 1<<5
}
 
enum  { PHY_X_P_NO_PAUSE = 0<<7, PHY_X_P_SYM_MD = 1<<7, PHY_X_P_ASYM_MD = 2<<7, PHY_X_P_BOTH_MD = 3<<7 }
 
enum  { PHY_X_EX_FD = 1<<15, PHY_X_EX_HD = 1<<14 }
 
enum  {
  PHY_X_RS_PAUSE = 3<<7, PHY_X_RS_HD = 1<<6, PHY_X_RS_FD = 1<<5, PHY_X_RS_ABLMIS = 1<<4,
  PHY_X_RS_PAUMIS = 1<<3
}
 
enum  { X_RFB_OK = 0<<12, X_RFB_LF = 1<<12, X_RFB_OFF = 2<<12, X_RFB_AN_ERR = 3<<12 }
 
enum  {
  PHY_B_1000C_TEST = 7<<13, PHY_B_1000C_MSE = 1<<12, PHY_B_1000C_MSC = 1<<11, PHY_B_1000C_RD = 1<<10,
  PHY_B_1000C_AFD = 1<<9, PHY_B_1000C_AHD = 1<<8
}
 
enum  {
  PHY_B_1000S_MSF = 1<<15, PHY_B_1000S_MSR = 1<<14, PHY_B_1000S_LRS = 1<<13, PHY_B_1000S_RRS = 1<<12,
  PHY_B_1000S_LP_FD = 1<<11, PHY_B_1000S_LP_HD = 1<<10, PHY_B_1000S_IEC = 0xff
}
 
enum  { PHY_B_ES_X_FD_CAP = 1<<15, PHY_B_ES_X_HD_CAP = 1<<14, PHY_B_ES_T_FD_CAP = 1<<13, PHY_B_ES_T_HD_CAP = 1<<12 }
 
enum  {
  PHY_B_PEC_MAC_PHY = 1<<15, PHY_B_PEC_DIS_CROSS = 1<<14, PHY_B_PEC_TX_DIS = 1<<13, PHY_B_PEC_INT_DIS = 1<<12,
  PHY_B_PEC_F_INT = 1<<11, PHY_B_PEC_BY_45 = 1<<10, PHY_B_PEC_BY_SCR = 1<<9, PHY_B_PEC_BY_MLT3 = 1<<8,
  PHY_B_PEC_BY_RXA = 1<<7, PHY_B_PEC_RES_SCR = 1<<6, PHY_B_PEC_EN_LTR = 1<<5, PHY_B_PEC_LED_ON = 1<<4,
  PHY_B_PEC_LED_OFF = 1<<3, PHY_B_PEC_EX_IPG = 1<<2, PHY_B_PEC_3_LED = 1<<1, PHY_B_PEC_HIGH_LA = 1<<0
}
 
enum  {
  PHY_B_PES_CROSS_STAT = 1<<13, PHY_B_PES_INT_STAT = 1<<12, PHY_B_PES_RRS = 1<<11, PHY_B_PES_LRS = 1<<10,
  PHY_B_PES_LOCKED = 1<<9, PHY_B_PES_LS = 1<<8, PHY_B_PES_RF = 1<<7, PHY_B_PES_CE_ER = 1<<6,
  PHY_B_PES_BAD_SSD = 1<<5, PHY_B_PES_BAD_ESD = 1<<4, PHY_B_PES_RX_ER = 1<<3, PHY_B_PES_TX_ER = 1<<2,
  PHY_B_PES_LOCK_ER = 1<<1, PHY_B_PES_MLT3_ER = 1<<0
}
 
enum  { PHY_B_AN_RF = 1<<13, PHY_B_AN_ASP = 1<<11, PHY_B_AN_PC = 1<<10 }
 
enum  {
  PHY_B_FC_CTR = 0xff, PHY_B_RC_LOC_MSK = 0xff00, PHY_B_RC_REM_MSK = 0x00ff, PHY_B_AC_L_SQE = 1<<15,
  PHY_B_AC_LONG_PACK = 1<<14, PHY_B_AC_ER_CTRL = 3<<12, PHY_B_AC_TX_TST = 1<<10, PHY_B_AC_DIS_PRF = 1<<7,
  PHY_B_AC_DIS_PM = 1<<5, PHY_B_AC_DIAG = 1<<3
}
 
enum  {
  PHY_B_AS_AN_C = 1<<15, PHY_B_AS_AN_CA = 1<<14, PHY_B_AS_ANACK_D = 1<<13, PHY_B_AS_ANAB_D = 1<<12,
  PHY_B_AS_NPW = 1<<11, PHY_B_AS_AN_RES_MSK = 7<<8, PHY_B_AS_PDF = 1<<7, PHY_B_AS_RF = 1<<6,
  PHY_B_AS_ANP_R = 1<<5, PHY_B_AS_LP_ANAB = 1<<4, PHY_B_AS_LP_NPAB = 1<<3, PHY_B_AS_LS = 1<<2,
  PHY_B_AS_PRR = 1<<1, PHY_B_AS_PRT = 1<<0
}
 
enum  {
  PHY_B_IS_PSE = 1<<14, PHY_B_IS_MDXI_SC = 1<<13, PHY_B_IS_HCT = 1<<12, PHY_B_IS_LCT = 1<<11,
  PHY_B_IS_AN_PR = 1<<10, PHY_B_IS_NO_HDCL = 1<<9, PHY_B_IS_NO_HDC = 1<<8, PHY_B_IS_NEG_USHDC = 1<<7,
  PHY_B_IS_SCR_S_ER = 1<<6, PHY_B_IS_RRS_CHANGE = 1<<5, PHY_B_IS_LRS_CHANGE = 1<<4, PHY_B_IS_DUP_CHANGE = 1<<3,
  PHY_B_IS_LSP_CHANGE = 1<<2, PHY_B_IS_LST_CHANGE = 1<<1, PHY_B_IS_CRC_ER = 1<<0
}
 
enum  { PHY_B_P_NO_PAUSE = 0<<10, PHY_B_P_SYM_MD = 1<<10, PHY_B_P_ASYM_MD = 2<<10, PHY_B_P_BOTH_MD = 3<<10 }
 
enum  { PHY_B_RES_1000FD = 7<<8, PHY_B_RES_1000HD = 6<<8 }
 
enum  {
  PHY_M_AN_NXT_PG = 1<<15, PHY_M_AN_ACK = 1<<14, PHY_M_AN_RF = 1<<13, PHY_M_AN_ASP = 1<<11,
  PHY_M_AN_PC = 1<<10, PHY_M_AN_100_T4 = 1<<9, PHY_M_AN_100_FD = 1<<8, PHY_M_AN_100_HD = 1<<7,
  PHY_M_AN_10_FD = 1<<6, PHY_M_AN_10_HD = 1<<5, PHY_M_AN_SEL_MSK =0x1f<<4
}
 Marvell-Specific. More...
 
enum  { PHY_M_AN_ASP_X = 1<<8, PHY_M_AN_PC_X = 1<<7, PHY_M_AN_1000X_AHD = 1<<6, PHY_M_AN_1000X_AFD = 1<<5 }
 
enum  { PHY_M_P_NO_PAUSE_X = 0<<7, PHY_M_P_SYM_MD_X = 1<<7, PHY_M_P_ASYM_MD_X = 2<<7, PHY_M_P_BOTH_MD_X = 3<<7 }
 
enum  {
  PHY_M_1000C_TEST = 7<<13, PHY_M_1000C_MSE = 1<<12, PHY_M_1000C_MSC = 1<<11, PHY_M_1000C_MPD = 1<<10,
  PHY_M_1000C_AFD = 1<<9, PHY_M_1000C_AHD = 1<<8
}
 
enum  {
  PHY_M_PC_TX_FFD_MSK = 3<<14, PHY_M_PC_RX_FFD_MSK = 3<<12, PHY_M_PC_ASS_CRS_TX = 1<<11, PHY_M_PC_FL_GOOD = 1<<10,
  PHY_M_PC_EN_DET_MSK = 3<<8, PHY_M_PC_ENA_EXT_D = 1<<7, PHY_M_PC_MDIX_MSK = 3<<5, PHY_M_PC_DIS_125CLK = 1<<4,
  PHY_M_PC_MAC_POW_UP = 1<<3, PHY_M_PC_SQE_T_ENA = 1<<2, PHY_M_PC_POL_R_DIS = 1<<1, PHY_M_PC_DIS_JABBER = 1<<0
}
 
enum  { PHY_M_PC_EN_DET = 2<<8, PHY_M_PC_EN_DET_PLUS = 3<<8 }
 
enum  { PHY_M_PC_MAN_MDI = 0, PHY_M_PC_MAN_MDIX = 1, PHY_M_PC_ENA_AUTO = 3 }
 
enum  {
  PHY_M_PC_ENA_DTE_DT = 1<<15, PHY_M_PC_ENA_ENE_DT = 1<<14, PHY_M_PC_DIS_NLP_CK = 1<<13, PHY_M_PC_ENA_LIP_NP = 1<<12,
  PHY_M_PC_DIS_NLP_GN = 1<<11, PHY_M_PC_DIS_SCRAMB = 1<<9, PHY_M_PC_DIS_FEFI = 1<<8, PHY_M_PC_SH_TP_SEL = 1<<6,
  PHY_M_PC_RX_FD_MSK = 3<<2
}
 
enum  {
  PHY_M_PS_SPEED_MSK = 3<<14, PHY_M_PS_SPEED_1000 = 1<<15, PHY_M_PS_SPEED_100 = 1<<14, PHY_M_PS_SPEED_10 = 0,
  PHY_M_PS_FULL_DUP = 1<<13, PHY_M_PS_PAGE_REC = 1<<12, PHY_M_PS_SPDUP_RES = 1<<11, PHY_M_PS_LINK_UP = 1<<10,
  PHY_M_PS_CABLE_MSK = 7<<7, PHY_M_PS_MDI_X_STAT = 1<<6, PHY_M_PS_DOWNS_STAT = 1<<5, PHY_M_PS_ENDET_STAT = 1<<4,
  PHY_M_PS_TX_P_EN = 1<<3, PHY_M_PS_RX_P_EN = 1<<2, PHY_M_PS_POL_REV = 1<<1, PHY_M_PS_JABBER = 1<<0
}
 
enum  { PHY_M_PS_DTE_DETECT = 1<<15, PHY_M_PS_RES_SPEED = 1<<14 }
 
enum  {
  PHY_M_IS_AN_ERROR = 1<<15, PHY_M_IS_LSP_CHANGE = 1<<14, PHY_M_IS_DUP_CHANGE = 1<<13, PHY_M_IS_AN_PR = 1<<12,
  PHY_M_IS_AN_COMPL = 1<<11, PHY_M_IS_LST_CHANGE = 1<<10, PHY_M_IS_SYMB_ERROR = 1<<9, PHY_M_IS_FALSE_CARR = 1<<8,
  PHY_M_IS_FIFO_ERROR = 1<<7, PHY_M_IS_MDI_CHANGE = 1<<6, PHY_M_IS_DOWNSH_DET = 1<<5, PHY_M_IS_END_CHANGE = 1<<4,
  PHY_M_IS_DTE_CHANGE = 1<<2, PHY_M_IS_POL_CHANGE = 1<<1, PHY_M_IS_JABBER = 1<<0, PHY_M_IS_DEF_MSK,
  PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL
}
 
enum  {
  PHY_M_EC_ENA_BC_EXT = 1<<15, PHY_M_EC_ENA_LIN_LB = 1<<14, PHY_M_EC_DIS_LINK_P = 1<<12, PHY_M_EC_M_DSC_MSK = 3<<10,
  PHY_M_EC_S_DSC_MSK = 3<<8, PHY_M_EC_M_DSC_MSK2 = 7<<9, PHY_M_EC_DOWN_S_ENA = 1<<8, PHY_M_EC_RX_TIM_CT = 1<<7,
  PHY_M_EC_MAC_S_MSK = 7<<4, PHY_M_EC_FIB_AN_ENA = 1<<3, PHY_M_EC_DTE_D_ENA = 1<<2, PHY_M_EC_TX_TIM_CT = 1<<1,
  PHY_M_EC_TRANS_DIS = 1<<0
}
 
enum  { MAC_TX_CLK_0_MHZ = 2, MAC_TX_CLK_2_5_MHZ = 6, MAC_TX_CLK_25_MHZ = 7 }
 
enum  {
  PHY_M_LEDC_DIS_LED = 1<<15, PHY_M_LEDC_PULS_MSK = 7<<12, PHY_M_LEDC_F_INT = 1<<11, PHY_M_LEDC_BL_R_MSK = 7<<8,
  PHY_M_LEDC_DP_C_LSB = 1<<7, PHY_M_LEDC_TX_C_LSB = 1<<6, PHY_M_LEDC_LK_C_MSK = 7<<3
}
 
enum  {
  PHY_M_LEDC_LINK_MSK = 3<<3, PHY_M_LEDC_DP_CTRL = 1<<2, PHY_M_LEDC_DP_C_MSB = 1<<2, PHY_M_LEDC_RX_CTRL = 1<<1,
  PHY_M_LEDC_TX_CTRL = 1<<0, PHY_M_LEDC_TX_C_MSB = 1<<0
}
 
enum  {
  PULS_NO_STR = 0, PULS_21MS = 1, PULS_42MS = 2, PULS_84MS = 3,
  PULS_170MS = 4, PULS_340MS = 5, PULS_670MS = 6, PULS_1300MS = 7
}
 
enum  {
  BLINK_42MS = 0, BLINK_84MS = 1, BLINK_170MS = 2, BLINK_340MS = 3,
  BLINK_670MS = 4
}
 
enum  { MO_LED_NORM = 0, MO_LED_BLINK = 1, MO_LED_OFF = 2, MO_LED_ON = 3 }
 
enum  {
  PHY_M_EC2_FI_IMPED = 1<<6, PHY_M_EC2_FO_IMPED = 1<<5, PHY_M_EC2_FO_M_CLK = 1<<4, PHY_M_EC2_FO_BOOST = 1<<3,
  PHY_M_EC2_FO_AM_MSK = 7
}
 
enum  {
  PHY_M_FC_AUTO_SEL = 1<<15, PHY_M_FC_AN_REG_ACC = 1<<14, PHY_M_FC_RESOLUTION = 1<<13, PHY_M_SER_IF_AN_BP = 1<<12,
  PHY_M_SER_IF_BP_ST = 1<<11, PHY_M_IRQ_POLARITY = 1<<10, PHY_M_DIS_AUT_MED = 1<<9, PHY_M_UNDOC1 = 1<<7,
  PHY_M_DTE_POW_STAT = 1<<4, PHY_M_MODE_MASK = 0xf
}
 
enum  {
  PHY_M_CABD_ENA_TEST = 1<<15, PHY_M_CABD_DIS_WAIT = 1<<15, PHY_M_CABD_STAT_MSK = 3<<13, PHY_M_CABD_AMPL_MSK = 0x1f<<8,
  PHY_M_CABD_DIST_MSK = 0xff
}
 
enum  { CABD_STAT_NORMAL = 0, CABD_STAT_SHORT = 1, CABD_STAT_OPEN = 2, CABD_STAT_FAIL = 3 }
 
enum  { PHY_M_FELP_LED2_MSK = 0xf<<8, PHY_M_FELP_LED1_MSK = 0xf<<4, PHY_M_FELP_LED0_MSK = 0xf }
 
enum  {
  LED_PAR_CTRL_COLX = 0x00, LED_PAR_CTRL_ERROR = 0x01, LED_PAR_CTRL_DUPLEX = 0x02, LED_PAR_CTRL_DP_COL = 0x03,
  LED_PAR_CTRL_SPEED = 0x04, LED_PAR_CTRL_LINK = 0x05, LED_PAR_CTRL_TX = 0x06, LED_PAR_CTRL_RX = 0x07,
  LED_PAR_CTRL_ACT = 0x08, LED_PAR_CTRL_LNK_RX = 0x09, LED_PAR_CTRL_LNK_AC = 0x0a, LED_PAR_CTRL_ACT_BL = 0x0b,
  LED_PAR_CTRL_TX_BL = 0x0c, LED_PAR_CTRL_RX_BL = 0x0d, LED_PAR_CTRL_COL_BL = 0x0e, LED_PAR_CTRL_INACT = 0x0f
}
 
enum  { PHY_M_FESC_DIS_WAIT = 1<<2, PHY_M_FESC_ENA_MCLK = 1<<1, PHY_M_FESC_SEL_CL_A = 1<<0 }
 
enum  { PHY_M_LEDC_LOS_MSK = 0xf<<12, PHY_M_LEDC_INIT_MSK = 0xf<<8, PHY_M_LEDC_STA1_MSK = 0xf<<4, PHY_M_LEDC_STA0_MSK = 0xf }
 
enum  {
  GM_GP_STAT = 0x0000, GM_GP_CTRL = 0x0004, GM_TX_CTRL = 0x0008, GM_RX_CTRL = 0x000c,
  GM_TX_FLOW_CTRL = 0x0010, GM_TX_PARAM = 0x0014, GM_SERIAL_MODE = 0x0018, GM_SRC_ADDR_1L = 0x001c,
  GM_SRC_ADDR_1M = 0x0020, GM_SRC_ADDR_1H = 0x0024, GM_SRC_ADDR_2L = 0x0028, GM_SRC_ADDR_2M = 0x002c,
  GM_SRC_ADDR_2H = 0x0030, GM_MC_ADDR_H1 = 0x0034, GM_MC_ADDR_H2 = 0x0038, GM_MC_ADDR_H3 = 0x003c,
  GM_MC_ADDR_H4 = 0x0040, GM_TX_IRQ_SRC = 0x0044, GM_RX_IRQ_SRC = 0x0048, GM_TR_IRQ_SRC = 0x004c,
  GM_TX_IRQ_MSK = 0x0050, GM_RX_IRQ_MSK = 0x0054, GM_TR_IRQ_MSK = 0x0058, GM_SMI_CTRL = 0x0080,
  GM_SMI_DATA = 0x0084, GM_PHY_ADDR = 0x0088
}
 
enum  {
  GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24,
  GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64,
  GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, GM_RXF_SHT = GM_MIB_CNT_BASE + 80, GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, GM_RXF_64B = GM_MIB_CNT_BASE + 96,
  GM_RXF_127B = GM_MIB_CNT_BASE + 104, GM_RXF_255B = GM_MIB_CNT_BASE + 112, GM_RXF_511B = GM_MIB_CNT_BASE + 120, GM_RXF_1023B = GM_MIB_CNT_BASE + 128,
  GM_RXF_1518B = GM_MIB_CNT_BASE + 136, GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,
  GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,
  GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, GM_TXF_64B = GM_MIB_CNT_BASE + 240,
  GM_TXF_127B = GM_MIB_CNT_BASE + 248, GM_TXF_255B = GM_MIB_CNT_BASE + 256, GM_TXF_511B = GM_MIB_CNT_BASE + 264, GM_TXF_1023B = GM_MIB_CNT_BASE + 272,
  GM_TXF_1518B = GM_MIB_CNT_BASE + 280, GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, GM_TXF_COL = GM_MIB_CNT_BASE + 304, GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,
  GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344
}
 
enum  {
  GM_GPSR_SPEED = 1<<15, GM_GPSR_DUPLEX = 1<<14, GM_GPSR_FC_TX_DIS = 1<<13, GM_GPSR_LINK_UP = 1<<12,
  GM_GPSR_PAUSE = 1<<11, GM_GPSR_TX_ACTIVE = 1<<10, GM_GPSR_EXC_COL = 1<<9, GM_GPSR_LAT_COL = 1<<8,
  GM_GPSR_PHY_ST_CH = 1<<5, GM_GPSR_GIG_SPEED = 1<<4, GM_GPSR_PART_MODE = 1<<3, GM_GPSR_FC_RX_DIS = 1<<2,
  GM_GPSR_PROM_EN = 1<<1
}
 
enum  {
  GM_GPCR_PROM_ENA = 1<<14, GM_GPCR_FC_TX_DIS = 1<<13, GM_GPCR_TX_ENA = 1<<12, GM_GPCR_RX_ENA = 1<<11,
  GM_GPCR_BURST_ENA = 1<<10, GM_GPCR_LOOP_ENA = 1<<9, GM_GPCR_PART_ENA = 1<<8, GM_GPCR_GIGS_ENA = 1<<7,
  GM_GPCR_FL_PASS = 1<<6, GM_GPCR_DUP_FULL = 1<<5, GM_GPCR_FC_RX_DIS = 1<<4, GM_GPCR_SPEED_100 = 1<<3,
  GM_GPCR_AU_DUP_DIS = 1<<2, GM_GPCR_AU_FCT_DIS = 1<<1, GM_GPCR_AU_SPD_DIS = 1<<0
}
 
enum  { GM_TXCR_FORCE_JAM = 1<<15, GM_TXCR_CRC_DIS = 1<<14, GM_TXCR_PAD_DIS = 1<<13, GM_TXCR_COL_THR_MSK = 7<<10 }
 
enum  { GM_RXCR_UCF_ENA = 1<<15, GM_RXCR_MCF_ENA = 1<<14, GM_RXCR_CRC_DIS = 1<<13, GM_RXCR_PASS_FC = 1<<12 }
 
enum  {
  GM_TXPA_JAMLEN_MSK = 0x03<<14, GM_TXPA_JAMIPG_MSK = 0x1f<<9, GM_TXPA_JAMDAT_MSK = 0x1f<<4, TX_JAM_LEN_DEF = 0x03,
  TX_JAM_IPG_DEF = 0x0b, TX_IPG_JAM_DEF = 0x1c
}
 
enum  {
  GM_SMOD_DATABL_MSK = 0x1f<<11, GM_SMOD_LIMIT_4 = 1<<10, GM_SMOD_VLAN_ENA = 1<<9, GM_SMOD_JUMBO_ENA = 1<<8,
  GM_SMOD_IPG_MSK = 0x1f
}
 
enum  {
  GM_SMI_CT_PHY_A_MSK = 0x1f<<11, GM_SMI_CT_REG_A_MSK = 0x1f<<6, GM_SMI_CT_OP_RD = 1<<5, GM_SMI_CT_RD_VAL = 1<<4,
  GM_SMI_CT_BUSY = 1<<3
}
 
enum  { GM_PAR_MIB_CLR = 1<<5, GM_PAR_MIB_TST = 1<<4 }
 
enum  {
  GMR_FS_LEN = 0xffff<<16, GMR_FS_LEN_SHIFT = 16, GMR_FS_VLAN = 1<<13, GMR_FS_JABBER = 1<<12,
  GMR_FS_UN_SIZE = 1<<11, GMR_FS_MC = 1<<10, GMR_FS_BC = 1<<9, GMR_FS_RX_OK = 1<<8,
  GMR_FS_GOOD_FC = 1<<7, GMR_FS_BAD_FC = 1<<6, GMR_FS_MII_ERR = 1<<5, GMR_FS_LONG_ERR = 1<<4,
  GMR_FS_FRAGMENT = 1<<3, GMR_FS_CRC_ERR = 1<<1, GMR_FS_RX_FF_OV = 1<<0, GMR_FS_ANY_ERR,
  RX_FF_FL_DEF_MSK
}
 
enum  {
  GMF_WP_TST_ON = 1<<14, GMF_WP_TST_OFF = 1<<13, GMF_WP_STEP = 1<<12, GMF_RP_TST_ON = 1<<10,
  GMF_RP_TST_OFF = 1<<9, GMF_RP_STEP = 1<<8, GMF_RX_F_FL_ON = 1<<7, GMF_RX_F_FL_OFF = 1<<6,
  GMF_CLI_RX_FO = 1<<5, GMF_CLI_RX_FC = 1<<4, GMF_OPER_ON = 1<<3, GMF_OPER_OFF = 1<<2,
  GMF_RST_CLR = 1<<1, GMF_RST_SET = 1<<0, RX_GMF_FL_THR_DEF = 0xa
}
 
enum  {
  GMF_WSP_TST_ON = 1<<18, GMF_WSP_TST_OFF = 1<<17, GMF_WSP_STEP = 1<<16, GMF_CLI_TX_FU = 1<<6,
  GMF_CLI_TX_FC = 1<<5, GMF_CLI_TX_PE = 1<<4
}
 
enum  { GMT_ST_START = 1<<2, GMT_ST_STOP = 1<<1, GMT_ST_CLR_IRQ = 1<<0 }
 
enum  {
  GMC_H_BURST_ON = 1<<7, GMC_H_BURST_OFF = 1<<6, GMC_F_LOOPB_ON = 1<<5, GMC_F_LOOPB_OFF = 1<<4,
  GMC_PAUSE_ON = 1<<3, GMC_PAUSE_OFF = 1<<2, GMC_RST_CLR = 1<<1, GMC_RST_SET = 1<<0
}
 
enum  {
  GPC_SEL_BDT = 1<<28, GPC_INT_POL_HI = 1<<27, GPC_75_OHM = 1<<26, GPC_DIS_FC = 1<<25,
  GPC_DIS_SLEEP = 1<<24, GPC_HWCFG_M_3 = 1<<23, GPC_HWCFG_M_2 = 1<<22, GPC_HWCFG_M_1 = 1<<21,
  GPC_HWCFG_M_0 = 1<<20, GPC_ANEG_0 = 1<<19, GPC_ENA_XC = 1<<18, GPC_DIS_125 = 1<<17,
  GPC_ANEG_3 = 1<<16, GPC_ANEG_2 = 1<<15, GPC_ANEG_1 = 1<<14, GPC_ENA_PAUSE = 1<<13,
  GPC_PHYADDR_4 = 1<<12, GPC_PHYADDR_3 = 1<<11, GPC_PHYADDR_2 = 1<<10, GPC_PHYADDR_1 = 1<<9,
  GPC_PHYADDR_0 = 1<<8, GPC_RST_CLR = 1<<1, GPC_RST_SET = 1<<0
}
 
enum  {
  GM_IS_TX_CO_OV = 1<<5, GM_IS_RX_CO_OV = 1<<4, GM_IS_TX_FF_UR = 1<<3, GM_IS_TX_COMPL = 1<<2,
  GM_IS_RX_FF_OR = 1<<1, GM_IS_RX_COMPL = 1<<0, GMLC_RST_CLR = 1<<1, GMLC_RST_SET = 1<<0,
  WOL_CTL_LINK_CHG_OCC = 1<<15, WOL_CTL_MAGIC_PKT_OCC = 1<<14, WOL_CTL_PATTERN_OCC = 1<<13, WOL_CTL_CLEAR_RESULT = 1<<12,
  WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
  WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
  WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, WOL_CTL_ENA_PATTERN_UNIT = 1<<1, WOL_CTL_DIS_PATTERN_UNIT = 1<<0
}
 
enum  {
  XM_MMU_CMD = 0x0000, XM_POFF = 0x0008, XM_BURST = 0x000c, XM_1L_VLAN_TAG = 0x0010,
  XM_2L_VLAN_TAG = 0x0014, XM_TX_CMD = 0x0020, XM_TX_RT_LIM = 0x0024, XM_TX_STIME = 0x0028,
  XM_TX_IPG = 0x002c, XM_RX_CMD = 0x0030, XM_PHY_ADDR = 0x0034, XM_PHY_DATA = 0x0038,
  XM_GP_PORT = 0x0040, XM_IMSK = 0x0044, XM_ISRC = 0x0048, XM_HW_CFG = 0x004c,
  XM_TX_LO_WM = 0x0060, XM_TX_HI_WM = 0x0062, XM_TX_THR = 0x0064, XM_HT_THR = 0x0066,
  XM_PAUSE_DA = 0x0068, XM_CTL_PARA = 0x0070, XM_MAC_OPCODE = 0x0074, XM_MAC_PTIME = 0x0076,
  XM_TX_STAT = 0x0078, XM_EXM_START = 0x0080
}
 
enum  {
  XM_SRC_CHK = 0x0100, XM_SA = 0x0108, XM_HSM = 0x0110, XM_RX_LO_WM = 0x0118,
  XM_RX_HI_WM = 0x011a, XM_RX_THR = 0x011c, XM_DEV_ID = 0x0120, XM_MODE = 0x0124,
  XM_LSA = 0x0128, XM_TS_READ = 0x0130, XM_TS_LOAD = 0x0134, XM_STAT_CMD = 0x0200,
  XM_RX_CNT_EV = 0x0204, XM_TX_CNT_EV = 0x0208, XM_RX_EV_MSK = 0x020c, XM_TX_EV_MSK = 0x0210,
  XM_TXF_OK = 0x0280, XM_TXO_OK_HI = 0x0284, XM_TXO_OK_LO = 0x0288, XM_TXF_BC_OK = 0x028c,
  XM_TXF_MC_OK = 0x0290, XM_TXF_UC_OK = 0x0294, XM_TXF_LONG = 0x0298, XM_TXE_BURST = 0x029c,
  XM_TXF_MPAUSE = 0x02a0, XM_TXF_MCTRL = 0x02a4, XM_TXF_SNG_COL = 0x02a8, XM_TXF_MUL_COL = 0x02ac,
  XM_TXF_ABO_COL = 0x02b0, XM_TXF_LAT_COL = 0x02b4, XM_TXF_DEF = 0x02b8, XM_TXF_EX_DEF = 0x02bc,
  XM_TXE_FIFO_UR = 0x02c0, XM_TXE_CS_ERR = 0x02c4, XM_TXP_UTIL = 0x02c8, XM_TXF_64B = 0x02d0,
  XM_TXF_127B = 0x02d4, XM_TXF_255B = 0x02d8, XM_TXF_511B = 0x02dc, XM_TXF_1023B = 0x02e0,
  XM_TXF_MAX_SZ = 0x02e4, XM_RXF_OK = 0x0300, XM_RXO_OK_HI = 0x0304, XM_RXO_OK_LO = 0x0308,
  XM_RXF_BC_OK = 0x030c, XM_RXF_MC_OK = 0x0310, XM_RXF_UC_OK = 0x0314, XM_RXF_MPAUSE = 0x0318,
  XM_RXF_MCTRL = 0x031c, XM_RXF_INV_MP = 0x0320, XM_RXF_INV_MOC = 0x0324, XM_RXE_BURST = 0x0328,
  XM_RXE_FMISS = 0x032c, XM_RXF_FRA_ERR = 0x0330, XM_RXE_FIFO_OV = 0x0334, XM_RXF_JAB_PKT = 0x0338,
  XM_RXE_CAR_ERR = 0x033c, XM_RXF_LEN_ERR = 0x0340, XM_RXE_SYM_ERR = 0x0344, XM_RXE_SHT_ERR = 0x0348,
  XM_RXE_RUNT = 0x034c, XM_RXF_LNG_ERR = 0x0350, XM_RXF_FCS_ERR = 0x0354, XM_RXF_CEX_ERR = 0x035c,
  XM_RXP_UTIL = 0x0360, XM_RXF_64B = 0x0368, XM_RXF_127B = 0x036c, XM_RXF_255B = 0x0370,
  XM_RXF_511B = 0x0374, XM_RXF_1023B = 0x0378, XM_RXF_MAX_SZ = 0x037c
}
 
enum  {
  XM_MMU_PHY_RDY = 1<<12, XM_MMU_PHY_BUSY = 1<<11, XM_MMU_IGN_PF = 1<<10, XM_MMU_MAC_LB = 1<<9,
  XM_MMU_FRC_COL = 1<<7, XM_MMU_SIM_COL = 1<<6, XM_MMU_NO_PRE = 1<<5, XM_MMU_GMII_FD = 1<<4,
  XM_MMU_RAT_CTRL = 1<<3, XM_MMU_GMII_LOOP = 1<<2, XM_MMU_ENA_RX = 1<<1, XM_MMU_ENA_TX = 1<<0
}
 
enum  {
  XM_TX_BK2BK = 1<<6, XM_TX_ENC_BYP = 1<<5, XM_TX_SAM_LINE = 1<<4, XM_TX_NO_GIG_MD = 1<<3,
  XM_TX_NO_PRE = 1<<2, XM_TX_NO_CRC = 1<<1, XM_TX_AUTO_PAD = 1<<0
}
 
enum  {
  XM_RX_LENERR_OK = 1<<8, XM_RX_BIG_PK_OK = 1<<7, XM_RX_IPG_CAP = 1<<6, XM_RX_TP_MD = 1<<5,
  XM_RX_STRIP_FCS = 1<<4, XM_RX_SELF_RX = 1<<3, XM_RX_SAM_LINE = 1<<2, XM_RX_STRIP_PAD = 1<<1,
  XM_RX_DIS_CEXT = 1<<0
}
 
enum  {
  XM_GP_ANIP = 1<<6, XM_GP_FRC_INT = 1<<5, XM_GP_RES_MAC = 1<<3, XM_GP_RES_STAT = 1<<2,
  XM_GP_INP_ASS = 1<<0
}
 
enum  {
  XM_IS_LNK_AE = 1<<14, XM_IS_TX_ABORT = 1<<13, XM_IS_FRC_INT = 1<<12, XM_IS_INP_ASS = 1<<11,
  XM_IS_LIPA_RC = 1<<10, XM_IS_RX_PAGE = 1<<9, XM_IS_TX_PAGE = 1<<8, XM_IS_AND = 1<<7,
  XM_IS_TSC_OV = 1<<6, XM_IS_RXC_OV = 1<<5, XM_IS_TXC_OV = 1<<4, XM_IS_RXF_OV = 1<<3,
  XM_IS_TXF_UR = 1<<2, XM_IS_TX_COMP = 1<<1, XM_IS_RX_COMP = 1<<0, XM_IMSK_DISABLE = 0xffff
}
 
enum  { XM_HW_GEN_EOP = 1<<3, XM_HW_COM4SIG = 1<<2, XM_HW_GMII_MD = 1<<0 }
 
enum  {
  XM_ST_VALID = (1UL<<31), XM_ST_BYTE_CNT = (0x3fffL<<17), XM_ST_RETRY_CNT = (0x1fL<<12), XM_ST_EX_COL = 1<<11,
  XM_ST_EX_DEF = 1<<10, XM_ST_BURST = 1<<9, XM_ST_DEFER = 1<<8, XM_ST_BC = 1<<7,
  XM_ST_MC = 1<<6, XM_ST_UC = 1<<5, XM_ST_TX_UR = 1<<4, XM_ST_CS_ERR = 1<<3,
  XM_ST_LAT_COL = 1<<2, XM_ST_MUL_COL = 1<<1, XM_ST_SGN_COL = 1<<0
}
 
enum  {
  XM_MD_ENA_REJ = 1<<26, XM_MD_SPOE_E = 1<<25, XM_MD_TX_REP = 1<<24, XM_MD_SPOFF_I = 1<<23,
  XM_MD_LE_STW = 1<<22, XM_MD_TX_CONT = 1<<21, XM_MD_TX_PAUSE = 1<<20, XM_MD_ATS = 1<<19,
  XM_MD_SPOL_I = 1<<18, XM_MD_SPOH_I = 1<<17, XM_MD_CAP = 1<<16, XM_MD_ENA_HASH = 1<<15,
  XM_MD_CSA = 1<<14, XM_MD_CAA = 1<<13, XM_MD_RX_MCTRL = 1<<12, XM_MD_RX_RUNT = 1<<11,
  XM_MD_RX_IRLE = 1<<10, XM_MD_RX_LONG = 1<<9, XM_MD_RX_CRCE = 1<<8, XM_MD_RX_ERR = 1<<7,
  XM_MD_DIS_UC = 1<<6, XM_MD_DIS_MC = 1<<5, XM_MD_DIS_BC = 1<<4, XM_MD_ENA_PROM = 1<<3,
  XM_MD_ENA_BE = 1<<2, XM_MD_FTF = 1<<1, XM_MD_FRF = 1<<0
}
 
enum  {
  XM_SC_SNP_RXC = 1<<5, XM_SC_SNP_TXC = 1<<4, XM_SC_CP_RXC = 1<<3, XM_SC_CP_TXC = 1<<2,
  XM_SC_CLR_RXC = 1<<1, XM_SC_CLR_TXC = 1<<0
}
 
enum  {
  XMR_MAX_SZ_OV = 1<<31, XMR_1023B_OV = 1<<30, XMR_511B_OV = 1<<29, XMR_255B_OV = 1<<28,
  XMR_127B_OV = 1<<27, XMR_64B_OV = 1<<26, XMR_UTIL_OV = 1<<25, XMR_UTIL_UR = 1<<24,
  XMR_CEX_ERR_OV = 1<<23, XMR_FCS_ERR_OV = 1<<21, XMR_LNG_ERR_OV = 1<<20, XMR_RUNT_OV = 1<<19,
  XMR_SHT_ERR_OV = 1<<18, XMR_SYM_ERR_OV = 1<<17, XMR_CAR_ERR_OV = 1<<15, XMR_JAB_PKT_OV = 1<<14,
  XMR_FIFO_OV = 1<<13, XMR_FRA_ERR_OV = 1<<12, XMR_FMISS_OV = 1<<11, XMR_BURST = 1<<10,
  XMR_INV_MOC = 1<<9, XMR_INV_MP = 1<<8, XMR_MCTRL_OV = 1<<7, XMR_MPAUSE_OV = 1<<6,
  XMR_UC_OK_OV = 1<<5, XMR_MC_OK_OV = 1<<4, XMR_BC_OK_OV = 1<<3, XMR_OK_LO_OV = 1<<2,
  XMR_OK_HI_OV = 1<<1, XMR_OK_OV = 1<<0
}
 
enum  {
  XMT_MAX_SZ_OV = 1<<25, XMT_1023B_OV = 1<<24, XMT_511B_OV = 1<<23, XMT_255B_OV = 1<<22,
  XMT_127B_OV = 1<<21, XMT_64B_OV = 1<<20, XMT_UTIL_OV = 1<<19, XMT_UTIL_UR = 1<<18,
  XMT_CS_ERR_OV = 1<<17, XMT_FIFO_UR_OV = 1<<16, XMT_EX_DEF_OV = 1<<15, XMT_DEF = 1<<14,
  XMT_LAT_COL_OV = 1<<13, XMT_ABO_COL_OV = 1<<12, XMT_MUL_COL_OV = 1<<11, XMT_SNG_COL = 1<<10,
  XMT_MCTRL_OV = 1<<9, XMT_MPAUSE = 1<<8, XMT_BURST = 1<<7, XMT_LONG = 1<<6,
  XMT_UC_OK_OV = 1<<5, XMT_MC_OK_OV = 1<<4, XMT_BC_OK_OV = 1<<3, XMT_OK_LO_OV = 1<<2,
  XMT_OK_HI_OV = 1<<1, XMT_OK_OV = 1<<0
}
 
enum  pause_control { FLOW_MODE_NONE = 1, FLOW_MODE_LOC_SEND = 2, FLOW_MODE_SYMMETRIC = 3, FLOW_MODE_SYM_OR_REM = 4 }
 
enum  pause_status {
  FLOW_STAT_INDETERMINATED =0, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_LOC_SEND,
  FLOW_STAT_SYMMETRIC
}
 

Functions

 FILE_LICENCE (GPL2_ONLY)
 
static u32 skge_read32 (const struct skge_hw *hw, int reg)
 
static u16 skge_read16 (const struct skge_hw *hw, int reg)
 
static u8 skge_read8 (const struct skge_hw *hw, int reg)
 
static void skge_write32 (const struct skge_hw *hw, int reg, u32 val)
 
static void skge_write16 (const struct skge_hw *hw, int reg, u16 val)
 
static void skge_write8 (const struct skge_hw *hw, int reg, u8 val)
 
static u32 xm_read32 (const struct skge_hw *hw, int port, int reg)
 
static u16 xm_read16 (const struct skge_hw *hw, int port, int reg)
 
static void xm_write32 (const struct skge_hw *hw, int port, int r, u32 v)
 
static void xm_write16 (const struct skge_hw *hw, int port, int r, u16 v)
 
static void xm_outhash (const struct skge_hw *hw, int port, int reg, const u8 *hash)
 
static void xm_outaddr (const struct skge_hw *hw, int port, int reg, const u8 *addr)
 
static u16 gma_read16 (const struct skge_hw *hw, int port, int reg)
 
static u32 gma_read32 (const struct skge_hw *hw, int port, int reg)
 
static void gma_write16 (const struct skge_hw *hw, int port, int r, u16 v)
 
static void gma_set_addr (struct skge_hw *hw, int port, int reg, const u8 *addr)
 

Macro Definition Documentation

◆ PCI_DEV_REG1

#define PCI_DEV_REG1   0x40

Definition at line 10 of file skge.h.

◆ PCI_PHY_COMA

#define PCI_PHY_COMA   0x8000000

Definition at line 11 of file skge.h.

◆ PCI_VIO

#define PCI_VIO   0x2000000

Definition at line 12 of file skge.h.

◆ PCI_DEV_REG2

#define PCI_DEV_REG2   0x44

Definition at line 14 of file skge.h.

◆ PCI_VPD_ROM_SZ

#define PCI_VPD_ROM_SZ   7L<<14 /* VPD ROM size 0=256, 1=512, ... */

Definition at line 15 of file skge.h.

◆ PCI_REV_DESC

#define PCI_REV_DESC   1<<2 /* Reverse Descriptor bytes */

Definition at line 16 of file skge.h.

◆ DRV_NAME

#define DRV_NAME   "skge"

Definition at line 18 of file skge.h.

◆ DRV_VERSION

#define DRV_VERSION   "1.13"

Definition at line 19 of file skge.h.

◆ PFX

#define PFX   DRV_NAME " "

Definition at line 20 of file skge.h.

◆ NUM_TX_DESC

#define NUM_TX_DESC   8

Definition at line 22 of file skge.h.

◆ NUM_RX_DESC

#define NUM_RX_DESC   8

Definition at line 23 of file skge.h.

◆ SKGE_RING_ALIGN

#define SKGE_RING_ALIGN   8

Definition at line 26 of file skge.h.

◆ RX_BUF_SIZE

#define RX_BUF_SIZE   1536

Definition at line 27 of file skge.h.

◆ PHY_RETRIES

#define PHY_RETRIES   1000

Definition at line 28 of file skge.h.

◆ TX_RING_SIZE

#define TX_RING_SIZE   ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) )

Definition at line 30 of file skge.h.

◆ RX_RING_SIZE

#define RX_RING_SIZE   ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) )

Definition at line 31 of file skge.h.

◆ RING_SIZE

#define RING_SIZE   ( TX_RING_SIZE + RX_RING_SIZE )

Definition at line 32 of file skge.h.

◆ SKGE_REG_SIZE

#define SKGE_REG_SIZE   0x4000

Definition at line 34 of file skge.h.

◆ SKGE_EEPROM_MAGIC

#define SKGE_EEPROM_MAGIC   0x9933aabb

Definition at line 36 of file skge.h.

◆ AUTONEG_DISABLE

#define AUTONEG_DISABLE   0x00

Definition at line 41 of file skge.h.

◆ AUTONEG_ENABLE

#define AUTONEG_ENABLE   0x01

Definition at line 42 of file skge.h.

◆ DUPLEX_HALF

#define DUPLEX_HALF   0x00

Definition at line 44 of file skge.h.

◆ DUPLEX_FULL

#define DUPLEX_FULL   0x01

Definition at line 45 of file skge.h.

◆ SPEED_10

#define SPEED_10   10

Definition at line 47 of file skge.h.

◆ SPEED_100

#define SPEED_100   100

Definition at line 48 of file skge.h.

◆ SPEED_1000

#define SPEED_1000   1000

Definition at line 49 of file skge.h.

◆ ADVERTISED_10baseT_Half

#define ADVERTISED_10baseT_Half   (1 << 0)

Definition at line 51 of file skge.h.

◆ ADVERTISED_10baseT_Full

#define ADVERTISED_10baseT_Full   (1 << 1)

Definition at line 52 of file skge.h.

◆ ADVERTISED_100baseT_Half

#define ADVERTISED_100baseT_Half   (1 << 2)

Definition at line 53 of file skge.h.

◆ ADVERTISED_100baseT_Full

#define ADVERTISED_100baseT_Full   (1 << 3)

Definition at line 54 of file skge.h.

◆ ADVERTISED_1000baseT_Half

#define ADVERTISED_1000baseT_Half   (1 << 4)

Definition at line 55 of file skge.h.

◆ ADVERTISED_1000baseT_Full

#define ADVERTISED_1000baseT_Full   (1 << 5)

Definition at line 56 of file skge.h.

◆ SUPPORTED_10baseT_Half

#define SUPPORTED_10baseT_Half   (1 << 0)

Definition at line 58 of file skge.h.

◆ SUPPORTED_10baseT_Full

#define SUPPORTED_10baseT_Full   (1 << 1)

Definition at line 59 of file skge.h.

◆ SUPPORTED_100baseT_Half

#define SUPPORTED_100baseT_Half   (1 << 2)

Definition at line 60 of file skge.h.

◆ SUPPORTED_100baseT_Full

#define SUPPORTED_100baseT_Full   (1 << 3)

Definition at line 61 of file skge.h.

◆ SUPPORTED_1000baseT_Half

#define SUPPORTED_1000baseT_Half   (1 << 4)

Definition at line 62 of file skge.h.

◆ SUPPORTED_1000baseT_Full

#define SUPPORTED_1000baseT_Full   (1 << 5)

Definition at line 63 of file skge.h.

◆ SUPPORTED_Autoneg

#define SUPPORTED_Autoneg   (1 << 6)

Definition at line 64 of file skge.h.

◆ SUPPORTED_TP

#define SUPPORTED_TP   (1 << 7)

Definition at line 65 of file skge.h.

◆ SUPPORTED_FIBRE

#define SUPPORTED_FIBRE   (1 << 10)

Definition at line 66 of file skge.h.

◆ PCI_STATUS_ERROR_BITS

#define PCI_STATUS_ERROR_BITS
Value:
(PCI_STATUS_DETECTED_PARITY | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_PARITY)
PCI_STATUS_DETECTED_PARITY
#define PCI_STATUS_DETECTED_PARITY
Detected parity error.
Definition: pci.h:41

Definition at line 70 of file skge.h.

◆ RAM_ADR_RAN

#define RAM_ADR_RAN   0x0007ffffL /* Bit 18.. 0: RAM Address Range */

Definition at line 416 of file skge.h.

◆ SK_MAC_TO_53

#define SK_MAC_TO_53   72 /* MAC arbiter timeout */

Definition at line 439 of file skge.h.

◆ SK_PKT_TO_53

#define SK_PKT_TO_53   0x2000 /* Packet arbiter timeout */

Definition at line 440 of file skge.h.

◆ SK_PKT_TO_MAX

#define SK_PKT_TO_MAX   0xffff /* Maximum value */

Definition at line 441 of file skge.h.

◆ SK_RI_TO_53

#define SK_RI_TO_53   36 /* RAM interface timeout */

Definition at line 442 of file skge.h.

◆ PA_ENA_TO_ALL

#define PA_ENA_TO_ALL
Value:
(PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
PA_ENA_TO_TX1 | PA_ENA_TO_TX2)

Definition at line 463 of file skge.h.

◆ TXA_MAX_VAL

#define TXA_MAX_VAL   0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */

Definition at line 473 of file skge.h.

◆ Q_ADDR

#define Q_ADDR (   reg,
  offs 
)    (B8_Q_REGS + (reg) + (offs))

Definition at line 534 of file skge.h.

◆ RB_ADDR

#define RB_ADDR (   offs,
  queue 
)    ((u16)B16_RAM_REGS + (u16)(queue) + (offs))

Definition at line 590 of file skge.h.

◆ CSR_SET_RESET

#define CSR_SET_RESET
Value:
(CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
CSR_TRANS_RST)

Definition at line 790 of file skge.h.

◆ CSR_CLR_RESET

#define CSR_CLR_RESET
Value:
(CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
CSR_TRANS_RUN)

Definition at line 793 of file skge.h.

◆ RB_MSK

#define RB_MSK   0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */

Definition at line 820 of file skge.h.

◆ SK_XMIT_DUR

#define SK_XMIT_DUR   0x002faf08UL /* 50 ms */

Definition at line 856 of file skge.h.

◆ SK_BLK_DUR

#define SK_BLK_DUR   0x01dcd650UL /* 500 ms */

Definition at line 857 of file skge.h.

◆ SK_DPOLL_DEF

#define SK_DPOLL_DEF   0x00ee6b28UL /* 250 ms at 62.5 MHz */

Definition at line 859 of file skge.h.

◆ SK_DPOLL_MAX

#define SK_DPOLL_MAX   0x00ffffffUL /* 268 ms at 62.5 MHz */

Definition at line 861 of file skge.h.

◆ SK_FACT_62

#define SK_FACT_62   100 /* is given in percent */

Definition at line 864 of file skge.h.

◆ SK_FACT_53

#define SK_FACT_53   85 /* on GENESIS: 53.12 MHz */

Definition at line 865 of file skge.h.

◆ SK_FACT_78

#define SK_FACT_78   125 /* on YUKON: 78.12 MHz */

Definition at line 866 of file skge.h.

◆ WOL_REGS

#define WOL_REGS (   port,
  x 
)    (x + (port)*0x80)

Definition at line 934 of file skge.h.

◆ WOL_PATT_RAM_BASE

#define WOL_PATT_RAM_BASE (   port)    (WOL_PATT_RAM_1 + (port)*0x400)

Definition at line 940 of file skge.h.

◆ PHY_B_AS_PAUSE_MSK

#define PHY_B_AS_PAUSE_MSK   (PHY_B_AS_PRR | PHY_B_AS_PRT)

Definition at line 1307 of file skge.h.

◆ PHY_B_DEF_MSK

#define PHY_B_DEF_MSK
Value:
(~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))

Definition at line 1328 of file skge.h.

◆ PHY_M_PS_PAUSE_MSK

#define PHY_M_PS_PAUSE_MSK   (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)

Definition at line 1451 of file skge.h.

◆ PHY_M_EC_M_DSC

#define PHY_M_EC_M_DSC (   x)    ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */

Definition at line 1504 of file skge.h.

◆ PHY_M_EC_S_DSC

#define PHY_M_EC_S_DSC (   x)    ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */

Definition at line 1505 of file skge.h.

◆ PHY_M_EC_MAC_S

#define PHY_M_EC_MAC_S (   x)    ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */

Definition at line 1506 of file skge.h.

◆ PHY_M_EC_M_DSC_2

#define PHY_M_EC_M_DSC_2 (   x)    ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */

Definition at line 1508 of file skge.h.

◆ PHY_M_LED_PULS_DUR

#define PHY_M_LED_PULS_DUR (   x)    (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)

Definition at line 1527 of file skge.h.

◆ PHY_M_LED_BLINK_RT

#define PHY_M_LED_BLINK_RT (   x)    (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)

Definition at line 1528 of file skge.h.

◆ PHY_M_LED_MO_SGMII

#define PHY_M_LED_MO_SGMII (   x)    ((x)<<14) /* Bit 15..14: SGMII AN Timer */

Definition at line 1561 of file skge.h.

◆ PHY_M_LED_MO_DUP

#define PHY_M_LED_MO_DUP (   x)    ((x)<<10) /* Bit 11..10: Duplex */

Definition at line 1563 of file skge.h.

◆ PHY_M_LED_MO_10

#define PHY_M_LED_MO_10 (   x)    ((x)<<8) /* Bit 9.. 8: Link 10 */

Definition at line 1564 of file skge.h.

◆ PHY_M_LED_MO_100

#define PHY_M_LED_MO_100 (   x)    ((x)<<6) /* Bit 7.. 6: Link 100 */

Definition at line 1565 of file skge.h.

◆ PHY_M_LED_MO_1000

#define PHY_M_LED_MO_1000 (   x)    ((x)<<4) /* Bit 5.. 4: Link 1000 */

Definition at line 1566 of file skge.h.

◆ PHY_M_LED_MO_RX

#define PHY_M_LED_MO_RX (   x)    ((x)<<2) /* Bit 3.. 2: Rx */

Definition at line 1567 of file skge.h.

◆ PHY_M_LED_MO_TX

#define PHY_M_LED_MO_TX (   x)    ((x)<<0) /* Bit 1.. 0: Tx */

Definition at line 1568 of file skge.h.

◆ PHY_M_FELP_LED2_CTRL

#define PHY_M_FELP_LED2_CTRL (   x)    (((x)<<8) & PHY_M_FELP_LED2_MSK)

Definition at line 1630 of file skge.h.

◆ PHY_M_FELP_LED1_CTRL

#define PHY_M_FELP_LED1_CTRL (   x)    (((x)<<4) & PHY_M_FELP_LED1_MSK)

Definition at line 1631 of file skge.h.

◆ PHY_M_FELP_LED0_CTRL

#define PHY_M_FELP_LED0_CTRL (   x)    (((x)<<0) & PHY_M_FELP_LED0_MSK)

Definition at line 1632 of file skge.h.

◆ PHY_M_LEDC_LOS_CTRL

#define PHY_M_LEDC_LOS_CTRL (   x)    (((x)<<12) & PHY_M_LEDC_LOS_MSK)

Definition at line 1669 of file skge.h.

◆ PHY_M_LEDC_INIT_CTRL

#define PHY_M_LEDC_INIT_CTRL (   x)    (((x)<<8) & PHY_M_LEDC_INIT_MSK)

Definition at line 1670 of file skge.h.

◆ PHY_M_LEDC_STA1_CTRL

#define PHY_M_LEDC_STA1_CTRL (   x)    (((x)<<4) & PHY_M_LEDC_STA1_MSK)

Definition at line 1671 of file skge.h.

◆ PHY_M_LEDC_STA0_CTRL

#define PHY_M_LEDC_STA0_CTRL (   x)    (((x)<<0) & PHY_M_LEDC_STA0_MSK)

Definition at line 1672 of file skge.h.

◆ GM_MIB_CNT_BASE

#define GM_MIB_CNT_BASE   0x0100 /* Base Address of MIB Counters */

Definition at line 1715 of file skge.h.

◆ GM_MIB_CNT_SIZE

#define GM_MIB_CNT_SIZE   44 /* Number of MIB Counters */

Definition at line 1716 of file skge.h.

◆ GM_GPCR_SPEED_1000

#define GM_GPCR_SPEED_1000   (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)

Definition at line 1807 of file skge.h.

◆ GM_GPCR_AU_ALL_DIS

#define GM_GPCR_AU_ALL_DIS   (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)

Definition at line 1808 of file skge.h.

◆ TX_COL_THR

#define TX_COL_THR (   x)    (((x)<<10) & GM_TXCR_COL_THR_MSK)

Definition at line 1818 of file skge.h.

◆ TX_COL_DEF

#define TX_COL_DEF   0x04 /* late collision after 64 byte */

Definition at line 1819 of file skge.h.

◆ TX_JAM_LEN_VAL

#define TX_JAM_LEN_VAL (   x)    (((x)<<14) & GM_TXPA_JAMLEN_MSK)

Definition at line 1840 of file skge.h.

◆ TX_JAM_IPG_VAL

#define TX_JAM_IPG_VAL (   x)    (((x)<<9) & GM_TXPA_JAMIPG_MSK)

Definition at line 1841 of file skge.h.

◆ TX_IPG_JAM_DATA

#define TX_IPG_JAM_DATA (   x)    (((x)<<4) & GM_TXPA_JAMDAT_MSK)

Definition at line 1842 of file skge.h.

◆ DATA_BLIND_VAL

#define DATA_BLIND_VAL (   x)    (((x)<<11) & GM_SMOD_DATABL_MSK)

Definition at line 1854 of file skge.h.

◆ DATA_BLIND_DEF

#define DATA_BLIND_DEF   0x04

Definition at line 1855 of file skge.h.

◆ IPG_DATA_VAL

#define IPG_DATA_VAL (   x)    (x & GM_SMOD_IPG_MSK)

Definition at line 1857 of file skge.h.

◆ IPG_DATA_DEF

#define IPG_DATA_DEF   0x1e

Definition at line 1858 of file skge.h.

◆ GM_SMI_CT_PHY_AD

#define GM_SMI_CT_PHY_AD (   x)    (((x)<<11) & GM_SMI_CT_PHY_A_MSK)

Definition at line 1869 of file skge.h.

◆ GM_SMI_CT_REG_AD

#define GM_SMI_CT_REG_AD (   x)    (((x)<<6) & GM_SMI_CT_REG_A_MSK)

Definition at line 1870 of file skge.h.

◆ GPC_HWCFG_GMII_COP

#define GPC_HWCFG_GMII_COP   (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)

Definition at line 1988 of file skge.h.

◆ GPC_HWCFG_GMII_FIB

#define GPC_HWCFG_GMII_FIB   (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)

Definition at line 1989 of file skge.h.

◆ GPC_ANEG_ADV_ALL_M

#define GPC_ANEG_ADV_ALL_M   (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)

Definition at line 1990 of file skge.h.

◆ GPC_FRC10MBIT_HALF

#define GPC_FRC10MBIT_HALF   0

Definition at line 1993 of file skge.h.

◆ GPC_FRC10MBIT_FULL

#define GPC_FRC10MBIT_FULL   GPC_ANEG_0

Definition at line 1994 of file skge.h.

◆ GPC_FRC100MBIT_HALF

#define GPC_FRC100MBIT_HALF   GPC_ANEG_1

Definition at line 1995 of file skge.h.

◆ GPC_FRC100MBIT_FULL

#define GPC_FRC100MBIT_FULL   (GPC_ANEG_0 | GPC_ANEG_1)

Definition at line 1996 of file skge.h.

◆ GPC_ADV_1000_HALF

#define GPC_ADV_1000_HALF   GPC_ANEG_2

Definition at line 2000 of file skge.h.

◆ GPC_ADV_1000_FULL

#define GPC_ADV_1000_FULL   GPC_ANEG_3

Definition at line 2001 of file skge.h.

◆ GPC_ADV_ALL

#define GPC_ADV_ALL   (GPC_ANEG_2 | GPC_ANEG_3)

Definition at line 2002 of file skge.h.

◆ GPC_FORCE_MASTER

#define GPC_FORCE_MASTER   0

Definition at line 2006 of file skge.h.

◆ GPC_FORCE_SLAVE

#define GPC_FORCE_SLAVE   GPC_ANEG_0

Definition at line 2007 of file skge.h.

◆ GPC_PREF_MASTER

#define GPC_PREF_MASTER   GPC_ANEG_1

Definition at line 2008 of file skge.h.

◆ GPC_PREF_SLAVE

#define GPC_PREF_SLAVE   (GPC_ANEG_1 | GPC_ANEG_0)

Definition at line 2009 of file skge.h.

◆ GMAC_DEF_MSK

#define GMAC_DEF_MSK   (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)

Definition at line 2021 of file skge.h.

◆ WOL_CTL_DEFAULT

#define WOL_CTL_DEFAULT
Value:
(WOL_CTL_DIS_PME_ON_LINK_CHG | \
WOL_CTL_DIS_PME_ON_PATTERN | \
WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
WOL_CTL_DIS_LINK_CHG_UNIT | \
WOL_CTL_DIS_PATTERN_UNIT | \
WOL_CTL_DIS_MAGIC_PKT_UNIT)

Definition at line 2048 of file skge.h.

◆ WOL_CTL_PATT_ENA

#define WOL_CTL_PATT_ENA (   x)    (1 << (x))

Definition at line 2057 of file skge.h.

◆ XM_EXM

#define XM_EXM (   reg)    (XM_EXM_START + ((reg) << 3))

Definition at line 2089 of file skge.h.

◆ XM_RT_LIM_MSK

#define XM_RT_LIM_MSK   0x1f /* Bit 4..0: Tx Retry Limit */

Definition at line 2195 of file skge.h.

◆ XM_STIME_MSK

#define XM_STIME_MSK   0x7f /* Bit 6..0: Tx Slottime bits */

Definition at line 2199 of file skge.h.

◆ XM_IPG_MSK

#define XM_IPG_MSK   0xff /* Bit 7..0: IPG value bits */

Definition at line 2203 of file skge.h.

◆ XM_TX_WM_MSK

#define XM_TX_WM_MSK   0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */

Definition at line 2264 of file skge.h.

◆ XM_THR_MSK

#define XM_THR_MSK   0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */

Definition at line 2269 of file skge.h.

◆ XM_RX_WM_MSK

#define XM_RX_WM_MSK   0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */

Definition at line 2293 of file skge.h.

◆ XM_DEV_OUI

#define XM_DEV_OUI   (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */

Definition at line 2297 of file skge.h.

◆ XM_DEV_REV

#define XM_DEV_REV   (0x07L << 5) /* Bit 7..5: Chip Rev Num */

Definition at line 2298 of file skge.h.

◆ XM_PAUSE_MODE

#define XM_PAUSE_MODE   (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)

Definition at line 2336 of file skge.h.

◆ XM_DEF_MODE

#define XM_DEF_MODE
Value:
(XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)

Definition at line 2337 of file skge.h.

◆ XMR_DEF_MSK

#define XMR_DEF_MSK   (XMR_OK_LO_OV | XMR_OK_HI_OV)

Definition at line 2386 of file skge.h.

◆ XMT_DEF_MSK

#define XMT_DEF_MSK   (XMT_OK_LO_OV | XMT_OK_HI_OV)

Definition at line 2420 of file skge.h.

◆ SK_REG

#define SK_REG (   port,
  reg 
)    (((port)<<7)+(u16)(reg))

Definition at line 2548 of file skge.h.

◆ SK_XMAC_REG

#define SK_XMAC_REG (   port,
  reg 
)    ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)

Definition at line 2549 of file skge.h.

◆ SK_GMAC_REG

#define SK_GMAC_REG (   port,
  reg 
)    (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))

Definition at line 2593 of file skge.h.

Enumeration Type Documentation

◆ csr_regs

enum csr_regs
Enumerator
B0_RAP 
B0_CTST 
B0_LED 
B0_POWER_CTRL 
B0_ISRC 
B0_IMSK 
B0_HWE_ISRC 
B0_HWE_IMSK 
B0_SP_ISRC 
B0_XM1_IMSK 
B0_XM1_ISRC 
B0_XM1_PHY_ADDR 
B0_XM1_PHY_DATA 
B0_XM2_IMSK 
B0_XM2_ISRC 
B0_XM2_PHY_ADDR 
B0_XM2_PHY_DATA 
B0_R1_CSR 
B0_R2_CSR 
B0_XS1_CSR 
B0_XA1_CSR 
B0_XS2_CSR 
B0_XA2_CSR 
B2_MAC_1 
B2_MAC_2 
B2_MAC_3 
B2_CONN_TYP 
B2_PMD_TYP 
B2_MAC_CFG 
B2_CHIP_ID 
B2_E_0 
B2_E_1 
B2_E_2 
B2_E_3 
B2_FAR 
B2_FDP 
B2_LD_CTRL 
B2_LD_TEST 
B2_TI_INI 
B2_TI_VAL 
B2_TI_CTRL 
B2_TI_TEST 
B2_IRQM_INI 
B2_IRQM_VAL 
B2_IRQM_CTRL 
B2_IRQM_TEST 
B2_IRQM_MSK 
B2_IRQM_HWE_MSK 
B2_TST_CTRL1 
B2_TST_CTRL2 
B2_GP_IO 
B2_I2C_CTRL 
B2_I2C_DATA 
B2_I2C_IRQ 
B2_I2C_SW 
B2_BSC_INI 
B2_BSC_VAL 
B2_BSC_CTRL 
B2_BSC_STAT 
B2_BSC_TST 
B3_RAM_ADDR 
B3_RAM_DATA_LO 
B3_RAM_DATA_HI 
B3_RI_WTO_R1 
B3_RI_WTO_XA1 
B3_RI_WTO_XS1 
B3_RI_RTO_R1 
B3_RI_RTO_XA1 
B3_RI_RTO_XS1 
B3_RI_WTO_R2 
B3_RI_WTO_XA2 
B3_RI_WTO_XS2 
B3_RI_RTO_R2 
B3_RI_RTO_XA2 
B3_RI_RTO_XS2 
B3_RI_TO_VAL 
B3_RI_CTRL 
B3_RI_TEST 
B3_MA_TOINI_RX1 
B3_MA_TOINI_RX2 
B3_MA_TOINI_TX1 
B3_MA_TOINI_TX2 
B3_MA_TOVAL_RX1 
B3_MA_TOVAL_RX2 
B3_MA_TOVAL_TX1 
B3_MA_TOVAL_TX2 
B3_MA_TO_CTRL 
B3_MA_TO_TEST 
B3_MA_RCINI_RX1 
B3_MA_RCINI_RX2 
B3_MA_RCINI_TX1 
B3_MA_RCINI_TX2 
B3_MA_RCVAL_RX1 
B3_MA_RCVAL_RX2 
B3_MA_RCVAL_TX1 
B3_MA_RCVAL_TX2 
B3_MA_RC_CTRL 
B3_MA_RC_TEST 
B3_PA_TOINI_RX1 
B3_PA_TOINI_RX2 
B3_PA_TOINI_TX1 
B3_PA_TOINI_TX2 
B3_PA_TOVAL_RX1 
B3_PA_TOVAL_RX2 
B3_PA_TOVAL_TX1 
B3_PA_TOVAL_TX2 
B3_PA_CTRL 
B3_PA_TEST 
B0_RAP 
B0_CTST 
B0_Y2LED 
B0_POWER_CTRL 
B0_ISRC 
B0_IMSK 
B0_HWE_ISRC 
B0_HWE_IMSK 
B0_Y2_SP_ISRC2 
B0_Y2_SP_ISRC3 
B0_Y2_SP_EISR 
B0_Y2_SP_LISR 
B0_Y2_SP_ICR 
B2_MAC_1 
B2_MAC_2 
B2_MAC_3 
B2_CONN_TYP 
B2_PMD_TYP 
B2_MAC_CFG 
B2_CHIP_ID 
B2_E_0 
B2_Y2_CLK_GATE 
B2_Y2_HW_RES 
B2_E_3 
B2_Y2_CLK_CTRL 
B2_TI_INI 
B2_TI_VAL 
B2_TI_CTRL 
B2_TI_TEST 
B2_TST_CTRL1 
B2_TST_CTRL2 
B2_GP_IO 
B2_I2C_CTRL 
B2_I2C_DATA 
B2_I2C_IRQ 
B2_I2C_SW 
B3_RAM_ADDR 
B3_RAM_DATA_LO 
B3_RAM_DATA_HI 
B3_RI_WTO_R1 
B3_RI_WTO_XA1 
B3_RI_WTO_XS1 
B3_RI_RTO_R1 
B3_RI_RTO_XA1 
B3_RI_RTO_XS1 
B3_RI_WTO_R2 
B3_RI_WTO_XA2 
B3_RI_WTO_XS2 
B3_RI_RTO_R2 
B3_RI_RTO_XA2 
B3_RI_RTO_XS2 
B3_RI_TO_VAL 
B3_RI_CTRL 
B3_RI_TEST 
B3_MA_TOINI_RX1 
B3_MA_TOINI_RX2 
B3_MA_TOINI_TX1 
B3_MA_TOINI_TX2 
B3_MA_TOVAL_RX1 
B3_MA_TOVAL_RX2 
B3_MA_TOVAL_TX1 
B3_MA_TOVAL_TX2 
B3_MA_TO_CTRL 
B3_MA_TO_TEST 
B3_MA_RCINI_RX1 
B3_MA_RCINI_RX2 
B3_MA_RCINI_TX1 
B3_MA_RCINI_TX2 
B3_MA_RCVAL_RX1 
B3_MA_RCVAL_RX2 
B3_MA_RCVAL_TX1 
B3_MA_RCVAL_TX2 
B3_MA_RC_CTRL 
B3_MA_RC_TEST 
B3_PA_TOINI_RX1 
B3_PA_TOINI_RX2 
B3_PA_TOINI_TX1 
B3_PA_TOINI_TX2 
B3_PA_TOVAL_RX1 
B3_PA_TOVAL_RX2 
B3_PA_TOVAL_TX1 
B3_PA_TOVAL_TX2 
B3_PA_CTRL 
B3_PA_TEST 
Y2_CFG_SPC 
Y2_CFG_AER 

Definition at line 76 of file skge.h.

76  {
77  B0_RAP = 0x0000,
78  B0_CTST = 0x0004,
79  B0_LED = 0x0006,
80  B0_POWER_CTRL = 0x0007,
81  B0_ISRC = 0x0008,
82  B0_IMSK = 0x000c,
83  B0_HWE_ISRC = 0x0010,
84  B0_HWE_IMSK = 0x0014,
85  B0_SP_ISRC = 0x0018,
86  B0_XM1_IMSK = 0x0020,
87  B0_XM1_ISRC = 0x0028,
88  B0_XM1_PHY_ADDR = 0x0030,
89  B0_XM1_PHY_DATA = 0x0034,
90  B0_XM2_IMSK = 0x0040,
91  B0_XM2_ISRC = 0x0048,
92  B0_XM2_PHY_ADDR = 0x0050,
93  B0_XM2_PHY_DATA = 0x0054,
94  B0_R1_CSR = 0x0060,
95  B0_R2_CSR = 0x0064,
96  B0_XS1_CSR = 0x0068,
97  B0_XA1_CSR = 0x006c,
98  B0_XS2_CSR = 0x0070,
99  B0_XA2_CSR = 0x0074,
100 
101  B2_MAC_1 = 0x0100,
102  B2_MAC_2 = 0x0108,
103  B2_MAC_3 = 0x0110,
104  B2_CONN_TYP = 0x0118,
105  B2_PMD_TYP = 0x0119,
106  B2_MAC_CFG = 0x011a,
107  B2_CHIP_ID = 0x011b,
108  B2_E_0 = 0x011c,
109  B2_E_1 = 0x011d,
110  B2_E_2 = 0x011e,
111  B2_E_3 = 0x011f,
112  B2_FAR = 0x0120,
113  B2_FDP = 0x0124,
114  B2_LD_CTRL = 0x0128,
115  B2_LD_TEST = 0x0129,
116  B2_TI_INI = 0x0130,
117  B2_TI_VAL = 0x0134,
118  B2_TI_CTRL = 0x0138,
119  B2_TI_TEST = 0x0139,
120  B2_IRQM_INI = 0x0140,
121  B2_IRQM_VAL = 0x0144,
122  B2_IRQM_CTRL = 0x0148,
123  B2_IRQM_TEST = 0x0149,
124  B2_IRQM_MSK = 0x014c,
125  B2_IRQM_HWE_MSK = 0x0150,
126  B2_TST_CTRL1 = 0x0158,
127  B2_TST_CTRL2 = 0x0159,
128  B2_GP_IO = 0x015c,
129  B2_I2C_CTRL = 0x0160,
130  B2_I2C_DATA = 0x0164,
131  B2_I2C_IRQ = 0x0168,
132  B2_I2C_SW = 0x016c,
133  B2_BSC_INI = 0x0170,
134  B2_BSC_VAL = 0x0174,
135  B2_BSC_CTRL = 0x0178,
136  B2_BSC_STAT = 0x0179,
137  B2_BSC_TST = 0x017a,
138 
139  B3_RAM_ADDR = 0x0180,
140  B3_RAM_DATA_LO = 0x0184,
141  B3_RAM_DATA_HI = 0x0188,
142  B3_RI_WTO_R1 = 0x0190,
143  B3_RI_WTO_XA1 = 0x0191,
144  B3_RI_WTO_XS1 = 0x0192,
145  B3_RI_RTO_R1 = 0x0193,
146  B3_RI_RTO_XA1 = 0x0194,
147  B3_RI_RTO_XS1 = 0x0195,
148  B3_RI_WTO_R2 = 0x0196,
149  B3_RI_WTO_XA2 = 0x0197,
150  B3_RI_WTO_XS2 = 0x0198,
151  B3_RI_RTO_R2 = 0x0199,
152  B3_RI_RTO_XA2 = 0x019a,
153  B3_RI_RTO_XS2 = 0x019b,
154  B3_RI_TO_VAL = 0x019c,
155  B3_RI_CTRL = 0x01a0,
156  B3_RI_TEST = 0x01a2,
157  B3_MA_TOINI_RX1 = 0x01b0,
158  B3_MA_TOINI_RX2 = 0x01b1,
159  B3_MA_TOINI_TX1 = 0x01b2,
160  B3_MA_TOINI_TX2 = 0x01b3,
161  B3_MA_TOVAL_RX1 = 0x01b4,
162  B3_MA_TOVAL_RX2 = 0x01b5,
163  B3_MA_TOVAL_TX1 = 0x01b6,
164  B3_MA_TOVAL_TX2 = 0x01b7,
165  B3_MA_TO_CTRL = 0x01b8,
166  B3_MA_TO_TEST = 0x01ba,
167  B3_MA_RCINI_RX1 = 0x01c0,
168  B3_MA_RCINI_RX2 = 0x01c1,
169  B3_MA_RCINI_TX1 = 0x01c2,
170  B3_MA_RCINI_TX2 = 0x01c3,
171  B3_MA_RCVAL_RX1 = 0x01c4,
172  B3_MA_RCVAL_RX2 = 0x01c5,
173  B3_MA_RCVAL_TX1 = 0x01c6,
174  B3_MA_RCVAL_TX2 = 0x01c7,
175  B3_MA_RC_CTRL = 0x01c8,
176  B3_MA_RC_TEST = 0x01ca,
177  B3_PA_TOINI_RX1 = 0x01d0,
178  B3_PA_TOINI_RX2 = 0x01d4,
179  B3_PA_TOINI_TX1 = 0x01d8,
180  B3_PA_TOINI_TX2 = 0x01dc,
181  B3_PA_TOVAL_RX1 = 0x01e0,
182  B3_PA_TOVAL_RX2 = 0x01e4,
183  B3_PA_TOVAL_TX1 = 0x01e8,
184  B3_PA_TOVAL_TX2 = 0x01ec,
185  B3_PA_CTRL = 0x01f0,
186  B3_PA_TEST = 0x01f2,
187 };
B2_E_0
Definition: skge.h:108
B0_RAP
Definition: skge.h:77
B0_ISRC
Definition: skge.h:81
B2_MAC_2
Definition: skge.h:102
B2_E_2
Definition: skge.h:110
B0_IMSK
Definition: skge.h:82
B2_E_1
Definition: skge.h:109
B0_LED
Definition: skge.h:79
B0_R1_CSR
Definition: skge.h:94
B2_E_3
Definition: skge.h:111
B2_FDP
Definition: skge.h:113
B0_CTST
Definition: skge.h:78
B2_MAC_3
Definition: skge.h:103
B0_R2_CSR
Definition: skge.h:95
B2_GP_IO
Definition: skge.h:128
B2_FAR
Definition: skge.h:112
B2_MAC_1
Definition: skge.h:101

◆ anonymous enum

anonymous enum
Enumerator
CS_CLK_RUN_HOT 
CS_CLK_RUN_RST 
CS_CLK_RUN_ENA 
CS_VAUX_AVAIL 
CS_BUS_CLOCK 
CS_BUS_SLOT_SZ 
CS_ST_SW_IRQ 
CS_CL_SW_IRQ 
CS_STOP_DONE 
CS_STOP_MAST 
CS_MRST_CLR 
CS_MRST_SET 
CS_RST_CLR 
CS_RST_SET 
LED_STAT_ON 
LED_STAT_OFF 
PC_VAUX_ENA 
PC_VAUX_DIS 
PC_VCC_ENA 
PC_VCC_DIS 
PC_VAUX_ON 
PC_VAUX_OFF 
PC_VCC_ON 
PC_VCC_OFF 

Definition at line 190 of file skge.h.

190  {
191  CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
192  CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
193  CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
194  CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
195  CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
196  CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
197  CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
198  CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
199  CS_STOP_DONE = 1<<5, /* Stop Master is finished */
200  CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
201  CS_MRST_CLR = 1<<3, /* Clear Master reset */
202  CS_MRST_SET = 1<<2, /* Set Master reset */
203  CS_RST_CLR = 1<<1, /* Clear Software reset */
204  CS_RST_SET = 1, /* Set Software reset */
205 
206 /* B0_LED 8 Bit LED register */
207 /* Bit 7.. 2: reserved */
208  LED_STAT_ON = 1<<1, /* Status LED on */
209  LED_STAT_OFF = 1, /* Status LED off */
210 
211 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
212  PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
213  PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
214  PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
215  PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
216  PC_VAUX_ON = 1<<3, /* Switch VAUX On */
217  PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
218  PC_VCC_ON = 1<<1, /* Switch VCC On */
219  PC_VCC_OFF = 1<<0, /* Switch VCC Off */
220 };

◆ anonymous enum

anonymous enum
Enumerator
IS_ALL_MSK 
IS_HW_ERR 
IS_PA_TO_RX1 
IS_PA_TO_RX2 
IS_PA_TO_TX1 
IS_PA_TO_TX2 
IS_I2C_READY 
IS_IRQ_SW 
IS_EXT_REG 
IS_TIMINT 
IS_MAC1 
IS_LNK_SYNC_M1 
IS_MAC2 
IS_LNK_SYNC_M2 
IS_R1_B 
IS_R1_F 
IS_R1_C 
IS_R2_B 
IS_R2_F 
IS_R2_C 
IS_XS1_B 
IS_XS1_F 
IS_XS1_C 
IS_XA1_B 
IS_XA1_F 
IS_XA1_C 
IS_XS2_B 
IS_XS2_F 
IS_XS2_C 
IS_XA2_B 
IS_XA2_F 
IS_XA2_C 
IS_TO_PORT1 
IS_TO_PORT2 
IS_PORT_1 
IS_PORT_2 

Definition at line 223 of file skge.h.

223  {
224  IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
225  IS_HW_ERR = 1<<31, /* Interrupt HW Error */
226  /* Bit 30: reserved */
227  IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
228  IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
229  IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
230  IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
231  IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
232  IS_IRQ_SW = 1<<24, /* SW forced IRQ */
233  IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
234  /* IRQ from PHY (YUKON only) */
235  IS_TIMINT = 1<<22, /* IRQ from Timer */
236  IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
237  IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
238  IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
239  IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
240 /* Receive Queue 1 */
241  IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
242  IS_R1_F = 1<<16, /* Q_R1 End of Frame */
243  IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
244 /* Receive Queue 2 */
245  IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
246  IS_R2_F = 1<<13, /* Q_R2 End of Frame */
247  IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
248 /* Synchronous Transmit Queue 1 */
249  IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
250  IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
251  IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
252 /* Asynchronous Transmit Queue 1 */
253  IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
254  IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
255  IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
256 /* Synchronous Transmit Queue 2 */
257  IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
258  IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
259  IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
260 /* Asynchronous Transmit Queue 2 */
261  IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
262  IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
263  IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
264 
265  IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
266  IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
267 
268  IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
269  IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
270 };
IS_XA1_F
Definition: skge.h:254
IS_XS1_F
Definition: skge.h:250
IS_XS2_C
Definition: skge.h:259
IS_XA2_C
Definition: skge.h:263
IS_XA1_B
Definition: skge.h:253
IS_R1_C
Definition: skge.h:243
IS_R2_B
Definition: skge.h:245
IS_MAC1
Definition: skge.h:236
IS_XA2_B
Definition: skge.h:261
IS_XS1_B
Definition: skge.h:249
IS_XA2_F
Definition: skge.h:262
IS_XS2_F
Definition: skge.h:258
IS_R1_F
Definition: skge.h:242
IS_XS2_B
Definition: skge.h:257
IS_MAC2
Definition: skge.h:238
IS_XA1_C
Definition: skge.h:255
IS_XS1_C
Definition: skge.h:251
IS_R2_C
Definition: skge.h:247
IS_R2_F
Definition: skge.h:246
IS_R1_B
Definition: skge.h:241

◆ anonymous enum

anonymous enum
Enumerator
IS_IRQ_TIST_OV 
IS_IRQ_SENSOR 
IS_IRQ_MST_ERR 
IS_IRQ_STAT 
IS_NO_STAT_M1 
IS_NO_STAT_M2 
IS_NO_TIST_M1 
IS_NO_TIST_M2 
IS_RAM_RD_PAR 
IS_RAM_WR_PAR 
IS_M1_PAR_ERR 
IS_M2_PAR_ERR 
IS_R1_PAR_ERR 
IS_R2_PAR_ERR 
IS_ERR_MSK 

Definition at line 274 of file skge.h.

274  {
275  IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
276  IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
277  IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
278  IS_IRQ_STAT = 1<<10, /* IRQ status exception */
279  IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
280  IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
281  IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
282  IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
283  IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
284  IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
285  IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
286  IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
287  IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
288  IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
289 
290  IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
291  | IS_RAM_RD_PAR | IS_RAM_WR_PAR
292  | IS_M1_PAR_ERR | IS_M2_PAR_ERR
293  | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
294 };

◆ anonymous enum

anonymous enum
Enumerator
TST_FRC_DPERR_MR 
TST_FRC_DPERR_MW 
TST_FRC_DPERR_TR 
TST_FRC_DPERR_TW 
TST_FRC_APERR_M 
TST_FRC_APERR_T 
TST_CFG_WRITE_ON 
TST_CFG_WRITE_OFF 

Definition at line 297 of file skge.h.

297  {
298  TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
299  TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
300  TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
301  TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
302  TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
303  TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
304  TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
305  TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
306 };

◆ anonymous enum

anonymous enum
Enumerator
CFG_CHIP_R_MSK 
CFG_DIS_M2_CLK 
CFG_SNG_MAC 

Definition at line 309 of file skge.h.

309  {
310  CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
311  /* Bit 3.. 2: reserved */
312  CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
313  CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
314 };

◆ anonymous enum

anonymous enum
Enumerator
CHIP_ID_GENESIS 
CHIP_ID_YUKON 
CHIP_ID_YUKON_LITE 
CHIP_ID_YUKON_LP 
CHIP_ID_YUKON_XL 
CHIP_ID_YUKON_EC 
CHIP_ID_YUKON_FE 
CHIP_REV_YU_LITE_A1 
CHIP_REV_YU_LITE_A3 

Definition at line 317 of file skge.h.

317  {
318  CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
319  CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
320  CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
321  CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
322  CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
323  CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
324  CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
325 
326  CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
327  CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
328 };

◆ anonymous enum

anonymous enum
Enumerator
TIM_START 
TIM_STOP 
TIM_CLR_IRQ 

Definition at line 332 of file skge.h.

332  {
333  TIM_START = 1<<2, /* Start Timer */
334  TIM_STOP = 1<<1, /* Stop Timer */
335  TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
336 };
TIM_STOP
Definition: skge.h:334

◆ anonymous enum

anonymous enum
Enumerator
TIM_T_ON 
TIM_T_OFF 
TIM_T_STEP 

Definition at line 341 of file skge.h.

341  {
342  TIM_T_ON = 1<<2, /* Test mode on */
343  TIM_T_OFF = 1<<1, /* Test mode off */
344  TIM_T_STEP = 1<<0, /* Test step */
345 };
TIM_T_ON
Definition: skge.h:342

◆ anonymous enum

anonymous enum
Enumerator
GP_DIR_9 
GP_DIR_8 
GP_DIR_7 
GP_DIR_6 
GP_DIR_5 
GP_DIR_4 
GP_DIR_3 
GP_DIR_2 
GP_DIR_1 
GP_DIR_0 
GP_IO_9 
GP_IO_8 
GP_IO_7 
GP_IO_6 
GP_IO_5 
GP_IO_4 
GP_IO_3 
GP_IO_2 
GP_IO_1 
GP_IO_0 

Definition at line 348 of file skge.h.

348  {
349  GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
350  GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
351  GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
352  GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
353  GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
354  GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
355  GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
356  GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
357  GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
358  GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
359 
360  GP_IO_9 = 1<<9, /* IO_9 pin */
361  GP_IO_8 = 1<<8, /* IO_8 pin */
362  GP_IO_7 = 1<<7, /* IO_7 pin */
363  GP_IO_6 = 1<<6, /* IO_6 pin */
364  GP_IO_5 = 1<<5, /* IO_5 pin */
365  GP_IO_4 = 1<<4, /* IO_4 pin */
366  GP_IO_3 = 1<<3, /* IO_3 pin */
367  GP_IO_2 = 1<<2, /* IO_2 pin */
368  GP_IO_1 = 1<<1, /* IO_1 pin */
369  GP_IO_0 = 1<<0, /* IO_0 pin */
370 };
GP_IO_5
Definition: skge.h:364
GP_IO_7
Definition: skge.h:362
GP_IO_6
Definition: skge.h:363
GP_IO_3
Definition: skge.h:366
GP_DIR_5
Definition: skge.h:353
GP_IO_2
Definition: skge.h:367
GP_DIR_3
Definition: skge.h:355
GP_DIR_9
Definition: skge.h:349
GP_DIR_8
Definition: skge.h:350
GP_IO_9
Definition: skge.h:360
GP_DIR_6
Definition: skge.h:352
GP_DIR_0
Definition: skge.h:358
GP_IO_4
Definition: skge.h:365
GP_IO_0
Definition: skge.h:369
GP_IO_1
Definition: skge.h:368
GP_DIR_7
Definition: skge.h:351
GP_DIR_2
Definition: skge.h:356
GP_DIR_4
Definition: skge.h:354
GP_DIR_1
Definition: skge.h:357
GP_IO_8
Definition: skge.h:361

◆ anonymous enum

anonymous enum
Enumerator
BMU_OWN 
BMU_STF 
BMU_EOF 
BMU_IRQ_EOB 
BMU_IRQ_EOF 
BMU_STFWD 
BMU_NO_FCS 
BMU_SW 
BMU_DEV_0 
BMU_STAT_VAL 
BMU_TIST_VAL 
BMU_CHECK 
BMU_TCP_CHECK 
BMU_UDP_CHECK 
BMU_BBC 

Definition at line 375 of file skge.h.

375  {
376  BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
377  BMU_STF = 1<<30, /* Start of Frame */
378  BMU_EOF = 1<<29, /* End of Frame */
379  BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
380  BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
381  /* TxCtrl specific bits */
382  BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
383  BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
384  BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
385  /* RxCtrl specific bits */
386  BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
387  BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
388  BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
389  /* Bit 23..16: BMU Check Opcodes */
390  BMU_CHECK = 0x55<<16, /* Default BMU check */
391  BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
392  BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
393  BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
394 };
BMU_STF
Definition: skge.h:377
BMU_SW
Definition: skge.h:384
BMU_BBC
Definition: skge.h:393
BMU_EOF
Definition: skge.h:378
BMU_OWN
Definition: skge.h:376

◆ anonymous enum

anonymous enum
Enumerator
BSC_START 
BSC_STOP 

Definition at line 397 of file skge.h.

397  {
398  BSC_START = 1<<1, /* Start Blink Source Counter */
399  BSC_STOP = 1<<0, /* Stop Blink Source Counter */
400 };
BSC_STOP
Definition: skge.h:399

◆ anonymous enum

anonymous enum
Enumerator
BSC_SRC 

Definition at line 403 of file skge.h.

403  {
404  BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
405 };
BSC_SRC
Definition: skge.h:404

◆ anonymous enum

anonymous enum
Enumerator
BSC_T_ON 
BSC_T_OFF 
BSC_T_STEP 

Definition at line 408 of file skge.h.

408  {
409  BSC_T_ON = 1<<2, /* Test mode on */
410  BSC_T_OFF = 1<<1, /* Test mode off */
411  BSC_T_STEP = 1<<0, /* Test step */
412 };
BSC_T_ON
Definition: skge.h:409

◆ anonymous enum

anonymous enum
Enumerator
RI_CLR_RD_PERR 
RI_CLR_WR_PERR 
RI_RST_CLR 
RI_RST_SET 

Definition at line 420 of file skge.h.

420  {
421  RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
422  RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
423 
424  RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
425  RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
426 };

◆ anonymous enum

anonymous enum
Enumerator
MA_FOE_ON 
MA_FOE_OFF 
MA_RST_CLR 
MA_RST_SET 

Definition at line 430 of file skge.h.

430  {
431  MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
432  MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
433  MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
434  MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
435 
436 };

◆ anonymous enum

anonymous enum
Enumerator
PA_CLR_TO_TX2 
PA_CLR_TO_TX1 
PA_CLR_TO_RX2 
PA_CLR_TO_RX1 
PA_ENA_TO_TX2 
PA_DIS_TO_TX2 
PA_ENA_TO_TX1 
PA_DIS_TO_TX1 
PA_ENA_TO_RX2 
PA_DIS_TO_RX2 
PA_ENA_TO_RX1 
PA_DIS_TO_RX1 
PA_RST_CLR 
PA_RST_SET 

Definition at line 446 of file skge.h.

446  {
447  PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
448  PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
449  PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
450  PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
451  PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
452  PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
453  PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
454  PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
455  PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
456  PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
457  PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
458  PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
459  PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
460  PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
461 };

◆ anonymous enum

anonymous enum
Enumerator
TXA_ENA_FSYNC 
TXA_DIS_FSYNC 
TXA_ENA_ALLOC 
TXA_DIS_ALLOC 
TXA_START_RC 
TXA_STOP_RC 
TXA_ENA_ARB 
TXA_DIS_ARB 

Definition at line 476 of file skge.h.

476  {
477  TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
478  TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
479  TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
480  TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
481  TXA_START_RC = 1<<3, /* Start sync Rate Control */
482  TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
483  TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
484  TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
485 };

◆ anonymous enum

anonymous enum
Enumerator
TXA_ITI_INI 
TXA_ITI_VAL 
TXA_LIM_INI 
TXA_LIM_VAL 
TXA_CTRL 
TXA_TEST 
TXA_STAT 

Definition at line 491 of file skge.h.

491  {
492  TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
493  TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
494  TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
495  TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
496  TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
497  TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
498  TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
499 };
TXA_CTRL
Definition: skge.h:496
TXA_TEST
Definition: skge.h:497
TXA_STAT
Definition: skge.h:498

◆ anonymous enum

anonymous enum
Enumerator
B6_EXT_REG 
B7_CFG_SPC 
B8_RQ1_REGS 
B8_RQ2_REGS 
B8_TS1_REGS 
B8_TA1_REGS 
B8_TS2_REGS 
B8_TA2_REGS 
B16_RAM_REGS 

Definition at line 502 of file skge.h.

502  {
503  B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
504  B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
505  B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
506  B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
507  B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
508  B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
509  B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
510  B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
511  B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
512 };

◆ anonymous enum

anonymous enum
Enumerator
B8_Q_REGS 
Q_D 
Q_DA_L 
Q_DA_H 
Q_AC_L 
Q_AC_H 
Q_BC 
Q_CSR 
Q_F 
Q_T1 
Q_T1_TR 
Q_T1_WR 
Q_T1_RD 
Q_T1_SV 
Q_T2 
Q_T3 

Definition at line 515 of file skge.h.

515  {
516  B8_Q_REGS = 0x0400, /* base of Queue registers */
517  Q_D = 0x00, /* 8*32 bit Current Descriptor */
518  Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
519  Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
520  Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
521  Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
522  Q_BC = 0x30, /* 32 bit Current Byte Counter */
523  Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
524  Q_F = 0x38, /* 32 bit Flag Register */
525  Q_T1 = 0x3c, /* 32 bit Test Register 1 */
526  Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
527  Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
528  Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
529  Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
530  Q_T2 = 0x40, /* 32 bit Test Register 2 */
531  Q_T3 = 0x44, /* 32 bit Test Register 3 */
532 
533 };
Q_T2
Definition: skge.h:530
Q_F
Definition: skge.h:524
Q_DA_H
Definition: skge.h:519
Q_CSR
Definition: skge.h:523
Q_T1_TR
Definition: skge.h:526
Q_T3
Definition: skge.h:531
Q_BC
Definition: skge.h:522
Q_T1_RD
Definition: skge.h:528
Q_D
Definition: skge.h:517
Q_AC_H
Definition: skge.h:521
Q_AC_L
Definition: skge.h:520
Q_T1_WR
Definition: skge.h:527
Q_T1_SV
Definition: skge.h:529
Q_T1
Definition: skge.h:525
Q_DA_L
Definition: skge.h:518

◆ anonymous enum

anonymous enum
Enumerator
RB_START 
RB_END 
RB_WP 
RB_RP 
RB_RX_UTPP 
RB_RX_LTPP 
RB_RX_UTHP 
RB_RX_LTHP 
RB_PC 
RB_LEV 
RB_CTRL 
RB_TST1 
RB_TST2 

Definition at line 537 of file skge.h.

537  {
538 
539  RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
540  RB_END = 0x04,/* 32 bit RAM Buffer End Address */
541  RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
542  RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
543  RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
544  RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
545  RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
546  RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
547  /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
548  RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
549  RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
550  RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
551  RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
552  RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
553 };
RB_CTRL
Definition: skge.h:550
RB_LEV
Definition: skge.h:549
RB_START
Definition: skge.h:539
RB_WP
Definition: skge.h:541
RB_PC
Definition: skge.h:548
RB_RP
Definition: skge.h:542
RB_TST1
Definition: skge.h:551
RB_TST2
Definition: skge.h:552
RB_END
Definition: skge.h:540

◆ anonymous enum

anonymous enum
Enumerator
Q_R1 
Q_R2 
Q_XS1 
Q_XA1 
Q_XS2 
Q_XA2 

Definition at line 556 of file skge.h.

556  {
557  Q_R1 = 0x0000, /* Receive Queue 1 */
558  Q_R2 = 0x0080, /* Receive Queue 2 */
559  Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
560  Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
561  Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
562  Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
563 };
Q_R2
Definition: skge.h:558
Q_XS1
Definition: skge.h:559
Q_R1
Definition: skge.h:557
Q_XA1
Definition: skge.h:560
Q_XS2
Definition: skge.h:561
Q_XA2
Definition: skge.h:562

◆ anonymous enum

anonymous enum
Enumerator
SK_MAC_XMAC 
SK_MAC_GMAC 

Definition at line 566 of file skge.h.

566  {
567  SK_MAC_XMAC = 0, /* Xaqti XMAC II */
568  SK_MAC_GMAC = 1, /* Marvell GMAC */
569 };

◆ anonymous enum

anonymous enum
Enumerator
SK_PHY_XMAC 
SK_PHY_BCOM 
SK_PHY_LONE 
SK_PHY_NAT 
SK_PHY_MARV_COPPER 
SK_PHY_MARV_FIBER 

Definition at line 572 of file skge.h.

572  {
573  SK_PHY_XMAC = 0,/* integrated in XMAC II */
574  SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
575  SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
576  SK_PHY_NAT = 3,/* National DP83891 [not supported] */
577  SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
578  SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
579 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_ADDR_XMAC 
PHY_ADDR_BCOM 
PHY_ADDR_MARV 

Definition at line 582 of file skge.h.

582  {
583  PHY_ADDR_XMAC = 0<<8,
584  PHY_ADDR_BCOM = 1<<8,
585 
586 /* GPHY address (bits 15..11 of SMI control reg) */
587  PHY_ADDR_MARV = 0,
588 };

◆ anonymous enum

anonymous enum
Enumerator
RX_MFF_EA 
RX_MFF_WP 
RX_MFF_RP 
RX_MFF_PC 
RX_MFF_LEV 
RX_MFF_CTRL1 
RX_MFF_STAT_TO 
RX_MFF_TIST_TO 
RX_MFF_CTRL2 
RX_MFF_TST1 
RX_MFF_TST2 
RX_LED_INI 
RX_LED_VAL 
RX_LED_CTRL 
RX_LED_TST 
LNK_SYNC_INI 
LNK_SYNC_VAL 
LNK_SYNC_CTRL 
LNK_SYNC_TST 
LNK_LED_REG 

Definition at line 593 of file skge.h.

593  {
594  RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
595  RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
596 
597  RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
598  RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
599  RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
600  RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
601  RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
602  RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
603  RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
604  RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
605  RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
606 
607  RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
608  RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
609  RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
610  RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
611 
612  LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
613  LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
614  LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
615  LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
616  LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
617 };

◆ anonymous enum

anonymous enum
Enumerator
MFF_ENA_RDY_PAT 
MFF_DIS_RDY_PAT 
MFF_ENA_TIM_PAT 
MFF_DIS_TIM_PAT 
MFF_ENA_ALM_FUL 
MFF_DIS_ALM_FUL 
MFF_ENA_PAUSE 
MFF_DIS_PAUSE 
MFF_ENA_FLUSH 
MFF_DIS_FLUSH 
MFF_ENA_TIST 
MFF_DIS_TIST 
MFF_CLR_INTIST 
MFF_CLR_INSTAT 
MFF_RX_CTRL_DEF 

Definition at line 621 of file skge.h.

621  {
622  MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
623  MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
624  MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
625  MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
626  MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
627  MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
628  MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
629  MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
630  MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
631  MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
632  MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
633  MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
634  MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
635  MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
636  MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
637 };

◆ anonymous enum

anonymous enum
Enumerator
MFF_CLR_PERR 
MFF_ENA_PKT_REC 
MFF_DIS_PKT_REC 
MFF_ENA_W4E 
MFF_DIS_W4E 
MFF_ENA_LOOPB 
MFF_DIS_LOOPB 
MFF_CLR_MAC_RST 
MFF_SET_MAC_RST 
MFF_TX_CTRL_DEF 

Definition at line 640 of file skge.h.

640  {
641  MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
642 
643  MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
644  MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
645 
646  MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
647  MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
648 
649  MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
650  MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
651  MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
652  MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
653 
654  MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
655 };
u16
#define u16
Definition: vga.h:20

◆ anonymous enum

anonymous enum
Enumerator
MFF_WSP_T_ON 
MFF_WSP_T_OFF 
MFF_WSP_INC 
MFF_PC_DEC 
MFF_PC_T_ON 
MFF_PC_T_OFF 
MFF_PC_INC 

Definition at line 660 of file skge.h.

660  {
661  MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
662  MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
663  MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
664  MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
665  MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
666  MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
667  MFF_PC_INC = 1<<0, /* Packet Counter Increment */
668 };

◆ anonymous enum

anonymous enum
Enumerator
MFF_WP_T_ON 
MFF_WP_T_OFF 
MFF_WP_INC 
MFF_RP_T_ON 
MFF_RP_T_OFF 
MFF_RP_DEC 

Definition at line 672 of file skge.h.

672  {
673  MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
674  MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
675  MFF_WP_INC = 1<<4, /* Write Pointer Increm */
676 
677  MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
678  MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
679  MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
680 };

◆ anonymous enum

anonymous enum
Enumerator
MFF_ENA_OP_MD 
MFF_DIS_OP_MD 
MFF_RST_CLR 
MFF_RST_SET 

Definition at line 684 of file skge.h.

684  {
685  MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
686  MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
687  MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
688  MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
689 };

◆ anonymous enum

anonymous enum
Enumerator
LED_START 
LED_STOP 
LED_STATE 

Definition at line 697 of file skge.h.

697  {
698  LED_START = 1<<2, /* Start Timer */
699  LED_STOP = 1<<1, /* Stop Timer */
700  LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
701 };
LED_STOP
Definition: skge.h:699

◆ anonymous enum

anonymous enum
Enumerator
LED_T_ON 
LED_T_OFF 
LED_T_STEP 

Definition at line 706 of file skge.h.

706  {
707  LED_T_ON = 1<<2, /* LED Counter Test mode On */
708  LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
709  LED_T_STEP = 1<<0, /* LED Counter Step */
710 };
LED_T_ON
Definition: skge.h:707

◆ anonymous enum

anonymous enum
Enumerator
LED_BLK_ON 
LED_BLK_OFF 
LED_SYNC_ON 
LED_SYNC_OFF 
LED_ON 
LED_OFF 

Definition at line 713 of file skge.h.

713  {
714  LED_BLK_ON = 1<<5, /* Link LED Blinking On */
715  LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
716  LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
717  LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
718  LED_ON = 1<<1, /* switch LED on */
719  LED_OFF = 1<<0, /* switch LED off */
720 };
LED_OFF
Definition: skge.h:719
LED_ON
Definition: skge.h:718

◆ anonymous enum

anonymous enum
Enumerator
RX_GMF_EA 
RX_GMF_AF_THR 
RX_GMF_CTRL_T 
RX_GMF_FL_MSK 
RX_GMF_FL_THR 
RX_GMF_WP 
RX_GMF_WLEV 
RX_GMF_RP 
RX_GMF_RLEV 

Definition at line 723 of file skge.h.

723  {
724  RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
725  RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
726  RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
727  RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
728  RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
729  RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
730  RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
731  RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
732  RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
733 };

◆ anonymous enum

anonymous enum
Enumerator
TXA_INT_T_ON 
TXA_INT_T_OFF 
TXA_INT_T_STEP 
TXA_LIM_T_ON 
TXA_LIM_T_OFF 
TXA_LIM_T_STEP 

Definition at line 737 of file skge.h.

737  {
738  TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
739  TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
740  TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
741  TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
742  TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
743  TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
744 };

◆ anonymous enum

anonymous enum
Enumerator
TXA_PRIO_XS 

Definition at line 747 of file skge.h.

747  {
748  TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
749 };

◆ anonymous enum

anonymous enum
Enumerator
CSR_SV_IDLE 
CSR_DESC_CLR 
CSR_DESC_SET 
CSR_FIFO_CLR 
CSR_FIFO_SET 
CSR_HPI_RUN 
CSR_HPI_RST 
CSR_SV_RUN 
CSR_SV_RST 
CSR_DREAD_RUN 
CSR_DREAD_RST 
CSR_DWRITE_RUN 
CSR_DWRITE_RST 
CSR_TRANS_RUN 
CSR_TRANS_RST 
CSR_ENA_POL 
CSR_DIS_POL 
CSR_STOP 
CSR_START 
CSR_IRQ_CL_P 
CSR_IRQ_CL_B 
CSR_IRQ_CL_F 
CSR_IRQ_CL_C 

Definition at line 763 of file skge.h.

763  {
764  CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
765 
766  CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
767  CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
768  CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
769  CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
770  CSR_HPI_RUN = 1<<17, /* Release HPI SM */
771  CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
772  CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
773  CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
774  CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
775  CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
776  CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
777  CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
778  CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
779  CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
780  CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
781  CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
782  CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
783  CSR_START = 1<<4, /* Start Rx/Tx Queue */
784  CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
785  CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
786  CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
787  CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
788 };
CSR_STOP
Definition: skge.h:782

◆ anonymous enum

anonymous enum
Enumerator
F_ALM_FULL 
F_EMPTY 
F_FIFO_EOF 
F_WM_REACHED 
F_FIFO_LEVEL 
F_WATER_MARK 

Definition at line 798 of file skge.h.

798  {
799  F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
800  F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
801  F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
802  F_WM_REACHED = 1<<25, /* Watermark reached */
803 
804  F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
805  F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
806 };
F_EMPTY
Definition: skge.h:800

◆ anonymous enum

anonymous enum
Enumerator
RB_ENA_STFWD 
RB_DIS_STFWD 
RB_ENA_OP_MD 
RB_DIS_OP_MD 
RB_RST_CLR 
RB_RST_SET 

Definition at line 825 of file skge.h.

825  {
826  RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
827  RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
828  RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
829  RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
830  RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
831  RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
832 };

◆ anonymous enum

anonymous enum
Enumerator
TX_MFF_EA 
TX_MFF_WP 
TX_MFF_WSP 
TX_MFF_RP 
TX_MFF_PC 
TX_MFF_LEV 
TX_MFF_CTRL1 
TX_MFF_WAF 
TX_MFF_CTRL2 
TX_MFF_TST1 
TX_MFF_TST2 
TX_LED_INI 
TX_LED_VAL 
TX_LED_CTRL 
TX_LED_TST 

Definition at line 835 of file skge.h.

835  {
836  TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
837  TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
838  TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
839  TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
840  TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
841  TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
842  TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
843  TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
844 
845  TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
846  TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
847  TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
848 
849  TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
850  TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
851  TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
852  TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
853 };

◆ anonymous enum

anonymous enum
Enumerator
TX_GMF_EA 
TX_GMF_AE_THR 
TX_GMF_CTRL_T 
TX_GMF_WP 
TX_GMF_WSP 
TX_GMF_WLEV 
TX_GMF_RP 
TX_GMF_RSTP 
TX_GMF_RLEV 
B28_DPT_INI 
B28_DPT_VAL 
B28_DPT_CTRL 
B28_DPT_TST 
GMAC_TI_ST_VAL 
GMAC_TI_ST_CTRL 
GMAC_TI_ST_TST 

Definition at line 870 of file skge.h.

870  {
871  TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
872  TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
873  TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
874 
875  TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
876  TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
877  TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
878 
879  TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
880  TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
881  TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
882 
883  /* Descriptor Poll Timer Registers */
884  B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
885  B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
886  B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
887 
888  B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
889 
890  /* Time Stamp Timer Registers (YUKON only) */
891  GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
892  GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
893  GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
894 };

◆ anonymous enum

anonymous enum
Enumerator
LINKLED_OFF 
LINKLED_ON 
LINKLED_LINKSYNC_OFF 
LINKLED_LINKSYNC_ON 
LINKLED_BLINK_OFF 
LINKLED_BLINK_ON 

Definition at line 897 of file skge.h.

897  {
898  LINKLED_OFF = 0x01,
899  LINKLED_ON = 0x02,
900  LINKLED_LINKSYNC_OFF = 0x04,
901  LINKLED_LINKSYNC_ON = 0x08,
902  LINKLED_BLINK_OFF = 0x10,
903  LINKLED_BLINK_ON = 0x20,
904 };

◆ anonymous enum

anonymous enum
Enumerator
GMAC_CTRL 
GPHY_CTRL 
GMAC_IRQ_SRC 
GMAC_IRQ_MSK 
GMAC_LINK_CTRL 
WOL_REG_OFFS 
WOL_CTRL_STAT 
WOL_MATCH_CTL 
WOL_MATCH_RES 
WOL_MAC_ADDR 
WOL_PATT_RPTR 
WOL_PATT_LEN_LO 
WOL_PATT_LEN_HI 
WOL_PATT_CNT_0 
WOL_PATT_CNT_4 

Definition at line 907 of file skge.h.

907  {
908  GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
909  GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
910  GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
911  GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
912  GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
913 
914 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
915 
916  WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
917 
918  WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
919  WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
920  WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
921  WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
922  WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
923 
924 /* WOL Pattern Length Registers (YUKON only) */
925 
926  WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
927  WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
928 
929 /* WOL Pattern Counter Registers (YUKON only) */
930 
931  WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
932  WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
933 };

◆ anonymous enum

anonymous enum
Enumerator
WOL_PATT_RAM_1 
WOL_PATT_RAM_2 

Definition at line 936 of file skge.h.

936  {
937  WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
938  WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
939 };

◆ anonymous enum

anonymous enum
Enumerator
BASE_XMAC_1 
BASE_GMAC_1 
BASE_XMAC_2 
BASE_GMAC_2 

Definition at line 942 of file skge.h.

942  {
943  BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
944  BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
945  BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
946  BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
947 };

◆ anonymous enum

anonymous enum
Enumerator
XMR_FS_LEN 
XMR_FS_LEN_SHIFT 
XMR_FS_2L_VLAN 
XMR_FS_1_VLAN 
XMR_FS_BC 
XMR_FS_MC 
XMR_FS_UC 
XMR_FS_BURST 
XMR_FS_CEX_ERR 
XMR_FS_802_3 
XMR_FS_COL_ERR 
XMR_FS_CAR_ERR 
XMR_FS_LEN_ERR 
XMR_FS_FRA_ERR 
XMR_FS_RUNT 
XMR_FS_LNG_ERR 
XMR_FS_FCS_ERR 
XMR_FS_ERR 
XMR_FS_MCTRL 

Definition at line 952 of file skge.h.

952  {
953  XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
954  XMR_FS_LEN_SHIFT = 18,
955  XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
956  XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
957  XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
958  XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
959  XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
960 
961  XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
962  XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
963  XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
964  XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
965  XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
966  XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
967  XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
968  XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
969  XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
970  XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
971  XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
972  XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
973 
974 /*
975  * XMR_FS_ERR will be set if
976  * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
977  * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
978  * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
979  * XMR_FS_ERR unless the corresponding bit in the Receive Command
980  * Register is set.
981  */
982 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_XMAC_CTRL 
PHY_XMAC_STAT 
PHY_XMAC_ID0 
PHY_XMAC_ID1 
PHY_XMAC_AUNE_ADV 
PHY_XMAC_AUNE_LP 
PHY_XMAC_AUNE_EXP 
PHY_XMAC_NEPG 
PHY_XMAC_NEPG_LP 
PHY_XMAC_EXT_STAT 
PHY_XMAC_RES_ABI 

Definition at line 987 of file skge.h.

987  {
988  PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
989  PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
990  PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
991  PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
992  PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
993  PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
994  PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
995  PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
996  PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
997 
998  PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
999  PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
1000 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_BCOM_CTRL 
PHY_BCOM_STAT 
PHY_BCOM_ID0 
PHY_BCOM_ID1 
PHY_BCOM_AUNE_ADV 
PHY_BCOM_AUNE_LP 
PHY_BCOM_AUNE_EXP 
PHY_BCOM_NEPG 
PHY_BCOM_NEPG_LP 
PHY_BCOM_1000T_CTRL 
PHY_BCOM_1000T_STAT 
PHY_BCOM_EXT_STAT 
PHY_BCOM_P_EXT_CTRL 
PHY_BCOM_P_EXT_STAT 
PHY_BCOM_RE_CTR 
PHY_BCOM_FC_CTR 
PHY_BCOM_RNO_CTR 
PHY_BCOM_AUX_CTRL 
PHY_BCOM_AUX_STAT 
PHY_BCOM_INT_STAT 
PHY_BCOM_INT_MASK 

Definition at line 1004 of file skge.h.

1004  {
1005  PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1006  PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1007  PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1008  PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1009  PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1010  PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1011  PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1012  PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1013  PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1014  /* Broadcom-specific registers */
1015  PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1016  PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1017  PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1018  PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1019  PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1020  PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1021  PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1022  PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1023 
1024  PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1025  PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1026  PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1027  PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1028 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_MARV_CTRL 
PHY_MARV_STAT 
PHY_MARV_ID0 
PHY_MARV_ID1 
PHY_MARV_AUNE_ADV 
PHY_MARV_AUNE_LP 
PHY_MARV_AUNE_EXP 
PHY_MARV_NEPG 
PHY_MARV_NEPG_LP 
PHY_MARV_1000T_CTRL 
PHY_MARV_1000T_STAT 
PHY_MARV_EXT_STAT 
PHY_MARV_PHY_CTRL 
PHY_MARV_PHY_STAT 
PHY_MARV_INT_MASK 
PHY_MARV_INT_STAT 
PHY_MARV_EXT_CTRL 
PHY_MARV_RXE_CNT 
PHY_MARV_EXT_ADR 
PHY_MARV_PORT_IRQ 
PHY_MARV_LED_CTRL 
PHY_MARV_LED_OVER 
PHY_MARV_EXT_CTRL_2 
PHY_MARV_EXT_P_STAT 
PHY_MARV_CABLE_DIAG 
PHY_MARV_PAGE_ADDR 
PHY_MARV_PAGE_DATA 
PHY_MARV_FE_LED_PAR 
PHY_MARV_FE_LED_SER 
PHY_MARV_FE_VCT_TX 
PHY_MARV_FE_VCT_RX 
PHY_MARV_FE_SPEC_2 

Definition at line 1033 of file skge.h.

1033  {
1034  PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1035  PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1036  PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1037  PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1038  PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1039  PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1040  PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1041  PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1042  PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1043  /* Marvel-specific registers */
1044  PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1045  PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1046  PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1047  PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1048  PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1049  PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1050  PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1051  PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1052  PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1053  PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1054  PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1055  PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1056  PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1057  PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1058  PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1059  PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1060  PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1061  PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1062 
1063 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1064  PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1065  PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1066  PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1067  PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1068  PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1069 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_CT_RESET 
PHY_CT_LOOP 
PHY_CT_SPS_LSB 
PHY_CT_ANE 
PHY_CT_PDOWN 
PHY_CT_ISOL 
PHY_CT_RE_CFG 
PHY_CT_DUP_MD 
PHY_CT_COL_TST 
PHY_CT_SPS_MSB 

Definition at line 1071 of file skge.h.

1071  {
1072  PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1073  PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1074  PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1075  PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1076  PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1077  PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1078  PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1079  PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1080  PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1081  PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1082 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_CT_SP1000 
PHY_CT_SP100 
PHY_CT_SP10 

Definition at line 1084 of file skge.h.

1084  {
1085  PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1086  PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1087  PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1088 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_ST_EXT_ST 
PHY_ST_PRE_SUP 
PHY_ST_AN_OVER 
PHY_ST_REM_FLT 
PHY_ST_AN_CAP 
PHY_ST_LSYNC 
PHY_ST_JAB_DET 
PHY_ST_EXT_REG 

Definition at line 1090 of file skge.h.

1090  {
1091  PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1092 
1093  PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1094  PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1095  PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
1096  PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1097  PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1098  PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1099  PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1100 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_I1_OUI_MSK 
PHY_I1_MOD_NUM 
PHY_I1_REV_MSK 

Definition at line 1102 of file skge.h.

1102  {
1103  PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1104  PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1105  PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1106 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_BCOM_ID1_A1 
PHY_BCOM_ID1_B2 
PHY_BCOM_ID1_C0 
PHY_BCOM_ID1_C5 

Definition at line 1109 of file skge.h.

1109  {
1110  PHY_BCOM_ID1_A1 = 0x6041,
1111  PHY_BCOM_ID1_B2 = 0x6043,
1112  PHY_BCOM_ID1_C0 = 0x6044,
1113  PHY_BCOM_ID1_C5 = 0x6047,
1114 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_MARV_ID0_VAL 
PHY_MARV_ID1_B0 
PHY_MARV_ID1_B2 
PHY_MARV_ID1_C2 
PHY_MARV_ID1_Y2 

Definition at line 1117 of file skge.h.

1117  {
1118  PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1119  PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1120  PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1121  PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1122  PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1123 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_AN_NXT_PG 
PHY_AN_ACK 
PHY_AN_RF 
PHY_AN_PAUSE_ASYM 
PHY_AN_PAUSE_CAP 
PHY_AN_100BASE4 
PHY_AN_100FULL 
PHY_AN_100HALF 
PHY_AN_10FULL 
PHY_AN_10HALF 
PHY_AN_CSMA 
PHY_AN_SEL 
PHY_AN_FULL 
PHY_AN_ALL 

Definition at line 1126 of file skge.h.

1126  {
1127  PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1128  PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1129  PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1130 
1131  PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1132  PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1133  PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1134  PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1135  PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1136  PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1137  PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1138  PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1139  PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1140  PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1141  PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1142  PHY_AN_100HALF | PHY_AN_100FULL,
1143 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_X_AN_NXT_PG 
PHY_X_AN_ACK 
PHY_X_AN_RFB 
PHY_X_AN_PAUSE 
PHY_X_AN_HD 
PHY_X_AN_FD 

Definition at line 1146 of file skge.h.

1146  {
1147  PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1148  PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1149  PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1150 
1151  PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1152  PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1153  PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1154 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_X_P_NO_PAUSE 
PHY_X_P_SYM_MD 
PHY_X_P_ASYM_MD 
PHY_X_P_BOTH_MD 

Definition at line 1157 of file skge.h.

1157  {
1158  PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1159  PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1160  PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1161  PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1162 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_X_EX_FD 
PHY_X_EX_HD 

Definition at line 1166 of file skge.h.

1166  {
1167  PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1168  PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1169 };

◆ anonymous enum

anonymous enum
Enumerator
PHY_X_RS_PAUSE 
PHY_X_RS_HD 
PHY_X_RS_FD 
PHY_X_RS_ABLMIS 
PHY_X_RS_PAUMIS 

Definition at line 1172 of file skge.h.

1172  {
1173  PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1174  PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1175  PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1176  PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1177  PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1178 };

◆ anonymous enum

anonymous enum
Enumerator
X_RFB_OK 
X_RFB_LF 
X_RFB_OFF 
X_RFB_AN_ERR 

Definition at line 1181 of file skge.h.

1181  {
1182  X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1183  X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
1184  X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1185  X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1186 };

◆ anonymous enum

anonymous enum
</
Enumerator
PHY_B_1000C_TEST 
PHY_B_1000C_MSE 
PHY_B_1000C_MSC 
PHY_B_1000C_RD 
PHY_B_1000C_AFD 
PHY_B_1000C_AHD