iPXE
vxge_traffic.h
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1 /*
2  * vxge-traffic.h: iPXE driver for Neterion Inc's X3100 Series 10GbE
3  * PCIe I/O Virtualized Server Adapter.
4  *
5  * Copyright(c) 2002-2010 Neterion Inc.
6  *
7  * This software may be used and distributed according to the terms of
8  * the GNU General Public License (GPL), incorporated herein by
9  * reference. Drivers based on or derived from this code fall under
10  * the GPL and must retain the authorship, copyright and license
11  * notice.
12  *
13  */
14 
15 FILE_LICENCE(GPL2_ONLY);
16 
17 #ifndef VXGE_TRAFFIC_H
18 #define VXGE_TRAFFIC_H
19 
20 #include <stdint.h>
21 #include <ipxe/if_ether.h>
22 #include <ipxe/iobuf.h>
23 
24 #include "vxge_reg.h"
25 #include "vxge_version.h"
26 
27 #define VXGE_HW_DTR_MAX_T_CODE 16
28 #define VXGE_HW_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL
29 #define VXGE_HW_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL
30 #define VXGE_HW_MAX_VIRTUAL_PATHS 17
31 
32 #define VXGE_HW_MAX_VIRTUAL_FUNCTIONS 8
33 
34 #define VXGE_HW_MAC_MAX_MAC_PORT_ID 3
35 
36 #define VXGE_HW_DEFAULT_32 0xffffffff
37 /* frames sizes */
38 #define VXGE_HW_HEADER_802_2_SIZE 3
39 #define VXGE_HW_HEADER_SNAP_SIZE 5
40 #define VXGE_HW_HEADER_VLAN_SIZE 4
41 #define VXGE_HW_MAC_HEADER_MAX_SIZE \
42  (ETH_HLEN + \
43  VXGE_HW_HEADER_802_2_SIZE + \
44  VXGE_HW_HEADER_VLAN_SIZE + \
45  VXGE_HW_HEADER_SNAP_SIZE)
46 
47 /* 32bit alignments */
48 
49 /* A receive data corruption can occur resulting in either a single-bit or
50 double-bit ECC error being flagged in the ASIC if the starting offset of a
51 buffer in single buffer mode is 0x2 to 0xa. The single bit ECC error will not
52 lock up the card but can hide the data corruption while the double-bit ECC
53 error will lock up the card. Limiting the starting offset of the buffers to
54 0x0, 0x1 or to a value greater than 0xF will workaround this issue.
55 VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
56 buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
57 aligned. The start of buffer of 0x2 will cause this problem to occur. To
58 avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start of
59 buffer is outside of the problem causing offsets.
60 */
61 #define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN 0x12
62 #define VXGE_HW_HEADER_802_2_SNAP_ALIGN 2
63 #define VXGE_HW_HEADER_802_2_ALIGN 3
64 #define VXGE_HW_HEADER_SNAP_ALIGN 1
65 
66 #define VXGE_HW_L3_CKSUM_OK 0xFFFF
67 #define VXGE_HW_L4_CKSUM_OK 0xFFFF
68 
69 /* Forward declarations */
70 struct __vxge_hw_device;
72 struct __vxge_hw_fifo;
73 struct __vxge_hw_ring;
74 struct vxge_hw_ring_rxd_1;
75 struct vxge_hw_fifo_txd;
76 
77 #ifndef TRUE
78 #define TRUE 1
79 #endif
80 
81 #ifndef FALSE
82 #define FALSE 0
83 #endif
84 
85 /*VXGE_HW_STATUS_H*/
86 #define VXGE_HW_EVENT_BASE 0
87 #define VXGE_LL_EVENT_BASE 100
88 
89 /**
90  * enum vxge_hw_event- Enumerates slow-path HW events.
91  * @VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event.
92  * @VXGE_HW_EVENT_SERR: Serious vpath hardware error event.
93  * @VXGE_HW_EVENT_ECCERR: vpath ECC error event.
94  * @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath
95  * @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error.
96  * @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event.
97  * @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event.
98  * @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event.
99  * @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset
100  * @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed
101  * @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
102  * slot-freeze from the rest critical events (e.g. ECC) when it is
103  * impossible to PIO read "through" the bus, i.e. when getting all-foxes.
104  *
105  * enum vxge_hw_event enumerates slow-path HW eventis.
106  *
107  * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
108  * vxge_uld_link_down_f{}.
109  */
112  /* HW events */
127 };
128 
129 #define VXGE_HW_MAX_INTR_PER_VP 4
130 #define VXGE_HW_VPATH_INTR_TX 0
131 #define VXGE_HW_VPATH_INTR_RX 1
132 #define VXGE_HW_VPATH_INTR_EINTA 2
133 #define VXGE_HW_VPATH_INTR_BMAP 3
134 
135 #define VXGE_HW_BLOCK_SIZE 4096
136 
137 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17
138 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18
139 #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19
140 #define VXGE_HW_TIM_UTIL_SEL_PER_VPATH 63
141 
142 /**
143  * enum vxge_hw_ring_tcode - Transfer codes returned by adapter
144  * @VXGE_HW_RING_T_CODE_OK: Transfer ok.
145  * @VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation
146  * configuration mismatch.
147  * @VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation
148  * configuration mismatch.
149  * @VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum
150  * presentation configuration mismatch.
151  * @VXGE_HW_RING_T_CODE_L3_PKT_ERR: Layer 3 error unparseable packet,
152  * such as unknown IPv6 header.
153  * @VXGE_HW_RING_T_CODE_L2_FRM_ERR: Layer 2 error frame integrity
154  * error, such as FCS or ECC).
155  * @VXGE_HW_RING_T_CODE_BUF_SIZE_ERR: Buffer size error the RxD buffer(
156  * s) were not appropriately sized and data loss occurred.
157  * @VXGE_HW_RING_T_CODE_INT_ECC_ERR: Internal ECC error RxD corrupted.
158  * @VXGE_HW_RING_T_CODE_BENIGN_OVFLOW: Benign overflow the contents of
159  * Segment1 exceeded the capacity of Buffer1 and the remainder
160  * was placed in Buffer2. Segment2 now starts in Buffer3.
161  * No data loss or errors occurred.
162  * @VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0 one of the RxDs
163  * assigned buffers has a size of 0 bytes.
164  * @VXGE_HW_RING_T_CODE_FRM_DROP: Frame dropped either due to
165  * VPath Reset or because of a VPIN mismatch.
166  * @VXGE_HW_RING_T_CODE_UNUSED: Unused
167  * @VXGE_HW_RING_T_CODE_MULTI_ERR: Multiple errors more than one
168  * transfer code condition occurred.
169  *
170  * Transfer codes returned by adapter.
171  */
186 };
187 
188 
189 /**
190  * enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD
191  * @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL
192  * @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL
193  * @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL
194  * @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.
195  *
196  * These gather codes are used to indicate the position of a TxD in a TxD list
197  */
203 };
204 
205 /**
206  * enum enum vxge_hw_fifo_tcode - tcodes used in fifo
207  * @VXGE_HW_FIFO_T_CODE_OK: Transfer OK
208  * @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or
209  * frame data) returned with corrupt data.
210  * @VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned
211  * with no data.
212  * @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a
213  * frame or LSO MSS that was too long (>9800B).
214  * @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send
215  * Offload operation, due to improper header template,
216  * unsupported protocol, etc.
217  * @VXGE_HW_FIFO_T_CODE_UNUSED: Unused
218  * @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple
219  * data buffer transfer errors are encountered (see below).
220  * Otherwise it is set to 0.
221  *
222  * These tcodes are returned in various API for TxD status
223  */
232 };
233 
234 enum vxge_hw_status
236 
237 void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring_handle,
238  struct vxge_hw_ring_rxd_1 *rxdp);
239 
241  struct vxge_hw_fifo_txd *txdp,
242  struct io_buffer *iob);
243 
244 void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo,
245  struct vxge_hw_fifo_txd *txdp);
246 
248  struct __vxge_hw_virtualpath *vpath,
249  struct __vxge_hw_ring *ring);
250 
252  struct __vxge_hw_ring *ringh);
253 
255  struct __vxge_hw_virtualpath *vpath,
256  struct __vxge_hw_fifo *fifo);
257 
258 enum vxge_hw_status
260 
262  struct __vxge_hw_device *devh, u32 vp_id);
263 
264 enum vxge_hw_status
265 __vxge_hw_vpath_enable(struct __vxge_hw_device *devh, u32 vp_id);
266 
267 void
269 
270 enum vxge_hw_status
272 
273 enum vxge_hw_status
275 
276 enum vxge_hw_status
278 
279 enum vxge_hw_status
280 __vxge_hw_vpath_initialize(struct __vxge_hw_device *devh, u32 vp_id);
281 
283  struct __vxge_hw_device *hldev, u32 vp_id,
284  struct __vxge_hw_virtualpath *vpath);
285 
286 void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev,
287  struct __vxge_hw_virtualpath *vpath);
288 
289 enum vxge_hw_status
291 
292 void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev);
293 
295 
296 void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev);
297 
298 void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev);
299 
300 void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ringh);
301 
303 
305 
306 struct vxge_hw_fifo_txd *
308 
309 #endif
enum vxge_hw_status vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
Definition: vxge_config.c:557
enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_fifo *fifo)
Definition: vxge_config.c:844
struct vxge_hw_fifo_txd - Transmit Descriptor
Definition: vxge_config.h:212
void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp)
vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
Definition: vxge_traffic.c:399
enum vxge_hw_status __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id, struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1595
I/O buffers.
void __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev)
Definition: vxge_config.c:1290
vxge_hw_event
enum vxge_hw_event- Enumerates slow-path HW events.
Definition: vxge_traffic.h:110
enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_ring *ringh)
Definition: vxge_config.c:658
void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ringh)
vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.
Definition: vxge_traffic.c:607
enum vxge_hw_status __vxge_hw_vpath_initialize(struct __vxge_hw_device *devh, u32 vp_id)
Definition: vxge_config.c:1514
void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
vxge_hw_device_unmask_all - Unmask all device interrupts.
Definition: vxge_traffic.c:231
void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp, struct io_buffer *iob)
vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.
Definition: vxge_traffic.c:374
enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo)
vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.
Definition: vxge_traffic.c:722
enum vxge_hw_status __vxge_hw_vpath_enable(struct __vxge_hw_device *devh, u32 vp_id)
void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
vxge_hw_device_mask_all - Mask all device interrupts.
Definition: vxge_traffic.c:210
enum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev)
vxge_hw_device_begin_irq - Begin IRQ processing.
Definition: vxge_traffic.c:554
struct vxge_hw_fifo_txd * vxge_hw_fifo_free_txdl_get(struct __vxge_hw_fifo *fifo)
vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo
Definition: vxge_traffic.c:354
enum vxge_hw_status __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *devh, u32 vp_id)
Definition: vxge_config.c:1334
enum vxge_hw_status __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *devh)
Definition: vxge_config.c:1398
enum vxge_hw_status __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *devh, u32 vp_id)
Definition: vxge_config.c:1428
Definition: sis900.h:30
vxge_hw_fifo_gather_code
enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD @VXGE_HW_FIFO_GATHER_CODE_FIRST: F...
Definition: vxge_traffic.h:198
struct __vxge_hw_device - Hal device object @magic: Magic Number @bar0: BAR0 virtual address.
Definition: vxge_config.h:477
void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
vxge_hw_device_intr_enable - Enable interrupts.
Definition: vxge_traffic.c:250
FILE_LICENCE(GPL2_ONLY)
vxge_hw_ring_tcode
enum vxge_hw_ring_tcode - Transfer codes returned by adapter @VXGE_HW_RING_T_CODE_OK: Transfer ok.
Definition: vxge_traffic.h:172
enum vxge_hw_status __vxge_hw_vpath_reset(struct __vxge_hw_device *devh, u32 vp_id)
Definition: vxge_config.c:1269
vxge_hw_status
Definition: vxge_config.h:70
Definition: sis900.h:32
enum vxge_hw_status __vxge_hw_ring_create(struct __vxge_hw_virtualpath *vpath, struct __vxge_hw_ring *ring)
Definition: vxge_config.c:615
void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring_handle, struct vxge_hw_ring_rxd_1 *rxdp)
enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ringh)
Definition: vxge_traffic.c:641
void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
vxge_hw_device_intr_disable - Disable Titan interrupts.
Definition: vxge_traffic.c:295
#define VXGE_HW_EVENT_BASE
Definition: vxge_traffic.h:86
struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
Definition: vxge_config.h:154
uint32_t u32
Definition: stdint.h:23
vxge_hw_fifo_tcode
enum enum vxge_hw_fifo_tcode - tcodes used in fifo @VXGE_HW_FIFO_T_CODE_OK: Transfer OK @VXGE_HW_FIFO...
Definition: vxge_traffic.h:224
void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1641
A persistent I/O buffer.
Definition: iobuf.h:32
enum vxge_hw_status __vxge_hw_fifo_create(struct __vxge_hw_virtualpath *vpath, struct __vxge_hw_fifo *fifo)
Definition: vxge_config.c:813