168 }
while (++i <= max_millis);
228 val64 =
readq(&legacy_reg->toc_first_pointer);
273 (hldev->
bar0 + val64);
286 (hldev->
bar0 + val64);
340 return access_rights;
402 if (legacy_reg ==
NULL) {
476 hw_info->mac_addrs[i],
477 hw_info->mac_addr_masks[i]);
525 "failed\n", __func__, __LINE__);
575 if (!ring->
iobuf[i]) {
593 rxd->control_0 =
rxd->control_1 = 0;
601 block->reserved_2_pNext_RxD_block = (
unsigned long)
block;
624 hldev = vpath->
hldev;
625 vp_id = vpath->
vp_id;
743 #if (__BYTE_ORDER != __BIG_ENDIAN) 909 val64 =
readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
922 writeq(0, &vpath_reg->rts_access_steer_ctrl);
924 writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0);
925 writeq(0, &vpath_reg->rts_access_steer_data1);
959 &vpath_reg->rts_access_steer_ctrl,
966 val64 =
readq(&vpath_reg->rts_access_steer_ctrl);
969 data1 =
readq(&vpath_reg->rts_access_steer_data0);
972 data2 =
readq(&vpath_reg->rts_access_steer_data1);
989 &vpath_reg->rts_access_steer_ctrl,
996 val64 =
readq(&vpath_reg->rts_access_steer_ctrl);
1000 data1 =
readq(&vpath_reg->rts_access_steer_data0);
1003 data2 =
readq(&vpath_reg->rts_access_steer_data1);
1026 &vpath_reg->rts_access_steer_ctrl,
1033 val64 =
readq(&vpath_reg->rts_access_steer_ctrl);
1037 data1 =
readq(&vpath_reg->rts_access_steer_data0);
1040 data2 =
readq(&vpath_reg->rts_access_steer_data1);
1077 &vpath_reg->rts_access_steer_ctrl,
1084 val64 =
readq(&vpath_reg->rts_access_steer_ctrl);
1088 data1 =
readq(&vpath_reg->rts_access_steer_data0);
1089 data2 =
readq(&vpath_reg->rts_access_steer_data1);
1124 flash_version->
major =
1126 flash_version->
minor =
1128 flash_version->
build =
1133 flash_version->
build);
1188 macaddr[i-1] = (
u8)(
data1 & 0xFF);
1191 macaddr_mask[i-1] = (
u8)(
data2 & 0xFF);
1215 u32 i,
mtu = 0, max_pyld = 0;
1258 1 << (16 - vpath->
vp_id)),
1374 #if (__BYTE_ORDER != __BIG_ENDIAN) 1386 (hldev->
kdfc + (vp_id *
1607 vpath->
vp_id = vp_id;
1609 vpath->
hldev = hldev;
1701 goto vpath_open_exit1;
1706 goto vpath_open_exit1;
1710 goto vpath_open_exit2;
1714 goto vpath_open_exit3;
1739 u64 new_count, val64;
1745 new_count &= 0x1fff;
1768 devh = vpath->
hldev;
1772 goto vpath_close_exit;
1800 vp_id = vpath->
vp_id;
1826 vp_id = vpath->
vp_id;
1827 hldev = vpath->
hldev;
1861 hldev = vpath->
hldev;
1864 1 << (16 - vpath->
vp_id));
#define VXGE_HW_FIFO_TXD_DEPTH
#define VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(val)
#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val)
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits)
u64 kdfc_trpl_fifo_0_wb_address
u64 toc_vpmgmt_pointer[17]
u64 pci_config_access_status
struct vxge_hw_device_date fw_date
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits)
struct __vxge_hw_virtualpath * vpathh
struct vxge_hw_device_date flash_date
void vxge_hw_vpath_enable(struct __vxge_hw_virtualpath *vpath)
#define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY
struct vxge_hw_legacy_reg * legacy_reg
#define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1
static unsigned int unsigned int reg
struct vxge_hw_fifo_txd - Transmit Descriptor
#define VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(val)
static struct vxge_hw_legacy_reg __iomem * __vxge_hw_device_get_legacy_reg(struct pci_device *pdev, void __iomem *bar0)
#define VXGE_HW_NO_MR_SR_VH0_FUNCTION0
u64 toc_vpath_pointer[17]
struct vxge_hw_device_version fw_version
void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
char date[VXGE_HW_FW_STRLEN]
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits)
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
struct __vxge_hw_virtualpath * vpathh
#define VXGE_HW_FW_STRLEN
struct vxge_hw_device_date - Date Format @day: Day @month: Month @year: Year
#define VXGE_HW_VPATH_INTR_EINTA
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(val)
#define VXGE_HW_PRC_CFG6_RXD_CRXDT(val)
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits)
enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_ring *ring)
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
struct vxge_hw_toc_reg __iomem * __vxge_hw_device_toc_get(void __iomem *bar0, struct vxge_hw_legacy_reg __iomem *legacy_reg)
struct __vxge_hw_virtualpath virtual_path
#define VXGE_HW_PRC_CFG4_RING_MODE(val)
struct vxge_hw_common_reg * common_reg
void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring __unused, struct vxge_hw_ring_rxd_1 *rxdp)
vxge_hw_ring_rxd_post - Post descriptor on the ring.
#define VXGE_HW_DEVICE_DEAD
enum vxge_hw_status __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
#define VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
struct __vxge_hw_non_offload_db_wrapper * nofl_db
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(val)
#define VXGE_HW_SWAPPER_BYTE_SWAPPED
#define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM
enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_virtualpath *vpath)
#define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val)
static void *__malloc malloc_phys(size_t size, size_t phys_align)
Allocate memory with specified physical alignment.
u64 host_type_assignments
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA
#define PCI_BASE_ADDRESS_0
#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(val)
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val)
#define PCI_COMMAND
PCI command.
#define VXGE_HW_SWAPPER_BIT_FLIPPED
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS
#define VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE
enum vxge_hw_status __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits)
enum vxge_hw_status __vxge_hw_vpath_card_info_get(struct vxge_hw_vpath_reg __iomem *vpath_reg, struct vxge_hw_device_hw_info *hw_info)
#define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION
#define VXGE_HW_INTR_MASK_ALL
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
#define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i)
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits)
enum vxge_hw_status vxge_hw_set_fw_api(struct __vxge_hw_device *hldev, u64 vp_id, u32 action, u32 offset, u64 data0, u64 data1)
#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(val)
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY
enum vxge_hw_status __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev)
u64 kdfc_fifo_trpl_partition
#define VXGE_HW_VPATH_INTR_RX
#define vxge_debug(mask, fmt...)
#define VXGE_HW_PRC_CFG5_RXD0_ADD(val)
Dynamic memory allocation.
struct vxge_hw_device_hw_info - Device information @host_type: Host Type @func_id: Function Id @vpath...
static enum vxge_hw_status __vxge_hw_vpath_mgmt_read(struct __vxge_hw_virtualpath *vpath)
enum vxge_hw_status __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
#define VXGE_TTI_BTIMER_VAL
enum vxge_hw_status __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
enum vxge_hw_status __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg, struct vxge_hw_vpath_reg __iomem *vpath_reg)
#define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE
#define VXGE_HW_MAC_MAX_MAC_PORT_ID
#define VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE
#define VXGE_HW_TITAN_SRPCIM_REG_SPACES
struct vxge_hw_vpath_reg * vp_reg
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits)
#define VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK
#define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val)
enum vxge_hw_status __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
#define VXGE_HW_MAX_INTR_PER_VP
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
enum vxge_hw_status vxge_hw_device_initialize(struct __vxge_hw_device **devh, void *bar0, struct pci_device *pdev, u8 titan1)
#define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits)
#define VXGE_HW_MAX_PAYLOAD_SIZE_512
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits)
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(val)
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE
#define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits)
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0
struct io_buffer * iobuf[VXGE_HW_RING_BUF_PER_BLOCK+1]
void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
#define VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE
u8 serial_number[VXGE_HW_INFO_LEN]
#define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val)
#define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val)
struct vxge_hw_common_reg * common_reg
#define VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN
#define VXGE_HW_PRC_CFG4_RTH_DISABLE
u64 rxmac_cfg0_port_vpmgmt_clone[3]
#define VXGE_HW_MAX_VIRTUAL_PATHS
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
enum vxge_hw_status vxge_hw_get_func_mode(struct __vxge_hw_device *hldev, u32 *func_mode)
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits)
u64 rts_access_steer_data0
#define VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(val)
#define VXGE_HW_DEF_DEVICE_POLL_MILLIS
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY
#define VXGE_HW_TITAN_VPATH_REG_SPACES
#define VXGE_HW_VPATH_INTR_BMAP
u64 xmac_vsport_choices_vp
struct __vxge_hw_ring_block * rxdl
struct vxge_hw_device_version flash_version
enum vxge_hw_status vxge_hw_vpath_recover_from_reset(struct __vxge_hw_virtualpath *vpath)
#define VXGE_HW_MAC_HEADER_MAX_SIZE
#define VXGE_HW_RING_RXD_QWORDS_MODE_1
#define VXGE_LL_MAX_FRAME_SIZE(dev)
#define VXGE_HW_PCI_EXP_DEVCTL_READRQ
#define VXGE_HW_TITAN_VPMGMT_REG_SPACES
#define be64_to_cpu(value)
static void(* free)(struct refcnt *refcnt))
u64 rts_access_steer_ctrl
void * zalloc(size_t size)
Allocate cleared memory.
u64 xgmac_gen_status_vpmgmt_clone
#define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i)
#define vxge_bVALn(bits, loc, n)
#define VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ
u64 kdfc_trpl_fifo_0_ctrl
#define VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE
#define VXGE_HW_TIM_PCI_CFG_ADD_PAD
#define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits)
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER
enum vxge_hw_status vxge_hw_device_hw_info_get(struct pci_device *pdev, void __iomem *bar0, struct vxge_hw_device_hw_info *hw_info)
vxge_hw_device_hw_info_get - Get the hw information Returns the vpath mask that has the bits set for ...
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits)
#define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls)
#define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL
enum vxge_hw_status vxge_hw_vpath_mtu_set(struct __vxge_hw_virtualpath *vpath, u32 new_mtu)
#define VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(val)
#define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC
u64 pci_config_access_cfg1
u8 product_desc[VXGE_HW_INFO_LEN]
static enum vxge_hw_status __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr, u64 mask, u32 max_millis)
void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_virtualpath *vpath)
struct vxge_hw_vpath_reg * vpath_reg[VXGE_HW_TITAN_VPATH_REG_SPACES]
u64 xgmac_gen_fw_memo_mask
#define VXGE_HW_VPATH_INTR_TX
#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits)
enum vxge_hw_status __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
enum vxge_hw_status vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_fifo *fifo)
#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN
void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, struct __vxge_hw_virtualpath *vpath)
#define VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val)
#define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val)
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
#define VXGE_HW_SWAPPER_INITIAL_VALUE
struct vxge_hw_vpmgmt_reg * vpmgmt_reg[VXGE_HW_TITAN_VPMGMT_REG_SPACES]
u64 rts_access_steer_data1
#define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits)
u64 kdfc_drbl_triplet_total
enum vxge_hw_status __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id, struct __vxge_hw_virtualpath *vpath)
struct __vxge_hw_non_offload_db_wrapper * nofl_db
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN
struct __vxge_hw_device - Hal device object @magic: Magic Number @bar0: BAR0 virtual address.
#define VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val)
#define VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN
enum vxge_hw_status __vxge_hw_fifo_create(struct __vxge_hw_virtualpath *vpath, struct __vxge_hw_fifo *fifo)
#define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val)
u64 toc_kdfc_vpath_stride
u64 rxmac_cfg0_port_vpmgmt_clone[3]
struct vxge_hw_vpmgmt_reg * vpmgmt_reg
uint8_t block[3][8]
DES-encrypted blocks.
u8 part_number[VXGE_HW_INFO_LEN]
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY
#define VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(val)
#define VXGE_HW_SR_VH_VIRTUAL_FUNCTION
struct __vxge_hw_ring ringh
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits)
struct vxge_hw_vpath_reg * vp_reg
#define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION
#define VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0
#define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE
struct vxge_hw_toc_reg * toc_reg
#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS
#define VXGE_HW_SR_VH_FUNCTION0
static void vxge_hw_ring_rxd_1b_set(struct vxge_hw_ring_rxd_1 *rxdp, struct io_buffer *iob, u32 size)
vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
enum vxge_hw_status __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
#define VXGE_HW_MR_SR_VH0_INVALID_CONFIG
#define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0
#define VXGE_HW_VH_NORMAL_FUNCTION
#define VXGE_RTI_BTIMER_VAL
#define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION
u32 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
#define VXGE_HW_RING_BUF_PER_BLOCK
#define VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(val)
static u32 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
#define VXGE_HW_PRC_CFG4_IN_SVC
#define VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val)
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO
#define VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI
#define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(val)
struct vxge_hw_vpath_reg * vp_reg
enum vxge_hw_status __vxge_hw_vpath_addr_get(struct vxge_hw_vpath_reg *vpath_reg, u8(macaddr)[ETH_ALEN], u8(macaddr_mask)[ETH_ALEN])
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
enum vxge_hw_status __vxge_hw_vpath_fw_ver_get(struct vxge_hw_vpath_reg __iomem *vpath_reg, struct vxge_hw_device_hw_info *hw_info)
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER
static void free_phys(void *ptr, size_t size)
Free memory allocated with malloc_phys()
struct __vxge_hw_device * hldev
#define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE
#define VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(val)
uint16_t offset
Offset to command line.
enum vxge_hw_status __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
struct vxge_hw_mrpcim_reg * mrpcim_reg
#define VXGE_HW_RING_RXD_QWORD_LIMIT
#define VXGE_RTI_LTIMER_VAL
#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val)
#define VXGE_TTI_LTIMER_VAL
struct __vxge_hw_fifo fifoh
#define VXGE_HW_GET_FUNC_MODE_VAL(val)
#define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH
#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL
void vxge_hw_vpath_set_zero_rx_frm_len(struct __vxge_hw_device *hldev)
struct vxge_hw_fifo_txd * txdl
#define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE
#define VXGE_HW_VP_NOT_OPEN
#define VXGE_HW_PRC_CFG6_RXD_SPAT(val)
#define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val)
static void __vxge_hw_read_rts_ds(struct vxge_hw_vpath_reg __iomem *vpath_reg, u64 dta_struct_sel)
u64 toc_srpcim_pointer[17]
#define VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR
enum vxge_hw_status __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath, u32 phy_func_0, u32 offset, u32 *val)
#define VXGE_HW_TIM_RING_ASSN_INT_NUM(val)
void vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
u64 pci_config_access_cfg2
enum vxge_hw_status vxge_hw_vpath_open(struct __vxge_hw_device *hldev, struct vxge_vpath *vpath)
#define VXGE_HW_FW_API_GET_FUNC_MODE
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits)
enum vxge_hw_status __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
struct vxge_hw_ring_rxd_1 rxd[VXGE_HW_MAX_RXDS_PER_BLOCK_1]
#define VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED
#define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val)
enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_virtualpath *vpath)
#define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val)
enum vxge_hw_status vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
void __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev)
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val)
#define NULL
NULL pointer (VOID *)
#define VXGE_HW_DEVICE_MAGIC
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY
u64 rtdma_rd_optimization_ctrl
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits)
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
#define VXGE_HW_RING_RX_POLL_WEIGHT
enum vxge_hw_status __vxge_hw_ring_create(struct __vxge_hw_virtualpath *vpath, struct __vxge_hw_ring *ring)
enum vxge_hw_status __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
#define VXGE_HW_MAX_RXDS_PER_BLOCK_1
#define VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER
void * memset(void *dest, int character, size_t len) __nonnull
struct vxge_hw_srpcim_reg * srpcim_reg[VXGE_HW_TITAN_SRPCIM_REG_SPACES]
char version[VXGE_HW_FW_STRLEN]