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Data Structures | Macros | Functions | Variables
vxge_reg.h File Reference
#include <stdint.h>

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Data Structures

struct  vxge_hw_legacy_reg
 
struct  vxge_hw_toc_reg
 
struct  vxge_hw_common_reg
 
struct  vxge_hw_memrepair_reg
 
struct  vxge_hw_pcicfgmgmt_reg
 
struct  vxge_hw_mrpcim_reg
 
struct  vxge_hw_srpcim_reg
 
struct  vxge_hw_vpmgmt_reg
 
struct  vxge_hw_vpath_reg
 

Macros

#define VXGE_REG_H
 
#define vxge_mBIT(loc)   (0x8000000000000000ULL >> (loc))
 
#define vxge_vBIT(val, loc, sz)   (((u64)(val)) << (64-(loc)-(sz)))
 
#define vxge_vBIT32(val, loc, sz)   (((u32)(val)) << (32-(loc)-(sz)))
 
#define vxge_bVALn(bits, loc, n)   ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1))
 
#define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits)   vxge_bVALn(bits, 0, 16)
 
#define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits)   vxge_bVALn(bits, 48, 8)
 
#define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits)   vxge_bVALn(bits, 56, 8)
 
#define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits)   vxge_bVALn(bits, 3, 5)
 
#define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits)   vxge_bVALn(bits, 5, 3)
 
#define VXGE_HW_PF_SW_RESET_COMMAND   0xA5
 
#define VXGE_HW_TITAN_PCICFGMGMT_REG_SPACES   17
 
#define VXGE_HW_TITAN_SRPCIM_REG_SPACES   17
 
#define VXGE_HW_TITAN_VPMGMT_REG_SPACES   17
 
#define VXGE_HW_TITAN_VPATH_REG_SPACES   17
 
#define VXGE_HW_PRIV_FN_ACTION   8
 
#define VXGE_HW_PRIV_VP_ACTION   5
 
#define VXGE_HW_PRIV_FN_MEMO   13
 
#define VXGE_HW_EN_DIS_UDP_RTH   10
 
#define VXGE_HW_BW_CONTROL   12
 
#define VXGE_HW_RTS_ACCESS_FW_MEMO_ACTION_PRIV_NWIF   17
 
#define VXGE_HW_FW_API_FUNC_MODE   11
 
#define VXGE_HW_FW_API_GET_FUNC_MODE   29
 
#define VXGE_HW_FW_API_FUNC_MODE_COMMIT   21
 
#define VXGE_HW_GET_FUNC_MODE_VAL(val)   (val & 0xFF)
 
#define VXGE_HW_BYTES_PER_U64   8
 
#define VXGE_HW_FW_UPGRADE_MEMO   13
 
#define VXGE_HW_FW_UPGRADE_ACTION   16
 
#define VXGE_HW_FW_UPGRADE_OFFSET_START   2 /* Start upgrade */
 
#define VXGE_HW_FW_UPGRADE_OFFSET_SEND   3 /* Send upgrade data */
 
#define VXGE_HW_FW_UPGRADE_OFFSET_COMMIT   4 /* Commit upgrade */
 
#define VXGE_HW_FW_UPGRADE_OFFSET_READ   5 /* Read upgrade version */
 
#define VXGE_HW_FW_UPGRADE_BLK_SIZE   16 /* Bytes to write */
 
#define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val)   (val & 0xff)
 
#define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val)   ((val >> 8) & 0xff)
 
#define VXGE_HW_ASIC_MODE_RESERVED   0
 
#define VXGE_HW_ASIC_MODE_NO_IOV   1
 
#define VXGE_HW_ASIC_MODE_SR_IOV   2
 
#define VXGE_HW_ASIC_MODE_MR_IOV   3
 
#define VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN   vxge_mBIT(3)
 
#define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE   vxge_mBIT(19)
 
#define VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH   vxge_mBIT(23)
 
#define VXGE_HW_TXMAC_GEN_CFG1_HOST_APPEND_FCS   vxge_mBIT(31)
 
#define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits)   vxge_bVALn(bits, 3, 1)
 
#define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits)   vxge_bVALn(bits, 50, 14)
 
#define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits)   vxge_bVALn(bits, 0, 17)
 
#define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits)   vxge_bVALn(bits, 3, 5)
 
#define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits)   vxge_bVALn(bits, 17, 15)
 
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE   0
 
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY   1
 
#define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE   2
 
#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY   0
 
#define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE   1
 
#define VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val)   (val&~VXGE_HW_TOC_KDFC_INITIAL_BIR(7))
 
#define VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val)   vxge_bVALn(val, 61, 3)
 
#define VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET(val)   (val&~VXGE_HW_TOC_USDC_INITIAL_BIR(7))
 
#define VXGE_HW_TOC_GET_USDC_INITIAL_BIR(val)   vxge_bVALn(val, 61, 3)
 
#define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits)   bits
 
#define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits)   bits
 
#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits)   vxge_bVALn(bits, 1, 15)
 
#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits)   vxge_bVALn(bits, 17, 15)
 
#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits)   vxge_bVALn(bits, 33, 15)
 
#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val)   vxge_vBIT(val, 42, 5)
 
#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val)   vxge_vBIT(val, 47, 2)
 
#define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER   0
 
#define VXGE_HW_PRC_CFG4_RING_MODE_THREE_BUFFER   1
 
#define VXGE_HW_PRC_CFG4_RING_MODE_FIVE_BUFFER   2
 
#define VXGE_HW_PRC_CFG7_SCATTER_MODE_A   0
 
#define VXGE_HW_PRC_CFG7_SCATTER_MODE_B   2
 
#define VXGE_HW_PRC_CFG7_SCATTER_MODE_C   1
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_WE_READ   0
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_WE_WRITE   1
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA   0
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID   1
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE   2
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN   3
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN   4
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG   5
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT   6
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG   7
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK   8
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY   9
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS   10
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS   11
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT   12
 
#define VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_VERSION   13
 
#define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits)   vxge_bVALn(bits, 0, 48)
 
#define VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)   vxge_bVALn(bits, 0, 48)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE   vxge_mBIT(54)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits)   vxge_bVALn(bits, 55, 5)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)   vxge_vBIT(val, 55, 5)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits)   vxge_bVALn(bits, 62, 2)
 
#define VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val)   vxge_vBIT(val, 62, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY   0
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY   1
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY   2
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY   3
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY   0
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY   1
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY   3
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL   4
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR   172
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA   0
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID   1
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE   2
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN   3
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG   5
 
#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT   6
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG   7
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK   8
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY   9
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS   10
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS   11
 
#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT   12
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO   13
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits)   vxge_bVALn(bits, 0, 48)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_SEND_TO_NW   vxge_mBIT(51)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits)   vxge_bVALn(bits, 0, 12)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(val)   vxge_vBIT(val, 0, 12)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits)   vxge_bVALn(bits, 0, 11)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits)   vxge_bVALn(bits, 3, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL   vxge_mBIT(3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits)   vxge_bVALn(bits, 7, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL   vxge_mBIT(7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits)   vxge_bVALn(bits, 8, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val)   vxge_vBIT(val, 8, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits)   vxge_bVALn(bits, 3, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN   vxge_mBIT(3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits)   vxge_bVALn(bits, 4, 4)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits)   vxge_bVALn(bits, 10, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val)   vxge_vBIT(val, 10, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS   0
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS   1
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C   2
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits)   vxge_bVALn(bits, 15, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN   vxge_mBIT(15)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits)   vxge_bVALn(bits, 19, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN   vxge_mBIT(19)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits)   vxge_bVALn(bits, 23, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN   vxge_mBIT(23)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits)   vxge_bVALn(bits, 27, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN   vxge_mBIT(27)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits)   vxge_bVALn(bits, 31, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN   vxge_mBIT(31)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits)   vxge_bVALn(bits, 35, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN   vxge_mBIT(35)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits)   vxge_bVALn(bits, 39, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE   vxge_mBIT(39)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits)   vxge_bVALn(bits, 43, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN   vxge_mBIT(43)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits)   vxge_bVALn(bits, 3, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN   vxge_mBIT(3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits)   vxge_bVALn(bits, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val)   vxge_vBIT(val, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits)   vxge_bVALn(bits, 8, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN   vxge_mBIT(8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits)   vxge_bVALn(bits, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val)   vxge_vBIT(val, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits)   vxge_bVALn(bits, 16, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits)   vxge_bVALn(bits, 24, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN   vxge_mBIT(24)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits)   vxge_bVALn(bits, 25, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val)   vxge_vBIT(val, 25, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits)   vxge_bVALn(bits, 8, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN   vxge_mBIT(8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits)   vxge_bVALn(bits, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val)   vxge_vBIT(val, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits)   vxge_bVALn(bits, 16, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits)   vxge_bVALn(bits, 24, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN   vxge_mBIT(24)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits)   vxge_bVALn(bits, 25, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val)   vxge_vBIT(val, 25, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val)   vxge_vBIT(val, 0, 32)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits)   vxge_bVALn(bits, 0, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits)   vxge_bVALn(bits, 32, 4)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val)   vxge_vBIT(val, 32, 4)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits)   vxge_bVALn(bits, 36, 4)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val)   vxge_vBIT(val, 36, 4)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits)   vxge_bVALn(bits, 40, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val)   vxge_vBIT(val, 40, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits)   vxge_bVALn(bits, 42, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val)   vxge_vBIT(val, 42, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits)   vxge_bVALn(bits, 0, 64)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits)   vxge_bVALn(bits, 3, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN   vxge_mBIT(3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits)   vxge_bVALn(bits, 3, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN   vxge_mBIT(3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits)   vxge_bVALn(bits, 0, 48)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val)   vxge_vBIT(val, 62, 2)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits)   vxge_bVALn(bits, 8, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN   vxge_mBIT(8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits)   vxge_bVALn(bits, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val)   vxge_vBIT(val, 9, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits)   vxge_bVALn(bits, 16, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits)   vxge_bVALn(bits, 24, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN   vxge_mBIT(24)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits)   vxge_bVALn(bits, 25, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val)   vxge_vBIT(val, 25, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits)   vxge_bVALn(bits, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val)   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits)   vxge_bVALn(bits, 40, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN   vxge_mBIT(40)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits)   vxge_bVALn(bits, 41, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val)   vxge_vBIT(val, 41, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits)   vxge_bVALn(bits, 48, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val)   vxge_vBIT(val, 48, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits)   vxge_bVALn(bits, 56, 1)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN   vxge_mBIT(56)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits)   vxge_bVALn(bits, 57, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val)   vxge_vBIT(val, 57, 7)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER   0
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER   1
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_VERSION   2
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE   3
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0   4
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1   5
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2   6
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3   7
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORTS   8
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_TYPE   10
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_VENDOR   11
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_PARTNO   13
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT0_PMD_SERNO   14
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_TYPE   20
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_VENDOR   21
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_PARTNO   23
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PORT1_PMD_SERNO   24
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON   1
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF   0
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits)   vxge_bVALn(bits, 8, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits)   vxge_bVALn(bits, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits)   vxge_bVALn(bits, 40, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR   vxge_vBIT(val, 40, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits)   vxge_bVALn(bits, 48, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits)   vxge_bVALn(bits, 8, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits)   vxge_bVALn(bits, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits)   vxge_bVALn(bits, 40, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR   vxge_vBIT(val, 40, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits)   vxge_bVALn(bits, 48, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_API_VER(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_TX_PRIORITY(bits)   vxge_bVALn(bits, 21, 3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_TX_MIN_BW(bits)   vxge_bVALn(bits, 24, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_TX_MAX_BW(bits)   vxge_bVALn(bits, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RX_PRIORITY(bits)   vxge_bVALn(bits, 45, 3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RX_MIN_BW(bits)   vxge_bVALn(bits, 48, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RX_MAX_BW(bits)   vxge_bVALn(bits, 56, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(val)   vxge_vBIT(val, 21, 3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_TX_MIN_BW(val)   vxge_vBIT(val, 24, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(val)   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(val)   vxge_vBIT(val, 45, 3)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_RX_MIN_BW(val)   vxge_vBIT(val, 48, 8)
 
#define VXGE_HW_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(val)   vxge_vBIT(val, 56, 8)
 
#define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)   vxge_bVALn(bits, 0, 18)
 
#define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits)   vxge_bVALn(bits, 48, 16)
 
#define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits)   vxge_bVALn(bits, 48, 16)
 
#define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits)   (bits)
 
#define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits)   (bits)
 
#define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits)   vxge_bVALn(bits, 48, 16)
 
#define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits)   vxge_bVALn(bits, 0, 16)
 
#define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits)   vxge_bVALn(bits, 32, 16)
 
#define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits)   vxge_bVALn(bits, 0, 16)
 
#define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits)   vxge_bVALn(bits, 32, 16)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits)   vxge_bVALn(bits, 0, 32)
 
#define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits)   vxge_bVALn(bits, 0, 16)
 
#define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits)   vxge_bVALn(bits, 32, 16)
 
#define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits)   vxge_bVALn(bits, 0, 16)
 
#define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits)   vxge_bVALn(bits, 16, 16)
 
#define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits)   vxge_bVALn(bits, 32, 16)
 
#define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits)   vxge_bVALn(bits, 32, 32)
 
#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits)   vxge_bVALn(bits, 8, 8)
 
#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits)   vxge_bVALn(bits, 16, 8)
 
#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits)   vxge_bVALn(bits, 0, 8)
 
#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits)   vxge_bVALn(bits, 8, 8)
 
#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits)   vxge_bVALn(bits, 16, 8)
 
#define VXGE_HW_CONFIG_PRIV_H
 
#define VXGE_HW_SWAPPER_INITIAL_VALUE   0x0123456789abcdefULL
 
#define VXGE_HW_SWAPPER_BYTE_SWAPPED   0xefcdab8967452301ULL
 
#define VXGE_HW_SWAPPER_BIT_FLIPPED   0x80c4a2e691d5b3f7ULL
 
#define VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED   0xf7b3d591e6a2c480ULL
 
#define VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE   0xFFFFFFFFFFFFFFFFULL
 
#define VXGE_HW_SWAPPER_READ_BYTE_SWAP_DISABLE   0x0000000000000000ULL
 
#define VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE   0xFFFFFFFFFFFFFFFFULL
 
#define VXGE_HW_SWAPPER_READ_BIT_FLAP_DISABLE   0x0000000000000000ULL
 
#define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE   0xFFFFFFFFFFFFFFFFULL
 
#define VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_DISABLE   0x0000000000000000ULL
 
#define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE   0xFFFFFFFFFFFFFFFFULL
 
#define VXGE_HW_SWAPPER_WRITE_BIT_FLAP_DISABLE   0x0000000000000000ULL
 
#define VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_KDFC_INITIAL_OFFSET(val)   vxge_vBIT(val, 0, 61)
 
#define VXGE_HW_TOC_KDFC_INITIAL_BIR(val)   vxge_vBIT(val, 61, 3)
 
#define VXGE_HW_TOC_USDC_INITIAL_OFFSET(val)   vxge_vBIT(val, 0, 61)
 
#define VXGE_HW_TOC_USDC_INITIAL_BIR(val)   vxge_vBIT(val, 61, 3)
 
#define VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_PRC_STATUS1_PRC_VP_QUIESCENT(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXDCM_RESET_IN_PROGRESS_PRC_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RD_REQ_IN_PROGRESS_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RD_REQ_OUTSTANDING_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_KDFC_RESET_IN_PROGRESS_NOA_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_ONE_CFG_VP_RDY(n)   vxge_mBIT(n)
 
#define VXGE_HW_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n)   vxge_mBIT(n)
 
#define VXGE_HW_TIM_INT_EN_TIM_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_TIM_SET_INT_EN_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_TIM_CLR_INT_EN_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_TIM_MASK_INT_DURING_RESET_VPATH(n)   vxge_mBIT(n)
 
#define VXGE_HW_TIM_RESET_IN_PROGRESS_TIM_VPATH(n)   vxge_mBIT(n)
 
#define VXGE_HW_TIM_OUTSTANDING_BMAP_TIM_VPATH(n)   vxge_mBIT(n)
 
#define VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_MSG_MXP_MR_READY_MP_BOOTED(n)   vxge_mBIT(n)
 
#define VXGE_HW_MSG_UXP_MR_READY_UP_BOOTED(n)   vxge_mBIT(n)
 
#define VXGE_HW_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n)   vxge_mBIT(n)
 
#define VXGE_HW_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n)   vxge_mBIT(n)
 
#define VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_STATS_CFG0_STATS_ENABLE(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_MASK_VECTOR_MASK_VECTOR(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val)   vxge_vBIT(val, 48, 8)
 
#define VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val)   vxge_vBIT(val, 56, 8)
 
#define VXGE_HW_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT   vxge_mBIT(0)
 
#define VXGE_HW_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT   vxge_mBIT(1)
 
#define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT   vxge_mBIT(2)
 
#define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val)   vxge_vBIT(val, 3, 17)
 
#define VXGE_HW_TITAN_MASK_ALL_INT_ALARM   vxge_mBIT(7)
 
#define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC   vxge_mBIT(15)
 
#define VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1(val)   vxge_vBIT(val, 0, 4)
 
#define VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1(val)   vxge_vBIT(val, 0, 4)
 
#define VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTI_INT_MASK_RTI_INT_MASK(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_ADAPTER_STATUS_RTDMA_RTDMA_READY   vxge_mBIT(0)
 
#define VXGE_HW_ADAPTER_STATUS_WRDMA_WRDMA_READY   vxge_mBIT(1)
 
#define VXGE_HW_ADAPTER_STATUS_KDFC_KDFC_READY   vxge_mBIT(2)
 
#define VXGE_HW_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY   vxge_mBIT(3)
 
#define VXGE_HW_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT   vxge_mBIT(4)
 
#define VXGE_HW_ADAPTER_STATUS_XGMAC_NETWORK_FAULT   vxge_mBIT(5)
 
#define VXGE_HW_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT   vxge_mBIT(6)
 
#define VXGE_HW_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY   vxge_mBIT(7)
 
#define VXGE_HW_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY   vxge_mBIT(8)
 
#define VXGE_HW_ADAPTER_STATUS_RIC_RIC_RUNNING   vxge_mBIT(9)
 
#define VXGE_HW_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK   vxge_mBIT(10)
 
#define VXGE_HW_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK   vxge_mBIT(11)
 
#define VXGE_HW_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK   vxge_mBIT(12)
 
#define VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE(val)   vxge_vBIT(val, 24, 8)
 
#define VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT(val)   vxge_vBIT(val, 44, 8)
 
#define VXGE_HW_GEN_CTRL_SPI_MRPCIM_WR_DIS   vxge_mBIT(0)
 
#define VXGE_HW_GEN_CTRL_SPI_MRPCIM_RD_DIS   vxge_mBIT(1)
 
#define VXGE_HW_GEN_CTRL_SPI_SRPCIM_WR_DIS   vxge_mBIT(2)
 
#define VXGE_HW_GEN_CTRL_SPI_SRPCIM_RD_DIS   vxge_mBIT(3)
 
#define VXGE_HW_GEN_CTRL_SPI_DEBUG_DIS   vxge_mBIT(4)
 
#define VXGE_HW_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS   vxge_mBIT(5)
 
#define VXGE_HW_GEN_CTRL_SPI_NOT_USED(val)   vxge_vBIT(val, 6, 4)
 
#define VXGE_HW_ADAPTER_READY_ADAPTER_READY   vxge_mBIT(63)
 
#define VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_CP_RESET_IN_PROGRESS_CP_VPATH(n)   vxge_mBIT(n)
 
#define VXGE_HW_XGMAC_READY_XMACJ_READY(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_FBIF_READY_FAU_READY(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_ICMP_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_TCPSYN_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_ZL4PYLD_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_ACCESS_IPFRAG_EN(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RESOURCE_NO_PFN_OR_VF   BIT(3)
 
#define VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK(val)   vxge_vBIT(val, 2, 6)
 
#define VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK(val)   vxge_vBIT(val, 2, 6)
 
#define VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK(val)   vxge_vBIT(val, 2, 6)
 
#define VXGE_HW_MSIXGRP_NO_TABLE_SIZE(val)   vxge_vBIT(val, 5, 11)
 
#define VXGE_HW_G3FBCT_INT_STATUS_ERR_G3IF_INT   vxge_mBIT(0)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_DECC   vxge_mBIT(5)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC   vxge_mBIT(6)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC   vxge_mBIT(7)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_SECC   vxge_mBIT(29)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC   vxge_mBIT(30)
 
#define VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC   vxge_mBIT(31)
 
#define VXGE_HW_WRDMA_INT_STATUS_RC_ALARM_RC_INT   vxge_mBIT(0)
 
#define VXGE_HW_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT   vxge_mBIT(1)
 
#define VXGE_HW_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT   vxge_mBIT(2)
 
#define VXGE_HW_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT   vxge_mBIT(3)
 
#define VXGE_HW_WRDMA_INT_STATUS_RDA_ERR_RDA_INT   vxge_mBIT(6)
 
#define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT   vxge_mBIT(8)
 
#define VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT   vxge_mBIT(9)
 
#define VXGE_HW_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT   vxge_mBIT(12)
 
#define VXGE_HW_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT   vxge_mBIT(13)
 
#define VXGE_HW_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT   vxge_mBIT(14)
 
#define VXGE_HW_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT   vxge_mBIT(15)
 
#define VXGE_HW_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT   vxge_mBIT(16)
 
#define VXGE_HW_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT   vxge_mBIT(17)
 
#define VXGE_HW_RC_ALARM_REG_FTC_SM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_RC_ALARM_REG_FTC_SM_PHASE_ERR   vxge_mBIT(1)
 
#define VXGE_HW_RC_ALARM_REG_BTDWM_SM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_RC_ALARM_REG_BTC_SM_ERR   vxge_mBIT(3)
 
#define VXGE_HW_RC_ALARM_REG_BTDCM_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_RC_ALARM_REG_BTDRM_SM_ERR   vxge_mBIT(5)
 
#define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR   vxge_mBIT(6)
 
#define VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR   vxge_mBIT(7)
 
#define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR   vxge_mBIT(8)
 
#define VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR   vxge_mBIT(9)
 
#define VXGE_HW_RC_ALARM_REG_RMM_SM_ERR   vxge_mBIT(10)
 
#define VXGE_HW_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR   vxge_mBIT(12)
 
#define VXGE_HW_RXDRM_SM_ERR_REG_PRC_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXDCM_SM_ERR_REG_PRC_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXDWM_SM_ERR_REG_PRC_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RDA_ERR_REG_RDA_SM0_ERR_ALARM   vxge_mBIT(0)
 
#define VXGE_HW_RDA_ERR_REG_RDA_MISC_ERR   vxge_mBIT(1)
 
#define VXGE_HW_RDA_ERR_REG_RDA_PCIX_ERR   vxge_mBIT(2)
 
#define VXGE_HW_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR   vxge_mBIT(3)
 
#define VXGE_HW_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR   vxge_mBIT(4)
 
#define VXGE_HW_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR   vxge_mBIT(5)
 
#define VXGE_HW_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR   vxge_mBIT(6)
 
#define VXGE_HW_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR   vxge_mBIT(7)
 
#define VXGE_HW_RDA_ECC_DB_REG_RDA_RXD_ERR(n)   vxge_mBIT(n)
 
#define VXGE_HW_RDA_ECC_SG_REG_RDA_RXD_ERR(n)   vxge_mBIT(n)
 
#define VXGE_HW_RQA_ERR_REG_RQA_SM_ERR_ALARM   vxge_mBIT(0)
 
#define VXGE_HW_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n)   vxge_mBIT(n)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB   vxge_mBIT(0)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG   vxge_mBIT(1)
 
#define VXGE_HW_ROCRC_ALARM_REG_NOA_NMA_SM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB   vxge_mBIT(3)
 
#define VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG   vxge_mBIT(4)
 
#define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB   vxge_mBIT(5)
 
#define VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG   vxge_mBIT(6)
 
#define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB   vxge_mBIT(11)
 
#define VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG   vxge_mBIT(12)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR   vxge_mBIT(13)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR   vxge_mBIT(14)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR   vxge_mBIT(15)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR   vxge_mBIT(16)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR   vxge_mBIT(17)
 
#define VXGE_HW_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR   vxge_mBIT(18)
 
#define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW   vxge_mBIT(19)
 
#define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW   vxge_mBIT(20)
 
#define VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW   vxge_mBIT(21)
 
#define VXGE_HW_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR   vxge_mBIT(22)
 
#define VXGE_HW_WDE0_ALARM_REG_WDE0_DCC_SM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_WDE0_ALARM_REG_WDE0_PRM_SM_ERR   vxge_mBIT(1)
 
#define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_SM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_WDE0_ALARM_REG_WDE0_CP_CMD_ERR   vxge_mBIT(3)
 
#define VXGE_HW_WDE0_ALARM_REG_WDE0_PCR_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_WDE1_ALARM_REG_WDE1_DCC_SM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_WDE1_ALARM_REG_WDE1_PRM_SM_ERR   vxge_mBIT(1)
 
#define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_SM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_WDE1_ALARM_REG_WDE1_CP_CMD_ERR   vxge_mBIT(3)
 
#define VXGE_HW_WDE1_ALARM_REG_WDE1_PCR_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_WDE2_ALARM_REG_WDE2_DCC_SM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_WDE2_ALARM_REG_WDE2_PRM_SM_ERR   vxge_mBIT(1)
 
#define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_SM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_WDE2_ALARM_REG_WDE2_CP_CMD_ERR   vxge_mBIT(3)
 
#define VXGE_HW_WDE2_ALARM_REG_WDE2_PCR_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_WDE3_ALARM_REG_WDE3_DCC_SM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_WDE3_ALARM_REG_WDE3_PRM_SM_ERR   vxge_mBIT(1)
 
#define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_SM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_WDE3_ALARM_REG_WDE3_CP_CMD_ERR   vxge_mBIT(3)
 
#define VXGE_HW_WDE3_ALARM_REG_WDE3_PCR_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_WRR_RING_SERVICE_STATES   171
 
#define VXGE_HW_WRR_RING_COUNT   22
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_RX_QUEUE_SELECT_NUMBER(n)   vxge_mBIT(n)
 
#define VXGE_HW_RX_QUEUE_SELECT_ENABLE_CODE   vxge_mBIT(15)
 
#define VXGE_HW_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY   vxge_mBIT(23)
 
#define VXGE_HW_RQA_VPBP_CTRL_WR_XON_DIS   vxge_mBIT(15)
 
#define VXGE_HW_RQA_VPBP_CTRL_ROCRC_DIS   vxge_mBIT(23)
 
#define VXGE_HW_RQA_VPBP_CTRL_TXPE_DIS   vxge_mBIT(31)
 
#define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_DIS   vxge_mBIT(0)
 
#define VXGE_HW_RX_MULTI_CAST_CTRL_FRM_DROP_DIS   vxge_mBIT(1)
 
#define VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val)   vxge_vBIT(val, 2, 30)
 
#define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD(val)   vxge_vBIT(val, 2, 10)
 
#define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val)   vxge_vBIT(val, 18, 14)
 
#define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW   vxge_mBIT(32)
 
#define VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY   vxge_mBIT(33)
 
#define VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE(val)   vxge_vBIT(val, 46, 2)
 
#define VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_NOA_CTRL_IGNORE_KDFC_IF_STATUS   vxge_mBIT(16)
 
#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val)   vxge_vBIT(val, 37, 4)
 
#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val)   vxge_vBIT(val, 45, 4)
 
#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val)   vxge_vBIT(val, 53, 4)
 
#define VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val)   vxge_vBIT(val, 60, 4)
 
#define VXGE_HW_PHASE_CFG_QCC_WR_PHASE_EN   vxge_mBIT(0)
 
#define VXGE_HW_PHASE_CFG_QCC_RD_PHASE_EN   vxge_mBIT(3)
 
#define VXGE_HW_PHASE_CFG_IMMM_WR_PHASE_EN   vxge_mBIT(7)
 
#define VXGE_HW_PHASE_CFG_IMMM_RD_PHASE_EN   vxge_mBIT(11)
 
#define VXGE_HW_PHASE_CFG_UMQM_WR_PHASE_EN   vxge_mBIT(15)
 
#define VXGE_HW_PHASE_CFG_UMQM_RD_PHASE_EN   vxge_mBIT(19)
 
#define VXGE_HW_PHASE_CFG_RCBM_WR_PHASE_EN   vxge_mBIT(23)
 
#define VXGE_HW_PHASE_CFG_RCBM_RD_PHASE_EN   vxge_mBIT(27)
 
#define VXGE_HW_PHASE_CFG_RXD_RC_WR_PHASE_EN   vxge_mBIT(31)
 
#define VXGE_HW_PHASE_CFG_RXD_RC_RD_PHASE_EN   vxge_mBIT(35)
 
#define VXGE_HW_PHASE_CFG_RXD_RHS_WR_PHASE_EN   vxge_mBIT(39)
 
#define VXGE_HW_PHASE_CFG_RXD_RHS_RD_PHASE_EN   vxge_mBIT(43)
 
#define VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val)   vxge_vBIT(val, 10, 22)
 
#define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val)   vxge_vBIT(val, 39, 9)
 
#define VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val)   vxge_vBIT(val, 55, 9)
 
#define VXGE_HW_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT   vxge_mBIT(7)
 
#define VXGE_HW_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT   vxge_mBIT(15)
 
#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR   vxge_mBIT(7)
 
#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR   vxge_mBIT(15)
 
#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM   vxge_mBIT(23)
 
#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1   vxge_mBIT(32)
 
#define VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR   vxge_mBIT(39)
 
#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR   vxge_mBIT(7)
 
#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR   vxge_mBIT(15)
 
#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM   vxge_mBIT(23)
 
#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1   vxge_mBIT(32)
 
#define VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR   vxge_mBIT(39)
 
#define VXGE_HW_KDFC_VP_PARTITION_0_ENABLE   vxge_mBIT(0)
 
#define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1(val)   vxge_vBIT(val, 37, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3(val)   vxge_vBIT(val, 37, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5(val)   vxge_vBIT(val, 37, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7(val)   vxge_vBIT(val, 37, 3)
 
#define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val)   vxge_vBIT(val, 49, 15)
 
#define VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16(val)   vxge_vBIT(val, 17, 15)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_WRR_FIFO_COUNT   20
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val)   vxge_vBIT(val, 19, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val)   vxge_vBIT(val, 35, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val)   vxge_vBIT(val, 43, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val)   vxge_vBIT(val, 51, 5)
 
#define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val)   vxge_vBIT(val, 14, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val)   vxge_vBIT(val, 22, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val)   vxge_vBIT(val, 30, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val)   vxge_vBIT(val, 38, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val)   vxge_vBIT(val, 46, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val)   vxge_vBIT(val, 54, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val)   vxge_vBIT(val, 62, 2)
 
#define VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_WEIGHTED_RR_SERVICE_STATES   176
 
#define VXGE_HW_WRR_FIFO_SERVICE_STATES   153
 
#define VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT   vxge_mBIT(7)
 
#define VXGE_HW_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT   vxge_mBIT(11)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val)   vxge_vBIT(val, 0, 4)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val)   vxge_vBIT(val, 8, 4)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val)   vxge_vBIT(val, 16, 4)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val)   vxge_vBIT(val, 20, 4)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val)   vxge_vBIT(val, 24, 2)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val)   vxge_vBIT(val, 26, 2)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val)   vxge_vBIT(val, 28, 2)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val)   vxge_vBIT(val, 30, 2)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR   vxge_mBIT(32)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR   vxge_mBIT(33)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR   vxge_mBIT(34)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR   vxge_mBIT(35)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR   vxge_mBIT(36)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR   vxge_mBIT(37)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR   vxge_mBIT(38)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR   vxge_mBIT(39)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val)   vxge_vBIT(val, 40, 7)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val)   vxge_vBIT(val, 47, 7)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val)   vxge_vBIT(val, 54, 3)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val)   vxge_vBIT(val, 57, 3)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR   vxge_mBIT(60)
 
#define VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR   vxge_mBIT(61)
 
#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR   vxge_mBIT(1)
 
#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR   vxge_mBIT(2)
 
#define VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_GEN_CFG_SCALE_RMAC_UTIL   vxge_mBIT(11)
 
#define VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXMAC_AUTHORIZE_ALL_VID_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val)   vxge_vBIT(val, 0, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val)   vxge_vBIT(val, 8, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val)   vxge_vBIT(val, 16, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val)   vxge_vBIT(val, 20, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val)   vxge_vBIT(val, 24, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val)   vxge_vBIT(val, 28, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN   vxge_mBIT(35)
 
#define VXGE_HW_RXMAC_CFG0_PORT_RMAC_EN   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_CFG0_PORT_STRIP_FCS   vxge_mBIT(7)
 
#define VXGE_HW_RXMAC_CFG0_PORT_DISCARD_PFRM   vxge_mBIT(11)
 
#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_FCS_ERR   vxge_mBIT(15)
 
#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LONG_ERR   vxge_mBIT(19)
 
#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR   vxge_mBIT(23)
 
#define VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH   vxge_mBIT(27)
 
#define VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val)   vxge_vBIT(val, 50, 14)
 
#define VXGE_HW_RXMAC_CFG2_PORT_PROM_EN   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN   vxge_mBIT(7)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val)   vxge_vBIT(val, 9, 3)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR   vxge_mBIT(15)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val)   vxge_vBIT(val, 20, 16)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR   vxge_mBIT(39)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR   vxge_mBIT(43)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_LIMITER_EN   vxge_mBIT(47)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val)   vxge_vBIT(val, 48, 8)
 
#define VXGE_HW_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL   vxge_mBIT(59)
 
#define VXGE_HW_RXMAC_RED_CFG0_PORT_RED_EN_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXMAC_RED_CFG1_PORT_FINE_EN   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE   vxge_mBIT(11)
 
#define VXGE_HW_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val)   vxge_vBIT(val, 1, 7)
 
#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val)   vxge_vBIT(val, 8, 4)
 
#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val)   vxge_vBIT(val, 16, 4)
 
#define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR   vxge_mBIT(23)
 
#define VXGE_HW_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N   vxge_mBIT(7)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO   vxge_mBIT(18)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS   vxge_mBIT(19)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING   vxge_mBIT(23)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN   vxge_mBIT(27)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE   vxge_mBIT(35)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR   vxge_mBIT(39)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR   vxge_mBIT(43)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR   vxge_mBIT(47)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR   vxge_mBIT(51)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR   vxge_mBIT(55)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR   vxge_mBIT(59)
 
#define VXGE_HW_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN   vxge_mBIT(63)
 
#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH   vxge_mBIT(3)
 
#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH   vxge_mBIT(7)
 
#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH   vxge_mBIT(11)
 
#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH   vxge_mBIT(15)
 
#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF   vxge_mBIT(19)
 
#define VXGE_HW_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG   vxge_mBIT(23)
 
#define VXGE_HW_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY   vxge_mBIT(3)
 
#define VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val)   vxge_vBIT(val, 24, 8)
 
#define VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH   vxge_mBIT(35)
 
#define VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH   vxge_mBIT(39)
 
#define VXGE_HW_RTS_MGR_CFG0_ZL4PYLD_TRASH   vxge_mBIT(43)
 
#define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH   vxge_mBIT(47)
 
#define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH   vxge_mBIT(51)
 
#define VXGE_HW_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH   vxge_mBIT(55)
 
#define VXGE_HW_RTS_MGR_CFG0_IPFRAG_TRASH   vxge_mBIT(59)
 
#define VXGE_HW_RTS_MGR_CFG1_DA_ACTIVE_TABLE   vxge_mBIT(3)
 
#define VXGE_HW_RTS_MGR_CFG1_PN_ACTIVE_TABLE   vxge_mBIT(7)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val)   vxge_vBIT(val, 9, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN(val)   vxge_vBIT(val, 13, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val)   vxge_vBIT(val, 17, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val)   vxge_vBIT(val, 21, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS(val)   vxge_vBIT(val, 25, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS(val)   vxge_vBIT(val, 29, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val)   vxge_vBIT(val, 33, 3)
 
#define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val)   vxge_vBIT(val, 37, 3)
 
#define VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0(val)   vxge_vBIT(val, 0, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2(val)   vxge_vBIT(val, 8, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0(val)   vxge_vBIT(val, 16, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1(val)   vxge_vBIT(val, 20, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2(val)   vxge_vBIT(val, 24, 4)
 
#define VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3(val)   vxge_vBIT(val, 28, 4)
 
#define VXGE_HW_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT   vxge_mBIT(3)
 
#define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0   vxge_mBIT(7)
 
#define VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1   vxge_mBIT(11)
 
#define VXGE_HW_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT   vxge_mBIT(15)
 
#define VXGE_HW_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT   vxge_mBIT(19)
 
#define VXGE_HW_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT   vxge_mBIT(23)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED   vxge_mBIT(7)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED   vxge_mBIT(11)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU   vxge_mBIT(15)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED   vxge_mBIT(19)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED   vxge_mBIT(23)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU   vxge_mBIT(27)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED   vxge_mBIT(31)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val)   vxge_vBIT(val, 40, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val)   vxge_vBIT(val, 42, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val)   vxge_vBIT(val, 44, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val)   vxge_vBIT(val, 46, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val)   vxge_vBIT(val, 48, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val)   vxge_vBIT(val, 50, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val)   vxge_vBIT(val, 52, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val)   vxge_vBIT(val, 54, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val)   vxge_vBIT(val, 56, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val)   vxge_vBIT(val, 58, 2)
 
#define VXGE_HW_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR   vxge_mBIT(63)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN   vxge_mBIT(3)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP   vxge_mBIT(7)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN   vxge_mBIT(11)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP   vxge_mBIT(15)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT   vxge_mBIT(19)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK   vxge_mBIT(23)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN   vxge_mBIT(27)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP   vxge_mBIT(31)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE   vxge_mBIT(35)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV   vxge_mBIT(39)
 
#define VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE   vxge_mBIT(47)
 
#define VXGE_HW_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR   vxge_mBIT(63)
 
#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN   vxge_mBIT(3)
 
#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP   vxge_mBIT(7)
 
#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN   vxge_mBIT(11)
 
#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP   vxge_mBIT(15)
 
#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT   vxge_mBIT(19)
 
#define VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK   vxge_mBIT(23)
 
#define VXGE_HW_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n)   vxge_mBIT(n)
 
#define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_OK   vxge_mBIT(3)
 
#define VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE   vxge_mBIT(11)
 
#define VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val)   vxge_vBIT(val, 0, 17)
 
#define VXGE_HW_XGMAC_MAIN_CFG_PORT_PORT_EN   vxge_mBIT(3)
 
#define VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val)   vxge_vBIT(val, 2, 2)
 
#define VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT   vxge_mBIT(7)
 
#define VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAVIOUR   vxge_mBIT(27)
 
#define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP(val)   vxge_vBIT(val, 28, 4)
 
#define VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val)   vxge_vBIT(val, 32, 4)
 
#define VXGE_HW_XMAC_TIMESTAMP_EN   vxge_mBIT(3)
 
#define VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_XMAC_TIMESTAMP_TIMER_RESTART   vxge_mBIT(19)
 
#define VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val)   vxge_vBIT(val, 8, 4)
 
#define VXGE_HW_XMAC_STATS_GEN_CFG_VLAN_HANDLING   vxge_mBIT(15)
 
#define VXGE_HW_XMAC_STATS_SYS_CMD_OP(val)   vxge_vBIT(val, 5, 3)
 
#define VXGE_HW_XMAC_STATS_SYS_CMD_STROBE   vxge_mBIT(15)
 
#define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val)   vxge_vBIT(val, 27, 5)
 
#define VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(val)   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_ASIC_NTWK_CTRL_REQ_TEST_NTWK   vxge_mBIT(3)
 
#define VXGE_HW_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT   vxge_mBIT(11)
 
#define VXGE_HW_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT   vxge_mBIT(15)
 
#define VXGE_HW_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_ASIC_NTWK_CFG_PORT_NUM_VP(n)   vxge_mBIT(n)
 
#define VXGE_HW_XMAC_CFG_PORT_XGMII_LOOPBACK   vxge_mBIT(3)
 
#define VXGE_HW_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK   vxge_mBIT(7)
 
#define VXGE_HW_XMAC_CFG_PORT_XGMII_TX_BEHAV   vxge_mBIT(11)
 
#define VXGE_HW_XMAC_CFG_PORT_XGMII_RX_BEHAV   vxge_mBIT(15)
 
#define VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_LAG_CFG_EN   vxge_mBIT(3)
 
#define VXGE_HW_LAG_CFG_MODE(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_LAG_CFG_TX_DISCARD_BEHAV   vxge_mBIT(11)
 
#define VXGE_HW_LAG_CFG_RX_DISCARD_BEHAV   vxge_mBIT(15)
 
#define VXGE_HW_LAG_CFG_PREF_INDIV_PORT_NUM   vxge_mBIT(19)
 
#define VXGE_HW_LAG_STATUS_XLCM_WAITING_TO_FAILBACK   vxge_mBIT(3)
 
#define VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY   vxge_mBIT(3)
 
#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES   vxge_mBIT(7)
 
#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM   vxge_mBIT(11)
 
#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK   vxge_mBIT(15)
 
#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN   vxge_mBIT(19)
 
#define VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_LACP_CFG_EN   vxge_mBIT(3)
 
#define VXGE_HW_LAG_LACP_CFG_LACP_BEGIN   vxge_mBIT(7)
 
#define VXGE_HW_LAG_LACP_CFG_DISCARD_LACP   vxge_mBIT(11)
 
#define VXGE_HW_LAG_LACP_CFG_LIBERAL_LEN_CHK   vxge_mBIT(15)
 
#define VXGE_HW_LAG_TIMER_CFG_1_FAST_PER(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT(val)   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val)   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_LAG_SYS_ID_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR   vxge_mBIT(51)
 
#define VXGE_HW_LAG_SYS_ID_ADDR_SEL   vxge_mBIT(55)
 
#define VXGE_HW_LAG_SYS_CFG_SYS_PRI(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR   vxge_mBIT(51)
 
#define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL   vxge_mBIT(55)
 
#define VXGE_HW_LAG_AGGR_ID_CFG_ID(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR   vxge_mBIT(19)
 
#define VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_AGGR_STATE_LAGC_TX   vxge_mBIT(3)
 
#define VXGE_HW_LAG_AGGR_STATE_LAGC_RX   vxge_mBIT(7)
 
#define VXGE_HW_LAG_AGGR_STATE_LAGC_READY   vxge_mBIT(11)
 
#define VXGE_HW_LAG_AGGR_STATE_LAGC_INDIVIDUAL   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_CFG_EN   vxge_mBIT(3)
 
#define VXGE_HW_LAG_PORT_CFG_DISCARD_SLOW_PROTO   vxge_mBIT(7)
 
#define VXGE_HW_LAG_PORT_CFG_HOST_CHOSEN_AGGR   vxge_mBIT(11)
 
#define VXGE_HW_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val)   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY   vxge_mBIT(3)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT   vxge_mBIT(7)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION   vxge_mBIT(11)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING   vxge_mBIT(19)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING   vxge_mBIT(23)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED   vxge_mBIT(27)
 
#define VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED   vxge_mBIT(31)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val)   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY   vxge_mBIT(3)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT   vxge_mBIT(7)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION   vxge_mBIT(11)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING   vxge_mBIT(19)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING   vxge_mBIT(23)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED   vxge_mBIT(27)
 
#define VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED   vxge_mBIT(31)
 
#define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID   vxge_mBIT(19)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY   vxge_mBIT(3)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT   vxge_mBIT(7)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION   vxge_mBIT(11)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING   vxge_mBIT(19)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING   vxge_mBIT(23)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED   vxge_mBIT(27)
 
#define VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED   vxge_mBIT(31)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val)   vxge_vBIT(val, 0, 48)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val)   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY   vxge_mBIT(3)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT   vxge_mBIT(7)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION   vxge_mBIT(11)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING   vxge_mBIT(19)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING   vxge_mBIT(23)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED   vxge_mBIT(27)
 
#define VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED   vxge_mBIT(31)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_READY   vxge_mBIT(3)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM   vxge_mBIT(11)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED   vxge_mBIT(15)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED   vxge_mBIT(18)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED   vxge_mBIT(19)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_NTT   vxge_mBIT(23)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN   vxge_mBIT(27)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN   vxge_mBIT(31)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH   vxge_mBIT(32)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH   vxge_mBIT(33)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH   vxge_mBIT(34)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH   vxge_mBIT(35)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val)   vxge_vBIT(val, 37, 3)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val)   vxge_vBIT(val, 41, 3)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val)   vxge_vBIT(val, 44, 4)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE   vxge_mBIT(54)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE   vxge_mBIT(55)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val)   vxge_vBIT(val, 56, 4)
 
#define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val)   vxge_vBIT(val, 60, 4)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val)   vxge_vBIT(val, 24, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val)   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val)   vxge_vBIT(val, 40, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val)   vxge_vBIT(val, 48, 8)
 
#define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val)   vxge_vBIT(val, 56, 8)
 
#define VXGE_HW_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT   vxge_mBIT(1)
 
#define VXGE_HW_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT   vxge_mBIT(2)
 
#define VXGE_HW_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT   vxge_mBIT(4)
 
#define VXGE_HW_RTDMA_INT_STATUS_SM_ERROR_SM_INT   vxge_mBIT(5)
 
#define VXGE_HW_PDA_ALARM_REG_PDA_HSC_FIFO_ERR   vxge_mBIT(0)
 
#define VXGE_HW_PDA_ALARM_REG_PDA_SM_ERR   vxge_mBIT(1)
 
#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_ERROR_REG_PCC_PCC_SERR(n)   vxge_mBIT(n)
 
#define VXGE_HW_LSO_ERROR_REG_PCC_LSO_ABORT(n)   vxge_mBIT(n)
 
#define VXGE_HW_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n)   vxge_mBIT(n)
 
#define VXGE_HW_SM_ERROR_REG_SM_FSM_ERR_ALARM   vxge_mBIT(15)
 
#define VXGE_HW_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP   vxge_mBIT(7)
 
#define VXGE_HW_PCC_CFG_PCC_ENABLE(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_CFG_PCC_ECC_ENABLE_N(n)   vxge_mBIT(n)
 
#define VXGE_HW_PCC_CONTROL_FE_ENABLE(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN   vxge_mBIT(15)
 
#define VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR   vxge_mBIT(31)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR(val)   vxge_vBIT(val, 20, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR(val)   vxge_vBIT(val, 28, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR(val)   vxge_vBIT(val, 36, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR(val)   vxge_vBIT(val, 44, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR(val)   vxge_vBIT(val, 52, 4)
 
#define VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR(val)   vxge_vBIT(val, 60, 4)
 
#define VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_G3CMCT_INT_STATUS_ERR_G3IF_INT   vxge_mBIT(0)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_SM_ERR   vxge_mBIT(4)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_DECC   vxge_mBIT(5)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC   vxge_mBIT(6)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC   vxge_mBIT(7)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_SECC   vxge_mBIT(29)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC   vxge_mBIT(30)
 
#define VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC   vxge_mBIT(31)
 
#define VXGE_HW_MC_INT_STATUS_MC_ERR_MC_INT   vxge_mBIT(3)
 
#define VXGE_HW_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT   vxge_mBIT(7)
 
#define VXGE_HW_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT   vxge_mBIT(11)
 
#define VXGE_HW_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT   vxge_mBIT(15)
 
#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A   vxge_mBIT(3)
 
#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B   vxge_mBIT(4)
 
#define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR   vxge_mBIT(5)
 
#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0   vxge_mBIT(6)
 
#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1   vxge_mBIT(7)
 
#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A   vxge_mBIT(10)
 
#define VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B   vxge_mBIT(11)
 
#define VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR   vxge_mBIT(12)
 
#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0   vxge_mBIT(13)
 
#define VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1   vxge_mBIT(14)
 
#define VXGE_HW_MC_ERR_REG_MC_SM_ERR   vxge_mBIT(15)
 
#define VXGE_HW_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR   vxge_mBIT(3)
 
#define VXGE_HW_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR   vxge_mBIT(7)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1(val)   vxge_vBIT(val, 24, 8)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2(val)   vxge_vBIT(val, 32, 8)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3(val)   vxge_vBIT(val, 40, 8)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN   vxge_mBIT(62)
 
#define VXGE_HW_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ   vxge_mBIT(63)
 
#define VXGE_HW_FBMC_ECC_CFG_ENABLE(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT   vxge_mBIT(3)
 
#define VXGE_HW_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT   vxge_mBIT(7)
 
#define VXGE_HW_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT   vxge_mBIT(11)
 
#define VXGE_HW_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT   vxge_mBIT(15)
 
#define VXGE_HW_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT   vxge_mBIT(19)
 
#define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR   vxge_mBIT(3)
 
#define VXGE_HW_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR   vxge_mBIT(7)
 
#define VXGE_HW_DBECC_ERR_REG_PCI_P_HDR_DB_ERR   vxge_mBIT(11)
 
#define VXGE_HW_DBECC_ERR_REG_PCI_P_DATA_DB_ERR   vxge_mBIT(15)
 
#define VXGE_HW_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR   vxge_mBIT(19)
 
#define VXGE_HW_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR   vxge_mBIT(23)
 
#define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR   vxge_mBIT(3)
 
#define VXGE_HW_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR   vxge_mBIT(7)
 
#define VXGE_HW_SBECC_ERR_REG_PCI_P_HDR_SG_ERR   vxge_mBIT(11)
 
#define VXGE_HW_SBECC_ERR_REG_PCI_P_DATA_SG_ERR   vxge_mBIT(15)
 
#define VXGE_HW_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR   vxge_mBIT(19)
 
#define VXGE_HW_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR   vxge_mBIT(23)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG   vxge_mBIT(3)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG   vxge_mBIT(7)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR   vxge_mBIT(11)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE   vxge_mBIT(15)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET   vxge_mBIT(19)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET   vxge_mBIT(23)
 
#define VXGE_HW_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP   vxge_mBIT(27)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT   vxge_mBIT(0)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT   vxge_mBIT(1)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT   vxge_mBIT(2)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT   vxge_mBIT(3)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT   vxge_mBIT(4)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT   vxge_mBIT(5)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT   vxge_mBIT(6)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT   vxge_mBIT(7)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT   vxge_mBIT(8)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT   vxge_mBIT(9)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT   vxge_mBIT(10)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT   vxge_mBIT(11)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT   vxge_mBIT(12)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT   vxge_mBIT(13)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT   vxge_mBIT(14)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT   vxge_mBIT(15)
 
#define VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT   vxge_mBIT(16)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT   vxge_mBIT(0)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT   vxge_mBIT(1)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT   vxge_mBIT(2)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT   vxge_mBIT(3)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT   vxge_mBIT(4)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT   vxge_mBIT(5)
 
#define VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT   vxge_mBIT(6)
 
#define VXGE_HW_GCMG1_INT_STATUS_UQM_ERR_UQM_INT   vxge_mBIT(7)
 
#define VXGE_HW_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT   vxge_mBIT(8)
 
#define VXGE_HW_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT   vxge_mBIT(0)
 
#define VXGE_HW_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT   vxge_mBIT(1)
 
#define VXGE_HW_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT   vxge_mBIT(2)
 
#define VXGE_HW_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT   vxge_mBIT(3)
 
#define VXGE_HW_ONE_INT_STATUS_RXPE_ERR_RXPE_INT   vxge_mBIT(7)
 
#define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT   vxge_mBIT(13)
 
#define VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT   vxge_mBIT(14)
 
#define VXGE_HW_ONE_INT_STATUS_TXPE_ERR_TXPE_INT   vxge_mBIT(15)
 
#define VXGE_HW_ONE_INT_STATUS_DLM_ERR_DLM_INT   vxge_mBIT(23)
 
#define VXGE_HW_ONE_INT_STATUS_PE_ERR_PE_INT   vxge_mBIT(31)
 
#define VXGE_HW_ONE_INT_STATUS_RPE_ERR_RPE_INT   vxge_mBIT(39)
 
#define VXGE_HW_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT   vxge_mBIT(47)
 
#define VXGE_HW_ONE_INT_STATUS_OES_ERR_OES_INT   vxge_mBIT(55)
 
#define VXGE_HW_NOA_WCT_CTRL_VP_INT_NUM   vxge_mBIT(0)
 
#define VXGE_HW_RC_CFG2_BUFF1_SIZE(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_RC_CFG2_BUFF2_SIZE(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_RC_CFG2_BUFF3_SIZE(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_RC_CFG2_BUFF4_SIZE(val)   vxge_vBIT(val, 48, 16)
 
#define VXGE_HW_RC_CFG3_BUFF5_SIZE(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_RX_MULTI_CAST_CTRL1_ENABLE   vxge_mBIT(7)
 
#define VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val)   vxge_vBIT(val, 11, 5)
 
#define VXGE_HW_RXDM_DBG_RD_ADDR(val)   vxge_vBIT(val, 0, 12)
 
#define VXGE_HW_RXDM_DBG_RD_ENABLE   vxge_mBIT(31)
 
#define VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val)   vxge_vBIT(val, 59, 5)
 
#define VXGE_HW_TIM_STATUS_TIM_RESET_IN_PROGRESS   vxge_mBIT(0)
 
#define VXGE_HW_TIM_ECC_ENABLE_VBLS_N   vxge_mBIT(7)
 
#define VXGE_HW_TIM_ECC_ENABLE_BMAP_N   vxge_mBIT(15)
 
#define VXGE_HW_TIM_ECC_ENABLE_BMAP_MSG_N   vxge_mBIT(23)
 
#define VXGE_HW_TIM_BP_CTRL_RD_XON   vxge_mBIT(7)
 
#define VXGE_HW_TIM_BP_CTRL_WR_XON   vxge_mBIT(15)
 
#define VXGE_HW_TIM_BP_CTRL_ROCRC_BYP   vxge_mBIT(23)
 
#define VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val)   vxge_vBIT(val, 0, 32)
 
#define VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val)   vxge_vBIT(val, 3, 5)
 
#define VXGE_HW_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT   vxge_mBIT(7)
 
#define VXGE_HW_GCMG2_INT_STATUS_GCP_ERR_GCP_INT   vxge_mBIT(15)
 
#define VXGE_HW_GCMG2_INT_STATUS_CMC_ERR_CMC_INT   vxge_mBIT(23)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val)   vxge_vBIT(val, 0, 4)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val)   vxge_vBIT(val, 4, 4)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR   vxge_mBIT(8)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR   vxge_mBIT(9)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR   vxge_mBIT(10)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR   vxge_mBIT(11)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR   vxge_mBIT(12)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR   vxge_mBIT(13)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR   vxge_mBIT(14)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR   vxge_mBIT(15)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR   vxge_mBIT(16)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR   vxge_mBIT(17)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR   vxge_mBIT(18)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR   vxge_mBIT(19)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR   vxge_mBIT(20)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW   vxge_mBIT(21)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW   vxge_mBIT(22)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR   vxge_mBIT(23)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW   vxge_mBIT(24)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW   vxge_mBIT(25)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR   vxge_mBIT(26)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR   vxge_mBIT(27)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR   vxge_mBIT(28)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR   vxge_mBIT(29)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR   vxge_mBIT(30)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR   vxge_mBIT(31)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR   vxge_mBIT(32)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR   vxge_mBIT(33)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR   vxge_mBIT(34)
 
#define VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR   vxge_mBIT(35)
 
#define VXGE_HW_CMC_ERR_REG_CMC_CMC_SM_ERR   vxge_mBIT(0)
 
#define VXGE_HW_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR   vxge_mBIT(0)
 
#define VXGE_HW_GCP_ERR_REG_CP_STC2CP_FIFO_ERR   vxge_mBIT(1)
 
#define VXGE_HW_GCP_ERR_REG_CP_STE2CP_FIFO_ERR   vxge_mBIT(2)
 
#define VXGE_HW_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR   vxge_mBIT(3)
 
#define VXGE_HW_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT   vxge_mBIT(7)
 
#define VXGE_HW_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT   vxge_mBIT(15)
 
#define VXGE_HW_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT   vxge_mBIT(23)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val)   vxge_vBIT(val, 0, 2)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR   vxge_mBIT(2)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR   vxge_mBIT(3)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR   vxge_mBIT(4)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR   vxge_mBIT(5)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR   vxge_mBIT(6)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR   vxge_mBIT(7)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR   vxge_mBIT(8)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR   vxge_mBIT(9)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR   vxge_mBIT(10)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR   vxge_mBIT(11)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR   vxge_mBIT(12)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR   vxge_mBIT(13)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR   vxge_mBIT(14)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR   vxge_mBIT(15)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR   vxge_mBIT(16)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR   vxge_mBIT(17)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR   vxge_mBIT(18)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR   vxge_mBIT(19)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR   vxge_mBIT(20)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR   vxge_mBIT(21)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR   vxge_mBIT(22)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR   vxge_mBIT(23)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR   vxge_mBIT(24)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR   vxge_mBIT(25)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR   vxge_mBIT(26)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR   vxge_mBIT(27)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR   vxge_mBIT(28)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR   vxge_mBIT(29)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR   vxge_mBIT(30)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR   vxge_mBIT(31)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR   vxge_mBIT(32)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR   vxge_mBIT(33)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR   vxge_mBIT(34)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR   vxge_mBIT(35)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR   vxge_mBIT(36)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR   vxge_mBIT(37)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR   vxge_mBIT(38)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR   vxge_mBIT(39)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR   vxge_mBIT(40)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR   vxge_mBIT(41)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR   vxge_mBIT(42)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR   vxge_mBIT(43)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR   vxge_mBIT(44)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR   vxge_mBIT(45)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR   vxge_mBIT(46)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR   vxge_mBIT(47)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR   vxge_mBIT(48)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR   vxge_mBIT(49)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR   vxge_mBIT(50)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR   vxge_mBIT(51)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR   vxge_mBIT(52)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR   vxge_mBIT(53)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val)   vxge_vBIT(val, 54, 2)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR   vxge_mBIT(56)
 
#define VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR   vxge_mBIT(57)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val)   vxge_vBIT(val, 8, 2)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_SG_ERR   vxge_mBIT(10)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_SG_ERR   vxge_mBIT(11)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_SG_ERR   vxge_mBIT(12)
 
#define VXGE_HW_CP_ERR_REG_CP_DMA2CP_SG_ERR   vxge_mBIT(13)
 
#define VXGE_HW_CP_ERR_REG_CP_MP2CP_SG_ERR   vxge_mBIT(14)
 
#define VXGE_HW_CP_ERR_REG_CP_QCC2CP_SG_ERR   vxge_mBIT(15)
 
#define VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR(val)   vxge_vBIT(val, 16, 2)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val)   vxge_vBIT(val, 24, 8)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val)   vxge_vBIT(val, 32, 2)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_DTAG_DB_ERR   vxge_mBIT(34)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_ITAG_DB_ERR   vxge_mBIT(35)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_TRACE_DB_ERR   vxge_mBIT(36)
 
#define VXGE_HW_CP_ERR_REG_CP_DMA2CP_DB_ERR   vxge_mBIT(37)
 
#define VXGE_HW_CP_ERR_REG_CP_MP2CP_DB_ERR   vxge_mBIT(38)
 
#define VXGE_HW_CP_ERR_REG_CP_QCC2CP_DB_ERR   vxge_mBIT(39)
 
#define VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR(val)   vxge_vBIT(val, 40, 2)
 
#define VXGE_HW_CP_ERR_REG_CP_H2L2CP_FIFO_ERR   vxge_mBIT(48)
 
#define VXGE_HW_CP_ERR_REG_CP_STC2CP_FIFO_ERR   vxge_mBIT(49)
 
#define VXGE_HW_CP_ERR_REG_CP_STE2CP_FIFO_ERR   vxge_mBIT(50)
 
#define VXGE_HW_CP_ERR_REG_CP_TTE2CP_FIFO_ERR   vxge_mBIT(51)
 
#define VXGE_HW_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR   vxge_mBIT(52)
 
#define VXGE_HW_CP_ERR_REG_CP_CP2DMA_FIFO_ERR   vxge_mBIT(53)
 
#define VXGE_HW_CP_ERR_REG_CP_DAM2CP_FIFO_ERR   vxge_mBIT(54)
 
#define VXGE_HW_CP_ERR_REG_CP_MP2CP_FIFO_ERR   vxge_mBIT(55)
 
#define VXGE_HW_CP_ERR_REG_CP_QCC2CP_FIFO_ERR   vxge_mBIT(56)
 
#define VXGE_HW_CP_ERR_REG_CP_DMA2CP_FIFO_ERR   vxge_mBIT(57)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR   vxge_mBIT(60)
 
#define VXGE_HW_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR   vxge_mBIT(61)
 
#define VXGE_HW_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR   vxge_mBIT(62)
 
#define VXGE_HW_CP_ERR_REG_CP_PIFT_CREDIT_ERR   vxge_mBIT(63)
 
#define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_INFO_INT   vxge_mBIT(47)
 
#define VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT   vxge_mBIT(55)
 
#define VXGE_HW_CP_EXC_REG_CP_CP_SERR   vxge_mBIT(63)
 
#define VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_MSG_INT_STATUS_TIM_ERR_TIM_INT   vxge_mBIT(7)
 
#define VXGE_HW_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT   vxge_mBIT(60)
 
#define VXGE_HW_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT   vxge_mBIT(61)
 
#define VXGE_HW_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT   vxge_mBIT(62)
 
#define VXGE_HW_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT   vxge_mBIT(63)
 
#define VXGE_HW_TIM_ERR_REG_TIM_VBLS_SG_ERR   vxge_mBIT(4)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR   vxge_mBIT(5)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR   vxge_mBIT(6)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR   vxge_mBIT(7)
 
#define VXGE_HW_TIM_ERR_REG_TIM_VBLS_DB_ERR   vxge_mBIT(12)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR   vxge_mBIT(13)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR   vxge_mBIT(14)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR   vxge_mBIT(15)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR   vxge_mBIT(18)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR   vxge_mBIT(19)
 
#define VXGE_HW_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR   vxge_mBIT(20)
 
#define VXGE_HW_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR   vxge_mBIT(22)
 
#define VXGE_HW_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR   vxge_mBIT(23)
 
#define VXGE_HW_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH   vxge_mBIT(46)
 
#define VXGE_HW_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n)   vxge_mBIT(n)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR   vxge_mBIT(0)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR   vxge_mBIT(1)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR   vxge_mBIT(2)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR   vxge_mBIT(3)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR   vxge_mBIT(4)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR   vxge_mBIT(5)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR   vxge_mBIT(6)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR   vxge_mBIT(7)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR   vxge_mBIT(8)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR   vxge_mBIT(10)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR   vxge_mBIT(12)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR   vxge_mBIT(14)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR   vxge_mBIT(16)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR   vxge_mBIT(17)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR   vxge_mBIT(18)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR   vxge_mBIT(19)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR   vxge_mBIT(20)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR   vxge_mBIT(21)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR   vxge_mBIT(26)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR   vxge_mBIT(27)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR   vxge_mBIT(29)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR   vxge_mBIT(31)
 
#define VXGE_HW_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR   vxge_mBIT(33)
 
#define VXGE_HW_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR   vxge_mBIT(34)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR   vxge_mBIT(35)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR   vxge_mBIT(36)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR   vxge_mBIT(38)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR   vxge_mBIT(39)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR   vxge_mBIT(41)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR   vxge_mBIT(43)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR   vxge_mBIT(45)
 
#define VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR   vxge_mBIT(47)
 
#define VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR   vxge_mBIT(48)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR   vxge_mBIT(49)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR   vxge_mBIT(50)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR   vxge_mBIT(51)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR   vxge_mBIT(52)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR   vxge_mBIT(53)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR   vxge_mBIT(54)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR   vxge_mBIT(55)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR   vxge_mBIT(56)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR   vxge_mBIT(57)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR   vxge_mBIT(58)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR   vxge_mBIT(59)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR   vxge_mBIT(60)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR   vxge_mBIT(61)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR   vxge_mBIT(62)
 
#define VXGE_HW_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR   vxge_mBIT(63)
 
#define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT   vxge_mBIT(50)
 
#define VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT   vxge_mBIT(51)
 
#define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT   vxge_mBIT(54)
 
#define VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT   vxge_mBIT(55)
 
#define VXGE_HW_MSG_EXC_REG_MP_MXP_SERR   vxge_mBIT(62)
 
#define VXGE_HW_MSG_EXC_REG_UP_UXP_SERR   vxge_mBIT(63)
 
#define VXGE_HW_MSG_EXC_CAUSE_MP_MXP(val)   vxge_vBIT(val, 0, 32)
 
#define VXGE_HW_MSG_EXC_CAUSE_UP_UXP(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR   vxge_mBIT(0)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR   vxge_mBIT(1)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR   vxge_mBIT(2)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR   vxge_mBIT(3)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR   vxge_mBIT(4)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR   vxge_mBIT(5)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR   vxge_mBIT(6)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR   vxge_mBIT(7)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR   vxge_mBIT(8)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR   vxge_mBIT(9)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR   vxge_mBIT(10)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR   vxge_mBIT(11)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR   vxge_mBIT(12)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR   vxge_mBIT(13)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR   vxge_mBIT(14)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR   vxge_mBIT(15)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR   vxge_mBIT(16)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR   vxge_mBIT(17)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR   vxge_mBIT(18)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR   vxge_mBIT(19)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR   vxge_mBIT(20)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR   vxge_mBIT(21)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR   vxge_mBIT(22)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR   vxge_mBIT(23)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR   vxge_mBIT(24)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR   vxge_mBIT(25)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR   vxge_mBIT(26)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR   vxge_mBIT(27)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR   vxge_mBIT(28)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR   vxge_mBIT(29)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR   vxge_mBIT(30)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR   vxge_mBIT(31)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR   vxge_mBIT(32)
 
#define VXGE_HW_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR   vxge_mBIT(33)
 
#define VXGE_HW_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR   vxge_mBIT(34)
 
#define VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR   vxge_mBIT(62)
 
#define VXGE_HW_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR   vxge_mBIT(63)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0   vxge_mBIT(0)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1   vxge_mBIT(1)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2   vxge_mBIT(2)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3   vxge_mBIT(3)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4   vxge_mBIT(4)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5   vxge_mBIT(5)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6   vxge_mBIT(6)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7   vxge_mBIT(7)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0   vxge_mBIT(8)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1   vxge_mBIT(9)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0   vxge_mBIT(16)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1   vxge_mBIT(17)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2   vxge_mBIT(18)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3   vxge_mBIT(19)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4   vxge_mBIT(20)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5   vxge_mBIT(21)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6   vxge_mBIT(22)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7   vxge_mBIT(23)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0   vxge_mBIT(24)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1   vxge_mBIT(25)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0   vxge_mBIT(32)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1   vxge_mBIT(33)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2   vxge_mBIT(34)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3   vxge_mBIT(35)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4   vxge_mBIT(36)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5   vxge_mBIT(37)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6   vxge_mBIT(38)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7   vxge_mBIT(39)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0   vxge_mBIT(40)
 
#define VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1   vxge_mBIT(41)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0   vxge_mBIT(48)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1   vxge_mBIT(49)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2   vxge_mBIT(50)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3   vxge_mBIT(51)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4   vxge_mBIT(52)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5   vxge_mBIT(53)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6   vxge_mBIT(54)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7   vxge_mBIT(55)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0   vxge_mBIT(56)
 
#define VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1   vxge_mBIT(57)
 
#define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP   vxge_mBIT(3)
 
#define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP   vxge_mBIT(7)
 
#define VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP   vxge_mBIT(11)
 
#define VXGE_HW_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIFICATION   vxge_mBIT(15)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR   vxge_mBIT(0)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR   vxge_mBIT(1)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val)   vxge_vBIT(val, 2, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val)   vxge_vBIT(val, 4, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR   vxge_mBIT(6)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR   vxge_mBIT(7)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val)   vxge_vBIT(val, 8, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val)   vxge_vBIT(val, 10, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR   vxge_mBIT(12)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR   vxge_mBIT(13)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val)   vxge_vBIT(val, 14, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val)   vxge_vBIT(val, 16, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val)   vxge_vBIT(val, 18, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val)   vxge_vBIT(val, 20, 2)
 
#define VXGE_HW_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR   vxge_mBIT(31)
 
#define VXGE_HW_FAU_PA_CFG_REPL_L4_COMP_CSUM   vxge_mBIT(3)
 
#define VXGE_HW_FAU_PA_CFG_REPL_L3_INCL_CF   vxge_mBIT(7)
 
#define VXGE_HW_FAU_PA_CFG_REPL_L3_COMP_CSUM   vxge_mBIT(11)
 
#define VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_FAU_LAG_CFG_COLL_ALG(val)   vxge_vBIT(val, 2, 2)
 
#define VXGE_HW_FAU_LAG_CFG_INCR_RX_AGGR_STATS   vxge_mBIT(7)
 
#define VXGE_HW_TPA_INT_STATUS_ORP_ERR_ORP_INT   vxge_mBIT(15)
 
#define VXGE_HW_TPA_INT_STATUS_PTM_ALARM_PTM_INT   vxge_mBIT(23)
 
#define VXGE_HW_TPA_INT_STATUS_TPA_ERROR_TPA_INT   vxge_mBIT(31)
 
#define VXGE_HW_ORP_ERR_REG_ORP_FIFO_SG_ERR   vxge_mBIT(3)
 
#define VXGE_HW_ORP_ERR_REG_ORP_FIFO_DB_ERR   vxge_mBIT(7)
 
#define VXGE_HW_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR   vxge_mBIT(11)
 
#define VXGE_HW_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR   vxge_mBIT(15)
 
#define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR   vxge_mBIT(19)
 
#define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR   vxge_mBIT(23)
 
#define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR   vxge_mBIT(27)
 
#define VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR   vxge_mBIT(31)
 
#define VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR   vxge_mBIT(35)
 
#define VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR   vxge_mBIT(39)
 
#define VXGE_HW_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR   vxge_mBIT(43)
 
#define VXGE_HW_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR   vxge_mBIT(47)
 
#define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR   vxge_mBIT(3)
 
#define VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR   vxge_mBIT(7)
 
#define VXGE_HW_PTM_ALARM_REG_XFMD_RD_FIFO_ERR   vxge_mBIT(11)
 
#define VXGE_HW_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR   vxge_mBIT(15)
 
#define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val)   vxge_vBIT(val, 18, 2)
 
#define VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val)   vxge_vBIT(val, 22, 2)
 
#define VXGE_HW_TPA_ERROR_REG_TPA_FSM_ERR_ALARM   vxge_mBIT(3)
 
#define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR   vxge_mBIT(7)
 
#define VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR   vxge_mBIT(11)
 
#define VXGE_HW_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N   vxge_mBIT(7)
 
#define VXGE_HW_TPA_GLOBAL_CFG_ECC_ENABLE_N   vxge_mBIT(35)
 
#define VXGE_HW_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N   vxge_mBIT(3)
 
#define VXGE_HW_PTM_PHASE_CFG_FRMM_WR_PHASE_EN   vxge_mBIT(3)
 
#define VXGE_HW_PTM_PHASE_CFG_FRMM_RD_PHASE_EN   vxge_mBIT(7)
 
#define VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT   vxge_mBIT(3)
 
#define VXGE_HW_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT   vxge_mBIT(7)
 
#define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP   vxge_mBIT(3)
 
#define VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT   vxge_mBIT(7)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR   vxge_mBIT(3)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR   vxge_mBIT(7)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR   vxge_mBIT(11)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR   vxge_mBIT(15)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR   vxge_mBIT(19)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR   vxge_mBIT(23)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR   vxge_mBIT(27)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR   vxge_mBIT(31)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR   vxge_mBIT(35)
 
#define VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR   vxge_mBIT(39)
 
#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val)   vxge_vBIT(val, 1, 7)
 
#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val)   vxge_vBIT(val, 8, 4)
 
#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val)   vxge_vBIT(val, 12, 4)
 
#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val)   vxge_vBIT(val, 16, 4)
 
#define VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR   vxge_mBIT(23)
 
#define VXGE_HW_TXMAC_CFG0_PORT_TMAC_EN   vxge_mBIT(3)
 
#define VXGE_HW_TXMAC_CFG0_PORT_APPEND_PAD   vxge_mBIT(7)
 
#define VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG(val)   vxge_vBIT(val, 40, 8)
 
#define VXGE_HW_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT   vxge_mBIT(3)
 
#define VXGE_HW_LAG_DISTRIB_DEST_MAP_VPATH(n)   vxge_mBIT(n)
 
#define VXGE_HW_LAG_MARKER_CFG_GEN_RCVR_EN   vxge_mBIT(3)
 
#define VXGE_HW_LAG_MARKER_CFG_RESP_EN   vxge_mBIT(7)
 
#define VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_LAG_MARKER_CFG_THROTTLE_MRKR_RESP   vxge_mBIT(51)
 
#define VXGE_HW_LAG_TX_CFG_INCR_TX_AGGR_STATS   vxge_mBIT(3)
 
#define VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL(val)   vxge_vBIT(val, 6, 2)
 
#define VXGE_HW_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL   vxge_mBIT(11)
 
#define VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val)   vxge_vBIT(val, 0, 8)
 
#define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val)   vxge_vBIT(val, 8, 8)
 
#define VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val)   vxge_vBIT(val, 16, 8)
 
#define VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG(val)   vxge_vBIT(val, 0, 64)
 
#define VXGE_HW_DEBUG_STATS0_RSTDROP_MSG(val)   vxge_vBIT(val, 0, 32)
 
#define VXGE_HW_DEBUG_STATS0_RSTDROP_CPL(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0(val)   vxge_vBIT(val, 0, 32)
 
#define VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1(val)   vxge_vBIT(val, 32, 32)
 
#define VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2(val)   vxge_vBIT(val, 0, 32)
 
#define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD(val)   vxge_vBIT(val, 0, 16)
 
#define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD(val)   vxge_vBIT(val, 16, 16)
 
#define VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD(val)   vxge_vBIT(val, 32, 16)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PIC_INT   vxge_mBIT(0)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCI_INT   vxge_mBIT(1)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT   vxge_mBIT(2)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT   vxge_mBIT(3)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT   vxge_mBIT(4)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT   vxge_mBIT(5)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT   vxge_mBIT(6)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT   vxge_mBIT(7)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT   vxge_mBIT(8)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT   vxge_mBIT(9)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT   vxge_mBIT(10)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT   vxge_mBIT(11)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT   vxge_mBIT(12)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_XMAC_INT   vxge_mBIT(13)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT   vxge_mBIT(14)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TMAC_INT   vxge_mBIT(15)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT   vxge_mBIT(16)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_FBMC_INT   vxge_mBIT(17)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT   vxge_mBIT(18)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TPA_INT   vxge_mBIT(19)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT   vxge_mBIT(20)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_ONE_INT   vxge_mBIT(21)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_STATUS_MSG_INT   vxge_mBIT(22)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PIC_INT   vxge_mBIT(0)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCI_INT   vxge_mBIT(1)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RTDMA_INT   vxge_mBIT(2)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_WRDMA_INT   vxge_mBIT(3)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT   vxge_mBIT(4)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG1_INT   vxge_mBIT(5)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG2_INT   vxge_mBIT(6)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG3_INT   vxge_mBIT(7)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT   vxge_mBIT(8)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT   vxge_mBIT(9)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG1_INT   vxge_mBIT(10)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG2_INT   vxge_mBIT(11)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG3_INT   vxge_mBIT(12)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_XMAC_INT   vxge_mBIT(13)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_RXMAC_INT   vxge_mBIT(14)
 
#define VXGE_HW_MRPCIM_GENERAL_INT_MASK_TMAC_INT   vxge_mBIT(15)