vxge_traffic.h File Reference

#include <stdint.h>
#include <ipxe/if_ether.h>
#include <ipxe/iobuf.h>
#include "vxge_reg.h"
#include "vxge_version.h"

Go to the source code of this file.

Macros
#define	VXGE_TRAFFIC_H
#define	VXGE_HW_DTR_MAX_T_CODE   16
#define	VXGE_HW_ALL_FOXES   0xFFFFFFFFFFFFFFFFULL
#define	VXGE_HW_INTR_MASK_ALL   0xFFFFFFFFFFFFFFFFULL
#define	VXGE_HW_MAX_VIRTUAL_PATHS   17
#define	VXGE_HW_MAX_VIRTUAL_FUNCTIONS   8
#define	VXGE_HW_MAC_MAX_MAC_PORT_ID   3
#define	VXGE_HW_DEFAULT_32   0xffffffff
#define	VXGE_HW_HEADER_802_2_SIZE   3
#define	VXGE_HW_HEADER_SNAP_SIZE   5
#define	VXGE_HW_HEADER_VLAN_SIZE   4
#define	VXGE_HW_MAC_HEADER_MAX_SIZE
#define	VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN   0x12
#define	VXGE_HW_HEADER_802_2_SNAP_ALIGN   2
#define	VXGE_HW_HEADER_802_2_ALIGN   3
#define	VXGE_HW_HEADER_SNAP_ALIGN   1
#define	VXGE_HW_L3_CKSUM_OK   0xFFFF
#define	VXGE_HW_L4_CKSUM_OK   0xFFFF
#define	TRUE   1
#define	FALSE   0
#define	VXGE_HW_EVENT_BASE   0
#define	VXGE_LL_EVENT_BASE   100
#define	VXGE_HW_MAX_INTR_PER_VP   4
#define	VXGE_HW_VPATH_INTR_TX   0
#define	VXGE_HW_VPATH_INTR_RX   1
#define	VXGE_HW_VPATH_INTR_EINTA   2
#define	VXGE_HW_VPATH_INTR_BMAP   3
#define	VXGE_HW_BLOCK_SIZE   4096
#define	VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL   17
#define	VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL   18
#define	VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL   19
#define	VXGE_HW_TIM_UTIL_SEL_PER_VPATH   63

Enumerations
enum	vxge_hw_event {   VXGE_HW_EVENT_UNKNOWN = 0 , VXGE_HW_EVENT_RESET_START = VXGE_HW_EVENT_BASE + 1 , VXGE_HW_EVENT_RESET_COMPLETE = VXGE_HW_EVENT_BASE + 2 , VXGE_HW_EVENT_LINK_DOWN = VXGE_HW_EVENT_BASE + 3 ,   VXGE_HW_EVENT_LINK_UP = VXGE_HW_EVENT_BASE + 4 , VXGE_HW_EVENT_ALARM_CLEARED = VXGE_HW_EVENT_BASE + 5 , VXGE_HW_EVENT_ECCERR = VXGE_HW_EVENT_BASE + 6 , VXGE_HW_EVENT_MRPCIM_ECCERR = VXGE_HW_EVENT_BASE + 7 ,   VXGE_HW_EVENT_FIFO_ERR = VXGE_HW_EVENT_BASE + 8 , VXGE_HW_EVENT_VPATH_ERR = VXGE_HW_EVENT_BASE + 9 , VXGE_HW_EVENT_CRITICAL_ERR = VXGE_HW_EVENT_BASE + 10 , VXGE_HW_EVENT_SERR = VXGE_HW_EVENT_BASE + 11 ,   VXGE_HW_EVENT_SRPCIM_SERR = VXGE_HW_EVENT_BASE + 12 , VXGE_HW_EVENT_MRPCIM_SERR = VXGE_HW_EVENT_BASE + 13 , VXGE_HW_EVENT_SLOT_FREEZE = VXGE_HW_EVENT_BASE + 14 }
	enum vxge_hw_event- Enumerates slow-path HW events. More...
enum	vxge_hw_ring_tcode {   VXGE_HW_RING_T_CODE_OK = 0x0 , VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH = 0x1 , VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH = 0x2 , VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH = 0x3 ,   VXGE_HW_RING_T_CODE_L3_PKT_ERR = 0x5 , VXGE_HW_RING_T_CODE_L2_FRM_ERR = 0x6 , VXGE_HW_RING_T_CODE_BUF_SIZE_ERR = 0x7 , VXGE_HW_RING_T_CODE_INT_ECC_ERR = 0x8 ,   VXGE_HW_RING_T_CODE_BENIGN_OVFLOW = 0x9 , VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF = 0xA , VXGE_HW_RING_T_CODE_FRM_DROP = 0xC , VXGE_HW_RING_T_CODE_UNUSED = 0xE ,   VXGE_HW_RING_T_CODE_MULTI_ERR = 0xF }
	enum vxge_hw_ring_tcode - Transfer codes returned by adapter @VXGE_HW_RING_T_CODE_OK: Transfer ok. More...
enum	vxge_hw_fifo_gather_code { VXGE_HW_FIFO_GATHER_CODE_FIRST = 0x2 , VXGE_HW_FIFO_GATHER_CODE_MIDDLE = 0x0 , VXGE_HW_FIFO_GATHER_CODE_LAST = 0x1 , VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST = 0x3 }
	enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL. More...
enum	vxge_hw_fifo_tcode {   VXGE_HW_FIFO_T_CODE_OK = 0x0 , VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1 , VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL = 0x2 , VXGE_HW_FIFO_T_CODE_INVALID_MSS = 0x3 ,   VXGE_HW_FIFO_T_CODE_LSO_ERROR = 0x4 , VXGE_HW_FIFO_T_CODE_UNUSED = 0x7 , VXGE_HW_FIFO_T_CODE_MULTI_ERROR = 0x8 }
	enum enum vxge_hw_fifo_tcode - tcodes used in fifo @VXGE_HW_FIFO_T_CODE_OK: Transfer OK @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or frame data) returned with corrupt data. More...

Functions
	FILE_LICENCE (GPL2_ONLY)
enum vxge_hw_status	vxge_hw_ring_replenish (struct __vxge_hw_ring *ring)
void	vxge_hw_ring_rxd_post (struct __vxge_hw_ring *ring_handle, struct vxge_hw_ring_rxd_1 *rxdp)
void	vxge_hw_fifo_txdl_buffer_set (struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp, struct io_buffer *iob)
	vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.
void	vxge_hw_fifo_txdl_post (struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp)
	vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
enum vxge_hw_status	__vxge_hw_ring_create (struct __vxge_hw_virtualpath *vpath, struct __vxge_hw_ring *ring)
enum vxge_hw_status	__vxge_hw_ring_delete (struct __vxge_hw_ring *ringh)
enum vxge_hw_status	__vxge_hw_fifo_create (struct __vxge_hw_virtualpath *vpath, struct __vxge_hw_fifo *fifo)
enum vxge_hw_status	__vxge_hw_fifo_delete (struct __vxge_hw_fifo *fifo)
enum vxge_hw_status	__vxge_hw_vpath_reset (struct __vxge_hw_device *devh, u32 vp_id)
enum vxge_hw_status	__vxge_hw_vpath_enable (struct __vxge_hw_device *devh, u32 vp_id)
void	__vxge_hw_vpath_prc_configure (struct __vxge_hw_device *hldev)
enum vxge_hw_status	__vxge_hw_vpath_kdfc_configure (struct __vxge_hw_device *devh, u32 vp_id)
enum vxge_hw_status	__vxge_hw_vpath_mac_configure (struct __vxge_hw_device *devh)
enum vxge_hw_status	__vxge_hw_vpath_tim_configure (struct __vxge_hw_device *devh, u32 vp_id)
enum vxge_hw_status	__vxge_hw_vpath_initialize (struct __vxge_hw_device *devh, u32 vp_id)
enum vxge_hw_status	__vxge_hw_vp_initialize (struct __vxge_hw_device *hldev, u32 vp_id, struct __vxge_hw_virtualpath *vpath)
void	__vxge_hw_vp_terminate (struct __vxge_hw_device *hldev, struct __vxge_hw_virtualpath *vpath)
enum vxge_hw_status	vxge_hw_device_begin_irq (struct __vxge_hw_device *hldev)
	vxge_hw_device_begin_irq - Begin IRQ processing.
void	vxge_hw_device_intr_enable (struct __vxge_hw_device *hldev)
	vxge_hw_device_intr_enable - Enable interrupts.
void	vxge_hw_device_intr_disable (struct __vxge_hw_device *hldev)
	vxge_hw_device_intr_disable - Disable Titan interrupts.
void	vxge_hw_device_mask_all (struct __vxge_hw_device *hldev)
	vxge_hw_device_mask_all - Mask all device interrupts.
void	vxge_hw_device_unmask_all (struct __vxge_hw_device *hldev)
	vxge_hw_device_unmask_all - Unmask all device interrupts.
void	vxge_hw_vpath_doorbell_rx (struct __vxge_hw_ring *ringh)
	vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.
enum vxge_hw_status	vxge_hw_vpath_poll_rx (struct __vxge_hw_ring *ringh)
enum vxge_hw_status	vxge_hw_vpath_poll_tx (struct __vxge_hw_fifo *fifo)
	vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.
struct vxge_hw_fifo_txd *	vxge_hw_fifo_free_txdl_get (struct __vxge_hw_fifo *fifo)
	vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo

Macro Definition Documentation

VXGE_TRAFFIC_H

#define VXGE_TRAFFIC_H

Definition at line 18 of file vxge_traffic.h.

VXGE_HW_DTR_MAX_T_CODE

#define VXGE_HW_DTR_MAX_T_CODE   16

Definition at line 27 of file vxge_traffic.h.

VXGE_HW_ALL_FOXES

#define VXGE_HW_ALL_FOXES   0xFFFFFFFFFFFFFFFFULL

Definition at line 28 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_alarm_process(), and vxge_hw_device_begin_irq().

VXGE_HW_INTR_MASK_ALL

#define VXGE_HW_INTR_MASK_ALL   0xFFFFFFFFFFFFFFFFULL

Definition at line 29 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_alarm_process(), __vxge_hw_vpath_pci_read(), vxge_hw_device_intr_disable(), vxge_hw_vpath_intr_disable(), and vxge_hw_vpath_intr_enable().

VXGE_HW_MAX_VIRTUAL_PATHS

#define VXGE_HW_MAX_VIRTUAL_PATHS   17

Definition at line 30 of file vxge_traffic.h.

Referenced by __vxge_hw_device_host_info_get(), __vxge_hw_vpath_initialize(), vxge_hw_device_hw_info::u8(), vxge_hw_device_hw_info::u8(), vxge_hw_device_begin_irq(), vxge_hw_device_hw_info_get(), vxge_hw_vpath_strip_fcs_check(), and vxge_probe().

VXGE_HW_MAX_VIRTUAL_FUNCTIONS

#define VXGE_HW_MAX_VIRTUAL_FUNCTIONS   8

Definition at line 32 of file vxge_traffic.h.

VXGE_HW_MAC_MAX_MAC_PORT_ID

#define VXGE_HW_MAC_MAX_MAC_PORT_ID   3

Definition at line 34 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_mgmt_read(), and vxge_hw_vpath_strip_fcs_check().

VXGE_HW_DEFAULT_32

#define VXGE_HW_DEFAULT_32   0xffffffff

Definition at line 36 of file vxge_traffic.h.

Referenced by vxge_hw_device_intr_disable().

VXGE_HW_HEADER_802_2_SIZE

#define VXGE_HW_HEADER_802_2_SIZE   3

Definition at line 38 of file vxge_traffic.h.

VXGE_HW_HEADER_SNAP_SIZE

#define VXGE_HW_HEADER_SNAP_SIZE   5

Definition at line 39 of file vxge_traffic.h.

VXGE_HW_HEADER_VLAN_SIZE

#define VXGE_HW_HEADER_VLAN_SIZE   4

Definition at line 40 of file vxge_traffic.h.

VXGE_HW_MAC_HEADER_MAX_SIZE

#define VXGE_HW_MAC_HEADER_MAX_SIZE

Value:

                        (ETH_HLEN + \
                        VXGE_HW_HEADER_802_2_SIZE + \
                        VXGE_HW_HEADER_VLAN_SIZE + \
                        VXGE_HW_HEADER_SNAP_SIZE)

Definition at line 41 of file vxge_traffic.h.

#define VXGE_HW_MAC_HEADER_MAX_SIZE \
                        (ETH_HLEN + \
                        VXGE_HW_HEADER_802_2_SIZE + \
                        VXGE_HW_HEADER_VLAN_SIZE + \
                        VXGE_HW_HEADER_SNAP_SIZE)

Referenced by __vxge_hw_vpath_mgmt_read(), and vxge_hw_vpath_mtu_set().

VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN

#define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN   0x12

Definition at line 61 of file vxge_traffic.h.

VXGE_HW_HEADER_802_2_SNAP_ALIGN

#define VXGE_HW_HEADER_802_2_SNAP_ALIGN   2

Definition at line 62 of file vxge_traffic.h.

VXGE_HW_HEADER_802_2_ALIGN

#define VXGE_HW_HEADER_802_2_ALIGN   3

Definition at line 63 of file vxge_traffic.h.

VXGE_HW_HEADER_SNAP_ALIGN

#define VXGE_HW_HEADER_SNAP_ALIGN   1

Definition at line 64 of file vxge_traffic.h.

VXGE_HW_L3_CKSUM_OK

#define VXGE_HW_L3_CKSUM_OK   0xFFFF

Definition at line 66 of file vxge_traffic.h.

VXGE_HW_L4_CKSUM_OK

#define VXGE_HW_L4_CKSUM_OK   0xFFFF

Definition at line 67 of file vxge_traffic.h.

TRUE

#define TRUE   1

Definition at line 78 of file vxge_traffic.h.

FALSE

#define FALSE   0

Definition at line 82 of file vxge_traffic.h.

VXGE_HW_EVENT_BASE

#define VXGE_HW_EVENT_BASE   0

Definition at line 86 of file vxge_traffic.h.

VXGE_LL_EVENT_BASE

#define VXGE_LL_EVENT_BASE   100

Definition at line 87 of file vxge_traffic.h.

VXGE_HW_MAX_INTR_PER_VP

#define VXGE_HW_MAX_INTR_PER_VP   4

Definition at line 129 of file vxge_traffic.h.

Referenced by __vxge_hw_fifo_create(), and __vxge_hw_vpath_tim_configure().

VXGE_HW_VPATH_INTR_TX

#define VXGE_HW_VPATH_INTR_TX   0

Definition at line 130 of file vxge_traffic.h.

Referenced by __vxge_hw_fifo_create(), __vxge_hw_vpath_tim_configure(), vxge_hw_device_clear_tx_rx(), and vxge_hw_device_intr_enable().

VXGE_HW_VPATH_INTR_RX

#define VXGE_HW_VPATH_INTR_RX   1

Definition at line 131 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_tim_configure(), vxge_hw_device_clear_tx_rx(), and vxge_hw_device_intr_enable().

VXGE_HW_VPATH_INTR_EINTA

#define VXGE_HW_VPATH_INTR_EINTA   2

Definition at line 132 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_tim_configure().

VXGE_HW_VPATH_INTR_BMAP

#define VXGE_HW_VPATH_INTR_BMAP   3

Definition at line 133 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_tim_configure().

VXGE_HW_BLOCK_SIZE

#define VXGE_HW_BLOCK_SIZE   4096

Definition at line 135 of file vxge_traffic.h.

VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL

#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL   17

Definition at line 137 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_tim_configure().

VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL

#define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL   18

Definition at line 138 of file vxge_traffic.h.

Referenced by __vxge_hw_vpath_tim_configure().

VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL

#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL   19

Definition at line 139 of file vxge_traffic.h.

VXGE_HW_TIM_UTIL_SEL_PER_VPATH

#define VXGE_HW_TIM_UTIL_SEL_PER_VPATH   63

Definition at line 140 of file vxge_traffic.h.

Enumeration Type Documentation

vxge_hw_event

enum vxge_hw_event

enum vxge_hw_event- Enumerates slow-path HW events.

@VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event. @VXGE_HW_EVENT_SERR: Serious vpath hardware error event. @VXGE_HW_EVENT_ECCERR: vpath ECC error event. @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error. @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event. @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event. @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event. @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish slot-freeze from the rest critical events (e.g. ECC) when it is impossible to PIO read "through" the bus, i.e. when getting all-foxes.

enum vxge_hw_event enumerates slow-path HW eventis.

See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{}, vxge_uld_link_down_f{}.

Enumerator
VXGE_HW_EVENT_UNKNOWN
VXGE_HW_EVENT_RESET_START
VXGE_HW_EVENT_RESET_COMPLETE
VXGE_HW_EVENT_LINK_DOWN
VXGE_HW_EVENT_LINK_UP
VXGE_HW_EVENT_ALARM_CLEARED
VXGE_HW_EVENT_ECCERR
VXGE_HW_EVENT_MRPCIM_ECCERR
VXGE_HW_EVENT_FIFO_ERR
VXGE_HW_EVENT_VPATH_ERR
VXGE_HW_EVENT_CRITICAL_ERR
VXGE_HW_EVENT_SERR
VXGE_HW_EVENT_SRPCIM_SERR
VXGE_HW_EVENT_MRPCIM_SERR
VXGE_HW_EVENT_SLOT_FREEZE

Definition at line 110 of file vxge_traffic.h.

                   {
        VXGE_HW_EVENT_UNKNOWN           = 0,
        /* HW events */
        VXGE_HW_EVENT_RESET_START       = VXGE_HW_EVENT_BASE + 1,
        VXGE_HW_EVENT_RESET_COMPLETE    = VXGE_HW_EVENT_BASE + 2,
        VXGE_HW_EVENT_LINK_DOWN         = VXGE_HW_EVENT_BASE + 3,
        VXGE_HW_EVENT_LINK_UP           = VXGE_HW_EVENT_BASE + 4,
        VXGE_HW_EVENT_ALARM_CLEARED     = VXGE_HW_EVENT_BASE + 5,
        VXGE_HW_EVENT_ECCERR            = VXGE_HW_EVENT_BASE + 6,
        VXGE_HW_EVENT_MRPCIM_ECCERR     = VXGE_HW_EVENT_BASE + 7,
        VXGE_HW_EVENT_FIFO_ERR          = VXGE_HW_EVENT_BASE + 8,
        VXGE_HW_EVENT_VPATH_ERR         = VXGE_HW_EVENT_BASE + 9,
        VXGE_HW_EVENT_CRITICAL_ERR      = VXGE_HW_EVENT_BASE + 10,
        VXGE_HW_EVENT_SERR              = VXGE_HW_EVENT_BASE + 11,
        VXGE_HW_EVENT_SRPCIM_SERR       = VXGE_HW_EVENT_BASE + 12,
        VXGE_HW_EVENT_MRPCIM_SERR       = VXGE_HW_EVENT_BASE + 13,
        VXGE_HW_EVENT_SLOT_FREEZE       = VXGE_HW_EVENT_BASE + 14,
};

vxge_hw_ring_tcode

enum vxge_hw_ring_tcode

enum vxge_hw_ring_tcode - Transfer codes returned by adapter @VXGE_HW_RING_T_CODE_OK: Transfer ok.

@VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation configuration mismatch. @VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation configuration mismatch. @VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum presentation configuration mismatch. @VXGE_HW_RING_T_CODE_L3_PKT_ERR: Layer 3 error unparseable packet, such as unknown IPv6 header. @VXGE_HW_RING_T_CODE_L2_FRM_ERR: Layer 2 error frame integrity error, such as FCS or ECC). @VXGE_HW_RING_T_CODE_BUF_SIZE_ERR: Buffer size error the RxD buffer( s) were not appropriately sized and data loss occurred. @VXGE_HW_RING_T_CODE_INT_ECC_ERR: Internal ECC error RxD corrupted. @VXGE_HW_RING_T_CODE_BENIGN_OVFLOW: Benign overflow the contents of Segment1 exceeded the capacity of Buffer1 and the remainder was placed in Buffer2. Segment2 now starts in Buffer3. No data loss or errors occurred. @VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0 one of the RxDs assigned buffers has a size of 0 bytes. @VXGE_HW_RING_T_CODE_FRM_DROP: Frame dropped either due to VPath Reset or because of a VPIN mismatch. @VXGE_HW_RING_T_CODE_UNUSED: Unused @VXGE_HW_RING_T_CODE_MULTI_ERR: Multiple errors more than one transfer code condition occurred.

Transfer codes returned by adapter.

Enumerator
VXGE_HW_RING_T_CODE_OK
VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH
VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH
VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH
VXGE_HW_RING_T_CODE_L3_PKT_ERR
VXGE_HW_RING_T_CODE_L2_FRM_ERR
VXGE_HW_RING_T_CODE_BUF_SIZE_ERR
VXGE_HW_RING_T_CODE_INT_ECC_ERR
VXGE_HW_RING_T_CODE_BENIGN_OVFLOW
VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF
VXGE_HW_RING_T_CODE_FRM_DROP
VXGE_HW_RING_T_CODE_UNUSED
VXGE_HW_RING_T_CODE_MULTI_ERR

Definition at line 172 of file vxge_traffic.h.

                        {
        VXGE_HW_RING_T_CODE_OK                            = 0x0,
        VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH              = 0x1,
        VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH              = 0x2,
        VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH        = 0x3,
        VXGE_HW_RING_T_CODE_L3_PKT_ERR                    = 0x5,
        VXGE_HW_RING_T_CODE_L2_FRM_ERR                    = 0x6,
        VXGE_HW_RING_T_CODE_BUF_SIZE_ERR                = 0x7,
        VXGE_HW_RING_T_CODE_INT_ECC_ERR                  = 0x8,
        VXGE_HW_RING_T_CODE_BENIGN_OVFLOW              = 0x9,
        VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF              = 0xA,
        VXGE_HW_RING_T_CODE_FRM_DROP                        = 0xC,
        VXGE_HW_RING_T_CODE_UNUSED                    = 0xE,
        VXGE_HW_RING_T_CODE_MULTI_ERR                      = 0xF
};

vxge_hw_fifo_gather_code

enum vxge_hw_fifo_gather_code

enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.

These gather codes are used to indicate the position of a TxD in a TxD list

Enumerator
VXGE_HW_FIFO_GATHER_CODE_FIRST
VXGE_HW_FIFO_GATHER_CODE_MIDDLE
VXGE_HW_FIFO_GATHER_CODE_LAST
VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST

Definition at line 198 of file vxge_traffic.h.

                              {
        VXGE_HW_FIFO_GATHER_CODE_FIRST            = 0x2,
        VXGE_HW_FIFO_GATHER_CODE_MIDDLE          = 0x0,
        VXGE_HW_FIFO_GATHER_CODE_LAST              = 0x1,
        VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST  = 0x3
};

vxge_hw_fifo_tcode

enum vxge_hw_fifo_tcode

enum enum vxge_hw_fifo_tcode - tcodes used in fifo @VXGE_HW_FIFO_T_CODE_OK: Transfer OK @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or frame data) returned with corrupt data.

@VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned with no data. @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a frame or LSO MSS that was too long (>9800B). @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send Offload operation, due to improper header template, unsupported protocol, etc. @VXGE_HW_FIFO_T_CODE_UNUSED: Unused @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple data buffer transfer errors are encountered (see below). Otherwise it is set to 0.

These tcodes are returned in various API for TxD status

Enumerator
VXGE_HW_FIFO_T_CODE_OK
VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT
VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL
VXGE_HW_FIFO_T_CODE_INVALID_MSS
VXGE_HW_FIFO_T_CODE_LSO_ERROR
VXGE_HW_FIFO_T_CODE_UNUSED
VXGE_HW_FIFO_T_CODE_MULTI_ERROR

Definition at line 224 of file vxge_traffic.h.

                        {
        VXGE_HW_FIFO_T_CODE_OK                    = 0x0,
        VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT        = 0x1,
        VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL      = 0x2,
        VXGE_HW_FIFO_T_CODE_INVALID_MSS          = 0x3,
        VXGE_HW_FIFO_T_CODE_LSO_ERROR              = 0x4,
        VXGE_HW_FIFO_T_CODE_UNUSED            = 0x7,
        VXGE_HW_FIFO_T_CODE_MULTI_ERROR          = 0x8
};

Function Documentation

FILE_LICENCE()

FILE_LICENCE

(

GPL2_ONLY

)

vxge_hw_ring_replenish()

enum vxge_hw_status vxge_hw_ring_replenish

(

struct __vxge_hw_ring *

ring

)

Definition at line 558 of file vxge_config.c.

{
        struct __vxge_hw_device *hldev;
        struct vxge_hw_ring_rxd_1 *rxd;
        enum vxge_hw_status status = VXGE_HW_OK;
        u8 offset = 0;
        struct __vxge_hw_ring_block *block;
        u8 i, iob_off;
 
        vxge_trace();
 
        hldev = ring->vpathh->hldev;
        /*
         * We allocate all the dma buffers first and then share the
         * these buffers among the all rx descriptors in the block.
         */
        for (i = 0; i < ARRAY_SIZE(ring->iobuf); i++) {
                ring->iobuf[i] = alloc_iob(VXGE_LL_MAX_FRAME_SIZE(hldev->vdev));
                if (!ring->iobuf[i]) {
                        while (i) {
                                free_iob(ring->iobuf[--i]);
                                ring->iobuf[i] = NULL;
                        }
                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
                        goto iobuf_err;
                }
        }
 
        for (offset = 0; offset < VXGE_HW_MAX_RXDS_PER_BLOCK_1; offset++) {
 
                rxd = &ring->rxdl->rxd[offset];
                if (offset == (VXGE_HW_MAX_RXDS_PER_BLOCK_1 - 1))
                        iob_off = VXGE_HW_RING_BUF_PER_BLOCK;
                else
                        iob_off = offset % ring->buf_per_block;
 
                rxd->control_0 = rxd->control_1 = 0;
                vxge_hw_ring_rxd_1b_set(rxd, ring->iobuf[iob_off],
                                VXGE_LL_MAX_FRAME_SIZE(hldev->vdev));
 
                vxge_hw_ring_rxd_post(ring, rxd);
        }
        /* linking the block to itself as we use only one rx block*/
        block = ring->rxdl;
        block->reserved_2_pNext_RxD_block = (unsigned long) block;
        block->pNext_RxD_Blk_physical = (u64)virt_to_bus(block);
 
        ring->rxd_offset = 0;
iobuf_err:
        return status;
}

References alloc_iob(), ARRAY_SIZE, block, __vxge_hw_ring::buf_per_block, free_iob(), __vxge_hw_virtualpath::hldev, __vxge_hw_ring::iobuf, NULL, offset, __vxge_hw_ring_block::rxd, rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, status, u8, __vxge_hw_device::vdev, virt_to_bus(), __vxge_hw_ring::vpathh, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_OK, VXGE_HW_RING_BUF_PER_BLOCK, vxge_hw_ring_rxd_1b_set(), vxge_hw_ring_rxd_post(), VXGE_LL_MAX_FRAME_SIZE, and vxge_trace.

Referenced by __vxge_hw_ring_create().

vxge_hw_ring_rxd_post()

void vxge_hw_ring_rxd_post	(	struct __vxge_hw_ring *	ring_handle,
		struct vxge_hw_ring_rxd_1 *	rxdp )

References rxdp, txdp, and u32.

vxge_hw_fifo_txdl_buffer_set()

void vxge_hw_fifo_txdl_buffer_set	(	struct __vxge_hw_fifo *	fifo,
		struct vxge_hw_fifo_txd *	txdp,
		struct io_buffer *	iob )

vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.

@fifo: Handle to the fifo object used for non offload send @txdlh: Descriptor handle. @iob: data buffer.

Definition at line 375 of file vxge_traffic.c.

{
        txdp->control_0 = VXGE_HW_FIFO_TXD_GATHER_CODE(
                        VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST);
        txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(iob_len(iob));
 
        txdp->control_1 = VXGE_HW_FIFO_TXD_INT_NUMBER(fifo->tx_intr_num);
        txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
 
        txdp->host_control = (intptr_t)iob;
        txdp->buffer_pointer = virt_to_bus(iob->data);
}

References io_buffer::data, iob_len(), __vxge_hw_fifo::tx_intr_num, txdp, virt_to_bus(), VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST, VXGE_HW_FIFO_TXD_BUFFER_SIZE, VXGE_HW_FIFO_TXD_GATHER_CODE, VXGE_HW_FIFO_TXD_INT_NUMBER, and VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST.

Referenced by vxge_xmit().

vxge_hw_fifo_txdl_post()

void vxge_hw_fifo_txdl_post	(	struct __vxge_hw_fifo *	fifo,
		struct vxge_hw_fifo_txd *	txdp )

vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.

@fifo: Handle to the fifo object used for non offload send @txdp: Tx Descriptor

Post descriptor on the 'fifo' type channel for transmission. Prior to posting the descriptor should be filled in accordance with Host/Titan interface specification for a given service (LL, etc.).

Definition at line 400 of file vxge_traffic.c.

{
        txdp->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
 
        __vxge_hw_non_offload_db_post(fifo, (u64) virt_to_bus(txdp), 0);
 
        vxge_hw_fifo_txd_offset_up(&fifo->sw_offset);
}

References __vxge_hw_non_offload_db_post(), __vxge_hw_fifo::sw_offset, txdp, virt_to_bus(), VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, and vxge_hw_fifo_txd_offset_up().

Referenced by vxge_xmit().

__vxge_hw_ring_create()

enum vxge_hw_status __vxge_hw_ring_create	(	struct __vxge_hw_virtualpath *	vpath,
		struct __vxge_hw_ring *	ring )

Definition at line 616 of file vxge_config.c.

{
        enum vxge_hw_status status = VXGE_HW_OK;
        struct __vxge_hw_device *hldev;
        u32 vp_id;
 
        vxge_trace();
 
        hldev = vpath->hldev;
        vp_id = vpath->vp_id;
 
        ring->rxdl = malloc_phys(sizeof(struct __vxge_hw_ring_block),
                        sizeof(struct __vxge_hw_ring_block));
        if (!ring->rxdl) {
                vxge_debug(VXGE_ERR, "%s:%d malloc_phys error\n",
                                __func__, __LINE__);
                status = VXGE_HW_ERR_OUT_OF_MEMORY;
                goto exit;
        }
        ring->rxd_offset = 0;
        ring->vpathh = vpath;
        ring->buf_per_block = VXGE_HW_RING_BUF_PER_BLOCK;
        ring->rx_poll_weight = VXGE_HW_RING_RX_POLL_WEIGHT;
        ring->vp_id = vp_id;
        ring->vp_reg = vpath->vp_reg;
        ring->common_reg = hldev->common_reg;
 
        ring->rxd_qword_limit = VXGE_HW_RING_RXD_QWORD_LIMIT;
 
        status = vxge_hw_ring_replenish(ring);
        if (status != VXGE_HW_OK) {
                __vxge_hw_ring_delete(ring);
                goto exit;
        }
exit:
        return status;
}

References __vxge_hw_ring_delete(), __vxge_hw_ring::buf_per_block, __vxge_hw_device::common_reg, __vxge_hw_ring::common_reg, __vxge_hw_virtualpath::hldev, malloc_phys(), __vxge_hw_ring::rx_poll_weight, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::rxdl, status, u32, __vxge_hw_ring::vp_id, __vxge_hw_virtualpath::vp_id, __vxge_hw_ring::vp_reg, __vxge_hw_virtualpath::vp_reg, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_OK, VXGE_HW_RING_BUF_PER_BLOCK, vxge_hw_ring_replenish(), VXGE_HW_RING_RX_POLL_WEIGHT, VXGE_HW_RING_RXD_QWORD_LIMIT, and vxge_trace.

Referenced by vxge_hw_vpath_open().

__vxge_hw_ring_delete()

enum vxge_hw_status __vxge_hw_ring_delete

(

struct __vxge_hw_ring *

ringh

)

Definition at line 659 of file vxge_config.c.

{
        u8 i;
 
        vxge_trace();
 
        for (i = 0; (i < ARRAY_SIZE(ring->iobuf)) && ring->iobuf[i]; i++) {
                free_iob(ring->iobuf[i]);
                ring->iobuf[i] = NULL;
        }
 
        if (ring->rxdl) {
                free_phys(ring->rxdl, sizeof(struct __vxge_hw_ring_block));
                ring->rxdl = NULL;
        }
        ring->rxd_offset = 0;
 
        return VXGE_HW_OK;
}

References ARRAY_SIZE, free_iob(), free_phys(), __vxge_hw_ring::iobuf, NULL, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u8, VXGE_HW_OK, and vxge_trace.

Referenced by __vxge_hw_ring_create(), and vxge_hw_vpath_close().

__vxge_hw_fifo_create()

enum vxge_hw_status __vxge_hw_fifo_create	(	struct __vxge_hw_virtualpath *	vpath,
		struct __vxge_hw_fifo *	fifo )

Definition at line 814 of file vxge_config.c.

{
        enum vxge_hw_status status = VXGE_HW_OK;
 
        vxge_trace();
 
        fifo->vpathh = vpath;
        fifo->depth = VXGE_HW_FIFO_TXD_DEPTH;
        fifo->hw_offset = fifo->sw_offset = 0;
        fifo->nofl_db = vpath->nofl_db;
        fifo->vp_id = vpath->vp_id;
        fifo->vp_reg = vpath->vp_reg;
        fifo->tx_intr_num = (vpath->vp_id * VXGE_HW_MAX_INTR_PER_VP)
                                + VXGE_HW_VPATH_INTR_TX;
 
        fifo->txdl = malloc_phys(sizeof(struct vxge_hw_fifo_txd)
                                * fifo->depth, fifo->depth);
        if (!fifo->txdl) {
                vxge_debug(VXGE_ERR, "%s:%d malloc_phys error\n",
                                __func__, __LINE__);
                return VXGE_HW_ERR_OUT_OF_MEMORY;
        }
        memset(fifo->txdl, 0, sizeof(struct vxge_hw_fifo_txd) * fifo->depth);
        return status;
}

References __vxge_hw_fifo::depth, __vxge_hw_fifo::hw_offset, malloc_phys(), memset(), __vxge_hw_fifo::nofl_db, __vxge_hw_virtualpath::nofl_db, status, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::tx_intr_num, __vxge_hw_fifo::txdl, __vxge_hw_fifo::vp_id, __vxge_hw_virtualpath::vp_id, __vxge_hw_fifo::vp_reg, __vxge_hw_virtualpath::vp_reg, __vxge_hw_fifo::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FIFO_TXD_DEPTH, VXGE_HW_MAX_INTR_PER_VP, VXGE_HW_OK, VXGE_HW_VPATH_INTR_TX, and vxge_trace.

Referenced by vxge_hw_vpath_open().

__vxge_hw_fifo_delete()

enum vxge_hw_status __vxge_hw_fifo_delete

(

struct __vxge_hw_fifo *

fifo

)

Definition at line 845 of file vxge_config.c.

{
        vxge_trace();
 
        if (fifo->txdl)
                free_phys(fifo->txdl,
                        sizeof(struct vxge_hw_fifo_txd) * fifo->depth);
 
        fifo->txdl = NULL;
        fifo->hw_offset = fifo->sw_offset = 0;
 
        return VXGE_HW_OK;
}

References __vxge_hw_fifo::depth, free_phys(), __vxge_hw_fifo::hw_offset, NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, VXGE_HW_OK, and vxge_trace.

Referenced by vxge_hw_vpath_close(), and vxge_hw_vpath_open().

__vxge_hw_vpath_reset()

enum vxge_hw_status __vxge_hw_vpath_reset	(	struct __vxge_hw_device *	devh,
		u32	vp_id )

Definition at line 1270 of file vxge_config.c.

{
        u64 val64;
        enum vxge_hw_status status = VXGE_HW_OK;
 
        vxge_trace();
 
        val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
 
        __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
                                &hldev->common_reg->cmn_rsthdlr_cfg0);
 
        return status;
}

References __vxge_hw_pio_mem_write32_upper(), vxge_hw_common_reg::cmn_rsthdlr_cfg0, __vxge_hw_device::common_reg, status, u32, vxge_bVALn, VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH, VXGE_HW_OK, and vxge_trace.

Referenced by __vxge_hw_vp_initialize(), and vxge_hw_vpath_reset().

__vxge_hw_vpath_enable()

enum vxge_hw_status __vxge_hw_vpath_enable	(	struct __vxge_hw_device *	devh,
		u32	vp_id )

References u32.

__vxge_hw_vpath_prc_configure()

void __vxge_hw_vpath_prc_configure

(

struct __vxge_hw_device *

hldev

)

Definition at line 1291 of file vxge_config.c.

{
        u64 val64;
        struct __vxge_hw_virtualpath *vpath;
        struct vxge_hw_vpath_reg __iomem *vp_reg;
 
        vxge_trace();
 
        vpath = &hldev->virtual_path;
        vp_reg = vpath->vp_reg;
 
        val64 = readq(&vp_reg->prc_cfg1);
        val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
        writeq(val64, &vp_reg->prc_cfg1);
 
        val64 = readq(&vpath->vp_reg->prc_cfg6);
        val64 &= ~VXGE_HW_PRC_CFG6_RXD_CRXDT(0x1ff);
        val64 &= ~VXGE_HW_PRC_CFG6_RXD_SPAT(0x1ff);
        val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
        val64 |= VXGE_HW_PRC_CFG6_RXD_CRXDT(0x3);
        val64 |= VXGE_HW_PRC_CFG6_RXD_SPAT(0xf);
        writeq(val64, &vpath->vp_reg->prc_cfg6);
 
        writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
                        (u64)virt_to_bus(vpath->ringh.rxdl) >> 3),
                        &vp_reg->prc_cfg5);
 
        val64 = readq(&vp_reg->prc_cfg4);
        val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
        val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
        val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
                        VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
        val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
 
        writeq(val64, &vp_reg->prc_cfg4);
        return;
}

References __iomem, vxge_hw_vpath_reg::prc_cfg1, vxge_hw_vpath_reg::prc_cfg4, vxge_hw_vpath_reg::prc_cfg5, vxge_hw_vpath_reg::prc_cfg6, readq, __vxge_hw_virtualpath::ringh, __vxge_hw_ring::rxdl, virt_to_bus(), __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE, VXGE_HW_PRC_CFG4_IN_SVC, VXGE_HW_PRC_CFG4_RING_MODE, VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER, VXGE_HW_PRC_CFG4_RTH_DISABLE, VXGE_HW_PRC_CFG5_RXD0_ADD, VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN, VXGE_HW_PRC_CFG6_RXD_CRXDT, VXGE_HW_PRC_CFG6_RXD_SPAT, vxge_trace, and writeq.

Referenced by vxge_hw_vpath_open(), and vxge_hw_vpath_recover_from_reset().

__vxge_hw_vpath_kdfc_configure()

enum vxge_hw_status __vxge_hw_vpath_kdfc_configure	(	struct __vxge_hw_device *	devh,
		u32	vp_id )

Definition at line 1335 of file vxge_config.c.

{
        u64 val64;
        u64 vpath_stride;
        enum vxge_hw_status status = VXGE_HW_OK;
        struct __vxge_hw_virtualpath *vpath;
        struct vxge_hw_vpath_reg __iomem *vp_reg;
 
        vxge_trace();
 
        vpath = &hldev->virtual_path;
        vp_reg = vpath->vp_reg;
        status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
 
        if (status != VXGE_HW_OK)
                goto exit;
 
        val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
 
        vpath->max_kdfc_db =
                (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
                        val64+1)/2;
 
        vpath->max_nofl_db = vpath->max_kdfc_db;
 
        val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
                                (vpath->max_nofl_db*2)-1);
 
        writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
 
        writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
                &vp_reg->kdfc_fifo_trpl_ctrl);
 
        val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
 
        val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
                   VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
 
        val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
                 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
#if (__BYTE_ORDER != __BIG_ENDIAN)
                 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
#endif
                 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
 
        writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
        writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
        wmb();
        vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
 
        vpath->nofl_db =
                (struct __vxge_hw_non_offload_db_wrapper __iomem *)
                (hldev->kdfc + (vp_id *
                VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
                                        vpath_stride)));
exit:
        return status;
}

References __iomem, __vxge_hw_kdfc_swapper_set(), __vxge_hw_device::kdfc, vxge_hw_vpath_reg::kdfc_drbl_triplet_total, vxge_hw_vpath_reg::kdfc_fifo_trpl_ctrl, vxge_hw_vpath_reg::kdfc_fifo_trpl_partition, vxge_hw_vpath_reg::kdfc_trpl_fifo_0_ctrl, vxge_hw_vpath_reg::kdfc_trpl_fifo_0_wb_address, __vxge_hw_device::legacy_reg, __vxge_hw_virtualpath::max_kdfc_db, __vxge_hw_virtualpath::max_nofl_db, __vxge_hw_virtualpath::nofl_db, readq, status, vxge_hw_toc_reg::toc_kdfc_vpath_stride, __vxge_hw_device::toc_reg, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE, VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN, VXGE_HW_OK, VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE, vxge_trace, wmb, and writeq.

Referenced by __vxge_hw_vpath_initialize().

__vxge_hw_vpath_mac_configure()

enum vxge_hw_status __vxge_hw_vpath_mac_configure

(

struct __vxge_hw_device *

devh

)

Definition at line 1399 of file vxge_config.c.

{
        u64 val64;
        enum vxge_hw_status status = VXGE_HW_OK;
        struct __vxge_hw_virtualpath *vpath;
        struct vxge_hw_vpath_reg __iomem *vp_reg;
 
        vxge_trace();
 
        vpath = &hldev->virtual_path;
        vp_reg = vpath->vp_reg;
 
        writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
                        vpath->vsport_number), &vp_reg->xmac_vsport_choice);
 
        val64 = readq(&vp_reg->rxmac_vcfg1);
 
        val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
                VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
 
        writeq(val64, &vp_reg->rxmac_vcfg1);
        return status;
}

References __iomem, readq, vxge_hw_vpath_reg::rxmac_vcfg1, status, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, __vxge_hw_virtualpath::vsport_number, VXGE_HW_OK, VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE, VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE, VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER, vxge_trace, writeq, and vxge_hw_vpath_reg::xmac_vsport_choice.

Referenced by __vxge_hw_vpath_initialize().

__vxge_hw_vpath_tim_configure()

enum vxge_hw_status __vxge_hw_vpath_tim_configure	(	struct __vxge_hw_device *	devh,
		u32	vp_id )

Definition at line 1429 of file vxge_config.c.

{
        u64 val64;
        enum vxge_hw_status status = VXGE_HW_OK;
        struct __vxge_hw_virtualpath *vpath;
        struct vxge_hw_vpath_reg __iomem *vp_reg;
 
        vxge_trace();
 
        vpath = &hldev->virtual_path;
        vp_reg = vpath->vp_reg;
 
        writeq((u64)0, &vp_reg->tim_dest_addr);
        writeq((u64)0, &vp_reg->tim_vpath_map);
        writeq((u64)0, &vp_reg->tim_bitmap);
        writeq((u64)0, &vp_reg->tim_remap);
 
        writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
                (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
                VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
 
        val64 = readq(&vp_reg->tim_pci_cfg);
        val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
        writeq(val64, &vp_reg->tim_pci_cfg);
 
        /* TX configuration */
        val64 = VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
                        (VXGE_TTI_BTIMER_VAL * 1000) / 272);
        val64 |= (VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC |
                        VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI |
                        VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN);
        val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(TTI_TX_URANGE_A) |
                        VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(TTI_TX_URANGE_B) |
                        VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(TTI_TX_URANGE_C);
        writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
 
        val64 = VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(TTI_TX_UFC_A) |
                        VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(TTI_TX_UFC_B) |
                        VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(TTI_TX_UFC_C) |
                        VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(TTI_TX_UFC_D);
        writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
 
        val64 = VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
                        VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL);
        val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
                        (VXGE_TTI_LTIMER_VAL * 1000) / 272);
        writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
 
        /* RX configuration */
        val64 = VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
                        (VXGE_RTI_BTIMER_VAL * 1000) / 272);
        val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
        val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(RTI_RX_URANGE_A) |
                        VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(RTI_RX_URANGE_B) |
                        VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(RTI_RX_URANGE_C);
        writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
 
        val64 = VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(RTI_RX_UFC_A) |
                        VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(RTI_RX_UFC_B) |
                        VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(RTI_RX_UFC_C) |
                        VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(RTI_RX_UFC_D);
        writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
 
        val64 = VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
                        VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL);
        val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
                        (VXGE_RTI_LTIMER_VAL * 1000) / 272);
        writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
 
        val64 = 0;
        writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
        writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
        writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
        writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
        writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
        writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
 
        return status;
}

References __iomem, readq, RTI_RX_UFC_A, RTI_RX_UFC_B, RTI_RX_UFC_C, RTI_RX_UFC_D, RTI_RX_URANGE_A, RTI_RX_URANGE_B, RTI_RX_URANGE_C, status, vxge_hw_vpath_reg::tim_bitmap, vxge_hw_vpath_reg::tim_cfg1_int_num, vxge_hw_vpath_reg::tim_cfg2_int_num, vxge_hw_vpath_reg::tim_cfg3_int_num, vxge_hw_vpath_reg::tim_dest_addr, vxge_hw_vpath_reg::tim_pci_cfg, vxge_hw_vpath_reg::tim_remap, vxge_hw_vpath_reg::tim_ring_assn, vxge_hw_vpath_reg::tim_vpath_map, TTI_TX_UFC_A, TTI_TX_UFC_B, TTI_TX_UFC_C, TTI_TX_UFC_D, TTI_TX_URANGE_A, TTI_TX_URANGE_B, TTI_TX_URANGE_C, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_MAX_INTR_PER_VP, VXGE_HW_OK, VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL, VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC, VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI, VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN, VXGE_HW_TIM_CFG1_INT_NUM_URNG_A, VXGE_HW_TIM_CFG1_INT_NUM_URNG_B, VXGE_HW_TIM_CFG1_INT_NUM_URNG_C, VXGE_HW_TIM_CFG2_INT_NUM_UEC_A, VXGE_HW_TIM_CFG2_INT_NUM_UEC_B, VXGE_HW_TIM_CFG2_INT_NUM_UEC_C, VXGE_HW_TIM_CFG2_INT_NUM_UEC_D, VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL, VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL, VXGE_HW_TIM_PCI_CFG_ADD_PAD, VXGE_HW_TIM_RING_ASSN_INT_NUM, VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL, VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL, VXGE_HW_VPATH_INTR_BMAP, VXGE_HW_VPATH_INTR_EINTA, VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, VXGE_RTI_BTIMER_VAL, VXGE_RTI_LTIMER_VAL, vxge_trace, VXGE_TTI_BTIMER_VAL, VXGE_TTI_LTIMER_VAL, and writeq.

Referenced by __vxge_hw_vpath_initialize().

__vxge_hw_vpath_initialize()

enum vxge_hw_status __vxge_hw_vpath_initialize	(	struct __vxge_hw_device *	devh,
		u32	vp_id )

Definition at line 1515 of file vxge_config.c.

{
        u64 val64;
        u32 val32;
        int i;
        enum vxge_hw_status status = VXGE_HW_OK;
        struct __vxge_hw_virtualpath *vpath;
        struct vxge_hw_vpath_reg *vp_reg;
 
        vxge_trace();
 
        vpath = &hldev->virtual_path;
 
        if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
                status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
                goto exit;
        }
        vp_reg = vpath->vp_reg;
        status = __vxge_hw_legacy_swapper_set(hldev->legacy_reg);
        if (status != VXGE_HW_OK)
                goto exit;
 
        status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
 
        if (status != VXGE_HW_OK)
                goto exit;
        val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
 
        for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
                if (val64 & vxge_mBIT(i))
                        vpath->vsport_number = i;
        }
 
        status = __vxge_hw_vpath_mac_configure(hldev);
 
        if (status != VXGE_HW_OK)
                goto exit;
 
        status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
 
        if (status != VXGE_HW_OK)
                goto exit;
 
        status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
 
        if (status != VXGE_HW_OK)
                goto exit;
 
        val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
 
        /* Get MRRS value from device control */
        status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
 
        if (status == VXGE_HW_OK) {
                val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
                val64 &=
                    ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
                val64 |=
                    VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
 
                val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
        }
 
        val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
        val64 |=
            VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
                    VXGE_HW_MAX_PAYLOAD_SIZE_512);
 
        val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
        writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
 
exit:
        return status;
}

References __vxge_hw_legacy_swapper_set(), __vxge_hw_vpath_kdfc_configure(), __vxge_hw_vpath_mac_configure(), __vxge_hw_vpath_pci_read(), __vxge_hw_vpath_swapper_set(), __vxge_hw_vpath_tim_configure(), __vxge_hw_device::legacy_reg, readq, vxge_hw_vpath_reg::rtdma_rd_optimization_ctrl, status, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, __vxge_hw_device::vpath_assignments, __vxge_hw_virtualpath::vpmgmt_reg, __vxge_hw_virtualpath::vsport_number, VXGE_HW_ERR_VPATH_NOT_AVAILABLE, VXGE_HW_MAX_PAYLOAD_SIZE_512, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_PCI_EXP_DEVCTL_READRQ, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE, vxge_mBIT, vxge_trace, writeq, and vxge_hw_vpmgmt_reg::xmac_vsport_choices_vp.

Referenced by __vxge_hw_vp_initialize(), and vxge_hw_vpath_recover_from_reset().

__vxge_hw_vp_initialize()

enum vxge_hw_status __vxge_hw_vp_initialize	(	struct __vxge_hw_device *	hldev,
		u32	vp_id,
		struct __vxge_hw_virtualpath *	vpath )

Definition at line 1596 of file vxge_config.c.

{
        enum vxge_hw_status status = VXGE_HW_OK;
 
        vxge_trace();
 
        if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
                status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
                goto exit;
        }
 
        vpath->vp_id = vp_id;
        vpath->vp_open = VXGE_HW_VP_OPEN;
        vpath->hldev = hldev;
        vpath->vp_reg = hldev->vpath_reg[vp_id];
        vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
 
        __vxge_hw_vpath_reset(hldev, vp_id);
 
        status = __vxge_hw_vpath_reset_check(vpath);
        if (status != VXGE_HW_OK) {
                memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
                goto exit;
        }
 
        VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
                hldev->tim_int_mask1, vp_id);
 
        status = __vxge_hw_vpath_initialize(hldev, vp_id);
 
        if (status != VXGE_HW_OK) {
                __vxge_hw_vp_terminate(hldev, vpath);
                goto exit;
        }
 
        status = __vxge_hw_vpath_mgmt_read(vpath);
exit:
        return status;
}

References __vxge_hw_vp_terminate(), __vxge_hw_vpath_initialize(), __vxge_hw_vpath_mgmt_read(), __vxge_hw_vpath_reset(), __vxge_hw_vpath_reset_check(), __vxge_hw_virtualpath::hldev, memset(), status, __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, u32, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, __vxge_hw_device::vpath_assignments, __vxge_hw_device::vpath_reg, __vxge_hw_device::vpmgmt_reg, __vxge_hw_virtualpath::vpmgmt_reg, VXGE_HW_DEVICE_TIM_INT_MASK_SET, VXGE_HW_ERR_VPATH_NOT_AVAILABLE, VXGE_HW_OK, VXGE_HW_VP_OPEN, vxge_mBIT, and vxge_trace.

Referenced by vxge_hw_vpath_open().

__vxge_hw_vp_terminate()

void __vxge_hw_vp_terminate	(	struct __vxge_hw_device *	hldev,
		struct __vxge_hw_virtualpath *	vpath )

Definition at line 1642 of file vxge_config.c.

{
        vxge_trace();
 
        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
                return;
 
        VXGE_HW_DEVICE_TIM_INT_MASK_RESET(hldev->tim_int_mask0,
                hldev->tim_int_mask1, vpath->vp_id);
 
        memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
}

References memset(), __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, VXGE_HW_DEVICE_TIM_INT_MASK_RESET, VXGE_HW_VP_NOT_OPEN, and vxge_trace.

Referenced by __vxge_hw_vp_initialize(), vxge_hw_vpath_close(), and vxge_hw_vpath_open().

vxge_hw_device_begin_irq()

enum vxge_hw_status vxge_hw_device_begin_irq

(

struct __vxge_hw_device *

hldev

)

vxge_hw_device_begin_irq - Begin IRQ processing.

@hldev: HW device handle.

The function performs two actions, It first checks whether (shared IRQ) the interrupt was raised by the device. Next, it masks the device interrupts.

Note: vxge_hw_device_begin_irq() does not flush MMIO writes through the bridge. Therefore, two back-to-back interrupts are potentially possible.

Returns: 0, if the interrupt is not "ours" (note that in this case the device remain enabled). Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter status.

Definition at line 555 of file vxge_traffic.c.

{
        u64 val64;
        u64 adapter_status;
        u64 vpath_mask;
        enum vxge_hw_status ret = VXGE_HW_OK;
 
        val64 = readq(&hldev->common_reg->titan_general_int_status);
 
        if (!val64) {
                ret = VXGE_HW_ERR_WRONG_IRQ;
                goto exit;
        }
 
        if (val64 == VXGE_HW_ALL_FOXES) {
 
                adapter_status = readq(&hldev->common_reg->adapter_status);
 
                if (adapter_status == VXGE_HW_ALL_FOXES) {
 
                        vxge_debug(VXGE_ERR, "%s: %s:%d critical error "
                                "occurred\n", hldev->ndev->name,
                                __func__, __LINE__);
                        ret = VXGE_HW_ERR_SLOT_FREEZE;
                        goto exit;
                }
        }
 
        vpath_mask = hldev->vpaths_deployed >>
                                (64 - VXGE_HW_MAX_VIRTUAL_PATHS);
        if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(
                                vpath_mask))
                vxge_hw_device_clear_tx_rx(hldev);
 
        if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)
                ret = __vxge_hw_vpath_alarm_process(&hldev->virtual_path);
 
exit:
        return ret;
}

References __vxge_hw_vpath_alarm_process(), adapter_status, vxge_hw_common_reg::adapter_status, __vxge_hw_device::common_reg, net_device::name, __vxge_hw_device::ndev, readq, vxge_hw_common_reg::titan_general_int_status, __vxge_hw_device::virtual_path, __vxge_hw_device::vpaths_deployed, vxge_debug, VXGE_ERR, VXGE_HW_ALL_FOXES, vxge_hw_device_clear_tx_rx(), VXGE_HW_ERR_SLOT_FREEZE, VXGE_HW_ERR_WRONG_IRQ, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT, and VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT.

Referenced by vxge_poll().

vxge_hw_device_intr_enable()

void vxge_hw_device_intr_enable

(

struct __vxge_hw_device *

hldev

)

vxge_hw_device_intr_enable - Enable interrupts.

@hldev: HW device handle.

Enable Titan interrupts. The function is to be executed the last in Titan initialization sequence.

See also: vxge_hw_device_intr_disable()

Definition at line 251 of file vxge_traffic.c.

{
        u64 val64;
        u32 val32;
 
        vxge_hw_device_mask_all(hldev);
 
        vxge_hw_vpath_intr_enable(&hldev->virtual_path);
 
        val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
                        hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
 
        if (val64 != 0) {
                writeq(val64, &hldev->common_reg->tim_int_status0);
 
                writeq(~val64, &hldev->common_reg->tim_int_mask0);
        }
 
        val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
                        hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
 
        if (val32 != 0) {
                __vxge_hw_pio_mem_write32_upper(val32,
                                &hldev->common_reg->tim_int_status1);
 
                __vxge_hw_pio_mem_write32_upper(~val32,
                                &hldev->common_reg->tim_int_mask1);
        }
 
        val64 = readq(&hldev->common_reg->titan_general_int_status);
 
        /* We have not enabled the top level interrupt yet.
         * This will be controlled from vxge_irq() entry api.
         */
        return;
}

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, readq, __vxge_hw_device::tim_int_mask0, vxge_hw_common_reg::tim_int_mask0, __vxge_hw_device::tim_int_mask1, vxge_hw_common_reg::tim_int_mask1, vxge_hw_common_reg::tim_int_status0, vxge_hw_common_reg::tim_int_status1, vxge_hw_common_reg::titan_general_int_status, u32, __vxge_hw_device::virtual_path, vxge_hw_device_mask_all(), vxge_hw_vpath_intr_enable(), VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, and writeq.

Referenced by vxge_open().

vxge_hw_device_intr_disable()

void vxge_hw_device_intr_disable

(

struct __vxge_hw_device *

hldev

)

vxge_hw_device_intr_disable - Disable Titan interrupts.

@hldev: HW device handle.

Disable Titan interrupts.

See also: vxge_hw_device_intr_enable()

Definition at line 296 of file vxge_traffic.c.

{
        vxge_hw_device_mask_all(hldev);
 
        /* mask all the tim interrupts */
        writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
        __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
                                &hldev->common_reg->tim_int_mask1);
 
        vxge_hw_vpath_intr_disable(&hldev->virtual_path);
 
        return;
}

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::tim_int_mask0, vxge_hw_common_reg::tim_int_mask1, __vxge_hw_device::virtual_path, VXGE_HW_DEFAULT_32, vxge_hw_device_mask_all(), VXGE_HW_INTR_MASK_ALL, vxge_hw_vpath_intr_disable(), and writeq.

Referenced by vxge_close().

vxge_hw_device_mask_all()

void vxge_hw_device_mask_all

(

struct __vxge_hw_device *

hldev

)

vxge_hw_device_mask_all - Mask all device interrupts.

@hldev: HW device handle.

Mask all device interrupts.

See also: vxge_hw_device_unmask_all()

Definition at line 211 of file vxge_traffic.c.

{
        u64 val64;
 
        val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
                        VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
 
        __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
                        &hldev->common_reg->titan_mask_all_int);
 
        return;
}

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, u32, vxge_bVALn, VXGE_HW_TITAN_MASK_ALL_INT_ALARM, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.

Referenced by vxge_hw_device_intr_disable(), vxge_hw_device_intr_enable(), and vxge_irq().

vxge_hw_device_unmask_all()

void vxge_hw_device_unmask_all

(

struct __vxge_hw_device *

hldev

)

vxge_hw_device_unmask_all - Unmask all device interrupts.

@hldev: HW device handle.

Unmask all device interrupts.

See also: vxge_hw_device_mask_all()

Definition at line 232 of file vxge_traffic.c.

{
        u64 val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
 
        __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
                        &hldev->common_reg->titan_mask_all_int);
 
        return;
}

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, u32, vxge_bVALn, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.

Referenced by vxge_close(), and vxge_irq().

vxge_hw_vpath_doorbell_rx()

void vxge_hw_vpath_doorbell_rx

(

struct __vxge_hw_ring *

ring

)

vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.

@ring: Handle to the ring object used for receive

The function writes the number of qwords of rxds posted during replishment. Since the function is called frequently, a flush is not required to post the write transaction. At the very least, the previous write will be flushed once the subsequent write is made.

Returns: None.

Definition at line 608 of file vxge_traffic.c.

{
        u32 rxds_qw_per_block = VXGE_HW_MAX_RXDS_PER_BLOCK_1 *
                VXGE_HW_RING_RXD_QWORDS_MODE_1;
 
        ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
 
        ring->total_db_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
 
        if (ring->total_db_cnt >= rxds_qw_per_block) {
                /* For each block add 4 more qwords */
                ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
 
                /* Reset total count */
                ring->total_db_cnt -= rxds_qw_per_block;
        }
 
        if (ring->doorbell_cnt >= ring->rxd_qword_limit) {
                wmb();
                writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(
                        ring->doorbell_cnt),
                        &ring->vp_reg->prc_rxd_doorbell);
                ring->doorbell_cnt = 0;
        }
}

References __vxge_hw_ring::doorbell_cnt, vxge_hw_vpath_reg::prc_rxd_doorbell, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::total_db_cnt, u32, __vxge_hw_ring::vp_reg, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT, VXGE_HW_RING_RXD_QWORDS_MODE_1, wmb, and writeq.

Referenced by vxge_hw_vpath_poll_rx().

vxge_hw_vpath_poll_rx()

enum vxge_hw_status vxge_hw_vpath_poll_rx

(

struct __vxge_hw_ring *

ringh

)

Definition at line 642 of file vxge_traffic.c.

{
        struct __vxge_hw_device *hldev;
        enum vxge_hw_status status = VXGE_HW_OK;
        struct vxge_hw_ring_rxd_1 *rxd;
        unsigned int len;
        enum vxge_hw_ring_tcode tcode;
        struct io_buffer *rx_iob, *iobuf = NULL;
        u16 poll_count = 0;
 
        hldev = ring->vpathh->hldev;
 
        do {
                rxd = &ring->rxdl->rxd[ring->rxd_offset];
                tcode = VXGE_HW_RING_RXD_T_CODE_GET(rxd->control_0);
 
                /* if tcode is VXGE_HW_RING_T_CODE_FRM_DROP, it is
                 * possible the ownership bit still set to adapter
                 */
                if ((rxd->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER)
                        && (tcode == VXGE_HW_RING_T_CODE_OK)) {
 
                        status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
                        goto err0;
                }
 
                vxge_debug(VXGE_INFO, "%s: rx frame received at offset %d\n",
                        hldev->ndev->name, ring->rxd_offset);
 
                iobuf = (struct io_buffer *)(intptr_t)rxd->host_control;
 
                if (tcode != VXGE_HW_RING_T_CODE_OK) {
                        netdev_rx_err(hldev->ndev, NULL, -EINVAL);
                        vxge_debug(VXGE_ERR, "%s:%d, rx error tcode %d\n",
                                __func__, __LINE__, tcode);
                        status = VXGE_HW_FAIL;
                        goto err1;
                }
 
                len = VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxd->control_1);
                len -= ETH_FCS_LEN;
 
                rx_iob = alloc_iob(len);
                if (!rx_iob) {
                        netdev_rx_err(hldev->ndev, NULL, -ENOMEM);
                        vxge_debug(VXGE_ERR, "%s:%d, alloc_iob error\n",
                                __func__, __LINE__);
                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
                        goto err1;
                }
 
                memcpy(iob_put(rx_iob, len), iobuf->data, len);
                /* Add this packet to the receive queue. */
                netdev_rx(hldev->ndev, rx_iob);
 
err1:
                /* repost the rxd */
                rxd->control_0 = rxd->control_1 = 0;
                vxge_hw_ring_rxd_1b_set(rxd, iobuf,
                                VXGE_LL_MAX_FRAME_SIZE(hldev->vdev));
                vxge_hw_ring_rxd_post(ring, rxd);
 
                /* repost the qword count for doorbell */
                vxge_hw_vpath_doorbell_rx(ring);
 
                /* increment the descriptor offset */
                vxge_hw_ring_rxd_offset_up(&ring->rxd_offset);
 
        } while (++poll_count < ring->rx_poll_weight);
err0:
        return status;
}

References alloc_iob(), io_buffer::data, EINVAL, ENOMEM, ETH_FCS_LEN, __vxge_hw_virtualpath::hldev, iob_put, len, memcpy(), net_device::name, __vxge_hw_device::ndev, netdev_rx(), netdev_rx_err(), NULL, __vxge_hw_ring_block::rxd, rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, status, u16, __vxge_hw_device::vdev, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FAIL, VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS, VXGE_HW_OK, VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET, vxge_hw_ring_rxd_1b_set(), VXGE_HW_RING_RXD_LIST_OWN_ADAPTER, vxge_hw_ring_rxd_offset_up(), vxge_hw_ring_rxd_post(), VXGE_HW_RING_RXD_T_CODE_GET, VXGE_HW_RING_T_CODE_OK, vxge_hw_vpath_doorbell_rx(), VXGE_INFO, and VXGE_LL_MAX_FRAME_SIZE.

Referenced by vxge_poll().

vxge_hw_vpath_poll_tx()

enum vxge_hw_status vxge_hw_vpath_poll_tx

(

struct __vxge_hw_fifo *

fifo

)

vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.

@fifo: Handle to the fifo object used for non offload send

The function polls the Tx for the completed descriptors and calls the driver via supplied completion callback.

Definition at line 723 of file vxge_traffic.c.

{
        enum vxge_hw_status status = VXGE_HW_OK;
        struct vxge_hw_fifo_txd *txdp;
 
        txdp = fifo->txdl + fifo->hw_offset;
        if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)
                && (txdp->host_control)) {
 
                vxge_xmit_compl(fifo, txdp,
                        VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0));
 
                vxge_hw_fifo_txd_offset_up(&fifo->hw_offset);
        }
 
        return status;
}

References __vxge_hw_fifo::hw_offset, status, __vxge_hw_fifo::txdl, txdp, VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, vxge_hw_fifo_txd_offset_up(), VXGE_HW_FIFO_TXD_T_CODE_GET, VXGE_HW_OK, and vxge_xmit_compl().

Referenced by vxge_poll().

vxge_hw_fifo_free_txdl_get()

struct vxge_hw_fifo_txd * vxge_hw_fifo_free_txdl_get

(

struct __vxge_hw_fifo *

fifo

)

vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo

@fifo: tx channel handle

Definition at line 355 of file vxge_traffic.c.

{
        struct vxge_hw_fifo_txd *txdp;
 
        txdp = fifo->txdl + fifo->sw_offset;
        if (txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER) {
                vxge_debug(VXGE_ERR, "%s:%d, error: txd(%d) owned by hw\n",
                                __func__, __LINE__, fifo->sw_offset);
                return NULL;
        }
 
        return txdp;
}

References NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, txdp, vxge_debug, VXGE_ERR, and VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER.

Referenced by vxge_xmit().