iPXE
vxge_config.h
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1 /*
2  * vxge-config.h: iPXE driver for Neterion Inc's X3100 Series 10GbE
3  * PCIe I/O Virtualized Server Adapter.
4  *
5  * Copyright(c) 2002-2010 Neterion Inc.
6  *
7  * This software may be used and distributed according to the terms of
8  * the GNU General Public License (GPL), incorporated herein by
9  * reference. Drivers based on or derived from this code fall under
10  * the GPL and must retain the authorship, copyright and license
11  * notice.
12  *
13  */
14 
15 FILE_LICENCE(GPL2_ONLY);
16 
17 #ifndef VXGE_CONFIG_H
18 #define VXGE_CONFIG_H
19 
20 #include <stdint.h>
21 #include <ipxe/list.h>
22 #include <ipxe/pci.h>
23 
24 #ifndef VXGE_CACHE_LINE_SIZE
25 #define VXGE_CACHE_LINE_SIZE 4096
26 #endif
27 
28 #define WAIT_FACTOR 1
29 
30 #define VXGE_HW_MAC_MAX_WIRE_PORTS 2
31 #define VXGE_HW_MAC_MAX_AGGR_PORTS 2
32 #define VXGE_HW_MAC_MAX_PORTS 3
33 
34 #define VXGE_HW_MIN_MTU 68
35 #define VXGE_HW_MAX_MTU 9600
36 #define VXGE_HW_DEFAULT_MTU 1500
37 
38 #ifndef __iomem
39 #define __iomem
40 #endif
41 
42 #ifndef ____cacheline_aligned
43 #define ____cacheline_aligned
44 #endif
45 
46 /**
47  * debug filtering masks
48  */
49 #define VXGE_NONE 0x00
50 #define VXGE_INFO 0x01
51 #define VXGE_INTR 0x02
52 #define VXGE_XMIT 0x04
53 #define VXGE_POLL 0x08
54 #define VXGE_ERR 0x10
55 #define VXGE_TRACE 0x20
56 #define VXGE_ALL (VXGE_INFO|VXGE_INTR|VXGE_XMIT\
57  |VXGE_POLL|VXGE_ERR|VXGE_TRACE)
58 
59 #define NULL_VPID 0xFFFFFFFF
60 
61 #define VXGE_HW_EVENT_BASE 0
62 #define VXGE_LL_EVENT_BASE 100
63 
64 #define VXGE_HW_BASE_INF 100
65 #define VXGE_HW_BASE_ERR 200
66 #define VXGE_HW_BASE_BADCFG 300
67 #define VXGE_HW_DEF_DEVICE_POLL_MILLIS 1000
68 #define VXGE_HW_MAX_PAYLOAD_SIZE_512 2
69 
75 
83 
117 
128 
130 };
131 
132 /**
133  * enum enum vxge_hw_device_link_state - Link state enumeration.
134  * @VXGE_HW_LINK_NONE: Invalid link state.
135  * @VXGE_HW_LINK_DOWN: Link is down.
136  * @VXGE_HW_LINK_UP: Link is up.
137  *
138  */
143 };
144 
145 /*forward declaration*/
146 struct vxge_vpath;
147 struct __vxge_hw_virtualpath;
148 
149 /**
150  * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
151  *
152  * One buffer mode RxD for ring structure
153  */
157 #define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7)
158 
159 #define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER vxge_mBIT(7)
160 
161 #define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1)
162 
163 #define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1)
164 
165 #define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1)
166 
167 #define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4)
168 #define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4)
169 
170 #define VXGE_HW_RING_RXD_T_CODE_UNUSED VXGE_HW_RING_T_CODE_UNUSED
171 
172 #define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1)
173 
174 #define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1)
175 
176 #define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1)
177 
178 #define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1)
179 
180 #define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4)
181 
182 #define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1)
183 
184 #define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2)
185 
186 #define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5)
187 
188 #define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16)
189 
190 #define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16)
191 
193 
194 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14)
195 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14)
196 #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK vxge_vBIT(0x3FFF, 2, 14)
197 
198 #define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32)
199 
200 #define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16)
201 
203 };
204 
205 /**
206  * struct vxge_hw_fifo_txd - Transmit Descriptor
207  *
208  * Transmit descriptor (TxD).Fifo descriptor contains configured number
209  * (list) of TxDs. * For more details please refer to Titan User Guide,
210  * Section 5.4.2 "Transmit Descriptor (TxD) Format".
211  */
214 #define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER vxge_mBIT(7)
215 
216 #define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4)
217 #define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4)
218 #define VXGE_HW_FIFO_TXD_T_CODE_UNUSED VXGE_HW_FIFO_T_CODE_UNUSED
219 
220 #define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2)
221 #define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST VXGE_HW_FIFO_GATHER_CODE_FIRST
222 #define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST VXGE_HW_FIFO_GATHER_CODE_LAST
223 
224 #define VXGE_HW_FIFO_TXD_LSO_EN vxge_mBIT(30)
225 #define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14)
226 #define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16)
227 
229 #define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN vxge_mBIT(5)
230 #define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN vxge_mBIT(6)
231 #define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN vxge_mBIT(7)
232 #define VXGE_HW_FIFO_TXD_VLAN_ENABLE vxge_mBIT(15)
233 
234 #define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16)
235 #define VXGE_HW_FIFO_TXD_NO_BW_LIMIT vxge_mBIT(43)
236 
237 #define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6)
238 
239 #define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST vxge_mBIT(46)
240 #define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ vxge_mBIT(47)
241 
243 
245 };
246 
247 /**
248  * struct vxge_hw_device_date - Date Format
249  * @day: Day
250  * @month: Month
251  * @year: Year
252  * @date: Date in string format
253  *
254  * Structure for returning date
255  */
256 
257 #define VXGE_HW_FW_STRLEN 32
263 };
264 
270 };
271 
273  u32 vp_id,
274  struct vxge_hw_vpath_reg __iomem *vpath_reg);
275 
276 /*
277  * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper
278  * @control_0: Bits 0 to 7 - Doorbell type.
279  * Bits 8 to 31 - Reserved.
280  * Bits 32 to 39 - The highest TxD in this TxDL.
281  * Bits 40 to 47 - Reserved.
282  * Bits 48 to 55 - Reserved.
283  * Bits 56 to 63 - No snoop flags.
284  * @txdl_ptr: The starting location of the TxDL in host memory.
285  *
286  * Created by the host and written to the adapter via PIO to a Kernel Doorbell
287  * FIFO. All non-offload doorbell wrapper fields must be written by the host as
288  * part of a doorbell write. Consumed by the adapter but is not written by the
289  * adapter.
290  */
293 #define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8)
294 #define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8)
295 #define VXGE_HW_NODBW_TYPE_NODBW 0
296 
297 #define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8)
298 #define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8)
299 
300 #define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8)
301 #define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8)
302 #define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2
303 #define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1
304 
306 };
307 
308 /*
309  * struct __vxge_hw_fifo - Fifo.
310  * @vp_id: Virtual path id
311  * @tx_intr_num: Interrupt Number associated with the TX
312  * @txdl: Start pointer of the txdl list of this fifo.
313  * iPXE does not support tx fragmentation, so we need
314  * only one txd in a list
315  * @depth: total number of lists in this fifo
316  * @hw_offset: txd index from where adapter owns the txd list
317  * @sw_offset: txd index from where driver owns the txd list
318  *
319  * @stats: Statistics of this fifo
320  *
321  */
327 
329 #define VXGE_HW_FIFO_TXD_DEPTH 128
333 
335 };
336 
337 /* Structure that represents the Rx descriptor block which contains
338  * 128 Rx descriptors.
339  */
341 #define VXGE_HW_MAX_RXDS_PER_BLOCK_1 127
343 
345 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
346  /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
348  /* Logical ptr to next */
350  /* Buff0_ptr.In a 32 bit arch the upper 32 bits should be 0 */
352 };
353 
354 /*
355  * struct __vxge_hw_ring - Ring channel.
356  *
357  * Note: The structure is cache line aligned to better utilize
358  * CPU cache performance.
359  */
364 #define VXGE_HW_RING_RXD_QWORDS_MODE_1 4
367 #define VXGE_HW_RING_RXD_QWORD_LIMIT 16
369 
371 #define VXGE_HW_RING_BUF_PER_BLOCK 9
374 
375 #define VXGE_HW_RING_RX_POLL_WEIGHT 8
377 
380 };
381 
382 /*
383  * struct __vxge_hw_virtualpath - Virtual Path
384  *
385  * Virtual path structure to encapsulate the data related to a virtual path.
386  * Virtual paths are allocated by the HW upon getting configuration from the
387  * driver and inserted into the list of virtual paths.
388  */
391 
393 #define VXGE_HW_VP_NOT_OPEN 0
394 #define VXGE_HW_VP_OPEN 1
395 
400 
405 
408 };
409 #define VXGE_HW_INFO_LEN 64
410 #define VXGE_HW_PMD_INFO_LEN 16
411 #define VXGE_MAX_PRINT_BUF_SIZE 128
412 /**
413  * struct vxge_hw_device_hw_info - Device information
414  * @host_type: Host Type
415  * @func_id: Function Id
416  * @vpath_mask: vpath bit mask
417  * @fw_version: Firmware version
418  * @fw_date: Firmware Date
419  * @flash_version: Firmware version
420  * @flash_date: Firmware Date
421  * @mac_addrs: Mac addresses for each vpath
422  * @mac_addr_masks: Mac address masks for each vpath
423  *
424  * Returns the vpath mask that has the bits set for each vpath allocated
425  * for the driver and the first mac address for each vpath
426  */
429 #define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION 0
430 #define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION 1
431 #define VXGE_HW_NO_MR_SR_VH0_FUNCTION0 2
432 #define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3
433 #define VXGE_HW_MR_SR_VH0_INVALID_CONFIG 4
434 #define VXGE_HW_SR_VH_FUNCTION0 5
435 #define VXGE_HW_SR_VH_VIRTUAL_FUNCTION 6
436 #define VXGE_HW_VH_NORMAL_FUNCTION 7
438 #define VXGE_HW_FUNCTION_MODE_MIN 0
439 #define VXGE_HW_FUNCTION_MODE_MAX 11
440 
441 #define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION 0
442 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION 1
443 #define VXGE_HW_FUNCTION_MODE_SRIOV 2
444 #define VXGE_HW_FUNCTION_MODE_MRIOV 3
445 #define VXGE_HW_FUNCTION_MODE_MRIOV_8 4
446 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_17 5
447 #define VXGE_HW_FUNCTION_MODE_SRIOV_8 6
448 #define VXGE_HW_FUNCTION_MODE_SRIOV_4 7
449 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_2 8
450 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_4 9
451 #define VXGE_HW_FUNCTION_MODE_MRIOV_4 10
452 #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_DIRECT_IO 11
453 
463  u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
464  u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
465 };
466 
467 /**
468  * struct __vxge_hw_device - Hal device object
469  * @magic: Magic Number
470  * @bar0: BAR0 virtual address.
471  * @pdev: Physical device handle
472  * @config: Confguration passed by the LL driver at initialization
473  * @link_state: Link state
474  *
475  * HW device object. Represents Titan adapter
476  */
479 #define VXGE_HW_DEVICE_MAGIC 0x12345678
480 #define VXGE_HW_DEVICE_DEAD 0xDEADDEAD
481  void __iomem *bar0;
482  struct pci_device *pdev;
483  struct net_device *ndev;
484  struct vxgedev *vdev;
485 
487 
492 #define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH 0x1
493 #define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM 0x2
494 #define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM 0x4
513 
515 };
516 
517 #define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls)
518 
519 #define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \
520  if (i < 16) { \
521  m0[0] |= vxge_vBIT(0x8, (i*4), 4); \
522  m0[1] |= vxge_vBIT(0x4, (i*4), 4); \
523  } \
524  else { \
525  m1[0] = 0x80000000; \
526  m1[1] = 0x40000000; \
527  } \
528 }
529 
530 #define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \
531  if (i < 16) { \
532  m0[0] &= ~vxge_vBIT(0x8, (i*4), 4); \
533  m0[1] &= ~vxge_vBIT(0x4, (i*4), 4); \
534  } \
535  else { \
536  m1[0] = 0; \
537  m1[1] = 0; \
538  } \
539 }
540 
541 /**
542  * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state.
543  * @VXGE_HW_TXDL_STATE_NONE: Invalid state.
544  * @VXGE_HW_TXDL_STATE_AVAIL: Descriptor is available for reservation.
545  * @VXGE_HW_TXDL_STATE_POSTED: Descriptor is posted for processing by the
546  * device.
547  * @VXGE_HW_TXDL_STATE_FREED: Descriptor is free and can be reused for
548  * filling-in and posting later.
549  *
550  * Titan/HW descriptor states.
551  *
552  */
558 };
559 
560 
561 /* fifo and ring circular buffer offset tracking apis */
562 static inline void __vxge_hw_desc_offset_up(u16 upper_limit,
563  u16 *offset)
564 {
565  if (++(*offset) >= upper_limit)
566  *offset = 0;
567 }
568 
569 /* rxd offset handling apis */
571 {
573  offset);
574 }
575 /* txd offset handling apis */
577 {
579 }
580 
581 /**
582  * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
583  * @rxdh: Descriptor handle.
584  * @dma_pointer: DMA address of a single receive buffer this descriptor
585  * should carry. Note that by the time vxge_hw_ring_rxd_1b_set is called,
586  * the receive buffer should be already mapped to the device
587  * @size: Size of the receive @dma_pointer buffer.
588  *
589  * Prepare 1-buffer-mode Rx descriptor for posting
590  * (via vxge_hw_ring_rxd_post()).
591  *
592  * This inline helper-function does not return any parameters and always
593  * succeeds.
594  *
595  */
596 static inline
598  struct io_buffer *iob, u32 size)
599 {
600  rxdp->host_control = (intptr_t)(iob);
601  rxdp->buffer0_ptr = virt_to_bus(iob->data);
604 }
605 
607  struct pci_device *pdev,
608  void __iomem *bar0,
609  struct vxge_hw_device_hw_info *hw_info);
610 
611 enum vxge_hw_status
613  struct vxge_hw_vpath_reg __iomem *vpath_reg,
614  struct vxge_hw_device_hw_info *hw_info);
615 
616 enum vxge_hw_status
618  struct vxge_hw_vpath_reg __iomem *vpath_reg,
619  struct vxge_hw_device_hw_info *hw_info);
620 
621 /**
622  * vxge_hw_device_link_state_get - Get link state.
623  * @devh: HW device handle.
624  *
625  * Get link state.
626  * Returns: link state.
627  */
628 static inline
630  struct __vxge_hw_device *devh)
631 {
632  return devh->link_state;
633 }
634 
635 void vxge_hw_device_terminate(struct __vxge_hw_device *devh);
636 
638  struct __vxge_hw_device **devh,
639  void *bar0,
640  struct pci_device *pdev,
641  u8 titan1);
642 
643 enum vxge_hw_status
644 vxge_hw_vpath_open(struct __vxge_hw_device *hldev, struct vxge_vpath *vpath);
645 
646 enum vxge_hw_status
648 
650 
652 
653 enum vxge_hw_status
655 
656 void
658 
659 enum vxge_hw_status
660 vxge_hw_vpath_mtu_set(struct __vxge_hw_virtualpath *vpath, u32 new_mtu);
661 
662 void
664 
665 void
667 
668 enum vxge_hw_status
670 
671 enum vxge_hw_status
673 
674 enum vxge_hw_status
676  struct vxge_hw_vpath_reg __iomem *vpath_reg);
677 
678 enum vxge_hw_status
680  void __iomem *reg,
681  u64 mask, u32 max_millis);
682 
683 #ifndef readq
684 static inline u64 readq(void __iomem *addr)
685 {
686  u64 ret = 0;
687  ret = readl(addr + 4);
688  ret <<= 32;
689  ret |= readl(addr);
690 
691  return ret;
692 }
693 #endif
694 
695 #ifndef writeq
696 static inline void writeq(u64 val, void __iomem *addr)
697 {
698  writel((u32) (val), addr);
699  writel((u32) (val >> 32), (addr + 4));
700 }
701 #endif
702 
704 {
705  writel(val, addr + 4);
706 }
707 
709 {
710  writel(val, addr);
711 }
712 
713 static inline enum vxge_hw_status
715  u64 mask, u32 max_millis)
716 {
718 
720  wmb();
722  wmb();
723 
724  status = __vxge_hw_device_register_poll(addr, mask, max_millis);
725  return status;
726 }
727 
728 void
730 
731 enum vxge_hw_status
733 
734 enum vxge_hw_status
736  struct __vxge_hw_virtualpath *vpath,
737  u32 phy_func_0,
738  u32 offset,
739  u32 *val);
740 
741 enum vxge_hw_status
743  struct vxge_hw_vpath_reg __iomem *vpath_reg,
744  u8 (macaddr)[ETH_ALEN],
745  u8 (macaddr_mask)[ETH_ALEN]);
746 
747 u32
749 
750 enum vxge_hw_status
752 
753 enum vxge_hw_status
755 
756 /**
757  * vxge_debug
758  * @mask: mask for the debug
759  * @fmt: printf like format string
760  */
761 static const u16 debug_filter = VXGE_ERR;
762 #define vxge_debug(mask, fmt...) do { \
763  if (debug_filter & mask) \
764  DBG(fmt); \
765  } while (0);
766 
767 #define vxge_trace() vxge_debug(VXGE_TRACE, "%s:%d\n", __func__, __LINE__);
768 
769 enum vxge_hw_status
770 vxge_hw_get_func_mode(struct __vxge_hw_device *hldev, u32 *func_mode);
771 
772 enum vxge_hw_status
774  u64 vp_id, u32 action,
776 void
778 
779 #endif
u64 tim_int_mask0[4]
Definition: vxge_config.h:511
#define VXGE_HW_FIFO_TXD_DEPTH
Definition: vxge_config.h:329
uint16_t u16
Definition: stdint.h:21
vxge_hw_txdl_state
enum enum vxge_hw_txdl_state - Descriptor (TXDL) state.
Definition: vxge_config.h:553
enum vxge_hw_status __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath, u32 phy_func_0, u32 offset, u32 *val)
Definition: vxge_config.c:864
wmb()
struct vxge_hw_device_date fw_date
Definition: vxge_config.h:457
enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1760
#define VXGE_HW_BASE_BADCFG
Definition: vxge_config.h:66
struct __vxge_hw_virtualpath * vpathh
Definition: vxge_config.h:334
struct vxge_hw_device_date flash_date
Definition: vxge_config.h:459
struct vxge_hw_legacy_reg * legacy_reg
Definition: vxge_config.h:495
struct vxge_hw_fifo_txd - Transmit Descriptor
Definition: vxge_config.h:212
vxge_hw_device_link_state
enum enum vxge_hw_device_link_state - Link state enumeration.
Definition: vxge_config.h:139
struct vxge_hw_device_version fw_version
Definition: vxge_config.h:456
char date[VXGE_HW_FW_STRLEN]
Definition: vxge_config.h:262
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
struct __vxge_hw_virtualpath * vpathh
Definition: vxge_config.h:379
#define VXGE_HW_FW_STRLEN
struct vxge_hw_device_date - Date Format @day: Day @month: Month @year: Year
Definition: vxge_config.h:257
u32 data1
Definition: ar9003_mac.h:71
void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
Definition: vxge_config.c:347
struct __vxge_hw_virtualpath virtual_path
Definition: vxge_config.h:507
void vxge_hw_device_terminate(struct __vxge_hw_device *devh)
Definition: vxge_config.c:542
#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK
Definition: vxge_config.h:196
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
struct __vxge_hw_non_offload_db_wrapper * nofl_db
Definition: vxge_config.h:324
u32 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
Definition: vxge_config.c:905
static enum vxge_hw_device_link_state vxge_hw_device_link_state_get(struct __vxge_hw_device *devh)
vxge_hw_device_link_state_get - Get link state.
Definition: vxge_config.h:629
static void vxge_hw_ring_rxd_offset_up(u16 *offset)
Definition: vxge_config.h:570
static void vxge_hw_fifo_txd_offset_up(u16 *offset)
Definition: vxge_config.h:576
u64 __vxge_hw_vpath_pci_func_mode_get(u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg)
unsigned long intptr_t
Definition: stdint.h:21
static void __vxge_hw_desc_offset_up(u16 upper_limit, u16 *offset)
Definition: vxge_config.h:562
enum vxge_hw_status vxge_hw_get_func_mode(struct __vxge_hw_device *hldev, u32 *func_mode)
Definition: vxge_config.c:97
struct vxge_hw_device_hw_info - Device information @host_type: Host Type @func_id: Function Id @vpath...
Definition: vxge_config.h:427
enum vxge_hw_status __vxge_hw_vpath_card_info_get(struct vxge_hw_vpath_reg __iomem *vpath_reg, struct vxge_hw_device_hw_info *hw_info)
Definition: vxge_config.c:935
enum vxge_hw_status __vxge_hw_vpath_addr_get(struct vxge_hw_vpath_reg __iomem *vpath_reg, u8(macaddr)[ETH_ALEN], u8(macaddr_mask)[ETH_ALEN])
struct vxgedev * vdev
Definition: vxge_config.h:484
uint8_t status
Status.
Definition: ena.h:16
#define VXGE_HW_TITAN_SRPCIM_REG_SPACES
Definition: vxge_reg.h:52
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:361
u64 vpath_rst_in_prog
Definition: vxge_reg.h:167
FILE_LICENCE(GPL2_ONLY)
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
enum vxge_hw_status __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg, struct vxge_hw_vpath_reg __iomem *vpath_reg)
Definition: vxge_config.c:760
#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val)
Definition: vxge_config.h:195
struct io_buffer * iobuf[VXGE_HW_RING_BUF_PER_BLOCK+1]
Definition: vxge_config.h:378
static const u16 debug_filter
vxge_debug @mask: mask for the debug @fmt: printf like format string
Definition: vxge_config.h:761
u8 serial_number[VXGE_HW_INFO_LEN]
Definition: vxge_config.h:460
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:362
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define VXGE_HW_MAX_VIRTUAL_PATHS
Definition: vxge_traffic.h:30
enum vxge_hw_status vxge_hw_vpath_recover_from_reset(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1818
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
uint64_t u64
Definition: stdint.h:25
u32 tim_int_mask1[4]
Definition: vxge_config.h:512
#define VXGE_HW_TITAN_VPATH_REG_SPACES
Definition: vxge_reg.h:54
void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1737
enum vxge_hw_status __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
Definition: vxge_config.c:178
struct __vxge_hw_ring_block * rxdl
Definition: vxge_config.h:370
struct vxge_hw_device_version flash_version
Definition: vxge_config.h:458
enum vxge_hw_status __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1249
enum vxge_hw_status vxge_hw_set_fw_api(struct __vxge_hw_device *hldev, u64 vp_id, u32 action, u32 offset, u64 data0, u64 data1)
Definition: vxge_config.c:47
Linked lists.
#define VXGE_HW_TITAN_VPMGMT_REG_SPACES
Definition: vxge_reg.h:53
void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
Definition: vxge_config.c:126
#define vxge_bVALn(bits, loc, n)
Definition: vxge_reg.h:35
static unsigned int unsigned int reg
Definition: intel.h:245
PCI bus.
A PCI device.
Definition: pci.h:187
u8(mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]
#define VXGE_HW_BASE_ERR
Definition: vxge_config.h:65
#define VXGE_HW_INFO_LEN
Definition: vxge_config.h:409
A network device.
Definition: netdevice.h:348
enum vxge_hw_status vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
Definition: vxge_config.c:789
u32 addr
Definition: sky2.h:8
enum vxge_hw_status __vxge_hw_vpath_fw_ver_get(struct vxge_hw_vpath_reg __iomem *vpath_reg, struct vxge_hw_device_hw_info *hw_info)
Definition: vxge_config.c:1056
u8 product_desc[VXGE_HW_INFO_LEN]
Definition: vxge_config.h:462
static enum vxge_hw_status __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr, u64 mask, u32 max_millis)
Definition: vxge_config.h:714
enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1793
enum vxge_hw_status vxge_hw_device_initialize(struct __vxge_hw_device **devh, void *bar0, struct pci_device *pdev, u8 titan1)
Definition: vxge_config.c:495
struct vxge_hw_vpath_reg * vpath_reg[VXGE_HW_TITAN_VPATH_REG_SPACES]
Definition: vxge_config.h:503
#define ETH_ALEN
Definition: if_ether.h:8
struct vxge_hw_vpmgmt_reg * vpmgmt_reg[VXGE_HW_TITAN_VPMGMT_REG_SPACES]
Definition: vxge_config.h:501
void __asmcall int val
Definition: setjmp.h:28
struct __vxge_hw_non_offload_db_wrapper * nofl_db
Definition: vxge_config.h:399
enum vxge_hw_status vxge_hw_vpath_open(struct __vxge_hw_device *hldev, struct vxge_vpath *vpath)
Definition: vxge_config.c:1690
void __iomem * bar0
Definition: vxge_config.h:481
struct __vxge_hw_device - Hal device object @magic: Magic Number @bar0: BAR0 virtual address.
Definition: vxge_config.h:477
struct vxge_hw_device_hw_info hw_info
Definition: vxge_config.h:514
void vxge_hw_vpath_set_zero_rx_frm_len(struct __vxge_hw_device *hldev)
Definition: vxge_config.c:30
struct vxge_hw_vpmgmt_reg * vpmgmt_reg
Definition: vxge_config.h:398
u8 part_number[VXGE_HW_INFO_LEN]
Definition: vxge_config.h:461
static void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr)
Definition: vxge_config.h:708
struct __vxge_hw_ring ringh
Definition: vxge_config.h:406
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:397
struct vxge_hw_toc_reg * toc_reg
Definition: vxge_config.h:496
void * data
Start of data.
Definition: iobuf.h:44
static void vxge_hw_ring_rxd_1b_set(struct vxge_hw_ring_rxd_1 *rxdp, struct io_buffer *iob, u32 size)
vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
Definition: vxge_config.h:597
#define __iomem
Definition: vxge_config.h:39
enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
#define VXGE_HW_RING_BUF_PER_BLOCK
Definition: vxge_config.h:371
vxge_hw_status
Definition: vxge_config.h:70
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
enum vxge_hw_status vxge_hw_device_hw_info_get(struct pci_device *pdev, void __iomem *bar0, struct vxge_hw_device_hw_info *hw_info)
vxge_hw_device_hw_info_get - Get the hw information Returns the vpath mask that has the bits set for ...
Definition: vxge_config.c:384
Definition: sis900.h:32
struct pci_device * pdev
Definition: vxge_config.h:482
enum vxge_hw_status vxge_hw_vpath_mtu_set(struct __vxge_hw_virtualpath *vpath, u32 new_mtu)
Definition: vxge_config.c:1661
enum vxge_hw_status __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
Definition: vxge_config.c:739
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:323
void vxge_hw_vpath_enable(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_config.c:1854
struct __vxge_hw_device * hldev
Definition: vxge_config.h:396
struct vxge_hw_mrpcim_reg * mrpcim_reg
Definition: vxge_config.h:498
struct __vxge_hw_fifo fifoh
Definition: vxge_config.h:407
struct vxge_hw_fifo_txd * txdl
Definition: vxge_config.h:328
u32 data0
Definition: ar9003_mac.h:69
enum vxge_hw_status __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
Definition: vxge_config.c:683
enum vxge_hw_status __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
Definition: vxge_config.c:147
struct vxge_hw_ring_rxd_1 rxd[VXGE_HW_MAX_RXDS_PER_BLOCK_1]
Definition: vxge_config.h:342
struct net_device * ndev
Definition: vxge_config.h:483
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
#define VXGE_HW_BASE_INF
Definition: vxge_config.h:64
struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
Definition: vxge_config.h:154
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
#define VXGE_ERR
Definition: vxge_config.h:54
#define VXGE_HW_MAX_RXDS_PER_BLOCK_1
Definition: vxge_config.h:341
struct vxge_hw_srpcim_reg * srpcim_reg[VXGE_HW_TITAN_SRPCIM_REG_SPACES]
Definition: vxge_config.h:499
A persistent I/O buffer.
Definition: iobuf.h:32
char version[VXGE_HW_FW_STRLEN]
Definition: vxge_config.h:269
enum vxge_hw_device_link_state link_state
Definition: vxge_config.h:486