iPXE
amd8111e.c
Go to the documentation of this file.
00001 /* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver 
00002  * Copyright (C) 2004 Advanced Micro Devices 
00003  * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
00004  * 
00005  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
00006  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
00007  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
00008  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
00009  * Copyright 1993 United States Government as represented by the
00010  *      Director, National Security Agency.[ pcnet32.c ]
00011  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
00012  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
00013  *
00014  * 
00015  * This program is free software; you can redistribute it and/or modify
00016  * it under the terms of the GNU General Public License as published by
00017  * the Free Software Foundation; either version 2 of the License, or
00018  * (at your option) any later version.
00019  *
00020  * This program is distributed in the hope that it will be useful,
00021  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00022  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00023  * GNU General Public License for more details.
00024  *
00025  * You should have received a copy of the GNU General Public License
00026  * along with this program; if not, write to the Free Software
00027  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00028  * 02110-1301, USA.
00029  * USA
00030  */
00031 
00032 FILE_LICENCE ( GPL2_OR_LATER );
00033 
00034 #include "etherboot.h"
00035 #include "nic.h"
00036 #include "mii.h"
00037 #include <ipxe/pci.h>
00038 #include <ipxe/ethernet.h>
00039 #include "string.h"
00040 #include "stdint.h"
00041 #include "amd8111e.h"
00042 
00043 
00044 /* driver definitions */
00045 #define NUM_TX_SLOTS    2
00046 #define NUM_RX_SLOTS    4
00047 #define TX_SLOTS_MASK   1
00048 #define RX_SLOTS_MASK   3
00049 
00050 #define TX_BUF_LEN      1536
00051 #define RX_BUF_LEN      1536
00052 
00053 #define TX_PKT_LEN_MAX  (ETH_FRAME_LEN - ETH_HLEN)
00054 #define RX_PKT_LEN_MIN  60
00055 #define RX_PKT_LEN_MAX  ETH_FRAME_LEN
00056 
00057 #define TX_TIMEOUT      3000
00058 #define TX_PROCESS_TIME 10
00059 #define TX_RETRY        (TX_TIMEOUT / TX_PROCESS_TIME)
00060 
00061 #define PHY_RW_RETRY    10
00062 
00063 
00064 struct amd8111e_tx_desc {
00065         u16 buf_len;
00066         u16 tx_flags;
00067         u16 tag_ctrl_info;
00068         u16 tag_ctrl_cmd;
00069         u32 buf_phy_addr;
00070         u32 reserved;
00071 }; 
00072 
00073 struct amd8111e_rx_desc {
00074         u32 reserved;
00075         u16 msg_len;
00076         u16 tag_ctrl_info; 
00077         u16 buf_len;
00078         u16 rx_flags;
00079         u32 buf_phy_addr;
00080 };
00081 
00082 struct eth_frame {
00083         u8 dst_addr[ETH_ALEN];
00084         u8 src_addr[ETH_ALEN];
00085         u16 type;
00086         u8 data[ETH_FRAME_LEN - ETH_HLEN];
00087 } __attribute__((packed));
00088 
00089 struct amd8111e_priv {
00090         struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS];
00091         struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS];
00092         unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
00093         unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
00094         unsigned long tx_idx, rx_idx;
00095         int tx_consistent;
00096 
00097         char opened;
00098         char link;
00099         char speed;
00100         char duplex;
00101         int ext_phy_addr;
00102         u32 ext_phy_id;
00103 
00104         struct pci_device *pdev;
00105         struct nic *nic;
00106         void *mmio;
00107 };
00108 
00109 static struct amd8111e_priv amd8111e;
00110 
00111 
00112 /********************************************************
00113  *              locale functions                        *
00114  ********************************************************/
00115 static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
00116 static int amd8111e_start(struct amd8111e_priv *lp);
00117 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
00118 #if 0
00119 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
00120 #endif
00121 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
00122 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
00123 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
00124 static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
00125 static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
00126 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
00127 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
00128 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
00129 static void amd8111e_wait_link(struct amd8111e_priv *lp);
00130 static void amd8111e_poll_link(struct amd8111e_priv *lp);
00131 static void amd8111e_restart(struct amd8111e_priv *lp);
00132 
00133 
00134 /* 
00135  * This function clears necessary the device registers. 
00136  */     
00137 static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
00138 {
00139         unsigned int reg_val;
00140         void *mmio = lp->mmio;
00141 
00142         /* stop the chip */
00143         writel(RUN, mmio + CMD0);
00144 
00145         /* Clear RCV_RING_BASE_ADDR */
00146         writel(0, mmio + RCV_RING_BASE_ADDR0);
00147 
00148         /* Clear XMT_RING_BASE_ADDR */
00149         writel(0, mmio + XMT_RING_BASE_ADDR0);
00150         writel(0, mmio + XMT_RING_BASE_ADDR1);
00151         writel(0, mmio + XMT_RING_BASE_ADDR2);
00152         writel(0, mmio + XMT_RING_BASE_ADDR3);
00153 
00154         /* Clear CMD0  */
00155         writel(CMD0_CLEAR, mmio + CMD0);
00156         
00157         /* Clear CMD2 */
00158         writel(CMD2_CLEAR, mmio + CMD2);
00159 
00160         /* Clear CMD7 */
00161         writel(CMD7_CLEAR, mmio + CMD7);
00162 
00163         /* Clear DLY_INT_A and DLY_INT_B */
00164         writel(0x0, mmio + DLY_INT_A);
00165         writel(0x0, mmio + DLY_INT_B);
00166 
00167         /* Clear FLOW_CONTROL */
00168         writel(0x0, mmio + FLOW_CONTROL);
00169 
00170         /* Clear INT0  write 1 to clear register */
00171         reg_val = readl(mmio + INT0);
00172         writel(reg_val, mmio + INT0);
00173 
00174         /* Clear STVAL */
00175         writel(0x0, mmio + STVAL);
00176 
00177         /* Clear INTEN0 */
00178         writel(INTEN0_CLEAR, mmio + INTEN0);
00179 
00180         /* Clear LADRF */
00181         writel(0x0, mmio + LADRF);
00182 
00183         /* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
00184         writel(0x80010, mmio + SRAM_SIZE);
00185 
00186         /* Clear RCV_RING0_LEN */
00187         writel(0x0, mmio +  RCV_RING_LEN0);
00188 
00189         /* Clear XMT_RING0/1/2/3_LEN */
00190         writel(0x0, mmio +  XMT_RING_LEN0);
00191         writel(0x0, mmio +  XMT_RING_LEN1);
00192         writel(0x0, mmio +  XMT_RING_LEN2);
00193         writel(0x0, mmio +  XMT_RING_LEN3);
00194 
00195         /* Clear XMT_RING_LIMIT */
00196         writel(0x0, mmio + XMT_RING_LIMIT);
00197 
00198         /* Clear MIB */
00199         writew(MIB_CLEAR, mmio + MIB_ADDR);
00200 
00201         /* Clear LARF */
00202         writel( 0, mmio + LADRF);
00203         writel( 0, mmio + LADRF + 4);
00204 
00205         /* SRAM_SIZE register */
00206         reg_val = readl(mmio + SRAM_SIZE);
00207         
00208         /* Set default value to CTRL1 Register */
00209         writel(CTRL1_DEFAULT, mmio + CTRL1);
00210 
00211         /* To avoid PCI posting bug */
00212         readl(mmio + CMD2);
00213 }
00214 
00215 /* 
00216  * This function initializes the device registers  and starts the device.  
00217  */
00218 static int amd8111e_start(struct amd8111e_priv *lp)
00219 {
00220         struct nic *nic = lp->nic;
00221         void *mmio = lp->mmio;
00222         int i, reg_val;
00223 
00224         /* stop the chip */
00225         writel(RUN, mmio + CMD0);
00226 
00227         /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
00228         writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
00229 
00230         /* enable the port manager and set auto negotiation always */
00231         writel(VAL1 | EN_PMGR, mmio + CMD3 );
00232         writel(XPHYANE | XPHYRST, mmio + CTRL2); 
00233 
00234         /* set control registers */
00235         reg_val = readl(mmio + CTRL1);
00236         reg_val &= ~XMTSP_MASK;
00237         writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
00238 
00239         /* initialize tx and rx ring base addresses */
00240         amd8111e_init_tx_ring(lp);
00241         amd8111e_init_rx_ring(lp);
00242         writel(virt_to_bus(lp->tx_ring), mmio + XMT_RING_BASE_ADDR0);
00243         writel(virt_to_bus(lp->rx_ring), mmio + RCV_RING_BASE_ADDR0);
00244         writew(NUM_TX_SLOTS, mmio + XMT_RING_LEN0);
00245         writew(NUM_RX_SLOTS, mmio + RCV_RING_LEN0);
00246         
00247         /* set default IPG to 96 */
00248         writew(DEFAULT_IPG, mmio + IPG);
00249         writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1); 
00250 
00251         /* AutoPAD transmit, Retransmit on Underflow */
00252         writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
00253         
00254         /* JUMBO disabled */
00255         writel(JUMBO, mmio + CMD3);
00256 
00257         /* Setting the MAC address to the device */
00258         for(i = 0; i < ETH_ALEN; i++)
00259                 writeb(nic->node_addr[i], mmio + PADR + i); 
00260 
00261         /* set RUN bit to start the chip, interrupt not enabled */
00262         writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
00263         
00264         /* To avoid PCI posting bug */
00265         readl(mmio + CMD0);
00266         return 0;
00267 }
00268 
00269 /* 
00270 This function will read the PHY registers.
00271 */
00272 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
00273 {
00274         void *mmio = lp->mmio;
00275         unsigned int reg_val;
00276         unsigned int retry = PHY_RW_RETRY;
00277 
00278         reg_val = readl(mmio + PHY_ACCESS);
00279         while (reg_val & PHY_CMD_ACTIVE)
00280                 reg_val = readl(mmio + PHY_ACCESS);
00281 
00282         writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
00283                 mmio + PHY_ACCESS);
00284         do {
00285                 reg_val = readl(mmio + PHY_ACCESS);
00286                 udelay(30);  /* It takes 30 us to read/write data */
00287         } while (--retry && (reg_val & PHY_CMD_ACTIVE));
00288 
00289         if (reg_val & PHY_RD_ERR) {
00290                 *val = 0;
00291                 return -1;
00292         }
00293         
00294         *val = reg_val & 0xffff;
00295         return 0;
00296 }
00297 
00298 /* 
00299 This function will write into PHY registers. 
00300 */
00301 #if 0
00302 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
00303 {
00304         void *mmio = lp->mmio;
00305         unsigned int reg_val;
00306         unsigned int retry = PHY_RW_RETRY;
00307 
00308         reg_val = readl(mmio + PHY_ACCESS);
00309         while (reg_val & PHY_CMD_ACTIVE)
00310                 reg_val = readl(mmio + PHY_ACCESS);
00311 
00312         writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
00313                 mmio + PHY_ACCESS);
00314         do {
00315                 reg_val = readl(mmio + PHY_ACCESS);
00316                 udelay(30);  /* It takes 30 us to read/write the data */
00317         } while (--retry && (reg_val & PHY_CMD_ACTIVE));
00318         
00319         if(reg_val & PHY_RD_ERR)
00320                 return -1;
00321 
00322         return 0;
00323 }
00324 #endif
00325 
00326 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
00327 {
00328         int i;
00329 
00330         lp->ext_phy_id = 0;
00331         lp->ext_phy_addr = 1;
00332         
00333         for (i = 0x1e; i >= 0; i--) {
00334                 u32 id1, id2;
00335 
00336                 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
00337                         continue;
00338                 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
00339                         continue;
00340                 lp->ext_phy_id = (id1 << 16) | id2;
00341                 lp->ext_phy_addr = i;
00342                 break;
00343         }
00344 
00345         if (lp->ext_phy_id)
00346                 printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
00347                        (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
00348         else
00349                 printf("Couldn't detect MII PHY, assuming address 0x01\n");
00350 }
00351 
00352 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
00353 {
00354         void *mmio = lp->mmio;
00355         unsigned int int0;
00356 
00357         writel(INTREN, mmio + CMD0);
00358         writel(INTEN0_CLEAR, mmio + INTEN0);
00359         int0 = readl(mmio + INT0);
00360         writel(int0, mmio + INT0);
00361         readl(mmio + INT0);
00362 }
00363 
00364 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
00365 {
00366         void *mmio = lp->mmio;
00367 
00368         writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
00369         writel(VAL0 | INTREN, mmio + CMD0);
00370         readl(mmio + CMD0);
00371 }
00372 
00373 static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
00374 {
00375         void *mmio = lp->mmio;
00376 
00377         writel(VAL0 | UINTCMD, mmio + CMD0);
00378         readl(mmio + CMD0);
00379 }
00380 
00381 static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
00382 {
00383         struct nic *nic = lp->nic;
00384         void *mmio = lp->mmio;
00385         int i;
00386 
00387         /* BIOS should have set mac address to PADR register,
00388          * so we read PADR to get it.
00389          */
00390         for (i = 0; i < ETH_ALEN; i++)
00391                 nic->node_addr[i] = readb(mmio + PADR + i);
00392 
00393         DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
00394 
00395         return 0;
00396 }
00397 
00398 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
00399 {
00400         int i;
00401 
00402         lp->rx_idx = 0;
00403         
00404         /* Initilaizing receive descriptors */
00405         for (i = 0; i < NUM_RX_SLOTS; i++) {
00406                 lp->rx_ring[i].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[i]));
00407                 lp->rx_ring[i].buf_len = cpu_to_le16(RX_BUF_LEN);
00408                 wmb();
00409                 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
00410         }
00411 
00412         return 0;
00413 }
00414 
00415 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
00416 {
00417         int i;
00418 
00419         lp->tx_idx = 0;
00420         lp->tx_consistent = 1;
00421         
00422         /* Initializing transmit descriptors */
00423         for (i = 0; i < NUM_TX_SLOTS; i++) {
00424                 lp->tx_ring[i].tx_flags = 0;
00425                 lp->tx_ring[i].buf_phy_addr = 0;
00426                 lp->tx_ring[i].buf_len = 0;
00427         }
00428 
00429         return 0;
00430 }
00431 
00432 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
00433 {
00434         volatile u16 status;
00435         int retry = TX_RETRY;
00436 
00437         status = le16_to_cpu(lp->tx_ring[index].tx_flags);
00438         while (--retry && (status & OWN_BIT)) {
00439                 mdelay(TX_PROCESS_TIME);
00440                 status = le16_to_cpu(lp->tx_ring[index].tx_flags);
00441         }
00442         if (status & OWN_BIT) {
00443                 printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
00444                 amd8111e_restart(lp);
00445                 return -1;
00446         }
00447 
00448         return 0;
00449 }
00450 
00451 static void amd8111e_wait_link(struct amd8111e_priv *lp)
00452 {
00453         unsigned int status;
00454         u32 reg_val;
00455 
00456         do {
00457                 /* read phy to update STAT0 register */
00458                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
00459                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
00460                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
00461                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
00462                 status = readl(lp->mmio + STAT0);
00463         } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
00464 }
00465 
00466 static void amd8111e_poll_link(struct amd8111e_priv *lp)
00467 {
00468         unsigned int status, speed;
00469         u32 reg_val;
00470 
00471         if (!lp->link) {
00472                 /* read phy to update STAT0 register */
00473                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
00474                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
00475                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
00476                 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
00477                 status = readl(lp->mmio + STAT0);
00478 
00479                 if (status & LINK_STATS) {
00480                         lp->link = 1;
00481                         speed = (status & SPEED_MASK) >> 7;
00482                         if (speed == PHY_SPEED_100)
00483                                 lp->speed = 1;
00484                         else
00485                                 lp->speed = 0;
00486                         if (status & FULL_DPLX)
00487                                 lp->duplex = 1;
00488                         else
00489                                 lp->duplex = 0;
00490 
00491                         printf("Link is up: %s Mbps %s duplex\n",
00492                                 lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
00493                 }
00494         } else {
00495                 status = readl(lp->mmio + STAT0);
00496                 if (!(status & LINK_STATS)) {
00497                         lp->link = 0;
00498                         printf("Link is down\n");
00499                 }
00500         }
00501 }
00502 
00503 static void amd8111e_restart(struct amd8111e_priv *lp)
00504 {
00505         printf("\nStarting nic...\n");
00506         amd8111e_disable_interrupt(lp);
00507         amd8111e_init_hw_default(lp);
00508         amd8111e_probe_ext_phy(lp);
00509         amd8111e_get_mac_address(lp);
00510         amd8111e_start(lp);
00511 
00512         printf("Waiting link up...\n");
00513         lp->link = 0;
00514         amd8111e_wait_link(lp);
00515         amd8111e_poll_link(lp);
00516 }
00517 
00518 
00519 /********************************************************
00520  *              Interface Functions                     *
00521  ********************************************************/
00522 
00523 static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
00524                 unsigned int type, unsigned int size, const char *packet)
00525 {
00526         struct amd8111e_priv *lp = nic->priv_data;
00527         struct eth_frame *frame;
00528         unsigned int index;
00529 
00530         /* check packet size */
00531         if (size > TX_PKT_LEN_MAX) {
00532                 printf("amd8111e_transmit(): too large packet, drop\n");
00533                 return;
00534         }
00535 
00536         /* get tx slot */
00537         index = lp->tx_idx;
00538         if (amd8111e_wait_tx_ring(lp, index))
00539                 return;
00540 
00541         /* fill frame */
00542         frame = (struct eth_frame *)lp->tx_buf[index];
00543         memset(frame->data, 0, TX_PKT_LEN_MAX);
00544         memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
00545         memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
00546         frame->type = htons(type);
00547         memcpy(frame->data, packet, size);
00548 
00549         /* start xmit */
00550         lp->tx_ring[index].buf_len = cpu_to_le16(ETH_HLEN + size);
00551         lp->tx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(frame));
00552         wmb();
00553         lp->tx_ring[index].tx_flags = 
00554                 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT | ADD_FCS_BIT | LTINT_BIT);
00555         writel(VAL1 | TDMD0, lp->mmio + CMD0);
00556         readl(lp->mmio + CMD0);
00557 
00558         /* update slot pointer */
00559         lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
00560 }
00561 
00562 static int amd8111e_poll(struct nic *nic, int retrieve)
00563 {
00564         /* return true if there's an ethernet packet ready to read */
00565         /* nic->packet should contain data on return */
00566         /* nic->packetlen should contain length of data */
00567 
00568         struct amd8111e_priv *lp = nic->priv_data;
00569         u16 status, pkt_len;
00570         unsigned int index, pkt_ok;
00571 
00572         amd8111e_poll_link(lp);
00573 
00574         index = lp->rx_idx;
00575         status = le16_to_cpu(lp->rx_ring[index].rx_flags);
00576         pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4;  /* remove 4bytes FCS */
00577         
00578         if (status & OWN_BIT)
00579                 return 0;
00580 
00581         if (status & ERR_BIT)
00582                 pkt_ok = 0;
00583         else if (!(status & STP_BIT))
00584                 pkt_ok = 0;
00585         else if (!(status & ENP_BIT))
00586                 pkt_ok = 0;
00587         else if (pkt_len < RX_PKT_LEN_MIN)
00588                 pkt_ok = 0;
00589         else if (pkt_len > RX_PKT_LEN_MAX)
00590                 pkt_ok = 0;
00591         else
00592                 pkt_ok = 1;
00593 
00594         if (pkt_ok) {
00595                 if (!retrieve)
00596                         return 1;
00597                 nic->packetlen = pkt_len;
00598                 memcpy(nic->packet, lp->rx_buf[index], nic->packetlen);
00599         }
00600 
00601         lp->rx_ring[index].buf_phy_addr = cpu_to_le32(virt_to_bus(lp->rx_buf[index]));
00602         lp->rx_ring[index].buf_len = cpu_to_le16(RX_BUF_LEN);
00603         wmb();
00604         lp->rx_ring[index].rx_flags = cpu_to_le16(OWN_BIT);
00605         writel(VAL2 | RDMD0, lp->mmio + CMD0);
00606         readl(lp->mmio + CMD0);
00607 
00608         lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
00609         return pkt_ok;
00610 }
00611 
00612 static void amd8111e_disable(struct nic *nic)
00613 {
00614         struct amd8111e_priv *lp = nic->priv_data;
00615 
00616         /* disable interrupt */
00617         amd8111e_disable_interrupt(lp);
00618 
00619         /* stop chip */
00620         amd8111e_init_hw_default(lp);
00621 
00622         /* unmap mmio */
00623         iounmap(lp->mmio);
00624 
00625         /* update status */
00626         lp->opened = 0;
00627 }
00628 
00629 static void amd8111e_irq(struct nic *nic, irq_action_t action)
00630 {
00631         struct amd8111e_priv *lp = nic->priv_data;
00632                 
00633         switch (action) {
00634         case DISABLE:
00635                 amd8111e_disable_interrupt(lp);
00636                 break;
00637         case ENABLE:
00638                 amd8111e_enable_interrupt(lp);
00639                 break;
00640         case FORCE:
00641                 amd8111e_force_interrupt(lp);
00642                 break;
00643         }
00644 }
00645 
00646 static struct nic_operations amd8111e_operations = {
00647         .connect        = dummy_connect,
00648         .poll           = amd8111e_poll,
00649         .transmit       = amd8111e_transmit,
00650         .irq            = amd8111e_irq,
00651 };
00652 
00653 static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
00654 {
00655         struct amd8111e_priv *lp = &amd8111e;
00656         unsigned long mmio_start, mmio_len;
00657 
00658         nic->ioaddr = pdev->ioaddr;
00659         nic->irqno  = pdev->irq;
00660         
00661         mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
00662         mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
00663 
00664         memset(lp, 0, sizeof(*lp));
00665         lp->pdev = pdev;
00666         lp->nic = nic;
00667         lp->mmio = ioremap(mmio_start, mmio_len);
00668         lp->opened = 1;
00669         adjust_pci_device(pdev);
00670 
00671         nic->priv_data = lp;
00672 
00673         amd8111e_restart(lp);
00674 
00675         nic->nic_op     = &amd8111e_operations;
00676         return 1;
00677 }
00678 
00679 static struct pci_device_id amd8111e_nics[] = {
00680         PCI_ROM(0x1022, 0x7462, "amd8111e",     "AMD8111E", 0),
00681 };
00682 
00683 PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
00684 
00685 DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
00686          amd8111e_probe, amd8111e_disable );
00687 
00688 /*
00689  * Local variables:
00690  *  c-basic-offset: 8
00691  *  c-indent-level: 8
00692  *  tab-width: 8
00693  * End:
00694  */