iPXE
tg3_phy.c
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00001 
00002 #include <mii.h>
00003 #include <stdio.h>
00004 #include <errno.h>
00005 #include <unistd.h>
00006 #include <byteswap.h>
00007 #include <ipxe/pci.h>
00008 
00009 #include "tg3.h"
00010 
00011 static void tg3_link_report(struct tg3 *tp);
00012 
00013 void tg3_mdio_init(struct tg3 *tp)
00014 {       DBGP("%s\n", __func__);
00015 
00016         if (tg3_flag(tp, 5717_PLUS)) {
00017                 u32 is_serdes;
00018 
00019                 tp->phy_addr = PCI_FUNC(tp->pdev->busdevfn) + 1;
00020 
00021                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
00022                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
00023                 else
00024                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
00025                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
00026                 if (is_serdes)
00027                         tp->phy_addr += 7;
00028         } else
00029                 tp->phy_addr = TG3_PHY_MII_ADDR;
00030 }
00031 
00032 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
00033 {       DBGP("%s\n", __func__);
00034 
00035         int i;
00036         u32 val;
00037 
00038         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
00039         tw32(OTP_CTRL, cmd);
00040 
00041         /* Wait for up to 1 ms for command to execute. */
00042         for (i = 0; i < 100; i++) {
00043                 val = tr32(OTP_STATUS);
00044                 if (val & OTP_STATUS_CMD_DONE)
00045                         break;
00046                 udelay(10);
00047         }
00048 
00049         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
00050 }
00051 
00052 /* Read the gphy configuration from the OTP region of the chip.  The gphy
00053  * configuration is a 32-bit value that straddles the alignment boundary.
00054  * We do two 32-bit reads and then shift and merge the results.
00055  */
00056 u32 tg3_read_otp_phycfg(struct tg3 *tp)
00057 {       DBGP("%s\n", __func__);
00058 
00059         u32 bhalf_otp, thalf_otp;
00060 
00061         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
00062 
00063         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
00064                 return 0;
00065 
00066         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
00067 
00068         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
00069                 return 0;
00070 
00071         thalf_otp = tr32(OTP_READ_DATA);
00072 
00073         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
00074 
00075         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
00076                 return 0;
00077 
00078         bhalf_otp = tr32(OTP_READ_DATA);
00079 
00080         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
00081 }
00082 
00083 #define PHY_BUSY_LOOPS  5000
00084 
00085 int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
00086 {       DBGP("%s\n", __func__);
00087 
00088         u32 frame_val;
00089         unsigned int loops;
00090         int ret;
00091 
00092         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
00093                 tw32_f(MAC_MI_MODE,
00094                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
00095                 udelay(80);
00096         }
00097 
00098         *val = 0x0;
00099 
00100         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
00101                       MI_COM_PHY_ADDR_MASK);
00102         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
00103                       MI_COM_REG_ADDR_MASK);
00104         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
00105 
00106         tw32_f(MAC_MI_COM, frame_val);
00107 
00108         loops = PHY_BUSY_LOOPS;
00109         while (loops != 0) {
00110                 udelay(10);
00111                 frame_val = tr32(MAC_MI_COM);
00112 
00113                 if ((frame_val & MI_COM_BUSY) == 0) {
00114                         udelay(5);
00115                         frame_val = tr32(MAC_MI_COM);
00116                         break;
00117                 }
00118                 loops -= 1;
00119         }
00120 
00121         ret = -EBUSY;
00122         if (loops != 0) {
00123                 *val = frame_val & MI_COM_DATA_MASK;
00124                 ret = 0;
00125         }
00126 
00127         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
00128                 tw32_f(MAC_MI_MODE, tp->mi_mode);
00129                 udelay(80);
00130         }
00131 
00132         return ret;
00133 }
00134 
00135 struct subsys_tbl_ent {
00136         u16 subsys_vendor, subsys_devid;
00137         u32 phy_id;
00138 };
00139 
00140 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
00141         /* Broadcom boards. */
00142         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00143           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
00144         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00145           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
00146         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00147           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
00148         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00149           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
00150         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00151           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
00152         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00153           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
00154         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00155           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
00156         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00157           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
00158         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00159           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
00160         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00161           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
00162         { TG3PCI_SUBVENDOR_ID_BROADCOM,
00163           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
00164 
00165         /* 3com boards. */
00166         { TG3PCI_SUBVENDOR_ID_3COM,
00167           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
00168         { TG3PCI_SUBVENDOR_ID_3COM,
00169           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
00170         { TG3PCI_SUBVENDOR_ID_3COM,
00171           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
00172         { TG3PCI_SUBVENDOR_ID_3COM,
00173           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
00174         { TG3PCI_SUBVENDOR_ID_3COM,
00175           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
00176 
00177         /* DELL boards. */
00178         { TG3PCI_SUBVENDOR_ID_DELL,
00179           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
00180         { TG3PCI_SUBVENDOR_ID_DELL,
00181           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
00182         { TG3PCI_SUBVENDOR_ID_DELL,
00183           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
00184         { TG3PCI_SUBVENDOR_ID_DELL,
00185           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
00186 
00187         /* Compaq boards. */
00188         { TG3PCI_SUBVENDOR_ID_COMPAQ,
00189           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
00190         { TG3PCI_SUBVENDOR_ID_COMPAQ,
00191           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
00192         { TG3PCI_SUBVENDOR_ID_COMPAQ,
00193           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
00194         { TG3PCI_SUBVENDOR_ID_COMPAQ,
00195           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
00196         { TG3PCI_SUBVENDOR_ID_COMPAQ,
00197           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
00198 
00199         /* IBM boards. */
00200         { TG3PCI_SUBVENDOR_ID_IBM,
00201           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
00202 };
00203 
00204 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
00205 {       DBGP("%s\n", __func__);
00206 
00207         int i;
00208 
00209         DBGC(tp->dev, "Matching with: %x:%x\n", tp->subsystem_vendor, tp->subsystem_device);
00210 
00211         for (i = 0; i < (int) ARRAY_SIZE(subsys_id_to_phy_id); i++) {
00212                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
00213                      tp->subsystem_vendor) &&
00214                     (subsys_id_to_phy_id[i].subsys_devid ==
00215                      tp->subsystem_device))
00216                         return &subsys_id_to_phy_id[i];
00217         }
00218         return NULL;
00219 }
00220 
00221 int tg3_writephy(struct tg3 *tp, int reg, u32 val)
00222 {       DBGP("%s\n", __func__);
00223 
00224         u32 frame_val;
00225         unsigned int loops;
00226         int ret;
00227 
00228         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
00229             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
00230                 return 0;
00231 
00232         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
00233                 tw32_f(MAC_MI_MODE,
00234                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
00235                 udelay(80);
00236         }
00237 
00238         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
00239                       MI_COM_PHY_ADDR_MASK);
00240         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
00241                       MI_COM_REG_ADDR_MASK);
00242         frame_val |= (val & MI_COM_DATA_MASK);
00243         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
00244 
00245         tw32_f(MAC_MI_COM, frame_val);
00246 
00247         loops = PHY_BUSY_LOOPS;
00248         while (loops != 0) {
00249                 udelay(10);
00250                 frame_val = tr32(MAC_MI_COM);
00251                 if ((frame_val & MI_COM_BUSY) == 0) {
00252                         udelay(5);
00253                         frame_val = tr32(MAC_MI_COM);
00254                         break;
00255                 }
00256                 loops -= 1;
00257         }
00258 
00259         ret = -EBUSY;
00260         if (loops != 0)
00261                 ret = 0;
00262 
00263         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
00264                 tw32_f(MAC_MI_MODE, tp->mi_mode);
00265                 udelay(80);
00266         }
00267 
00268         return ret;
00269 }
00270 
00271 static int tg3_bmcr_reset(struct tg3 *tp)
00272 {       DBGP("%s\n", __func__);
00273 
00274         u32 phy_control;
00275         int limit, err;
00276 
00277         /* OK, reset it, and poll the BMCR_RESET bit until it
00278          * clears or we time out.
00279          */
00280         phy_control = BMCR_RESET;
00281         err = tg3_writephy(tp, MII_BMCR, phy_control);
00282         if (err != 0)
00283                 return -EBUSY;
00284 
00285         limit = 5000;
00286         while (limit--) {
00287                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
00288                 if (err != 0)
00289                         return -EBUSY;
00290 
00291                 if ((phy_control & BMCR_RESET) == 0) {
00292                         udelay(40);
00293                         break;
00294                 }
00295                 udelay(10);
00296         }
00297         if (limit < 0)
00298                 return -EBUSY;
00299 
00300         return 0;
00301 }
00302 
00303 static int tg3_wait_macro_done(struct tg3 *tp)
00304 {       DBGP("%s\n", __func__);
00305 
00306         int limit = 100;
00307 
00308         while (limit--) {
00309                 u32 tmp32;
00310 
00311                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
00312                         if ((tmp32 & 0x1000) == 0)
00313                                 break;
00314                 }
00315         }
00316         if (limit < 0)
00317                 return -EBUSY;
00318 
00319         return 0;
00320 }
00321 
00322 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
00323 {       DBGP("%s\n", __func__);
00324 
00325         static const u32 test_pat[4][6] = {
00326         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
00327         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
00328         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
00329         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
00330         };
00331         int chan;
00332 
00333         for (chan = 0; chan < 4; chan++) {
00334                 int i;
00335 
00336                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
00337                              (chan * 0x2000) | 0x0200);
00338                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
00339 
00340                 for (i = 0; i < 6; i++)
00341                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
00342                                      test_pat[chan][i]);
00343 
00344                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
00345                 if (tg3_wait_macro_done(tp)) {
00346                         *resetp = 1;
00347                         return -EBUSY;
00348                 }
00349 
00350                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
00351                              (chan * 0x2000) | 0x0200);
00352                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
00353                 if (tg3_wait_macro_done(tp)) {
00354                         *resetp = 1;
00355                         return -EBUSY;
00356                 }
00357 
00358                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
00359                 if (tg3_wait_macro_done(tp)) {
00360                         *resetp = 1;
00361                         return -EBUSY;
00362                 }
00363 
00364                 for (i = 0; i < 6; i += 2) {
00365                         u32 low, high;
00366 
00367                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
00368                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
00369                             tg3_wait_macro_done(tp)) {
00370                                 *resetp = 1;
00371                                 return -EBUSY;
00372                         }
00373                         low &= 0x7fff;
00374                         high &= 0x000f;
00375                         if (low != test_pat[chan][i] ||
00376                             high != test_pat[chan][i+1]) {
00377                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
00378                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
00379                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
00380 
00381                                 return -EBUSY;
00382                         }
00383                 }
00384         }
00385 
00386         return 0;
00387 }
00388 
00389 static int tg3_phy_reset_chanpat(struct tg3 *tp)
00390 {       DBGP("%s\n", __func__);
00391 
00392         int chan;
00393 
00394         for (chan = 0; chan < 4; chan++) {
00395                 int i;
00396 
00397                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
00398                              (chan * 0x2000) | 0x0200);
00399                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
00400                 for (i = 0; i < 6; i++)
00401                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
00402                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
00403                 if (tg3_wait_macro_done(tp))
00404                         return -EBUSY;
00405         }
00406 
00407         return 0;
00408 }
00409 
00410 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
00411 {       DBGP("%s\n", __func__);
00412 
00413         int err;
00414 
00415         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
00416         if (!err)
00417                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
00418 
00419         return err;
00420 }
00421 
00422 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
00423 {       DBGP("%s\n", __func__);
00424 
00425         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
00426                 set |= MII_TG3_AUXCTL_MISC_WREN;
00427 
00428         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
00429 }
00430 
00431 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
00432         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
00433                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
00434                              MII_TG3_AUXCTL_ACTL_TX_6DB)
00435 
00436 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
00437         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
00438                              MII_TG3_AUXCTL_ACTL_TX_6DB);
00439 
00440 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
00441 {       DBGP("%s\n", __func__);
00442 
00443         u32 reg32, phy9_orig;
00444         int retries, do_phy_reset, err;
00445 
00446         retries = 10;
00447         do_phy_reset = 1;
00448         do {
00449                 if (do_phy_reset) {
00450                         err = tg3_bmcr_reset(tp);
00451                         if (err)
00452                                 return err;
00453                         do_phy_reset = 0;
00454                 }
00455 
00456                 /* Disable transmitter and interrupt.  */
00457                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
00458                         continue;
00459 
00460                 reg32 |= 0x3000;
00461                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
00462 
00463                 /* Set full-duplex, 1000 mbps.  */
00464                 tg3_writephy(tp, MII_BMCR,
00465                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
00466 
00467                 /* Set to master mode.  */
00468                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
00469                         continue;
00470 
00471                 tg3_writephy(tp, MII_TG3_CTRL,
00472                              (MII_TG3_CTRL_AS_MASTER |
00473                               MII_TG3_CTRL_ENABLE_AS_MASTER));
00474 
00475                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
00476                 if (err)
00477                         return err;
00478 
00479                 /* Block the PHY control access.  */
00480                 tg3_phydsp_write(tp, 0x8005, 0x0800);
00481 
00482                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
00483                 if (!err)
00484                         break;
00485         } while (--retries);
00486 
00487         err = tg3_phy_reset_chanpat(tp);
00488         if (err)
00489                 return err;
00490 
00491         tg3_phydsp_write(tp, 0x8005, 0x0000);
00492 
00493         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
00494         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
00495 
00496         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
00497 
00498         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
00499 
00500         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
00501                 reg32 &= ~0x3000;
00502                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
00503         } else if (!err)
00504                 err = -EBUSY;
00505 
00506         return err;
00507 }
00508 
00509 static void tg3_phy_apply_otp(struct tg3 *tp)
00510 {       DBGP("%s\n", __func__);
00511 
00512         u32 otp, phy;
00513 
00514         if (!tp->phy_otp)
00515                 return;
00516 
00517         otp = tp->phy_otp;
00518 
00519         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
00520                 return;
00521 
00522         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
00523         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
00524         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
00525 
00526         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
00527               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
00528         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
00529 
00530         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
00531         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
00532         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
00533 
00534         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
00535         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
00536 
00537         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
00538         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
00539 
00540         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
00541               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
00542         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
00543 
00544         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
00545 }
00546 
00547 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
00548 {       DBGP("%s\n", __func__);
00549 
00550         int err;
00551 
00552         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
00553                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
00554                            MII_TG3_AUXCTL_SHDWSEL_MISC);
00555         if (!err)
00556                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
00557 
00558         return err;
00559 }
00560 
00561 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
00562 {       DBGP("%s\n", __func__);
00563 
00564         u32 phy;
00565 
00566         if (!tg3_flag(tp, 5705_PLUS) ||
00567             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
00568                 return;
00569 
00570         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
00571                 u32 ephy;
00572 
00573                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
00574                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
00575 
00576                         tg3_writephy(tp, MII_TG3_FET_TEST,
00577                                      ephy | MII_TG3_FET_SHADOW_EN);
00578                         if (!tg3_readphy(tp, reg, &phy)) {
00579                                 if (enable)
00580                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
00581                                 else
00582                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
00583                                 tg3_writephy(tp, reg, phy);
00584                         }
00585                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
00586                 }
00587         } else {
00588                 int ret;
00589 
00590                 ret = tg3_phy_auxctl_read(tp,
00591                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
00592                 if (!ret) {
00593                         if (enable)
00594                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
00595                         else
00596                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
00597                         tg3_phy_auxctl_write(tp,
00598                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
00599                 }
00600         }
00601 }
00602 
00603 static void tg3_phy_set_wirespeed(struct tg3 *tp)
00604 {       DBGP("%s\n", __func__);
00605 
00606         int ret;
00607         u32 val;
00608 
00609         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
00610                 return;
00611 
00612         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
00613         if (!ret)
00614                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
00615                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
00616 }
00617 
00618 /* This will reset the tigon3 PHY if there is no valid
00619  * link unless the FORCE argument is non-zero.
00620  */
00621 int tg3_phy_reset(struct tg3 *tp)
00622 {       DBGP("%s\n", __func__);
00623 
00624         u32 val, cpmuctrl;
00625         int err;
00626 
00627         DBGCP(&tp->pdev->dev, "%s\n", __func__);
00628 
00629         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
00630                 val = tr32(GRC_MISC_CFG);
00631                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
00632                 udelay(40);
00633         }
00634         err  = tg3_readphy(tp, MII_BMSR, &val);
00635         err |= tg3_readphy(tp, MII_BMSR, &val);
00636         if (err != 0)
00637                 return -EBUSY;
00638 
00639         netdev_link_down(tp->dev);
00640         tg3_link_report(tp);
00641 
00642         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
00643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
00644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
00645                 err = tg3_phy_reset_5703_4_5(tp);
00646                 if (err)
00647                         return err;
00648                 goto out;
00649         }
00650 
00651         cpmuctrl = 0;
00652         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
00653             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
00654                 cpmuctrl = tr32(TG3_CPMU_CTRL);
00655                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
00656                         tw32(TG3_CPMU_CTRL,
00657                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
00658         }
00659 
00660         err = tg3_bmcr_reset(tp);
00661         if (err)
00662                 return err;
00663 
00664         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
00665                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
00666                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
00667 
00668                 tw32(TG3_CPMU_CTRL, cpmuctrl);
00669         }
00670 
00671         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
00672             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
00673                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
00674                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
00675                     CPMU_LSPD_1000MB_MACCLK_12_5) {
00676                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
00677                         udelay(40);
00678                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
00679                 }
00680         }
00681 
00682         if (tg3_flag(tp, 5717_PLUS) &&
00683             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
00684                 return 0;
00685 
00686         tg3_phy_apply_otp(tp);
00687 
00688 out:
00689         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
00690             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
00691                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
00692                 tg3_phydsp_write(tp, 0x000a, 0x0323);
00693                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
00694         }
00695 
00696         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
00697                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
00698                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
00699         }
00700 
00701         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
00702                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
00703                         tg3_phydsp_write(tp, 0x000a, 0x310b);
00704                         tg3_phydsp_write(tp, 0x201f, 0x9506);
00705                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
00706                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
00707                 }
00708         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
00709                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
00710                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
00711                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
00712                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
00713                                 tg3_writephy(tp, MII_TG3_TEST1,
00714                                              MII_TG3_TEST1_TRIM_EN | 0x4);
00715                         } else
00716                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
00717 
00718                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
00719                 }
00720         }
00721 
00722         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
00723                 /* Cannot do read-modify-write on 5401 */
00724                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
00725         }
00726 
00727         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
00728                 /* adjust output voltage */
00729                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
00730         }
00731 
00732         tg3_phy_toggle_automdix(tp, 1);
00733         tg3_phy_set_wirespeed(tp);
00734         return 0;
00735 }
00736 
00737 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
00738 {       DBGP("%s\n", __func__);
00739 
00740         u32 adv_reg, all_mask = 0;
00741 
00742         if (mask & ADVERTISED_10baseT_Half)
00743                 all_mask |= ADVERTISE_10HALF;
00744         if (mask & ADVERTISED_10baseT_Full)
00745                 all_mask |= ADVERTISE_10FULL;
00746         if (mask & ADVERTISED_100baseT_Half)
00747                 all_mask |= ADVERTISE_100HALF;
00748         if (mask & ADVERTISED_100baseT_Full)
00749                 all_mask |= ADVERTISE_100FULL;
00750 
00751         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
00752                 return 0;
00753 
00754         if ((adv_reg & all_mask) != all_mask)
00755                 return 0;
00756         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
00757                 u32 tg3_ctrl;
00758 
00759                 all_mask = 0;
00760                 if (mask & ADVERTISED_1000baseT_Half)
00761                         all_mask |= ADVERTISE_1000HALF;
00762                 if (mask & ADVERTISED_1000baseT_Full)
00763                         all_mask |= ADVERTISE_1000FULL;
00764 
00765                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
00766                         return 0;
00767 
00768                 if ((tg3_ctrl & all_mask) != all_mask)
00769                         return 0;
00770         }
00771         return 1;
00772 }
00773 
00774 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
00775 {       DBGP("%s\n", __func__);
00776 
00777         u16 miireg;
00778 
00779         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
00780                 miireg = ADVERTISE_PAUSE_CAP;
00781         else if (flow_ctrl & FLOW_CTRL_TX)
00782                 miireg = ADVERTISE_PAUSE_ASYM;
00783         else if (flow_ctrl & FLOW_CTRL_RX)
00784                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
00785         else
00786                 miireg = 0;
00787 
00788         return miireg;
00789 }
00790 
00791 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
00792 {       DBGP("%s\n", __func__);
00793 
00794         int err = 0;
00795         u32 val __unused, new_adv;
00796 
00797         new_adv = ADVERTISE_CSMA;
00798         if (advertise & ADVERTISED_10baseT_Half)
00799                 new_adv |= ADVERTISE_10HALF;
00800         if (advertise & ADVERTISED_10baseT_Full)
00801                 new_adv |= ADVERTISE_10FULL;
00802         if (advertise & ADVERTISED_100baseT_Half)
00803                 new_adv |= ADVERTISE_100HALF;
00804         if (advertise & ADVERTISED_100baseT_Full)
00805                 new_adv |= ADVERTISE_100FULL;
00806 
00807         new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
00808 
00809         err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
00810         if (err)
00811                 goto done;
00812 
00813         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
00814                 goto done;
00815 
00816         new_adv = 0;
00817         if (advertise & ADVERTISED_1000baseT_Half)
00818                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
00819         if (advertise & ADVERTISED_1000baseT_Full)
00820                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
00821 
00822         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
00823             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
00824                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
00825                             MII_TG3_CTRL_ENABLE_AS_MASTER);
00826 
00827         err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
00828         if (err)
00829                 goto done;
00830 
00831         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
00832                 goto done;
00833 
00834 done:
00835         return err;
00836 }
00837 
00838 static int tg3_init_5401phy_dsp(struct tg3 *tp)
00839 {       DBGP("%s\n", __func__);
00840 
00841         int err;
00842 
00843         /* Turn off tap power management. */
00844         /* Set Extended packet length bit */
00845         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
00846 
00847         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
00848         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
00849         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
00850         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
00851         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
00852 
00853         udelay(40);
00854 
00855         return err;
00856 }
00857 
00858 #define ADVERTISED_Autoneg              (1 << 6)
00859 #define ADVERTISED_Pause                (1 << 13)
00860 #define ADVERTISED_TP                   (1 << 7)
00861 #define ADVERTISED_FIBRE                (1 << 10)
00862 
00863 #define AUTONEG_ENABLE          0x01
00864 
00865 static void tg3_phy_init_link_config(struct tg3 *tp)
00866 {       DBGP("%s\n", __func__);
00867 
00868         u32 adv = ADVERTISED_Autoneg |
00869                   ADVERTISED_Pause;
00870 
00871 
00872         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
00873                 adv |= ADVERTISED_1000baseT_Half |
00874                        ADVERTISED_1000baseT_Full;
00875         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
00876                 adv |= ADVERTISED_100baseT_Half |
00877                        ADVERTISED_100baseT_Full |
00878                        ADVERTISED_10baseT_Half |
00879                        ADVERTISED_10baseT_Full |
00880                        ADVERTISED_TP;
00881         else
00882                 adv |= ADVERTISED_FIBRE;
00883 
00884         tp->link_config.advertising = adv;
00885         tp->link_config.speed = SPEED_INVALID;
00886         tp->link_config.duplex = DUPLEX_INVALID;
00887         tp->link_config.autoneg = AUTONEG_ENABLE;
00888         tp->link_config.active_speed = SPEED_INVALID;
00889         tp->link_config.active_duplex = DUPLEX_INVALID;
00890         tp->link_config.orig_speed = SPEED_INVALID;
00891         tp->link_config.orig_duplex = DUPLEX_INVALID;
00892         tp->link_config.orig_autoneg = AUTONEG_INVALID;
00893 }
00894 
00895 int tg3_phy_probe(struct tg3 *tp)
00896 {       DBGP("%s\n", __func__);
00897 
00898         u32 hw_phy_id_1, hw_phy_id_2;
00899         u32 hw_phy_id, hw_phy_id_masked;
00900         int err;
00901 
00902         /* flow control autonegotiation is default behavior */
00903         tg3_flag_set(tp, PAUSE_AUTONEG);
00904         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
00905 
00906         /* Reading the PHY ID register can conflict with ASF
00907          * firmware access to the PHY hardware.
00908          */
00909         err = 0;
00910         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
00911                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
00912         } else {
00913                 /* Now read the physical PHY_ID from the chip and verify
00914                  * that it is sane.  If it doesn't look good, we fall back
00915                  * to either the hard-coded table based PHY_ID and failing
00916                  * that the value found in the eeprom area.
00917                  */
00918                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
00919                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
00920 
00921                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
00922                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
00923                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
00924 
00925                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
00926         }
00927 
00928         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
00929                 tp->phy_id = hw_phy_id;
00930                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
00931                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
00932                 else
00933                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
00934         } else {
00935                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
00936                         /* Do nothing, phy ID already set up in
00937                          * tg3_get_eeprom_hw_cfg().
00938                          */
00939                 } else {
00940                         struct subsys_tbl_ent *p;
00941 
00942                         /* No eeprom signature?  Try the hardcoded
00943                          * subsys device table.
00944                          */
00945                         p = tg3_lookup_by_subsys(tp);
00946                         if (!p) {
00947                                 DBGC(&tp->pdev->dev, "lookup by subsys failed\n");
00948                                 return -ENODEV;
00949                         }
00950 
00951                         tp->phy_id = p->phy_id;
00952                         if (!tp->phy_id ||
00953                             tp->phy_id == TG3_PHY_ID_BCM8002)
00954                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
00955                 }
00956         }
00957 
00958         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
00959             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
00960               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
00961              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
00962               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
00963                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
00964 
00965         tg3_phy_init_link_config(tp);
00966 
00967         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
00968             !tg3_flag(tp, ENABLE_APE) &&
00969             !tg3_flag(tp, ENABLE_ASF)) {
00970                 u32 bmsr;
00971                 u32 mask;
00972 
00973                 tg3_readphy(tp, MII_BMSR, &bmsr);
00974                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
00975                     (bmsr & BMSR_LSTATUS))
00976                         goto skip_phy_reset;
00977 
00978                 err = tg3_phy_reset(tp);
00979                 if (err)
00980                         return err;
00981 
00982                 tg3_phy_set_wirespeed(tp);
00983 
00984                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
00985                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
00986                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
00987                 if (!tg3_copper_is_advertising_all(tp, mask)) {
00988                         tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
00989                                             tp->link_config.flowctrl);
00990 
00991                         tg3_writephy(tp, MII_BMCR,
00992                                      BMCR_ANENABLE | BMCR_ANRESTART);
00993                 }
00994         }
00995 
00996 skip_phy_reset:
00997         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
00998                 err = tg3_init_5401phy_dsp(tp);
00999                 if (err)
01000                         return err;
01001 
01002                 err = tg3_init_5401phy_dsp(tp);
01003         }
01004 
01005         return err;
01006 }
01007 
01008 void tg3_poll_link(struct tg3 *tp)
01009 {       DBGP("%s\n", __func__);
01010 
01011         if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
01012                 DBGC(tp->dev,"link_changed\n");
01013                 tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
01014                 tg3_setup_phy(tp, 0);
01015         }
01016 }
01017 
01018 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
01019 {       DBGP("%s\n", __func__);
01020 
01021         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
01022         case MII_TG3_AUX_STAT_10HALF:
01023                 *speed = SPEED_10;
01024                 *duplex = DUPLEX_HALF;
01025                 break;
01026 
01027         case MII_TG3_AUX_STAT_10FULL:
01028                 *speed = SPEED_10;
01029                 *duplex = DUPLEX_FULL;
01030                 break;
01031 
01032         case MII_TG3_AUX_STAT_100HALF:
01033                 *speed = SPEED_100;
01034                 *duplex = DUPLEX_HALF;
01035                 break;
01036 
01037         case MII_TG3_AUX_STAT_100FULL:
01038                 *speed = SPEED_100;
01039                 *duplex = DUPLEX_FULL;
01040                 break;
01041 
01042         case MII_TG3_AUX_STAT_1000HALF:
01043                 *speed = SPEED_1000;
01044                 *duplex = DUPLEX_HALF;
01045                 break;
01046 
01047         case MII_TG3_AUX_STAT_1000FULL:
01048                 *speed = SPEED_1000;
01049                 *duplex = DUPLEX_FULL;
01050                 break;
01051 
01052         default:
01053                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
01054                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
01055                                  SPEED_10;
01056                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
01057                                   DUPLEX_HALF;
01058                         break;
01059                 }
01060                 *speed = SPEED_INVALID;
01061                 *duplex = DUPLEX_INVALID;
01062                 break;
01063         }
01064 }
01065 
01066 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
01067 {       DBGP("%s\n", __func__);
01068 
01069         u32 curadv, reqadv;
01070 
01071         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
01072                 return 1;
01073 
01074         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
01075         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
01076 
01077         if (tp->link_config.active_duplex == DUPLEX_FULL) {
01078                 if (curadv != reqadv)
01079                         return 0;
01080 
01081                 if (tg3_flag(tp, PAUSE_AUTONEG))
01082                         tg3_readphy(tp, MII_LPA, rmtadv);
01083         } else {
01084                 /* Reprogram the advertisement register, even if it
01085                  * does not affect the current link.  If the link
01086                  * gets renegotiated in the future, we can save an
01087                  * additional renegotiation cycle by advertising
01088                  * it correctly in the first place.
01089                  */
01090                 if (curadv != reqadv) {
01091                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
01092                                      ADVERTISE_PAUSE_ASYM);
01093                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
01094                 }
01095         }
01096 
01097         return 1;
01098 }
01099 
01100 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
01101 {       DBGP("%s\n", __func__);
01102 
01103         u8 cap = 0;
01104 
01105         if (lcladv & ADVERTISE_1000XPAUSE) {
01106                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
01107                         if (rmtadv & LPA_1000XPAUSE)
01108                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
01109                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
01110                                 cap = FLOW_CTRL_RX;
01111                 } else {
01112                         if (rmtadv & LPA_1000XPAUSE)
01113                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
01114                 }
01115         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
01116                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
01117                         cap = FLOW_CTRL_TX;
01118         }
01119 
01120         return cap;
01121 }
01122 
01123 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
01124 {       DBGP("%s\n", __func__);
01125 
01126         u8 flowctrl = 0;
01127         u32 old_rx_mode = tp->rx_mode;
01128         u32 old_tx_mode = tp->tx_mode;
01129 
01130         if (tg3_flag(tp, PAUSE_AUTONEG)) {
01131                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
01132                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
01133                 else
01134                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
01135         } else
01136                 flowctrl = tp->link_config.flowctrl;
01137 
01138         tp->link_config.active_flowctrl = flowctrl;
01139 
01140         if (flowctrl & FLOW_CTRL_RX)
01141                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
01142         else
01143                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
01144 
01145         if (old_rx_mode != tp->rx_mode)
01146                 tw32_f(MAC_RX_MODE, tp->rx_mode);
01147 
01148         if (flowctrl & FLOW_CTRL_TX)
01149                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
01150         else
01151                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
01152 
01153         if (old_tx_mode != tp->tx_mode)
01154                 tw32_f(MAC_TX_MODE, tp->tx_mode);
01155 }
01156 
01157 static void tg3_phy_copper_begin(struct tg3 *tp)
01158 {       DBGP("%s\n", __func__);
01159 
01160         u32 new_adv;
01161 
01162         if (tp->link_config.speed == SPEED_INVALID) {
01163                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
01164                         tp->link_config.advertising &=
01165                                 ~(ADVERTISED_1000baseT_Half |
01166                                   ADVERTISED_1000baseT_Full);
01167 
01168                 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
01169                                     tp->link_config.flowctrl);
01170         } else {
01171                 /* Asking for a specific link mode. */
01172                 if (tp->link_config.speed == SPEED_1000) {
01173                         if (tp->link_config.duplex == DUPLEX_FULL)
01174                                 new_adv = ADVERTISED_1000baseT_Full;
01175                         else
01176                                 new_adv = ADVERTISED_1000baseT_Half;
01177                 } else if (tp->link_config.speed == SPEED_100) {
01178                         if (tp->link_config.duplex == DUPLEX_FULL)
01179                                 new_adv = ADVERTISED_100baseT_Full;
01180                         else
01181                                 new_adv = ADVERTISED_100baseT_Half;
01182                 } else {
01183                         if (tp->link_config.duplex == DUPLEX_FULL)
01184                                 new_adv = ADVERTISED_10baseT_Full;
01185                         else
01186                                 new_adv = ADVERTISED_10baseT_Half;
01187                 }
01188 
01189                 tg3_phy_autoneg_cfg(tp, new_adv,
01190                                     tp->link_config.flowctrl);
01191         }
01192 
01193         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
01194 }
01195 
01196 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
01197 {       DBGP("%s\n", __func__);
01198 
01199         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
01200                 return 1;
01201         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
01202                 if (speed != SPEED_10)
01203                         return 1;
01204         } else if (speed == SPEED_10)
01205                 return 1;
01206 
01207         return 0;
01208 }
01209 
01210 #if 1
01211 
01212 static void tg3_ump_link_report(struct tg3 *tp)
01213 {       DBGP("%s\n", __func__);
01214 
01215         u32 reg;
01216         u32 val;
01217 
01218         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
01219                 return;
01220 
01221         tg3_wait_for_event_ack(tp);
01222 
01223         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
01224 
01225         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
01226 
01227         val = 0;
01228         if (!tg3_readphy(tp, MII_BMCR, &reg))
01229                 val = reg << 16;
01230         if (!tg3_readphy(tp, MII_BMSR, &reg))
01231                 val |= (reg & 0xffff);
01232         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
01233 
01234         val = 0;
01235         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
01236                 val = reg << 16;
01237         if (!tg3_readphy(tp, MII_LPA, &reg))
01238                 val |= (reg & 0xffff);
01239         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
01240 
01241         val = 0;
01242         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
01243                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
01244                         val = reg << 16;
01245                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
01246                         val |= (reg & 0xffff);
01247         }
01248         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
01249 
01250         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
01251                 val = reg << 16;
01252         else
01253                 val = 0;
01254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
01255 
01256         tg3_generate_fw_event(tp);
01257 }
01258 
01259 /* NOTE: Debugging only code */
01260 static void tg3_link_report(struct tg3 *tp)
01261 {       DBGP("%s\n", __func__);
01262 
01263         if (!netdev_link_ok(tp->dev)) {
01264                 DBGC(tp->dev, "Link is down\n");
01265                 tg3_ump_link_report(tp);
01266         } else {
01267                 DBGC(tp->dev, "Link is up at %d Mbps, %s duplex\n",
01268                             (tp->link_config.active_speed == SPEED_1000 ?
01269                              1000 :
01270                              (tp->link_config.active_speed == SPEED_100 ?
01271                               100 : 10)),
01272                             (tp->link_config.active_duplex == DUPLEX_FULL ?
01273                              "full" : "half"));
01274 
01275                 DBGC(tp->dev, "Flow control is %s for TX and %s for RX\n",
01276                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
01277                             "on" : "off",
01278                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
01279                             "on" : "off");
01280 
01281                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
01282                         DBGC(tp->dev, "EEE is %s\n",
01283                                     tp->setlpicnt ? "enabled" : "disabled");
01284 
01285                 tg3_ump_link_report(tp);
01286         }
01287 }
01288 #endif
01289 
01290 struct tg3_fiber_aneginfo {
01291         int state;
01292 #define ANEG_STATE_UNKNOWN              0
01293 #define ANEG_STATE_AN_ENABLE            1
01294 #define ANEG_STATE_RESTART_INIT         2
01295 #define ANEG_STATE_RESTART              3
01296 #define ANEG_STATE_DISABLE_LINK_OK      4
01297 #define ANEG_STATE_ABILITY_DETECT_INIT  5
01298 #define ANEG_STATE_ABILITY_DETECT       6
01299 #define ANEG_STATE_ACK_DETECT_INIT      7
01300 #define ANEG_STATE_ACK_DETECT           8
01301 #define ANEG_STATE_COMPLETE_ACK_INIT    9
01302 #define ANEG_STATE_COMPLETE_ACK         10
01303 #define ANEG_STATE_IDLE_DETECT_INIT     11
01304 #define ANEG_STATE_IDLE_DETECT          12
01305 #define ANEG_STATE_LINK_OK              13
01306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
01307 #define ANEG_STATE_NEXT_PAGE_WAIT       15
01308 
01309         u32 flags;
01310 #define MR_AN_ENABLE            0x00000001
01311 #define MR_RESTART_AN           0x00000002
01312 #define MR_AN_COMPLETE          0x00000004
01313 #define MR_PAGE_RX              0x00000008
01314 #define MR_NP_LOADED            0x00000010
01315 #define MR_TOGGLE_TX            0x00000020
01316 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
01317 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
01318 #define MR_LP_ADV_SYM_PAUSE     0x00000100
01319 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
01320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
01321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
01322 #define MR_LP_ADV_NEXT_PAGE     0x00001000
01323 #define MR_TOGGLE_RX            0x00002000
01324 #define MR_NP_RX                0x00004000
01325 
01326 #define MR_LINK_OK              0x80000000
01327 
01328         unsigned long link_time, cur_time;
01329 
01330         u32 ability_match_cfg;
01331         int ability_match_count;
01332 
01333         char ability_match, idle_match, ack_match;
01334 
01335         u32 txconfig, rxconfig;
01336 #define ANEG_CFG_NP             0x00000080
01337 #define ANEG_CFG_ACK            0x00000040
01338 #define ANEG_CFG_RF2            0x00000020
01339 #define ANEG_CFG_RF1            0x00000010
01340 #define ANEG_CFG_PS2            0x00000001
01341 #define ANEG_CFG_PS1            0x00008000
01342 #define ANEG_CFG_HD             0x00004000
01343 #define ANEG_CFG_FD             0x00002000
01344 #define ANEG_CFG_INVAL          0x00001f06
01345 
01346 };
01347 #define ANEG_OK         0
01348 #define ANEG_DONE       1
01349 #define ANEG_TIMER_ENAB 2
01350 #define ANEG_FAILED     -1
01351 
01352 #define ANEG_STATE_SETTLE_TIME  10000
01353 
01354 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
01355 {
01356         u16 miireg;
01357 
01358         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
01359                 miireg = ADVERTISE_1000XPAUSE;
01360         else if (flow_ctrl & FLOW_CTRL_TX)
01361                 miireg = ADVERTISE_1000XPSE_ASYM;
01362         else if (flow_ctrl & FLOW_CTRL_RX)
01363                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
01364         else
01365                 miireg = 0;
01366 
01367         return miireg;
01368 }
01369 
01370 static void tg3_init_bcm8002(struct tg3 *tp)
01371 {
01372         u32 mac_status = tr32(MAC_STATUS);
01373         int i;
01374 
01375         /* Reset when initting first time or we have a link. */
01376         if (tg3_flag(tp, INIT_COMPLETE) &&
01377             !(mac_status & MAC_STATUS_PCS_SYNCED))
01378                 return;
01379 
01380         /* Set PLL lock range. */
01381         tg3_writephy(tp, 0x16, 0x8007);
01382 
01383         /* SW reset */
01384         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
01385 
01386         /* Wait for reset to complete. */
01387         /* XXX schedule_timeout() ... */
01388         for (i = 0; i < 500; i++)
01389                 udelay(10);
01390 
01391         /* Config mode; select PMA/Ch 1 regs. */
01392         tg3_writephy(tp, 0x10, 0x8411);
01393 
01394         /* Enable auto-lock and comdet, select txclk for tx. */
01395         tg3_writephy(tp, 0x11, 0x0a10);
01396 
01397         tg3_writephy(tp, 0x18, 0x00a0);
01398         tg3_writephy(tp, 0x16, 0x41ff);
01399 
01400         /* Assert and deassert POR. */
01401         tg3_writephy(tp, 0x13, 0x0400);
01402         udelay(40);
01403         tg3_writephy(tp, 0x13, 0x0000);
01404 
01405         tg3_writephy(tp, 0x11, 0x0a50);
01406         udelay(40);
01407         tg3_writephy(tp, 0x11, 0x0a10);
01408 
01409         /* Wait for signal to stabilize */
01410         /* XXX schedule_timeout() ... */
01411         for (i = 0; i < 15000; i++)
01412                 udelay(10);
01413 
01414         /* Deselect the channel register so we can read the PHYID
01415          * later.
01416          */
01417         tg3_writephy(tp, 0x10, 0x8011);
01418 }
01419 
01420 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
01421 {
01422         u16 flowctrl;
01423         int current_link_up;
01424         u32 sg_dig_ctrl, sg_dig_status;
01425         u32 serdes_cfg, expected_sg_dig_ctrl;
01426         int workaround, port_a;
01427 
01428         serdes_cfg = 0;
01429         expected_sg_dig_ctrl = 0;
01430         workaround = 0;
01431         port_a = 1;
01432         current_link_up = 0;
01433 
01434         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
01435             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
01436                 workaround = 1;
01437                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
01438                         port_a = 0;
01439 
01440                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
01441                 /* preserve bits 20-23 for voltage regulator */
01442                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
01443         }
01444 
01445         sg_dig_ctrl = tr32(SG_DIG_CTRL);
01446 
01447         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
01448                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
01449                         if (workaround) {
01450                                 u32 val = serdes_cfg;
01451 
01452                                 if (port_a)
01453                                         val |= 0xc010000;
01454                                 else
01455                                         val |= 0x4010000;
01456                                 tw32_f(MAC_SERDES_CFG, val);
01457                         }
01458 
01459                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
01460                 }
01461                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
01462                         tg3_setup_flow_control(tp, 0, 0);
01463                         current_link_up = 1;
01464                 }
01465                 goto out;
01466         }
01467 
01468         /* Want auto-negotiation.  */
01469         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
01470 
01471         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
01472         if (flowctrl & ADVERTISE_1000XPAUSE)
01473                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
01474         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
01475                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
01476 
01477         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
01478                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
01479                     tp->serdes_counter &&
01480                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
01481                                     MAC_STATUS_RCVD_CFG)) ==
01482                      MAC_STATUS_PCS_SYNCED)) {
01483                         tp->serdes_counter--;
01484                         current_link_up = 1;
01485                         goto out;
01486                 }
01487 restart_autoneg:
01488                 if (workaround)
01489                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
01490                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
01491                 udelay(5);
01492                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
01493 
01494                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
01495                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
01496         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
01497                                  MAC_STATUS_SIGNAL_DET)) {
01498                 sg_dig_status = tr32(SG_DIG_STATUS);
01499                 mac_status = tr32(MAC_STATUS);
01500 
01501                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
01502                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
01503                         u32 local_adv = 0, remote_adv = 0;
01504 
01505                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
01506                                 local_adv |= ADVERTISE_1000XPAUSE;
01507                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
01508                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
01509 
01510                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
01511                                 remote_adv |= LPA_1000XPAUSE;
01512                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
01513                                 remote_adv |= LPA_1000XPAUSE_ASYM;
01514 
01515                         tp->link_config.rmt_adv =
01516                                            mii_adv_to_ethtool_adv_x(remote_adv);
01517 
01518                         tg3_setup_flow_control(tp, local_adv, remote_adv);
01519                         current_link_up = 1;
01520                         tp->serdes_counter = 0;
01521                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
01522                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
01523                         if (tp->serdes_counter)
01524                                 tp->serdes_counter--;
01525                         else {
01526                                 if (workaround) {
01527                                         u32 val = serdes_cfg;
01528 
01529                                         if (port_a)
01530                                                 val |= 0xc010000;
01531                                         else
01532                                                 val |= 0x4010000;
01533 
01534                                         tw32_f(MAC_SERDES_CFG, val);
01535                                 }
01536 
01537                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
01538                                 udelay(40);
01539 
01540                                 /* Link parallel detection - link is up */
01541                                 /* only if we have PCS_SYNC and not */
01542                                 /* receiving config code words */
01543                                 mac_status = tr32(MAC_STATUS);
01544                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
01545                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
01546                                         tg3_setup_flow_control(tp, 0, 0);
01547                                         current_link_up = 1;
01548                                         tp->phy_flags |=
01549                                                 TG3_PHYFLG_PARALLEL_DETECT;
01550                                         tp->serdes_counter =
01551                                                 SERDES_PARALLEL_DET_TIMEOUT;
01552                                 } else
01553                                         goto restart_autoneg;
01554                         }
01555                 }
01556         } else {
01557                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
01558                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
01559         }
01560 
01561 out:
01562         return current_link_up;
01563 }
01564 
01565 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
01566                                    struct tg3_fiber_aneginfo *ap)
01567 {
01568         u16 flowctrl;
01569         unsigned long delta;
01570         u32 rx_cfg_reg;
01571         int ret;
01572 
01573         if (ap->state == ANEG_STATE_UNKNOWN) {
01574                 ap->rxconfig = 0;
01575                 ap->link_time = 0;
01576                 ap->cur_time = 0;
01577                 ap->ability_match_cfg = 0;
01578                 ap->ability_match_count = 0;
01579                 ap->ability_match = 0;
01580                 ap->idle_match = 0;
01581                 ap->ack_match = 0;
01582         }
01583         ap->cur_time++;
01584 
01585         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
01586                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
01587 
01588                 if (rx_cfg_reg != ap->ability_match_cfg) {
01589                         ap->ability_match_cfg = rx_cfg_reg;
01590                         ap->ability_match = 0;
01591                         ap->ability_match_count = 0;
01592                 } else {
01593                         if (++ap->ability_match_count > 1) {
01594                                 ap->ability_match = 1;
01595                                 ap->ability_match_cfg = rx_cfg_reg;
01596                         }
01597                 }
01598                 if (rx_cfg_reg & ANEG_CFG_ACK)
01599                         ap->ack_match = 1;
01600                 else
01601                         ap->ack_match = 0;
01602 
01603                 ap->idle_match = 0;
01604         } else {
01605                 ap->idle_match = 1;
01606                 ap->ability_match_cfg = 0;
01607                 ap->ability_match_count = 0;
01608                 ap->ability_match = 0;
01609                 ap->ack_match = 0;
01610 
01611                 rx_cfg_reg = 0;
01612         }
01613 
01614         ap->rxconfig = rx_cfg_reg;
01615         ret = ANEG_OK;
01616 
01617         switch (ap->state) {
01618         case ANEG_STATE_UNKNOWN:
01619                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
01620                         ap->state = ANEG_STATE_AN_ENABLE;
01621 
01622                 /* fallthru */
01623         case ANEG_STATE_AN_ENABLE:
01624                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
01625                 if (ap->flags & MR_AN_ENABLE) {
01626                         ap->link_time = 0;
01627                         ap->cur_time = 0;
01628                         ap->ability_match_cfg = 0;
01629                         ap->ability_match_count = 0;
01630                         ap->ability_match = 0;
01631                         ap->idle_match = 0;
01632                         ap->ack_match = 0;
01633 
01634                         ap->state = ANEG_STATE_RESTART_INIT;
01635                 } else {
01636                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
01637                 }
01638                 break;
01639 
01640         case ANEG_STATE_RESTART_INIT:
01641                 ap->link_time = ap->cur_time;
01642                 ap->flags &= ~(MR_NP_LOADED);
01643                 ap->txconfig = 0;
01644                 tw32(MAC_TX_AUTO_NEG, 0);
01645                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
01646                 tw32_f(MAC_MODE, tp->mac_mode);
01647                 udelay(40);
01648 
01649                 ret = ANEG_TIMER_ENAB;
01650                 ap->state = ANEG_STATE_RESTART;
01651 
01652                 /* fallthru */
01653         case ANEG_STATE_RESTART:
01654                 delta = ap->cur_time - ap->link_time;
01655                 if (delta > ANEG_STATE_SETTLE_TIME)
01656                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
01657                 else
01658                         ret = ANEG_TIMER_ENAB;
01659                 break;
01660 
01661         case ANEG_STATE_DISABLE_LINK_OK:
01662                 ret = ANEG_DONE;
01663                 break;
01664 
01665         case ANEG_STATE_ABILITY_DETECT_INIT:
01666                 ap->flags &= ~(MR_TOGGLE_TX);
01667                 ap->txconfig = ANEG_CFG_FD;
01668                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
01669                 if (flowctrl & ADVERTISE_1000XPAUSE)
01670                         ap->txconfig |= ANEG_CFG_PS1;
01671                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
01672                         ap->txconfig |= ANEG_CFG_PS2;
01673                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
01674                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
01675                 tw32_f(MAC_MODE, tp->mac_mode);
01676                 udelay(40);
01677 
01678                 ap->state = ANEG_STATE_ABILITY_DETECT;
01679                 break;
01680 
01681         case ANEG_STATE_ABILITY_DETECT:
01682                 if (ap->ability_match != 0 && ap->rxconfig != 0)
01683                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
01684                 break;
01685 
01686         case ANEG_STATE_ACK_DETECT_INIT:
01687                 ap->txconfig |= ANEG_CFG_ACK;
01688                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
01689                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
01690                 tw32_f(MAC_MODE, tp->mac_mode);
01691                 udelay(40);
01692 
01693                 ap->state = ANEG_STATE_ACK_DETECT;
01694 
01695                 /* fallthru */
01696         case ANEG_STATE_ACK_DETECT:
01697                 if (ap->ack_match != 0) {
01698                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
01699                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
01700                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
01701                         } else {
01702                                 ap->state = ANEG_STATE_AN_ENABLE;
01703                         }
01704                 } else if (ap->ability_match != 0 &&
01705                            ap->rxconfig == 0) {
01706                         ap->state = ANEG_STATE_AN_ENABLE;
01707                 }
01708                 break;
01709 
01710         case ANEG_STATE_COMPLETE_ACK_INIT:
01711                 if (ap->rxconfig & ANEG_CFG_INVAL) {
01712                         ret = ANEG_FAILED;
01713                         break;
01714                 }
01715                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
01716                                MR_LP_ADV_HALF_DUPLEX |
01717                                MR_LP_ADV_SYM_PAUSE |
01718                                MR_LP_ADV_ASYM_PAUSE |
01719                                MR_LP_ADV_REMOTE_FAULT1 |
01720                                MR_LP_ADV_REMOTE_FAULT2 |
01721                                MR_LP_ADV_NEXT_PAGE |
01722                                MR_TOGGLE_RX |
01723                                MR_NP_RX);
01724                 if (ap->rxconfig & ANEG_CFG_FD)
01725                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
01726                 if (ap->rxconfig & ANEG_CFG_HD)
01727                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
01728                 if (ap->rxconfig & ANEG_CFG_PS1)
01729                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
01730                 if (ap->rxconfig & ANEG_CFG_PS2)
01731                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
01732                 if (ap->rxconfig & ANEG_CFG_RF1)
01733                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
01734                 if (ap->rxconfig & ANEG_CFG_RF2)
01735                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
01736                 if (ap->rxconfig & ANEG_CFG_NP)
01737                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
01738 
01739                 ap->link_time = ap->cur_time;
01740 
01741                 ap->flags ^= (MR_TOGGLE_TX);
01742                 if (ap->rxconfig & 0x0008)
01743                         ap->flags |= MR_TOGGLE_RX;
01744                 if (ap->rxconfig & ANEG_CFG_NP)
01745                         ap->flags |= MR_NP_RX;
01746                 ap->flags |= MR_PAGE_RX;
01747 
01748                 ap->state = ANEG_STATE_COMPLETE_ACK;
01749                 ret = ANEG_TIMER_ENAB;
01750                 break;
01751 
01752         case ANEG_STATE_COMPLETE_ACK:
01753                 if (ap->ability_match != 0 &&
01754                     ap->rxconfig == 0) {
01755                         ap->state = ANEG_STATE_AN_ENABLE;
01756                         break;
01757                 }
01758                 delta = ap->cur_time - ap->link_time;
01759                 if (delta > ANEG_STATE_SETTLE_TIME) {
01760                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
01761                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
01762                         } else {
01763                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
01764                                     !(ap->flags & MR_NP_RX)) {
01765                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
01766                                 } else {
01767                                         ret = ANEG_FAILED;
01768                                 }
01769                         }
01770                 }
01771                 break;
01772 
01773         case ANEG_STATE_IDLE_DETECT_INIT:
01774                 ap->link_time = ap->cur_time;
01775                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
01776                 tw32_f(MAC_MODE, tp->mac_mode);
01777                 udelay(40);
01778 
01779                 ap->state = ANEG_STATE_IDLE_DETECT;
01780                 ret = ANEG_TIMER_ENAB;
01781                 break;
01782 
01783         case ANEG_STATE_IDLE_DETECT:
01784                 if (ap->ability_match != 0 &&
01785                     ap->rxconfig == 0) {
01786                         ap->state = ANEG_STATE_AN_ENABLE;
01787                         break;
01788                 }
01789                 delta = ap->cur_time - ap->link_time;
01790                 if (delta > ANEG_STATE_SETTLE_TIME) {
01791                         /* XXX another gem from the Broadcom driver :( */
01792                         ap->state = ANEG_STATE_LINK_OK;
01793                 }
01794                 break;
01795 
01796         case ANEG_STATE_LINK_OK:
01797                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
01798                 ret = ANEG_DONE;
01799                 break;
01800 
01801         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
01802                 /* ??? unimplemented */
01803                 break;
01804 
01805         case ANEG_STATE_NEXT_PAGE_WAIT:
01806                 /* ??? unimplemented */
01807                 break;
01808 
01809         default:
01810                 ret = ANEG_FAILED;
01811                 break;
01812         }
01813 
01814         return ret;
01815 }
01816 
01817 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
01818 {
01819         int res = 0;
01820         struct tg3_fiber_aneginfo aninfo;
01821         int status = ANEG_FAILED;
01822         unsigned int tick;
01823         u32 tmp;
01824 
01825         tw32_f(MAC_TX_AUTO_NEG, 0);
01826 
01827         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
01828         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
01829         udelay(40);
01830 
01831         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
01832         udelay(40);
01833 
01834         memset(&aninfo, 0, sizeof(aninfo));
01835         aninfo.flags |= MR_AN_ENABLE;
01836         aninfo.state = ANEG_STATE_UNKNOWN;
01837         aninfo.cur_time = 0;
01838         tick = 0;
01839         while (++tick < 195000) {
01840                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
01841                 if (status == ANEG_DONE || status == ANEG_FAILED)
01842                         break;
01843 
01844                 udelay(1);
01845         }
01846 
01847         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
01848         tw32_f(MAC_MODE, tp->mac_mode);
01849         udelay(40);
01850 
01851         *txflags = aninfo.txconfig;
01852         *rxflags = aninfo.flags;
01853 
01854         if (status == ANEG_DONE &&
01855             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
01856                              MR_LP_ADV_FULL_DUPLEX)))
01857                 res = 1;
01858 
01859         return res;
01860 }
01861 
01862 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
01863 {
01864         int current_link_up = 0;
01865 
01866         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
01867                 goto out;
01868 
01869         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
01870                 u32 txflags, rxflags;
01871                 int i;
01872 
01873                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
01874                         u32 local_adv = 0, remote_adv = 0;
01875 
01876                         if (txflags & ANEG_CFG_PS1)
01877                                 local_adv |= ADVERTISE_1000XPAUSE;
01878                         if (txflags & ANEG_CFG_PS2)
01879                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
01880 
01881                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
01882                                 remote_adv |= LPA_1000XPAUSE;
01883                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
01884                                 remote_adv |= LPA_1000XPAUSE_ASYM;
01885 
01886                         tp->link_config.rmt_adv =
01887                                            mii_adv_to_ethtool_adv_x(remote_adv);
01888 
01889                         tg3_setup_flow_control(tp, local_adv, remote_adv);
01890 
01891                         current_link_up = 1;
01892                 }
01893                 for (i = 0; i < 30; i++) {
01894                         udelay(20);
01895                         tw32_f(MAC_STATUS,
01896                                (MAC_STATUS_SYNC_CHANGED |
01897                                 MAC_STATUS_CFG_CHANGED));
01898                         udelay(40);
01899                         if ((tr32(MAC_STATUS) &
01900                              (MAC_STATUS_SYNC_CHANGED |
01901                               MAC_STATUS_CFG_CHANGED)) == 0)
01902                                 break;
01903                 }
01904 
01905                 mac_status = tr32(MAC_STATUS);
01906                 if (!current_link_up &&
01907                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
01908                     !(mac_status & MAC_STATUS_RCVD_CFG))
01909                         current_link_up = 1;
01910         } else {
01911                 tg3_setup_flow_control(tp, 0, 0);
01912 
01913                 /* Forcing 1000FD link up. */
01914                 current_link_up = 1;
01915 
01916                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
01917                 udelay(40);
01918 
01919                 tw32_f(MAC_MODE, tp->mac_mode);
01920                 udelay(40);
01921         }
01922 
01923 out:
01924         return current_link_up;
01925 }
01926 
01927 static int tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
01928 {
01929         if (curr_link_up != tp->link_up) {
01930                 if (curr_link_up) {
01931                         netdev_link_up(tp->dev);
01932                 } else {
01933                         netdev_link_down(tp->dev);
01934                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
01935                                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
01936                 }
01937 
01938                 tg3_link_report(tp);
01939                 return 1;
01940         }
01941 
01942         return 0;
01943 }
01944 
01945 static void tg3_clear_mac_status(struct tg3 *tp)
01946 {
01947         tw32(MAC_EVENT, 0);
01948 
01949         tw32_f(MAC_STATUS,
01950                MAC_STATUS_SYNC_CHANGED |
01951                MAC_STATUS_CFG_CHANGED |
01952                MAC_STATUS_MI_COMPLETION |
01953                MAC_STATUS_LNKSTATE_CHANGED);
01954         udelay(40);
01955 }
01956 
01957 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
01958 {
01959         u32 orig_pause_cfg;
01960         u16 orig_active_speed;
01961         u8 orig_active_duplex;
01962         u32 mac_status;
01963         int current_link_up = force_reset;
01964         int i;
01965 
01966         orig_pause_cfg = tp->link_config.active_flowctrl;
01967         orig_active_speed = tp->link_config.active_speed;
01968         orig_active_duplex = tp->link_config.active_duplex;
01969 
01970         if (!tg3_flag(tp, HW_AUTONEG) &&
01971             tp->link_up &&
01972             tg3_flag(tp, INIT_COMPLETE)) {
01973                 mac_status = tr32(MAC_STATUS);
01974                 mac_status &= (MAC_STATUS_PCS_SYNCED |
01975                                MAC_STATUS_SIGNAL_DET |
01976                                MAC_STATUS_CFG_CHANGED |
01977                                MAC_STATUS_RCVD_CFG);
01978                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
01979                                    MAC_STATUS_SIGNAL_DET)) {
01980                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
01981                                             MAC_STATUS_CFG_CHANGED));
01982                         return 0;
01983                 }
01984         }
01985 
01986         tw32_f(MAC_TX_AUTO_NEG, 0);
01987 
01988         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
01989         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
01990         tw32_f(MAC_MODE, tp->mac_mode);
01991         udelay(40);
01992 
01993         if (tp->phy_id == TG3_PHY_ID_BCM8002)
01994                 tg3_init_bcm8002(tp);
01995 
01996         /* Enable link change event even when serdes polling.  */
01997         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
01998         udelay(40);
01999 
02000         current_link_up = 0;
02001         tp->link_config.rmt_adv = 0;
02002         mac_status = tr32(MAC_STATUS);
02003 
02004         if (tg3_flag(tp, HW_AUTONEG))
02005                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
02006         else
02007                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
02008 
02009         tp->hw_status->status =
02010                 (SD_STATUS_UPDATED |
02011                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
02012 
02013         for (i = 0; i < 100; i++) {
02014                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
02015                                     MAC_STATUS_CFG_CHANGED));
02016                 udelay(5);
02017                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
02018                                          MAC_STATUS_CFG_CHANGED |
02019                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
02020                         break;
02021         }
02022 
02023         mac_status = tr32(MAC_STATUS);
02024         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
02025                 current_link_up = 0;
02026                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
02027                     tp->serdes_counter == 0) {
02028                         tw32_f(MAC_MODE, (tp->mac_mode |
02029                                           MAC_MODE_SEND_CONFIGS));
02030                         udelay(1);
02031                         tw32_f(MAC_MODE, tp->mac_mode);
02032                 }
02033         }
02034 
02035         if (current_link_up) {
02036                 tp->link_config.active_speed = SPEED_1000;
02037                 tp->link_config.active_duplex = DUPLEX_FULL;
02038                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
02039                                     LED_CTRL_LNKLED_OVERRIDE |
02040                                     LED_CTRL_1000MBPS_ON));
02041         } else {
02042                 tp->link_config.active_speed = SPEED_UNKNOWN;
02043                 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
02044                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
02045                                     LED_CTRL_LNKLED_OVERRIDE |
02046                                     LED_CTRL_TRAFFIC_OVERRIDE));
02047         }
02048 
02049         if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
02050                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
02051                 if (orig_pause_cfg != now_pause_cfg ||
02052                     orig_active_speed != tp->link_config.active_speed ||
02053                     orig_active_duplex != tp->link_config.active_duplex)
02054                         tg3_link_report(tp);
02055         }
02056 
02057         return 0;
02058 }
02059 
02060 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
02061 {
02062         int err = 0;
02063         u32 bmsr, bmcr;
02064         u16 current_speed = SPEED_UNKNOWN;
02065         u8 current_duplex = DUPLEX_UNKNOWN;
02066         int current_link_up = 0;
02067         u32 local_adv, remote_adv, sgsr;
02068 
02069         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
02070              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
02071              !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
02072              (sgsr & SERDES_TG3_SGMII_MODE)) {
02073 
02074                 if (force_reset)
02075                         tg3_phy_reset(tp);
02076 
02077                 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
02078 
02079                 if (!(sgsr & SERDES_TG3_LINK_UP)) {
02080                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
02081                 } else {
02082                         current_link_up = 1;
02083                         if (sgsr & SERDES_TG3_SPEED_1000) {
02084                                 current_speed = SPEED_1000;
02085                                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
02086                         } else if (sgsr & SERDES_TG3_SPEED_100) {
02087                                 current_speed = SPEED_100;
02088                                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
02089                         } else {
02090                                 current_speed = SPEED_10;
02091                                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
02092                         }
02093 
02094                         if (sgsr & SERDES_TG3_FULL_DUPLEX)
02095                                 current_duplex = DUPLEX_FULL;
02096                         else
02097                                 current_duplex = DUPLEX_HALF;
02098                 }
02099 
02100                 tw32_f(MAC_MODE, tp->mac_mode);
02101                 udelay(40);
02102 
02103                 tg3_clear_mac_status(tp);
02104 
02105                 goto fiber_setup_done;
02106         }
02107 
02108         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
02109         tw32_f(MAC_MODE, tp->mac_mode);
02110         udelay(40);
02111 
02112         tg3_clear_mac_status(tp);
02113 
02114         if (force_reset)
02115                 tg3_phy_reset(tp);
02116 
02117         tp->link_config.rmt_adv = 0;
02118 
02119         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
02120         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
02121         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
02122                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
02123                         bmsr |= BMSR_LSTATUS;
02124                 else
02125                         bmsr &= ~BMSR_LSTATUS;
02126         }
02127 
02128         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
02129 
02130         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
02131             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
02132                 /* do nothing, just check for link up at the end */
02133         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
02134                 u32 adv, newadv;
02135 
02136                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
02137                 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
02138                                  ADVERTISE_1000XPAUSE |
02139                                  ADVERTISE_1000XPSE_ASYM |
02140                                  ADVERTISE_SLCT);
02141 
02142                 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
02143                 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
02144 
02145                 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
02146                         tg3_writephy(tp, MII_ADVERTISE, newadv);
02147                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
02148                         tg3_writephy(tp, MII_BMCR, bmcr);
02149 
02150                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
02151                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
02152                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
02153 
02154                         return err;
02155                 }
02156         } else {
02157                 u32 new_bmcr;
02158 
02159                 bmcr &= ~BMCR_SPEED1000;
02160                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
02161 
02162                 if (tp->link_config.duplex == DUPLEX_FULL)
02163                         new_bmcr |= BMCR_FULLDPLX;
02164 
02165                 if (new_bmcr != bmcr) {
02166                         /* BMCR_SPEED1000 is a reserved bit that needs
02167                          * to be set on write.
02168                          */
02169                         new_bmcr |= BMCR_SPEED1000;
02170 
02171                         /* Force a linkdown */
02172                         if (tp->link_up) {
02173                                 u32 adv;
02174 
02175                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
02176                                 adv &= ~(ADVERTISE_1000XFULL |
02177                                          ADVERTISE_1000XHALF |
02178                                          ADVERTISE_SLCT);
02179                                 tg3_writephy(tp, MII_ADVERTISE, adv);
02180                                 tg3_writephy(tp, MII_BMCR, bmcr |
02181                                                            BMCR_ANRESTART |
02182                                                            BMCR_ANENABLE);
02183                                 udelay(10);
02184                                 netdev_link_down(tp->dev);
02185                         }
02186                         tg3_writephy(tp, MII_BMCR, new_bmcr);
02187                         bmcr = new_bmcr;
02188                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
02189                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
02190                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
02191                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
02192                                         bmsr |= BMSR_LSTATUS;
02193                                 else
02194                                         bmsr &= ~BMSR_LSTATUS;
02195                         }
02196                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
02197                 }
02198         }
02199 
02200         if (bmsr & BMSR_LSTATUS) {
02201                 current_speed = SPEED_1000;
02202                 current_link_up = 1;
02203                 if (bmcr & BMCR_FULLDPLX)
02204                         current_duplex = DUPLEX_FULL;
02205                 else
02206                         current_duplex = DUPLEX_HALF;
02207 
02208                 local_adv = 0;
02209                 remote_adv = 0;
02210 
02211                 if (bmcr & BMCR_ANENABLE) {
02212                         u32 common;
02213 
02214                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
02215                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
02216                         common = local_adv & remote_adv;
02217                         if (common & (ADVERTISE_1000XHALF |
02218                                       ADVERTISE_1000XFULL)) {
02219                                 if (common & ADVERTISE_1000XFULL)
02220                                         current_duplex = DUPLEX_FULL;
02221                                 else
02222                                         current_duplex = DUPLEX_HALF;
02223 
02224                                 tp->link_config.rmt_adv =
02225                                            mii_adv_to_ethtool_adv_x(remote_adv);
02226                         } else if (!tg3_flag(tp, 5780_CLASS)) {
02227                                 /* Link is up via parallel detect */
02228                         } else {
02229                                 current_link_up = 0;
02230                         }
02231                 }
02232         }
02233 
02234 fiber_setup_done:
02235         if (current_link_up && current_duplex == DUPLEX_FULL)
02236                 tg3_setup_flow_control(tp, local_adv, remote_adv);
02237 
02238         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
02239         if (tp->link_config.active_duplex == DUPLEX_HALF)
02240                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
02241 
02242         tw32_f(MAC_MODE, tp->mac_mode);
02243         udelay(40);
02244 
02245         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
02246 
02247         tp->link_config.active_speed = current_speed;
02248         tp->link_config.active_duplex = current_duplex;
02249 
02250         tg3_test_and_report_link_chg(tp, current_link_up);
02251         return err;
02252 }
02253 
02254 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
02255 {       DBGP("%s\n", __func__);
02256 
02257         int current_link_up;
02258         u32 bmsr, val;
02259         u32 lcl_adv, rmt_adv;
02260         u16 current_speed;
02261         u8 current_duplex;
02262         int i, err;
02263 
02264         tw32(MAC_EVENT, 0);
02265 
02266         tw32_f(MAC_STATUS,
02267              (MAC_STATUS_SYNC_CHANGED |
02268               MAC_STATUS_CFG_CHANGED |
02269               MAC_STATUS_MI_COMPLETION |
02270               MAC_STATUS_LNKSTATE_CHANGED));
02271         udelay(40);
02272 
02273         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
02274                 tw32_f(MAC_MI_MODE,
02275                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
02276                 udelay(80);
02277         }
02278 
02279         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
02280 
02281         /* Some third-party PHYs need to be reset on link going
02282          * down.
02283          */
02284         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
02285              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
02286              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
02287             netdev_link_ok(tp->dev)) {
02288                 tg3_readphy(tp, MII_BMSR, &bmsr);
02289                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
02290                     !(bmsr & BMSR_LSTATUS))
02291                         force_reset = 1;
02292         }
02293         if (force_reset)
02294                 tg3_phy_reset(tp);
02295 
02296         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
02297                 tg3_readphy(tp, MII_BMSR, &bmsr);
02298                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
02299                     !tg3_flag(tp, INIT_COMPLETE))
02300                         bmsr = 0;
02301 
02302                 if (!(bmsr & BMSR_LSTATUS)) {
02303                         err = tg3_init_5401phy_dsp(tp);
02304                         if (err)
02305                                 return err;
02306 
02307                         tg3_readphy(tp, MII_BMSR, &bmsr);
02308                         for (i = 0; i < 1000; i++) {
02309                                 udelay(10);
02310                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
02311                                     (bmsr & BMSR_LSTATUS)) {
02312                                         udelay(40);
02313                                         break;
02314                                 }
02315                         }
02316 
02317                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
02318                             TG3_PHY_REV_BCM5401_B0 &&
02319                             !(bmsr & BMSR_LSTATUS) &&
02320                             tp->link_config.active_speed == SPEED_1000) {
02321                                 err = tg3_phy_reset(tp);
02322                                 if (!err)
02323                                         err = tg3_init_5401phy_dsp(tp);
02324                                 if (err)
02325                                         return err;
02326                         }
02327                 }
02328         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
02329                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
02330                 /* 5701 {A0,B0} CRC bug workaround */
02331                 tg3_writephy(tp, 0x15, 0x0a75);
02332                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
02333                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
02334                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
02335         }
02336 
02337         /* Clear pending interrupts... */
02338         tg3_readphy(tp, MII_TG3_ISTAT, &val);
02339         tg3_readphy(tp, MII_TG3_ISTAT, &val);
02340 
02341         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
02342                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
02343         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
02344                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
02345 
02346         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
02347             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
02348                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
02349                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
02350                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
02351                 else
02352                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
02353         }
02354 
02355         current_link_up = 0;
02356         current_speed = SPEED_INVALID;
02357         current_duplex = DUPLEX_INVALID;
02358 
02359         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
02360                 err = tg3_phy_auxctl_read(tp,
02361                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
02362                                           &val);
02363                 if (!err && !(val & (1 << 10))) {
02364                         tg3_phy_auxctl_write(tp,
02365                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
02366                                              val | (1 << 10));
02367                         goto relink;
02368                 }
02369         }
02370 
02371         bmsr = 0;
02372         for (i = 0; i < 100; i++) {
02373                 tg3_readphy(tp, MII_BMSR, &bmsr);
02374                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
02375                     (bmsr & BMSR_LSTATUS))
02376                         break;
02377                 udelay(40);
02378         }
02379 
02380         if (bmsr & BMSR_LSTATUS) {
02381                 u32 aux_stat, bmcr;
02382 
02383                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
02384                 for (i = 0; i < 2000; i++) {
02385                         udelay(10);
02386                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
02387                             aux_stat)
02388                                 break;
02389                 }
02390 
02391                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
02392                                              &current_speed,
02393                                              &current_duplex);
02394 
02395                 bmcr = 0;
02396                 for (i = 0; i < 200; i++) {
02397                         tg3_readphy(tp, MII_BMCR, &bmcr);
02398                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
02399                                 continue;
02400                         if (bmcr && bmcr != 0x7fff)
02401                                 break;
02402                         udelay(10);
02403                 }
02404 
02405                 lcl_adv = 0;
02406                 rmt_adv = 0;
02407 
02408                 tp->link_config.active_speed = current_speed;
02409                 tp->link_config.active_duplex = current_duplex;
02410 
02411                 if ((bmcr & BMCR_ANENABLE) &&
02412                     tg3_copper_is_advertising_all(tp,
02413                                         tp->link_config.advertising)) {
02414                         if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
02415                                                           &rmt_adv)) {
02416                                 current_link_up = 1;
02417                         }
02418                 }
02419 
02420                 if (current_link_up == 1 &&
02421                     tp->link_config.active_duplex == DUPLEX_FULL)
02422                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
02423         }
02424 
02425 relink:
02426         if (current_link_up == 0) {
02427                 tg3_phy_copper_begin(tp);
02428 
02429                 tg3_readphy(tp, MII_BMSR, &bmsr);
02430                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
02431                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
02432                         current_link_up = 1;
02433         }
02434 
02435         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
02436         if (current_link_up == 1) {
02437                 if (tp->link_config.active_speed == SPEED_100 ||
02438                     tp->link_config.active_speed == SPEED_10)
02439                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
02440                 else
02441                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
02442         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
02443                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
02444         else
02445                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
02446 
02447         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
02448         if (tp->link_config.active_duplex == DUPLEX_HALF)
02449                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
02450 
02451         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
02452                 if (current_link_up == 1 &&
02453                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
02454                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
02455                 else
02456                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
02457         }
02458 
02459         /* ??? Without this setting Netgear GA302T PHY does not
02460          * ??? send/receive packets...
02461          */
02462         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
02463             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
02464                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
02465                 tw32_f(MAC_MI_MODE, tp->mi_mode);
02466                 udelay(80);
02467         }
02468 
02469         tw32_f(MAC_MODE, tp->mac_mode);
02470         udelay(40);
02471 
02472         /* Enabled attention when the link has changed state. */
02473         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
02474         udelay(40);
02475 
02476         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
02477             current_link_up == 1 &&
02478             tp->link_config.active_speed == SPEED_1000 &&
02479             (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
02480                 udelay(120);
02481                 /* NOTE: this freezes for mdc? */
02482                 tw32_f(MAC_STATUS,
02483                      (MAC_STATUS_SYNC_CHANGED |
02484                       MAC_STATUS_CFG_CHANGED));
02485                 udelay(40);
02486                 tg3_write_mem(tp,
02487                               NIC_SRAM_FIRMWARE_MBOX,
02488                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
02489         }
02490 
02491         /* Prevent send BD corruption. */
02492         if (tg3_flag(tp, CLKREQ_BUG)) {
02493                 u16 oldlnkctl, newlnkctl;
02494 
02495                 pci_read_config_word(tp->pdev,
02496                                      tp->pcie_cap + PCI_EXP_LNKCTL,
02497                                      &oldlnkctl);
02498                 if (tp->link_config.active_speed == SPEED_100 ||
02499                     tp->link_config.active_speed == SPEED_10)
02500                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
02501                 else
02502                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
02503                 if (newlnkctl != oldlnkctl)
02504                         pci_write_config_word(tp->pdev,
02505                                               tp->pcie_cap + PCI_EXP_LNKCTL,
02506                                               newlnkctl);
02507         }
02508 
02509         if (current_link_up != netdev_link_ok(tp->dev)) {
02510                 if (current_link_up)
02511                         netdev_link_up(tp->dev);
02512                 else
02513                         netdev_link_down(tp->dev);
02514                 tg3_link_report(tp);
02515         }
02516 
02517         return 0;
02518 }
02519 
02520 int tg3_setup_phy(struct tg3 *tp, int force_reset)
02521 {       DBGP("%s\n", __func__);
02522 
02523         u32 val;
02524         int err;
02525 
02526         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
02527                 err = tg3_setup_fiber_phy(tp, force_reset);
02528         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
02529                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
02530         else
02531                 err = tg3_setup_copper_phy(tp, force_reset);
02532 
02533         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
02534               (6 << TX_LENGTHS_IPG_SHIFT);
02535         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
02536                 val |= tr32(MAC_TX_LENGTHS) &
02537                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
02538                         TX_LENGTHS_CNT_DWN_VAL_MSK);
02539 
02540         if (tp->link_config.active_speed == SPEED_1000 &&
02541             tp->link_config.active_duplex == DUPLEX_HALF)
02542                 tw32(MAC_TX_LENGTHS, val |
02543                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
02544         else
02545                 tw32(MAC_TX_LENGTHS, val |
02546                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
02547 
02548         if (!tg3_flag(tp, 5705_PLUS)) {
02549                 if (netdev_link_ok(tp->dev)) {
02550                         tw32(HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS);
02551                 } else {
02552                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
02553                 }
02554         }
02555 
02556         val = tr32(PCIE_PWR_MGMT_THRESH);
02557         if (!netdev_link_ok(tp->dev))
02558                 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK);
02559         else
02560                 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
02561         tw32(PCIE_PWR_MGMT_THRESH, val);
02562 
02563         return err;
02564 }