iPXE
tg3_hw.c
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00001 /*
00002  * tg3.c: Broadcom Tigon3 ethernet driver.
00003  *
00004  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
00005  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
00006  * Copyright (C) 2004 Sun Microsystems Inc.
00007  * Copyright (C) 2005-2011 Broadcom Corporation.
00008  *
00009  * Firmware is:
00010  *      Derived from proprietary unpublished source code,
00011  *      Copyright (C) 2000-2003 Broadcom Corporation.
00012  *
00013  *      Permission is hereby granted for the distribution of this firmware
00014  *      data in hexadecimal or equivalent format, provided this copyright
00015  *      notice is accompanying it.
00016  */
00017 
00018 FILE_LICENCE ( GPL2_ONLY );
00019 
00020 #include <mii.h>
00021 #include <stdio.h>
00022 #include <errno.h>
00023 #include <unistd.h>
00024 #include <byteswap.h>
00025 #include <ipxe/pci.h>
00026 #include <ipxe/iobuf.h>
00027 #include <ipxe/timer.h>
00028 #include <ipxe/malloc.h>
00029 #include <ipxe/if_ether.h>
00030 #include <ipxe/ethernet.h>
00031 #include <ipxe/netdevice.h>
00032 
00033 #include "tg3.h"
00034 
00035 #define RESET_KIND_SHUTDOWN     0
00036 #define RESET_KIND_INIT         1
00037 #define RESET_KIND_SUSPEND      2
00038 
00039 #define TG3_DEF_MAC_MODE        0
00040 
00041 void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
00042 {       DBGP("%s\n", __func__);
00043 
00044         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
00045         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
00046 }
00047 
00048 u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
00049 {       DBGP("%s\n", __func__);
00050 
00051         u32 val;
00052 
00053         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
00054         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
00055         return val;
00056 }
00057 
00058 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
00059 {       DBGP("%s\n", __func__);
00060 
00061         return readl(tp->regs + off + GRCMBOX_BASE);
00062 }
00063 
00064 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
00065 {       DBGP("%s\n", __func__);
00066 
00067         writel(val, tp->regs + off + GRCMBOX_BASE);
00068 }
00069 
00070 void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
00071 {       DBGP("%s\n", __func__);
00072 
00073         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
00074                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
00075                                        TG3_64BIT_REG_LOW, val);
00076                 return;
00077         }
00078         if (off == TG3_RX_STD_PROD_IDX_REG) {
00079                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
00080                                        TG3_64BIT_REG_LOW, val);
00081                 return;
00082         }
00083 
00084         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
00085         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
00086 
00087         /* In indirect mode when disabling interrupts, we also need
00088          * to clear the interrupt bit in the GRC local ctrl register.
00089          */
00090         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
00091             (val == 0x1)) {
00092                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
00093                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
00094         }
00095 }
00096 
00097 u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
00098 {       DBGP("%s\n", __func__);
00099 
00100         u32 val;
00101 
00102         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
00103         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
00104 
00105         return val;
00106 }
00107 
00108 /* usec_wait specifies the wait time in usec when writing to certain registers
00109  * where it is unsafe to read back the register without some delay.
00110  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
00111  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
00112  */
00113 void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
00114 {       DBGP("%s\n", __func__);
00115 
00116         tw32(off, val);
00117         if (usec_wait)
00118                 udelay(usec_wait);
00119         tr32(off);
00120 
00121         /* Wait again after the read for the posted method to guarantee that
00122          * the wait time is met.
00123          */
00124         if (usec_wait)
00125                 udelay(usec_wait);
00126 }
00127 
00128 /* stolen from legacy etherboot tg3 driver */
00129 void tg3_set_power_state_0(struct tg3 *tp)
00130 {       DBGP("%s\n", __func__);
00131 
00132         uint16_t power_control;
00133         int pm = tp->pm_cap;
00134 
00135         /* Make sure register accesses (indirect or otherwise)
00136          * will function correctly.
00137          */
00138         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
00139 
00140         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
00141 
00142         power_control |= PCI_PM_CTRL_PME_STATUS;
00143         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
00144         power_control |= 0;
00145         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
00146 
00147         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
00148 
00149         return;
00150 }
00151 
00152 void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
00153 {       DBGP("%s\n", __func__);
00154 
00155         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
00156             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
00157                 *val = 0;
00158                 return;
00159         }
00160 
00161         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
00162         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
00163 
00164         /* Always leave this as zero. */
00165         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
00166 }
00167 
00168 #define PCI_VENDOR_ID_ARIMA                0x161f
00169 
00170 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
00171 {       DBGP("%s\n", __func__);
00172 
00173         u32 val;
00174         u16 pmcsr;
00175 
00176         /* On some early chips the SRAM cannot be accessed in D3hot state,
00177          * so need make sure we're in D0.
00178          */
00179         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
00180         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
00181         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
00182         mdelay(1);
00183 
00184         /* Make sure register accesses (indirect or otherwise)
00185          * will function correctly.
00186          */
00187         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
00188                                tp->misc_host_ctrl);
00189 
00190         /* The memory arbiter has to be enabled in order for SRAM accesses
00191          * to succeed.  Normally on powerup the tg3 chip firmware will make
00192          * sure it is enabled, but other entities such as system netboot
00193          * code might disable it.
00194          */
00195         val = tr32(MEMARB_MODE);
00196         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
00197 
00198         tp->phy_id = TG3_PHY_ID_INVALID;
00199         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
00200 
00201         /* Assume an onboard device by default.  */
00202         tg3_flag_set(tp, EEPROM_WRITE_PROT);
00203 
00204         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
00205         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
00206                 u32 nic_cfg, led_cfg;
00207                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
00208                 int eeprom_phy_serdes = 0;
00209 
00210                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
00211                 tp->nic_sram_data_cfg = nic_cfg;
00212 
00213                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
00214                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
00215                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
00216                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
00217                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
00218                     (ver > 0) && (ver < 0x100))
00219                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
00220 
00221                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
00222                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
00223 
00224                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
00225                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
00226                         eeprom_phy_serdes = 1;
00227 
00228                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
00229                 if (nic_phy_id != 0) {
00230                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
00231                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
00232 
00233                         eeprom_phy_id  = (id1 >> 16) << 10;
00234                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
00235                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
00236                 } else
00237                         eeprom_phy_id = 0;
00238 
00239                 tp->phy_id = eeprom_phy_id;
00240                 if (eeprom_phy_serdes) {
00241                         if (!tg3_flag(tp, 5705_PLUS))
00242                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
00243                         else
00244                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
00245                 }
00246 
00247                 if (tg3_flag(tp, 5750_PLUS))
00248                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
00249                                     SHASTA_EXT_LED_MODE_MASK);
00250                 else
00251                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
00252 
00253                 switch (led_cfg) {
00254                 default:
00255                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
00256                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
00257                         break;
00258 
00259                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
00260                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
00261                         break;
00262 
00263                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
00264                         tp->led_ctrl = LED_CTRL_MODE_MAC;
00265 
00266                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
00267                          * read on some older 5700/5701 bootcode.
00268                          */
00269                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
00270                             ASIC_REV_5700 ||
00271                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
00272                             ASIC_REV_5701)
00273                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
00274 
00275                         break;
00276 
00277                 case SHASTA_EXT_LED_SHARED:
00278                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
00279                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
00280                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
00281                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
00282                                                  LED_CTRL_MODE_PHY_2);
00283                         break;
00284 
00285                 case SHASTA_EXT_LED_MAC:
00286                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
00287                         break;
00288 
00289                 case SHASTA_EXT_LED_COMBO:
00290                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
00291                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
00292                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
00293                                                  LED_CTRL_MODE_PHY_2);
00294                         break;
00295 
00296                 }
00297 
00298                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
00299                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
00300                     tp->subsystem_vendor == PCI_VENDOR_ID_DELL)
00301                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
00302 
00303                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
00304                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
00305 
00306                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
00307                         tg3_flag_set(tp, EEPROM_WRITE_PROT);
00308                         if ((tp->subsystem_vendor ==
00309                              PCI_VENDOR_ID_ARIMA) &&
00310                             (tp->subsystem_device == 0x205a ||
00311                              tp->subsystem_device == 0x2063))
00312                                 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
00313                 } else {
00314                         tg3_flag_clear(tp, EEPROM_WRITE_PROT);
00315                         tg3_flag_set(tp, IS_NIC);
00316                 }
00317 
00318                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
00319                         tg3_flag_set(tp, ENABLE_ASF);
00320                         if (tg3_flag(tp, 5750_PLUS))
00321                                 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
00322                 }
00323 
00324                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
00325                     tg3_flag(tp, ENABLE_ASF))
00326                         tg3_flag_set(tp, ENABLE_APE);
00327 
00328                 if (cfg2 & (1 << 17))
00329                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
00330 
00331                 /* serdes signal pre-emphasis in register 0x590 set by */
00332                 /* bootcode if bit 18 is set */
00333                 if (cfg2 & (1 << 18))
00334                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
00335 
00336                 if ((tg3_flag(tp, 57765_PLUS) ||
00337                      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
00338                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
00339                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
00340                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
00341 
00342                 if (tg3_flag(tp, PCI_EXPRESS) &&
00343                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
00344                     !tg3_flag(tp, 57765_PLUS)) {
00345                         u32 cfg3;
00346 
00347                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
00348                 }
00349 
00350                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
00351                         tg3_flag_set(tp, RGMII_INBAND_DISABLE);
00352                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
00353                         tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
00354                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
00355                         tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
00356         }
00357 }
00358 
00359 static void tg3_switch_clocks(struct tg3 *tp)
00360 {       DBGP("%s\n", __func__);
00361 
00362         u32 clock_ctrl;
00363         u32 orig_clock_ctrl;
00364 
00365         if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
00366                 return;
00367 
00368         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
00369 
00370         orig_clock_ctrl = clock_ctrl;
00371         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
00372                        CLOCK_CTRL_CLKRUN_OENABLE |
00373                        0x1f);
00374         tp->pci_clock_ctrl = clock_ctrl;
00375 
00376         if (tg3_flag(tp, 5705_PLUS)) {
00377                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
00378                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
00379                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
00380                 }
00381         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
00382                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
00383                             clock_ctrl |
00384                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
00385                             40);
00386                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
00387                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
00388                             40);
00389         }
00390         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
00391 }
00392 
00393 int tg3_get_invariants(struct tg3 *tp)
00394 {       DBGP("%s\n", __func__);
00395 
00396         u32 misc_ctrl_reg;
00397         u32 pci_state_reg, grc_misc_cfg;
00398         u32 val;
00399         u16 pci_cmd;
00400         int err;
00401 
00402         /* Force memory write invalidate off.  If we leave it on,
00403          * then on 5700_BX chips we have to enable a workaround.
00404          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
00405          * to match the cacheline size.  The Broadcom driver have this
00406          * workaround but turns MWI off all the times so never uses
00407          * it.  This seems to suggest that the workaround is insufficient.
00408          */
00409         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
00410         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
00411         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
00412 
00413         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
00414          * has the register indirect write enable bit set before
00415          * we try to access any of the MMIO registers.  It is also
00416          * critical that the PCI-X hw workaround situation is decided
00417          * before that as well.
00418          */
00419         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
00420                               &misc_ctrl_reg);
00421 
00422         tp->pci_chip_rev_id = (misc_ctrl_reg >>
00423                                MISC_HOST_CTRL_CHIPREV_SHIFT);
00424         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
00425                 u32 prod_id_asic_rev;
00426 
00427                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
00428                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
00429                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
00430                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
00431                         pci_read_config_dword(tp->pdev,
00432                                               TG3PCI_GEN2_PRODID_ASICREV,
00433                                               &prod_id_asic_rev);
00434                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
00435                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
00436                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
00437                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
00438                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
00439                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
00440                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
00441                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
00442                         pci_read_config_dword(tp->pdev,
00443                                               TG3PCI_GEN15_PRODID_ASICREV,
00444                                               &prod_id_asic_rev);
00445                 else
00446                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
00447                                               &prod_id_asic_rev);
00448 
00449                 tp->pci_chip_rev_id = prod_id_asic_rev;
00450         }
00451 
00452         /* Wrong chip ID in 5752 A0. This code can be removed later
00453          * as A0 is not in production.
00454          */
00455         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
00456                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
00457 
00458         /* Initialize misc host control in PCI block. */
00459         tp->misc_host_ctrl |= (misc_ctrl_reg &
00460                                MISC_HOST_CTRL_CHIPREV);
00461         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
00462                                tp->misc_host_ctrl);
00463 
00464         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
00465             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
00466             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
00467                 tg3_flag_set(tp, 5717_PLUS);
00468 
00469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
00470             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766 ||
00471             tg3_flag(tp, 5717_PLUS))
00472                 tg3_flag_set(tp, 57765_PLUS);
00473 
00474         /* Intentionally exclude ASIC_REV_5906 */
00475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
00476             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
00477             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
00478             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
00479             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
00480             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
00481             tg3_flag(tp, 57765_PLUS))
00482                 tg3_flag_set(tp, 5755_PLUS);
00483 
00484         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
00485             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
00486             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
00487             tg3_flag(tp, 5755_PLUS) ||
00488             tg3_flag(tp, 5780_CLASS))
00489                 tg3_flag_set(tp, 5750_PLUS);
00490 
00491         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
00492             tg3_flag(tp, 5750_PLUS))
00493                 tg3_flag_set(tp, 5705_PLUS);
00494 
00495         if (tg3_flag(tp, 5717_PLUS))
00496                 tg3_flag_set(tp, LRG_PROD_RING_CAP);
00497 
00498         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
00499                               &pci_state_reg);
00500 
00501         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
00502         if (tp->pcie_cap != 0) {
00503                 u16 lnkctl;
00504 
00505                 tg3_flag_set(tp, PCI_EXPRESS);
00506 
00507                 pci_read_config_word(tp->pdev,
00508                                      tp->pcie_cap + PCI_EXP_LNKCTL,
00509                                      &lnkctl);
00510                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
00511                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
00512                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
00513                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
00514                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
00515                                 tg3_flag_set(tp, CLKREQ_BUG);
00516                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
00517                         tg3_flag_set(tp, L1PLLPD_EN);
00518                 }
00519         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
00520                 tg3_flag_set(tp, PCI_EXPRESS);
00521         } else if (!tg3_flag(tp, 5705_PLUS) ||
00522                    tg3_flag(tp, 5780_CLASS)) {
00523                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
00524                 if (!tp->pcix_cap) {
00525                         DBGC(&tp->pdev->dev,
00526                                 "Cannot find PCI-X capability, aborting\n");
00527                         return -EIO;
00528                 }
00529 
00530                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
00531                         tg3_flag_set(tp, PCIX_MODE);
00532         }
00533 
00534         /* If we have an AMD 762 or VIA K8T800 chipset, write
00535          * reordering to the mailbox registers done by the host
00536          * controller can cause major troubles.  We read back from
00537          * every mailbox register write to force the writes to be
00538          * posted to the chip in order.
00539          */
00540 
00541         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
00542                              &tp->pci_cacheline_sz);
00543         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
00544                              &tp->pci_lat_timer);
00545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
00546             tp->pci_lat_timer < 64) {
00547                 tp->pci_lat_timer = 64;
00548                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
00549                                       tp->pci_lat_timer);
00550         }
00551 
00552         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
00553                 /* 5700 BX chips need to have their TX producer index
00554                  * mailboxes written twice to workaround a bug.
00555                  */
00556                 tg3_flag_set(tp, TXD_MBOX_HWBUG);
00557 
00558                 /* If we are in PCI-X mode, enable register write workaround.
00559                  *
00560                  * The workaround is to use indirect register accesses
00561                  * for all chip writes not to mailbox registers.
00562                  */
00563                 if (tg3_flag(tp, PCIX_MODE)) {
00564                         u32 pm_reg;
00565 
00566                         tg3_flag_set(tp, PCIX_TARGET_HWBUG);
00567 
00568                         /* The chip can have it's power management PCI config
00569                          * space registers clobbered due to this bug.
00570                          * So explicitly force the chip into D0 here.
00571                          */
00572                         pci_read_config_dword(tp->pdev,
00573                                               tp->pm_cap + PCI_PM_CTRL,
00574                                               &pm_reg);
00575                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
00576                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
00577                         pci_write_config_dword(tp->pdev,
00578                                                tp->pm_cap + PCI_PM_CTRL,
00579                                                pm_reg);
00580 
00581                         /* Also, force SERR#/PERR# in PCI command. */
00582                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
00583                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
00584                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
00585                 }
00586         }
00587 
00588         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
00589                 tg3_flag_set(tp, PCI_HIGH_SPEED);
00590         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
00591                 tg3_flag_set(tp, PCI_32BIT);
00592 
00593         /* Chip-specific fixup from Broadcom driver */
00594         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
00595             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
00596                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
00597                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
00598         }
00599 
00600         tp->write32_mbox = tg3_write_indirect_reg32;
00601         tp->write32_rx_mbox = tg3_write_indirect_mbox;
00602         tp->write32_tx_mbox = tg3_write_indirect_mbox;
00603         tp->read32_mbox = tg3_read_indirect_mbox;
00604 
00605         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
00606                 tp->read32_mbox = tg3_read32_mbox_5906;
00607                 tp->write32_mbox = tg3_write32_mbox_5906;
00608                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
00609                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
00610         }
00611 
00612         /* Get eeprom hw config before calling tg3_set_power_state().
00613          * In particular, the TG3_FLAG_IS_NIC flag must be
00614          * determined before calling tg3_set_power_state() so that
00615          * we know whether or not to switch out of Vaux power.
00616          * When the flag is set, it means that GPIO1 is used for eeprom
00617          * write protect and also implies that it is a LOM where GPIOs
00618          * are not used to switch power.
00619          */
00620         tg3_get_eeprom_hw_cfg(tp);
00621 
00622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
00623             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
00624             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
00625             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
00626             tg3_flag(tp, 57765_PLUS))
00627                 tg3_flag_set(tp, CPMU_PRESENT);
00628 
00629         /* Set up tp->grc_local_ctrl before calling tg3_power_up().
00630          * GPIO1 driven high will bring 5700's external PHY out of reset.
00631          * It is also used as eeprom write protect on LOMs.
00632          */
00633         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
00634         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
00635             tg3_flag(tp, EEPROM_WRITE_PROT))
00636                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
00637                                        GRC_LCLCTRL_GPIO_OUTPUT1);
00638         /* Unused GPIO3 must be driven as output on 5752 because there
00639          * are no pull-up resistors on unused GPIO pins.
00640          */
00641         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
00642                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
00643 
00644         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
00645             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
00646             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
00647                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
00648 
00649         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
00650             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
00651                 /* Turn off the debug UART. */
00652                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
00653                 if (tg3_flag(tp, IS_NIC))
00654                         /* Keep VMain power. */
00655                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
00656                                               GRC_LCLCTRL_GPIO_OUTPUT0;
00657         }
00658 
00659         /* Force the chip into D0. */
00660         tg3_set_power_state_0(tp);
00661 
00662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
00663                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
00664 
00665         /* A few boards don't want Ethernet@WireSpeed phy feature */
00666         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
00667             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
00668              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
00669              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
00670             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
00671             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
00672                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
00673 
00674         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
00675             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
00676                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
00677         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
00678                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
00679 
00680         if (tg3_flag(tp, 5705_PLUS) &&
00681             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
00682             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
00683             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
00684             !tg3_flag(tp, 57765_PLUS)) {
00685                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
00686                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
00687                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
00688                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
00689                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
00690                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
00691                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
00692                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
00693                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
00694                 } else
00695                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
00696         }
00697 
00698         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
00699             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
00700                 tp->phy_otp = tg3_read_otp_phycfg(tp);
00701                 if (tp->phy_otp == 0)
00702                         tp->phy_otp = TG3_OTP_DEFAULT;
00703         }
00704 
00705         if (tg3_flag(tp, CPMU_PRESENT))
00706                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
00707         else
00708                 tp->mi_mode = MAC_MI_MODE_BASE;
00709 
00710         tp->coalesce_mode = 0;
00711         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
00712             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
00713                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
00714 
00715         /* Set these bits to enable statistics workaround. */
00716         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
00717             tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
00718             tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
00719                 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
00720                 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
00721         }
00722 
00723         tg3_mdio_init(tp);
00724 
00725         /* Initialize data/descriptor byte/word swapping. */
00726         val = tr32(GRC_MODE);
00727         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
00728                 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
00729                         GRC_MODE_WORD_SWAP_B2HRX_DATA |
00730                         GRC_MODE_B2HRX_ENABLE |
00731                         GRC_MODE_HTX2B_ENABLE |
00732                         GRC_MODE_HOST_STACKUP);
00733         else
00734                 val &= GRC_MODE_HOST_STACKUP;
00735 
00736         tw32(GRC_MODE, val | tp->grc_mode);
00737 
00738         tg3_switch_clocks(tp);
00739 
00740         /* Clear this out for sanity. */
00741         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
00742 
00743         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
00744                               &pci_state_reg);
00745         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
00746             !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
00747                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
00748 
00749                 if (chiprevid == CHIPREV_ID_5701_A0 ||
00750                     chiprevid == CHIPREV_ID_5701_B0 ||
00751                     chiprevid == CHIPREV_ID_5701_B2 ||
00752                     chiprevid == CHIPREV_ID_5701_B5) {
00753                         void *sram_base;
00754 
00755                         /* Write some dummy words into the SRAM status block
00756                          * area, see if it reads back correctly.  If the return
00757                          * value is bad, force enable the PCIX workaround.
00758                          */
00759                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
00760 
00761                         writel(0x00000000, sram_base);
00762                         writel(0x00000000, sram_base + 4);
00763                         writel(0xffffffff, sram_base + 4);
00764                         if (readl(sram_base) != 0x00000000)
00765                                 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
00766                 }
00767         }
00768 
00769         udelay(50);
00770         /* FIXME: do we need nvram access? */
00771 ///     tg3_nvram_init(tp);
00772 
00773         grc_misc_cfg = tr32(GRC_MISC_CFG);
00774         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
00775 
00776         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
00777             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
00778              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
00779                 tg3_flag_set(tp, IS_5788);
00780 
00781         if (!tg3_flag(tp, IS_5788) &&
00782             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
00783                 tg3_flag_set(tp, TAGGED_STATUS);
00784         if (tg3_flag(tp, TAGGED_STATUS)) {
00785                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
00786                                       HOSTCC_MODE_CLRTICK_TXBD);
00787 
00788                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
00789                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
00790                                        tp->misc_host_ctrl);
00791         }
00792 
00793         /* Preserve the APE MAC_MODE bits */
00794         if (tg3_flag(tp, ENABLE_APE))
00795                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
00796         else
00797                 tp->mac_mode = TG3_DEF_MAC_MODE;
00798 
00799         /* these are limited to 10/100 only */
00800         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
00801              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
00802             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
00803              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
00804              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
00805               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
00806               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
00807             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
00808              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
00809               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
00810               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
00811             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
00812             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
00813             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
00814             (tp->phy_flags & TG3_PHYFLG_IS_FET))
00815                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
00816 
00817         err = tg3_phy_probe(tp);
00818         if (err) {
00819                 DBGC(&tp->pdev->dev, "phy probe failed, err: %s\n", strerror(err));
00820                 /* ... but do not return immediately ... */
00821         }
00822 
00823         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
00824                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
00825         } else {
00826                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
00827                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
00828                 else
00829                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
00830         }
00831 
00832         /* For all SERDES we poll the MAC status register. */
00833         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
00834                 tg3_flag_set(tp, POLL_SERDES);
00835         else
00836                 tg3_flag_clear(tp, POLL_SERDES);
00837 
00838         /* Increment the rx prod index on the rx std ring by at most
00839          * 8 for these chips to workaround hw errata.
00840          */
00841         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
00842             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
00843             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
00844                 tp->rx_std_max_post = 8;
00845 
00846         return err;
00847 }
00848 
00849 void tg3_init_bufmgr_config(struct tg3 *tp)
00850 {       DBGP("%s\n", __func__);
00851 
00852         if (tg3_flag(tp, 57765_PLUS)) {
00853                 tp->bufmgr_config.mbuf_read_dma_low_water =
00854                         DEFAULT_MB_RDMA_LOW_WATER_5705;
00855                 tp->bufmgr_config.mbuf_mac_rx_low_water =
00856                         DEFAULT_MB_MACRX_LOW_WATER_57765;
00857                 tp->bufmgr_config.mbuf_high_water =
00858                         DEFAULT_MB_HIGH_WATER_57765;
00859 
00860                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
00861                         DEFAULT_MB_RDMA_LOW_WATER_5705;
00862                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
00863                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
00864                 tp->bufmgr_config.mbuf_high_water_jumbo =
00865                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
00866         } else if (tg3_flag(tp, 5705_PLUS)) {
00867                 tp->bufmgr_config.mbuf_read_dma_low_water =
00868                         DEFAULT_MB_RDMA_LOW_WATER_5705;
00869                 tp->bufmgr_config.mbuf_mac_rx_low_water =
00870                         DEFAULT_MB_MACRX_LOW_WATER_5705;
00871                 tp->bufmgr_config.mbuf_high_water =
00872                         DEFAULT_MB_HIGH_WATER_5705;
00873                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
00874                         tp->bufmgr_config.mbuf_mac_rx_low_water =
00875                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
00876                         tp->bufmgr_config.mbuf_high_water =
00877                                 DEFAULT_MB_HIGH_WATER_5906;
00878                 }
00879 
00880                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
00881                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
00882                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
00883                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
00884                 tp->bufmgr_config.mbuf_high_water_jumbo =
00885                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
00886         } else {
00887                 tp->bufmgr_config.mbuf_read_dma_low_water =
00888                         DEFAULT_MB_RDMA_LOW_WATER;
00889                 tp->bufmgr_config.mbuf_mac_rx_low_water =
00890                         DEFAULT_MB_MACRX_LOW_WATER;
00891                 tp->bufmgr_config.mbuf_high_water =
00892                         DEFAULT_MB_HIGH_WATER;
00893 
00894                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
00895                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
00896                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
00897                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
00898                 tp->bufmgr_config.mbuf_high_water_jumbo =
00899                         DEFAULT_MB_HIGH_WATER_JUMBO;
00900         }
00901 
00902         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
00903         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
00904 }
00905 
00906 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
00907 
00908 void tg3_wait_for_event_ack(struct tg3 *tp)
00909 {       DBGP("%s\n", __func__);
00910 
00911         int i;
00912 
00913         for (i = 0; i < TG3_FW_EVENT_TIMEOUT_USEC / 10; i++) {
00914                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
00915                         break;
00916 
00917                 udelay(10);
00918         }
00919 }
00920 
00921 void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
00922 {       DBGP("%s\n", __func__);
00923 
00924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
00925             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
00926                 return;
00927 
00928         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
00929         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
00930 
00931         /* Always leave this as zero. */
00932         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
00933 }
00934 
00935 static void tg3_stop_fw(struct tg3 *tp)
00936 {       DBGP("%s\n", __func__);
00937 
00938         if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
00939                 /* Wait for RX cpu to ACK the previous event. */
00940                 tg3_wait_for_event_ack(tp);
00941 
00942                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
00943 
00944                 tg3_generate_fw_event(tp);
00945 
00946                 /* Wait for RX cpu to ACK this event. */
00947                 tg3_wait_for_event_ack(tp);
00948         }
00949 }
00950 
00951 static void tg3_write_sig_pre_reset(struct tg3 *tp)
00952 {       DBGP("%s\n", __func__);
00953 
00954         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
00955                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
00956 }
00957 
00958 void tg3_disable_ints(struct tg3 *tp)
00959 {       DBGP("%s\n", __func__);
00960 
00961         tw32(TG3PCI_MISC_HOST_CTRL,
00962              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
00963 
00964         tw32_mailbox_f(tp->int_mbox, 0x00000001);
00965 }
00966 
00967 void tg3_enable_ints(struct tg3 *tp)
00968 {       DBGP("%s\n", __func__);
00969 
00970         tw32(TG3PCI_MISC_HOST_CTRL,
00971              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
00972 
00973         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
00974 
00975         tw32_mailbox_f(tp->int_mbox, tp->last_tag << 24);
00976 
00977         /* Force an initial interrupt */
00978         if (!tg3_flag(tp, TAGGED_STATUS) &&
00979             (tp->hw_status->status & SD_STATUS_UPDATED))
00980                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
00981         else
00982                 tw32(HOSTCC_MODE, tp->coal_now);
00983 }
00984 
00985 #define MAX_WAIT_CNT 1000
00986 
00987 /* To stop a block, clear the enable bit and poll till it clears. */
00988 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit)
00989 {       DBGP("%s\n", __func__);
00990 
00991         unsigned int i;
00992         u32 val;
00993 
00994         if (tg3_flag(tp, 5705_PLUS)) {
00995                 switch (ofs) {
00996                 case RCVLSC_MODE:
00997                 case DMAC_MODE:
00998                 case MBFREE_MODE:
00999                 case BUFMGR_MODE:
01000                 case MEMARB_MODE:
01001                         /* We can't enable/disable these bits of the
01002                          * 5705/5750, just say success.
01003                          */
01004                         return 0;
01005 
01006                 default:
01007                         break;
01008                 }
01009         }
01010 
01011         val = tr32(ofs);
01012         val &= ~enable_bit;
01013         tw32_f(ofs, val);
01014 
01015         for (i = 0; i < MAX_WAIT_CNT; i++) {
01016                 udelay(100);
01017                 val = tr32(ofs);
01018                 if ((val & enable_bit) == 0)
01019                         break;
01020         }
01021 
01022         if (i == MAX_WAIT_CNT) {
01023                 DBGC(&tp->pdev->dev,
01024                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
01025                         ofs, enable_bit);
01026                 return -ENODEV;
01027         }
01028 
01029         return 0;
01030 }
01031 
01032 static int tg3_abort_hw(struct tg3 *tp)
01033 {       DBGP("%s\n", __func__);
01034 
01035         int i, err;
01036 
01037         tg3_disable_ints(tp);
01038 
01039         tp->rx_mode &= ~RX_MODE_ENABLE;
01040         tw32_f(MAC_RX_MODE, tp->rx_mode);
01041         udelay(10);
01042 
01043         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE);
01044         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE);
01045         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE);
01046         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE);
01047         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE);
01048         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE);
01049 
01050         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE);
01051         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE);
01052         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
01053         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE);
01054         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
01055         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE);
01056         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE);
01057 
01058         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
01059         tw32_f(MAC_MODE, tp->mac_mode);
01060         udelay(40);
01061 
01062         tp->tx_mode &= ~TX_MODE_ENABLE;
01063         tw32_f(MAC_TX_MODE, tp->tx_mode);
01064 
01065         for (i = 0; i < MAX_WAIT_CNT; i++) {
01066                 udelay(100);
01067                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
01068                         break;
01069         }
01070         if (i >= MAX_WAIT_CNT) {
01071                 DBGC(&tp->pdev->dev,
01072                         "%s timed out, TX_MODE_ENABLE will not clear "
01073                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
01074                 err |= -ENODEV;
01075         }
01076 
01077         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
01078         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE);
01079         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
01080 
01081         tw32(FTQ_RESET, 0xffffffff);
01082         tw32(FTQ_RESET, 0x00000000);
01083 
01084         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
01085         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
01086 
01087         if (tp->hw_status)
01088                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
01089 
01090         return err;
01091 }
01092 
01093 void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
01094 {       DBGP("%s\n", __func__);
01095 
01096         u32 addr_high, addr_low;
01097         int i;
01098 
01099         addr_high = ((tp->dev->ll_addr[0] << 8) |
01100                      tp->dev->ll_addr[1]);
01101         addr_low = ((tp->dev->ll_addr[2] << 24) |
01102                     (tp->dev->ll_addr[3] << 16) |
01103                     (tp->dev->ll_addr[4] <<  8) |
01104                     (tp->dev->ll_addr[5] <<  0));
01105         for (i = 0; i < 4; i++) {
01106                 if (i == 1 && skip_mac_1)
01107                         continue;
01108                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
01109                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
01110         }
01111 
01112         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
01113             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
01114                 for (i = 0; i < 12; i++) {
01115                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
01116                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
01117                 }
01118         }
01119 
01120         addr_high = (tp->dev->ll_addr[0] +
01121                      tp->dev->ll_addr[1] +
01122                      tp->dev->ll_addr[2] +
01123                      tp->dev->ll_addr[3] +
01124                      tp->dev->ll_addr[4] +
01125                      tp->dev->ll_addr[5]) &
01126                 TX_BACKOFF_SEED_MASK;
01127         tw32(MAC_TX_BACKOFF_SEED, addr_high);
01128 }
01129 
01130 /* Save PCI command register before chip reset */
01131 static void tg3_save_pci_state(struct tg3 *tp)
01132 {       DBGP("%s\n", __func__);
01133 
01134         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
01135 }
01136 
01137 /* Restore PCI state after chip reset */
01138 static void tg3_restore_pci_state(struct tg3 *tp)
01139 {       DBGP("%s\n", __func__);
01140 
01141         u32 val;
01142 
01143         /* Re-enable indirect register accesses. */
01144         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
01145                                tp->misc_host_ctrl);
01146 
01147         /* Set MAX PCI retry to zero. */
01148         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
01149         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
01150             tg3_flag(tp, PCIX_MODE))
01151                 val |= PCISTATE_RETRY_SAME_DMA;
01152 
01153         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
01154 
01155         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
01156 
01157         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
01158                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
01159                                               tp->pci_cacheline_sz);
01160                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
01161                                               tp->pci_lat_timer);
01162         }
01163 
01164 
01165         /* Make sure PCI-X relaxed ordering bit is clear. */
01166         if (tg3_flag(tp, PCIX_MODE)) {
01167                 u16 pcix_cmd;
01168 
01169                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
01170                                      &pcix_cmd);
01171                 pcix_cmd &= ~PCI_X_CMD_ERO;
01172                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
01173                                       pcix_cmd);
01174         }
01175 }
01176 
01177 static int tg3_poll_fw(struct tg3 *tp)
01178 {       DBGP("%s\n", __func__);
01179 
01180         int i;
01181         u32 val;
01182 
01183         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
01184                 /* Wait up to 20ms for init done. */
01185                 for (i = 0; i < 200; i++) {
01186                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
01187                                 return 0;
01188                         udelay(100);
01189                 }
01190                 return -ENODEV;
01191         }
01192 
01193         /* Wait for firmware initialization to complete. */
01194         for (i = 0; i < 100000; i++) {
01195                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
01196                 if (val == (u32)~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
01197                         break;
01198                 udelay(10);
01199         }
01200 
01201         /* Chip might not be fitted with firmware.  Some Sun onboard
01202          * parts are configured like that.  So don't signal the timeout
01203          * of the above loop as an error, but do report the lack of
01204          * running firmware once.
01205          */
01206         if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
01207                 tg3_flag_set(tp, NO_FWARE_REPORTED);
01208 
01209                 DBGC(tp->dev, "No firmware running\n");
01210         }
01211 
01212         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
01213                 /* The 57765 A0 needs a little more
01214                  * time to do some important work.
01215                  */
01216                 mdelay(10);
01217         }
01218 
01219         return 0;
01220 }
01221 
01222 static int tg3_nvram_lock(struct tg3 *tp)
01223 {       DBGP("%s\n", __func__);
01224 
01225         if (tg3_flag(tp, NVRAM)) {
01226                 int i;
01227 
01228                 if (tp->nvram_lock_cnt == 0) {
01229                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
01230                         for (i = 0; i < 8000; i++) {
01231                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
01232                                         break;
01233                                 udelay(20);
01234                         }
01235                         if (i == 8000) {
01236                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
01237                                 return -ENODEV;
01238                         }
01239                 }
01240                 tp->nvram_lock_cnt++;
01241         }
01242         return 0;
01243 }
01244 
01245 static void tg3_nvram_unlock(struct tg3 *tp)
01246 {       DBGP("%s\n", __func__);
01247 
01248         if (tg3_flag(tp, NVRAM)) {
01249                 if (tp->nvram_lock_cnt > 0)
01250                         tp->nvram_lock_cnt--;
01251                 if (tp->nvram_lock_cnt == 0)
01252                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
01253         }
01254 }
01255 
01256 static int tg3_chip_reset(struct tg3 *tp)
01257 {       DBGP("%s\n", __func__);
01258 
01259         u32 val;
01260         int err;
01261 
01262         tg3_nvram_lock(tp);
01263 
01264 
01265         /* No matching tg3_nvram_unlock() after this because
01266          * chip reset below will undo the nvram lock.
01267          */
01268         tp->nvram_lock_cnt = 0;
01269 
01270         /* GRC_MISC_CFG core clock reset will clear the memory
01271          * enable bit in PCI register 4 and the MSI enable bit
01272          * on some chips, so we save relevant registers here.
01273          */
01274         tg3_save_pci_state(tp);
01275 
01276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
01277             tg3_flag(tp, 5755_PLUS))
01278                 tw32(GRC_FASTBOOT_PC, 0);
01279 
01280 #if 0
01281         /*
01282          * We must avoid the readl() that normally takes place.
01283          * It locks machines, causes machine checks, and other
01284          * fun things.  So, temporarily disable the 5701
01285          * hardware workaround, while we do the reset.
01286          */
01287         write_op = tp->write32;
01288         if (write_op == tg3_write_flush_reg32)
01289                 tp->write32 = tg3_write32;
01290 #endif
01291 
01292         /* Prevent the irq handler from reading or writing PCI registers
01293          * during chip reset when the memory enable bit in the PCI command
01294          * register may be cleared.  The chip does not generate interrupt
01295          * at this time, but the irq handler may still be called due to irq
01296          * sharing or irqpoll.
01297          */
01298         tg3_flag_set(tp, CHIP_RESETTING);
01299 
01300         if (tp->hw_status) {
01301                 tp->hw_status->status = 0;
01302                 tp->hw_status->status_tag = 0;
01303         }
01304         tp->last_tag = 0;
01305         tp->last_irq_tag = 0;
01306 
01307         mb();
01308 
01309         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
01310                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
01311                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
01312         }
01313 
01314         /* do the reset */
01315         val = GRC_MISC_CFG_CORECLK_RESET;
01316 
01317         if (tg3_flag(tp, PCI_EXPRESS)) {
01318                 /* Force PCIe 1.0a mode */
01319                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
01320                     !tg3_flag(tp, 57765_PLUS) &&
01321                     tr32(TG3_PCIE_PHY_TSTCTL) ==
01322                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
01323                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
01324 
01325                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
01326                         tw32(GRC_MISC_CFG, (1 << 29));
01327                         val |= (1 << 29);
01328                 }
01329         }
01330 
01331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
01332                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
01333                 tw32(GRC_VCPU_EXT_CTRL,
01334                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
01335         }
01336 
01337         /* Manage gphy power for all CPMU absent PCIe devices. */
01338         if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
01339                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
01340 
01341         tw32(GRC_MISC_CFG, val);
01342 
01343         /* Unfortunately, we have to delay before the PCI read back.
01344          * Some 575X chips even will not respond to a PCI cfg access
01345          * when the reset command is given to the chip.
01346          *
01347          * How do these hardware designers expect things to work
01348          * properly if the PCI write is posted for a long period
01349          * of time?  It is always necessary to have some method by
01350          * which a register read back can occur to push the write
01351          * out which does the reset.
01352          *
01353          * For most tg3 variants the trick below was working.
01354          * Ho hum...
01355          */
01356         udelay(120);
01357 
01358         /* Flush PCI posted writes.  The normal MMIO registers
01359          * are inaccessible at this time so this is the only
01360          * way to make this reliably (actually, this is no longer
01361          * the case, see above).  I tried to use indirect
01362          * register read/write but this upset some 5701 variants.
01363          */
01364         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
01365 
01366         udelay(120);
01367 
01368         if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) {
01369                 u16 val16;
01370 
01371                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
01372                         int i;
01373                         u32 cfg_val;
01374 
01375                         /* Wait for link training to complete.  */
01376                         for (i = 0; i < 5000; i++)
01377                                 udelay(100);
01378 
01379                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
01380                         pci_write_config_dword(tp->pdev, 0xc4,
01381                                                cfg_val | (1 << 15));
01382                 }
01383 
01384                 /* Clear the "no snoop" and "relaxed ordering" bits. */
01385                 pci_read_config_word(tp->pdev,
01386                                      tp->pcie_cap + PCI_EXP_DEVCTL,
01387                                      &val16);
01388                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
01389                            PCI_EXP_DEVCTL_NOSNOOP_EN);
01390                 /*
01391                  * Older PCIe devices only support the 128 byte
01392                  * MPS setting.  Enforce the restriction.
01393                  */
01394                 if (!tg3_flag(tp, CPMU_PRESENT))
01395                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
01396                 pci_write_config_word(tp->pdev,
01397                                       tp->pcie_cap + PCI_EXP_DEVCTL,
01398                                       val16);
01399 
01400                 /* Clear error status */
01401                 pci_write_config_word(tp->pdev,
01402                                       tp->pcie_cap + PCI_EXP_DEVSTA,
01403                                       PCI_EXP_DEVSTA_CED |
01404                                       PCI_EXP_DEVSTA_NFED |
01405                                       PCI_EXP_DEVSTA_FED |
01406                                       PCI_EXP_DEVSTA_URD);
01407         }
01408 
01409         tg3_restore_pci_state(tp);
01410 
01411         tg3_flag_clear(tp, CHIP_RESETTING);
01412         tg3_flag_clear(tp, ERROR_PROCESSED);
01413 
01414         val = 0;
01415         if (tg3_flag(tp, 5780_CLASS))
01416                 val = tr32(MEMARB_MODE);
01417         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
01418 
01419         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
01420                 tg3_stop_fw(tp);
01421                 tw32(0x5000, 0x400);
01422         }
01423 
01424         tw32(GRC_MODE, tp->grc_mode);
01425 
01426         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
01427                 val = tr32(0xc4);
01428 
01429                 tw32(0xc4, val | (1 << 15));
01430         }
01431 
01432         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
01433             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
01434                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
01435                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
01436                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
01437                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
01438         }
01439 
01440         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
01441                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
01442                 val = tp->mac_mode;
01443         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
01444                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
01445                 val = tp->mac_mode;
01446         } else
01447                 val = 0;
01448 
01449         tw32_f(MAC_MODE, val);
01450         udelay(40);
01451 
01452         err = tg3_poll_fw(tp);
01453         if (err)
01454                 return err;
01455 
01456         if (tg3_flag(tp, PCI_EXPRESS) &&
01457             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
01458             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
01459             !tg3_flag(tp, 57765_PLUS)) {
01460                 val = tr32(0x7c00);
01461 
01462                 tw32(0x7c00, val | (1 << 25));
01463         }
01464 
01465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
01466                 val = tr32(TG3_CPMU_CLCK_ORIDE);
01467                 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
01468         }
01469 
01470         if (tg3_flag(tp, CPMU_PRESENT)) {
01471                 tw32(TG3_CPMU_D0_CLCK_POLICY, 0);
01472                 val = tr32(TG3_CPMU_CLCK_ORIDE_EN);
01473                 tw32(TG3_CPMU_CLCK_ORIDE_EN,
01474                      val | CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN);
01475         }
01476 
01477         return 0;
01478 }
01479 
01480 int tg3_halt(struct tg3 *tp)
01481 {       DBGP("%s\n", __func__);
01482 
01483         int err;
01484 
01485         tg3_stop_fw(tp);
01486 
01487         tg3_write_sig_pre_reset(tp);
01488 
01489         tg3_abort_hw(tp);
01490         err = tg3_chip_reset(tp);
01491 
01492         __tg3_set_mac_addr(tp, 0);
01493 
01494         if (err)
01495                 return err;
01496 
01497         return 0;
01498 }
01499 
01500 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
01501                                         u32 offset, u32 *val)
01502 {       DBGP("%s\n", __func__);
01503 
01504         u32 tmp;
01505         int i;
01506 
01507         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
01508                 return -EINVAL;
01509 
01510         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
01511                                         EEPROM_ADDR_DEVID_MASK |
01512                                         EEPROM_ADDR_READ);
01513         tw32(GRC_EEPROM_ADDR,
01514              tmp |
01515              (0 << EEPROM_ADDR_DEVID_SHIFT) |
01516              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
01517               EEPROM_ADDR_ADDR_MASK) |
01518              EEPROM_ADDR_READ | EEPROM_ADDR_START);
01519 
01520         for (i = 0; i < 1000; i++) {
01521                 tmp = tr32(GRC_EEPROM_ADDR);
01522 
01523                 if (tmp & EEPROM_ADDR_COMPLETE)
01524                         break;
01525                 mdelay(1);
01526         }
01527         if (!(tmp & EEPROM_ADDR_COMPLETE))
01528                 return -EBUSY;
01529 
01530         tmp = tr32(GRC_EEPROM_DATA);
01531 
01532         /*
01533          * The data will always be opposite the native endian
01534          * format.  Perform a blind byteswap to compensate.
01535          */
01536         *val = bswap_32(tmp);
01537 
01538         return 0;
01539 }
01540 
01541 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
01542 {       DBGP("%s\n", __func__);
01543 
01544         if (tg3_flag(tp, NVRAM) &&
01545             tg3_flag(tp, NVRAM_BUFFERED) &&
01546             tg3_flag(tp, FLASH) &&
01547             !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
01548             (tp->nvram_jedecnum == JEDEC_ATMEL))
01549 
01550                 addr = ((addr / tp->nvram_pagesize) <<
01551                         ATMEL_AT45DB0X1B_PAGE_POS) +
01552                        (addr % tp->nvram_pagesize);
01553 
01554         return addr;
01555 }
01556 
01557 static void tg3_enable_nvram_access(struct tg3 *tp)
01558 {       DBGP("%s\n", __func__);
01559 
01560         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
01561                 u32 nvaccess = tr32(NVRAM_ACCESS);
01562 
01563                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
01564         }
01565 }
01566 
01567 static void tg3_disable_nvram_access(struct tg3 *tp)
01568 {       DBGP("%s\n", __func__);
01569 
01570         if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
01571                 u32 nvaccess = tr32(NVRAM_ACCESS);
01572 
01573                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
01574         }
01575 }
01576 
01577 #define NVRAM_CMD_TIMEOUT 10000
01578 
01579 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
01580 {       DBGP("%s\n", __func__);
01581 
01582         int i;
01583 
01584         tw32(NVRAM_CMD, nvram_cmd);
01585         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
01586                 udelay(10);
01587                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
01588                         udelay(10);
01589                         break;
01590                 }
01591         }
01592 
01593         if (i == NVRAM_CMD_TIMEOUT)
01594                 return -EBUSY;
01595 
01596         return 0;
01597 }
01598 
01599 /* NOTE: Data read in from NVRAM is byteswapped according to
01600  * the byteswapping settings for all other register accesses.
01601  * tg3 devices are BE devices, so on a BE machine, the data
01602  * returned will be exactly as it is seen in NVRAM.  On a LE
01603  * machine, the 32-bit value will be byteswapped.
01604  */
01605 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
01606 {       DBGP("%s\n", __func__);
01607 
01608         int ret;
01609 
01610         if (!tg3_flag(tp, NVRAM))
01611                 return tg3_nvram_read_using_eeprom(tp, offset, val);
01612 
01613         offset = tg3_nvram_phys_addr(tp, offset);
01614 
01615         if (offset > NVRAM_ADDR_MSK)
01616                 return -EINVAL;
01617 
01618         ret = tg3_nvram_lock(tp);
01619         if (ret)
01620                 return ret;
01621 
01622         tg3_enable_nvram_access(tp);
01623 
01624         tw32(NVRAM_ADDR, offset);
01625         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
01626                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
01627 
01628         if (ret == 0)
01629                 *val = tr32(NVRAM_RDDATA);
01630 
01631         tg3_disable_nvram_access(tp);
01632 
01633         tg3_nvram_unlock(tp);
01634 
01635         return ret;
01636 }
01637 
01638 /* Ensures NVRAM data is in bytestream format. */
01639 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, u32 *val)
01640 {       DBGP("%s\n", __func__);
01641 
01642         u32 v = 0;
01643         int res = tg3_nvram_read(tp, offset, &v);
01644         if (!res)
01645                 *val = cpu_to_be32(v);
01646         return res;
01647 }
01648 
01649 int tg3_get_device_address(struct tg3 *tp)
01650 {       DBGP("%s\n", __func__);
01651 
01652         struct net_device *dev = tp->dev;
01653         u32 hi, lo, mac_offset;
01654         int addr_ok = 0;
01655 
01656         mac_offset = 0x7c;
01657         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
01658             tg3_flag(tp, 5780_CLASS)) {
01659                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
01660                         mac_offset = 0xcc;
01661                 if (tg3_nvram_lock(tp))
01662                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
01663                 else
01664                         tg3_nvram_unlock(tp);
01665         } else if (tg3_flag(tp, 5717_PLUS)) {
01666                 if (PCI_FUNC(tp->pdev->busdevfn) & 1)
01667                         mac_offset = 0xcc;
01668                 if (PCI_FUNC(tp->pdev->busdevfn) > 1)
01669                         mac_offset += 0x18c;
01670         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
01671                 mac_offset = 0x10;
01672 
01673         /* First try to get it from MAC address mailbox. */
01674         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
01675         if ((hi >> 16) == 0x484b) {
01676                 dev->hw_addr[0] = (hi >>  8) & 0xff;
01677                 dev->hw_addr[1] = (hi >>  0) & 0xff;
01678 
01679                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
01680                 dev->hw_addr[2] = (lo >> 24) & 0xff;
01681                 dev->hw_addr[3] = (lo >> 16) & 0xff;
01682                 dev->hw_addr[4] = (lo >>  8) & 0xff;
01683                 dev->hw_addr[5] = (lo >>  0) & 0xff;
01684 
01685                 /* Some old bootcode may report a 0 MAC address in SRAM */
01686                 addr_ok = is_valid_ether_addr(&dev->hw_addr[0]);
01687         }
01688         if (!addr_ok) {
01689                 /* Next, try NVRAM. */
01690                 if (!tg3_flag(tp, NO_NVRAM) &&
01691                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
01692                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
01693                         memcpy(&dev->hw_addr[0], ((char *)&hi) + 2, 2);
01694                         memcpy(&dev->hw_addr[2], (char *)&lo, sizeof(lo));
01695                 }
01696                 /* Finally just fetch it out of the MAC control regs. */
01697                 else {
01698                         hi = tr32(MAC_ADDR_0_HIGH);
01699                         lo = tr32(MAC_ADDR_0_LOW);
01700 
01701                         dev->hw_addr[5] = lo & 0xff;
01702                         dev->hw_addr[4] = (lo >> 8) & 0xff;
01703                         dev->hw_addr[3] = (lo >> 16) & 0xff;
01704                         dev->hw_addr[2] = (lo >> 24) & 0xff;
01705                         dev->hw_addr[1] = hi & 0xff;
01706                         dev->hw_addr[0] = (hi >> 8) & 0xff;
01707                 }
01708         }
01709 
01710         if (!is_valid_ether_addr(&dev->hw_addr[0])) {
01711                 return -EINVAL;
01712         }
01713 
01714         return 0;
01715 }
01716 
01717 static void __tg3_set_rx_mode(struct net_device *dev)
01718 {       DBGP("%s\n", __func__);
01719 
01720         struct tg3 *tp = netdev_priv(dev);
01721         u32 rx_mode;
01722 
01723         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
01724                                   RX_MODE_KEEP_VLAN_TAG);
01725 
01726         rx_mode |= RX_MODE_KEEP_VLAN_TAG;
01727 
01728         /* Accept all multicast. */
01729         tw32(MAC_HASH_REG_0, 0xffffffff);
01730         tw32(MAC_HASH_REG_1, 0xffffffff);
01731         tw32(MAC_HASH_REG_2, 0xffffffff);
01732         tw32(MAC_HASH_REG_3, 0xffffffff);
01733 
01734         if (rx_mode != tp->rx_mode) {
01735                 tp->rx_mode = rx_mode;
01736                 tw32_f(MAC_RX_MODE, rx_mode);
01737                 udelay(10);
01738         }
01739 }
01740 
01741 static void __tg3_set_coalesce(struct tg3 *tp)
01742 {       DBGP("%s\n", __func__);
01743 
01744 
01745         tw32(HOSTCC_RXCOL_TICKS, 0);
01746         tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
01747         tw32(HOSTCC_RXMAX_FRAMES, 1);
01748         /* FIXME: mix between TXMAX and RXMAX taken from legacy driver */
01749         tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
01750         tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
01751         tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
01752 
01753         if (!tg3_flag(tp, 5705_PLUS)) {
01754                 u32 val = DEFAULT_STAT_COAL_TICKS;
01755 
01756                 tw32(HOSTCC_RXCOAL_TICK_INT, DEFAULT_RXCOAL_TICK_INT);
01757                 tw32(HOSTCC_TXCOAL_TICK_INT, DEFAULT_TXCOAL_TICK_INT);
01758 
01759                 if (!netdev_link_ok(tp->dev))
01760                         val = 0;
01761 
01762                 tw32(HOSTCC_STAT_COAL_TICKS, val);
01763         }
01764 }
01765 
01766 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
01767                            dma_addr_t mapping, u32 maxlen_flags,
01768                            u32 nic_addr)
01769 {       DBGP("%s\n", __func__);
01770 
01771         tg3_write_mem(tp,
01772                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
01773                       ((u64) mapping >> 32));
01774         tg3_write_mem(tp,
01775                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
01776                       ((u64) mapping & 0xffffffff));
01777         tg3_write_mem(tp,
01778                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
01779                        maxlen_flags);
01780 
01781         if (!tg3_flag(tp, 5705_PLUS))
01782                 tg3_write_mem(tp,
01783                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
01784                               nic_addr);
01785 }
01786 
01787 static void tg3_rings_reset(struct tg3 *tp)
01788 {       DBGP("%s\n", __func__);
01789 
01790         int i;
01791         u32 txrcb, rxrcb, limit;
01792 
01793         /* Disable all transmit rings but the first. */
01794         if (!tg3_flag(tp, 5705_PLUS))
01795                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
01796         else if (tg3_flag(tp, 5717_PLUS))
01797                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
01798         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
01799                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
01800         else
01801                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
01802 
01803         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
01804              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
01805                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
01806                               BDINFO_FLAGS_DISABLED);
01807 
01808 
01809         /* Disable all receive return rings but the first. */
01810         if (tg3_flag(tp, 5717_PLUS))
01811                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
01812         else if (!tg3_flag(tp, 5705_PLUS))
01813                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
01814         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
01815                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
01816                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
01817         else
01818                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
01819 
01820         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
01821              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
01822                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
01823                               BDINFO_FLAGS_DISABLED);
01824 
01825         /* Disable interrupts */
01826         tw32_mailbox_f(tp->int_mbox, 1);
01827 
01828         tp->tx_prod = 0;
01829         tp->tx_cons = 0;
01830         tw32_mailbox(tp->prodmbox, 0);
01831         tw32_rx_mbox(tp->consmbox, 0);
01832 
01833         /* Make sure the NIC-based send BD rings are disabled. */
01834         if (!tg3_flag(tp, 5705_PLUS)) {
01835                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
01836                 for (i = 0; i < 16; i++)
01837                         tw32_tx_mbox(mbox + i * 8, 0);
01838         }
01839 
01840         txrcb = NIC_SRAM_SEND_RCB;
01841         rxrcb = NIC_SRAM_RCV_RET_RCB;
01842 
01843         /* Clear status block in ram. */
01844         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
01845 
01846         /* Set status block DMA address */
01847         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
01848              ((u64) tp->status_mapping >> 32));
01849         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
01850              ((u64) tp->status_mapping & 0xffffffff));
01851 
01852         if (tp->tx_ring) {
01853                 tg3_set_bdinfo(tp, txrcb, tp->tx_desc_mapping,
01854                                (TG3_TX_RING_SIZE <<
01855                                 BDINFO_FLAGS_MAXLEN_SHIFT),
01856                                NIC_SRAM_TX_BUFFER_DESC);
01857                 txrcb += TG3_BDINFO_SIZE;
01858         }
01859 
01860         /* FIXME: will TG3_RX_RET_MAX_SIZE_5705 work on all cards? */
01861         if (tp->rx_rcb) {
01862                 tg3_set_bdinfo(tp, rxrcb, tp->rx_rcb_mapping,
01863                                 TG3_RX_RET_MAX_SIZE_5705 <<
01864                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
01865                 rxrcb += TG3_BDINFO_SIZE;
01866         }
01867 }
01868 
01869 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
01870 {       DBGP("%s\n", __func__);
01871 
01872         u32 val, bdcache_maxcnt;
01873 
01874         if (!tg3_flag(tp, 5750_PLUS) ||
01875             tg3_flag(tp, 5780_CLASS) ||
01876             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
01877             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
01878                 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
01879         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
01880                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
01881                 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
01882         else
01883                 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
01884 
01885 
01886         /* NOTE: legacy driver uses RX_PENDING / 8, we only use 4 descriptors
01887          * for now, use / 4 so the result is > 0
01888          */
01889         val = TG3_DEF_RX_RING_PENDING / 4;
01890         tw32(RCVBDI_STD_THRESH, val);
01891 
01892         if (tg3_flag(tp, 57765_PLUS))
01893                 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
01894 }
01895 
01896 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
01897 {       DBGP("%s\n", __func__);
01898 
01899         u32 val, rdmac_mode;
01900         int i, err, limit;
01901         struct tg3_rx_prodring_set *tpr = &tp->prodring;
01902 
01903         tg3_stop_fw(tp);
01904 
01905         tg3_write_sig_pre_reset(tp);
01906 
01907         if (tg3_flag(tp, INIT_COMPLETE))
01908                 tg3_abort_hw(tp);
01909 
01910         if (reset_phy)
01911                 tg3_phy_reset(tp);
01912 
01913         err = tg3_chip_reset(tp);
01914         if (err)
01915                 return err;
01916 
01917         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
01918                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
01919                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
01920                        PCIE_PWR_MGMT_L1_THRESH_4MS;
01921                 tw32(PCIE_PWR_MGMT_THRESH, val);
01922 
01923                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
01924                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
01925 
01926                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
01927 
01928                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
01929                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
01930         }
01931 
01932         if (tg3_flag(tp, L1PLLPD_EN)) {
01933                 u32 grc_mode = tr32(GRC_MODE);
01934 
01935                 /* Access the lower 1K of PL PCIE block registers. */
01936                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
01937                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
01938 
01939                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
01940                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
01941                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
01942 
01943                 tw32(GRC_MODE, grc_mode);
01944         }
01945 
01946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
01947                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
01948                         u32 grc_mode = tr32(GRC_MODE);
01949 
01950                         /* Access the lower 1K of PL PCIE block registers. */
01951                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
01952                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
01953 
01954                         val = tr32(TG3_PCIE_TLDLPL_PORT +
01955                                    TG3_PCIE_PL_LO_PHYCTL5);
01956                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
01957                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
01958 
01959                         tw32(GRC_MODE, grc_mode);
01960                 }
01961 
01962                 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
01963                         u32 grc_mode = tr32(GRC_MODE);
01964 
01965                         /* Access the lower 1K of DL PCIE block registers. */
01966                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
01967                         tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
01968 
01969                         val = tr32(TG3_PCIE_TLDLPL_PORT +
01970                                    TG3_PCIE_DL_LO_FTSMAX);
01971                         val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
01972                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
01973                              val | TG3_PCIE_DL_LO_FTSMAX_VAL);
01974 
01975                         tw32(GRC_MODE, grc_mode);
01976                 }
01977 
01978                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
01979                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
01980                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
01981                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
01982         }
01983 
01984         /* This works around an issue with Athlon chipsets on
01985          * B3 tigon3 silicon.  This bit has no effect on any
01986          * other revision.  But do not set this on PCI Express
01987          * chips and don't even touch the clocks if the CPMU is present.
01988          */
01989         if (!tg3_flag(tp, CPMU_PRESENT)) {
01990                 if (!tg3_flag(tp, PCI_EXPRESS))
01991                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
01992                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
01993         }
01994 
01995         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
01996             tg3_flag(tp, PCIX_MODE)) {
01997                 val = tr32(TG3PCI_PCISTATE);
01998                 val |= PCISTATE_RETRY_SAME_DMA;
01999                 tw32(TG3PCI_PCISTATE, val);
02000         }
02001 
02002         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
02003                 /* Enable some hw fixes.  */
02004                 val = tr32(TG3PCI_MSI_DATA);
02005                 val |= (1 << 26) | (1 << 28) | (1 << 29);
02006                 tw32(TG3PCI_MSI_DATA, val);
02007         }
02008 
02009         /* Descriptor ring init may make accesses to the
02010          * NIC SRAM area to setup the TX descriptors, so we
02011          * can only do this after the hardware has been
02012          * successfully reset.
02013          */
02014         err = tg3_init_rings(tp);
02015         if (err)
02016                 return err;
02017 
02018         if (tg3_flag(tp, 57765_PLUS)) {
02019                 val = tr32(TG3PCI_DMA_RW_CTRL) &
02020                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
02021                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
02022                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
02023                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
02024                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
02025                         val |= DMA_RWCTRL_TAGGED_STAT_WA;
02026                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
02027         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
02028                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
02029                 /* This value is determined during the probe time DMA
02030                  * engine test, tg3_test_dma.
02031                  */
02032                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
02033         }
02034 
02035         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
02036                           GRC_MODE_4X_NIC_SEND_RINGS |
02037                           GRC_MODE_NO_TX_PHDR_CSUM |
02038                           GRC_MODE_NO_RX_PHDR_CSUM);
02039         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
02040         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
02041 
02042         /* Pseudo-header checksum is done by hardware logic and not
02043          * the offload processers, so make the chip do the pseudo-
02044          * header checksums on receive.  For transmit it is more
02045          * convenient to do the pseudo-header checksum in software
02046          * as Linux does that on transmit for us in all cases.
02047          */
02048         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
02049 
02050         tw32(GRC_MODE,
02051              tp->grc_mode |
02052              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
02053 
02054         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
02055         val = tr32(GRC_MISC_CFG);
02056         val &= ~0xff;
02057         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
02058         tw32(GRC_MISC_CFG, val);
02059 
02060         /* Initialize MBUF/DESC pool. */
02061         if (tg3_flag(tp, 5750_PLUS)) {
02062                 /* Do nothing.  */
02063         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
02064                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
02065                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
02066                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
02067                 else
02068                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
02069                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
02070                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
02071         }
02072 
02073         tw32(BUFMGR_MB_RDMA_LOW_WATER,
02074              tp->bufmgr_config.mbuf_read_dma_low_water);
02075         tw32(BUFMGR_MB_MACRX_LOW_WATER,
02076              tp->bufmgr_config.mbuf_mac_rx_low_water);
02077         tw32(BUFMGR_MB_HIGH_WATER,
02078              tp->bufmgr_config.mbuf_high_water);
02079 
02080         tw32(BUFMGR_DMA_LOW_WATER,
02081              tp->bufmgr_config.dma_low_water);
02082         tw32(BUFMGR_DMA_HIGH_WATER,
02083              tp->bufmgr_config.dma_high_water);
02084 
02085         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
02086         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
02087                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
02088         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
02089             tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
02090             tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
02091                 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
02092         tw32(BUFMGR_MODE, val);
02093         for (i = 0; i < 2000; i++) {
02094                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
02095                         break;
02096                 udelay(10);
02097         }
02098         if (i >= 2000) {
02099                 DBGC(tp->dev, "%s cannot enable BUFMGR\n", __func__);
02100                 return -ENODEV;
02101         }
02102 
02103         if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
02104                 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
02105 
02106         tg3_setup_rxbd_thresholds(tp);
02107 
02108         /* Initialize TG3_BDINFO's at:
02109          *  RCVDBDI_STD_BD:     standard eth size rx ring
02110          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
02111          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
02112          *
02113          * like so:
02114          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
02115          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
02116          *                              ring attribute flags
02117          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
02118          *
02119          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
02120          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
02121          *
02122          * The size of each ring is fixed in the firmware, but the location is
02123          * configurable.
02124          */
02125         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
02126              ((u64) tpr->rx_std_mapping >> 32));
02127         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
02128              ((u64) tpr->rx_std_mapping & 0xffffffff));
02129         if (!tg3_flag(tp, 5717_PLUS))
02130                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
02131                      NIC_SRAM_RX_BUFFER_DESC);
02132 
02133         /* Disable the mini ring */
02134         if (!tg3_flag(tp, 5705_PLUS))
02135                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
02136                      BDINFO_FLAGS_DISABLED);
02137 
02138         val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
02139 
02140         if (tg3_flag(tp, 57765_PLUS))
02141                 val |= (RX_STD_MAX_SIZE << 2);
02142 
02143         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
02144 
02145         tpr->rx_std_prod_idx = 0;
02146 
02147         /* std prod index is updated by tg3_refill_prod_ring() */
02148         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, 0);
02149         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, 0);
02150 
02151         tg3_rings_reset(tp);
02152 
02153         __tg3_set_mac_addr(tp,0);
02154 
02155 #define TG3_MAX_MTU     1522
02156         /* MTU + ethernet header + FCS + optional VLAN tag */
02157         tw32(MAC_RX_MTU_SIZE, TG3_MAX_MTU);
02158 
02159         /* The slot time is changed by tg3_setup_phy if we
02160          * run at gigabit with half duplex.
02161          */
02162         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
02163               (6 << TX_LENGTHS_IPG_SHIFT) |
02164               (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
02165 
02166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
02167                 val |= tr32(MAC_TX_LENGTHS) &
02168                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
02169                         TX_LENGTHS_CNT_DWN_VAL_MSK);
02170 
02171         tw32(MAC_TX_LENGTHS, val);
02172 
02173         /* Receive rules. */
02174         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
02175         tw32(RCVLPC_CONFIG, 0x0181);
02176 
02177         /* Calculate RDMAC_MODE setting early, we need it to determine
02178          * the RCVLPC_STATE_ENABLE mask.
02179          */
02180         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
02181                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
02182                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
02183                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
02184                       RDMAC_MODE_LNGREAD_ENAB);
02185 
02186         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
02187                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
02188 
02189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
02190             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
02191             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
02192                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
02193                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
02194                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
02195 
02196         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
02197             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
02198                 if (tg3_flag(tp, TSO_CAPABLE) &&
02199                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
02200                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
02201                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
02202                            !tg3_flag(tp, IS_5788)) {
02203                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
02204                 }
02205         }
02206 
02207         if (tg3_flag(tp, PCI_EXPRESS))
02208                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
02209 
02210         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
02211                 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
02212 
02213         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
02214             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
02215             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
02216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
02217             tg3_flag(tp, 57765_PLUS)) {
02218                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
02219                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
02220                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
02221                         val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
02222                                  TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
02223                                  TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
02224                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
02225                                TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
02226                                TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
02227                 }
02228                 tw32(TG3_RDMA_RSRVCTRL_REG,
02229                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
02230         }
02231 
02232         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
02233             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
02234                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
02235                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
02236                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
02237                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
02238         }
02239 
02240         /* Receive/send statistics. */
02241         if (tg3_flag(tp, 5750_PLUS)) {
02242                 val = tr32(RCVLPC_STATS_ENABLE);
02243                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
02244                 tw32(RCVLPC_STATS_ENABLE, val);
02245         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
02246                    tg3_flag(tp, TSO_CAPABLE)) {
02247                 val = tr32(RCVLPC_STATS_ENABLE);
02248                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
02249                 tw32(RCVLPC_STATS_ENABLE, val);
02250         } else {
02251                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
02252         }
02253         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
02254         tw32(SNDDATAI_STATSENAB, 0xffffff);
02255         tw32(SNDDATAI_STATSCTRL,
02256              (SNDDATAI_SCTRL_ENABLE |
02257               SNDDATAI_SCTRL_FASTUPD));
02258 
02259         /* Setup host coalescing engine. */
02260         tw32(HOSTCC_MODE, 0);
02261         for (i = 0; i < 2000; i++) {
02262                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
02263                         break;
02264                 udelay(10);
02265         }
02266 
02267         __tg3_set_coalesce(tp);
02268 
02269         if (!tg3_flag(tp, 5705_PLUS)) {
02270                 /* Status/statistics block address.  See tg3_timer,
02271                  * the tg3_periodic_fetch_stats call there, and
02272                  * tg3_get_stats to see how this works for 5705/5750 chips.
02273                  * NOTE: stats block removed for iPXE
02274                  */
02275                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
02276 
02277                 /* Clear statistics and status block memory areas */
02278                 for (i = NIC_SRAM_STATS_BLK;
02279                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
02280                      i += sizeof(u32)) {
02281                         tg3_write_mem(tp, i, 0);
02282                         udelay(40);
02283                 }
02284         }
02285 
02286         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
02287 
02288         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
02289         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
02290         if (!tg3_flag(tp, 5705_PLUS))
02291                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
02292 
02293         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
02294                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
02295                 /* reset to prevent losing 1st rx packet intermittently */
02296                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
02297                 udelay(10);
02298         }
02299 
02300         if (tg3_flag(tp, ENABLE_APE))
02301                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
02302         else
02303                 tp->mac_mode = 0;
02304         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
02305                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
02306         if (!tg3_flag(tp, 5705_PLUS) &&
02307             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
02308             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
02309                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
02310         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
02311         udelay(40);
02312 
02313         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
02314          * If TG3_FLAG_IS_NIC is zero, we should read the
02315          * register to preserve the GPIO settings for LOMs. The GPIOs,
02316          * whether used as inputs or outputs, are set by boot code after
02317          * reset.
02318          */
02319         if (!tg3_flag(tp, IS_NIC)) {
02320                 u32 gpio_mask;
02321 
02322                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
02323                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
02324                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
02325 
02326                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
02327                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
02328                                      GRC_LCLCTRL_GPIO_OUTPUT3;
02329 
02330                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
02331                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
02332 
02333                 tp->grc_local_ctrl &= ~gpio_mask;
02334                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
02335 
02336                 /* GPIO1 must be driven high for eeprom write protect */
02337                 if (tg3_flag(tp, EEPROM_WRITE_PROT))
02338                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
02339                                                GRC_LCLCTRL_GPIO_OUTPUT1);
02340         }
02341         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
02342         udelay(100);
02343 
02344         if (!tg3_flag(tp, 5705_PLUS)) {
02345                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
02346                 udelay(40);
02347         }
02348 
02349         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
02350                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
02351                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
02352                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
02353                WDMAC_MODE_LNGREAD_ENAB);
02354 
02355         /* Enable host coalescing bug fix */
02356         if (tg3_flag(tp, 5755_PLUS))
02357                 val |= WDMAC_MODE_STATUS_TAG_FIX;
02358 
02359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
02360                 val |= WDMAC_MODE_BURST_ALL_DATA;
02361 
02362         tw32_f(WDMAC_MODE, val);
02363         udelay(40);
02364 
02365         if (tg3_flag(tp, PCIX_MODE)) {
02366                 u16 pcix_cmd;
02367 
02368                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
02369                                      &pcix_cmd);
02370                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
02371                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
02372                         pcix_cmd |= PCI_X_CMD_READ_2K;
02373                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
02374                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
02375                         pcix_cmd |= PCI_X_CMD_READ_2K;
02376                 }
02377                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
02378                                       pcix_cmd);
02379         }
02380 
02381         tw32_f(RDMAC_MODE, rdmac_mode);
02382         udelay(40);
02383 
02384         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
02385         if (!tg3_flag(tp, 5705_PLUS))
02386                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
02387 
02388         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
02389                 tw32(SNDDATAC_MODE,
02390                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
02391         else
02392                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
02393 
02394         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
02395         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
02396         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
02397         if (tg3_flag(tp, LRG_PROD_RING_CAP))
02398                 val |= RCVDBDI_MODE_LRG_RING_SZ;
02399         tw32(RCVDBDI_MODE, val);
02400         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
02401 
02402         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
02403         if (tg3_flag(tp, ENABLE_TSS))
02404                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
02405         tw32(SNDBDI_MODE, val);
02406         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
02407 
02408 
02409         /* FIXME: 5701 firmware fix? */
02410 #if 0
02411         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
02412                 err = tg3_load_5701_a0_firmware_fix(tp);
02413                 if (err)
02414                         return err;
02415         }
02416 #endif
02417 
02418         tp->tx_mode = TX_MODE_ENABLE;
02419 
02420         if (tg3_flag(tp, 5755_PLUS) ||
02421             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
02422                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
02423 
02424         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
02425                 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
02426                 tp->tx_mode &= ~val;
02427                 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
02428         }
02429 
02430         tw32_f(MAC_TX_MODE, tp->tx_mode);
02431         udelay(100);
02432 
02433         tp->rx_mode = RX_MODE_ENABLE;
02434 
02435         tw32_f(MAC_RX_MODE, tp->rx_mode);
02436         udelay(10);
02437 
02438         tw32(MAC_LED_CTRL, tp->led_ctrl);
02439 
02440         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
02441         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
02442                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
02443                 udelay(10);
02444         }
02445         tw32_f(MAC_RX_MODE, tp->rx_mode);
02446         udelay(10);
02447 
02448         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
02449                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
02450                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
02451                         /* Set drive transmission level to 1.2V  */
02452                         /* only if the signal pre-emphasis bit is not set  */
02453                         val = tr32(MAC_SERDES_CFG);
02454                         val &= 0xfffff000;
02455                         val |= 0x880;
02456                         tw32(MAC_SERDES_CFG, val);
02457                 }
02458                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
02459                         tw32(MAC_SERDES_CFG, 0x616000);
02460         }
02461 
02462         /* Prevent chip from dropping frames when flow control
02463          * is enabled.
02464          */
02465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
02466                 val = 1;
02467         else
02468                 val = 2;
02469         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
02470 
02471         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
02472             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
02473                 /* Use hardware link auto-negotiation */
02474                 tg3_flag_set(tp, HW_AUTONEG);
02475         }
02476 
02477         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
02478             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
02479                 u32 tmp;
02480 
02481                 tmp = tr32(SERDES_RX_CTRL);
02482                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
02483                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
02484                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
02485                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
02486         }
02487 
02488         err = tg3_setup_phy(tp, 0);
02489         if (err)
02490                 return err;
02491 
02492         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
02493             !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
02494                 u32 tmp;
02495 
02496                 /* Clear CRC stats. */
02497                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
02498                         tg3_writephy(tp, MII_TG3_TEST1,
02499                                      tmp | MII_TG3_TEST1_CRC_EN);
02500                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
02501                 }
02502         }
02503 
02504         __tg3_set_rx_mode(tp->dev);
02505 
02506         /* Initialize receive rules. */
02507         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
02508         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
02509         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
02510         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
02511 
02512         if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
02513                 limit = 8;
02514         else
02515                 limit = 16;
02516         if (tg3_flag(tp, ENABLE_ASF))
02517                 limit -= 4;
02518         switch (limit) {
02519         case 16:
02520                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
02521                 /* Fall through */
02522         case 15:
02523                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
02524                 /* Fall through */
02525         case 14:
02526                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
02527                 /* Fall through */
02528         case 13:
02529                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
02530                 /* Fall through */
02531         case 12:
02532                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
02533                 /* Fall through */
02534         case 11:
02535                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
02536                 /* Fall through */
02537         case 10:
02538                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
02539                 /* Fall through */
02540         case 9:
02541                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
02542                 /* Fall through */
02543         case 8:
02544                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
02545                 /* Fall through */
02546         case 7:
02547                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
02548                 /* Fall through */
02549         case 6:
02550                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
02551                 /* Fall through */
02552         case 5:
02553                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
02554                 /* Fall through */
02555         case 4:
02556                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
02557         case 3:
02558                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
02559         case 2:
02560         case 1:
02561 
02562         default:
02563                 break;
02564         }
02565 
02566         return 0;
02567 }
02568 
02569 /* Called at device open time to get the chip ready for
02570  * packet processing.  Invoked with tp->lock held.
02571  */
02572 int tg3_init_hw(struct tg3 *tp, int reset_phy)
02573 {       DBGP("%s\n", __func__);
02574 
02575         tg3_switch_clocks(tp);
02576 
02577         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
02578 
02579         return tg3_reset_hw(tp, reset_phy);
02580 }
02581 
02582 void tg3_set_txd(struct tg3 *tp, int entry,
02583                         dma_addr_t mapping, int len, u32 flags)
02584 {       DBGP("%s\n", __func__);
02585 
02586         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
02587 
02588         txd->addr_hi = ((u64) mapping >> 32);
02589         txd->addr_lo = ((u64) mapping & 0xffffffff);
02590         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
02591         txd->vlan_tag = 0;
02592 }
02593 
02594 int tg3_do_test_dma(struct tg3 *tp, u32 __unused *buf, dma_addr_t buf_dma, int size, int to_device)
02595 {       DBGP("%s\n", __func__);
02596 
02597         struct tg3_internal_buffer_desc test_desc;
02598         u32 sram_dma_descs;
02599         int ret;
02600         unsigned int i;
02601 
02602         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
02603 
02604         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
02605         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
02606         tw32(RDMAC_STATUS, 0);
02607         tw32(WDMAC_STATUS, 0);
02608 
02609         tw32(BUFMGR_MODE, 0);
02610         tw32(FTQ_RESET, 0);
02611 
02612         test_desc.addr_hi = ((u64) buf_dma) >> 32;
02613         test_desc.addr_lo = buf_dma & 0xffffffff;
02614         test_desc.nic_mbuf = 0x00002100;
02615         test_desc.len = size;
02616 
02617         /*
02618          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
02619          * the *second* time the tg3 driver was getting loaded after an
02620          * initial scan.
02621          *
02622          * Broadcom tells me:
02623          *   ...the DMA engine is connected to the GRC block and a DMA
02624          *   reset may affect the GRC block in some unpredictable way...
02625          *   The behavior of resets to individual blocks has not been tested.
02626          *
02627          * Broadcom noted the GRC reset will also reset all sub-components.
02628          */
02629         if (to_device) {
02630                 test_desc.cqid_sqid = (13 << 8) | 2;
02631 
02632                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
02633                 udelay(40);
02634         } else {
02635                 test_desc.cqid_sqid = (16 << 8) | 7;
02636 
02637                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
02638                 udelay(40);
02639         }
02640         test_desc.flags = 0x00000005;
02641 
02642         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
02643                 u32 val;
02644 
02645                 val = *(((u32 *)&test_desc) + i);
02646                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
02647                                        sram_dma_descs + (i * sizeof(u32)));
02648                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
02649         }
02650         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
02651 
02652         if (to_device)
02653                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
02654         else
02655                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
02656 
02657         ret = -ENODEV;
02658         for (i = 0; i < 40; i++) {
02659                 u32 val;
02660 
02661                 if (to_device)
02662                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
02663                 else
02664                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
02665                 if ((val & 0xffff) == sram_dma_descs) {
02666                         ret = 0;
02667                         break;
02668                 }
02669 
02670                 udelay(100);
02671         }
02672 
02673         return ret;
02674 }