iPXE
tlan.c
Go to the documentation of this file.
00001 /**************************************************************************
00002 *
00003 *    tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
00004 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
00005 *
00006 *    This program is free software; you can redistribute it and/or modify
00007 *    it under the terms of the GNU General Public License as published by
00008 *    the Free Software Foundation; either version 2 of the License, or
00009 *    (at your option) any later version.
00010 *
00011 *    This program is distributed in the hope that it will be useful,
00012 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
00013 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00014 *    GNU General Public License for more details.
00015 *
00016 *    You should have received a copy of the GNU General Public License
00017 *    along with this program; if not, write to the Free Software
00018 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00019 *    02110-1301, USA.
00020 *
00021 *    Portions of this code based on:
00022 *       lan.c: Linux ThunderLan Driver:
00023 *
00024 *       by James Banks
00025 *
00026 *       (C) 1997-1998 Caldera, Inc.
00027 *       (C) 1998 James Banks
00028 *       (C) 1999-2001 Torben Mathiasen
00029 *       (C) 2002 Samuel Chessman
00030 *
00031 *    REVISION HISTORY:
00032 *    ================
00033 *    v1.0       07-08-2003      timlegge        Initial not quite working version
00034 *    v1.1       07-27-2003      timlegge        Sync 5.0 and 5.1 versions
00035 *    v1.2       08-19-2003      timlegge        Implement Multicast Support
00036 *    v1.3       08-23-2003      timlegge        Fix the transmit Function
00037 *    v1.4       01-17-2004      timlegge        Initial driver output cleanup    
00038 *    
00039 *    Indent Options: indent -kr -i8
00040 ***************************************************************************/
00041 
00042 FILE_LICENCE ( GPL2_OR_LATER );
00043 
00044 #include "etherboot.h"
00045 #include "nic.h"
00046 #include <ipxe/pci.h>
00047 #include <ipxe/ethernet.h>
00048 #include <mii.h>
00049 #include "tlan.h"
00050 
00051 #define drv_version "v1.4"
00052 #define drv_date "01-17-2004"
00053 
00054 /* NIC specific static variables go here */
00055 #define HZ 100
00056 #define TX_TIME_OUT       (6*HZ)
00057 
00058 /* Condensed operations for readability. */
00059 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
00060 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
00061 
00062 static void TLan_ResetLists(struct nic *nic __unused);
00063 static void TLan_ResetAdapter(struct nic *nic __unused);
00064 static void TLan_FinishReset(struct nic *nic __unused);
00065 
00066 static void TLan_EeSendStart(u16);
00067 static int TLan_EeSendByte(u16, u8, int);
00068 static void TLan_EeReceiveByte(u16, u8 *, int);
00069 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
00070 
00071 static void TLan_PhyDetect(struct nic *nic);
00072 static void TLan_PhyPowerDown(struct nic *nic);
00073 static void TLan_PhyPowerUp(struct nic *nic);
00074 
00075 
00076 static void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac);
00077 
00078 static void TLan_PhyReset(struct nic *nic);
00079 static void TLan_PhyStartLink(struct nic *nic);
00080 static void TLan_PhyFinishAutoNeg(struct nic *nic);
00081 
00082 #ifdef MONITOR
00083 static void TLan_PhyMonitor(struct nic *nic);
00084 #endif
00085 
00086 
00087 static void refill_rx(struct nic *nic __unused);
00088 
00089 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
00090 static void TLan_MiiSendData(u16, u32, unsigned);
00091 static void TLan_MiiSync(u16);
00092 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
00093 
00094 
00095 static const char *media[] = {
00096         "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
00097         "100baseTx-FD", "100baseT4", NULL
00098 };
00099 
00100 /* This much match tlan_pci_tbl[]!  */
00101 enum tlan_nics {
00102         NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
00103             4, NETEL100PI = 5,
00104         NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
00105             10, NETELLIGENT_10_100_WS_5100 = 11,
00106         NETELLIGENT_10_T2 = 12
00107 };
00108 
00109 struct pci_id_info {
00110         const char *name;
00111         int nic_id;
00112         struct match_info {
00113                 u32 pci, pci_mask, subsystem, subsystem_mask;
00114                 u32 revision, revision_mask;    /* Only 8 bits. */
00115         } id;
00116         u32 flags;
00117         u16 addrOfs;            /* Address Offset */
00118 };
00119 
00120 static const struct pci_id_info tlan_pci_tbl[] = {
00121         {"Compaq Netelligent 10 T PCI UTP", NETEL10,
00122          {0xae340e11, 0xffffffff, 0, 0, 0, 0},
00123          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
00124         {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
00125          {0xae320e11, 0xffffffff, 0, 0, 0, 0},
00126          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
00127         {"Compaq Integrated NetFlex-3/P", NETFLEX3I,
00128          {0xae350e11, 0xffffffff, 0, 0, 0, 0},
00129          TLAN_ADAPTER_NONE, 0x83},
00130         {"Compaq NetFlex-3/P", THUNDER,
00131          {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
00132          TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
00133         {"Compaq NetFlex-3/P", NETFLEX3B,
00134          {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
00135          TLAN_ADAPTER_NONE, 0x83},
00136         {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
00137          {0xae430e11, 0xffffffff, 0, 0, 0, 0},
00138          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
00139         {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
00140          {0xae400e11, 0xffffffff, 0, 0, 0, 0},
00141          TLAN_ADAPTER_NONE, 0x83},
00142         {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
00143          {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
00144          TLAN_ADAPTER_NONE, 0x83},
00145         {"Olicom OC-2183/2185", OC2183,
00146          {0x0013108d, 0xffffffff, 0, 0, 0, 0},
00147          TLAN_ADAPTER_USE_INTERN_10, 0x83},
00148         {"Olicom OC-2325", OC2325,
00149          {0x0012108d, 0xffffffff, 0, 0, 0, 0},
00150          TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
00151         {"Olicom OC-2326", OC2326,
00152          {0x0014108d, 0xffffffff, 0, 0, 0, 0},
00153          TLAN_ADAPTER_USE_INTERN_10, 0xF8},
00154         {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
00155          {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
00156          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
00157         {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
00158          {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
00159          TLAN_ADAPTER_NONE, 0x83},
00160         {"Compaq NetFlex-3/E", 0,       /* EISA card */
00161          {0, 0, 0, 0, 0, 0},
00162          TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
00163          TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
00164         {"Compaq NetFlex-3/E", 0,       /* EISA card */
00165          {0, 0, 0, 0, 0, 0},
00166          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
00167         {NULL, 0,
00168          {0, 0, 0, 0, 0, 0},
00169          0, 0},
00170 };
00171 
00172 struct TLanList {
00173         u32 forward;
00174         u16 cStat;
00175         u16 frameSize;
00176         struct {
00177                 u32 count;
00178                 u32 address;
00179         } buffer[TLAN_BUFFERS_PER_LIST];
00180 };
00181 
00182 struct {
00183         struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
00184         unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
00185         struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
00186         unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
00187 } tlan_buffers __shared;
00188 #define tx_ring tlan_buffers.tx_ring
00189 #define txb tlan_buffers.txb
00190 #define rx_ring tlan_buffers.rx_ring
00191 #define rxb tlan_buffers.rxb
00192 
00193 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
00194 
00195 static int chip_idx;
00196 
00197 /*****************************************************************
00198 * TLAN Private Information Structure
00199 *
00200 ****************************************************************/
00201 static struct tlan_private {
00202         unsigned short vendor_id;       /* PCI Vendor code */
00203         unsigned short dev_id;  /* PCI Device code */
00204         const char *nic_name;
00205         unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indices */
00206         unsigned rx_buf_sz;     /* Based on mtu + Slack */
00207         struct TLanList *txList;
00208         u32 txHead;
00209         u32 txInProgress;
00210         u32 txTail;
00211         int eoc;
00212         u32 phyOnline;
00213         u32 aui;
00214         u32 duplex;
00215         u32 phy[2];
00216         u32 phyNum;
00217         u32 speed;
00218         u8 tlanRev;
00219         u8 tlanFullDuplex;
00220         u8 link;
00221         u8 neg_be_verbose;
00222 } TLanPrivateInfo;
00223 
00224 static struct tlan_private *priv;
00225 
00226 static u32 BASE;
00227 
00228 /***************************************************************
00229 *       TLan_ResetLists
00230 *
00231 *       Returns:
00232 *               Nothing
00233 *       Parms:
00234 *               dev     The device structure with the list
00235 *                       stuctures to be reset.
00236 *
00237 *       This routine sets the variables associated with managing
00238 *       the TLAN lists to their initial values.
00239 *
00240 **************************************************************/
00241 
00242 static void TLan_ResetLists(struct nic *nic __unused)
00243 {
00244 
00245         int i;
00246         struct TLanList *list;
00247         priv->txHead = 0;
00248         priv->txTail = 0;
00249 
00250         for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
00251                 list = &tx_ring[i];
00252                 list->cStat = TLAN_CSTAT_UNUSED;
00253                 list->buffer[0].address = virt_to_bus(txb + 
00254                                 (i * TLAN_MAX_FRAME_SIZE)); 
00255                 list->buffer[2].count = 0;
00256                 list->buffer[2].address = 0;
00257                 list->buffer[9].address = 0;
00258         }
00259 
00260         priv->cur_rx = 0;
00261         priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
00262 //      priv->rx_head_desc = &rx_ring[0];
00263 
00264         /* Initialize all the Rx descriptors */
00265         for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
00266                 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
00267                 rx_ring[i].cStat = TLAN_CSTAT_READY;
00268                 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
00269                 rx_ring[i].buffer[0].count =
00270                     TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
00271                 rx_ring[i].buffer[0].address =
00272                     virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
00273                 rx_ring[i].buffer[1].count = 0;
00274                 rx_ring[i].buffer[1].address = 0;
00275         }
00276 
00277         /* Mark the last entry as wrapping the ring */
00278         rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
00279         priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
00280 
00281 } /* TLan_ResetLists */
00282 
00283 /***************************************************************
00284 *       TLan_Reset
00285 *
00286 *       Returns:
00287 *               0
00288 *       Parms:
00289 *               dev     Pointer to device structure of adapter
00290 *                       to be reset.
00291 *
00292 *       This function resets the adapter and it's physical
00293 *       device.  See Chap. 3, pp. 9-10 of the "ThunderLAN
00294 *       Programmer's Guide" for details.  The routine tries to
00295 *       implement what is detailed there, though adjustments
00296 *       have been made.
00297 *
00298 **************************************************************/
00299 
00300 void TLan_ResetAdapter(struct nic *nic __unused)
00301 {
00302         int i;
00303         u32 addr;
00304         u32 data;
00305         u8 data8;
00306 
00307         priv->tlanFullDuplex = FALSE;
00308         priv->phyOnline = 0;
00309 /*  1.  Assert reset bit. */
00310 
00311         data = inl(BASE + TLAN_HOST_CMD);
00312         data |= TLAN_HC_AD_RST;
00313         outl(data, BASE + TLAN_HOST_CMD);
00314 
00315         udelay(1000);
00316 
00317 /*  2.  Turn off interrupts. ( Probably isn't necessary ) */
00318 
00319         data = inl(BASE + TLAN_HOST_CMD);
00320         data |= TLAN_HC_INT_OFF;
00321         outl(data, BASE + TLAN_HOST_CMD);
00322 /*  3.  Clear AREGs and HASHs. */
00323 
00324         for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
00325                 TLan_DioWrite32(BASE, (u16) i, 0);
00326         }
00327 
00328 /*  4.  Setup NetConfig register. */
00329 
00330         data =
00331             TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
00332         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
00333 
00334 /*  5.  Load Ld_Tmr and Ld_Thr in HOST_CMD. */
00335 
00336         outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
00337         outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
00338 
00339 /*  6.  Unreset the MII by setting NMRST (in NetSio) to 1. */
00340 
00341         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
00342         addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
00343         TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
00344 
00345 /*  7.  Setup the remaining registers. */
00346 
00347         if (priv->tlanRev >= 0x30) {
00348                 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
00349                 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
00350         }
00351         TLan_PhyDetect(nic);
00352         data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
00353 
00354         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
00355                 data |= TLAN_NET_CFG_BIT;
00356                 if (priv->aui == 1) {
00357                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
00358                 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
00359                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
00360                         priv->tlanFullDuplex = TRUE;
00361                 } else {
00362                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
00363                 }
00364         }
00365 
00366         if (priv->phyNum == 0) {
00367                 data |= TLAN_NET_CFG_PHY_EN;
00368         }
00369         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
00370 
00371         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
00372                 TLan_FinishReset(nic);
00373         } else {
00374                 TLan_PhyPowerDown(nic);
00375         }
00376 
00377 }       /* TLan_ResetAdapter */
00378 
00379 void TLan_FinishReset(struct nic *nic)
00380 {
00381 
00382         u8 data;
00383         u32 phy;
00384         u8 sio;
00385         u16 status;
00386         u16 partner;
00387         u16 tlphy_ctl;
00388         u16 tlphy_par;
00389         u16 tlphy_id1, tlphy_id2;
00390         int i;
00391 
00392         phy = priv->phy[priv->phyNum];
00393 
00394         data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
00395         if (priv->tlanFullDuplex) {
00396                 data |= TLAN_NET_CMD_DUPLEX;
00397         }
00398         TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
00399         data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
00400         if (priv->phyNum == 0) {
00401                 data |= TLAN_NET_MASK_MASK7;
00402         }
00403         TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
00404         TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
00405         TLan_MiiReadReg(nic, phy, MII_PHYSID1, &tlphy_id1);
00406         TLan_MiiReadReg(nic, phy, MII_PHYSID2, &tlphy_id2);
00407 
00408         if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
00409             || (priv->aui)) {
00410                 status = BMSR_LSTATUS;
00411                 DBG ( "TLAN:  %s: Link forced.\n", priv->nic_name );
00412         } else {
00413                 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
00414                 udelay(1000);
00415                 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
00416                 if ((status & BMSR_LSTATUS) &&  /* We only support link info on Nat.Sem. PHY's */
00417                     (tlphy_id1 == NAT_SEM_ID1)
00418                     && (tlphy_id2 == NAT_SEM_ID2)) {
00419                         TLan_MiiReadReg(nic, phy, MII_LPA, &partner);
00420                         TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
00421                                         &tlphy_par);
00422 
00423                         DBG ( "TLAN: %s: Link active with ",
00424                                priv->nic_name );
00425                         if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
00426                                 DBG ( "forced 10%sMbps %s-Duplex\n",
00427                                        tlphy_par & TLAN_PHY_SPEED_100 ? ""
00428                                        : "0",
00429                                        tlphy_par & TLAN_PHY_DUPLEX_FULL ?
00430                                        "Full" : "Half" );
00431                         } else {
00432                                 DBG 
00433                                     ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
00434                                      tlphy_par & TLAN_PHY_SPEED_100 ? "" :
00435                                      "0",
00436                                      tlphy_par & TLAN_PHY_DUPLEX_FULL ?
00437                                      "Full" : "Half" );
00438                                 DBG ( "TLAN: Partner capability: " );
00439                                 for (i = 5; i <= 10; i++)
00440                                         if (partner & (1 << i)) {
00441                                                 DBG ( "%s", media[i - 5] );
00442                                         }
00443                                 DBG ( "\n" );
00444                         }
00445 
00446                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
00447 #ifdef MONITOR
00448                         /* We have link beat..for now anyway */
00449                         priv->link = 1;
00450                         /*Enabling link beat monitoring */
00451                         /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
00452                         mdelay(10000);
00453                         TLan_PhyMonitor(nic);
00454 #endif
00455                 } else if (status & BMSR_LSTATUS) {
00456                         DBG ( "TLAN: %s: Link active\n", priv->nic_name );
00457                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
00458                 }
00459         }
00460 
00461         if (priv->phyNum == 0) {
00462                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
00463                 tlphy_ctl |= TLAN_TC_INTEN;
00464                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
00465                 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
00466                 sio |= TLAN_NET_SIO_MINTEN;
00467                 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
00468         }
00469 
00470         if (status & BMSR_LSTATUS) {
00471                 TLan_SetMac(nic, 0, nic->node_addr);
00472                 priv->phyOnline = 1;
00473                 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
00474                 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
00475                 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
00476         } else {
00477                 DBG 
00478                     ( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
00479                      priv->nic_name );
00480                 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
00481                 mdelay(10000);
00482                 TLan_FinishReset(nic);
00483                 return;
00484 
00485         }
00486 
00487 }       /* TLan_FinishReset */
00488 
00489 /**************************************************************************
00490 POLL - Wait for a frame
00491 ***************************************************************************/
00492 static int tlan_poll(struct nic *nic, int retrieve)
00493 {
00494         /* return true if there's an ethernet packet ready to read */
00495         /* nic->packet should contain data on return */
00496         /* nic->packetlen should contain length of data */
00497         u32 framesize;
00498         u32 host_cmd = 0;
00499         u32 ack = 1;
00500         int eoc = 0;
00501         int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
00502         u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
00503         u16 host_int = inw(BASE + TLAN_HOST_INT);
00504 
00505         if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
00506           return 1;
00507 
00508         outw(host_int, BASE + TLAN_HOST_INT);
00509 
00510         if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
00511                 return 0;
00512 
00513         /* printf("PI-1: 0x%hX\n", host_int); */
00514         if (tmpCStat & TLAN_CSTAT_EOC)
00515                 eoc = 1;
00516 
00517         framesize = rx_ring[entry].frameSize;
00518 
00519         nic->packetlen = framesize;
00520 
00521         DBG ( ".%d.", (unsigned int) framesize ); 
00522      
00523         memcpy(nic->packet, rxb +
00524                (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
00525 
00526         rx_ring[entry].cStat = 0;
00527 
00528         DBG ( "%d", entry );  
00529 
00530         entry = (entry + 1) % TLAN_NUM_RX_LISTS;
00531         priv->cur_rx = entry;
00532         if (eoc) {
00533                 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
00534                     TLAN_CSTAT_READY) {
00535                         ack |= TLAN_HC_GO | TLAN_HC_RT;
00536                         host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
00537                         outl(host_cmd, BASE + TLAN_HOST_CMD);
00538                 }
00539         } else {
00540                 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
00541                 outl(host_cmd, BASE + TLAN_HOST_CMD);
00542                 
00543                 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) ); 
00544                 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
00545         }
00546         refill_rx(nic);
00547         return (1);             /* initially as this is called to flush the input */
00548 }
00549 
00550 static void refill_rx(struct nic *nic __unused)
00551 {
00552         int entry = 0;
00553 
00554         for (;
00555              (priv->cur_rx - priv->dirty_rx +
00556               TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
00557              priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
00558                 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
00559                 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
00560                 rx_ring[entry].cStat = TLAN_CSTAT_READY;
00561         }
00562 
00563 }
00564 
00565 /**************************************************************************
00566 TRANSMIT - Transmit a frame
00567 ***************************************************************************/
00568 static void tlan_transmit(struct nic *nic, const char *d,       /* Destination */
00569                           unsigned int t,       /* Type */
00570                           unsigned int s,       /* size */
00571                           const char *p)
00572 {                               /* Packet */
00573         u16 nstype;
00574         u32 to;
00575         struct TLanList *tail_list;
00576         struct TLanList *head_list;
00577         u8 *tail_buffer;
00578         u32 ack = 0;
00579         u32 host_cmd;
00580         int eoc = 0;
00581         u16 tmpCStat;
00582         u16 host_int = inw(BASE + TLAN_HOST_INT);
00583 
00584         int entry = 0;
00585 
00586         DBG ( "INT0-0x%hX\n", host_int );
00587 
00588         if (!priv->phyOnline) {
00589                 printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
00590                 return;
00591         }
00592 
00593         tail_list = priv->txList + priv->txTail;
00594 
00595         if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
00596                 printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n",
00597                        priv->nic_name, priv->txList, (unsigned int) priv->txTail);
00598                 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
00599 //              priv->txBusyCount++;
00600                 return;
00601         }
00602 
00603         tail_list->forward = 0;
00604 
00605         tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
00606 
00607         /* send the packet to destination */
00608         memcpy(tail_buffer, d, ETH_ALEN);
00609         memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
00610         nstype = htons((u16) t);
00611         memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
00612         memcpy(tail_buffer + ETH_HLEN, p, s);
00613 
00614         s += ETH_HLEN;
00615         s &= 0x0FFF;
00616         while (s < ETH_ZLEN)
00617                 tail_buffer[s++] = '\0';
00618 
00619         /*=====================================================*/
00620         /* Receive
00621          * 0000 0000 0001 1100
00622          * 0000 0000 0000 1100
00623          * 0000 0000 0000 0011 = 0x0003
00624          *
00625          * 0000 0000 0000 0000 0000 0000 0000 0011
00626          * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
00627          *
00628          * Transmit
00629          * 0000 0000 0001 1100
00630          * 0000 0000 0000 0100
00631          * 0000 0000 0000 0001 = 0x0001
00632          *
00633          * 0000 0000 0000 0000 0000 0000 0000 0001
00634          * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
00635          * */
00636 
00637         /* Setup the transmit descriptor */
00638         tail_list->frameSize = (u16) s;
00639         tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
00640         tail_list->buffer[1].count = 0;
00641         tail_list->buffer[1].address = 0;
00642 
00643         tail_list->cStat = TLAN_CSTAT_READY;
00644 
00645         DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
00646 
00647         if (!priv->txInProgress) {
00648                 priv->txInProgress = 1;
00649                 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
00650                 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
00651         } else {
00652                 if (priv->txTail == 0) {
00653                         DBG ( "Out buffer\n" );
00654                         (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
00655                             virt_to_le32desc(tail_list);
00656                 } else {
00657                         DBG ( "Fix this \n" );
00658                         (priv->txList + (priv->txTail - 1))->forward =
00659                             virt_to_le32desc(tail_list);
00660                 }
00661         }
00662         
00663         CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
00664 
00665         DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
00666 
00667         to = currticks() + TX_TIME_OUT;
00668         while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
00669 
00670         head_list = priv->txList + priv->txHead;
00671         while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) 
00672                         && (ack < 255)) {
00673                 ack++;
00674                 if(tmpCStat & TLAN_CSTAT_EOC)
00675                         eoc =1;
00676                 head_list->cStat = TLAN_CSTAT_UNUSED;
00677                 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
00678                 head_list = priv->txList + priv->txHead;
00679                 
00680         }
00681         if(!ack)
00682                 printf("Incomplete TX Frame\n");
00683 
00684         if(eoc) {
00685                 head_list = priv->txList + priv->txHead;
00686                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
00687                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
00688                         ack |= TLAN_HC_GO;
00689                 } else {
00690                         priv->txInProgress = 0;
00691                 }
00692         }
00693         if(ack) {
00694                 host_cmd = TLAN_HC_ACK | ack;
00695                 outl(host_cmd, BASE + TLAN_HOST_CMD);
00696         }
00697         
00698         if(priv->tlanRev < 0x30 ) {
00699                 ack = 1;
00700                 head_list = priv->txList + priv->txHead;
00701                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
00702                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
00703                         ack |= TLAN_HC_GO;
00704                 } else {
00705                         priv->txInProgress = 0;
00706                 }
00707                 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
00708                 outl(host_cmd, BASE + TLAN_HOST_CMD);
00709                 
00710         }
00711                         
00712         if (currticks() >= to) {
00713                 printf("TX Time Out");
00714         }
00715 }
00716 
00717 /**************************************************************************
00718 DISABLE - Turn off ethernet interface
00719 ***************************************************************************/
00720 static void tlan_disable ( struct nic *nic __unused ) {
00721         /* put the card in its initial state */
00722         /* This function serves 3 purposes.
00723          * This disables DMA and interrupts so we don't receive
00724          *  unexpected packets or interrupts from the card after
00725          *  etherboot has finished.
00726          * This frees resources so etherboot may use
00727          *  this driver on another interface
00728          * This allows etherboot to reinitialize the interface
00729          *  if something is something goes wrong.
00730          *
00731          */
00732         outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
00733 }
00734 
00735 /**************************************************************************
00736 IRQ - Enable, Disable, or Force interrupts
00737 ***************************************************************************/
00738 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
00739 {
00740   switch ( action ) {
00741   case DISABLE :
00742     break;
00743   case ENABLE :
00744     break;
00745   case FORCE :
00746     break;
00747   }
00748 }
00749 
00750 static struct nic_operations tlan_operations = {
00751         .connect        = dummy_connect,
00752         .poll           = tlan_poll,
00753         .transmit       = tlan_transmit,
00754         .irq            = tlan_irq,
00755 
00756 };
00757 
00758 static void TLan_SetMulticastList(struct nic *nic) {
00759         int i;
00760         u8 tmp;
00761 
00762         /* !IFF_PROMISC */
00763         tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
00764         TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
00765 
00766         /* IFF_ALLMULTI */
00767         for(i = 0; i< 3; i++)
00768                 TLan_SetMac(nic, i + 1, NULL);
00769         TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
00770         TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
00771 
00772         
00773 }
00774 /**************************************************************************
00775 PROBE - Look for an adapter, this routine's visible to the outside
00776 ***************************************************************************/
00777 
00778 #define board_found 1
00779 #define valid_link 0
00780 static int tlan_probe ( struct nic *nic, struct pci_device *pci ) {
00781 
00782         u16 data = 0;
00783         int err;
00784         int i;
00785 
00786         if (pci->ioaddr == 0)
00787                 return 0;
00788 
00789         nic->irqno  = 0;
00790         nic->ioaddr = pci->ioaddr;
00791 
00792         BASE = pci->ioaddr;
00793 
00794         /* Set nic as PCI bus master */
00795         adjust_pci_device(pci);
00796         
00797         /* Point to private storage */
00798         priv = &TLanPrivateInfo;
00799 
00800         /* Figure out which chip we're dealing with */
00801         i = 0;
00802         chip_idx = -1;
00803         while (tlan_pci_tbl[i].name) {
00804                 if ((((u32) pci->device << 16) | pci->vendor) ==
00805                     (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
00806                         chip_idx = i;
00807                         break;
00808                 }
00809                 i++;
00810         }
00811         if (chip_idx == -1)
00812                 return 0;
00813 
00814         priv->vendor_id = pci->vendor;
00815         priv->dev_id = pci->device;
00816         priv->nic_name = pci->id->name;
00817         priv->eoc = 0;
00818 
00819         err = 0;
00820         for (i = 0; i < 6; i++)
00821                 err |= TLan_EeReadByte(BASE,
00822                                        (u8) tlan_pci_tbl[chip_idx].
00823                                        addrOfs + i,
00824                                        (u8 *) & nic->node_addr[i]);
00825         if (err) {
00826             printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n",
00827                     pci->id->name, err);
00828         } else {
00829             DBG ( "%s: %s at ioaddr %#lX, ", 
00830                   pci->id->name, eth_ntoa ( nic->node_addr ), pci->ioaddr );
00831         }
00832 
00833         priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
00834         printf("revision: 0x%hX\n", priv->tlanRev);
00835 
00836         TLan_ResetLists(nic);
00837         TLan_ResetAdapter(nic);
00838 
00839         data = inl(BASE + TLAN_HOST_CMD);
00840         data |= TLAN_HC_INT_OFF;
00841         outw(data, BASE + TLAN_HOST_CMD);
00842 
00843         TLan_SetMulticastList(nic);
00844         udelay(100); 
00845         priv->txList = tx_ring;
00846 
00847 /*      if (board_found && valid_link)
00848         {*/
00849         /* point to NIC specific routines */
00850         nic->nic_op     = &tlan_operations;
00851         return 1;
00852 }
00853 
00854 
00855 /*****************************************************************************
00856 ******************************************************************************
00857 
00858         ThunderLAN Driver Eeprom routines
00859 
00860         The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
00861         EEPROM.  These functions are based on information in Microchip's
00862         data sheet.  I don't know how well this functions will work with
00863         other EEPROMs.
00864 
00865 ******************************************************************************
00866 *****************************************************************************/
00867 
00868 
00869 /***************************************************************
00870 *       TLan_EeSendStart
00871 *
00872 *       Returns:
00873 *               Nothing
00874 *       Parms:
00875 *               io_base         The IO port base address for the
00876 *                               TLAN device with the EEPROM to
00877 *                               use.
00878 *
00879 *       This function sends a start cycle to an EEPROM attached
00880 *       to a TLAN chip.
00881 *
00882 **************************************************************/
00883 
00884 void TLan_EeSendStart(u16 io_base)
00885 {
00886         u16 sio;
00887 
00888         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
00889         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
00890 
00891         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00892         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
00893         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
00894         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
00895         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00896 
00897 }       /* TLan_EeSendStart */
00898 
00899 /***************************************************************
00900 *       TLan_EeSendByte
00901 *
00902 *       Returns:
00903 *               If the correct ack was received, 0, otherwise 1
00904 *       Parms:  io_base         The IO port base address for the
00905 *                               TLAN device with the EEPROM to
00906 *                               use.
00907 *               data            The 8 bits of information to
00908 *                               send to the EEPROM.
00909 *               stop            If TLAN_EEPROM_STOP is passed, a
00910 *                               stop cycle is sent after the
00911 *                               byte is sent after the ack is
00912 *                               read.
00913 *
00914 *       This function sends a byte on the serial EEPROM line,
00915 *       driving the clock to send each bit. The function then
00916 *       reverses transmission direction and reads an acknowledge
00917 *       bit.
00918 *
00919 **************************************************************/
00920 
00921 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
00922 {
00923         int err;
00924         u8 place;
00925         u16 sio;
00926 
00927         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
00928         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
00929 
00930         /* Assume clock is low, tx is enabled; */
00931         for (place = 0x80; place != 0; place >>= 1) {
00932                 if (place & data)
00933                         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
00934                 else
00935                         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
00936                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00937                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00938         }
00939         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
00940         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00941         err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
00942         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00943         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
00944 
00945         if ((!err) && stop) {
00946                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
00947                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00948                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
00949         }
00950 
00951         return (err);
00952 
00953 }       /* TLan_EeSendByte */
00954 
00955 /***************************************************************
00956 *       TLan_EeReceiveByte
00957 *
00958 *       Returns:
00959 *               Nothing
00960 *       Parms:
00961 *               io_base         The IO port base address for the
00962 *                               TLAN device with the EEPROM to
00963 *                               use.
00964 *               data            An address to a char to hold the
00965 *                               data sent from the EEPROM.
00966 *               stop            If TLAN_EEPROM_STOP is passed, a
00967 *                               stop cycle is sent after the
00968 *                               byte is received, and no ack is
00969 *                               sent.
00970 *
00971 *       This function receives 8 bits of data from the EEPROM
00972 *       over the serial link.  It then sends and ack bit, or no
00973 *       ack and a stop bit.  This function is used to retrieve
00974 *       data after the address of a byte in the EEPROM has been
00975 *       sent.
00976 *
00977 **************************************************************/
00978 
00979 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
00980 {
00981         u8 place;
00982         u16 sio;
00983 
00984         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
00985         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
00986         *data = 0;
00987 
00988         /* Assume clock is low, tx is enabled; */
00989         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
00990         for (place = 0x80; place; place >>= 1) {
00991                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00992                 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
00993                         *data |= place;
00994                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00995         }
00996 
00997         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
00998         if (!stop) {
00999                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
01000                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
01001                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
01002         } else {
01003                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);   /* No ack = 1 (?) */
01004                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
01005                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
01006                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
01007                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
01008                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
01009         }
01010 
01011 }       /* TLan_EeReceiveByte */
01012 
01013 /***************************************************************
01014 *       TLan_EeReadByte
01015 *
01016 *       Returns:
01017 *               No error = 0, else, the stage at which the error
01018 *               occurred.
01019 *       Parms:
01020 *               io_base         The IO port base address for the
01021 *                               TLAN device with the EEPROM to
01022 *                               use.
01023 *               ee_addr         The address of the byte in the
01024 *                               EEPROM whose contents are to be
01025 *                               retrieved.
01026 *               data            An address to a char to hold the
01027 *                               data obtained from the EEPROM.
01028 *
01029 *       This function reads a byte of information from an byte
01030 *       cell in the EEPROM.
01031 *
01032 **************************************************************/
01033 
01034 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
01035 {
01036         int err;
01037         int ret = 0;
01038 
01039 
01040         TLan_EeSendStart(io_base);
01041         err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
01042         if (err) {
01043                 ret = 1;
01044                 goto fail;
01045         }
01046         err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
01047         if (err) {
01048                 ret = 2;
01049                 goto fail;
01050         }
01051         TLan_EeSendStart(io_base);
01052         err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
01053         if (err) {
01054                 ret = 3;
01055                 goto fail;
01056         }
01057         TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
01058       fail:
01059 
01060         return ret;
01061 
01062 }       /* TLan_EeReadByte */
01063 
01064 
01065 /*****************************************************************************
01066 ******************************************************************************
01067 
01068 ThunderLAN Driver MII Routines
01069 
01070 These routines are based on the information in Chap. 2 of the
01071 "ThunderLAN Programmer's Guide", pp. 15-24.
01072 
01073 ******************************************************************************
01074 *****************************************************************************/
01075 
01076 
01077 /***************************************************************
01078 *       TLan_MiiReadReg
01079 *
01080 *       Returns:
01081 *               0       if ack received ok
01082 *               1       otherwise.
01083 *
01084 *       Parms:
01085 *               dev             The device structure containing
01086 *                               The io address and interrupt count
01087 *                               for this device.
01088 *               phy             The address of the PHY to be queried.
01089 *               reg             The register whose contents are to be
01090 *                               retrieved.
01091 *               val             A pointer to a variable to store the
01092 *                               retrieved value.
01093 *
01094 *       This function uses the TLAN's MII bus to retrieve the contents
01095 *       of a given register on a PHY.  It sends the appropriate info
01096 *       and then reads the 16-bit register value from the MII bus via
01097 *       the TLAN SIO register.
01098 *
01099 **************************************************************/
01100 
01101 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
01102 {
01103         u8 nack;
01104         u16 sio, tmp;
01105         u32 i;
01106         int err;
01107         int minten;
01108 
01109         err = FALSE;
01110         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
01111         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
01112 
01113         TLan_MiiSync(BASE);
01114 
01115         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
01116         if (minten)
01117                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
01118 
01119         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
01120         TLan_MiiSendData(BASE, 0x2, 2); /* Read  ( 10b ) */
01121         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
01122         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
01123 
01124 
01125         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
01126 
01127         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Clock Idle bit */
01128         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01129         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Wait 300ns */
01130 
01131         nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);    /* Check for ACK */
01132         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);    /* Finish ACK */
01133         if (nack) {             /* No ACK, so fake it */
01134                 for (i = 0; i < 16; i++) {
01135                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01136                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01137                 }
01138                 tmp = 0xffff;
01139                 err = TRUE;
01140         } else {                /* ACK, so read data */
01141                 for (tmp = 0, i = 0x8000; i; i >>= 1) {
01142                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01143                         if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
01144                                 tmp |= i;
01145                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01146                 }
01147         }
01148 
01149 
01150         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
01151         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01152 
01153         if (minten)
01154                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
01155 
01156         *val = tmp;
01157 
01158         return err;
01159 
01160 }                               /* TLan_MiiReadReg */
01161 
01162 /***************************************************************
01163 *       TLan_MiiSendData
01164 *
01165 *       Returns:
01166 *               Nothing
01167 *       Parms:
01168 *               base_port       The base IO port of the adapter in
01169 *                               question.
01170 *               dev             The address of the PHY to be queried.
01171 *               data            The value to be placed on the MII bus.
01172 *               num_bits        The number of bits in data that are to
01173 *                               be placed on the MII bus.
01174 *
01175 *       This function sends on sequence of bits on the MII
01176 *       configuration bus.
01177 *
01178 **************************************************************/
01179 
01180 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
01181 {
01182         u16 sio;
01183         u32 i;
01184 
01185         if (num_bits == 0)
01186                 return;
01187 
01188         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
01189         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
01190         TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
01191 
01192         for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
01193                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01194                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
01195                 if (data & i)
01196                         TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
01197                 else
01198                         TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
01199                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01200                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
01201         }
01202 
01203 }                               /* TLan_MiiSendData */
01204 
01205 /***************************************************************
01206 *       TLan_MiiSync
01207 *
01208 *       Returns:
01209 *               Nothing
01210 *       Parms:
01211 *               base_port       The base IO port of the adapter in
01212 *                               question.
01213 *
01214 *       This functions syncs all PHYs in terms of the MII configuration
01215 *       bus.
01216 *
01217 **************************************************************/
01218 
01219 void TLan_MiiSync(u16 base_port)
01220 {
01221         int i;
01222         u16 sio;
01223 
01224         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
01225         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
01226 
01227         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
01228         for (i = 0; i < 32; i++) {
01229                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01230                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01231         }
01232 
01233 }                               /* TLan_MiiSync */
01234 
01235 /***************************************************************
01236 *       TLan_MiiWriteReg
01237 *
01238 *       Returns:
01239 *               Nothing
01240 *       Parms:
01241 *               dev             The device structure for the device
01242 *                               to write to.
01243 *               phy             The address of the PHY to be written to.
01244 *               reg             The register whose contents are to be
01245 *                               written.
01246 *               val             The value to be written to the register.
01247 *
01248 *       This function uses the TLAN's MII bus to write the contents of a
01249 *       given register on a PHY.  It sends the appropriate info and then
01250 *       writes the 16-bit register value from the MII configuration bus
01251 *       via the TLAN SIO register.
01252 *
01253 **************************************************************/
01254 
01255 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
01256 {
01257         u16 sio;
01258         int minten;
01259 
01260         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
01261         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
01262 
01263         TLan_MiiSync(BASE);
01264 
01265         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
01266         if (minten)
01267                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
01268 
01269         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
01270         TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
01271         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
01272         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
01273 
01274         TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
01275         TLan_MiiSendData(BASE, val, 16);        /* Send Data */
01276 
01277         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
01278         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01279 
01280         if (minten)
01281                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
01282 
01283 
01284 }                               /* TLan_MiiWriteReg */
01285 
01286 /***************************************************************
01287 *       TLan_SetMac
01288 *
01289 *       Returns:
01290 *               Nothing
01291 *       Parms:
01292 *               dev     Pointer to device structure of adapter
01293 *                       on which to change the AREG.
01294 *               areg    The AREG to set the address in (0 - 3).
01295 *               mac     A pointer to an array of chars.  Each
01296 *                       element stores one byte of the address.
01297 *                       IE, it isn't in ascii.
01298 *
01299 *       This function transfers a MAC address to one of the
01300 *       TLAN AREGs (address registers).  The TLAN chip locks
01301 *       the register on writing to offset 0 and unlocks the
01302 *       register after writing to offset 5.  If NULL is passed
01303 *       in mac, then the AREG is filled with 0's.
01304 *
01305 **************************************************************/
01306 
01307 void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac)
01308 {
01309         int i;
01310 
01311         areg *= 6;
01312 
01313         if (mac != NULL) {
01314                 for (i = 0; i < 6; i++)
01315                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
01316                                        mac[i]);
01317         } else {
01318                 for (i = 0; i < 6; i++)
01319                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
01320         }
01321 
01322 }                               /* TLan_SetMac */
01323 
01324 /*********************************************************************
01325 *       TLan_PhyDetect
01326 *
01327 *       Returns:
01328 *               Nothing
01329 *       Parms:
01330 *               dev     A pointer to the device structure of the adapter
01331 *                       for which the PHY needs determined.
01332 *
01333 *       So far I've found that adapters which have external PHYs
01334 *       may also use the internal PHY for part of the functionality.
01335 *       (eg, AUI/Thinnet).  This function finds out if this TLAN
01336 *       chip has an internal PHY, and then finds the first external
01337 *       PHY (starting from address 0) if it exists).
01338 *
01339 ********************************************************************/
01340 
01341 void TLan_PhyDetect(struct nic *nic)
01342 {
01343         u16 control;
01344         u16 hi;
01345         u16 lo;
01346         u32 phy;
01347 
01348         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
01349                 priv->phyNum = 0xFFFF;
01350                 return;
01351         }
01352 
01353         TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_PHYSID1, &hi);
01354 
01355         if (hi != 0xFFFF) {
01356                 priv->phy[0] = TLAN_PHY_MAX_ADDR;
01357         } else {
01358                 priv->phy[0] = TLAN_PHY_NONE;
01359         }
01360 
01361         priv->phy[1] = TLAN_PHY_NONE;
01362         for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
01363                 TLan_MiiReadReg(nic, phy, MII_BMCR, &control);
01364                 TLan_MiiReadReg(nic, phy, MII_PHYSID1, &hi);
01365                 TLan_MiiReadReg(nic, phy, MII_PHYSID2, &lo);
01366                 if ((control != 0xFFFF) || (hi != 0xFFFF)
01367                     || (lo != 0xFFFF)) {
01368                         printf("PHY found at %hX %hX %hX %hX\n", 
01369                                (unsigned int) phy, control, hi, lo);
01370                         if ((priv->phy[1] == TLAN_PHY_NONE)
01371                             && (phy != TLAN_PHY_MAX_ADDR)) {
01372                                 priv->phy[1] = phy;
01373                         }
01374                 }
01375         }
01376 
01377         if (priv->phy[1] != TLAN_PHY_NONE) {
01378                 priv->phyNum = 1;
01379         } else if (priv->phy[0] != TLAN_PHY_NONE) {
01380                 priv->phyNum = 0;
01381         } else {
01382                 printf
01383                     ("TLAN:  Cannot initialize device, no PHY was found!\n");
01384         }
01385 
01386 }                               /* TLan_PhyDetect */
01387 
01388 void TLan_PhyPowerDown(struct nic *nic)
01389 {
01390 
01391         u16 value;
01392         DBG ( "%s: Powering down PHY(s).\n", priv->nic_name );
01393         value = BMCR_PDOWN | BMCR_LOOPBACK | BMCR_ISOLATE;
01394         TLan_MiiSync(BASE);
01395         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
01396         if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
01397             &&
01398             (!(tlan_pci_tbl[chip_idx].
01399                flags & TLAN_ADAPTER_USE_INTERN_10))) {
01400                 TLan_MiiSync(BASE);
01401                 TLan_MiiWriteReg(nic, priv->phy[1], MII_BMCR, value);
01402         }
01403 
01404         /* Wait for 50 ms and powerup
01405          * This is abitrary.  It is intended to make sure the
01406          * tranceiver settles.
01407          */
01408         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
01409         mdelay(50);
01410         TLan_PhyPowerUp(nic);
01411 
01412 }                               /* TLan_PhyPowerDown */
01413 
01414 
01415 void TLan_PhyPowerUp(struct nic *nic)
01416 {
01417         u16 value;
01418 
01419         DBG ( "%s: Powering up PHY.\n", priv->nic_name );
01420         TLan_MiiSync(BASE);
01421         value = BMCR_LOOPBACK;
01422         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
01423         TLan_MiiSync(BASE);
01424         /* Wait for 500 ms and reset the
01425          * tranceiver.  The TLAN docs say both 50 ms and
01426          * 500 ms, so do the longer, just in case.
01427          */
01428         mdelay(500);
01429         TLan_PhyReset(nic);
01430         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
01431 
01432 }                               /* TLan_PhyPowerUp */
01433 
01434 void TLan_PhyReset(struct nic *nic)
01435 {
01436         u16 phy;
01437         u16 value;
01438 
01439         phy = priv->phy[priv->phyNum];
01440 
01441         DBG ( "%s: Reseting PHY.\n", priv->nic_name );
01442         TLan_MiiSync(BASE);
01443         value = BMCR_LOOPBACK | BMCR_RESET;
01444         TLan_MiiWriteReg(nic, phy, MII_BMCR, value);
01445         TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
01446         while (value & BMCR_RESET) {
01447                 TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
01448         }
01449 
01450         /* Wait for 500 ms and initialize.
01451          * I don't remember why I wait this long.
01452          * I've changed this to 50ms, as it seems long enough.
01453          */
01454         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
01455         mdelay(50);
01456         TLan_PhyStartLink(nic);
01457 
01458 }                               /* TLan_PhyReset */
01459 
01460 
01461 void TLan_PhyStartLink(struct nic *nic)
01462 {
01463 
01464         u16 ability;
01465         u16 control;
01466         u16 data;
01467         u16 phy;
01468         u16 status;
01469         u16 tctl;
01470 
01471         phy = priv->phy[priv->phyNum];
01472         DBG ( "%s: Trying to activate link.\n", priv->nic_name );
01473         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
01474         TLan_MiiReadReg(nic, phy, MII_BMSR, &ability);
01475 
01476         if ((status & BMSR_ANEGCAPABLE) && (!priv->aui)) {
01477                 ability = status >> 11;
01478                 if (priv->speed == TLAN_SPEED_10 &&
01479                     priv->duplex == TLAN_DUPLEX_HALF) {
01480                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0000);
01481                 } else if (priv->speed == TLAN_SPEED_10 &&
01482                            priv->duplex == TLAN_DUPLEX_FULL) {
01483                         priv->tlanFullDuplex = TRUE;
01484                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0100);
01485                 } else if (priv->speed == TLAN_SPEED_100 &&
01486                            priv->duplex == TLAN_DUPLEX_HALF) {
01487                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2000);
01488                 } else if (priv->speed == TLAN_SPEED_100 &&
01489                            priv->duplex == TLAN_DUPLEX_FULL) {
01490                         priv->tlanFullDuplex = TRUE;
01491                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2100);
01492                 } else {
01493 
01494                         /* Set Auto-Neg advertisement */
01495                         TLan_MiiWriteReg(nic, phy, MII_ADVERTISE,
01496                                          (ability << 5) | 1);
01497                         /* Enablee Auto-Neg */
01498                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1000);
01499                         /* Restart Auto-Neg */
01500                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1200);
01501                         /* Wait for 4 sec for autonegotiation
01502                          * to complete.  The max spec time is less than this
01503                          * but the card need additional time to start AN.
01504                          * .5 sec should be plenty extra.
01505                          */
01506                         DBG ( "TLAN: %s: Starting autonegotiation.\n",
01507                                priv->nic_name );
01508                         mdelay(4000);
01509                         TLan_PhyFinishAutoNeg(nic);
01510                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
01511                         return;
01512                 }
01513 
01514         }
01515 
01516         if ((priv->aui) && (priv->phyNum != 0)) {
01517                 priv->phyNum = 0;
01518                 data =
01519                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
01520                     TLAN_NET_CFG_PHY_EN;
01521                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
01522                 mdelay(50);
01523                 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
01524                 TLan_PhyPowerDown(nic);
01525                 return;
01526         } else if (priv->phyNum == 0) {
01527                 control = 0;
01528                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
01529                 if (priv->aui) {
01530                         tctl |= TLAN_TC_AUISEL;
01531                 } else {
01532                         tctl &= ~TLAN_TC_AUISEL;
01533                         if (priv->duplex == TLAN_DUPLEX_FULL) {
01534                                 control |= BMCR_FULLDPLX;
01535                                 priv->tlanFullDuplex = TRUE;
01536                         }
01537                         if (priv->speed == TLAN_SPEED_100) {
01538                                 control |= BMCR_SPEED100;
01539                         }
01540                 }
01541                 TLan_MiiWriteReg(nic, phy, MII_BMCR, control);
01542                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
01543         }
01544 
01545         /* Wait for 2 sec to give the tranceiver time
01546          * to establish link.
01547          */
01548         /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
01549         mdelay(2000);
01550         TLan_FinishReset(nic);
01551 
01552 }                               /* TLan_PhyStartLink */
01553 
01554 void TLan_PhyFinishAutoNeg(struct nic *nic)
01555 {
01556 
01557         u16 an_adv;
01558         u16 an_lpa;
01559         u16 data;
01560         u16 mode;
01561         u16 phy;
01562         u16 status;
01563 
01564         phy = priv->phy[priv->phyNum];
01565 
01566         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
01567         udelay(1000);
01568         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
01569 
01570         if (!(status & BMSR_ANEGCOMPLETE)) {
01571                 /* Wait for 8 sec to give the process
01572                  * more time.  Perhaps we should fail after a while.
01573                  */
01574                 if (!priv->neg_be_verbose++) {
01575                         printf
01576                             ("TLAN:  Giving autonegotiation more time.\n");
01577                         printf
01578                             ("TLAN:  Please check that your adapter has\n");
01579                         printf
01580                             ("TLAN:  been properly connected to a HUB or Switch.\n");
01581                         printf
01582                             ("TLAN:  Trying to establish link in the background...\n");
01583                 }
01584                 mdelay(8000);
01585                 TLan_PhyFinishAutoNeg(nic);
01586                 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
01587                 return;
01588         }
01589 
01590         DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name );
01591         TLan_MiiReadReg(nic, phy, MII_ADVERTISE, &an_adv);
01592         TLan_MiiReadReg(nic, phy, MII_LPA, &an_lpa);
01593         mode = an_adv & an_lpa & 0x03E0;
01594         if (mode & 0x0100) {
01595                 printf("Full Duplex\n");
01596                 priv->tlanFullDuplex = TRUE;
01597         } else if (!(mode & 0x0080) && (mode & 0x0040)) {
01598                 priv->tlanFullDuplex = TRUE;
01599                 printf("Full Duplex\n");
01600         }
01601 
01602         if ((!(mode & 0x0180))
01603             && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
01604             && (priv->phyNum != 0)) {
01605                 priv->phyNum = 0;
01606                 data =
01607                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
01608                     TLAN_NET_CFG_PHY_EN;
01609                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
01610                 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
01611                 mdelay(400);
01612                 TLan_PhyPowerDown(nic);
01613                 return;
01614         }
01615 
01616         if (priv->phyNum == 0) {
01617                 if ((priv->duplex == TLAN_DUPLEX_FULL)
01618                     || (an_adv & an_lpa & 0x0040)) {
01619                         TLan_MiiWriteReg(nic, phy, MII_BMCR,
01620                                          BMCR_ANENABLE | BMCR_FULLDPLX);
01621                         DBG 
01622                             ( "TLAN:  Starting internal PHY with FULL-DUPLEX\n" );
01623                 } else {
01624                         TLan_MiiWriteReg(nic, phy, MII_BMCR,
01625                                          BMCR_ANENABLE);
01626                         DBG 
01627                             ( "TLAN:  Starting internal PHY with HALF-DUPLEX\n" );
01628                 }
01629         }
01630 
01631         /* Wait for 100 ms.  No reason in partiticular.
01632          */
01633         /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
01634         mdelay(100);
01635         TLan_FinishReset(nic);
01636 
01637 }                               /* TLan_PhyFinishAutoNeg */
01638 
01639 #ifdef MONITOR
01640 
01641 /*********************************************************************
01642 *
01643 *      TLan_phyMonitor
01644 *
01645 *      Returns:
01646 *              None
01647 *
01648 *      Params:
01649 *              dev             The device structure of this device.
01650 *
01651 *
01652 *      This function monitors PHY condition by reading the status
01653 *      register via the MII bus. This can be used to give info
01654 *      about link changes (up/down), and possible switch to alternate
01655 *      media.
01656 *
01657 ********************************************************************/
01658 
01659 void TLan_PhyMonitor(struct net_device *dev)
01660 {
01661         TLanPrivateInfo *priv = dev->priv;
01662         u16 phy;
01663         u16 phy_status;
01664 
01665         phy = priv->phy[priv->phyNum];
01666 
01667         /* Get PHY status register */
01668         TLan_MiiReadReg(nic, phy, MII_BMSR, &phy_status);
01669 
01670         /* Check if link has been lost */
01671         if (!(phy_status & BMSR_LSTATUS)) {
01672                 if (priv->link) {
01673                         priv->link = 0;
01674                         printf("TLAN: %s has lost link\n", priv->nic_name);
01675                         priv->flags &= ~IFF_RUNNING;
01676                         mdelay(2000);
01677                         TLan_PhyMonitor(nic);
01678                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
01679                         return;
01680                 }
01681         }
01682 
01683         /* Link restablished? */
01684         if ((phy_status & BMSR_LSTATUS) && !priv->link) {
01685                 priv->link = 1;
01686                 printf("TLAN: %s has reestablished link\n",
01687                        priv->nic_name);
01688                 priv->flags |= IFF_RUNNING;
01689         }
01690 
01691         /* Setup a new monitor */
01692         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
01693         mdelay(2000);
01694         TLan_PhyMonitor(nic);
01695 }
01696 
01697 #endif                          /* MONITOR */
01698 
01699 static struct pci_device_id tlan_nics[] = {
01700         PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
01701         PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0),
01702         PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0),
01703         PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
01704         PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
01705         PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
01706         PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0),
01707         PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0),
01708         PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
01709         PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0),
01710         PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0),
01711         PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
01712         PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
01713 };
01714 
01715 PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
01716 
01717 DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver,
01718          tlan_probe, tlan_disable );
01719 
01720 /*
01721  * Local variables:
01722  *  c-basic-offset: 8
01723  *  c-indent-level: 8
01724  *  tab-width: 8
01725  * End:
01726  */