iPXE
ath5k.c
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1 /*
2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
4  * Copyright (c) 2006 Devicescape Software, Inc.
5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7  *
8  * Modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
9  * Original from Linux kernel 2.6.30.
10  *
11  * All rights reserved.
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 1. Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer,
18  * without modification.
19  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
20  * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
21  * redistribution must be conditioned upon including a substantially
22  * similar Disclaimer requirement for further binary redistribution.
23  * 3. Neither the names of the above-listed copyright holders nor the names
24  * of any contributors may be used to endorse or promote products derived
25  * from this software without specific prior written permission.
26  *
27  * Alternatively, this software may be distributed under the terms of the
28  * GNU General Public License ("GPL") version 2 as published by the Free
29  * Software Foundation.
30  *
31  * NO WARRANTY
32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
35  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
36  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
37  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
40  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
42  * THE POSSIBILITY OF SUCH DAMAGES.
43  *
44  */
45 
46 FILE_LICENCE ( BSD3 );
47 
48 #include <stdlib.h>
49 #include <ipxe/malloc.h>
50 #include <ipxe/timer.h>
51 #include <ipxe/netdevice.h>
52 #include <ipxe/pci.h>
53 #include <ipxe/pci_io.h>
54 
55 #include "base.h"
56 #include "reg.h"
57 
58 #define ATH5K_CALIB_INTERVAL 10 /* Calibrate PHY every 10 seconds */
59 #define ATH5K_RETRIES 4 /* Number of times to retry packet sends */
60 #define ATH5K_DESC_ALIGN 16 /* Alignment for TX/RX descriptors */
61 
62 /******************\
63 * Internal defines *
64 \******************/
65 
66 /* Known PCI ids */
67 static struct pci_device_id ath5k_nics[] = {
68  PCI_ROM(0x168c, 0x0207, "ath5210e", "Atheros 5210 early", AR5K_AR5210),
69  PCI_ROM(0x168c, 0x0007, "ath5210", "Atheros 5210", AR5K_AR5210),
70  PCI_ROM(0x168c, 0x0011, "ath5311", "Atheros 5311 (AHB)", AR5K_AR5211),
71  PCI_ROM(0x168c, 0x0012, "ath5211", "Atheros 5211", AR5K_AR5211),
72  PCI_ROM(0x168c, 0x0013, "ath5212", "Atheros 5212", AR5K_AR5212),
73  PCI_ROM(0xa727, 0x0013, "ath5212c","3com Ath 5212", AR5K_AR5212),
74  PCI_ROM(0x10b7, 0x0013, "rdag675", "3com 3CRDAG675", AR5K_AR5212),
75  PCI_ROM(0x168c, 0x1014, "ath5212m", "Ath 5212 miniPCI", AR5K_AR5212),
76  PCI_ROM(0x168c, 0x0014, "ath5212x14", "Atheros 5212 x14", AR5K_AR5212),
77  PCI_ROM(0x168c, 0x0015, "ath5212x15", "Atheros 5212 x15", AR5K_AR5212),
78  PCI_ROM(0x168c, 0x0016, "ath5212x16", "Atheros 5212 x16", AR5K_AR5212),
79  PCI_ROM(0x168c, 0x0017, "ath5212x17", "Atheros 5212 x17", AR5K_AR5212),
80  PCI_ROM(0x168c, 0x0018, "ath5212x18", "Atheros 5212 x18", AR5K_AR5212),
81  PCI_ROM(0x168c, 0x0019, "ath5212x19", "Atheros 5212 x19", AR5K_AR5212),
82  PCI_ROM(0x168c, 0x001a, "ath2413", "Atheros 2413 Griffin", AR5K_AR5212),
83  PCI_ROM(0x168c, 0x001b, "ath5413", "Atheros 5413 Eagle", AR5K_AR5212),
84  PCI_ROM(0x168c, 0x001c, "ath5212e", "Atheros 5212 PCI-E", AR5K_AR5212),
85  PCI_ROM(0x168c, 0x001d, "ath2417", "Atheros 2417 Nala", AR5K_AR5212),
86 };
87 
88 #define ATH5K_SPMBL_NO 1
89 #define ATH5K_SPMBL_YES 2
90 #define ATH5K_SPMBL_BOTH 3
91 
92 static const struct {
96 } ath5k_rates[] = {
112  { 0, 0, 0 },
113 };
114 
115 #define ATH5K_NR_RATES 15
116 
117 /*
118  * Prototypes - PCI stack related functions
119  */
120 static int ath5k_probe(struct pci_device *pdev);
121 static void ath5k_remove(struct pci_device *pdev);
122 
123 struct pci_driver ath5k_pci_driver __pci_driver = {
124  .ids = ath5k_nics,
125  .id_count = sizeof(ath5k_nics) / sizeof(ath5k_nics[0]),
126  .probe = ath5k_probe,
127  .remove = ath5k_remove,
128 };
129 
130 
131 
132 /*
133  * Prototypes - MAC 802.11 stack related functions
134  */
135 static int ath5k_tx(struct net80211_device *dev, struct io_buffer *skb);
136 static int ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan);
137 static int ath5k_reset_wake(struct ath5k_softc *sc);
138 static int ath5k_start(struct net80211_device *dev);
139 static void ath5k_stop(struct net80211_device *dev);
140 static int ath5k_config(struct net80211_device *dev, int changed);
141 static void ath5k_poll(struct net80211_device *dev);
142 static void ath5k_irq(struct net80211_device *dev, int enable);
143 
145  .open = ath5k_start,
146  .close = ath5k_stop,
147  .transmit = ath5k_tx,
148  .poll = ath5k_poll,
149  .irq = ath5k_irq,
150  .config = ath5k_config,
151 };
152 
153 /*
154  * Prototypes - Internal functions
155  */
156 /* Attach detach */
157 static int ath5k_attach(struct net80211_device *dev);
158 static void ath5k_detach(struct net80211_device *dev);
159 /* Channel/mode setup */
160 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
161  struct net80211_channel *channels,
162  unsigned int mode,
163  unsigned int max);
164 static int ath5k_setup_bands(struct net80211_device *dev);
165 static int ath5k_chan_set(struct ath5k_softc *sc,
166  struct net80211_channel *chan);
167 static void ath5k_setcurmode(struct ath5k_softc *sc,
168  unsigned int mode);
169 static void ath5k_mode_setup(struct ath5k_softc *sc);
170 
171 /* Descriptor setup */
172 static int ath5k_desc_alloc(struct ath5k_softc *sc);
173 static void ath5k_desc_free(struct ath5k_softc *sc);
174 /* Buffers setup */
175 static int ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf);
176 static int ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf);
177 
178 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
179  struct ath5k_buf *bf)
180 {
181  if (!bf->iob)
182  return;
183 
184  net80211_tx_complete(sc->dev, bf->iob, 0, ECANCELED);
185  bf->iob = NULL;
186 }
187 
188 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc __unused,
189  struct ath5k_buf *bf)
190 {
191  free_iob(bf->iob);
192  bf->iob = NULL;
193 }
194 
195 /* Queues setup */
196 static int ath5k_txq_setup(struct ath5k_softc *sc,
197  int qtype, int subtype);
198 static void ath5k_txq_drainq(struct ath5k_softc *sc,
199  struct ath5k_txq *txq);
200 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
201 static void ath5k_txq_release(struct ath5k_softc *sc);
202 /* Rx handling */
203 static int ath5k_rx_start(struct ath5k_softc *sc);
204 static void ath5k_rx_stop(struct ath5k_softc *sc);
205 /* Tx handling */
206 static void ath5k_tx_processq(struct ath5k_softc *sc,
207  struct ath5k_txq *txq);
208 
209 /* Interrupt handling */
210 static int ath5k_init(struct ath5k_softc *sc);
211 static int ath5k_stop_hw(struct ath5k_softc *sc);
212 
213 static void ath5k_calibrate(struct ath5k_softc *sc);
214 
215 /* Filter */
216 static void ath5k_configure_filter(struct ath5k_softc *sc);
217 
218 /********************\
219 * PCI Initialization *
220 \********************/
221 
222 #if DBGLVL_MAX
223 static const char *
224 ath5k_chip_name(enum ath5k_srev_type type, u16 val)
225 {
226  const char *name = "xxxxx";
227  unsigned int i;
228 
229  for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
230  if (srev_names[i].sr_type != type)
231  continue;
232 
233  if ((val & 0xf0) == srev_names[i].sr_val)
234  name = srev_names[i].sr_name;
235 
236  if ((val & 0xff) == srev_names[i].sr_val) {
237  name = srev_names[i].sr_name;
238  break;
239  }
240  }
241 
242  return name;
243 }
244 #endif
245 
246 static int ath5k_probe(struct pci_device *pdev)
247 {
248  void *mem;
249  struct ath5k_softc *sc;
250  struct net80211_device *dev;
251  int ret;
252  u8 csz;
253 
254  adjust_pci_device(pdev);
255 
256  /*
257  * Cache line size is used to size and align various
258  * structures used to communicate with the hardware.
259  */
261  if (csz == 0) {
262  /*
263  * We must have this setup properly for rx buffer
264  * DMA to work so force a reasonable value here if it
265  * comes up zero.
266  */
267  csz = 16;
269  }
270  /*
271  * The default setting of latency timer yields poor results,
272  * set it to the value used by other systems. It may be worth
273  * tweaking this setting more.
274  */
276 
277  /*
278  * Disable the RETRY_TIMEOUT register (0x41) to keep
279  * PCI Tx retries from interfering with C3 CPU state.
280  */
281  pci_write_config_byte(pdev, 0x41, 0);
282 
283  mem = ioremap(pdev->membase, 0x10000);
284  if (!mem) {
285  DBG("ath5k: cannot remap PCI memory region\n");
286  ret = -EIO;
287  goto err;
288  }
289 
290  /*
291  * Allocate dev (net80211 main struct)
292  * and dev->priv (driver private data)
293  */
294  dev = net80211_alloc(sizeof(*sc));
295  if (!dev) {
296  DBG("ath5k: cannot allocate 802.11 device\n");
297  ret = -ENOMEM;
298  goto err_map;
299  }
300 
301  /* Initialize driver private data */
302  sc = dev->priv;
303  sc->dev = dev;
304  sc->pdev = pdev;
305 
306  sc->hwinfo = zalloc(sizeof(*sc->hwinfo));
307  if (!sc->hwinfo) {
308  DBG("ath5k: cannot allocate 802.11 hardware info structure\n");
309  ret = -ENOMEM;
310  goto err_free;
311  }
312 
313  sc->hwinfo->flags = NET80211_HW_RX_HAS_FCS;
314  sc->hwinfo->signal_type = NET80211_SIGNAL_DB;
315  sc->hwinfo->signal_max = 40; /* 35dB should give perfect 54Mbps */
316  sc->hwinfo->channel_change_time = 5000;
317 
318  /* Avoid working with the device until setup is complete */
319  sc->status |= ATH_STAT_INVALID;
320 
321  sc->iobase = mem;
322  sc->cachelsz = csz * 4; /* convert to bytes */
323 
324  DBG("ath5k: register base at %p (%08lx)\n", sc->iobase, pdev->membase);
325  DBG("ath5k: cache line size %d\n", sc->cachelsz);
326 
327  /* Set private data */
328  pci_set_drvdata(pdev, dev);
329  dev->netdev->dev = (struct device *)pdev;
330 
331  /* Initialize device */
332  ret = ath5k_hw_attach(sc, pdev->id->driver_data, &sc->ah);
333  if (ret)
334  goto err_free_hwinfo;
335 
336  /* Finish private driver data initialization */
337  ret = ath5k_attach(dev);
338  if (ret)
339  goto err_ah;
340 
341 #if DBGLVL_MAX
342  DBG("Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
343  ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
344  sc->ah->ah_mac_srev, sc->ah->ah_phy_revision);
345 
346  if (!sc->ah->ah_single_chip) {
347  /* Single chip radio (!RF5111) */
348  if (sc->ah->ah_radio_5ghz_revision &&
349  !sc->ah->ah_radio_2ghz_revision) {
350  /* No 5GHz support -> report 2GHz radio */
352  DBG("RF%s 2GHz radio found (0x%x)\n",
353  ath5k_chip_name(AR5K_VERSION_RAD,
356  /* No 2GHz support (5110 and some
357  * 5Ghz only cards) -> report 5Ghz radio */
358  } else if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B)) {
359  DBG("RF%s 5GHz radio found (0x%x)\n",
360  ath5k_chip_name(AR5K_VERSION_RAD,
363  /* Multiband radio */
364  } else {
365  DBG("RF%s multiband radio found (0x%x)\n",
366  ath5k_chip_name(AR5K_VERSION_RAD,
369  }
370  }
371  /* Multi chip radio (RF5111 - RF2111) ->
372  * report both 2GHz/5GHz radios */
373  else if (sc->ah->ah_radio_5ghz_revision &&
374  sc->ah->ah_radio_2ghz_revision) {
375  DBG("RF%s 5GHz radio found (0x%x)\n",
376  ath5k_chip_name(AR5K_VERSION_RAD,
379  DBG("RF%s 2GHz radio found (0x%x)\n",
380  ath5k_chip_name(AR5K_VERSION_RAD,
383  }
384  }
385 #endif
386 
387  /* Ready to go */
388  sc->status &= ~ATH_STAT_INVALID;
389 
390  return 0;
391 err_ah:
392  ath5k_hw_detach(sc->ah);
393 err_free_hwinfo:
394  free(sc->hwinfo);
395 err_free:
396  net80211_free(dev);
397 err_map:
398  iounmap(mem);
399 err:
400  return ret;
401 }
402 
403 static void ath5k_remove(struct pci_device *pdev)
404 {
405  struct net80211_device *dev = pci_get_drvdata(pdev);
406  struct ath5k_softc *sc = dev->priv;
407 
408  ath5k_detach(dev);
409  ath5k_hw_detach(sc->ah);
410  iounmap(sc->iobase);
411  free(sc->hwinfo);
413 }
414 
415 
416 /***********************\
417 * Driver Initialization *
418 \***********************/
419 
420 static int
422 {
423  struct ath5k_softc *sc = dev->priv;
424  struct ath5k_hw *ah = sc->ah;
425  int ret;
426 
427  /*
428  * Collect the channel list. The 802.11 layer
429  * is resposible for filtering this list based
430  * on settings like the phy mode and regulatory
431  * domain restrictions.
432  */
433  ret = ath5k_setup_bands(dev);
434  if (ret) {
435  DBG("ath5k: can't get channels\n");
436  goto err;
437  }
438 
439  /* NB: setup here so ath5k_rate_update is happy */
440  if (ah->ah_modes & AR5K_MODE_BIT_11A)
442  else
444 
445  /*
446  * Allocate tx+rx descriptors and populate the lists.
447  */
448  ret = ath5k_desc_alloc(sc);
449  if (ret) {
450  DBG("ath5k: can't allocate descriptors\n");
451  goto err;
452  }
453 
454  /*
455  * Allocate hardware transmit queues. Note that hw functions
456  * handle reseting these queues at the needed time.
457  */
459  if (ret) {
460  DBG("ath5k: can't setup xmit queue\n");
461  goto err_desc;
462  }
463 
464  sc->last_calib_ticks = currticks();
465 
466  ret = ath5k_eeprom_read_mac(ah, sc->hwinfo->hwaddr);
467  if (ret) {
468  DBG("ath5k: unable to read address from EEPROM: 0x%04x\n",
469  sc->pdev->device);
470  goto err_queues;
471  }
472 
473  memset(sc->bssidmask, 0xff, ETH_ALEN);
475 
476  ret = net80211_register(sc->dev, &ath5k_ops, sc->hwinfo);
477  if (ret) {
478  DBG("ath5k: can't register ieee80211 hw\n");
479  goto err_queues;
480  }
481 
482  return 0;
483 err_queues:
484  ath5k_txq_release(sc);
485 err_desc:
486  ath5k_desc_free(sc);
487 err:
488  return ret;
489 }
490 
491 static void
493 {
494  struct ath5k_softc *sc = dev->priv;
495 
497  ath5k_desc_free(sc);
498  ath5k_txq_release(sc);
499 }
500 
501 
502 
503 
504 /********************\
505 * Channel/mode setup *
506 \********************/
507 
508 /*
509  * Convert IEEE channel number to MHz frequency.
510  */
511 static inline short
512 ath5k_ieee2mhz(short chan)
513 {
514  if (chan < 14)
515  return 2407 + 5 * chan;
516  if (chan == 14)
517  return 2484;
518  if (chan < 27)
519  return 2212 + 20 * chan;
520  return 5000 + 5 * chan;
521 }
522 
523 static unsigned int
525  struct net80211_channel *channels,
526  unsigned int mode, unsigned int max)
527 {
528  unsigned int i, count, size, chfreq, freq, ch;
529 
530  if (!(ah->ah_modes & (1 << mode)))
531  return 0;
532 
533  switch (mode) {
534  case AR5K_MODE_11A:
535  case AR5K_MODE_11A_TURBO:
536  /* 1..220, but 2GHz frequencies are filtered by check_channel */
537  size = 220;
538  chfreq = CHANNEL_5GHZ;
539  break;
540  case AR5K_MODE_11B:
541  case AR5K_MODE_11G:
542  case AR5K_MODE_11G_TURBO:
543  size = 26;
544  chfreq = CHANNEL_2GHZ;
545  break;
546  default:
547  return 0;
548  }
549 
550  for (i = 0, count = 0; i < size && max > 0; i++) {
551  ch = i + 1 ;
552  freq = ath5k_ieee2mhz(ch);
553 
554  /* Check if channel is supported by the chipset */
555  if (!ath5k_channel_ok(ah, freq, chfreq))
556  continue;
557 
558  /* Write channel info and increment counter */
559  channels[count].center_freq = freq;
560  channels[count].maxpower = 0; /* use regulatory */
561  channels[count].band = (chfreq == CHANNEL_2GHZ) ?
563  switch (mode) {
564  case AR5K_MODE_11A:
565  case AR5K_MODE_11G:
566  channels[count].hw_value = chfreq | CHANNEL_OFDM;
567  break;
568  case AR5K_MODE_11A_TURBO:
569  case AR5K_MODE_11G_TURBO:
570  channels[count].hw_value = chfreq |
572  break;
573  case AR5K_MODE_11B:
574  channels[count].hw_value = CHANNEL_B;
575  }
576 
577  count++;
578  max--;
579  }
580 
581  return count;
582 }
583 
584 static int
586 {
587  struct ath5k_softc *sc = dev->priv;
588  struct ath5k_hw *ah = sc->ah;
589  int max_c, count_c = 0;
590  int i;
591  int band;
592 
593  max_c = sizeof(sc->hwinfo->channels) / sizeof(sc->hwinfo->channels[0]);
594 
595  /* 2GHz band */
597  /* G mode */
598  band = NET80211_BAND_2GHZ;
601 
602  for (i = 0; i < 12; i++)
603  sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate;
604  sc->hwinfo->nr_rates[band] = 12;
605 
606  sc->hwinfo->nr_channels =
608  AR5K_MODE_11G, max_c);
609  count_c = sc->hwinfo->nr_channels;
610  max_c -= count_c;
611  } else if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B) {
612  /* B mode */
613  band = NET80211_BAND_2GHZ;
616 
617  for (i = 0; i < 4; i++)
618  sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate;
619  sc->hwinfo->nr_rates[band] = 4;
620 
621  sc->hwinfo->nr_channels =
623  AR5K_MODE_11B, max_c);
624  count_c = sc->hwinfo->nr_channels;
625  max_c -= count_c;
626  }
627 
628  /* 5GHz band, A mode */
630  band = NET80211_BAND_5GHZ;
632  sc->hwinfo->modes |= NET80211_MODE_A;
633 
634  for (i = 0; i < 8; i++)
635  sc->hwinfo->rates[band][i] = ath5k_rates[i+4].bitrate;
636  sc->hwinfo->nr_rates[band] = 8;
637 
638  sc->hwinfo->nr_channels =
640  AR5K_MODE_11B, max_c);
641  count_c = sc->hwinfo->nr_channels;
642  max_c -= count_c;
643  }
644 
645  return 0;
646 }
647 
648 /*
649  * Set/change channels. If the channel is really being changed,
650  * it's done by reseting the chip. To accomplish this we must
651  * first cleanup any pending DMA, then restart stuff after a la
652  * ath5k_init.
653  */
654 static int
655 ath5k_chan_set(struct ath5k_softc *sc, struct net80211_channel *chan)
656 {
657  if (chan->center_freq != sc->curchan->center_freq ||
658  chan->hw_value != sc->curchan->hw_value) {
659  /*
660  * To switch channels clear any pending DMA operations;
661  * wait long enough for the RX fifo to drain, reset the
662  * hardware at the new frequency, and then re-enable
663  * the relevant bits of the h/w.
664  */
665  DBG2("ath5k: resetting for channel change (%d -> %d MHz)\n",
666  sc->curchan->center_freq, chan->center_freq);
667  return ath5k_reset(sc, chan);
668  }
669 
670  return 0;
671 }
672 
673 static void
674 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
675 {
676  sc->curmode = mode;
677 
678  if (mode == AR5K_MODE_11A) {
680  } else {
682  }
683 }
684 
685 static void
687 {
688  struct ath5k_hw *ah = sc->ah;
689  u32 rfilt;
690 
691  /* configure rx filter */
692  rfilt = sc->filter_flags;
693  ath5k_hw_set_rx_filter(ah, rfilt);
694 
697 
698  /* configure operational mode */
700 
702 }
703 
704 static inline int
706 {
707  int i;
708 
709  for (i = 0; i < ATH5K_NR_RATES; i++) {
710  if (ath5k_rates[i].hw_code == hw_rix)
711  return ath5k_rates[i].bitrate;
712  }
713 
714  DBG("ath5k: invalid rix %02x\n", hw_rix);
715  return 10; /* use lowest rate */
716 }
717 
719 {
720  int i;
721 
722  for (i = 0; i < ATH5K_NR_RATES; i++) {
723  if (ath5k_rates[i].bitrate == bitrate)
724  return ath5k_rates[i].hw_code;
725  }
726 
727  DBG("ath5k: invalid bitrate %d\n", bitrate);
728  return ATH5K_RATE_CODE_1M; /* use lowest rate */
729 }
730 
731 /***************\
732 * Buffers setup *
733 \***************/
734 
735 static struct io_buffer *
736 ath5k_rx_iob_alloc(struct ath5k_softc *sc, u32 *iob_addr)
737 {
738  struct io_buffer *iob;
739  unsigned int off;
740 
741  /*
742  * Allocate buffer with headroom_needed space for the
743  * fake physical layer header at the start.
744  */
745  iob = alloc_iob(sc->rxbufsize + sc->cachelsz - 1);
746 
747  if (!iob) {
748  DBG("ath5k: can't alloc iobuf of size %d\n",
749  sc->rxbufsize + sc->cachelsz - 1);
750  return NULL;
751  }
752 
753  *iob_addr = virt_to_bus(iob->data);
754 
755  /*
756  * Cache-line-align. This is important (for the
757  * 5210 at least) as not doing so causes bogus data
758  * in rx'd frames.
759  */
760  off = *iob_addr % sc->cachelsz;
761  if (off != 0) {
762  iob_reserve(iob, sc->cachelsz - off);
763  *iob_addr += sc->cachelsz - off;
764  }
765 
766  return iob;
767 }
768 
769 static int
770 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
771 {
772  struct ath5k_hw *ah = sc->ah;
773  struct io_buffer *iob = bf->iob;
774  struct ath5k_desc *ds;
775 
776  if (!iob) {
777  iob = ath5k_rx_iob_alloc(sc, &bf->iobaddr);
778  if (!iob)
779  return -ENOMEM;
780  bf->iob = iob;
781  }
782 
783  /*
784  * Setup descriptors. For receive we always terminate
785  * the descriptor list with a self-linked entry so we'll
786  * not get overrun under high load (as can happen with a
787  * 5212 when ANI processing enables PHY error frames).
788  *
789  * To insure the last descriptor is self-linked we create
790  * each descriptor as self-linked and add it to the end. As
791  * each additional descriptor is added the previous self-linked
792  * entry is ``fixed'' naturally. This should be safe even
793  * if DMA is happening. When processing RX interrupts we
794  * never remove/process the last, self-linked, entry on the
795  * descriptor list. This insures the hardware always has
796  * someplace to write a new frame.
797  */
798  ds = bf->desc;
799  ds->ds_link = bf->daddr; /* link to self */
800  ds->ds_data = bf->iobaddr;
801  if (ah->ah_setup_rx_desc(ah, ds,
802  iob_tailroom(iob), /* buffer size */
803  0) != 0) {
804  DBG("ath5k: error setting up RX descriptor for %zd bytes\n", iob_tailroom(iob));
805  return -EINVAL;
806  }
807 
808  if (sc->rxlink != NULL)
809  *sc->rxlink = bf->daddr;
810  sc->rxlink = &ds->ds_link;
811  return 0;
812 }
813 
814 static int
815 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
816 {
817  struct ath5k_hw *ah = sc->ah;
818  struct ath5k_txq *txq = &sc->txq;
819  struct ath5k_desc *ds = bf->desc;
820  struct io_buffer *iob = bf->iob;
821  unsigned int pktlen, flags;
822  int ret;
823  u16 duration = 0;
824  u16 cts_rate = 0;
825 
827  bf->iobaddr = virt_to_bus(iob->data);
828  pktlen = iob_len(iob);
829 
830  /* FIXME: If we are in g mode and rate is a CCK rate
831  * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
832  * from tx power (value is in dB units already) */
834  struct net80211_device *dev = sc->dev;
835 
837  cts_rate = sc->hw_rtscts_rate;
838  duration = net80211_cts_duration(dev, pktlen);
839  }
840  ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
843  sc->hw_rate, ATH5K_RETRIES,
845  cts_rate, duration);
846  if (ret)
847  return ret;
848 
849  ds->ds_link = 0;
850  ds->ds_data = bf->iobaddr;
851 
852  list_add_tail(&bf->list, &txq->q);
853  if (txq->link == NULL) /* is this first packet? */
854  ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
855  else /* no, so only link it */
856  *txq->link = bf->daddr;
857 
858  txq->link = &ds->ds_link;
860  mb();
861 
862  return 0;
863 }
864 
865 /*******************\
866 * Descriptors setup *
867 \*******************/
868 
869 static int
871 {
872  struct ath5k_desc *ds;
873  struct ath5k_buf *bf;
874  u32 da;
875  unsigned int i;
876  int ret;
877 
878  /* allocate descriptors */
879  sc->desc_len = sizeof(struct ath5k_desc) * (ATH_TXBUF + ATH_RXBUF + 1);
881  if (sc->desc == NULL) {
882  DBG("ath5k: can't allocate descriptors\n");
883  ret = -ENOMEM;
884  goto err;
885  }
886  memset(sc->desc, 0, sc->desc_len);
887  sc->desc_daddr = virt_to_bus(sc->desc);
888 
889  ds = sc->desc;
890  da = sc->desc_daddr;
891 
892  bf = calloc(ATH_TXBUF + ATH_RXBUF + 1, sizeof(struct ath5k_buf));
893  if (bf == NULL) {
894  DBG("ath5k: can't allocate buffer pointers\n");
895  ret = -ENOMEM;
896  goto err_free;
897  }
898  sc->bufptr = bf;
899 
900  INIT_LIST_HEAD(&sc->rxbuf);
901  for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
902  bf->desc = ds;
903  bf->daddr = da;
904  list_add_tail(&bf->list, &sc->rxbuf);
905  }
906 
907  INIT_LIST_HEAD(&sc->txbuf);
908  sc->txbuf_len = ATH_TXBUF;
909  for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
910  bf->desc = ds;
911  bf->daddr = da;
912  list_add_tail(&bf->list, &sc->txbuf);
913  }
914 
915  return 0;
916 
917 err_free:
918  free_dma(sc->desc, sc->desc_len);
919 err:
920  sc->desc = NULL;
921  return ret;
922 }
923 
924 static void
926 {
927  struct ath5k_buf *bf;
928 
929  list_for_each_entry(bf, &sc->txbuf, list)
930  ath5k_txbuf_free(sc, bf);
931  list_for_each_entry(bf, &sc->rxbuf, list)
932  ath5k_rxbuf_free(sc, bf);
933 
934  /* Free memory associated with all descriptors */
935  free_dma(sc->desc, sc->desc_len);
936 
937  free(sc->bufptr);
938  sc->bufptr = NULL;
939 }
940 
941 
942 
943 
944 
945 /**************\
946 * Queues setup *
947 \**************/
948 
949 static int
950 ath5k_txq_setup(struct ath5k_softc *sc, int qtype, int subtype)
951 {
952  struct ath5k_hw *ah = sc->ah;
953  struct ath5k_txq *txq;
954  struct ath5k_txq_info qi = {
955  .tqi_subtype = subtype,
956  .tqi_aifs = AR5K_TXQ_USEDEFAULT,
957  .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
958  .tqi_cw_max = AR5K_TXQ_USEDEFAULT
959  };
960  int qnum;
961 
962  /*
963  * Enable interrupts only for EOL and DESC conditions.
964  * We mark tx descriptors to receive a DESC interrupt
965  * when a tx queue gets deep; otherwise waiting for the
966  * EOL to reap descriptors. Note that this is done to
967  * reduce interrupt load and this only defers reaping
968  * descriptors, never transmitting frames. Aside from
969  * reducing interrupts this also permits more concurrency.
970  * The only potential downside is if the tx queue backs
971  * up in which case the top half of the kernel may backup
972  * due to a lack of tx descriptors.
973  */
976  qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
977  if (qnum < 0) {
978  DBG("ath5k: can't set up a TX queue\n");
979  return -EIO;
980  }
981 
982  txq = &sc->txq;
983  if (!txq->setup) {
984  txq->qnum = qnum;
985  txq->link = NULL;
986  INIT_LIST_HEAD(&txq->q);
987  txq->setup = 1;
988  }
989  return 0;
990 }
991 
992 static void
993 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
994 {
995  struct ath5k_buf *bf, *bf0;
996 
997  list_for_each_entry_safe(bf, bf0, &txq->q, list) {
998  ath5k_txbuf_free(sc, bf);
999 
1000  list_del(&bf->list);
1001  list_add_tail(&bf->list, &sc->txbuf);
1002  sc->txbuf_len++;
1003  }
1004  txq->link = NULL;
1005 }
1006 
1007 /*
1008  * Drain the transmit queues and reclaim resources.
1009  */
1010 static void
1012 {
1013  struct ath5k_hw *ah = sc->ah;
1014 
1015  if (!(sc->status & ATH_STAT_INVALID)) {
1016  /* don't touch the hardware if marked invalid */
1017  if (sc->txq.setup) {
1019  DBG("ath5k: txq [%d] %x, link %p\n",
1020  sc->txq.qnum,
1021  ath5k_hw_get_txdp(ah, sc->txq.qnum),
1022  sc->txq.link);
1023  }
1024  }
1025 
1026  if (sc->txq.setup)
1027  ath5k_txq_drainq(sc, &sc->txq);
1028 }
1029 
1030 static void
1032 {
1033  if (sc->txq.setup) {
1035  sc->txq.setup = 0;
1036  }
1037 }
1038 
1039 
1040 
1041 
1042 /*************\
1043 * RX Handling *
1044 \*************/
1045 
1046 /*
1047  * Enable the receive h/w following a reset.
1048  */
1049 static int
1051 {
1052  struct ath5k_hw *ah = sc->ah;
1053  struct ath5k_buf *bf;
1054  int ret;
1055 
1057  if (sc->rxbufsize % sc->cachelsz != 0)
1058  sc->rxbufsize += sc->cachelsz - (sc->rxbufsize % sc->cachelsz);
1059 
1060  sc->rxlink = NULL;
1061 
1062  list_for_each_entry(bf, &sc->rxbuf, list) {
1063  ret = ath5k_rxbuf_setup(sc, bf);
1064  if (ret != 0)
1065  return ret;
1066  }
1067 
1068  bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list);
1069 
1070  ath5k_hw_set_rxdp(ah, bf->daddr);
1071  ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1072  ath5k_mode_setup(sc); /* set filters, etc. */
1073  ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1074 
1075  return 0;
1076 }
1077 
1078 /*
1079  * Disable the receive h/w in preparation for a reset.
1080  */
1081 static void
1083 {
1084  struct ath5k_hw *ah = sc->ah;
1085 
1086  ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1087  ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1088  ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1089 
1090  sc->rxlink = NULL; /* just in case */
1091 }
1092 
1093 static void
1095 {
1096  struct ath5k_rx_status rs;
1097  struct io_buffer *iob, *next_iob;
1098  u32 next_iob_addr;
1099  struct ath5k_buf *bf, *bf_last;
1100  struct ath5k_desc *ds;
1101  int ret;
1102 
1103  memset(&rs, 0, sizeof(rs));
1104 
1105  if (list_empty(&sc->rxbuf)) {
1106  DBG("ath5k: empty rx buf pool\n");
1107  return;
1108  }
1109 
1110  bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1111 
1112  do {
1113  bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list);
1114  assert(bf->iob != NULL);
1115  iob = bf->iob;
1116  ds = bf->desc;
1117 
1118  /*
1119  * last buffer must not be freed to ensure proper hardware
1120  * function. When the hardware finishes also a packet next to
1121  * it, we are sure, it doesn't use it anymore and we can go on.
1122  */
1123  if (bf_last == bf)
1124  bf->flags |= 1;
1125  if (bf->flags) {
1126  struct ath5k_buf *bf_next = list_entry(bf->list.next,
1127  struct ath5k_buf, list);
1128  ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1129  &rs);
1130  if (ret)
1131  break;
1132  bf->flags &= ~1;
1133  /* skip the overwritten one (even status is martian) */
1134  goto next;
1135  }
1136 
1137  ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1138  if (ret) {
1139  if (ret != -EINPROGRESS) {
1140  DBG("ath5k: error in processing rx desc: %s\n",
1141  strerror(ret));
1142  net80211_rx_err(sc->dev, NULL, -ret);
1143  } else {
1144  /* normal return, reached end of
1145  available descriptors */
1146  }
1147  return;
1148  }
1149 
1150  if (rs.rs_more) {
1151  DBG("ath5k: unsupported fragmented rx\n");
1152  goto next;
1153  }
1154 
1155  if (rs.rs_status) {
1156  if (rs.rs_status & AR5K_RXERR_PHY) {
1157  /* These are uncommon, and may indicate a real problem. */
1158  net80211_rx_err(sc->dev, NULL, EIO);
1159  goto next;
1160  }
1161  if (rs.rs_status & AR5K_RXERR_CRC) {
1162  /* These occur *all the time*. */
1163  goto next;
1164  }
1165  if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1166  /*
1167  * Decrypt error. If the error occurred
1168  * because there was no hardware key, then
1169  * let the frame through so the upper layers
1170  * can process it. This is necessary for 5210
1171  * parts which have no way to setup a ``clear''
1172  * key cache entry.
1173  *
1174  * XXX do key cache faulting
1175  */
1176  if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1177  !(rs.rs_status & AR5K_RXERR_CRC))
1178  goto accept;
1179  }
1180 
1181  /* any other error, unhandled */
1182  DBG("ath5k: packet rx status %x\n", rs.rs_status);
1183  goto next;
1184  }
1185 accept:
1186  next_iob = ath5k_rx_iob_alloc(sc, &next_iob_addr);
1187 
1188  /*
1189  * If we can't replace bf->iob with a new iob under memory
1190  * pressure, just skip this packet
1191  */
1192  if (!next_iob) {
1193  DBG("ath5k: dropping packet under memory pressure\n");
1194  goto next;
1195  }
1196 
1197  iob_put(iob, rs.rs_datalen);
1198 
1199  /* The MAC header is padded to have 32-bit boundary if the
1200  * packet payload is non-zero. However, iPXE only
1201  * supports standard 802.11 packets with 24-byte
1202  * header, so no padding correction should be needed.
1203  */
1204 
1205  DBG2("ath5k: rx %d bytes, signal %d\n", rs.rs_datalen,
1206  rs.rs_rssi);
1207 
1208  net80211_rx(sc->dev, iob, rs.rs_rssi,
1210 
1211  bf->iob = next_iob;
1212  bf->iobaddr = next_iob_addr;
1213 next:
1214  list_del(&bf->list);
1215  list_add_tail(&bf->list, &sc->rxbuf);
1216  } while (ath5k_rxbuf_setup(sc, bf) == 0);
1217 }
1218 
1219 
1220 
1221 
1222 /*************\
1223 * TX Handling *
1224 \*************/
1225 
1226 static void
1227 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1228 {
1229  struct ath5k_tx_status ts;
1230  struct ath5k_buf *bf, *bf0;
1231  struct ath5k_desc *ds;
1232  struct io_buffer *iob;
1233  int ret;
1234 
1235  memset(&ts, 0, sizeof(ts));
1236 
1237  list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1238  ds = bf->desc;
1239 
1240  ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1241  if (ret) {
1242  if (ret != -EINPROGRESS) {
1243  DBG("ath5k: error in processing tx desc: %s\n",
1244  strerror(ret));
1245  } else {
1246  /* normal return, reached end of tx completions */
1247  }
1248  break;
1249  }
1250 
1251  iob = bf->iob;
1252  bf->iob = NULL;
1253 
1254  DBG2("ath5k: tx %zd bytes complete, %d retries\n",
1255  iob_len(iob), ts.ts_retry[0]);
1256 
1257  net80211_tx_complete(sc->dev, iob, ts.ts_retry[0],
1258  ts.ts_status ? EIO : 0);
1259 
1260  list_del(&bf->list);
1261  list_add_tail(&bf->list, &sc->txbuf);
1262  sc->txbuf_len++;
1263  }
1264 
1265  if (list_empty(&txq->q))
1266  txq->link = NULL;
1267 }
1268 
1269 static void
1271 {
1272  ath5k_tx_processq(sc, &sc->txq);
1273 }
1274 
1275 
1276 /********************\
1277 * Interrupt handling *
1278 \********************/
1279 
1280 static void
1281 ath5k_irq(struct net80211_device *dev, int enable)
1282 {
1283  struct ath5k_softc *sc = dev->priv;
1284  struct ath5k_hw *ah = sc->ah;
1285 
1286  sc->irq_ena = enable;
1287  ah->ah_ier = enable ? AR5K_IER_ENABLE : AR5K_IER_DISABLE;
1288 
1289  ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER);
1290  ath5k_hw_set_imr(ah, sc->imask);
1291 }
1292 
1293 static int
1295 {
1296  struct ath5k_hw *ah = sc->ah;
1297  int ret, i;
1298 
1299  /*
1300  * Stop anything previously setup. This is safe
1301  * no matter this is the first time through or not.
1302  */
1303  ath5k_stop_hw(sc);
1304 
1305  /*
1306  * The basic interface to setting the hardware in a good
1307  * state is ``reset''. On return the hardware is known to
1308  * be powered up and with interrupts disabled. This must
1309  * be followed by initialization of the appropriate bits
1310  * and then setup of the interrupt mask.
1311  */
1312  sc->curchan = sc->dev->channels + sc->dev->channel;
1313  sc->curband = sc->curchan->band;
1317  ret = ath5k_reset(sc, NULL);
1318  if (ret)
1319  goto done;
1320 
1322 
1323  /*
1324  * Reset the key cache since some parts do not reset the
1325  * contents on initial power up or resume from suspend.
1326  */
1327  for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
1328  ath5k_hw_reset_key(ah, i);
1329 
1330  /* Set ack to be sent at low bit-rates */
1332 
1333  ret = 0;
1334 done:
1335  mb();
1336  return ret;
1337 }
1338 
1339 static int
1341 {
1342  struct ath5k_hw *ah = sc->ah;
1343 
1344  /*
1345  * Shutdown the hardware and driver:
1346  * stop output from above
1347  * disable interrupts
1348  * turn off timers
1349  * turn off the radio
1350  * clear transmit machinery
1351  * clear receive machinery
1352  * drain and release tx queues
1353  * reclaim beacon resources
1354  * power down hardware
1355  *
1356  * Note that some of this work is not possible if the
1357  * hardware is gone (invalid).
1358  */
1359 
1360  if (!(sc->status & ATH_STAT_INVALID)) {
1361  ath5k_hw_set_imr(ah, 0);
1362  }
1363  ath5k_txq_cleanup(sc);
1364  if (!(sc->status & ATH_STAT_INVALID)) {
1365  ath5k_rx_stop(sc);
1367  } else
1368  sc->rxlink = NULL;
1369 
1370  ath5k_rfkill_hw_stop(sc->ah);
1371 
1372  return 0;
1373 }
1374 
1375 static void
1377 {
1378  struct ath5k_softc *sc = dev->priv;
1379  struct ath5k_hw *ah = sc->ah;
1380  enum ath5k_int status;
1381  unsigned int counter = 1000;
1382 
1383  if (currticks() - sc->last_calib_ticks >
1385  ath5k_calibrate(sc);
1386  sc->last_calib_ticks = currticks();
1387  }
1388 
1389  if ((sc->status & ATH_STAT_INVALID) ||
1390  (sc->irq_ena && !ath5k_hw_is_intr_pending(ah)))
1391  return;
1392 
1393  do {
1394  ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
1395  DBGP("ath5k: status %#x/%#x\n", status, sc->imask);
1396  if (status & AR5K_INT_FATAL) {
1397  /*
1398  * Fatal errors are unrecoverable.
1399  * Typically these are caused by DMA errors.
1400  */
1401  DBG("ath5k: fatal error, resetting\n");
1402  ath5k_reset_wake(sc);
1403  } else if (status & AR5K_INT_RXORN) {
1404  DBG("ath5k: rx overrun, resetting\n");
1405  ath5k_reset_wake(sc);
1406  } else {
1407  if (status & AR5K_INT_RXEOL) {
1408  /*
1409  * NB: the hardware should re-read the link when
1410  * RXE bit is written, but it doesn't work at
1411  * least on older hardware revs.
1412  */
1413  DBG("ath5k: rx EOL\n");
1414  sc->rxlink = NULL;
1415  }
1416  if (status & AR5K_INT_TXURN) {
1417  /* bump tx trigger level */
1418  DBG("ath5k: tx underrun\n");
1420  }
1422  ath5k_handle_rx(sc);
1425  ath5k_handle_tx(sc);
1426  }
1427  } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
1428 
1429  if (!counter)
1430  DBG("ath5k: too many interrupts, giving up for now\n");
1431 }
1432 
1433 /*
1434  * Periodically recalibrate the PHY to account
1435  * for temperature/environment changes.
1436  */
1437 static void
1439 {
1440  struct ath5k_hw *ah = sc->ah;
1441 
1443  /*
1444  * Rfgain is out of bounds, reset the chip
1445  * to load new gain values.
1446  */
1447  DBG("ath5k: resetting for calibration\n");
1448  ath5k_reset_wake(sc);
1449  }
1450  if (ath5k_hw_phy_calibrate(ah, sc->curchan))
1451  DBG("ath5k: calibration of channel %d failed\n",
1452  sc->curchan->channel_nr);
1453 }
1454 
1455 
1456 /********************\
1457 * Net80211 functions *
1458 \********************/
1459 
1460 static int
1461 ath5k_tx(struct net80211_device *dev, struct io_buffer *iob)
1462 {
1463  struct ath5k_softc *sc = dev->priv;
1464  struct ath5k_buf *bf;
1465  int rc;
1466 
1467  /*
1468  * The hardware expects the header padded to 4 byte boundaries.
1469  * iPXE only ever sends 24-byte headers, so no action necessary.
1470  */
1471 
1472  if (list_empty(&sc->txbuf)) {
1473  DBG("ath5k: dropping packet because no tx bufs available\n");
1474  return -ENOBUFS;
1475  }
1476 
1477  bf = list_entry(sc->txbuf.next, struct ath5k_buf, list);
1478  list_del(&bf->list);
1479  sc->txbuf_len--;
1480 
1481  bf->iob = iob;
1482 
1483  if ((rc = ath5k_txbuf_setup(sc, bf)) != 0) {
1484  bf->iob = NULL;
1485  list_add_tail(&bf->list, &sc->txbuf);
1486  sc->txbuf_len++;
1487  return rc;
1488  }
1489  return 0;
1490 }
1491 
1492 /*
1493  * Reset the hardware. If chan is not NULL, then also pause rx/tx
1494  * and change to the given channel.
1495  */
1496 static int
1497 ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan)
1498 {
1499  struct ath5k_hw *ah = sc->ah;
1500  int ret;
1501 
1502  if (chan) {
1503  ath5k_hw_set_imr(ah, 0);
1504  ath5k_txq_cleanup(sc);
1505  ath5k_rx_stop(sc);
1506 
1507  sc->curchan = chan;
1508  sc->curband = chan->band;
1509  }
1510 
1511  ret = ath5k_hw_reset(ah, sc->curchan, 1);
1512  if (ret) {
1513  DBG("ath5k: can't reset hardware: %s\n", strerror(ret));
1514  return ret;
1515  }
1516 
1517  ret = ath5k_rx_start(sc);
1518  if (ret) {
1519  DBG("ath5k: can't start rx logic: %s\n", strerror(ret));
1520  return ret;
1521  }
1522 
1523  /*
1524  * Change channels and update the h/w rate map if we're switching;
1525  * e.g. 11a to 11b/g.
1526  *
1527  * We may be doing a reset in response to an ioctl that changes the
1528  * channel so update any state that might change as a result.
1529  *
1530  * XXX needed?
1531  */
1532 /* ath5k_chan_change(sc, c); */
1533 
1534  /* Reenable interrupts if necessary */
1535  ath5k_irq(sc->dev, sc->irq_ena);
1536 
1537  return 0;
1538 }
1539 
1540 static int ath5k_reset_wake(struct ath5k_softc *sc)
1541 {
1542  return ath5k_reset(sc, sc->curchan);
1543 }
1544 
1545 static int ath5k_start(struct net80211_device *dev)
1546 {
1547  struct ath5k_softc *sc = dev->priv;
1548  int ret;
1549 
1550  if ((ret = ath5k_init(sc)) != 0)
1551  return ret;
1552 
1553  sc->assoc = 0;
1556 
1557  return 0;
1558 }
1559 
1560 static void ath5k_stop(struct net80211_device *dev)
1561 {
1562  struct ath5k_softc *sc = dev->priv;
1563  u8 mac[ETH_ALEN] = {};
1564 
1565  ath5k_hw_set_lladdr(sc->ah, mac);
1566 
1567  ath5k_stop_hw(sc);
1568 }
1569 
1570 static int
1571 ath5k_config(struct net80211_device *dev, int changed)
1572 {
1573  struct ath5k_softc *sc = dev->priv;
1574  struct ath5k_hw *ah = sc->ah;
1575  struct net80211_channel *chan = &dev->channels[dev->channel];
1576  int ret;
1577 
1578  if (changed & NET80211_CFG_CHANNEL) {
1579  sc->power_level = chan->maxpower;
1580  if ((ret = ath5k_chan_set(sc, chan)) != 0)
1581  return ret;
1582  }
1583 
1584  if ((changed & NET80211_CFG_RATE) ||
1585  (changed & NET80211_CFG_PHY_PARAMS)) {
1586  int spmbl = ATH5K_SPMBL_NO;
1587  u16 rate = dev->rates[dev->rate];
1588  u16 slowrate = dev->rates[dev->rtscts_rate];
1589  int i;
1590 
1592  spmbl = ATH5K_SPMBL_YES;
1593 
1594  for (i = 0; i < ATH5K_NR_RATES; i++) {
1595  if (ath5k_rates[i].bitrate == rate &&
1596  (ath5k_rates[i].short_pmbl & spmbl))
1597  sc->hw_rate = ath5k_rates[i].hw_code;
1598 
1599  if (ath5k_rates[i].bitrate == slowrate &&
1600  (ath5k_rates[i].short_pmbl & spmbl))
1601  sc->hw_rtscts_rate = ath5k_rates[i].hw_code;
1602  }
1603  }
1604 
1605  if (changed & NET80211_CFG_ASSOC) {
1606  sc->assoc = !!(dev->state & NET80211_ASSOCIATED);
1607  if (sc->assoc) {
1608  memcpy(ah->ah_bssid, dev->bssid, ETH_ALEN);
1609  } else {
1610  memset(ah->ah_bssid, 0xff, ETH_ALEN);
1611  }
1612  ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
1613  }
1614 
1615  return 0;
1616 }
1617 
1618 /*
1619  * o always accept unicast, broadcast, and multicast traffic
1620  * o multicast traffic for all BSSIDs will be enabled if mac80211
1621  * says it should be
1622  * o maintain current state of phy ofdm or phy cck error reception.
1623  * If the hardware detects any of these type of errors then
1624  * ath5k_hw_get_rx_filter() will pass to us the respective
1625  * hardware filters to be able to receive these type of frames.
1626  * o probe request frames are accepted only when operating in
1627  * hostap, adhoc, or monitor modes
1628  * o enable promiscuous mode according to the interface state
1629  * o accept beacons:
1630  * - when operating in adhoc mode so the 802.11 layer creates
1631  * node table entries for peers,
1632  * - when operating in station mode for collecting rssi data when
1633  * the station is otherwise quiet, or
1634  * - when scanning
1635  */
1636 static void ath5k_configure_filter(struct ath5k_softc *sc)
1637 {
1638  struct ath5k_hw *ah = sc->ah;
1639  u32 mfilt[2], rfilt;
1640 
1641  /* Enable all multicast */
1642  mfilt[0] = ~0;
1643  mfilt[1] = ~0;
1644 
1645  /* Enable data frames and beacons */
1648 
1649  /* Set filters */
1650  ath5k_hw_set_rx_filter(ah, rfilt);
1651 
1652  /* Set multicast bits */
1653  ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
1654 
1655  /* Set the cached hw filter flags, this will alter actually
1656  * be set in HW */
1657  sc->filter_flags = rfilt;
1658 }
struct ath5k_txq txq
Definition: base.h:124
uint16_t u16
Definition: stdint.h:21
#define AR5K_RXERR_PHY
Definition: ath5k.h:580
struct ath5k_capabilities ah_capabilities
Definition: ath5k.h:1007
static void ath5k_rxbuf_free(struct ath5k_softc *sc __unused, struct ath5k_buf *bf)
Definition: ath5k.c:188
#define EINVAL
Invalid argument.
Definition: errno.h:428
unsigned long membase
Memory base.
Definition: pci.h:194
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
const char * name
Definition: ath9k_hw.c:1984
static void ath5k_remove(struct pci_device *pdev)
Definition: ath5k.c:403
#define PCI_CACHE_LINE_SIZE
PCI cache line size.
Definition: pci.h:46
unsigned int curmode
Definition: base.h:111
int modes
A bitwise OR of the 802.11x modes supported by this device.
Definition: net80211.h:450
void net80211_free(struct net80211_device *dev)
Free 802.11 device.
Definition: net80211.c:838
struct net80211_channel channels[NET80211_MAX_CHANNELS]
List of RF channels supported by the card.
Definition: net80211.h:498
static void ath5k_txq_cleanup(struct ath5k_softc *sc)
Definition: ath5k.c:1011
#define ath5k_hw_hasbssidmask(_ah)
Definition: base.h:140
#define iob_put(iobuf, len)
Definition: iobuf.h:116
#define ATH_TXBUF
Definition: base.h:53
#define TICKS_PER_SEC
Number of ticks per second.
Definition: timer.h:15
int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
ath5k_hw_stop_rx_dma - Stop DMA receive
Definition: ath5k_dma.c:65
A PCI driver.
Definition: pci.h:224
#define max(x, y)
Definition: ath.h:39
#define ATH5K_SPMBL_BOTH
Definition: ath5k.c:90
static struct io_buffer * ath5k_rx_iob_alloc(struct ath5k_softc *sc, u32 *iob_addr)
Definition: ath5k.c:736
int(* ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, struct ath5k_tx_status *)
Definition: ath5k.h:1060
int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
Definition: ath5k_pcu.c:496
u8 channel
The channel currently in use, as an index into the channels array.
Definition: net80211.h:812
#define ATH5K_CALIB_INTERVAL
Definition: ath5k.c:58
#define ATH_RXBUF
Definition: base.h:52
#define ATH5K_RATE_CODE_12M
Definition: ath5k.h:713
#define ATH5K_RATE_CODE_36M
Definition: ath5k.h:716
#define PCI_LATENCY_TIMER
PCI latency timer.
Definition: pci.h:49
uint32_t next
Next descriptor address.
Definition: myson.h:18
struct list_head * next
Next list entry.
Definition: list.h:20
#define ATH5K_RATE_CODE_11M
Definition: ath5k.h:709
static int ath5k_config(struct net80211_device *dev, int changed)
Definition: ath5k.c:1571
static void ath5k_detach(struct net80211_device *dev)
Definition: ath5k.c:492
#define ATH5K_RATE_CODE_2M
Definition: ath5k.h:707
u8 ts_retry[4]
Definition: ath5k.h:421
static int ath5k_hw_rix_to_bitrate(int hw_rix)
Definition: ath5k.c:705
int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
ath5k_hw_set_lladdr - Set station id
Definition: ath5k_pcu.c:200
#define ATH_STAT_INVALID
Definition: base.h:104
int ath5k_hw_phy_disable(struct ath5k_hw *ah)
Definition: ath5k_phy.c:1358
unsigned long driver_data
Arbitrary driver data.
Definition: pci.h:159
void net80211_rx_err(struct net80211_device *dev, struct io_buffer *iob, int rc)
Indicate an error in receiving a packet.
Definition: net80211.c:2788
#define AR5K_KEYTABLE_SIZE
Definition: reg.h:1851
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
struct list_head rxbuf
Definition: base.h:119
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:226
void net80211_rx(struct net80211_device *dev, struct io_buffer *iob, int signal, u16 rate)
Handle receipt of 802.11 frame.
Definition: net80211.c:2689
uint8_t type
Type.
Definition: ena.h:16
u8 rtscts_rate
The rate to use for RTS/CTS transmissions.
Definition: net80211.h:831
static int ath5k_txq_setup(struct ath5k_softc *sc, int qtype, int subtype)
Definition: ath5k.c:950
void ath5k_rfkill_hw_stop(struct ath5k_hw *ah)
Definition: ath5k_rfkill.c:97
void net80211_unregister(struct net80211_device *dev)
Unregister 802.11 device from network stack.
Definition: net80211.c:824
static void ath5k_handle_tx(struct ath5k_softc *sc)
Definition: ath5k.c:1270
#define AR5K_RXERR_CRC
Definition: ath5k.h:579
#define AR5K_TXQ_USEDEFAULT
Definition: ath5k.h:248
static void ath5k_poll(struct net80211_device *dev)
Definition: ath5k.c:1376
int setup
Definition: base.h:77
int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
Definition: ath5k_dma.c:292
#define ATH5K_NR_RATES
Definition: ath5k.c:115
u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
Definition: ath5k_dma.c:261
iPXE timers
static int ath5k_reset_wake(struct ath5k_softc *sc)
Definition: ath5k.c:1540
static int ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
Definition: ath5k.c:815
unsigned signal_max
Maximum signal in arbitrary cases.
Definition: net80211.h:495
enum net80211_hw_info::@547 flags
A set of flags indicating peculiarities of this device.
void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high)
ath5k_hw_set_ack_bitrate - set bitrate for ACKs
Definition: ath5k_pcu.c:95
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define ATH5K_RATE_CODE_6M
Definition: ath5k.h:711
u16 ah_phy_revision
Definition: ath5k.h:970
int irq_ena
Definition: base.h:95
static struct pci_device_id ath5k_nics[]
Definition: ath5k.c:67
int assoc
Definition: base.h:134
void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
ath5k_hw_set_associd - Set BSSID for association
Definition: ath5k_pcu.c:228
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
u16 ah_radio_5ghz_revision
Definition: ath5k.h:971
void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
ath5k_hw_start_rx_dma - Start DMA receive
Definition: ath5k_dma.c:54
ath5k_hw_get_isr - Get interrupt status
Definition: ath5k.h:953
void ath5k_rfkill_hw_start(struct ath5k_hw *ah)
Definition: ath5k_rfkill.c:80
#define ECANCELED
Operation canceled.
Definition: errno.h:343
#define AR5K_RXERR_DECRYPT
Definition: ath5k.h:582
static int ath5k_chan_set(struct ath5k_softc *sc, struct net80211_channel *chan)
Definition: ath5k.c:655
int(* open)(struct net80211_device *dev)
Open 802.11 device.
Definition: net80211.h:305
#define NET80211_BAND_BIT_5GHZ
Bitmask for the 5GHz band.
Definition: net80211.h:54
Dynamic memory allocation.
#define list_empty(list)
Test whether a list is empty.
Definition: list.h:136
#define AR5K_RXKEYIX_INVALID
Definition: ath5k.h:584
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45
#define ATH5K_RATE_CODE_18M
Definition: ath5k.h:714
uint8_t ch
Definition: registers.h:83
uint8_t status
Status.
Definition: ena.h:16
unsigned int txbuf_len
Definition: base.h:123
u16 rates[NET80211_NR_BANDS][NET80211_MAX_RATES]
List of transmission rates supported by the card, indexed by band.
Definition: net80211.h:508
#define list_del(list)
Delete an entry from a list.
Definition: list.h:119
struct io_buffer * iob
Definition: base.h:60
static struct net80211_device_operations ath5k_ops
Definition: ath5k.c:144
int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
Definition: ath5k_dma.c:127
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:338
static short ath5k_ieee2mhz(short chan)
Definition: ath5k.c:512
Operations that must be implemented by an 802.11 driver.
Definition: net80211.h:293
#define ENOMEM
Not enough space.
Definition: errno.h:534
A hardware device.
Definition: device.h:73
int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
Definition: ath5k_phy.c:830
void * memcpy(void *dest, const void *src, size_t len) __nonnull
struct pci_driver ath5k_pci_driver __pci_driver
Definition: ath5k.c:123
u16 hw_value
Hardware channel value.
Definition: net80211.h:414
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
uint16_t device
Device ID.
Definition: pci.h:204
void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
ath5k_hw_set_rx_filter - Set rx filter
Definition: ath5k_pcu.c:453
#define DBGP(...)
Definition: compiler.h:532
#define AR5K_TXDESC_INTREQ
Definition: desc.h:330
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
u8 hwaddr[ETH_ALEN]
Default hardware MAC address.
Definition: net80211.h:447
u8 maxpower
Maximum allowable transmit power, in dBm.
Definition: net80211.h:425
u8 hw_code
Definition: ath5k.c:95
int ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
ath5k_hw_is_intr_pending - Check if we have pending interrupts
Definition: ath5k_dma.c:391
#define list_for_each_entry(pos, head, member)
Iterate over entries in a list.
Definition: list.h:420
int curband
Definition: base.h:94
#define IEEE80211_TYP_FRAME_HEADER_LEN
Frame header length for frames we might work with.
Definition: ieee80211.h:60
u32 * link
Definition: base.h:75
#define list_add_tail(new, head)
Add a new entry to the tail of a list.
Definition: list.h:93
struct ath5k_buf * bufptr
Definition: base.h:97
int nr_rates[NET80211_NR_BANDS]
Number of supported rates, indexed by band.
Definition: net80211.h:511
enum ath5k_int imask
Definition: base.h:114
static int ath5k_rx_start(struct ath5k_softc *sc)
Definition: ath5k.c:1050
struct list_head q
Definition: base.h:76
void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
ath5k_hw_set_rxdp - Set RX Descriptor's address
Definition: ath5k_dma.c:102
static void *__malloc calloc(size_t nmemb, size_t size)
Allocate cleared memory.
Definition: stdlib.h:45
int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel)
Definition: ath5k_reset.c:690
static void ath5k_txq_release(struct ath5k_softc *sc)
Definition: ath5k.c:1031
u8 bssidmask[ETH_ALEN]
Definition: base.h:116
static int ath5k_stop_hw(struct ath5k_softc *sc)
Definition: ath5k.c:1340
void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
ath5k_hw_start_rx_pcu - Start RX engine
Definition: ath5k_pcu.c:384
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
Definition: net80211.h:47
#define list_for_each_entry_safe(pos, tmp, head, member)
Iterate over entries in a list, safe against deletion of the current entry.
Definition: list.h:447
void * priv
Driver private data.
Definition: net80211.h:798
#define NET80211_PHY_USE_SHORT_PREAMBLE
Whether to use 802.11b short preamble operation.
Definition: net80211.h:260
enum ath5k_tx_queue_subtype tqi_subtype
Definition: ath5k.h:508
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
struct list_head list
Definition: base.h:56
#define NET80211_PHY_USE_PROTECTION
Whether to use RTS/CTS or CTS-to-self protection for transmissions.
Definition: net80211.h:251
Definition: base.h:73
unsigned int rxbufsize
Definition: base.h:118
struct net80211_device * net80211_alloc(size_t priv_size)
Allocate 802.11 device.
Definition: net80211.c:754
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
u16 duration
Microseconds to reserve link.
Definition: ieee80211.h:15
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
int pci_write_config_byte(struct pci_device *pci, unsigned int where, uint8_t value)
Write byte to PCI configuration space.
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
u16 center_freq
The center frequency for this channel.
Definition: net80211.h:411
uint8_t subtype
Slow protocols subtype.
Definition: eth_slow.h:12
static int ath5k_start(struct net80211_device *dev)
Definition: ath5k.c:1545
u32 desc_daddr
Definition: base.h:99
u8 band
The band with which this channel is associated.
Definition: net80211.h:388
static int ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan)
Definition: ath5k.c:1497
PCI bus.
#define NET80211_CFG_PHY_PARAMS
Low-level link parameters (short preamble, protection, etc) have changed.
Definition: net80211.h:90
A PCI device.
Definition: pci.h:187
void ath5k_hw_release_tx_queue(struct ath5k_hw *ah)
Definition: ath5k_qcu.c:86
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
#define NET80211_ASSOCIATED
Whether we have successfully associated with the network.
Definition: net80211.h:201
#define ATH5K_RETRIES
Definition: ath5k.c:59
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
#define AR5K_SET_SHORT_PREAMBLE
Definition: ath5k.h:726
size_t desc_len
Definition: base.h:100
static void ath5k_desc_free(struct ath5k_softc *sc)
Definition: ath5k.c:925
ath5k_srev_type
Definition: ath5k.h:275
An 802.11 RF channel.
Definition: net80211.h:385
#define CHANNEL_TURBO
Definition: ath5k.h:629
static size_t iob_tailroom(struct io_buffer *iobuf)
Calculate available space at end of an I/O buffer.
Definition: iobuf.h:171
#define ATH5K_RATE_CODE_48M
Definition: ath5k.h:717
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
int ah_single_chip
Definition: ath5k.h:964
enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
ath5k_hw_set_imr - Set interrupt mask
Definition: ath5k_dma.c:548
#define CHANNEL_OFDM
Definition: ath5k.h:631
struct net80211_channel * curchan
Definition: base.h:112
#define ATH5K_SPMBL_YES
Definition: ath5k.c:89
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
static void ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
Definition: ath5k.c:993
#define AR5K_RX_FILTER_BEACON
Definition: reg.h:1331
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE
Definition: ath5k.h:490
void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
at5k_hw_stop_rx_pcu - Stop RX engine
Definition: ath5k_pcu.c:398
unsigned int filter_flags
Definition: base.h:110
static void ath5k_handle_rx(struct ath5k_softc *sc)
Definition: ath5k.c:1094
#define ATH5K_SPMBL_NO
Definition: ath5k.c:88
#define NET80211_MODE_B
802.11b: 1-11 Mbps operation using DSSS/CCK signaling on the 2.4GHz band
Definition: net80211.h:66
#define ETH_ALEN
Definition: if_ether.h:8
void net80211_tx_complete(struct net80211_device *dev, struct io_buffer *iob, int retries, int rc)
Indicate the completed transmission of a packet.
Definition: net80211.c:2808
A PCI device ID list entry.
Definition: pci.h:151
u16 ah_radio_2ghz_revision
Definition: ath5k.h:972
#define AR5K_TXKEYIX_INVALID
Definition: ath5k.h:585
u16 rates[NET80211_MAX_RATES]
A list of all possible TX rates we might use.
Definition: net80211.h:818
uint32_t ds
Definition: librm.h:254
static void ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
Definition: ath5k.c:674
Definition: base.h:55
static int ath5k_probe(struct pci_device *pdev)
Definition: ath5k.c:246
int phy_flags
Physical layer options.
Definition: net80211.h:983
void __asmcall int val
Definition: setjmp.h:28
int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
Definition: ath5k_dma.c:412
int(* ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, struct ath5k_rx_status *)
Definition: ath5k.h:1062
struct device * dev
Underlying hardware device.
Definition: netdevice.h:360
int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah)
ath5k_hw_attach - Check if hw is supported and init the needed structs
Definition: ath5k_attach.c:112
static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, struct net80211_channel *channels, unsigned int mode, unsigned int max)
Definition: ath5k.c:524
u16 bitrate
Definition: ath5k.c:93
#define AR5K_TXDESC_CLRDMASK
Definition: desc.h:326
static const struct @8 ath5k_rates[]
u32 daddr
Definition: base.h:59
#define AR5K_RX_FILTER_BCAST
Definition: reg.h:1329
Network device management.
struct pci_device * pdev
Definition: base.h:89
enum net80211_hw_info::@548 signal_type
Signal strength information that can be provided by the device.
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
struct ieee80211_ie_channels_channel_band channels[0]
List of (start, length) channel bands we can use.
Definition: ieee80211.h:18
static int ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
Definition: ath5k.c:770
struct ath5k_desc * desc
Definition: base.h:58
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:348
struct net_device * netdev
The net_device that wraps us.
Definition: net80211.h:789
unsigned int qnum
Definition: base.h:74
FILE_LICENCE(BSD3)
#define iob_reserve(iobuf, len)
Definition: iobuf.h:63
#define INIT_LIST_HEAD(list)
Initialise a list head.
Definition: list.h:45
static int ath5k_setup_bands(struct net80211_device *dev)
Definition: ath5k.c:585
int status
Definition: base.h:103
struct net80211_hw_info * hwinfo
Definition: base.h:93
#define AR5K_IER_ENABLE
Definition: reg.h:92
struct list_head list
List of which this buffer is a member.
Definition: iobuf.h:39
u16 cachelsz
Definition: base.h:101
int ath5k_hw_set_opmode(struct ath5k_hw *ah)
ath5k_hw_set_opmode - Set PCU operating mode
Definition: ath5k_pcu.c:48
int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
ath5k_hw_set_bssid_mask - filter out bssids we listen
Definition: ath5k_pcu.c:348
#define AR5K_TXDESC_CTSENA
Definition: desc.h:329
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
PCI I/O API.
struct list_head * prev
Previous list entry.
Definition: list.h:22
static int ath5k_desc_alloc(struct ath5k_softc *sc)
Definition: ath5k.c:870
void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
Definition: ath5k_pcu.c:406
void * iobase
Definition: base.h:90
#define AR5K_IER_DISABLE
Definition: reg.h:91
#define AR5K_RX_FILTER_UCAST
Definition: reg.h:1327
#define NET80211_BAND_BIT_2GHZ
Bitmask for the 2GHz band.
Definition: net80211.h:52
#define CHANNEL_5GHZ
Definition: ath5k.h:633
void * data
Start of data.
Definition: iobuf.h:44
int nr_channels
Number of supported channels.
Definition: net80211.h:501
#define EIO
Input/output error.
Definition: errno.h:433
struct net80211_channel channels[NET80211_MAX_CHANNELS]
A list of all possible channels we might use.
Definition: net80211.h:806
uint16_t count
Number of entries.
Definition: ena.h:22
u16 tqi_flags
Definition: ath5k.h:509
int power_level
Definition: base.h:133
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
struct pci_device_id * id
Driver device ID.
Definition: pci.h:220
int ath5k_bitrate_to_hw_rix(int bitrate)
Definition: ath5k.c:718
#define ATH5K_RATE_CODE_5_5M
Definition: ath5k.h:708
int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase)
ath5k_hw_update_tx_triglevel - Update tx trigger level
Definition: ath5k_dma.c:339
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define ATH5K_RATE_CODE_24M
Definition: ath5k.h:715
#define ATH5K_RATE_CODE_1M
Definition: ath5k.h:706
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE
Definition: ath5k.h:491
#define NET80211_CFG_RATE
Requested transmission rate (dev->rate) has changed.
Definition: net80211.h:84
int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
Definition: ath5k_phy.c:389
uint8_t ah
Definition: registers.h:85
void mb(void)
Memory barrier.
static u16 net80211_cts_duration(struct net80211_device *dev, int size)
Calculate duration field for a CTS control frame.
Definition: net80211.h:1179
struct net80211_device * dev
Definition: base.h:91
u8 short_pmbl
Definition: ath5k.c:94
#define AR5K_IER
Definition: reg.h:90
#define NET80211_CFG_CHANNEL
Channel choice (dev->channel) or regulatory parameters have changed.
Definition: net80211.h:81
int bands
A bitwise OR of the bands on which this device can communicate.
Definition: net80211.h:453
static int ath5k_init(struct ath5k_softc *sc)
Definition: ath5k.c:1294
u8 bssid[ETH_ALEN]
MAC address of the access point most recently associated.
Definition: net80211.h:954
static void ath5k_irq(struct net80211_device *dev, int enable)
Definition: ath5k.c:1281
int hw_rtscts_rate
Definition: base.h:137
u16 state
State of our association to the network.
Definition: net80211.h:921
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:381
u32 ah_mac_srev
Definition: ath5k.h:967
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
#define CHANNEL_2GHZ
Definition: ath5k.h:632
#define ATH5K_DESC_ALIGN
Definition: ath5k.c:60
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
u8 channel_nr
A channel number interpreted according to the band.
Definition: net80211.h:405
#define list_entry(list, type, member)
Get the container of a list entry.
Definition: list.h:321
int last_calib_ticks
Definition: base.h:131
u16 rs_datalen
Definition: ath5k.h:568
int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
Definition: ath5k_dma.c:167
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
unsigned int flags
Definition: base.h:57
int hw_rate
Definition: base.h:136
struct ath5k_hw * ah
Definition: base.h:92
unsigned channel_change_time
Estimate of the time required to change channels, in microseconds.
Definition: net80211.h:518
#define NET80211_CFG_ASSOC
Association has been established with a new BSS (dev->bssid)
Definition: net80211.h:87
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel)
Definition: ath5k_phy.c:1345
static int ath5k_attach(struct net80211_device *dev)
Definition: ath5k.c:421
#define ATH5K_RATE_CODE_54M
Definition: ath5k.h:718
void ath5k_hw_detach(struct ath5k_hw *ah)
ath5k_hw_detach - Free the ath5k_hw struct
Definition: ath5k_attach.c:335
u8 rate
The rate currently in use, as an index into the rates array.
Definition: net80211.h:824
u32 * rxlink
Definition: base.h:120
struct list_head txbuf
Definition: base.h:122
struct bofm_section_header done
Definition: bofm_test.c:46
#define NET80211_MODE_G
802.11g: 54 Mbps operation using ERP/OFDM signaling on the 2.4GHz band
Definition: net80211.h:69
uint8_t u8
Definition: stdint.h:19
ath5k_int
enum ath5k_int - Hardware interrupt masks helpers
Definition: ath5k.h:804
uint32_t u32
Definition: stdint.h:23
#define ATH5K_RATE_CODE_9M
Definition: ath5k.h:712
int net80211_register(struct net80211_device *dev, struct net80211_device_operations *ops, struct net80211_hw_info *hw)
Register 802.11 device with network stack.
Definition: net80211.c:791
int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info)
Definition: ath5k_qcu.c:55
#define NET80211_MODE_A
802.11a: 54 Mbps operation using OFDM signaling on the 5GHz band
Definition: net80211.h:63
static void ath5k_txbuf_free(struct ath5k_softc *sc, struct ath5k_buf *bf)
Definition: ath5k.c:178
static void ath5k_stop(struct net80211_device *dev)
Definition: ath5k.c:1560
struct ath5k_desc * desc
Definition: base.h:98
static void ath5k_mode_setup(struct ath5k_softc *sc)
Definition: ath5k.c:686
#define DBG2(...)
Definition: compiler.h:515
#define AR5K_RX_FILTER_MCAST
Definition: reg.h:1328
static void ath5k_rx_stop(struct ath5k_softc *sc)
Definition: ath5k.c:1082
static int ath5k_tx(struct net80211_device *dev, struct io_buffer *skb)
Definition: ath5k.c:1461
#define IEEE80211_MAX_LEN
Definition: ath5k.h:158
void * memset(void *dest, int character, size_t len) __nonnull
u32 iobaddr
Definition: base.h:61
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
static unsigned int unsigned int mem
Definition: intel.h:271
A persistent I/O buffer.
Definition: iobuf.h:32
uint8_t flags
Flags.
Definition: ena.h:18
static void ath5k_configure_filter(struct ath5k_softc *sc)
Definition: ath5k.c:1636
static void ath5k_calibrate(struct ath5k_softc *sc)
Definition: ath5k.c:1438
static void ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
Definition: ath5k.c:1227