iPXE
efx_common.c
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1 /**************************************************************************
2  *
3  * Driver datapath common code for Solarflare network cards
4  *
5  * Written by Shradha Shah <sshah@solarflare.com>
6  *
7  * Copyright Fen Systems Ltd. 2005
8  * Copyright Level 5 Networks Inc. 2005
9  * Copyright 2006-2017 Solarflare Communications Inc.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of the
14  * License, or any later version.
15  *
16  * You can also choose to distribute this program under the terms of
17  * the Unmodified Binary Distribution Licence (as given in the file
18  * COPYING.UBDL), provided that you have satisfied its requirements.
19  *
20  ***************************************************************************/
21 #include <stdint.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <unistd.h>
25 #include <errno.h>
26 #include <assert.h>
27 #include <byteswap.h>
28 #include <ipxe/io.h>
29 #include <ipxe/pci.h>
30 #include <ipxe/malloc.h>
31 #include <ipxe/iobuf.h>
32 #include <ipxe/netdevice.h>
33 #include "efx_common.h"
34 #include "efx_bitfield.h"
35 #include "mc_driver_pcol.h"
36 
37 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
38 
39 /*******************************************************************************
40  *
41  *
42  * Low-level hardware access
43  *
44  *
45  ******************************************************************************/
46 
47 void
48 efx_writel(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
49 {
50  DBGCIO(efx, "Writing partial register %x with " EFX_DWORD_FMT "\n",
52  _efx_writel(efx, value->u32[0], reg);
53 }
54 
55 void
56 efx_readl(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
57 {
58  value->u32[0] = _efx_readl(efx, reg);
59  DBGCIO(efx, "Read from register %x, got " EFX_DWORD_FMT "\n",
61 }
62 
63 /*******************************************************************************
64  *
65  *
66  * Inititialization and Close
67  *
68  *
69  ******************************************************************************/
71 {
72  struct efx_nic *efx = netdev_priv(netdev);
73  struct pci_device *pci = container_of(netdev->dev,
74  struct pci_device, dev);
75  unsigned int reg = PCI_BASE_ADDRESS_0;
76  uint32_t bar_low;
77 
78  efx->netdev = netdev;
79  efx->revision = revision;
80 
81  /* Find the memory bar to use */
82  pci_read_config_dword(pci, reg, &bar_low);
85 
86  efx->mmio_start = pci_bar_start(pci, reg);
87  efx->mmio_len = pci_bar_size(pci, reg);
88  efx->membase = ioremap(efx->mmio_start, efx->mmio_len);
89 
90  DBGCP(efx, "BAR of %lx bytes at phys %lx mapped at %p\n",
91  efx->mmio_len, efx->mmio_start, efx->membase);
92 
93  /* Enable PCI access */
94  adjust_pci_device(pci);
95 }
96 
98 {
99  struct efx_nic *efx = netdev_priv(netdev);
100 
101  iounmap(efx->membase);
102  efx->membase = NULL;
103 }
void efx_writel(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
Definition: efx_common.c:48
static void * netdev_priv(struct net_device *netdev)
Get driver private area for this network device.
Definition: netdevice.h:566
iPXE I/O API
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
Hardware access.
Definition: efx_common.h:147
Error codes.
I/O buffers.
#define PCI_BASE_ADDRESS_0
Definition: pci.h:61
static void _efx_writel(struct efx_nic *efx, uint32_t value, unsigned int reg)
Definition: efx_common.h:205
A doubleword (4 byte) datatype - little-endian in HW.
Definition: efx_bitfield.h:87
void efx_probe(struct net_device *netdev, enum efx_revision revision)
Definition: efx_common.c:70
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
struct device dev
Generic device.
Definition: pci.h:189
unsigned long mmio_len
Definition: efx_common.h:158
Dynamic memory allocation.
#define PCI_BASE_ADDRESS_IO_MASK
I/O BAR mask.
Definition: pci.h:68
Assertions.
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
#define EFX_DWORD_FMT
Definition: efx_bitfield.h:107
efx_revision
Definition: efx_common.h:142
Efx bitfield access.
#define PCI_BASE_ADDRESS_2
Definition: pci.h:63
static struct net_device * netdev
Definition: gdbudp.c:52
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
uint32_t revision
Definition: ib_mad.h:20
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Find the size of a PCI BAR.
Definition: pciextra.c:90
static unsigned int unsigned int reg
Definition: intel.h:245
PCI bus.
A PCI device.
Definition: pci.h:187
#define EFX_DWORD_VAL(dword)
Definition: efx_bitfield.h:110
A network device.
Definition: netdevice.h:348
#define DBGCIO(...)
Definition: compiler.h:556
enum efx_revision revision
Definition: efx_common.h:149
unsigned int uint32_t
Definition: stdint.h:12
#define PCI_BASE_ADDRESS_SPACE_IO
I/O BAR.
Definition: pci.h:67
struct device * dev
Underlying hardware device.
Definition: netdevice.h:360
void * membase
Memory and IO base.
Definition: efx_common.h:156
Network device management.
void efx_remove(struct net_device *netdev)
Definition: efx_common.c:97
unsigned long mmio_start
Definition: efx_common.h:157
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define DBGCP(...)
Definition: compiler.h:539
static uint32_t _efx_readl(struct efx_nic *efx, unsigned int reg)
Definition: efx_common.h:211
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
void efx_readl(struct efx_nic *efx, efx_dword_t *value, unsigned int reg)
Definition: efx_common.c:56
This file is a subset of the MCDI headers generated from the yml files.
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct net_device * netdev
Definition: efx_common.h:148