igbvf_defines.h File Reference

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Macros
#define	_IGBVF_DEFINES_H_
#define	REQ_TX_DESCRIPTOR_MULTIPLE   8
#define	REQ_RX_DESCRIPTOR_MULTIPLE   8
#define	E1000_WUC_APME   0x00000001 /* APM Enable */
#define	E1000_WUC_PME_EN   0x00000002 /* PME Enable */
#define	E1000_WUC_PME_STATUS   0x00000004 /* PME Status */
#define	E1000_WUC_APMPME   0x00000008 /* Assert PME on APM Wakeup */
#define	E1000_WUC_LSCWE   0x00000010 /* Link Status wake up enable */
#define	E1000_WUC_LSCWO   0x00000020 /* Link Status wake up override */
#define	E1000_WUC_SPM   0x80000000 /* Enable SPM */
#define	E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
#define	E1000_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */
#define	E1000_WUFC_MAG   0x00000002 /* Magic Packet Wakeup Enable */
#define	E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
#define	E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
#define	E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
#define	E1000_WUFC_ARP   0x00000020 /* ARP Request Packet Wakeup Enable */
#define	E1000_WUFC_IPV4   0x00000040 /* Directed IPv4 Packet Wakeup Enable */
#define	E1000_WUFC_IPV6   0x00000080 /* Directed IPv6 Packet Wakeup Enable */
#define	E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
#define	E1000_WUFC_FLX0   0x00010000 /* Flexible Filter 0 Enable */
#define	E1000_WUFC_FLX1   0x00020000 /* Flexible Filter 1 Enable */
#define	E1000_WUFC_FLX2   0x00040000 /* Flexible Filter 2 Enable */
#define	E1000_WUFC_FLX3   0x00080000 /* Flexible Filter 3 Enable */
#define	E1000_WUFC_ALL_FILTERS   0x000F00FF /* Mask for all wakeup filters */
#define	E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
#define	E1000_WUFC_FLX_FILTERS   0x000F0000 /*Mask for the 4 flexible filters */
#define	E1000_WUS_LNKC   E1000_WUFC_LNKC
#define	E1000_WUS_MAG   E1000_WUFC_MAG
#define	E1000_WUS_EX   E1000_WUFC_EX
#define	E1000_WUS_MC   E1000_WUFC_MC
#define	E1000_WUS_BC   E1000_WUFC_BC
#define	E1000_WUS_ARP   E1000_WUFC_ARP
#define	E1000_WUS_IPV4   E1000_WUFC_IPV4
#define	E1000_WUS_IPV6   E1000_WUFC_IPV6
#define	E1000_WUS_FLX0   E1000_WUFC_FLX0
#define	E1000_WUS_FLX1   E1000_WUFC_FLX1
#define	E1000_WUS_FLX2   E1000_WUFC_FLX2
#define	E1000_WUS_FLX3   E1000_WUFC_FLX3
#define	E1000_WUS_FLX_FILTERS   E1000_WUFC_FLX_FILTERS
#define	E1000_WUPL_LENGTH_MASK   0x0FFF /* Only the lower 12 bits are valid */
#define	E1000_FLEXIBLE_FILTER_COUNT_MAX   4
#define	E1000_FLEXIBLE_FILTER_SIZE_MAX   128
#define	E1000_FFLT_SIZE   E1000_FLEXIBLE_FILTER_COUNT_MAX
#define	E1000_FFMT_SIZE   E1000_FLEXIBLE_FILTER_SIZE_MAX
#define	E1000_FFVT_SIZE   E1000_FLEXIBLE_FILTER_SIZE_MAX
#define	E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
#define	E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
#define	E1000_CTRL_EXT_PHYINT_EN   E1000_CTRL_EXT_GPI1_EN
#define	E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
#define	E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
#define	E1000_CTRL_EXT_SDP4_DATA   0x00000010 /* Value of SW Definable Pin 4 */
#define	E1000_CTRL_EXT_SDP5_DATA   0x00000020 /* Value of SW Definable Pin 5 */
#define	E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
#define	E1000_CTRL_EXT_SDP6_DATA   0x00000040 /* Value of SW Definable Pin 6 */
#define	E1000_CTRL_EXT_SDP3_DATA   0x00000080 /* Value of SW Definable Pin 3 */
#define	E1000_CTRL_EXT_SDP4_DIR   0x00000100 /* Direction of SDP4 0=in 1=out */
#define	E1000_CTRL_EXT_SDP5_DIR   0x00000200 /* Direction of SDP5 0=in 1=out */
#define	E1000_CTRL_EXT_SDP6_DIR   0x00000400 /* Direction of SDP6 0=in 1=out */
#define	E1000_CTRL_EXT_SDP3_DIR   0x00000800 /* Direction of SDP3 0=in 1=out */
#define	E1000_CTRL_EXT_ASDCHK   0x00001000 /* Initiate an ASD sequence */
#define	E1000_CTRL_EXT_EE_RST   0x00002000 /* Reinitialize from EEPROM */
#define	E1000_CTRL_EXT_IPS   0x00004000 /* Invert Power State */
#define	E1000_CTRL_EXT_SPD_BYPS   0x00008000 /* Speed Select Bypass */
#define	E1000_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
#define	E1000_CTRL_EXT_DMA_DYN_CLK_EN   0x00080000 /* DMA Dynamic Clock Gating */
#define	E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000
#define	E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000
#define	E1000_CTRL_EXT_LINK_MODE_TBI   0x00C00000
#define	E1000_CTRL_EXT_LINK_MODE_KMRN   0x00000000
#define	E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES   0x00C00000
#define	E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES   0x00800000
#define	E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
#define	E1000_CTRL_EXT_EIAME   0x01000000
#define	E1000_CTRL_EXT_IRCA   0x00000001
#define	E1000_CTRL_EXT_WR_WMARK_MASK   0x03000000
#define	E1000_CTRL_EXT_WR_WMARK_256   0x00000000
#define	E1000_CTRL_EXT_WR_WMARK_320   0x01000000
#define	E1000_CTRL_EXT_WR_WMARK_384   0x02000000
#define	E1000_CTRL_EXT_WR_WMARK_448   0x03000000
#define	E1000_CTRL_EXT_CANC   0x04000000 /* Int delay cancellation */
#define	E1000_CTRL_EXT_DRV_LOAD   0x10000000 /* Driver loaded bit for FW */
#define	E1000_CTRL_EXT_IAME   0x08000000 /* Int acknowledge Auto-mask */
#define	E1000_CRTL_EXT_PB_PAREN
#define	E1000_CTRL_EXT_DF_PAREN
#define	E1000_CTRL_EXT_GHOST_PAREN   0x40000000
#define	E1000_CTRL_EXT_PBA_CLR   0x80000000 /* PBA Clear */
#define	E1000_I2CCMD_REG_ADDR_SHIFT   16
#define	E1000_I2CCMD_REG_ADDR   0x00FF0000
#define	E1000_I2CCMD_PHY_ADDR_SHIFT   24
#define	E1000_I2CCMD_PHY_ADDR   0x07000000
#define	E1000_I2CCMD_OPCODE_READ   0x08000000
#define	E1000_I2CCMD_OPCODE_WRITE   0x00000000
#define	E1000_I2CCMD_RESET   0x10000000
#define	E1000_I2CCMD_READY   0x20000000
#define	E1000_I2CCMD_INTERRUPT_ENA   0x40000000
#define	E1000_I2CCMD_ERROR   0x80000000
#define	E1000_MAX_SGMII_PHY_REG_ADDR   255
#define	E1000_I2CCMD_PHY_TIMEOUT   200
#define	E1000_RXD_STAT_DD   0x01 /* Descriptor Done */
#define	E1000_RXD_STAT_EOP   0x02 /* End of Packet */
#define	E1000_RXD_STAT_IXSM   0x04 /* Ignore checksum */
#define	E1000_RXD_STAT_VP   0x08 /* IEEE VLAN Packet */
#define	E1000_RXD_STAT_UDPCS   0x10 /* UDP xsum calculated */
#define	E1000_RXD_STAT_TCPCS   0x20 /* TCP xsum calculated */
#define	E1000_RXD_STAT_IPCS   0x40 /* IP xsum calculated */
#define	E1000_RXD_STAT_PIF   0x80 /* passed in-exact filter */
#define	E1000_RXD_STAT_CRCV   0x100 /* Speculative CRC Valid */
#define	E1000_RXD_STAT_IPIDV   0x200 /* IP identification valid */
#define	E1000_RXD_STAT_UDPV   0x400 /* Valid UDP checksum */
#define	E1000_RXD_STAT_DYNINT   0x800 /* Pkt caused INT via DYNINT */
#define	E1000_RXD_STAT_ACK   0x8000 /* ACK Packet indication */
#define	E1000_RXD_ERR_CE   0x01 /* CRC Error */
#define	E1000_RXD_ERR_SE   0x02 /* Symbol Error */
#define	E1000_RXD_ERR_SEQ   0x04 /* Sequence Error */
#define	E1000_RXD_ERR_CXE   0x10 /* Carrier Extension Error */
#define	E1000_RXD_ERR_TCPE   0x20 /* TCP/UDP Checksum Error */
#define	E1000_RXD_ERR_IPE   0x40 /* IP Checksum Error */
#define	E1000_RXD_ERR_RXE   0x80 /* Rx Data Error */
#define	E1000_RXD_SPC_VLAN_MASK   0x0FFF /* VLAN ID is in lower 12 bits */
#define	E1000_RXD_SPC_PRI_MASK   0xE000 /* Priority is in upper 3 bits */
#define	E1000_RXD_SPC_PRI_SHIFT   13
#define	E1000_RXD_SPC_CFI_MASK   0x1000 /* CFI is bit 12 */
#define	E1000_RXD_SPC_CFI_SHIFT   12
#define	E1000_RXDEXT_STATERR_CE   0x01000000
#define	E1000_RXDEXT_STATERR_SE   0x02000000
#define	E1000_RXDEXT_STATERR_SEQ   0x04000000
#define	E1000_RXDEXT_STATERR_CXE   0x10000000
#define	E1000_RXDEXT_STATERR_TCPE   0x20000000
#define	E1000_RXDEXT_STATERR_IPE   0x40000000
#define	E1000_RXDEXT_STATERR_RXE   0x80000000
#define	E1000_RXD_ERR_FRAME_ERR_MASK
#define	E1000_RXDEXT_ERR_FRAME_ERR_MASK
#define	E1000_MRQC_ENABLE_MASK   0x00000007
#define	E1000_MRQC_ENABLE_RSS_2Q   0x00000001
#define	E1000_MRQC_ENABLE_RSS_INT   0x00000004
#define	E1000_MRQC_RSS_FIELD_MASK   0xFFFF0000
#define	E1000_MRQC_RSS_FIELD_IPV4_TCP   0x00010000
#define	E1000_MRQC_RSS_FIELD_IPV4   0x00020000
#define	E1000_MRQC_RSS_FIELD_IPV6_TCP_EX   0x00040000
#define	E1000_MRQC_RSS_FIELD_IPV6_EX   0x00080000
#define	E1000_MRQC_RSS_FIELD_IPV6   0x00100000
#define	E1000_MRQC_RSS_FIELD_IPV6_TCP   0x00200000
#define	E1000_RXDPS_HDRSTAT_HDRSP   0x00008000
#define	E1000_RXDPS_HDRSTAT_HDRLEN_MASK   0x000003FF
#define	E1000_MANC_SMBUS_EN   0x00000001 /* SMBus Enabled - RO */
#define	E1000_MANC_ASF_EN   0x00000002 /* ASF Enabled - RO */
#define	E1000_MANC_R_ON_FORCE   0x00000004 /* Reset on Force TCO - RO */
#define	E1000_MANC_RMCP_EN   0x00000100 /* Enable RCMP 026Fh Filtering */
#define	E1000_MANC_0298_EN   0x00000200 /* Enable RCMP 0298h Filtering */
#define	E1000_MANC_IPV4_EN   0x00000400 /* Enable IPv4 */
#define	E1000_MANC_IPV6_EN   0x00000800 /* Enable IPv6 */
#define	E1000_MANC_SNAP_EN   0x00001000 /* Accept LLC/SNAP */
#define	E1000_MANC_ARP_EN   0x00002000 /* Enable ARP Request Filtering */
#define	E1000_MANC_NEIGHBOR_EN   0x00004000
#define	E1000_MANC_ARP_RES_EN   0x00008000 /* Enable ARP response Filtering */
#define	E1000_MANC_TCO_RESET   0x00010000 /* TCO Reset Occurred */
#define	E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */
#define	E1000_MANC_REPORT_STATUS   0x00040000 /* Status Reporting Enabled */
#define	E1000_MANC_RCV_ALL   0x00080000 /* Receive All Enabled */
#define	E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
#define	E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
#define	E1000_MANC_EN_MNG2HOST   0x00200000
#define	E1000_MANC_EN_IP_ADDR_FILTER   0x00400000
#define	E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
#define	E1000_MANC_BR_EN   0x01000000 /* Enable broadcast filtering */
#define	E1000_MANC_SMB_REQ   0x01000000 /* SMBus Request */
#define	E1000_MANC_SMB_GNT   0x02000000 /* SMBus Grant */
#define	E1000_MANC_SMB_CLK_IN   0x04000000 /* SMBus Clock In */
#define	E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
#define	E1000_MANC_SMB_DATA_OUT   0x10000000 /* SMBus Data Out */
#define	E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
#define	E1000_MANC_SMB_DATA_OUT_SHIFT   28 /* SMBus Data Out Shift */
#define	E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
#define	E1000_RCTL_RST   0x00000001 /* Software reset */
#define	E1000_RCTL_EN   0x00000002 /* enable */
#define	E1000_RCTL_SBP   0x00000004 /* store bad packet */
#define	E1000_RCTL_UPE   0x00000008 /* unicast promisc enable */
#define	E1000_RCTL_MPE   0x00000010 /* multicast promisc enable */
#define	E1000_RCTL_LPE   0x00000020 /* long packet enable */
#define	E1000_RCTL_LBM_NO   0x00000000 /* no loopback mode */
#define	E1000_RCTL_LBM_MAC   0x00000040 /* MAC loopback mode */
#define	E1000_RCTL_LBM_SLP   0x00000080 /* serial link loopback mode */
#define	E1000_RCTL_LBM_TCVR   0x000000C0 /* tcvr loopback mode */
#define	E1000_RCTL_DTYP_MASK   0x00000C00 /* Descriptor type mask */
#define	E1000_RCTL_DTYP_PS   0x00000400 /* Packet Split descriptor */
#define	E1000_RCTL_RDMTS_HALF   0x00000000 /* rx desc min thresh size */
#define	E1000_RCTL_RDMTS_QUAT   0x00000100 /* rx desc min thresh size */
#define	E1000_RCTL_RDMTS_EIGTH   0x00000200 /* rx desc min thresh size */
#define	E1000_RCTL_MO_SHIFT   12 /* multicast offset shift */
#define	E1000_RCTL_MO_0   0x00000000 /* multicast offset 11:0 */
#define	E1000_RCTL_MO_1   0x00001000 /* multicast offset 12:1 */
#define	E1000_RCTL_MO_2   0x00002000 /* multicast offset 13:2 */
#define	E1000_RCTL_MO_3   0x00003000 /* multicast offset 15:4 */
#define	E1000_RCTL_MDR   0x00004000 /* multicast desc ring 0 */
#define	E1000_RCTL_BAM   0x00008000 /* broadcast enable */
#define	E1000_RCTL_SZ_2048   0x00000000 /* rx buffer size 2048 */
#define	E1000_RCTL_SZ_1024   0x00010000 /* rx buffer size 1024 */
#define	E1000_RCTL_SZ_512   0x00020000 /* rx buffer size 512 */
#define	E1000_RCTL_SZ_256   0x00030000 /* rx buffer size 256 */
#define	E1000_RCTL_SZ_16384   0x00010000 /* rx buffer size 16384 */
#define	E1000_RCTL_SZ_8192   0x00020000 /* rx buffer size 8192 */
#define	E1000_RCTL_SZ_4096   0x00030000 /* rx buffer size 4096 */
#define	E1000_RCTL_VFE   0x00040000 /* vlan filter enable */
#define	E1000_RCTL_CFIEN   0x00080000 /* canonical form enable */
#define	E1000_RCTL_CFI   0x00100000 /* canonical form indicator */
#define	E1000_RCTL_DPF   0x00400000 /* discard pause frames */
#define	E1000_RCTL_PMCF   0x00800000 /* pass MAC control frames */
#define	E1000_RCTL_BSEX   0x02000000 /* Buffer size extension */
#define	E1000_RCTL_SECRC   0x04000000 /* Strip Ethernet CRC */
#define	E1000_RCTL_FLXBUF_MASK   0x78000000 /* Flexible buffer size */
#define	E1000_RCTL_FLXBUF_SHIFT   27 /* Flexible buffer shift */
#define	E1000_PSRCTL_BSIZE0_MASK   0x0000007F
#define	E1000_PSRCTL_BSIZE1_MASK   0x00003F00
#define	E1000_PSRCTL_BSIZE2_MASK   0x003F0000
#define	E1000_PSRCTL_BSIZE3_MASK   0x3F000000
#define	E1000_PSRCTL_BSIZE0_SHIFT   7 /* Shift _right_ 7 */
#define	E1000_PSRCTL_BSIZE1_SHIFT   2 /* Shift _right_ 2 */
#define	E1000_PSRCTL_BSIZE2_SHIFT   6 /* Shift _left_ 6 */
#define	E1000_PSRCTL_BSIZE3_SHIFT   14 /* Shift _left_ 14 */
#define	E1000_SWFW_EEP_SM   0x01
#define	E1000_SWFW_PHY0_SM   0x02
#define	E1000_SWFW_PHY1_SM   0x04
#define	E1000_SWFW_CSR_SM   0x08
#define	E1000_FACTPS_LFS   0x40000000 /* LAN Function Select */
#define	E1000_CTRL_FD   0x00000001 /* Full duplex.0=half; 1=full */
#define	E1000_CTRL_BEM   0x00000002 /* Endian Mode.0=little,1=big */
#define	E1000_CTRL_PRIOR   0x00000004 /* Priority on PCI. 0=rx,1=fair */
#define	E1000_CTRL_GIO_MASTER_DISABLE   0x00000004 /*Blocks new Master reqs */
#define	E1000_CTRL_LRST   0x00000008 /* Link reset. 0=normal,1=reset */
#define	E1000_CTRL_TME   0x00000010 /* Test mode. 0=normal,1=test */
#define	E1000_CTRL_SLE   0x00000020 /* Serial Link on 0=dis,1=en */
#define	E1000_CTRL_ASDE   0x00000020 /* Auto-speed detect enable */
#define	E1000_CTRL_SLU   0x00000040 /* Set link up (Force Link) */
#define	E1000_CTRL_ILOS   0x00000080 /* Invert Loss-Of Signal */
#define	E1000_CTRL_SPD_SEL   0x00000300 /* Speed Select Mask */
#define	E1000_CTRL_SPD_10   0x00000000 /* Force 10Mb */
#define	E1000_CTRL_SPD_100   0x00000100 /* Force 100Mb */
#define	E1000_CTRL_SPD_1000   0x00000200 /* Force 1Gb */
#define	E1000_CTRL_BEM32   0x00000400 /* Big Endian 32 mode */
#define	E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */
#define	E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */
#define	E1000_CTRL_D_UD_EN   0x00002000 /* Dock/Undock enable */
#define	E1000_CTRL_D_UD_POLARITY
#define	E1000_CTRL_FORCE_PHY_RESET
#define	E1000_CTRL_EXT_LINK_EN
#define	E1000_CTRL_SWDPIN0   0x00040000 /* SWDPIN 0 value */
#define	E1000_CTRL_SWDPIN1   0x00080000 /* SWDPIN 1 value */
#define	E1000_CTRL_SWDPIN2   0x00100000 /* SWDPIN 2 value */
#define	E1000_CTRL_SWDPIN3   0x00200000 /* SWDPIN 3 value */
#define	E1000_CTRL_SWDPIO0   0x00400000 /* SWDPIN 0 Input or output */
#define	E1000_CTRL_SWDPIO1   0x00800000 /* SWDPIN 1 input or output */
#define	E1000_CTRL_SWDPIO2   0x01000000 /* SWDPIN 2 input or output */
#define	E1000_CTRL_SWDPIO3   0x02000000 /* SWDPIN 3 input or output */
#define	E1000_CTRL_RST   0x04000000 /* Global reset */
#define	E1000_CTRL_RFCE   0x08000000 /* Receive Flow Control enable */
#define	E1000_CTRL_TFCE   0x10000000 /* Transmit flow control enable */
#define	E1000_CTRL_RTE   0x20000000 /* Routing tag enable */
#define	E1000_CTRL_VME   0x40000000 /* IEEE VLAN mode enable */
#define	E1000_CTRL_PHY_RST   0x80000000 /* PHY Reset */
#define	E1000_CTRL_SW2FW_INT   0x02000000 /* Initiate an interrupt to ME */
#define	E1000_CTRL_I2C_ENA   0x02000000 /* I2C enable */
#define	E1000_CTRL_PHY_RESET_DIR   E1000_CTRL_SWDPIO0
#define	E1000_CTRL_PHY_RESET   E1000_CTRL_SWDPIN0
#define	E1000_CTRL_MDIO_DIR   E1000_CTRL_SWDPIO2
#define	E1000_CTRL_MDIO   E1000_CTRL_SWDPIN2
#define	E1000_CTRL_MDC_DIR   E1000_CTRL_SWDPIO3
#define	E1000_CTRL_MDC   E1000_CTRL_SWDPIN3
#define	E1000_CTRL_PHY_RESET_DIR4   E1000_CTRL_EXT_SDP4_DIR
#define	E1000_CTRL_PHY_RESET4   E1000_CTRL_EXT_SDP4_DATA
#define	E1000_CONNSW_ENRGSRC   0x4
#define	E1000_PCS_CFG_PCS_EN   8
#define	E1000_PCS_LCTL_FLV_LINK_UP   1
#define	E1000_PCS_LCTL_FSV_10   0
#define	E1000_PCS_LCTL_FSV_100   2
#define	E1000_PCS_LCTL_FSV_1000   4
#define	E1000_PCS_LCTL_FDV_FULL   8
#define	E1000_PCS_LCTL_FSD   0x10
#define	E1000_PCS_LCTL_FORCE_LINK   0x20
#define	E1000_PCS_LCTL_LOW_LINK_LATCH   0x40
#define	E1000_PCS_LCTL_FORCE_FCTRL   0x80
#define	E1000_PCS_LCTL_AN_ENABLE   0x10000
#define	E1000_PCS_LCTL_AN_RESTART   0x20000
#define	E1000_PCS_LCTL_AN_TIMEOUT   0x40000
#define	E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000
#define	E1000_PCS_LCTL_AN_SGMII_TRIGGER   0x100000
#define	E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000
#define	E1000_PCS_LCTL_LINK_OK_FIX   0x2000000
#define	E1000_PCS_LCTL_CRS_ON_NI   0x4000000
#define	E1000_ENABLE_SERDES_LOOPBACK   0x0410
#define	E1000_PCS_LSTS_LINK_OK   1
#define	E1000_PCS_LSTS_SPEED_10   0
#define	E1000_PCS_LSTS_SPEED_100   2
#define	E1000_PCS_LSTS_SPEED_1000   4
#define	E1000_PCS_LSTS_DUPLEX_FULL   8
#define	E1000_PCS_LSTS_SYNK_OK   0x10
#define	E1000_PCS_LSTS_AN_COMPLETE   0x10000
#define	E1000_PCS_LSTS_AN_PAGE_RX   0x20000
#define	E1000_PCS_LSTS_AN_TIMED_OUT   0x40000
#define	E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000
#define	E1000_PCS_LSTS_AN_ERROR_RWS   0x100000
#define	E1000_STATUS_FD   0x00000001 /* Full duplex.0=half,1=full */
#define	E1000_STATUS_LU   0x00000002 /* Link up.0=no,1=link */
#define	E1000_STATUS_FUNC_MASK   0x0000000C /* PCI Function Mask */
#define	E1000_STATUS_FUNC_SHIFT   2
#define	E1000_STATUS_FUNC_0   0x00000000 /* Function 0 */
#define	E1000_STATUS_FUNC_1   0x00000004 /* Function 1 */
#define	E1000_STATUS_TXOFF   0x00000010 /* transmission paused */
#define	E1000_STATUS_TBIMODE   0x00000020 /* TBI mode */
#define	E1000_STATUS_SPEED_MASK   0x000000C0
#define	E1000_STATUS_SPEED_10   0x00000000 /* Speed 10Mb/s */
#define	E1000_STATUS_SPEED_100   0x00000040 /* Speed 100Mb/s */
#define	E1000_STATUS_SPEED_1000   0x00000080 /* Speed 1000Mb/s */
#define	E1000_STATUS_LAN_INIT_DONE   0x00000200 /* Lan Init Completion by NVM */
#define	E1000_STATUS_ASDV   0x00000300 /* Auto speed detect value */
#define	E1000_STATUS_PHYRA   0x00000400 /* PHY Reset Asserted */
#define	E1000_STATUS_DOCK_CI
#define	E1000_STATUS_GIO_MASTER_ENABLE   0x00080000 /* Master request status */
#define	E1000_STATUS_MTXCKOK   0x00000400 /* MTX clock running OK */
#define	E1000_STATUS_PCI66   0x00000800 /* In 66Mhz slot */
#define	E1000_STATUS_BUS64   0x00001000 /* In 64 bit slot */
#define	E1000_STATUS_PCIX_MODE   0x00002000 /* PCI-X mode */
#define	E1000_STATUS_PCIX_SPEED   0x0000C000 /* PCI-X bus speed */
#define	E1000_STATUS_BMC_SKU_0   0x00100000 /* BMC USB redirect disabled */
#define	E1000_STATUS_BMC_SKU_1   0x00200000 /* BMC SRAM disabled */
#define	E1000_STATUS_BMC_SKU_2   0x00400000 /* BMC SDRAM disabled */
#define	E1000_STATUS_BMC_CRYPTO   0x00800000 /* BMC crypto disabled */
#define	E1000_STATUS_BMC_LITE
#define	E1000_STATUS_RGMII_ENABLE   0x02000000 /* RGMII disabled */
#define	E1000_STATUS_FUSE_8   0x04000000
#define	E1000_STATUS_FUSE_9   0x08000000
#define	E1000_STATUS_SERDES0_DIS   0x10000000 /* SERDES disabled on port 0 */
#define	E1000_STATUS_SERDES1_DIS   0x20000000 /* SERDES disabled on port 1 */
#define	E1000_STATUS_PCIX_SPEED_66   0x00000000 /* PCI-X bus speed 50-66 MHz */
#define	E1000_STATUS_PCIX_SPEED_100   0x00004000 /* PCI-X bus speed 66-100 MHz */
#define	E1000_STATUS_PCIX_SPEED_133   0x00008000 /*PCI-X bus speed 100-133 MHz*/
#define	SPEED_10   10
#define	SPEED_100   100
#define	SPEED_1000   1000
#define	HALF_DUPLEX   1
#define	FULL_DUPLEX   2
#define	PHY_FORCE_TIME   20
#define	ADVERTISE_10_HALF   0x0001
#define	ADVERTISE_10_FULL   0x0002
#define	ADVERTISE_100_HALF   0x0004
#define	ADVERTISE_100_FULL   0x0008
#define	ADVERTISE_1000_HALF   0x0010 /* Not used, just FYI */
#define	ADVERTISE_1000_FULL   0x0020
#define	E1000_ALL_SPEED_DUPLEX
#define	E1000_ALL_NOT_GIG
#define	E1000_ALL_100_SPEED   (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
#define	E1000_ALL_10_SPEED   (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
#define	E1000_ALL_FULL_DUPLEX
#define	E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
#define	AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
#define	E1000_LEDCTL_LED0_MODE_MASK   0x0000000F
#define	E1000_LEDCTL_LED0_MODE_SHIFT   0
#define	E1000_LEDCTL_LED0_BLINK_RATE   0x00000020
#define	E1000_LEDCTL_LED0_IVRT   0x00000040
#define	E1000_LEDCTL_LED0_BLINK   0x00000080
#define	E1000_LEDCTL_LED1_MODE_MASK   0x00000F00
#define	E1000_LEDCTL_LED1_MODE_SHIFT   8
#define	E1000_LEDCTL_LED1_BLINK_RATE   0x00002000
#define	E1000_LEDCTL_LED1_IVRT   0x00004000
#define	E1000_LEDCTL_LED1_BLINK   0x00008000
#define	E1000_LEDCTL_LED2_MODE_MASK   0x000F0000
#define	E1000_LEDCTL_LED2_MODE_SHIFT   16
#define	E1000_LEDCTL_LED2_BLINK_RATE   0x00200000
#define	E1000_LEDCTL_LED2_IVRT   0x00400000
#define	E1000_LEDCTL_LED2_BLINK   0x00800000
#define	E1000_LEDCTL_LED3_MODE_MASK   0x0F000000
#define	E1000_LEDCTL_LED3_MODE_SHIFT   24
#define	E1000_LEDCTL_LED3_BLINK_RATE   0x20000000
#define	E1000_LEDCTL_LED3_IVRT   0x40000000
#define	E1000_LEDCTL_LED3_BLINK   0x80000000
#define	E1000_LEDCTL_MODE_LINK_10_1000   0x0
#define	E1000_LEDCTL_MODE_LINK_100_1000   0x1
#define	E1000_LEDCTL_MODE_LINK_UP   0x2
#define	E1000_LEDCTL_MODE_ACTIVITY   0x3
#define	E1000_LEDCTL_MODE_LINK_ACTIVITY   0x4
#define	E1000_LEDCTL_MODE_LINK_10   0x5
#define	E1000_LEDCTL_MODE_LINK_100   0x6
#define	E1000_LEDCTL_MODE_LINK_1000   0x7
#define	E1000_LEDCTL_MODE_PCIX_MODE   0x8
#define	E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
#define	E1000_LEDCTL_MODE_COLLISION   0xA
#define	E1000_LEDCTL_MODE_BUS_SPEED   0xB
#define	E1000_LEDCTL_MODE_BUS_SIZE   0xC
#define	E1000_LEDCTL_MODE_PAUSED   0xD
#define	E1000_LEDCTL_MODE_LED_ON   0xE
#define	E1000_LEDCTL_MODE_LED_OFF   0xF
#define	E1000_TXD_DTYP_D   0x00100000 /* Data Descriptor */
#define	E1000_TXD_DTYP_C   0x00000000 /* Context Descriptor */
#define	E1000_TXD_POPTS_SHIFT   8 /* POPTS shift */
#define	E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */
#define	E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */
#define	E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */
#define	E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
#define	E1000_TXD_CMD_IC   0x04000000 /* Insert Checksum */
#define	E1000_TXD_CMD_RS   0x08000000 /* Report Status */
#define	E1000_TXD_CMD_RPS   0x10000000 /* Report Packet Sent */
#define	E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
#define	E1000_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */
#define	E1000_TXD_CMD_IDE   0x80000000 /* Enable Tidv register */
#define	E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */
#define	E1000_TXD_STAT_EC   0x00000002 /* Excess Collisions */
#define	E1000_TXD_STAT_LC   0x00000004 /* Late Collisions */
#define	E1000_TXD_STAT_TU   0x00000008 /* Transmit underrun */
#define	E1000_TXD_CMD_TCP   0x01000000 /* TCP packet */
#define	E1000_TXD_CMD_IP   0x02000000 /* IP packet */
#define	E1000_TXD_CMD_TSE   0x04000000 /* TCP Seg enable */
#define	E1000_TXD_STAT_TC   0x00000004 /* Tx Underrun */
#define	E1000_TCTL_RST   0x00000001 /* software reset */
#define	E1000_TCTL_EN   0x00000002 /* enable tx */
#define	E1000_TCTL_BCE   0x00000004 /* busy check enable */
#define	E1000_TCTL_PSP   0x00000008 /* pad short packets */
#define	E1000_TCTL_CT   0x00000ff0 /* collision threshold */
#define	E1000_TCTL_COLD   0x003ff000 /* collision distance */
#define	E1000_TCTL_SWXOFF   0x00400000 /* SW Xoff transmission */
#define	E1000_TCTL_PBE   0x00800000 /* Packet Burst Enable */
#define	E1000_TCTL_RTLC   0x01000000 /* Re-transmit on late collision */
#define	E1000_TCTL_NRTU   0x02000000 /* No Re-transmit on underrun */
#define	E1000_TCTL_MULR   0x10000000 /* Multiple request support */
#define	E1000_TARC0_ENABLE   0x00000400 /* Enable Tx Queue 0 */
#define	E1000_SCTL_DISABLE_SERDES_LOOPBACK   0x0400
#define	E1000_RXCSUM_PCSS_MASK   0x000000FF /* Packet Checksum Start */
#define	E1000_RXCSUM_IPOFL   0x00000100 /* IPv4 checksum offload */
#define	E1000_RXCSUM_TUOFL   0x00000200 /* TCP / UDP checksum offload */
#define	E1000_RXCSUM_IPV6OFL   0x00000400 /* IPv6 checksum offload */
#define	E1000_RXCSUM_CRCOFL   0x00000800 /* CRC32 offload enable */
#define	E1000_RXCSUM_IPPCSE   0x00001000 /* IP payload checksum enable */
#define	E1000_RXCSUM_PCSD   0x00002000 /* packet checksum disabled */
#define	E1000_RFCTL_ISCSI_DIS   0x00000001
#define	E1000_RFCTL_ISCSI_DWC_MASK   0x0000003E
#define	E1000_RFCTL_ISCSI_DWC_SHIFT   1
#define	E1000_RFCTL_NFSW_DIS   0x00000040
#define	E1000_RFCTL_NFSR_DIS   0x00000080
#define	E1000_RFCTL_NFS_VER_MASK   0x00000300
#define	E1000_RFCTL_NFS_VER_SHIFT   8
#define	E1000_RFCTL_IPV6_DIS   0x00000400
#define	E1000_RFCTL_IPV6_XSUM_DIS   0x00000800
#define	E1000_RFCTL_ACK_DIS   0x00001000
#define	E1000_RFCTL_ACKD_DIS   0x00002000
#define	E1000_RFCTL_IPFRSP_DIS   0x00004000
#define	E1000_RFCTL_EXTEN   0x00008000
#define	E1000_RFCTL_IPV6_EX_DIS   0x00010000
#define	E1000_RFCTL_NEW_IPV6_EXT_DIS   0x00020000
#define	E1000_RFCTL_LEF   0x00040000
#define	E1000_COLLISION_THRESHOLD   15
#define	E1000_CT_SHIFT   4
#define	E1000_COLLISION_DISTANCE   63
#define	E1000_COLD_SHIFT   12
#define	DEFAULT_82543_TIPG_IPGT_FIBER   9
#define	DEFAULT_82543_TIPG_IPGT_COPPER   8
#define	E1000_TIPG_IPGT_MASK   0x000003FF
#define	E1000_TIPG_IPGR1_MASK   0x000FFC00
#define	E1000_TIPG_IPGR2_MASK   0x3FF00000
#define	DEFAULT_82543_TIPG_IPGR1   8
#define	E1000_TIPG_IPGR1_SHIFT   10
#define	DEFAULT_82543_TIPG_IPGR2   6
#define	DEFAULT_80003ES2LAN_TIPG_IPGR2   7
#define	E1000_TIPG_IPGR2_SHIFT   20
#define	ETHERNET_IEEE_VLAN_TYPE   0x8100 /* 802.3ac packet */
#define	ETHERNET_FCS_SIZE   4
#define	MAX_JUMBO_FRAME_SIZE   0x3F00
#define	E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP   0x00000020
#define	E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE   0x00000001
#define	E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE   0x00000008
#define	E1000_EXTCNF_CTRL_SWFLAG   0x00000020
#define	E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
#define	E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT   16
#define	E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
#define	E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT   16
#define	E1000_PHY_CTRL_SPD_EN   0x00000001
#define	E1000_PHY_CTRL_D0A_LPLU   0x00000002
#define	E1000_PHY_CTRL_NOND0A_LPLU   0x00000004
#define	E1000_PHY_CTRL_NOND0A_GBE_DISABLE   0x00000008
#define	E1000_PHY_CTRL_GBE_DISABLE   0x00000040
#define	E1000_KABGTXD_BGSQLBIAS   0x00050000
#define	E1000_PBA_6K   0x0006 /* 6KB */
#define	E1000_PBA_8K   0x0008 /* 8KB */
#define	E1000_PBA_10K   0x000A /* 10KB */
#define	E1000_PBA_12K   0x000C /* 12KB */
#define	E1000_PBA_14K   0x000E /* 14KB */
#define	E1000_PBA_16K   0x0010 /* 16KB */
#define	E1000_PBA_18K   0x0012
#define	E1000_PBA_20K   0x0014
#define	E1000_PBA_22K   0x0016
#define	E1000_PBA_24K   0x0018
#define	E1000_PBA_26K   0x001A
#define	E1000_PBA_30K   0x001E
#define	E1000_PBA_32K   0x0020
#define	E1000_PBA_34K   0x0022
#define	E1000_PBA_35K   0x0023
#define	E1000_PBA_38K   0x0026
#define	E1000_PBA_40K   0x0028
#define	E1000_PBA_48K   0x0030 /* 48KB */
#define	E1000_PBA_64K   0x0040 /* 64KB */
#define	E1000_PBS_16K   E1000_PBA_16K
#define	E1000_PBS_24K   E1000_PBA_24K
#define	IFS_MAX   80
#define	IFS_MIN   40
#define	IFS_RATIO   4
#define	IFS_STEP   10
#define	MIN_NUM_XMITS   1000
#define	E1000_SWSM_SMBI   0x00000001 /* Driver Semaphore bit */
#define	E1000_SWSM_SWESMBI   0x00000002 /* FW Semaphore bit */
#define	E1000_SWSM_WMNG   0x00000004 /* Wake MNG Clock */
#define	E1000_SWSM_DRV_LOAD   0x00000008 /* Driver Loaded Bit */
#define	E1000_SWSM2_LOCK   0x00000002 /* Secondary driver semaphore bit */
#define	E1000_ICR_TXDW   0x00000001 /* Transmit desc written back */
#define	E1000_ICR_TXQE   0x00000002 /* Transmit Queue empty */
#define	E1000_ICR_LSC   0x00000004 /* Link Status Change */
#define	E1000_ICR_RXSEQ   0x00000008 /* rx sequence error */
#define	E1000_ICR_RXDMT0   0x00000010 /* rx desc min. threshold (0) */
#define	E1000_ICR_RXO   0x00000040 /* rx overrun */
#define	E1000_ICR_RXT0   0x00000080 /* rx timer intr (ring 0) */
#define	E1000_ICR_VMMB   0x00000100 /* VM MB event */
#define	E1000_ICR_MDAC   0x00000200 /* MDIO access complete */
#define	E1000_ICR_RXCFG   0x00000400 /* Rx /c/ ordered set */
#define	E1000_ICR_GPI_EN0   0x00000800 /* GP Int 0 */
#define	E1000_ICR_GPI_EN1   0x00001000 /* GP Int 1 */
#define	E1000_ICR_GPI_EN2   0x00002000 /* GP Int 2 */
#define	E1000_ICR_GPI_EN3   0x00004000 /* GP Int 3 */
#define	E1000_ICR_TXD_LOW   0x00008000
#define	E1000_ICR_SRPD   0x00010000
#define	E1000_ICR_ACK   0x00020000 /* Receive Ack frame */
#define	E1000_ICR_MNG   0x00040000 /* Manageability event */
#define	E1000_ICR_DOCK   0x00080000 /* Dock/Undock */
#define	E1000_ICR_INT_ASSERTED
#define	E1000_ICR_RXD_FIFO_PAR0   0x00100000 /* Q0 Rx desc FIFO parity error */
#define	E1000_ICR_TXD_FIFO_PAR0   0x00200000 /* Q0 Tx desc FIFO parity error */
#define	E1000_ICR_HOST_ARB_PAR   0x00400000 /* host arb read buffer parity err */
#define	E1000_ICR_PB_PAR   0x00800000 /* packet buffer parity error */
#define	E1000_ICR_RXD_FIFO_PAR1   0x01000000 /* Q1 Rx desc FIFO parity error */
#define	E1000_ICR_TXD_FIFO_PAR1   0x02000000 /* Q1 Tx desc FIFO parity error */
#define	E1000_ICR_ALL_PARITY   0x03F00000 /* all parity error bits */
#define	E1000_ICR_DSW
#define	E1000_ICR_PHYINT
#define	E1000_ICR_DOUTSYNC   0x10000000 /* NIC DMA out of sync */
#define	E1000_ICR_EPRST   0x00100000 /* ME hardware reset occurs */
#define	POLL_IMS_ENABLE_MASK
#define	IMS_ENABLE_MASK
#define	E1000_IMS_TXDW   E1000_ICR_TXDW /* Tx desc written back */
#define	E1000_IMS_TXQE   E1000_ICR_TXQE /* Transmit Queue empty */
#define	E1000_IMS_LSC   E1000_ICR_LSC /* Link Status Change */
#define	E1000_IMS_VMMB   E1000_ICR_VMMB /* Mail box activity */
#define	E1000_IMS_RXSEQ   E1000_ICR_RXSEQ /* rx sequence error */
#define	E1000_IMS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define	E1000_IMS_RXO   E1000_ICR_RXO /* rx overrun */
#define	E1000_IMS_RXT0   E1000_ICR_RXT0 /* rx timer intr */
#define	E1000_IMS_MDAC   E1000_ICR_MDAC /* MDIO access complete */
#define	E1000_IMS_RXCFG   E1000_ICR_RXCFG /* Rx /c/ ordered set */
#define	E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0 /* GP Int 0 */
#define	E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1 /* GP Int 1 */
#define	E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2 /* GP Int 2 */
#define	E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3 /* GP Int 3 */
#define	E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
#define	E1000_IMS_SRPD   E1000_ICR_SRPD
#define	E1000_IMS_ACK   E1000_ICR_ACK /* Receive Ack frame */
#define	E1000_IMS_MNG   E1000_ICR_MNG /* Manageability event */
#define	E1000_IMS_DOCK   E1000_ICR_DOCK /* Dock/Undock */
#define	E1000_IMS_RXD_FIFO_PAR0
#define	E1000_IMS_TXD_FIFO_PAR0
#define	E1000_IMS_HOST_ARB_PAR
#define	E1000_IMS_PB_PAR
#define	E1000_IMS_RXD_FIFO_PAR1
#define	E1000_IMS_TXD_FIFO_PAR1
#define	E1000_IMS_DSW   E1000_ICR_DSW
#define	E1000_IMS_PHYINT   E1000_ICR_PHYINT
#define	E1000_IMS_DOUTSYNC   E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
#define	E1000_IMS_EPRST   E1000_ICR_EPRST
#define	E1000_ICS_TXDW   E1000_ICR_TXDW /* Tx desc written back */
#define	E1000_ICS_TXQE   E1000_ICR_TXQE /* Transmit Queue empty */
#define	E1000_ICS_LSC   E1000_ICR_LSC /* Link Status Change */
#define	E1000_ICS_RXSEQ   E1000_ICR_RXSEQ /* rx sequence error */
#define	E1000_ICS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define	E1000_ICS_RXO   E1000_ICR_RXO /* rx overrun */
#define	E1000_ICS_RXT0   E1000_ICR_RXT0 /* rx timer intr */
#define	E1000_ICS_MDAC   E1000_ICR_MDAC /* MDIO access complete */
#define	E1000_ICS_RXCFG   E1000_ICR_RXCFG /* Rx /c/ ordered set */
#define	E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0 /* GP Int 0 */
#define	E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1 /* GP Int 1 */
#define	E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2 /* GP Int 2 */
#define	E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3 /* GP Int 3 */
#define	E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
#define	E1000_ICS_SRPD   E1000_ICR_SRPD
#define	E1000_ICS_ACK   E1000_ICR_ACK /* Receive Ack frame */
#define	E1000_ICS_MNG   E1000_ICR_MNG /* Manageability event */
#define	E1000_ICS_DOCK   E1000_ICR_DOCK /* Dock/Undock */
#define	E1000_ICS_RXD_FIFO_PAR0
#define	E1000_ICS_TXD_FIFO_PAR0
#define	E1000_ICS_HOST_ARB_PAR
#define	E1000_ICS_PB_PAR
#define	E1000_ICS_RXD_FIFO_PAR1
#define	E1000_ICS_TXD_FIFO_PAR1
#define	E1000_ICS_DSW   E1000_ICR_DSW
#define	E1000_ICS_DOUTSYNC   E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
#define	E1000_ICS_PHYINT   E1000_ICR_PHYINT
#define	E1000_ICS_EPRST   E1000_ICR_EPRST
#define	E1000_TXDCTL_PTHRESH   0x0000003F /* TXDCTL Prefetch Threshold */
#define	E1000_TXDCTL_HTHRESH   0x00003F00 /* TXDCTL Host Threshold */
#define	E1000_TXDCTL_WTHRESH   0x003F0000 /* TXDCTL Writeback Threshold */
#define	E1000_TXDCTL_GRAN   0x01000000 /* TXDCTL Granularity */
#define	E1000_TXDCTL_LWTHRESH   0xFE000000 /* TXDCTL Low Threshold */
#define	E1000_TXDCTL_FULL_TX_DESC_WB   0x01010000 /* GRAN=1, WTHRESH=1 */
#define	E1000_TXDCTL_MAX_TX_DESC_PREFETCH   0x0100001F /* GRAN=1, PTHRESH=31 */
#define	E1000_TXDCTL_COUNT_DESC   0x00400000
#define	FLOW_CONTROL_ADDRESS_LOW   0x00C28001
#define	FLOW_CONTROL_ADDRESS_HIGH   0x00000100
#define	FLOW_CONTROL_TYPE   0x8808
#define	VLAN_TAG_SIZE   4 /* 802.3ac tag (not DMA'd) */
#define	E1000_VLAN_FILTER_TBL_SIZE   128 /* VLAN Filter Table (4096 bits) */
#define	E1000_RAR_ENTRIES   15
#define	E1000_RAH_AV   0x80000000 /* Receive descriptor valid */
#define	E1000_RAL_MAC_ADDR_LEN   4
#define	E1000_RAH_MAC_ADDR_LEN   2
#define	E1000_RAH_POOL_MASK   0x03FC0000
#define	E1000_RAH_POOL_1   0x00040000
#define	E1000_SUCCESS   0
#define	E1000_ERR_NVM   1
#define	E1000_ERR_PHY   2
#define	E1000_ERR_CONFIG   3
#define	E1000_ERR_PARAM   4
#define	E1000_ERR_MAC_INIT   5
#define	E1000_ERR_PHY_TYPE   6
#define	E1000_ERR_RESET   9
#define	E1000_ERR_MASTER_REQUESTS_PENDING   10
#define	E1000_ERR_HOST_INTERFACE_COMMAND   11
#define	E1000_BLK_PHY_RESET   12
#define	E1000_ERR_SWFW_SYNC   13
#define	E1000_NOT_IMPLEMENTED   14
#define	E1000_ERR_MBX   15
#define	FIBER_LINK_UP_LIMIT   50
#define	COPPER_LINK_UP_LIMIT   10
#define	PHY_AUTO_NEG_LIMIT   45
#define	PHY_FORCE_LIMIT   20
#define	MASTER_DISABLE_TIMEOUT   800
#define	PHY_CFG_TIMEOUT   100
#define	MDIO_OWNERSHIP_TIMEOUT   10
#define	AUTO_READ_DONE_TIMEOUT   10
#define	E1000_FCRTH_RTH   0x0000FFF8 /* Mask Bits[15:3] for RTH */
#define	E1000_FCRTH_XFCE   0x80000000 /* External Flow Control Enable */
#define	E1000_FCRTL_RTL   0x0000FFF8 /* Mask Bits[15:3] for RTL */
#define	E1000_FCRTL_XONE   0x80000000 /* Enable XON frame transmission */
#define	E1000_TXCW_FD   0x00000020 /* TXCW full duplex */
#define	E1000_TXCW_HD   0x00000040 /* TXCW half duplex */
#define	E1000_TXCW_PAUSE   0x00000080 /* TXCW sym pause request */
#define	E1000_TXCW_ASM_DIR   0x00000100 /* TXCW astm pause direction */
#define	E1000_TXCW_PAUSE_MASK   0x00000180 /* TXCW pause request mask */
#define	E1000_TXCW_RF   0x00003000 /* TXCW remote fault */
#define	E1000_TXCW_NP   0x00008000 /* TXCW next page */
#define	E1000_TXCW_CW   0x0000ffff /* TxConfigWord mask */
#define	E1000_TXCW_TXC   0x40000000 /* Transmit Config control */
#define	E1000_TXCW_ANE   0x80000000 /* Auto-neg enable */
#define	E1000_RXCW_CW   0x0000ffff /* RxConfigWord mask */
#define	E1000_RXCW_NC   0x04000000 /* Receive config no carrier */
#define	E1000_RXCW_IV   0x08000000 /* Receive config invalid */
#define	E1000_RXCW_CC   0x10000000 /* Receive config change */
#define	E1000_RXCW_C   0x20000000 /* Receive config */
#define	E1000_RXCW_SYNCH   0x40000000 /* Receive config synch */
#define	E1000_RXCW_ANC   0x80000000 /* Auto-neg complete */
#define	E1000_GCR_RXD_NO_SNOOP   0x00000001
#define	E1000_GCR_RXDSCW_NO_SNOOP   0x00000002
#define	E1000_GCR_RXDSCR_NO_SNOOP   0x00000004
#define	E1000_GCR_TXD_NO_SNOOP   0x00000008
#define	E1000_GCR_TXDSCW_NO_SNOOP   0x00000010
#define	E1000_GCR_TXDSCR_NO_SNOOP   0x00000020
#define	E1000_GCR_CMPL_TMOUT_MASK   0x0000F000
#define	E1000_GCR_CMPL_TMOUT_10ms   0x00001000
#define	E1000_GCR_CMPL_TMOUT_RESEND   0x00010000
#define	E1000_GCR_CAP_VER2   0x00040000
#define	PCIE_NO_SNOOP_ALL
#define	MII_CR_SPEED_SELECT_MSB   0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define	MII_CR_COLL_TEST_ENABLE   0x0080 /* Collision test enable */
#define	MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */
#define	MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */
#define	MII_CR_ISOLATE   0x0400 /* Isolate PHY from MII */
#define	MII_CR_POWER_DOWN   0x0800 /* Power down */
#define	MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */
#define	MII_CR_SPEED_SELECT_LSB   0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define	MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */
#define	MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */
#define	MII_CR_SPEED_1000   0x0040
#define	MII_CR_SPEED_100   0x2000
#define	MII_CR_SPEED_10   0x0000
#define	MII_SR_EXTENDED_CAPS   0x0001 /* Extended register capabilities */
#define	MII_SR_JABBER_DETECT   0x0002 /* Jabber Detected */
#define	MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */
#define	MII_SR_AUTONEG_CAPS   0x0008 /* Auto Neg Capable */
#define	MII_SR_REMOTE_FAULT   0x0010 /* Remote Fault Detect */
#define	MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */
#define	MII_SR_PREAMBLE_SUPPRESS   0x0040 /* Preamble may be suppressed */
#define	MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
#define	MII_SR_100T2_HD_CAPS   0x0200 /* 100T2 Half Duplex Capable */
#define	MII_SR_100T2_FD_CAPS   0x0400 /* 100T2 Full Duplex Capable */
#define	MII_SR_10T_HD_CAPS   0x0800 /* 10T Half Duplex Capable */
#define	MII_SR_10T_FD_CAPS   0x1000 /* 10T Full Duplex Capable */
#define	MII_SR_100X_HD_CAPS   0x2000 /* 100X Half Duplex Capable */
#define	MII_SR_100X_FD_CAPS   0x4000 /* 100X Full Duplex Capable */
#define	MII_SR_100T4_CAPS   0x8000 /* 100T4 Capable */
#define	NWAY_AR_SELECTOR_FIELD   0x0001 /* indicates IEEE 802.3 CSMA/CD */
#define	NWAY_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */
#define	NWAY_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */
#define	NWAY_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */
#define	NWAY_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */
#define	NWAY_AR_100T4_CAPS   0x0200 /* 100T4 Capable */
#define	NWAY_AR_PAUSE   0x0400 /* Pause operation desired */
#define	NWAY_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */
#define	NWAY_AR_REMOTE_FAULT   0x2000 /* Remote Fault detected */
#define	NWAY_AR_NEXT_PAGE   0x8000 /* Next Page ability supported */
#define	NWAY_LPAR_SELECTOR_FIELD   0x0000 /* LP protocol selector field */
#define	NWAY_LPAR_10T_HD_CAPS   0x0020 /* LP is 10T Half Duplex Capable */
#define	NWAY_LPAR_10T_FD_CAPS   0x0040 /* LP is 10T Full Duplex Capable */
#define	NWAY_LPAR_100TX_HD_CAPS   0x0080 /* LP is 100TX Half Duplex Capable */
#define	NWAY_LPAR_100TX_FD_CAPS   0x0100 /* LP is 100TX Full Duplex Capable */
#define	NWAY_LPAR_100T4_CAPS   0x0200 /* LP is 100T4 Capable */
#define	NWAY_LPAR_PAUSE   0x0400 /* LP Pause operation desired */
#define	NWAY_LPAR_ASM_DIR   0x0800 /* LP Asymmetric Pause Direction bit */
#define	NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
#define	NWAY_LPAR_ACKNOWLEDGE   0x4000 /* LP has rx'd link code word */
#define	NWAY_LPAR_NEXT_PAGE   0x8000 /* Next Page ability supported */
#define	NWAY_ER_LP_NWAY_CAPS   0x0001 /* LP has Auto Neg Capability */
#define	NWAY_ER_PAGE_RXD   0x0002 /* LP is 10T Half Duplex Capable */
#define	NWAY_ER_NEXT_PAGE_CAPS   0x0004 /* LP is 10T Full Duplex Capable */
#define	NWAY_ER_LP_NEXT_PAGE_CAPS   0x0008 /* LP is 100TX Half Duplex Capable */
#define	NWAY_ER_PAR_DETECT_FAULT   0x0010 /* LP is 100TX Full Duplex Capable */
#define	CR_1000T_ASYM_PAUSE   0x0080 /* Advertise asymmetric pause bit */
#define	CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */
#define	CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */
#define	CR_1000T_REPEATER_DTE   0x0400 /* 1=Repeater/switch device port */
#define	CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */
#define	CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */
#define	CR_1000T_TEST_MODE_NORMAL   0x0000 /* Normal Operation */
#define	CR_1000T_TEST_MODE_1   0x2000 /* Transmit Waveform test */
#define	CR_1000T_TEST_MODE_2   0x4000 /* Master Transmit Jitter test */
#define	CR_1000T_TEST_MODE_3   0x6000 /* Slave Transmit Jitter test */
#define	CR_1000T_TEST_MODE_4   0x8000 /* Transmitter Distortion test */
#define	SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
#define	SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
#define	SR_1000T_LP_HD_CAPS   0x0400 /* LP is 1000T HD capable */
#define	SR_1000T_LP_FD_CAPS   0x0800 /* LP is 1000T FD capable */
#define	SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */
#define	SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */
#define	SR_1000T_MS_CONFIG_RES   0x4000 /* 1=Local Tx is Master, 0=Slave */
#define	SR_1000T_MS_CONFIG_FAULT   0x8000 /* Master/Slave config fault */
#define	SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT   5
#define	PHY_CONTROL   0x00 /* Control Register */
#define	PHY_STATUS   0x01 /* Status Register */
#define	PHY_ID1   0x02 /* Phy Id Reg (word 1) */
#define	PHY_ID2   0x03 /* Phy Id Reg (word 2) */
#define	PHY_AUTONEG_ADV   0x04 /* Autoneg Advertisement */
#define	PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
#define	PHY_AUTONEG_EXP   0x06 /* Autoneg Expansion Reg */
#define	PHY_NEXT_PAGE_TX   0x07 /* Next Page Tx */
#define	PHY_LP_NEXT_PAGE   0x08 /* Link Partner Next Page */
#define	PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
#define	PHY_1000T_STATUS   0x0A /* 1000Base-T Status Reg */
#define	PHY_EXT_STATUS   0x0F /* Extended Status Reg */
#define	PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
#define	E1000_EECD_SK   0x00000001 /* NVM Clock */
#define	E1000_EECD_CS   0x00000002 /* NVM Chip Select */
#define	E1000_EECD_DI   0x00000004 /* NVM Data In */
#define	E1000_EECD_DO   0x00000008 /* NVM Data Out */
#define	E1000_EECD_FWE_MASK   0x00000030
#define	E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
#define	E1000_EECD_FWE_EN   0x00000020 /* Enable FLASH writes */
#define	E1000_EECD_FWE_SHIFT   4
#define	E1000_EECD_REQ   0x00000040 /* NVM Access Request */
#define	E1000_EECD_GNT   0x00000080 /* NVM Access Grant */
#define	E1000_EECD_PRES   0x00000100 /* NVM Present */
#define	E1000_EECD_SIZE   0x00000200 /* NVM Size (0=64 word 1=256 word) */
#define	E1000_EECD_ADDR_BITS   0x00000400
#define	E1000_EECD_TYPE   0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
#define	E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
#define	E1000_EECD_AUTO_RD   0x00000200 /* NVM Auto Read done */
#define	E1000_EECD_SIZE_EX_MASK   0x00007800 /* NVM Size */
#define	E1000_EECD_SIZE_EX_SHIFT   11
#define	E1000_EECD_NVADDS   0x00018000 /* NVM Address Size */
#define	E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
#define	E1000_EECD_INITSRAM   0x00040000 /* Initialize Shadow RAM */
#define	E1000_EECD_FLUPD   0x00080000 /* Update FLASH */
#define	E1000_EECD_AUPDEN   0x00100000 /* Enable Autonomous FLASH update */
#define	E1000_EECD_SHADV   0x00200000 /* Shadow RAM Data Valid */
#define	E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
#define	E1000_EECD_SECVAL_SHIFT   22
#define	E1000_EECD_SEC1VAL_VALID_MASK   (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
#define	E1000_NVM_SWDPIN0   0x0001 /* SWDPIN 0 NVM Value */
#define	E1000_NVM_LED_LOGIC   0x0020 /* Led Logic Word */
#define	E1000_NVM_RW_REG_DATA   16 /* Offset to data in NVM read/write regs */
#define	E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */
#define	E1000_NVM_RW_REG_START   1 /* Start operation */
#define	E1000_NVM_RW_ADDR_SHIFT   2 /* Shift to the address bits */
#define	E1000_NVM_POLL_WRITE   1 /* Flag for polling for write complete */
#define	E1000_NVM_POLL_READ   0 /* Flag for polling for read complete */
#define	E1000_FLASH_UPDATES   2000
#define	NVM_COMPAT   0x0003
#define	NVM_ID_LED_SETTINGS   0x0004
#define	NVM_VERSION   0x0005
#define	NVM_SERDES_AMPLITUDE   0x0006 /* SERDES output amplitude */
#define	NVM_PHY_CLASS_WORD   0x0007
#define	NVM_INIT_CONTROL1_REG   0x000A
#define	NVM_INIT_CONTROL2_REG   0x000F
#define	NVM_SWDEF_PINS_CTRL_PORT_1   0x0010
#define	NVM_INIT_CONTROL3_PORT_B   0x0014
#define	NVM_INIT_3GIO_3   0x001A
#define	NVM_SWDEF_PINS_CTRL_PORT_0   0x0020
#define	NVM_INIT_CONTROL3_PORT_A   0x0024
#define	NVM_CFG   0x0012
#define	NVM_FLASH_VERSION   0x0032
#define	NVM_ALT_MAC_ADDR_PTR   0x0037
#define	NVM_CHECKSUM_REG   0x003F
#define	E1000_NVM_CFG_DONE_PORT_0   0x040000 /* MNG config cycle done */
#define	E1000_NVM_CFG_DONE_PORT_1   0x080000 /* ...for second port */
#define	NVM_WORD0F_PAUSE_MASK   0x3000
#define	NVM_WORD0F_PAUSE   0x1000
#define	NVM_WORD0F_ASM_DIR   0x2000
#define	NVM_WORD0F_ANE   0x0800
#define	NVM_WORD0F_SWPDIO_EXT_MASK   0x00F0
#define	NVM_WORD0F_LPLU   0x0001
#define	NVM_WORD1A_ASPM_MASK   0x000C
#define	NVM_SUM   0xBABA
#define	NVM_MAC_ADDR_OFFSET   0
#define	NVM_PBA_OFFSET_0   8
#define	NVM_PBA_OFFSET_1   9
#define	NVM_RESERVED_WORD   0xFFFF
#define	NVM_PHY_CLASS_A   0x8000
#define	NVM_SERDES_AMPLITUDE_MASK   0x000F
#define	NVM_SIZE_MASK   0x1C00
#define	NVM_SIZE_SHIFT   10
#define	NVM_WORD_SIZE_BASE_SHIFT   6
#define	NVM_SWDPIO_EXT_SHIFT   4
#define	NVM_MAX_RETRY_SPI   5000 /* Max wait of 5ms, for RDY signal */
#define	NVM_READ_OPCODE_SPI   0x03 /* NVM read opcode */
#define	NVM_WRITE_OPCODE_SPI   0x02 /* NVM write opcode */
#define	NVM_A8_OPCODE_SPI   0x08 /* opcode bit-3 = address bit-8 */
#define	NVM_WREN_OPCODE_SPI   0x06 /* NVM set Write Enable latch */
#define	NVM_WRDI_OPCODE_SPI   0x04 /* NVM reset Write Enable latch */
#define	NVM_RDSR_OPCODE_SPI   0x05 /* NVM read Status register */
#define	NVM_WRSR_OPCODE_SPI   0x01 /* NVM write Status register */
#define	NVM_STATUS_RDY_SPI   0x01
#define	NVM_STATUS_WEN_SPI   0x02
#define	NVM_STATUS_BP0_SPI   0x04
#define	NVM_STATUS_BP1_SPI   0x08
#define	NVM_STATUS_WPEN_SPI   0x80
#define	ID_LED_RESERVED_0000   0x0000
#define	ID_LED_RESERVED_FFFF   0xFFFF
#define	ID_LED_DEFAULT
#define	ID_LED_DEF1_DEF2   0x1
#define	ID_LED_DEF1_ON2   0x2
#define	ID_LED_DEF1_OFF2   0x3
#define	ID_LED_ON1_DEF2   0x4
#define	ID_LED_ON1_ON2   0x5
#define	ID_LED_ON1_OFF2   0x6
#define	ID_LED_OFF1_DEF2   0x7
#define	ID_LED_OFF1_ON2   0x8
#define	ID_LED_OFF1_OFF2   0x9
#define	IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
#define	IGP_ACTIVITY_LED_ENABLE   0x0300
#define	IGP_LED3_MODE   0x07000000
#define	PCI_HEADER_TYPE_REGISTER   0x0E
#define	PCIE_LINK_STATUS   0x12
#define	PCIE_DEVICE_CONTROL2   0x28
#define	PCI_HEADER_TYPE_MULTIFUNC   0x80
#define	PCIE_LINK_WIDTH_MASK   0x3F0
#define	PCIE_LINK_WIDTH_SHIFT   4
#define	PCIE_DEVICE_CONTROL2_16ms   0x0005
#define	ETH_ADDR_LEN   6
#define	PHY_REVISION_MASK   0xFFFFFFF0
#define	MAX_PHY_REG_ADDRESS   0x1F /* 5 bit address bus (0-0x1F) */
#define	MAX_PHY_MULTI_PAGE_REG   0xF
#define	M88E1000_E_PHY_ID   0x01410C50
#define	M88E1000_I_PHY_ID   0x01410C30
#define	M88E1011_I_PHY_ID   0x01410C20
#define	IGP01E1000_I_PHY_ID   0x02A80380
#define	M88E1011_I_REV_4   0x04
#define	M88E1111_I_PHY_ID   0x01410CC0
#define	GG82563_E_PHY_ID   0x01410CA0
#define	IGP03E1000_E_PHY_ID   0x02A80390
#define	IFE_E_PHY_ID   0x02A80330
#define	IFE_PLUS_E_PHY_ID   0x02A80320
#define	IFE_C_E_PHY_ID   0x02A80310
#define	M88_VENDOR   0x0141
#define	M88E1000_PHY_SPEC_CTRL   0x10 /* PHY Specific Control Register */
#define	M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */
#define	M88E1000_INT_ENABLE   0x12 /* Interrupt Enable Register */
#define	M88E1000_INT_STATUS   0x13 /* Interrupt Status Register */
#define	M88E1000_EXT_PHY_SPEC_CTRL   0x14 /* Extended PHY Specific Control */
#define	M88E1000_RX_ERR_CNTR   0x15 /* Receive Error Counter */
#define	M88E1000_PHY_EXT_CTRL   0x1A /* PHY extend control register */
#define	M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */
#define	M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */
#define	M88E1000_PHY_VCO_REG_BIT8   0x100 /* Bits 8 & 11 are adjusted for */
#define	M88E1000_PHY_VCO_REG_BIT11   0x800 /* improved BER performance */
#define	M88E1000_PSCR_JABBER_DISABLE   0x0001 /* 1=Jabber Function disabled */
#define	M88E1000_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reverse enabled */
#define	M88E1000_PSCR_SQE_TEST   0x0004 /* 1=SQE Test enabled */
#define	M88E1000_PSCR_CLK125_DISABLE   0x0010
#define	M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */
#define	M88E1000_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */
#define	M88E1000_PSCR_AUTO_X_1000T   0x0040
#define	M88E1000_PSCR_AUTO_X_MODE   0x0060
#define	M88E1000_PSCR_EN_10BT_EXT_DIST   0x0080
#define	M88E1000_PSCR_MII_5BIT_ENABLE   0x0100
#define	M88E1000_PSCR_SCRAMBLER_DISABLE   0x0200 /* 1=Scrambler disable */
#define	M88E1000_PSCR_FORCE_LINK_GOOD   0x0400 /* 1=Force link good */
#define	M88E1000_PSCR_ASSERT_CRS_ON_TX   0x0800 /* 1=Assert CRS on Tx */
#define	M88E1000_PSSR_JABBER   0x0001 /* 1=Jabber */
#define	M88E1000_PSSR_REV_POLARITY   0x0002 /* 1=Polarity reversed */
#define	M88E1000_PSSR_DOWNSHIFT   0x0020 /* 1=Downshifted */
#define	M88E1000_PSSR_MDIX   0x0040 /* 1=MDIX; 0=MDI */
#define	M88E1000_PSSR_CABLE_LENGTH   0x0380
#define	M88E1000_PSSR_LINK   0x0400 /* 1=Link up, 0=Link down */
#define	M88E1000_PSSR_SPD_DPLX_RESOLVED   0x0800 /* 1=Speed & Duplex resolved */
#define	M88E1000_PSSR_PAGE_RCVD   0x1000 /* 1=Page received */
#define	M88E1000_PSSR_DPLX   0x2000 /* 1=Duplex 0=Half Duplex */
#define	M88E1000_PSSR_SPEED   0xC000 /* Speed, bits 14:15 */
#define	M88E1000_PSSR_10MBS   0x0000 /* 00=10Mbs */
#define	M88E1000_PSSR_100MBS   0x4000 /* 01=100Mbs */
#define	M88E1000_PSSR_1000MBS   0x8000 /* 10=1000Mbs */
#define	M88E1000_PSSR_CABLE_LENGTH_SHIFT   7
#define	M88E1000_EPSCR_FIBER_LOOPBACK   0x4000 /* 1=Fiber loopback */
#define	M88E1000_EPSCR_DOWN_NO_IDLE   0x8000
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK   0x0C00
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
#define	M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK   0x0300
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X   0x0100
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X   0x0200
#define	M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X   0x0300
#define	M88E1000_EPSCR_TX_CLK_2_5   0x0060 /* 2.5 MHz TX_CLK */
#define	M88E1000_EPSCR_TX_CLK_25   0x0070 /* 25 MHz TX_CLK */
#define	M88E1000_EPSCR_TX_CLK_0   0x0000 /* NO TX_CLK */
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK   0x0E00
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X   0x0000
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X   0x0200
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X   0x0400
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X   0x0600
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X   0x0800
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X   0x0A00
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X   0x0C00
#define	M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X   0x0E00
#define	GG82563_PAGE_SHIFT   5
#define	GG82563_REG(page, reg)   (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
#define	GG82563_MIN_ALT_REG   30
#define	GG82563_PHY_SPEC_CTRL   GG82563_REG(0, 16) /* PHY Specific Control */
#define	GG82563_PHY_SPEC_STATUS   GG82563_REG(0, 17) /* PHY Specific Status */
#define	GG82563_PHY_INT_ENABLE   GG82563_REG(0, 18) /* Interrupt Enable */
#define	GG82563_PHY_SPEC_STATUS_2   GG82563_REG(0, 19) /* PHY Specific Status 2 */
#define	GG82563_PHY_RX_ERR_CNTR   GG82563_REG(0, 21) /* Receive Error Counter */
#define	GG82563_PHY_PAGE_SELECT   GG82563_REG(0, 22) /* Page Select */
#define	GG82563_PHY_SPEC_CTRL_2   GG82563_REG(0, 26) /* PHY Specific Control 2 */
#define	GG82563_PHY_PAGE_SELECT_ALT   GG82563_REG(0, 29) /* Alternate Page Select */
#define	GG82563_PHY_TEST_CLK_CTRL   GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
#define	GG82563_PHY_MAC_SPEC_CTRL   GG82563_REG(2, 21) /* MAC Specific Control Register */
#define	GG82563_PHY_MAC_SPEC_CTRL_2   GG82563_REG(2, 26) /* MAC Specific Control 2 */
#define	GG82563_PHY_DSP_DISTANCE   GG82563_REG(5, 26) /* DSP Distance */
#define	GG82563_PHY_KMRN_MODE_CTRL   GG82563_REG(193, 16) /* Kumeran Mode Control */
#define	GG82563_PHY_PORT_RESET   GG82563_REG(193, 17) /* Port Reset */
#define	GG82563_PHY_REVISION_ID   GG82563_REG(193, 18) /* Revision ID */
#define	GG82563_PHY_DEVICE_ID   GG82563_REG(193, 19) /* Device ID */
#define	GG82563_PHY_PWR_MGMT_CTRL   GG82563_REG(193, 20) /* Power Management Control */
#define	GG82563_PHY_RATE_ADAPT_CTRL   GG82563_REG(193, 25) /* Rate Adaptation Control */
#define	GG82563_PHY_KMRN_FIFO_CTRL_STAT   GG82563_REG(194, 16) /* FIFO's Control/Status */
#define	GG82563_PHY_KMRN_CTRL   GG82563_REG(194, 17) /* Control */
#define	GG82563_PHY_INBAND_CTRL   GG82563_REG(194, 18) /* Inband Control */
#define	GG82563_PHY_KMRN_DIAGNOSTIC   GG82563_REG(194, 19) /* Diagnostic */
#define	GG82563_PHY_ACK_TIMEOUTS   GG82563_REG(194, 20) /* Acknowledge Timeouts */
#define	GG82563_PHY_ADV_ABILITY   GG82563_REG(194, 21) /* Advertised Ability */
#define	GG82563_PHY_LINK_PARTNER_ADV_ABILITY   GG82563_REG(194, 23) /* Link Partner Advertised Ability */
#define	GG82563_PHY_ADV_NEXT_PAGE   GG82563_REG(194, 24) /* Advertised Next Page */
#define	GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE   GG82563_REG(194, 25) /* Link Partner Advertised Next page */
#define	GG82563_PHY_KMRN_MISC   GG82563_REG(194, 26) /* Misc. */
#define	E1000_MDIC_DATA_MASK   0x0000FFFF
#define	E1000_MDIC_REG_MASK   0x001F0000
#define	E1000_MDIC_REG_SHIFT   16
#define	E1000_MDIC_PHY_MASK   0x03E00000
#define	E1000_MDIC_PHY_SHIFT   21
#define	E1000_MDIC_OP_WRITE   0x04000000
#define	E1000_MDIC_OP_READ   0x08000000
#define	E1000_MDIC_READY   0x10000000
#define	E1000_MDIC_INT_EN   0x20000000
#define	E1000_MDIC_ERROR   0x40000000
#define	E1000_GEN_CTL_READY   0x80000000
#define	E1000_GEN_CTL_ADDRESS_SHIFT   8
#define	E1000_GEN_POLL_TIMEOUT   640

Functions
	FILE_LICENCE (GPL2_ONLY)

Macro Definition Documentation

_IGBVF_DEFINES_H_

#define _IGBVF_DEFINES_H_

Definition at line 32 of file igbvf_defines.h.

REQ_TX_DESCRIPTOR_MULTIPLE

#define REQ_TX_DESCRIPTOR_MULTIPLE   8

Definition at line 35 of file igbvf_defines.h.

REQ_RX_DESCRIPTOR_MULTIPLE

#define REQ_RX_DESCRIPTOR_MULTIPLE   8

Definition at line 36 of file igbvf_defines.h.

E1000_WUC_APME

#define E1000_WUC_APME   0x00000001 /* APM Enable */

Definition at line 40 of file igbvf_defines.h.

E1000_WUC_PME_EN

#define E1000_WUC_PME_EN   0x00000002 /* PME Enable */

Definition at line 41 of file igbvf_defines.h.

E1000_WUC_PME_STATUS

#define E1000_WUC_PME_STATUS   0x00000004 /* PME Status */

Definition at line 42 of file igbvf_defines.h.

E1000_WUC_APMPME

#define E1000_WUC_APMPME   0x00000008 /* Assert PME on APM Wakeup */

Definition at line 43 of file igbvf_defines.h.

E1000_WUC_LSCWE

#define E1000_WUC_LSCWE   0x00000010 /* Link Status wake up enable */

Definition at line 44 of file igbvf_defines.h.

E1000_WUC_LSCWO

#define E1000_WUC_LSCWO   0x00000020 /* Link Status wake up override */

Definition at line 45 of file igbvf_defines.h.

E1000_WUC_SPM

#define E1000_WUC_SPM   0x80000000 /* Enable SPM */

Definition at line 46 of file igbvf_defines.h.

E1000_WUC_PHY_WAKE

#define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */

Definition at line 47 of file igbvf_defines.h.

E1000_WUFC_LNKC

#define E1000_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */

Definition at line 50 of file igbvf_defines.h.

E1000_WUFC_MAG

#define E1000_WUFC_MAG   0x00000002 /* Magic Packet Wakeup Enable */

Definition at line 51 of file igbvf_defines.h.

E1000_WUFC_EX

#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */

Definition at line 52 of file igbvf_defines.h.

E1000_WUFC_MC

#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */

Definition at line 53 of file igbvf_defines.h.

E1000_WUFC_BC

#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */

Definition at line 54 of file igbvf_defines.h.

E1000_WUFC_ARP

#define E1000_WUFC_ARP   0x00000020 /* ARP Request Packet Wakeup Enable */

Definition at line 55 of file igbvf_defines.h.

E1000_WUFC_IPV4

#define E1000_WUFC_IPV4   0x00000040 /* Directed IPv4 Packet Wakeup Enable */

Definition at line 56 of file igbvf_defines.h.

E1000_WUFC_IPV6

#define E1000_WUFC_IPV6   0x00000080 /* Directed IPv6 Packet Wakeup Enable */

Definition at line 57 of file igbvf_defines.h.

E1000_WUFC_IGNORE_TCO

#define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */

Definition at line 58 of file igbvf_defines.h.

E1000_WUFC_FLX0

#define E1000_WUFC_FLX0   0x00010000 /* Flexible Filter 0 Enable */

Definition at line 59 of file igbvf_defines.h.

E1000_WUFC_FLX1

#define E1000_WUFC_FLX1   0x00020000 /* Flexible Filter 1 Enable */

Definition at line 60 of file igbvf_defines.h.

E1000_WUFC_FLX2

#define E1000_WUFC_FLX2   0x00040000 /* Flexible Filter 2 Enable */

Definition at line 61 of file igbvf_defines.h.

E1000_WUFC_FLX3

#define E1000_WUFC_FLX3   0x00080000 /* Flexible Filter 3 Enable */

Definition at line 62 of file igbvf_defines.h.

E1000_WUFC_ALL_FILTERS

#define E1000_WUFC_ALL_FILTERS   0x000F00FF /* Mask for all wakeup filters */

Definition at line 63 of file igbvf_defines.h.

E1000_WUFC_FLX_OFFSET

#define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */

Definition at line 64 of file igbvf_defines.h.

E1000_WUFC_FLX_FILTERS

#define E1000_WUFC_FLX_FILTERS   0x000F0000 /*Mask for the 4 flexible filters */

Definition at line 65 of file igbvf_defines.h.

E1000_WUS_LNKC

#define E1000_WUS_LNKC   E1000_WUFC_LNKC

Definition at line 68 of file igbvf_defines.h.

E1000_WUS_MAG

#define E1000_WUS_MAG   E1000_WUFC_MAG

Definition at line 69 of file igbvf_defines.h.

E1000_WUS_EX

#define E1000_WUS_EX   E1000_WUFC_EX

Definition at line 70 of file igbvf_defines.h.

E1000_WUS_MC

#define E1000_WUS_MC   E1000_WUFC_MC

Definition at line 71 of file igbvf_defines.h.

E1000_WUS_BC

#define E1000_WUS_BC   E1000_WUFC_BC

Definition at line 72 of file igbvf_defines.h.

E1000_WUS_ARP

#define E1000_WUS_ARP   E1000_WUFC_ARP

Definition at line 73 of file igbvf_defines.h.

E1000_WUS_IPV4

#define E1000_WUS_IPV4   E1000_WUFC_IPV4

Definition at line 74 of file igbvf_defines.h.

E1000_WUS_IPV6

#define E1000_WUS_IPV6   E1000_WUFC_IPV6

Definition at line 75 of file igbvf_defines.h.

E1000_WUS_FLX0

#define E1000_WUS_FLX0   E1000_WUFC_FLX0

Definition at line 76 of file igbvf_defines.h.

E1000_WUS_FLX1

#define E1000_WUS_FLX1   E1000_WUFC_FLX1

Definition at line 77 of file igbvf_defines.h.

E1000_WUS_FLX2

#define E1000_WUS_FLX2   E1000_WUFC_FLX2

Definition at line 78 of file igbvf_defines.h.

E1000_WUS_FLX3

#define E1000_WUS_FLX3   E1000_WUFC_FLX3

Definition at line 79 of file igbvf_defines.h.

E1000_WUS_FLX_FILTERS

#define E1000_WUS_FLX_FILTERS   E1000_WUFC_FLX_FILTERS

Definition at line 80 of file igbvf_defines.h.

E1000_WUPL_LENGTH_MASK

#define E1000_WUPL_LENGTH_MASK   0x0FFF /* Only the lower 12 bits are valid */

Definition at line 83 of file igbvf_defines.h.

E1000_FLEXIBLE_FILTER_COUNT_MAX

#define E1000_FLEXIBLE_FILTER_COUNT_MAX   4

Definition at line 86 of file igbvf_defines.h.

E1000_FLEXIBLE_FILTER_SIZE_MAX

#define E1000_FLEXIBLE_FILTER_SIZE_MAX   128

Definition at line 89 of file igbvf_defines.h.

E1000_FFLT_SIZE

#define E1000_FFLT_SIZE   E1000_FLEXIBLE_FILTER_COUNT_MAX

Definition at line 91 of file igbvf_defines.h.

E1000_FFMT_SIZE

#define E1000_FFMT_SIZE   E1000_FLEXIBLE_FILTER_SIZE_MAX

Definition at line 92 of file igbvf_defines.h.

E1000_FFVT_SIZE

#define E1000_FFVT_SIZE   E1000_FLEXIBLE_FILTER_SIZE_MAX

Definition at line 93 of file igbvf_defines.h.

E1000_CTRL_EXT_GPI0_EN

#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */

Definition at line 96 of file igbvf_defines.h.

E1000_CTRL_EXT_GPI1_EN

#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */

Definition at line 97 of file igbvf_defines.h.

E1000_CTRL_EXT_PHYINT_EN

#define E1000_CTRL_EXT_PHYINT_EN   E1000_CTRL_EXT_GPI1_EN

Definition at line 98 of file igbvf_defines.h.

E1000_CTRL_EXT_GPI2_EN

#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */

Definition at line 99 of file igbvf_defines.h.

E1000_CTRL_EXT_GPI3_EN

#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */

Definition at line 100 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP4_DATA

#define E1000_CTRL_EXT_SDP4_DATA   0x00000010 /* Value of SW Definable Pin 4 */

Definition at line 102 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP5_DATA

#define E1000_CTRL_EXT_SDP5_DATA   0x00000020 /* Value of SW Definable Pin 5 */

Definition at line 103 of file igbvf_defines.h.

E1000_CTRL_EXT_PHY_INT

#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA

Definition at line 104 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP6_DATA

#define E1000_CTRL_EXT_SDP6_DATA   0x00000040 /* Value of SW Definable Pin 6 */

Definition at line 105 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP3_DATA

#define E1000_CTRL_EXT_SDP3_DATA   0x00000080 /* Value of SW Definable Pin 3 */

Definition at line 106 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP4_DIR

#define E1000_CTRL_EXT_SDP4_DIR   0x00000100 /* Direction of SDP4 0=in 1=out */

Definition at line 108 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP5_DIR

#define E1000_CTRL_EXT_SDP5_DIR   0x00000200 /* Direction of SDP5 0=in 1=out */

Definition at line 109 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP6_DIR

#define E1000_CTRL_EXT_SDP6_DIR   0x00000400 /* Direction of SDP6 0=in 1=out */

Definition at line 110 of file igbvf_defines.h.

E1000_CTRL_EXT_SDP3_DIR

#define E1000_CTRL_EXT_SDP3_DIR   0x00000800 /* Direction of SDP3 0=in 1=out */

Definition at line 111 of file igbvf_defines.h.

E1000_CTRL_EXT_ASDCHK

#define E1000_CTRL_EXT_ASDCHK   0x00001000 /* Initiate an ASD sequence */

Definition at line 112 of file igbvf_defines.h.

E1000_CTRL_EXT_EE_RST

#define E1000_CTRL_EXT_EE_RST   0x00002000 /* Reinitialize from EEPROM */

Definition at line 113 of file igbvf_defines.h.

E1000_CTRL_EXT_IPS

#define E1000_CTRL_EXT_IPS   0x00004000 /* Invert Power State */

Definition at line 114 of file igbvf_defines.h.

E1000_CTRL_EXT_SPD_BYPS

#define E1000_CTRL_EXT_SPD_BYPS   0x00008000 /* Speed Select Bypass */

Definition at line 115 of file igbvf_defines.h.

E1000_CTRL_EXT_RO_DIS

#define E1000_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */

Definition at line 116 of file igbvf_defines.h.

E1000_CTRL_EXT_DMA_DYN_CLK_EN

#define E1000_CTRL_EXT_DMA_DYN_CLK_EN   0x00080000 /* DMA Dynamic Clock Gating */

Definition at line 117 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_MASK

#define E1000_CTRL_EXT_LINK_MODE_MASK   0x00C00000

Definition at line 118 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_GMII

#define E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000

Definition at line 119 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_TBI

#define E1000_CTRL_EXT_LINK_MODE_TBI   0x00C00000

Definition at line 120 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_KMRN

#define E1000_CTRL_EXT_LINK_MODE_KMRN   0x00000000

Definition at line 121 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES

#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES   0x00C00000

Definition at line 122 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES

#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES   0x00800000

Definition at line 123 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_MODE_SGMII

#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000

Definition at line 124 of file igbvf_defines.h.

E1000_CTRL_EXT_EIAME

#define E1000_CTRL_EXT_EIAME   0x01000000

Definition at line 125 of file igbvf_defines.h.

E1000_CTRL_EXT_IRCA

#define E1000_CTRL_EXT_IRCA   0x00000001

Definition at line 126 of file igbvf_defines.h.

E1000_CTRL_EXT_WR_WMARK_MASK

#define E1000_CTRL_EXT_WR_WMARK_MASK   0x03000000

Definition at line 127 of file igbvf_defines.h.

E1000_CTRL_EXT_WR_WMARK_256

#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000

Definition at line 128 of file igbvf_defines.h.

E1000_CTRL_EXT_WR_WMARK_320

#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000

Definition at line 129 of file igbvf_defines.h.

E1000_CTRL_EXT_WR_WMARK_384

#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000

Definition at line 130 of file igbvf_defines.h.

E1000_CTRL_EXT_WR_WMARK_448

#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000

Definition at line 131 of file igbvf_defines.h.

E1000_CTRL_EXT_CANC

#define E1000_CTRL_EXT_CANC   0x04000000 /* Int delay cancellation */

Definition at line 132 of file igbvf_defines.h.

E1000_CTRL_EXT_DRV_LOAD

#define E1000_CTRL_EXT_DRV_LOAD   0x10000000 /* Driver loaded bit for FW */

Definition at line 133 of file igbvf_defines.h.

E1000_CTRL_EXT_IAME

#define E1000_CTRL_EXT_IAME   0x08000000 /* Int acknowledge Auto-mask */

Definition at line 135 of file igbvf_defines.h.

E1000_CRTL_EXT_PB_PAREN

#define E1000_CRTL_EXT_PB_PAREN

Value:

0x01000000 /* packet buffer parity error
                                                  * detection enabled */

Definition at line 136 of file igbvf_defines.h.

E1000_CTRL_EXT_DF_PAREN

#define E1000_CTRL_EXT_DF_PAREN

Value:

0x02000000 /* descriptor FIFO parity
                                                  * error detection enable */

Definition at line 138 of file igbvf_defines.h.

E1000_CTRL_EXT_GHOST_PAREN

#define E1000_CTRL_EXT_GHOST_PAREN   0x40000000

Definition at line 140 of file igbvf_defines.h.

E1000_CTRL_EXT_PBA_CLR

#define E1000_CTRL_EXT_PBA_CLR   0x80000000 /* PBA Clear */

Definition at line 141 of file igbvf_defines.h.

E1000_I2CCMD_REG_ADDR_SHIFT

#define E1000_I2CCMD_REG_ADDR_SHIFT   16

Definition at line 142 of file igbvf_defines.h.

E1000_I2CCMD_REG_ADDR

#define E1000_I2CCMD_REG_ADDR   0x00FF0000

Definition at line 143 of file igbvf_defines.h.

E1000_I2CCMD_PHY_ADDR_SHIFT

#define E1000_I2CCMD_PHY_ADDR_SHIFT   24

Definition at line 144 of file igbvf_defines.h.

E1000_I2CCMD_PHY_ADDR

#define E1000_I2CCMD_PHY_ADDR   0x07000000

Definition at line 145 of file igbvf_defines.h.

E1000_I2CCMD_OPCODE_READ

#define E1000_I2CCMD_OPCODE_READ   0x08000000

Definition at line 146 of file igbvf_defines.h.

E1000_I2CCMD_OPCODE_WRITE

#define E1000_I2CCMD_OPCODE_WRITE   0x00000000

Definition at line 147 of file igbvf_defines.h.

E1000_I2CCMD_RESET

#define E1000_I2CCMD_RESET   0x10000000

Definition at line 148 of file igbvf_defines.h.

E1000_I2CCMD_READY

#define E1000_I2CCMD_READY   0x20000000

Definition at line 149 of file igbvf_defines.h.

E1000_I2CCMD_INTERRUPT_ENA

#define E1000_I2CCMD_INTERRUPT_ENA   0x40000000

Definition at line 150 of file igbvf_defines.h.

E1000_I2CCMD_ERROR

#define E1000_I2CCMD_ERROR   0x80000000

Definition at line 151 of file igbvf_defines.h.

E1000_MAX_SGMII_PHY_REG_ADDR

#define E1000_MAX_SGMII_PHY_REG_ADDR   255

Definition at line 152 of file igbvf_defines.h.

E1000_I2CCMD_PHY_TIMEOUT

#define E1000_I2CCMD_PHY_TIMEOUT   200

Definition at line 153 of file igbvf_defines.h.

E1000_RXD_STAT_DD

#define E1000_RXD_STAT_DD   0x01 /* Descriptor Done */

Definition at line 156 of file igbvf_defines.h.

E1000_RXD_STAT_EOP

#define E1000_RXD_STAT_EOP   0x02 /* End of Packet */

Definition at line 157 of file igbvf_defines.h.

E1000_RXD_STAT_IXSM

#define E1000_RXD_STAT_IXSM   0x04 /* Ignore checksum */

Definition at line 158 of file igbvf_defines.h.

E1000_RXD_STAT_VP

#define E1000_RXD_STAT_VP   0x08 /* IEEE VLAN Packet */

Definition at line 159 of file igbvf_defines.h.

E1000_RXD_STAT_UDPCS

#define E1000_RXD_STAT_UDPCS   0x10 /* UDP xsum calculated */

Definition at line 160 of file igbvf_defines.h.

E1000_RXD_STAT_TCPCS

#define E1000_RXD_STAT_TCPCS   0x20 /* TCP xsum calculated */

Definition at line 161 of file igbvf_defines.h.

E1000_RXD_STAT_IPCS

#define E1000_RXD_STAT_IPCS   0x40 /* IP xsum calculated */

Definition at line 162 of file igbvf_defines.h.

E1000_RXD_STAT_PIF

#define E1000_RXD_STAT_PIF   0x80 /* passed in-exact filter */

Definition at line 163 of file igbvf_defines.h.

E1000_RXD_STAT_CRCV

#define E1000_RXD_STAT_CRCV   0x100 /* Speculative CRC Valid */

Definition at line 164 of file igbvf_defines.h.

E1000_RXD_STAT_IPIDV

#define E1000_RXD_STAT_IPIDV   0x200 /* IP identification valid */

Definition at line 165 of file igbvf_defines.h.

E1000_RXD_STAT_UDPV

#define E1000_RXD_STAT_UDPV   0x400 /* Valid UDP checksum */

Definition at line 166 of file igbvf_defines.h.

E1000_RXD_STAT_DYNINT

#define E1000_RXD_STAT_DYNINT   0x800 /* Pkt caused INT via DYNINT */

Definition at line 167 of file igbvf_defines.h.

E1000_RXD_STAT_ACK

#define E1000_RXD_STAT_ACK   0x8000 /* ACK Packet indication */

Definition at line 168 of file igbvf_defines.h.

E1000_RXD_ERR_CE

#define E1000_RXD_ERR_CE   0x01 /* CRC Error */

Definition at line 169 of file igbvf_defines.h.

E1000_RXD_ERR_SE

#define E1000_RXD_ERR_SE   0x02 /* Symbol Error */

Definition at line 170 of file igbvf_defines.h.

E1000_RXD_ERR_SEQ

#define E1000_RXD_ERR_SEQ   0x04 /* Sequence Error */

Definition at line 171 of file igbvf_defines.h.

E1000_RXD_ERR_CXE

#define E1000_RXD_ERR_CXE   0x10 /* Carrier Extension Error */

Definition at line 172 of file igbvf_defines.h.

E1000_RXD_ERR_TCPE

#define E1000_RXD_ERR_TCPE   0x20 /* TCP/UDP Checksum Error */

Definition at line 173 of file igbvf_defines.h.

E1000_RXD_ERR_IPE

#define E1000_RXD_ERR_IPE   0x40 /* IP Checksum Error */

Definition at line 174 of file igbvf_defines.h.

E1000_RXD_ERR_RXE

#define E1000_RXD_ERR_RXE   0x80 /* Rx Data Error */

Definition at line 175 of file igbvf_defines.h.

E1000_RXD_SPC_VLAN_MASK

#define E1000_RXD_SPC_VLAN_MASK   0x0FFF /* VLAN ID is in lower 12 bits */

Definition at line 176 of file igbvf_defines.h.

E1000_RXD_SPC_PRI_MASK

#define E1000_RXD_SPC_PRI_MASK   0xE000 /* Priority is in upper 3 bits */

Definition at line 177 of file igbvf_defines.h.

E1000_RXD_SPC_PRI_SHIFT

#define E1000_RXD_SPC_PRI_SHIFT   13

Definition at line 178 of file igbvf_defines.h.

E1000_RXD_SPC_CFI_MASK

#define E1000_RXD_SPC_CFI_MASK   0x1000 /* CFI is bit 12 */

Definition at line 179 of file igbvf_defines.h.

E1000_RXD_SPC_CFI_SHIFT

#define E1000_RXD_SPC_CFI_SHIFT   12

Definition at line 180 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_CE

#define E1000_RXDEXT_STATERR_CE   0x01000000

Definition at line 182 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_SE

#define E1000_RXDEXT_STATERR_SE   0x02000000

Definition at line 183 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_SEQ

#define E1000_RXDEXT_STATERR_SEQ   0x04000000

Definition at line 184 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_CXE

#define E1000_RXDEXT_STATERR_CXE   0x10000000

Definition at line 185 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_TCPE

#define E1000_RXDEXT_STATERR_TCPE   0x20000000

Definition at line 186 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_IPE

#define E1000_RXDEXT_STATERR_IPE   0x40000000

Definition at line 187 of file igbvf_defines.h.

E1000_RXDEXT_STATERR_RXE

#define E1000_RXDEXT_STATERR_RXE   0x80000000

Definition at line 188 of file igbvf_defines.h.

E1000_RXD_ERR_FRAME_ERR_MASK

#define E1000_RXD_ERR_FRAME_ERR_MASK

Value:

( \
    E1000_RXD_ERR_CE  |                \
    E1000_RXD_ERR_SE  |                \
    E1000_RXD_ERR_SEQ |                \
    E1000_RXD_ERR_CXE |                \
    E1000_RXD_ERR_RXE)

Definition at line 191 of file igbvf_defines.h.

E1000_RXDEXT_ERR_FRAME_ERR_MASK

#define E1000_RXDEXT_ERR_FRAME_ERR_MASK

Value:

( \
    E1000_RXDEXT_STATERR_CE  |            \
    E1000_RXDEXT_STATERR_SE  |            \
    E1000_RXDEXT_STATERR_SEQ |            \
    E1000_RXDEXT_STATERR_CXE |            \
    E1000_RXDEXT_STATERR_RXE)

Definition at line 199 of file igbvf_defines.h.

E1000_MRQC_ENABLE_MASK

#define E1000_MRQC_ENABLE_MASK   0x00000007

Definition at line 206 of file igbvf_defines.h.

E1000_MRQC_ENABLE_RSS_2Q

#define E1000_MRQC_ENABLE_RSS_2Q   0x00000001

Definition at line 207 of file igbvf_defines.h.

E1000_MRQC_ENABLE_RSS_INT

#define E1000_MRQC_ENABLE_RSS_INT   0x00000004

Definition at line 208 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_MASK

#define E1000_MRQC_RSS_FIELD_MASK   0xFFFF0000

Definition at line 209 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_IPV4_TCP

#define E1000_MRQC_RSS_FIELD_IPV4_TCP   0x00010000

Definition at line 210 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_IPV4

#define E1000_MRQC_RSS_FIELD_IPV4   0x00020000

Definition at line 211 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_IPV6_TCP_EX

#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX   0x00040000

Definition at line 212 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_IPV6_EX

#define E1000_MRQC_RSS_FIELD_IPV6_EX   0x00080000

Definition at line 213 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_IPV6

#define E1000_MRQC_RSS_FIELD_IPV6   0x00100000

Definition at line 214 of file igbvf_defines.h.

E1000_MRQC_RSS_FIELD_IPV6_TCP

#define E1000_MRQC_RSS_FIELD_IPV6_TCP   0x00200000

Definition at line 215 of file igbvf_defines.h.

E1000_RXDPS_HDRSTAT_HDRSP

#define E1000_RXDPS_HDRSTAT_HDRSP   0x00008000

Definition at line 217 of file igbvf_defines.h.

E1000_RXDPS_HDRSTAT_HDRLEN_MASK

#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK   0x000003FF

Definition at line 218 of file igbvf_defines.h.

E1000_MANC_SMBUS_EN

#define E1000_MANC_SMBUS_EN   0x00000001 /* SMBus Enabled - RO */

Definition at line 221 of file igbvf_defines.h.

E1000_MANC_ASF_EN

#define E1000_MANC_ASF_EN   0x00000002 /* ASF Enabled - RO */

Definition at line 222 of file igbvf_defines.h.

E1000_MANC_R_ON_FORCE

#define E1000_MANC_R_ON_FORCE   0x00000004 /* Reset on Force TCO - RO */

Definition at line 223 of file igbvf_defines.h.

E1000_MANC_RMCP_EN

#define E1000_MANC_RMCP_EN   0x00000100 /* Enable RCMP 026Fh Filtering */

Definition at line 224 of file igbvf_defines.h.

E1000_MANC_0298_EN

#define E1000_MANC_0298_EN   0x00000200 /* Enable RCMP 0298h Filtering */

Definition at line 225 of file igbvf_defines.h.

E1000_MANC_IPV4_EN

#define E1000_MANC_IPV4_EN   0x00000400 /* Enable IPv4 */

Definition at line 226 of file igbvf_defines.h.

E1000_MANC_IPV6_EN

#define E1000_MANC_IPV6_EN   0x00000800 /* Enable IPv6 */

Definition at line 227 of file igbvf_defines.h.

E1000_MANC_SNAP_EN

#define E1000_MANC_SNAP_EN   0x00001000 /* Accept LLC/SNAP */

Definition at line 228 of file igbvf_defines.h.

E1000_MANC_ARP_EN

#define E1000_MANC_ARP_EN   0x00002000 /* Enable ARP Request Filtering */

Definition at line 229 of file igbvf_defines.h.

E1000_MANC_NEIGHBOR_EN

#define E1000_MANC_NEIGHBOR_EN   0x00004000

Definition at line 231 of file igbvf_defines.h.

E1000_MANC_ARP_RES_EN

#define E1000_MANC_ARP_RES_EN   0x00008000 /* Enable ARP response Filtering */

Definition at line 232 of file igbvf_defines.h.

E1000_MANC_TCO_RESET

#define E1000_MANC_TCO_RESET   0x00010000 /* TCO Reset Occurred */

Definition at line 233 of file igbvf_defines.h.

E1000_MANC_RCV_TCO_EN

#define E1000_MANC_RCV_TCO_EN   0x00020000 /* Receive TCO Packets Enabled */

Definition at line 234 of file igbvf_defines.h.

E1000_MANC_REPORT_STATUS

#define E1000_MANC_REPORT_STATUS   0x00040000 /* Status Reporting Enabled */

Definition at line 235 of file igbvf_defines.h.

E1000_MANC_RCV_ALL

#define E1000_MANC_RCV_ALL   0x00080000 /* Receive All Enabled */

Definition at line 236 of file igbvf_defines.h.

E1000_MANC_BLK_PHY_RST_ON_IDE

#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */

Definition at line 237 of file igbvf_defines.h.

E1000_MANC_EN_MAC_ADDR_FILTER

#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000

Definition at line 239 of file igbvf_defines.h.

E1000_MANC_EN_MNG2HOST

#define E1000_MANC_EN_MNG2HOST   0x00200000

Definition at line 241 of file igbvf_defines.h.

E1000_MANC_EN_IP_ADDR_FILTER

#define E1000_MANC_EN_IP_ADDR_FILTER   0x00400000

Definition at line 243 of file igbvf_defines.h.

E1000_MANC_EN_XSUM_FILTER

#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */

Definition at line 244 of file igbvf_defines.h.

E1000_MANC_BR_EN

#define E1000_MANC_BR_EN   0x01000000 /* Enable broadcast filtering */

Definition at line 245 of file igbvf_defines.h.

E1000_MANC_SMB_REQ

#define E1000_MANC_SMB_REQ   0x01000000 /* SMBus Request */

Definition at line 246 of file igbvf_defines.h.

E1000_MANC_SMB_GNT

#define E1000_MANC_SMB_GNT   0x02000000 /* SMBus Grant */

Definition at line 247 of file igbvf_defines.h.

E1000_MANC_SMB_CLK_IN

#define E1000_MANC_SMB_CLK_IN   0x04000000 /* SMBus Clock In */

Definition at line 248 of file igbvf_defines.h.

E1000_MANC_SMB_DATA_IN

#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */

Definition at line 249 of file igbvf_defines.h.

E1000_MANC_SMB_DATA_OUT

#define E1000_MANC_SMB_DATA_OUT   0x10000000 /* SMBus Data Out */

Definition at line 250 of file igbvf_defines.h.

E1000_MANC_SMB_CLK_OUT

#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */

Definition at line 251 of file igbvf_defines.h.

E1000_MANC_SMB_DATA_OUT_SHIFT

#define E1000_MANC_SMB_DATA_OUT_SHIFT   28 /* SMBus Data Out Shift */

Definition at line 253 of file igbvf_defines.h.

E1000_MANC_SMB_CLK_OUT_SHIFT

#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */

Definition at line 254 of file igbvf_defines.h.

E1000_RCTL_RST

#define E1000_RCTL_RST   0x00000001 /* Software reset */

Definition at line 257 of file igbvf_defines.h.

E1000_RCTL_EN

#define E1000_RCTL_EN   0x00000002 /* enable */

Definition at line 258 of file igbvf_defines.h.

E1000_RCTL_SBP

#define E1000_RCTL_SBP   0x00000004 /* store bad packet */

Definition at line 259 of file igbvf_defines.h.

E1000_RCTL_UPE

#define E1000_RCTL_UPE   0x00000008 /* unicast promisc enable */

Definition at line 260 of file igbvf_defines.h.

E1000_RCTL_MPE

#define E1000_RCTL_MPE   0x00000010 /* multicast promisc enable */

Definition at line 261 of file igbvf_defines.h.

E1000_RCTL_LPE

#define E1000_RCTL_LPE   0x00000020 /* long packet enable */

Definition at line 262 of file igbvf_defines.h.

E1000_RCTL_LBM_NO

#define E1000_RCTL_LBM_NO   0x00000000 /* no loopback mode */

Definition at line 263 of file igbvf_defines.h.

E1000_RCTL_LBM_MAC

#define E1000_RCTL_LBM_MAC   0x00000040 /* MAC loopback mode */

Definition at line 264 of file igbvf_defines.h.

E1000_RCTL_LBM_SLP

#define E1000_RCTL_LBM_SLP   0x00000080 /* serial link loopback mode */

Definition at line 265 of file igbvf_defines.h.

E1000_RCTL_LBM_TCVR

#define E1000_RCTL_LBM_TCVR   0x000000C0 /* tcvr loopback mode */

Definition at line 266 of file igbvf_defines.h.

E1000_RCTL_DTYP_MASK

#define E1000_RCTL_DTYP_MASK   0x00000C00 /* Descriptor type mask */

Definition at line 267 of file igbvf_defines.h.

E1000_RCTL_DTYP_PS

#define E1000_RCTL_DTYP_PS   0x00000400 /* Packet Split descriptor */

Definition at line 268 of file igbvf_defines.h.

E1000_RCTL_RDMTS_HALF

#define E1000_RCTL_RDMTS_HALF   0x00000000 /* rx desc min thresh size */

Definition at line 269 of file igbvf_defines.h.

E1000_RCTL_RDMTS_QUAT

#define E1000_RCTL_RDMTS_QUAT   0x00000100 /* rx desc min thresh size */

Definition at line 270 of file igbvf_defines.h.

E1000_RCTL_RDMTS_EIGTH

#define E1000_RCTL_RDMTS_EIGTH   0x00000200 /* rx desc min thresh size */

Definition at line 271 of file igbvf_defines.h.

E1000_RCTL_MO_SHIFT

#define E1000_RCTL_MO_SHIFT   12 /* multicast offset shift */

Definition at line 272 of file igbvf_defines.h.

E1000_RCTL_MO_0

#define E1000_RCTL_MO_0   0x00000000 /* multicast offset 11:0 */

Definition at line 273 of file igbvf_defines.h.

E1000_RCTL_MO_1

#define E1000_RCTL_MO_1   0x00001000 /* multicast offset 12:1 */

Definition at line 274 of file igbvf_defines.h.

E1000_RCTL_MO_2

#define E1000_RCTL_MO_2   0x00002000 /* multicast offset 13:2 */

Definition at line 275 of file igbvf_defines.h.

E1000_RCTL_MO_3

#define E1000_RCTL_MO_3   0x00003000 /* multicast offset 15:4 */

Definition at line 276 of file igbvf_defines.h.

E1000_RCTL_MDR

#define E1000_RCTL_MDR   0x00004000 /* multicast desc ring 0 */

Definition at line 277 of file igbvf_defines.h.

E1000_RCTL_BAM

#define E1000_RCTL_BAM   0x00008000 /* broadcast enable */

Definition at line 278 of file igbvf_defines.h.

E1000_RCTL_SZ_2048

#define E1000_RCTL_SZ_2048   0x00000000 /* rx buffer size 2048 */

Definition at line 280 of file igbvf_defines.h.

E1000_RCTL_SZ_1024

#define E1000_RCTL_SZ_1024   0x00010000 /* rx buffer size 1024 */

Definition at line 281 of file igbvf_defines.h.

E1000_RCTL_SZ_512

#define E1000_RCTL_SZ_512   0x00020000 /* rx buffer size 512 */

Definition at line 282 of file igbvf_defines.h.

E1000_RCTL_SZ_256

#define E1000_RCTL_SZ_256   0x00030000 /* rx buffer size 256 */

Definition at line 283 of file igbvf_defines.h.

E1000_RCTL_SZ_16384

#define E1000_RCTL_SZ_16384   0x00010000 /* rx buffer size 16384 */

Definition at line 285 of file igbvf_defines.h.

E1000_RCTL_SZ_8192

#define E1000_RCTL_SZ_8192   0x00020000 /* rx buffer size 8192 */

Definition at line 286 of file igbvf_defines.h.

E1000_RCTL_SZ_4096

#define E1000_RCTL_SZ_4096   0x00030000 /* rx buffer size 4096 */

Definition at line 287 of file igbvf_defines.h.

E1000_RCTL_VFE

#define E1000_RCTL_VFE   0x00040000 /* vlan filter enable */

Definition at line 288 of file igbvf_defines.h.

E1000_RCTL_CFIEN

#define E1000_RCTL_CFIEN   0x00080000 /* canonical form enable */

Definition at line 289 of file igbvf_defines.h.

E1000_RCTL_CFI

#define E1000_RCTL_CFI   0x00100000 /* canonical form indicator */

Definition at line 290 of file igbvf_defines.h.

E1000_RCTL_DPF

#define E1000_RCTL_DPF   0x00400000 /* discard pause frames */

Definition at line 291 of file igbvf_defines.h.

E1000_RCTL_PMCF

#define E1000_RCTL_PMCF   0x00800000 /* pass MAC control frames */

Definition at line 292 of file igbvf_defines.h.

E1000_RCTL_BSEX

#define E1000_RCTL_BSEX   0x02000000 /* Buffer size extension */

Definition at line 293 of file igbvf_defines.h.

E1000_RCTL_SECRC

#define E1000_RCTL_SECRC   0x04000000 /* Strip Ethernet CRC */

Definition at line 294 of file igbvf_defines.h.

E1000_RCTL_FLXBUF_MASK

#define E1000_RCTL_FLXBUF_MASK   0x78000000 /* Flexible buffer size */

Definition at line 295 of file igbvf_defines.h.

E1000_RCTL_FLXBUF_SHIFT

#define E1000_RCTL_FLXBUF_SHIFT   27 /* Flexible buffer shift */

Definition at line 296 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE0_MASK

#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F

Definition at line 315 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE1_MASK

#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00

Definition at line 316 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE2_MASK

#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000

Definition at line 317 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE3_MASK

#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000

Definition at line 318 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE0_SHIFT

#define E1000_PSRCTL_BSIZE0_SHIFT   7 /* Shift _right_ 7 */

Definition at line 320 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE1_SHIFT

#define E1000_PSRCTL_BSIZE1_SHIFT   2 /* Shift _right_ 2 */

Definition at line 321 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE2_SHIFT

#define E1000_PSRCTL_BSIZE2_SHIFT   6 /* Shift _left_ 6 */

Definition at line 322 of file igbvf_defines.h.

E1000_PSRCTL_BSIZE3_SHIFT

#define E1000_PSRCTL_BSIZE3_SHIFT   14 /* Shift _left_ 14 */

Definition at line 323 of file igbvf_defines.h.

E1000_SWFW_EEP_SM

#define E1000_SWFW_EEP_SM   0x01

Definition at line 326 of file igbvf_defines.h.

E1000_SWFW_PHY0_SM

#define E1000_SWFW_PHY0_SM   0x02

Definition at line 327 of file igbvf_defines.h.

E1000_SWFW_PHY1_SM

#define E1000_SWFW_PHY1_SM   0x04

Definition at line 328 of file igbvf_defines.h.

E1000_SWFW_CSR_SM

#define E1000_SWFW_CSR_SM   0x08

Definition at line 329 of file igbvf_defines.h.

E1000_FACTPS_LFS

#define E1000_FACTPS_LFS   0x40000000 /* LAN Function Select */

Definition at line 332 of file igbvf_defines.h.

E1000_CTRL_FD

#define E1000_CTRL_FD   0x00000001 /* Full duplex.0=half; 1=full */

Definition at line 334 of file igbvf_defines.h.

E1000_CTRL_BEM

#define E1000_CTRL_BEM   0x00000002 /* Endian Mode.0=little,1=big */

Definition at line 335 of file igbvf_defines.h.

E1000_CTRL_PRIOR

#define E1000_CTRL_PRIOR   0x00000004 /* Priority on PCI. 0=rx,1=fair */

Definition at line 336 of file igbvf_defines.h.

E1000_CTRL_GIO_MASTER_DISABLE

#define E1000_CTRL_GIO_MASTER_DISABLE   0x00000004 /*Blocks new Master reqs */

Definition at line 337 of file igbvf_defines.h.

E1000_CTRL_LRST

#define E1000_CTRL_LRST   0x00000008 /* Link reset. 0=normal,1=reset */

Definition at line 338 of file igbvf_defines.h.

E1000_CTRL_TME

#define E1000_CTRL_TME   0x00000010 /* Test mode. 0=normal,1=test */

Definition at line 339 of file igbvf_defines.h.

E1000_CTRL_SLE

#define E1000_CTRL_SLE   0x00000020 /* Serial Link on 0=dis,1=en */

Definition at line 340 of file igbvf_defines.h.

E1000_CTRL_ASDE

#define E1000_CTRL_ASDE   0x00000020 /* Auto-speed detect enable */

Definition at line 341 of file igbvf_defines.h.

E1000_CTRL_SLU

#define E1000_CTRL_SLU   0x00000040 /* Set link up (Force Link) */

Definition at line 342 of file igbvf_defines.h.

E1000_CTRL_ILOS

#define E1000_CTRL_ILOS   0x00000080 /* Invert Loss-Of Signal */

Definition at line 343 of file igbvf_defines.h.

E1000_CTRL_SPD_SEL

#define E1000_CTRL_SPD_SEL   0x00000300 /* Speed Select Mask */

Definition at line 344 of file igbvf_defines.h.

E1000_CTRL_SPD_10

#define E1000_CTRL_SPD_10   0x00000000 /* Force 10Mb */

Definition at line 345 of file igbvf_defines.h.

E1000_CTRL_SPD_100

#define E1000_CTRL_SPD_100   0x00000100 /* Force 100Mb */

Definition at line 346 of file igbvf_defines.h.

E1000_CTRL_SPD_1000

#define E1000_CTRL_SPD_1000   0x00000200 /* Force 1Gb */

Definition at line 347 of file igbvf_defines.h.

E1000_CTRL_BEM32

#define E1000_CTRL_BEM32   0x00000400 /* Big Endian 32 mode */

Definition at line 348 of file igbvf_defines.h.

E1000_CTRL_FRCSPD

#define E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */

Definition at line 349 of file igbvf_defines.h.

E1000_CTRL_FRCDPX

#define E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */

Definition at line 350 of file igbvf_defines.h.

E1000_CTRL_D_UD_EN

#define E1000_CTRL_D_UD_EN   0x00002000 /* Dock/Undock enable */

Definition at line 351 of file igbvf_defines.h.

E1000_CTRL_D_UD_POLARITY

#define E1000_CTRL_D_UD_POLARITY

Value:

0x00004000 /* Defined polarity of Dock/Undock
                                             * indication in SDP[0] */

Definition at line 352 of file igbvf_defines.h.

E1000_CTRL_FORCE_PHY_RESET

#define E1000_CTRL_FORCE_PHY_RESET

Value:

0x00008000 /* Reset both PHY ports, through
                                               * PHYRST_N pin */

Definition at line 354 of file igbvf_defines.h.

E1000_CTRL_EXT_LINK_EN

#define E1000_CTRL_EXT_LINK_EN

Value:

0x00010000 /* enable link status from external
                                           * LINK_0 and LINK_1 pins */

Definition at line 356 of file igbvf_defines.h.

E1000_CTRL_SWDPIN0

#define E1000_CTRL_SWDPIN0   0x00040000 /* SWDPIN 0 value */

Definition at line 358 of file igbvf_defines.h.

E1000_CTRL_SWDPIN1

#define E1000_CTRL_SWDPIN1   0x00080000 /* SWDPIN 1 value */

Definition at line 359 of file igbvf_defines.h.

E1000_CTRL_SWDPIN2

#define E1000_CTRL_SWDPIN2   0x00100000 /* SWDPIN 2 value */

Definition at line 360 of file igbvf_defines.h.

E1000_CTRL_SWDPIN3

#define E1000_CTRL_SWDPIN3   0x00200000 /* SWDPIN 3 value */

Definition at line 361 of file igbvf_defines.h.

E1000_CTRL_SWDPIO0

#define E1000_CTRL_SWDPIO0   0x00400000 /* SWDPIN 0 Input or output */

Definition at line 362 of file igbvf_defines.h.

E1000_CTRL_SWDPIO1

#define E1000_CTRL_SWDPIO1   0x00800000 /* SWDPIN 1 input or output */

Definition at line 363 of file igbvf_defines.h.

E1000_CTRL_SWDPIO2

#define E1000_CTRL_SWDPIO2   0x01000000 /* SWDPIN 2 input or output */

Definition at line 364 of file igbvf_defines.h.

E1000_CTRL_SWDPIO3

#define E1000_CTRL_SWDPIO3   0x02000000 /* SWDPIN 3 input or output */

Definition at line 365 of file igbvf_defines.h.

E1000_CTRL_RST

#define E1000_CTRL_RST   0x04000000 /* Global reset */

Definition at line 366 of file igbvf_defines.h.

E1000_CTRL_RFCE

#define E1000_CTRL_RFCE   0x08000000 /* Receive Flow Control enable */

Definition at line 367 of file igbvf_defines.h.

E1000_CTRL_TFCE

#define E1000_CTRL_TFCE   0x10000000 /* Transmit flow control enable */

Definition at line 368 of file igbvf_defines.h.

E1000_CTRL_RTE

#define E1000_CTRL_RTE   0x20000000 /* Routing tag enable */

Definition at line 369 of file igbvf_defines.h.

E1000_CTRL_VME

#define E1000_CTRL_VME   0x40000000 /* IEEE VLAN mode enable */

Definition at line 370 of file igbvf_defines.h.

E1000_CTRL_PHY_RST

#define E1000_CTRL_PHY_RST   0x80000000 /* PHY Reset */

Definition at line 371 of file igbvf_defines.h.

E1000_CTRL_SW2FW_INT

#define E1000_CTRL_SW2FW_INT   0x02000000 /* Initiate an interrupt to ME */

Definition at line 372 of file igbvf_defines.h.

E1000_CTRL_I2C_ENA

#define E1000_CTRL_I2C_ENA   0x02000000 /* I2C enable */

Definition at line 373 of file igbvf_defines.h.

E1000_CTRL_PHY_RESET_DIR

#define E1000_CTRL_PHY_RESET_DIR   E1000_CTRL_SWDPIO0

Definition at line 379 of file igbvf_defines.h.

E1000_CTRL_PHY_RESET

#define E1000_CTRL_PHY_RESET   E1000_CTRL_SWDPIN0

Definition at line 380 of file igbvf_defines.h.

E1000_CTRL_MDIO_DIR

#define E1000_CTRL_MDIO_DIR   E1000_CTRL_SWDPIO2

Definition at line 381 of file igbvf_defines.h.

E1000_CTRL_MDIO

#define E1000_CTRL_MDIO   E1000_CTRL_SWDPIN2

Definition at line 382 of file igbvf_defines.h.

E1000_CTRL_MDC_DIR

#define E1000_CTRL_MDC_DIR   E1000_CTRL_SWDPIO3

Definition at line 383 of file igbvf_defines.h.

E1000_CTRL_MDC

#define E1000_CTRL_MDC   E1000_CTRL_SWDPIN3

Definition at line 384 of file igbvf_defines.h.

E1000_CTRL_PHY_RESET_DIR4

#define E1000_CTRL_PHY_RESET_DIR4   E1000_CTRL_EXT_SDP4_DIR

Definition at line 385 of file igbvf_defines.h.

E1000_CTRL_PHY_RESET4

#define E1000_CTRL_PHY_RESET4   E1000_CTRL_EXT_SDP4_DATA

Definition at line 386 of file igbvf_defines.h.

E1000_CONNSW_ENRGSRC

#define E1000_CONNSW_ENRGSRC   0x4

Definition at line 388 of file igbvf_defines.h.

E1000_PCS_CFG_PCS_EN

#define E1000_PCS_CFG_PCS_EN   8

Definition at line 389 of file igbvf_defines.h.

E1000_PCS_LCTL_FLV_LINK_UP

#define E1000_PCS_LCTL_FLV_LINK_UP   1

Definition at line 390 of file igbvf_defines.h.

E1000_PCS_LCTL_FSV_10

#define E1000_PCS_LCTL_FSV_10   0

Definition at line 391 of file igbvf_defines.h.

E1000_PCS_LCTL_FSV_100

#define E1000_PCS_LCTL_FSV_100   2

Definition at line 392 of file igbvf_defines.h.

E1000_PCS_LCTL_FSV_1000

#define E1000_PCS_LCTL_FSV_1000   4

Definition at line 393 of file igbvf_defines.h.

E1000_PCS_LCTL_FDV_FULL

#define E1000_PCS_LCTL_FDV_FULL   8

Definition at line 394 of file igbvf_defines.h.

E1000_PCS_LCTL_FSD

#define E1000_PCS_LCTL_FSD   0x10

Definition at line 395 of file igbvf_defines.h.

E1000_PCS_LCTL_FORCE_LINK

#define E1000_PCS_LCTL_FORCE_LINK   0x20

Definition at line 396 of file igbvf_defines.h.

E1000_PCS_LCTL_LOW_LINK_LATCH

#define E1000_PCS_LCTL_LOW_LINK_LATCH   0x40

Definition at line 397 of file igbvf_defines.h.

E1000_PCS_LCTL_FORCE_FCTRL

#define E1000_PCS_LCTL_FORCE_FCTRL   0x80

Definition at line 398 of file igbvf_defines.h.

E1000_PCS_LCTL_AN_ENABLE

#define E1000_PCS_LCTL_AN_ENABLE   0x10000

Definition at line 399 of file igbvf_defines.h.

E1000_PCS_LCTL_AN_RESTART

#define E1000_PCS_LCTL_AN_RESTART   0x20000

Definition at line 400 of file igbvf_defines.h.

E1000_PCS_LCTL_AN_TIMEOUT

#define E1000_PCS_LCTL_AN_TIMEOUT   0x40000

Definition at line 401 of file igbvf_defines.h.

E1000_PCS_LCTL_AN_SGMII_BYPASS

#define E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000

Definition at line 402 of file igbvf_defines.h.

E1000_PCS_LCTL_AN_SGMII_TRIGGER

#define E1000_PCS_LCTL_AN_SGMII_TRIGGER   0x100000

Definition at line 403 of file igbvf_defines.h.

E1000_PCS_LCTL_FAST_LINK_TIMER

#define E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000

Definition at line 404 of file igbvf_defines.h.

E1000_PCS_LCTL_LINK_OK_FIX

#define E1000_PCS_LCTL_LINK_OK_FIX   0x2000000

Definition at line 405 of file igbvf_defines.h.

E1000_PCS_LCTL_CRS_ON_NI

#define E1000_PCS_LCTL_CRS_ON_NI   0x4000000

Definition at line 406 of file igbvf_defines.h.

E1000_ENABLE_SERDES_LOOPBACK

#define E1000_ENABLE_SERDES_LOOPBACK   0x0410

Definition at line 407 of file igbvf_defines.h.

E1000_PCS_LSTS_LINK_OK

#define E1000_PCS_LSTS_LINK_OK   1

Definition at line 409 of file igbvf_defines.h.

E1000_PCS_LSTS_SPEED_10

#define E1000_PCS_LSTS_SPEED_10   0

Definition at line 410 of file igbvf_defines.h.

E1000_PCS_LSTS_SPEED_100

#define E1000_PCS_LSTS_SPEED_100   2

Definition at line 411 of file igbvf_defines.h.

E1000_PCS_LSTS_SPEED_1000

#define E1000_PCS_LSTS_SPEED_1000   4

Definition at line 412 of file igbvf_defines.h.

E1000_PCS_LSTS_DUPLEX_FULL

#define E1000_PCS_LSTS_DUPLEX_FULL   8

Definition at line 413 of file igbvf_defines.h.

E1000_PCS_LSTS_SYNK_OK

#define E1000_PCS_LSTS_SYNK_OK   0x10

Definition at line 414 of file igbvf_defines.h.

E1000_PCS_LSTS_AN_COMPLETE

#define E1000_PCS_LSTS_AN_COMPLETE   0x10000

Definition at line 415 of file igbvf_defines.h.

E1000_PCS_LSTS_AN_PAGE_RX

#define E1000_PCS_LSTS_AN_PAGE_RX   0x20000

Definition at line 416 of file igbvf_defines.h.

E1000_PCS_LSTS_AN_TIMED_OUT

#define E1000_PCS_LSTS_AN_TIMED_OUT   0x40000

Definition at line 417 of file igbvf_defines.h.

E1000_PCS_LSTS_AN_REMOTE_FAULT

#define E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000

Definition at line 418 of file igbvf_defines.h.

E1000_PCS_LSTS_AN_ERROR_RWS

#define E1000_PCS_LSTS_AN_ERROR_RWS   0x100000

Definition at line 419 of file igbvf_defines.h.

E1000_STATUS_FD

#define E1000_STATUS_FD   0x00000001 /* Full duplex.0=half,1=full */

Definition at line 422 of file igbvf_defines.h.

E1000_STATUS_LU

#define E1000_STATUS_LU   0x00000002 /* Link up.0=no,1=link */

Definition at line 423 of file igbvf_defines.h.

E1000_STATUS_FUNC_MASK

#define E1000_STATUS_FUNC_MASK   0x0000000C /* PCI Function Mask */

Definition at line 424 of file igbvf_defines.h.

E1000_STATUS_FUNC_SHIFT

#define E1000_STATUS_FUNC_SHIFT   2

Definition at line 425 of file igbvf_defines.h.

E1000_STATUS_FUNC_0

#define E1000_STATUS_FUNC_0   0x00000000 /* Function 0 */

Definition at line 426 of file igbvf_defines.h.

E1000_STATUS_FUNC_1

#define E1000_STATUS_FUNC_1   0x00000004 /* Function 1 */

Definition at line 427 of file igbvf_defines.h.

E1000_STATUS_TXOFF

#define E1000_STATUS_TXOFF   0x00000010 /* transmission paused */

Definition at line 428 of file igbvf_defines.h.

E1000_STATUS_TBIMODE

#define E1000_STATUS_TBIMODE   0x00000020 /* TBI mode */

Definition at line 429 of file igbvf_defines.h.

E1000_STATUS_SPEED_MASK

#define E1000_STATUS_SPEED_MASK   0x000000C0

Definition at line 430 of file igbvf_defines.h.

E1000_STATUS_SPEED_10

#define E1000_STATUS_SPEED_10   0x00000000 /* Speed 10Mb/s */

Definition at line 431 of file igbvf_defines.h.

E1000_STATUS_SPEED_100

#define E1000_STATUS_SPEED_100   0x00000040 /* Speed 100Mb/s */

Definition at line 432 of file igbvf_defines.h.

E1000_STATUS_SPEED_1000

#define E1000_STATUS_SPEED_1000   0x00000080 /* Speed 1000Mb/s */

Definition at line 433 of file igbvf_defines.h.

E1000_STATUS_LAN_INIT_DONE

#define E1000_STATUS_LAN_INIT_DONE   0x00000200 /* Lan Init Completion by NVM */

Definition at line 434 of file igbvf_defines.h.

E1000_STATUS_ASDV

#define E1000_STATUS_ASDV   0x00000300 /* Auto speed detect value */

Definition at line 435 of file igbvf_defines.h.

E1000_STATUS_PHYRA

#define E1000_STATUS_PHYRA   0x00000400 /* PHY Reset Asserted */

Definition at line 436 of file igbvf_defines.h.

E1000_STATUS_DOCK_CI

#define E1000_STATUS_DOCK_CI

Value:

0x00000800      /* Change in Dock/Undock state.
                                                 * Clear on write '0'. */

Definition at line 437 of file igbvf_defines.h.

E1000_STATUS_GIO_MASTER_ENABLE

#define E1000_STATUS_GIO_MASTER_ENABLE   0x00080000 /* Master request status */

Definition at line 439 of file igbvf_defines.h.

E1000_STATUS_MTXCKOK

#define E1000_STATUS_MTXCKOK   0x00000400 /* MTX clock running OK */

Definition at line 440 of file igbvf_defines.h.

E1000_STATUS_PCI66

#define E1000_STATUS_PCI66   0x00000800 /* In 66Mhz slot */

Definition at line 441 of file igbvf_defines.h.

E1000_STATUS_BUS64

#define E1000_STATUS_BUS64   0x00001000 /* In 64 bit slot */

Definition at line 442 of file igbvf_defines.h.

E1000_STATUS_PCIX_MODE

#define E1000_STATUS_PCIX_MODE   0x00002000 /* PCI-X mode */

Definition at line 443 of file igbvf_defines.h.

E1000_STATUS_PCIX_SPEED

#define E1000_STATUS_PCIX_SPEED   0x0000C000 /* PCI-X bus speed */

Definition at line 444 of file igbvf_defines.h.

E1000_STATUS_BMC_SKU_0

#define E1000_STATUS_BMC_SKU_0   0x00100000 /* BMC USB redirect disabled */

Definition at line 445 of file igbvf_defines.h.

E1000_STATUS_BMC_SKU_1

#define E1000_STATUS_BMC_SKU_1   0x00200000 /* BMC SRAM disabled */

Definition at line 446 of file igbvf_defines.h.

E1000_STATUS_BMC_SKU_2

#define E1000_STATUS_BMC_SKU_2   0x00400000 /* BMC SDRAM disabled */

Definition at line 447 of file igbvf_defines.h.

E1000_STATUS_BMC_CRYPTO

#define E1000_STATUS_BMC_CRYPTO   0x00800000 /* BMC crypto disabled */

Definition at line 448 of file igbvf_defines.h.

E1000_STATUS_BMC_LITE

#define E1000_STATUS_BMC_LITE

Value:

0x01000000 /* BMC external code execution
                                            * disabled */

Definition at line 449 of file igbvf_defines.h.

E1000_STATUS_RGMII_ENABLE

#define E1000_STATUS_RGMII_ENABLE   0x02000000 /* RGMII disabled */

Definition at line 451 of file igbvf_defines.h.

E1000_STATUS_FUSE_8

#define E1000_STATUS_FUSE_8   0x04000000

Definition at line 452 of file igbvf_defines.h.

E1000_STATUS_FUSE_9

#define E1000_STATUS_FUSE_9   0x08000000

Definition at line 453 of file igbvf_defines.h.

E1000_STATUS_SERDES0_DIS

#define E1000_STATUS_SERDES0_DIS   0x10000000 /* SERDES disabled on port 0 */

Definition at line 454 of file igbvf_defines.h.

E1000_STATUS_SERDES1_DIS

#define E1000_STATUS_SERDES1_DIS   0x20000000 /* SERDES disabled on port 1 */

Definition at line 455 of file igbvf_defines.h.

E1000_STATUS_PCIX_SPEED_66

#define E1000_STATUS_PCIX_SPEED_66   0x00000000 /* PCI-X bus speed 50-66 MHz */

Definition at line 458 of file igbvf_defines.h.

E1000_STATUS_PCIX_SPEED_100

#define E1000_STATUS_PCIX_SPEED_100   0x00004000 /* PCI-X bus speed 66-100 MHz */

Definition at line 459 of file igbvf_defines.h.

E1000_STATUS_PCIX_SPEED_133

#define E1000_STATUS_PCIX_SPEED_133   0x00008000 /*PCI-X bus speed 100-133 MHz*/

Definition at line 460 of file igbvf_defines.h.

SPEED_10

#define SPEED_10   10

Definition at line 462 of file igbvf_defines.h.

SPEED_100

#define SPEED_100   100

Definition at line 463 of file igbvf_defines.h.

SPEED_1000

#define SPEED_1000   1000

Definition at line 464 of file igbvf_defines.h.

HALF_DUPLEX

#define HALF_DUPLEX   1

Definition at line 465 of file igbvf_defines.h.

FULL_DUPLEX

#define FULL_DUPLEX   2

Definition at line 466 of file igbvf_defines.h.

PHY_FORCE_TIME

#define PHY_FORCE_TIME   20

Definition at line 468 of file igbvf_defines.h.

ADVERTISE_10_HALF

#define ADVERTISE_10_HALF   0x0001

Definition at line 470 of file igbvf_defines.h.

ADVERTISE_10_FULL

#define ADVERTISE_10_FULL   0x0002

Definition at line 471 of file igbvf_defines.h.

ADVERTISE_100_HALF

#define ADVERTISE_100_HALF   0x0004

Definition at line 472 of file igbvf_defines.h.

ADVERTISE_100_FULL

#define ADVERTISE_100_FULL   0x0008

Definition at line 473 of file igbvf_defines.h.

ADVERTISE_1000_HALF

#define ADVERTISE_1000_HALF   0x0010 /* Not used, just FYI */

Definition at line 474 of file igbvf_defines.h.

ADVERTISE_1000_FULL

#define ADVERTISE_1000_FULL   0x0020

Definition at line 475 of file igbvf_defines.h.

E1000_ALL_SPEED_DUPLEX

#define E1000_ALL_SPEED_DUPLEX

Value:

(ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
                                                     ADVERTISE_1000_FULL)

Definition at line 478 of file igbvf_defines.h.

E1000_ALL_NOT_GIG

#define E1000_ALL_NOT_GIG

Value:

(ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL)

Definition at line 481 of file igbvf_defines.h.

E1000_ALL_100_SPEED

#define E1000_ALL_100_SPEED   (ADVERTISE_100_HALF | ADVERTISE_100_FULL)

Definition at line 483 of file igbvf_defines.h.

E1000_ALL_10_SPEED

#define E1000_ALL_10_SPEED   (ADVERTISE_10_HALF | ADVERTISE_10_FULL)

Definition at line 484 of file igbvf_defines.h.

E1000_ALL_FULL_DUPLEX

#define E1000_ALL_FULL_DUPLEX

Value:

(ADVERTISE_10_FULL |  ADVERTISE_100_FULL | \
                                                     ADVERTISE_1000_FULL)

Definition at line 485 of file igbvf_defines.h.

E1000_ALL_HALF_DUPLEX

#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF | ADVERTISE_100_HALF)

Definition at line 487 of file igbvf_defines.h.

AUTONEG_ADVERTISE_SPEED_DEFAULT

#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX

Definition at line 489 of file igbvf_defines.h.

E1000_LEDCTL_LED0_MODE_MASK

#define E1000_LEDCTL_LED0_MODE_MASK   0x0000000F

Definition at line 492 of file igbvf_defines.h.

E1000_LEDCTL_LED0_MODE_SHIFT

#define E1000_LEDCTL_LED0_MODE_SHIFT   0

Definition at line 493 of file igbvf_defines.h.

E1000_LEDCTL_LED0_BLINK_RATE

#define E1000_LEDCTL_LED0_BLINK_RATE   0x00000020

Definition at line 494 of file igbvf_defines.h.

E1000_LEDCTL_LED0_IVRT

#define E1000_LEDCTL_LED0_IVRT   0x00000040

Definition at line 495 of file igbvf_defines.h.

E1000_LEDCTL_LED0_BLINK

#define E1000_LEDCTL_LED0_BLINK   0x00000080

Definition at line 496 of file igbvf_defines.h.

E1000_LEDCTL_LED1_MODE_MASK

#define E1000_LEDCTL_LED1_MODE_MASK   0x00000F00

Definition at line 497 of file igbvf_defines.h.

E1000_LEDCTL_LED1_MODE_SHIFT

#define E1000_LEDCTL_LED1_MODE_SHIFT   8

Definition at line 498 of file igbvf_defines.h.

E1000_LEDCTL_LED1_BLINK_RATE

#define E1000_LEDCTL_LED1_BLINK_RATE   0x00002000

Definition at line 499 of file igbvf_defines.h.

E1000_LEDCTL_LED1_IVRT

#define E1000_LEDCTL_LED1_IVRT   0x00004000

Definition at line 500 of file igbvf_defines.h.

E1000_LEDCTL_LED1_BLINK

#define E1000_LEDCTL_LED1_BLINK   0x00008000

Definition at line 501 of file igbvf_defines.h.

E1000_LEDCTL_LED2_MODE_MASK

#define E1000_LEDCTL_LED2_MODE_MASK   0x000F0000

Definition at line 502 of file igbvf_defines.h.

E1000_LEDCTL_LED2_MODE_SHIFT

#define E1000_LEDCTL_LED2_MODE_SHIFT   16

Definition at line 503 of file igbvf_defines.h.

E1000_LEDCTL_LED2_BLINK_RATE

#define E1000_LEDCTL_LED2_BLINK_RATE   0x00200000

Definition at line 504 of file igbvf_defines.h.

E1000_LEDCTL_LED2_IVRT

#define E1000_LEDCTL_LED2_IVRT   0x00400000

Definition at line 505 of file igbvf_defines.h.

E1000_LEDCTL_LED2_BLINK

#define E1000_LEDCTL_LED2_BLINK   0x00800000

Definition at line 506 of file igbvf_defines.h.

E1000_LEDCTL_LED3_MODE_MASK

#define E1000_LEDCTL_LED3_MODE_MASK   0x0F000000

Definition at line 507 of file igbvf_defines.h.

E1000_LEDCTL_LED3_MODE_SHIFT

#define E1000_LEDCTL_LED3_MODE_SHIFT   24

Definition at line 508 of file igbvf_defines.h.

E1000_LEDCTL_LED3_BLINK_RATE

#define E1000_LEDCTL_LED3_BLINK_RATE   0x20000000

Definition at line 509 of file igbvf_defines.h.

E1000_LEDCTL_LED3_IVRT

#define E1000_LEDCTL_LED3_IVRT   0x40000000

Definition at line 510 of file igbvf_defines.h.

E1000_LEDCTL_LED3_BLINK

#define E1000_LEDCTL_LED3_BLINK   0x80000000

Definition at line 511 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_10_1000

#define E1000_LEDCTL_MODE_LINK_10_1000   0x0

Definition at line 513 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_100_1000

#define E1000_LEDCTL_MODE_LINK_100_1000   0x1

Definition at line 514 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_UP

#define E1000_LEDCTL_MODE_LINK_UP   0x2

Definition at line 515 of file igbvf_defines.h.

E1000_LEDCTL_MODE_ACTIVITY

#define E1000_LEDCTL_MODE_ACTIVITY   0x3

Definition at line 516 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_ACTIVITY

#define E1000_LEDCTL_MODE_LINK_ACTIVITY   0x4

Definition at line 517 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_10

#define E1000_LEDCTL_MODE_LINK_10   0x5

Definition at line 518 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_100

#define E1000_LEDCTL_MODE_LINK_100   0x6

Definition at line 519 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LINK_1000

#define E1000_LEDCTL_MODE_LINK_1000   0x7

Definition at line 520 of file igbvf_defines.h.

E1000_LEDCTL_MODE_PCIX_MODE

#define E1000_LEDCTL_MODE_PCIX_MODE   0x8

Definition at line 521 of file igbvf_defines.h.

E1000_LEDCTL_MODE_FULL_DUPLEX

#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9

Definition at line 522 of file igbvf_defines.h.

E1000_LEDCTL_MODE_COLLISION

#define E1000_LEDCTL_MODE_COLLISION   0xA

Definition at line 523 of file igbvf_defines.h.

E1000_LEDCTL_MODE_BUS_SPEED

#define E1000_LEDCTL_MODE_BUS_SPEED   0xB

Definition at line 524 of file igbvf_defines.h.

E1000_LEDCTL_MODE_BUS_SIZE

#define E1000_LEDCTL_MODE_BUS_SIZE   0xC

Definition at line 525 of file igbvf_defines.h.

E1000_LEDCTL_MODE_PAUSED

#define E1000_LEDCTL_MODE_PAUSED   0xD

Definition at line 526 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LED_ON

#define E1000_LEDCTL_MODE_LED_ON   0xE

Definition at line 527 of file igbvf_defines.h.

E1000_LEDCTL_MODE_LED_OFF

#define E1000_LEDCTL_MODE_LED_OFF   0xF

Definition at line 528 of file igbvf_defines.h.

E1000_TXD_DTYP_D

#define E1000_TXD_DTYP_D   0x00100000 /* Data Descriptor */

Definition at line 531 of file igbvf_defines.h.

E1000_TXD_DTYP_C

#define E1000_TXD_DTYP_C   0x00000000 /* Context Descriptor */

Definition at line 532 of file igbvf_defines.h.

E1000_TXD_POPTS_SHIFT

#define E1000_TXD_POPTS_SHIFT   8 /* POPTS shift */

Definition at line 533 of file igbvf_defines.h.

E1000_TXD_POPTS_IXSM

#define E1000_TXD_POPTS_IXSM   0x01 /* Insert IP checksum */

Definition at line 534 of file igbvf_defines.h.

E1000_TXD_POPTS_TXSM

#define E1000_TXD_POPTS_TXSM   0x02 /* Insert TCP/UDP checksum */

Definition at line 535 of file igbvf_defines.h.

E1000_TXD_CMD_EOP

#define E1000_TXD_CMD_EOP   0x01000000 /* End of Packet */

Definition at line 536 of file igbvf_defines.h.

E1000_TXD_CMD_IFCS

#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */

Definition at line 537 of file igbvf_defines.h.

E1000_TXD_CMD_IC

#define E1000_TXD_CMD_IC   0x04000000 /* Insert Checksum */

Definition at line 538 of file igbvf_defines.h.

E1000_TXD_CMD_RS

#define E1000_TXD_CMD_RS   0x08000000 /* Report Status */

Definition at line 539 of file igbvf_defines.h.

E1000_TXD_CMD_RPS

#define E1000_TXD_CMD_RPS   0x10000000 /* Report Packet Sent */

Definition at line 540 of file igbvf_defines.h.

E1000_TXD_CMD_DEXT

#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */

Definition at line 541 of file igbvf_defines.h.

E1000_TXD_CMD_VLE

#define E1000_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */

Definition at line 542 of file igbvf_defines.h.

E1000_TXD_CMD_IDE

#define E1000_TXD_CMD_IDE   0x80000000 /* Enable Tidv register */

Definition at line 543 of file igbvf_defines.h.

E1000_TXD_STAT_DD

#define E1000_TXD_STAT_DD   0x00000001 /* Descriptor Done */

Definition at line 544 of file igbvf_defines.h.

E1000_TXD_STAT_EC

#define E1000_TXD_STAT_EC   0x00000002 /* Excess Collisions */

Definition at line 545 of file igbvf_defines.h.

E1000_TXD_STAT_LC

#define E1000_TXD_STAT_LC   0x00000004 /* Late Collisions */

Definition at line 546 of file igbvf_defines.h.

E1000_TXD_STAT_TU

#define E1000_TXD_STAT_TU   0x00000008 /* Transmit underrun */

Definition at line 547 of file igbvf_defines.h.

E1000_TXD_CMD_TCP

#define E1000_TXD_CMD_TCP   0x01000000 /* TCP packet */

Definition at line 548 of file igbvf_defines.h.

E1000_TXD_CMD_IP

#define E1000_TXD_CMD_IP   0x02000000 /* IP packet */

Definition at line 549 of file igbvf_defines.h.

E1000_TXD_CMD_TSE

#define E1000_TXD_CMD_TSE   0x04000000 /* TCP Seg enable */

Definition at line 550 of file igbvf_defines.h.

E1000_TXD_STAT_TC

#define E1000_TXD_STAT_TC   0x00000004 /* Tx Underrun */

Definition at line 551 of file igbvf_defines.h.

E1000_TCTL_RST

#define E1000_TCTL_RST   0x00000001 /* software reset */

Definition at line 555 of file igbvf_defines.h.

E1000_TCTL_EN

#define E1000_TCTL_EN   0x00000002 /* enable tx */

Definition at line 556 of file igbvf_defines.h.

E1000_TCTL_BCE

#define E1000_TCTL_BCE   0x00000004 /* busy check enable */

Definition at line 557 of file igbvf_defines.h.

E1000_TCTL_PSP

#define E1000_TCTL_PSP   0x00000008 /* pad short packets */

Definition at line 558 of file igbvf_defines.h.

E1000_TCTL_CT

#define E1000_TCTL_CT   0x00000ff0 /* collision threshold */

Definition at line 559 of file igbvf_defines.h.

E1000_TCTL_COLD

#define E1000_TCTL_COLD   0x003ff000 /* collision distance */

Definition at line 560 of file igbvf_defines.h.

E1000_TCTL_SWXOFF

#define E1000_TCTL_SWXOFF   0x00400000 /* SW Xoff transmission */

Definition at line 561 of file igbvf_defines.h.

E1000_TCTL_PBE

#define E1000_TCTL_PBE   0x00800000 /* Packet Burst Enable */

Definition at line 562 of file igbvf_defines.h.

E1000_TCTL_RTLC

#define E1000_TCTL_RTLC   0x01000000 /* Re-transmit on late collision */

Definition at line 563 of file igbvf_defines.h.

E1000_TCTL_NRTU

#define E1000_TCTL_NRTU   0x02000000 /* No Re-transmit on underrun */

Definition at line 564 of file igbvf_defines.h.

E1000_TCTL_MULR

#define E1000_TCTL_MULR   0x10000000 /* Multiple request support */

Definition at line 565 of file igbvf_defines.h.

E1000_TARC0_ENABLE

#define E1000_TARC0_ENABLE   0x00000400 /* Enable Tx Queue 0 */

Definition at line 568 of file igbvf_defines.h.

E1000_SCTL_DISABLE_SERDES_LOOPBACK

#define E1000_SCTL_DISABLE_SERDES_LOOPBACK   0x0400

Definition at line 571 of file igbvf_defines.h.

E1000_RXCSUM_PCSS_MASK

#define E1000_RXCSUM_PCSS_MASK   0x000000FF /* Packet Checksum Start */

Definition at line 574 of file igbvf_defines.h.

E1000_RXCSUM_IPOFL

#define E1000_RXCSUM_IPOFL   0x00000100 /* IPv4 checksum offload */

Definition at line 575 of file igbvf_defines.h.

E1000_RXCSUM_TUOFL

#define E1000_RXCSUM_TUOFL   0x00000200 /* TCP / UDP checksum offload */

Definition at line 576 of file igbvf_defines.h.

E1000_RXCSUM_IPV6OFL

#define E1000_RXCSUM_IPV6OFL   0x00000400 /* IPv6 checksum offload */

Definition at line 577 of file igbvf_defines.h.

E1000_RXCSUM_CRCOFL

#define E1000_RXCSUM_CRCOFL   0x00000800 /* CRC32 offload enable */

Definition at line 578 of file igbvf_defines.h.

E1000_RXCSUM_IPPCSE

#define E1000_RXCSUM_IPPCSE   0x00001000 /* IP payload checksum enable */

Definition at line 579 of file igbvf_defines.h.

E1000_RXCSUM_PCSD

#define E1000_RXCSUM_PCSD   0x00002000 /* packet checksum disabled */

Definition at line 580 of file igbvf_defines.h.

E1000_RFCTL_ISCSI_DIS

#define E1000_RFCTL_ISCSI_DIS   0x00000001

Definition at line 583 of file igbvf_defines.h.

E1000_RFCTL_ISCSI_DWC_MASK

#define E1000_RFCTL_ISCSI_DWC_MASK   0x0000003E

Definition at line 584 of file igbvf_defines.h.

E1000_RFCTL_ISCSI_DWC_SHIFT

#define E1000_RFCTL_ISCSI_DWC_SHIFT   1

Definition at line 585 of file igbvf_defines.h.

E1000_RFCTL_NFSW_DIS

#define E1000_RFCTL_NFSW_DIS   0x00000040

Definition at line 586 of file igbvf_defines.h.

E1000_RFCTL_NFSR_DIS

#define E1000_RFCTL_NFSR_DIS   0x00000080

Definition at line 587 of file igbvf_defines.h.

E1000_RFCTL_NFS_VER_MASK

#define E1000_RFCTL_NFS_VER_MASK   0x00000300

Definition at line 588 of file igbvf_defines.h.

E1000_RFCTL_NFS_VER_SHIFT

#define E1000_RFCTL_NFS_VER_SHIFT   8

Definition at line 589 of file igbvf_defines.h.

E1000_RFCTL_IPV6_DIS

#define E1000_RFCTL_IPV6_DIS   0x00000400

Definition at line 590 of file igbvf_defines.h.

E1000_RFCTL_IPV6_XSUM_DIS

#define E1000_RFCTL_IPV6_XSUM_DIS   0x00000800

Definition at line 591 of file igbvf_defines.h.

E1000_RFCTL_ACK_DIS

#define E1000_RFCTL_ACK_DIS   0x00001000

Definition at line 592 of file igbvf_defines.h.

E1000_RFCTL_ACKD_DIS

#define E1000_RFCTL_ACKD_DIS   0x00002000

Definition at line 593 of file igbvf_defines.h.

E1000_RFCTL_IPFRSP_DIS

#define E1000_RFCTL_IPFRSP_DIS   0x00004000

Definition at line 594 of file igbvf_defines.h.

E1000_RFCTL_EXTEN

#define E1000_RFCTL_EXTEN   0x00008000

Definition at line 595 of file igbvf_defines.h.

E1000_RFCTL_IPV6_EX_DIS

#define E1000_RFCTL_IPV6_EX_DIS   0x00010000

Definition at line 596 of file igbvf_defines.h.

E1000_RFCTL_NEW_IPV6_EXT_DIS

#define E1000_RFCTL_NEW_IPV6_EXT_DIS   0x00020000

Definition at line 597 of file igbvf_defines.h.

E1000_RFCTL_LEF

#define E1000_RFCTL_LEF   0x00040000

Definition at line 598 of file igbvf_defines.h.

E1000_COLLISION_THRESHOLD

#define E1000_COLLISION_THRESHOLD   15

Definition at line 601 of file igbvf_defines.h.

E1000_CT_SHIFT

#define E1000_CT_SHIFT   4

Definition at line 602 of file igbvf_defines.h.

E1000_COLLISION_DISTANCE

#define E1000_COLLISION_DISTANCE   63

Definition at line 603 of file igbvf_defines.h.

E1000_COLD_SHIFT

#define E1000_COLD_SHIFT   12

Definition at line 604 of file igbvf_defines.h.

DEFAULT_82543_TIPG_IPGT_FIBER

#define DEFAULT_82543_TIPG_IPGT_FIBER   9

Definition at line 607 of file igbvf_defines.h.

DEFAULT_82543_TIPG_IPGT_COPPER

#define DEFAULT_82543_TIPG_IPGT_COPPER   8

Definition at line 608 of file igbvf_defines.h.

E1000_TIPG_IPGT_MASK

#define E1000_TIPG_IPGT_MASK   0x000003FF

Definition at line 610 of file igbvf_defines.h.

E1000_TIPG_IPGR1_MASK

#define E1000_TIPG_IPGR1_MASK   0x000FFC00

Definition at line 611 of file igbvf_defines.h.

E1000_TIPG_IPGR2_MASK

#define E1000_TIPG_IPGR2_MASK   0x3FF00000

Definition at line 612 of file igbvf_defines.h.

DEFAULT_82543_TIPG_IPGR1

#define DEFAULT_82543_TIPG_IPGR1   8

Definition at line 614 of file igbvf_defines.h.

E1000_TIPG_IPGR1_SHIFT

#define E1000_TIPG_IPGR1_SHIFT   10

Definition at line 615 of file igbvf_defines.h.

DEFAULT_82543_TIPG_IPGR2

#define DEFAULT_82543_TIPG_IPGR2   6

Definition at line 617 of file igbvf_defines.h.

DEFAULT_80003ES2LAN_TIPG_IPGR2

#define DEFAULT_80003ES2LAN_TIPG_IPGR2   7

Definition at line 618 of file igbvf_defines.h.

E1000_TIPG_IPGR2_SHIFT

#define E1000_TIPG_IPGR2_SHIFT   20

Definition at line 619 of file igbvf_defines.h.

ETHERNET_IEEE_VLAN_TYPE

#define ETHERNET_IEEE_VLAN_TYPE   0x8100 /* 802.3ac packet */

Definition at line 622 of file igbvf_defines.h.

ETHERNET_FCS_SIZE

#define ETHERNET_FCS_SIZE   4

Definition at line 624 of file igbvf_defines.h.

MAX_JUMBO_FRAME_SIZE

#define MAX_JUMBO_FRAME_SIZE   0x3F00

Definition at line 625 of file igbvf_defines.h.

E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP

#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP   0x00000020

Definition at line 628 of file igbvf_defines.h.

E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE

#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE   0x00000001

Definition at line 629 of file igbvf_defines.h.

E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE

#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE   0x00000008

Definition at line 630 of file igbvf_defines.h.

E1000_EXTCNF_CTRL_SWFLAG

#define E1000_EXTCNF_CTRL_SWFLAG   0x00000020

Definition at line 631 of file igbvf_defines.h.

E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000

Definition at line 632 of file igbvf_defines.h.

E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT

#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT   16

Definition at line 633 of file igbvf_defines.h.

E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK

#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000

Definition at line 634 of file igbvf_defines.h.

E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT

#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT   16

Definition at line 635 of file igbvf_defines.h.

E1000_PHY_CTRL_SPD_EN

#define E1000_PHY_CTRL_SPD_EN   0x00000001

Definition at line 637 of file igbvf_defines.h.

E1000_PHY_CTRL_D0A_LPLU

#define E1000_PHY_CTRL_D0A_LPLU   0x00000002

Definition at line 638 of file igbvf_defines.h.

E1000_PHY_CTRL_NOND0A_LPLU

#define E1000_PHY_CTRL_NOND0A_LPLU   0x00000004

Definition at line 639 of file igbvf_defines.h.

E1000_PHY_CTRL_NOND0A_GBE_DISABLE

#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE   0x00000008

Definition at line 640 of file igbvf_defines.h.

E1000_PHY_CTRL_GBE_DISABLE

#define E1000_PHY_CTRL_GBE_DISABLE   0x00000040

Definition at line 641 of file igbvf_defines.h.

E1000_KABGTXD_BGSQLBIAS

#define E1000_KABGTXD_BGSQLBIAS   0x00050000

Definition at line 643 of file igbvf_defines.h.

E1000_PBA_6K

#define E1000_PBA_6K   0x0006 /* 6KB */

Definition at line 646 of file igbvf_defines.h.

E1000_PBA_8K

#define E1000_PBA_8K   0x0008 /* 8KB */

Definition at line 647 of file igbvf_defines.h.

E1000_PBA_10K

#define E1000_PBA_10K   0x000A /* 10KB */

Definition at line 648 of file igbvf_defines.h.

E1000_PBA_12K

#define E1000_PBA_12K   0x000C /* 12KB */

Definition at line 649 of file igbvf_defines.h.

E1000_PBA_14K

#define E1000_PBA_14K   0x000E /* 14KB */

Definition at line 650 of file igbvf_defines.h.

E1000_PBA_16K

#define E1000_PBA_16K   0x0010 /* 16KB */

Definition at line 651 of file igbvf_defines.h.

E1000_PBA_18K

#define E1000_PBA_18K   0x0012

Definition at line 652 of file igbvf_defines.h.

E1000_PBA_20K

#define E1000_PBA_20K   0x0014

Definition at line 653 of file igbvf_defines.h.

E1000_PBA_22K

#define E1000_PBA_22K   0x0016

Definition at line 654 of file igbvf_defines.h.

E1000_PBA_24K

#define E1000_PBA_24K   0x0018

Definition at line 655 of file igbvf_defines.h.

E1000_PBA_26K

#define E1000_PBA_26K   0x001A

Definition at line 656 of file igbvf_defines.h.

E1000_PBA_30K

#define E1000_PBA_30K   0x001E

Definition at line 657 of file igbvf_defines.h.

E1000_PBA_32K

#define E1000_PBA_32K   0x0020

Definition at line 658 of file igbvf_defines.h.

E1000_PBA_34K

#define E1000_PBA_34K   0x0022

Definition at line 659 of file igbvf_defines.h.

E1000_PBA_35K

#define E1000_PBA_35K   0x0023

Definition at line 660 of file igbvf_defines.h.

E1000_PBA_38K

#define E1000_PBA_38K   0x0026

Definition at line 661 of file igbvf_defines.h.

E1000_PBA_40K

#define E1000_PBA_40K   0x0028

Definition at line 662 of file igbvf_defines.h.

E1000_PBA_48K

#define E1000_PBA_48K   0x0030 /* 48KB */

Definition at line 663 of file igbvf_defines.h.

E1000_PBA_64K

#define E1000_PBA_64K   0x0040 /* 64KB */

Definition at line 664 of file igbvf_defines.h.

E1000_PBS_16K

#define E1000_PBS_16K   E1000_PBA_16K

Definition at line 666 of file igbvf_defines.h.

E1000_PBS_24K

#define E1000_PBS_24K   E1000_PBA_24K

Definition at line 667 of file igbvf_defines.h.

IFS_MAX

#define IFS_MAX   80

Definition at line 669 of file igbvf_defines.h.

IFS_MIN

#define IFS_MIN   40

Definition at line 670 of file igbvf_defines.h.

IFS_RATIO

#define IFS_RATIO   4

Definition at line 671 of file igbvf_defines.h.

IFS_STEP

#define IFS_STEP   10

Definition at line 672 of file igbvf_defines.h.

MIN_NUM_XMITS

#define MIN_NUM_XMITS   1000

Definition at line 673 of file igbvf_defines.h.

E1000_SWSM_SMBI

#define E1000_SWSM_SMBI   0x00000001 /* Driver Semaphore bit */

Definition at line 676 of file igbvf_defines.h.

E1000_SWSM_SWESMBI

#define E1000_SWSM_SWESMBI   0x00000002 /* FW Semaphore bit */

Definition at line 677 of file igbvf_defines.h.

E1000_SWSM_WMNG

#define E1000_SWSM_WMNG   0x00000004 /* Wake MNG Clock */

Definition at line 678 of file igbvf_defines.h.

E1000_SWSM_DRV_LOAD

#define E1000_SWSM_DRV_LOAD   0x00000008 /* Driver Loaded Bit */

Definition at line 679 of file igbvf_defines.h.

E1000_SWSM2_LOCK

#define E1000_SWSM2_LOCK   0x00000002 /* Secondary driver semaphore bit */

Definition at line 681 of file igbvf_defines.h.

E1000_ICR_TXDW

#define E1000_ICR_TXDW   0x00000001 /* Transmit desc written back */

Definition at line 684 of file igbvf_defines.h.

E1000_ICR_TXQE

#define E1000_ICR_TXQE   0x00000002 /* Transmit Queue empty */

Definition at line 685 of file igbvf_defines.h.

E1000_ICR_LSC

#define E1000_ICR_LSC   0x00000004 /* Link Status Change */

Definition at line 686 of file igbvf_defines.h.

E1000_ICR_RXSEQ

#define E1000_ICR_RXSEQ   0x00000008 /* rx sequence error */

Definition at line 687 of file igbvf_defines.h.

E1000_ICR_RXDMT0

#define E1000_ICR_RXDMT0   0x00000010 /* rx desc min. threshold (0) */

Definition at line 688 of file igbvf_defines.h.

E1000_ICR_RXO

#define E1000_ICR_RXO   0x00000040 /* rx overrun */

Definition at line 689 of file igbvf_defines.h.

E1000_ICR_RXT0

#define E1000_ICR_RXT0   0x00000080 /* rx timer intr (ring 0) */

Definition at line 690 of file igbvf_defines.h.

E1000_ICR_VMMB

#define E1000_ICR_VMMB   0x00000100 /* VM MB event */

Definition at line 691 of file igbvf_defines.h.

E1000_ICR_MDAC

#define E1000_ICR_MDAC   0x00000200 /* MDIO access complete */

Definition at line 692 of file igbvf_defines.h.

E1000_ICR_RXCFG

#define E1000_ICR_RXCFG   0x00000400 /* Rx /c/ ordered set */

Definition at line 693 of file igbvf_defines.h.

E1000_ICR_GPI_EN0

#define E1000_ICR_GPI_EN0   0x00000800 /* GP Int 0 */

Definition at line 694 of file igbvf_defines.h.

E1000_ICR_GPI_EN1

#define E1000_ICR_GPI_EN1   0x00001000 /* GP Int 1 */

Definition at line 695 of file igbvf_defines.h.

E1000_ICR_GPI_EN2

#define E1000_ICR_GPI_EN2   0x00002000 /* GP Int 2 */

Definition at line 696 of file igbvf_defines.h.

E1000_ICR_GPI_EN3

#define E1000_ICR_GPI_EN3   0x00004000 /* GP Int 3 */

Definition at line 697 of file igbvf_defines.h.

E1000_ICR_TXD_LOW

#define E1000_ICR_TXD_LOW   0x00008000

Definition at line 698 of file igbvf_defines.h.

E1000_ICR_SRPD

#define E1000_ICR_SRPD   0x00010000

Definition at line 699 of file igbvf_defines.h.

E1000_ICR_ACK

#define E1000_ICR_ACK   0x00020000 /* Receive Ack frame */

Definition at line 700 of file igbvf_defines.h.

E1000_ICR_MNG

#define E1000_ICR_MNG   0x00040000 /* Manageability event */

Definition at line 701 of file igbvf_defines.h.

E1000_ICR_DOCK

#define E1000_ICR_DOCK   0x00080000 /* Dock/Undock */

Definition at line 702 of file igbvf_defines.h.

E1000_ICR_INT_ASSERTED

#define E1000_ICR_INT_ASSERTED

Value:

0x80000000 /* If this bit asserted, the driver
                                            * should claim the interrupt */

Definition at line 703 of file igbvf_defines.h.

E1000_ICR_RXD_FIFO_PAR0

#define E1000_ICR_RXD_FIFO_PAR0   0x00100000 /* Q0 Rx desc FIFO parity error */

Definition at line 705 of file igbvf_defines.h.

E1000_ICR_TXD_FIFO_PAR0

#define E1000_ICR_TXD_FIFO_PAR0   0x00200000 /* Q0 Tx desc FIFO parity error */

Definition at line 706 of file igbvf_defines.h.

E1000_ICR_HOST_ARB_PAR

#define E1000_ICR_HOST_ARB_PAR   0x00400000 /* host arb read buffer parity err */

Definition at line 707 of file igbvf_defines.h.

E1000_ICR_PB_PAR

#define E1000_ICR_PB_PAR   0x00800000 /* packet buffer parity error */

Definition at line 708 of file igbvf_defines.h.

E1000_ICR_RXD_FIFO_PAR1

#define E1000_ICR_RXD_FIFO_PAR1   0x01000000 /* Q1 Rx desc FIFO parity error */

Definition at line 709 of file igbvf_defines.h.

E1000_ICR_TXD_FIFO_PAR1

#define E1000_ICR_TXD_FIFO_PAR1   0x02000000 /* Q1 Tx desc FIFO parity error */

Definition at line 710 of file igbvf_defines.h.

E1000_ICR_ALL_PARITY

#define E1000_ICR_ALL_PARITY   0x03F00000 /* all parity error bits */

Definition at line 711 of file igbvf_defines.h.

E1000_ICR_DSW

#define E1000_ICR_DSW

Value:

0x00000020 /* FW changed the status of DISSW
                                            * bit in the FWSM */

Definition at line 712 of file igbvf_defines.h.

E1000_ICR_PHYINT

#define E1000_ICR_PHYINT

Value:

0x00001000 /* LAN connected device generates
                                            * an interrupt */

Definition at line 714 of file igbvf_defines.h.

E1000_ICR_DOUTSYNC

#define E1000_ICR_DOUTSYNC   0x10000000 /* NIC DMA out of sync */

Definition at line 716 of file igbvf_defines.h.

E1000_ICR_EPRST

#define E1000_ICR_EPRST   0x00100000 /* ME hardware reset occurs */

Definition at line 717 of file igbvf_defines.h.

POLL_IMS_ENABLE_MASK

#define POLL_IMS_ENABLE_MASK

Value:

( \
    E1000_IMS_RXDMT0 |    \
    E1000_IMS_RXSEQ)

Definition at line 726 of file igbvf_defines.h.

IMS_ENABLE_MASK

#define IMS_ENABLE_MASK

Value:

( \
    E1000_IMS_RXT0   |    \
    E1000_IMS_TXDW   |    \
    E1000_IMS_RXDMT0 |    \
    E1000_IMS_RXSEQ  |    \
    E1000_IMS_LSC)

Definition at line 739 of file igbvf_defines.h.

E1000_IMS_TXDW

#define E1000_IMS_TXDW   E1000_ICR_TXDW /* Tx desc written back */

Definition at line 747 of file igbvf_defines.h.

E1000_IMS_TXQE

#define E1000_IMS_TXQE   E1000_ICR_TXQE /* Transmit Queue empty */

Definition at line 748 of file igbvf_defines.h.

E1000_IMS_LSC

#define E1000_IMS_LSC   E1000_ICR_LSC /* Link Status Change */

Definition at line 749 of file igbvf_defines.h.

E1000_IMS_VMMB

#define E1000_IMS_VMMB   E1000_ICR_VMMB /* Mail box activity */

Definition at line 750 of file igbvf_defines.h.

E1000_IMS_RXSEQ

#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ /* rx sequence error */

Definition at line 751 of file igbvf_defines.h.

E1000_IMS_RXDMT0

#define E1000_IMS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */

Definition at line 752 of file igbvf_defines.h.

E1000_IMS_RXO

#define E1000_IMS_RXO   E1000_ICR_RXO /* rx overrun */

Definition at line 753 of file igbvf_defines.h.

E1000_IMS_RXT0

#define E1000_IMS_RXT0   E1000_ICR_RXT0 /* rx timer intr */

Definition at line 754 of file igbvf_defines.h.

E1000_IMS_MDAC

#define E1000_IMS_MDAC   E1000_ICR_MDAC /* MDIO access complete */

Definition at line 755 of file igbvf_defines.h.

E1000_IMS_RXCFG

#define E1000_IMS_RXCFG   E1000_ICR_RXCFG /* Rx /c/ ordered set */

Definition at line 756 of file igbvf_defines.h.

E1000_IMS_GPI_EN0

#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0 /* GP Int 0 */

Definition at line 757 of file igbvf_defines.h.

E1000_IMS_GPI_EN1

#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1 /* GP Int 1 */

Definition at line 758 of file igbvf_defines.h.

E1000_IMS_GPI_EN2

#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2 /* GP Int 2 */

Definition at line 759 of file igbvf_defines.h.

E1000_IMS_GPI_EN3

#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3 /* GP Int 3 */

Definition at line 760 of file igbvf_defines.h.

E1000_IMS_TXD_LOW

#define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW

Definition at line 761 of file igbvf_defines.h.

E1000_IMS_SRPD

#define E1000_IMS_SRPD   E1000_ICR_SRPD

Definition at line 762 of file igbvf_defines.h.

E1000_IMS_ACK

#define E1000_IMS_ACK   E1000_ICR_ACK /* Receive Ack frame */

Definition at line 763 of file igbvf_defines.h.

E1000_IMS_MNG

#define E1000_IMS_MNG   E1000_ICR_MNG /* Manageability event */

Definition at line 764 of file igbvf_defines.h.

E1000_IMS_DOCK

#define E1000_IMS_DOCK   E1000_ICR_DOCK /* Dock/Undock */

Definition at line 765 of file igbvf_defines.h.

E1000_IMS_RXD_FIFO_PAR0

#define E1000_IMS_RXD_FIFO_PAR0

Value:

E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
                                                         * parity error */

Definition at line 766 of file igbvf_defines.h.

E1000_IMS_TXD_FIFO_PAR0

#define E1000_IMS_TXD_FIFO_PAR0

Value:

E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
                                                         * parity error */

Definition at line 768 of file igbvf_defines.h.

E1000_IMS_HOST_ARB_PAR

#define E1000_IMS_HOST_ARB_PAR

Value:

E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
                                                         * parity error */

Definition at line 770 of file igbvf_defines.h.

E1000_IMS_PB_PAR

#define E1000_IMS_PB_PAR

Value:

E1000_ICR_PB_PAR        /* packet buffer parity
                                                         * error */

Definition at line 772 of file igbvf_defines.h.

E1000_IMS_RXD_FIFO_PAR1

#define E1000_IMS_RXD_FIFO_PAR1

Value:

E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
                                                         * parity error */

Definition at line 774 of file igbvf_defines.h.

E1000_IMS_TXD_FIFO_PAR1

#define E1000_IMS_TXD_FIFO_PAR1

Value:

E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
                                                         * parity error */

Definition at line 776 of file igbvf_defines.h.

E1000_IMS_DSW

#define E1000_IMS_DSW   E1000_ICR_DSW

Definition at line 778 of file igbvf_defines.h.

E1000_IMS_PHYINT

#define E1000_IMS_PHYINT   E1000_ICR_PHYINT

Definition at line 779 of file igbvf_defines.h.

E1000_IMS_DOUTSYNC

#define E1000_IMS_DOUTSYNC   E1000_ICR_DOUTSYNC /* NIC DMA out of sync */

Definition at line 780 of file igbvf_defines.h.

E1000_IMS_EPRST

#define E1000_IMS_EPRST   E1000_ICR_EPRST

Definition at line 781 of file igbvf_defines.h.

E1000_ICS_TXDW

#define E1000_ICS_TXDW   E1000_ICR_TXDW /* Tx desc written back */

Definition at line 784 of file igbvf_defines.h.

E1000_ICS_TXQE

#define E1000_ICS_TXQE   E1000_ICR_TXQE /* Transmit Queue empty */

Definition at line 785 of file igbvf_defines.h.

E1000_ICS_LSC

#define E1000_ICS_LSC   E1000_ICR_LSC /* Link Status Change */

Definition at line 786 of file igbvf_defines.h.

E1000_ICS_RXSEQ

#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ /* rx sequence error */

Definition at line 787 of file igbvf_defines.h.

E1000_ICS_RXDMT0

#define E1000_ICS_RXDMT0   E1000_ICR_RXDMT0 /* rx desc min. threshold */

Definition at line 788 of file igbvf_defines.h.

E1000_ICS_RXO

#define E1000_ICS_RXO   E1000_ICR_RXO /* rx overrun */

Definition at line 789 of file igbvf_defines.h.

E1000_ICS_RXT0

#define E1000_ICS_RXT0   E1000_ICR_RXT0 /* rx timer intr */

Definition at line 790 of file igbvf_defines.h.

E1000_ICS_MDAC

#define E1000_ICS_MDAC   E1000_ICR_MDAC /* MDIO access complete */

Definition at line 791 of file igbvf_defines.h.

E1000_ICS_RXCFG

#define E1000_ICS_RXCFG   E1000_ICR_RXCFG /* Rx /c/ ordered set */

Definition at line 792 of file igbvf_defines.h.

E1000_ICS_GPI_EN0

#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0 /* GP Int 0 */

Definition at line 793 of file igbvf_defines.h.

E1000_ICS_GPI_EN1

#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1 /* GP Int 1 */

Definition at line 794 of file igbvf_defines.h.

E1000_ICS_GPI_EN2

#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2 /* GP Int 2 */

Definition at line 795 of file igbvf_defines.h.

E1000_ICS_GPI_EN3

#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3 /* GP Int 3 */

Definition at line 796 of file igbvf_defines.h.

E1000_ICS_TXD_LOW

#define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW

Definition at line 797 of file igbvf_defines.h.

E1000_ICS_SRPD

#define E1000_ICS_SRPD   E1000_ICR_SRPD

Definition at line 798 of file igbvf_defines.h.

E1000_ICS_ACK

#define E1000_ICS_ACK   E1000_ICR_ACK /* Receive Ack frame */

Definition at line 799 of file igbvf_defines.h.

E1000_ICS_MNG

#define E1000_ICS_MNG   E1000_ICR_MNG /* Manageability event */

Definition at line 800 of file igbvf_defines.h.

E1000_ICS_DOCK

#define E1000_ICS_DOCK   E1000_ICR_DOCK /* Dock/Undock */

Definition at line 801 of file igbvf_defines.h.

E1000_ICS_RXD_FIFO_PAR0

#define E1000_ICS_RXD_FIFO_PAR0

Value:

E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
                                                         * parity error */

Definition at line 802 of file igbvf_defines.h.

E1000_ICS_TXD_FIFO_PAR0

#define E1000_ICS_TXD_FIFO_PAR0

Value:

E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
                                                         * parity error */

Definition at line 804 of file igbvf_defines.h.

E1000_ICS_HOST_ARB_PAR

#define E1000_ICS_HOST_ARB_PAR

Value:

E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
                                                         * parity error */

Definition at line 806 of file igbvf_defines.h.

E1000_ICS_PB_PAR

#define E1000_ICS_PB_PAR

Value:

E1000_ICR_PB_PAR        /* packet buffer parity
                                                         * error */

Definition at line 808 of file igbvf_defines.h.

E1000_ICS_RXD_FIFO_PAR1

#define E1000_ICS_RXD_FIFO_PAR1

Value:

E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
                                                         * parity error */

Definition at line 810 of file igbvf_defines.h.

E1000_ICS_TXD_FIFO_PAR1

#define E1000_ICS_TXD_FIFO_PAR1

Value:

E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
                                                         * parity error */

Definition at line 812 of file igbvf_defines.h.

E1000_ICS_DSW

#define E1000_ICS_DSW   E1000_ICR_DSW

Definition at line 814 of file igbvf_defines.h.

E1000_ICS_DOUTSYNC

#define E1000_ICS_DOUTSYNC   E1000_ICR_DOUTSYNC /* NIC DMA out of sync */

Definition at line 815 of file igbvf_defines.h.

E1000_ICS_PHYINT

#define E1000_ICS_PHYINT   E1000_ICR_PHYINT

Definition at line 816 of file igbvf_defines.h.

E1000_ICS_EPRST

#define E1000_ICS_EPRST   E1000_ICR_EPRST

Definition at line 817 of file igbvf_defines.h.

E1000_TXDCTL_PTHRESH

#define E1000_TXDCTL_PTHRESH   0x0000003F /* TXDCTL Prefetch Threshold */

Definition at line 820 of file igbvf_defines.h.

E1000_TXDCTL_HTHRESH

#define E1000_TXDCTL_HTHRESH   0x00003F00 /* TXDCTL Host Threshold */

Definition at line 821 of file igbvf_defines.h.

E1000_TXDCTL_WTHRESH

#define E1000_TXDCTL_WTHRESH   0x003F0000 /* TXDCTL Writeback Threshold */

Definition at line 822 of file igbvf_defines.h.

E1000_TXDCTL_GRAN

#define E1000_TXDCTL_GRAN   0x01000000 /* TXDCTL Granularity */

Definition at line 823 of file igbvf_defines.h.

E1000_TXDCTL_LWTHRESH

#define E1000_TXDCTL_LWTHRESH   0xFE000000 /* TXDCTL Low Threshold */

Definition at line 824 of file igbvf_defines.h.

E1000_TXDCTL_FULL_TX_DESC_WB

#define E1000_TXDCTL_FULL_TX_DESC_WB   0x01010000 /* GRAN=1, WTHRESH=1 */

Definition at line 825 of file igbvf_defines.h.

E1000_TXDCTL_MAX_TX_DESC_PREFETCH

#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH   0x0100001F /* GRAN=1, PTHRESH=31 */

Definition at line 826 of file igbvf_defines.h.

E1000_TXDCTL_COUNT_DESC

#define E1000_TXDCTL_COUNT_DESC   0x00400000

Definition at line 828 of file igbvf_defines.h.

FLOW_CONTROL_ADDRESS_LOW

#define FLOW_CONTROL_ADDRESS_LOW   0x00C28001

Definition at line 831 of file igbvf_defines.h.

FLOW_CONTROL_ADDRESS_HIGH

#define FLOW_CONTROL_ADDRESS_HIGH   0x00000100

Definition at line 832 of file igbvf_defines.h.

FLOW_CONTROL_TYPE

#define FLOW_CONTROL_TYPE   0x8808

Definition at line 833 of file igbvf_defines.h.

VLAN_TAG_SIZE

#define VLAN_TAG_SIZE   4 /* 802.3ac tag (not DMA'd) */

Definition at line 836 of file igbvf_defines.h.

E1000_VLAN_FILTER_TBL_SIZE

#define E1000_VLAN_FILTER_TBL_SIZE   128 /* VLAN Filter Table (4096 bits) */

Definition at line 837 of file igbvf_defines.h.

E1000_RAR_ENTRIES

#define E1000_RAR_ENTRIES   15

Definition at line 847 of file igbvf_defines.h.

E1000_RAH_AV

#define E1000_RAH_AV   0x80000000 /* Receive descriptor valid */

Definition at line 848 of file igbvf_defines.h.

E1000_RAL_MAC_ADDR_LEN

#define E1000_RAL_MAC_ADDR_LEN   4

Definition at line 849 of file igbvf_defines.h.

E1000_RAH_MAC_ADDR_LEN

#define E1000_RAH_MAC_ADDR_LEN   2

Definition at line 850 of file igbvf_defines.h.

E1000_RAH_POOL_MASK

#define E1000_RAH_POOL_MASK   0x03FC0000

Definition at line 851 of file igbvf_defines.h.

E1000_RAH_POOL_1

#define E1000_RAH_POOL_1   0x00040000

Definition at line 852 of file igbvf_defines.h.

E1000_SUCCESS

#define E1000_SUCCESS   0

Definition at line 855 of file igbvf_defines.h.

E1000_ERR_NVM

#define E1000_ERR_NVM   1

Definition at line 856 of file igbvf_defines.h.

E1000_ERR_PHY

#define E1000_ERR_PHY   2

Definition at line 857 of file igbvf_defines.h.

E1000_ERR_CONFIG

#define E1000_ERR_CONFIG   3

Definition at line 858 of file igbvf_defines.h.

E1000_ERR_PARAM

#define E1000_ERR_PARAM   4

Definition at line 859 of file igbvf_defines.h.

E1000_ERR_MAC_INIT

#define E1000_ERR_MAC_INIT   5

Definition at line 860 of file igbvf_defines.h.

E1000_ERR_PHY_TYPE

#define E1000_ERR_PHY_TYPE   6

Definition at line 861 of file igbvf_defines.h.

E1000_ERR_RESET

#define E1000_ERR_RESET   9

Definition at line 862 of file igbvf_defines.h.

E1000_ERR_MASTER_REQUESTS_PENDING

#define E1000_ERR_MASTER_REQUESTS_PENDING   10

Definition at line 863 of file igbvf_defines.h.

E1000_ERR_HOST_INTERFACE_COMMAND

#define E1000_ERR_HOST_INTERFACE_COMMAND   11

Definition at line 864 of file igbvf_defines.h.

E1000_BLK_PHY_RESET

#define E1000_BLK_PHY_RESET   12

Definition at line 865 of file igbvf_defines.h.

E1000_ERR_SWFW_SYNC

#define E1000_ERR_SWFW_SYNC   13

Definition at line 866 of file igbvf_defines.h.

E1000_NOT_IMPLEMENTED

#define E1000_NOT_IMPLEMENTED   14

Definition at line 867 of file igbvf_defines.h.

E1000_ERR_MBX

#define E1000_ERR_MBX   15

Definition at line 868 of file igbvf_defines.h.

FIBER_LINK_UP_LIMIT

#define FIBER_LINK_UP_LIMIT   50

Definition at line 871 of file igbvf_defines.h.

COPPER_LINK_UP_LIMIT

#define COPPER_LINK_UP_LIMIT   10

Definition at line 872 of file igbvf_defines.h.

PHY_AUTO_NEG_LIMIT

#define PHY_AUTO_NEG_LIMIT   45

Definition at line 873 of file igbvf_defines.h.

PHY_FORCE_LIMIT

#define PHY_FORCE_LIMIT   20

Definition at line 874 of file igbvf_defines.h.

MASTER_DISABLE_TIMEOUT

#define MASTER_DISABLE_TIMEOUT   800

Definition at line 876 of file igbvf_defines.h.

PHY_CFG_TIMEOUT

#define PHY_CFG_TIMEOUT   100

Definition at line 878 of file igbvf_defines.h.

MDIO_OWNERSHIP_TIMEOUT

#define MDIO_OWNERSHIP_TIMEOUT   10

Definition at line 880 of file igbvf_defines.h.

AUTO_READ_DONE_TIMEOUT

#define AUTO_READ_DONE_TIMEOUT   10

Definition at line 882 of file igbvf_defines.h.

E1000_FCRTH_RTH

#define E1000_FCRTH_RTH   0x0000FFF8 /* Mask Bits[15:3] for RTH */

Definition at line 885 of file igbvf_defines.h.

E1000_FCRTH_XFCE

#define E1000_FCRTH_XFCE   0x80000000 /* External Flow Control Enable */

Definition at line 886 of file igbvf_defines.h.

E1000_FCRTL_RTL

#define E1000_FCRTL_RTL   0x0000FFF8 /* Mask Bits[15:3] for RTL */

Definition at line 887 of file igbvf_defines.h.

E1000_FCRTL_XONE

#define E1000_FCRTL_XONE   0x80000000 /* Enable XON frame transmission */

Definition at line 888 of file igbvf_defines.h.

E1000_TXCW_FD

#define E1000_TXCW_FD   0x00000020 /* TXCW full duplex */

Definition at line 891 of file igbvf_defines.h.

E1000_TXCW_HD

#define E1000_TXCW_HD   0x00000040 /* TXCW half duplex */

Definition at line 892 of file igbvf_defines.h.

E1000_TXCW_PAUSE

#define E1000_TXCW_PAUSE   0x00000080 /* TXCW sym pause request */

Definition at line 893 of file igbvf_defines.h.

E1000_TXCW_ASM_DIR

#define E1000_TXCW_ASM_DIR   0x00000100 /* TXCW astm pause direction */

Definition at line 894 of file igbvf_defines.h.

E1000_TXCW_PAUSE_MASK

#define E1000_TXCW_PAUSE_MASK   0x00000180 /* TXCW pause request mask */

Definition at line 895 of file igbvf_defines.h.

E1000_TXCW_RF

#define E1000_TXCW_RF   0x00003000 /* TXCW remote fault */

Definition at line 896 of file igbvf_defines.h.

E1000_TXCW_NP

#define E1000_TXCW_NP   0x00008000 /* TXCW next page */

Definition at line 897 of file igbvf_defines.h.

E1000_TXCW_CW

#define E1000_TXCW_CW   0x0000ffff /* TxConfigWord mask */

Definition at line 898 of file igbvf_defines.h.

E1000_TXCW_TXC

#define E1000_TXCW_TXC   0x40000000 /* Transmit Config control */

Definition at line 899 of file igbvf_defines.h.

E1000_TXCW_ANE

#define E1000_TXCW_ANE   0x80000000 /* Auto-neg enable */

Definition at line 900 of file igbvf_defines.h.

E1000_RXCW_CW

#define E1000_RXCW_CW   0x0000ffff /* RxConfigWord mask */

Definition at line 903 of file igbvf_defines.h.

E1000_RXCW_NC

#define E1000_RXCW_NC   0x04000000 /* Receive config no carrier */

Definition at line 904 of file igbvf_defines.h.

E1000_RXCW_IV

#define E1000_RXCW_IV   0x08000000 /* Receive config invalid */

Definition at line 905 of file igbvf_defines.h.

E1000_RXCW_CC

#define E1000_RXCW_CC   0x10000000 /* Receive config change */

Definition at line 906 of file igbvf_defines.h.

E1000_RXCW_C

#define E1000_RXCW_C   0x20000000 /* Receive config */

Definition at line 907 of file igbvf_defines.h.

E1000_RXCW_SYNCH

#define E1000_RXCW_SYNCH   0x40000000 /* Receive config synch */

Definition at line 908 of file igbvf_defines.h.

E1000_RXCW_ANC

#define E1000_RXCW_ANC   0x80000000 /* Auto-neg complete */

Definition at line 909 of file igbvf_defines.h.

E1000_GCR_RXD_NO_SNOOP

#define E1000_GCR_RXD_NO_SNOOP   0x00000001

Definition at line 913 of file igbvf_defines.h.

E1000_GCR_RXDSCW_NO_SNOOP

#define E1000_GCR_RXDSCW_NO_SNOOP   0x00000002

Definition at line 914 of file igbvf_defines.h.

E1000_GCR_RXDSCR_NO_SNOOP

#define E1000_GCR_RXDSCR_NO_SNOOP   0x00000004

Definition at line 915 of file igbvf_defines.h.

E1000_GCR_TXD_NO_SNOOP

#define E1000_GCR_TXD_NO_SNOOP   0x00000008

Definition at line 916 of file igbvf_defines.h.

E1000_GCR_TXDSCW_NO_SNOOP

#define E1000_GCR_TXDSCW_NO_SNOOP   0x00000010

Definition at line 917 of file igbvf_defines.h.

E1000_GCR_TXDSCR_NO_SNOOP

#define E1000_GCR_TXDSCR_NO_SNOOP   0x00000020

Definition at line 918 of file igbvf_defines.h.

E1000_GCR_CMPL_TMOUT_MASK

#define E1000_GCR_CMPL_TMOUT_MASK   0x0000F000

Definition at line 919 of file igbvf_defines.h.

E1000_GCR_CMPL_TMOUT_10ms

#define E1000_GCR_CMPL_TMOUT_10ms   0x00001000

Definition at line 920 of file igbvf_defines.h.

E1000_GCR_CMPL_TMOUT_RESEND

#define E1000_GCR_CMPL_TMOUT_RESEND   0x00010000

Definition at line 921 of file igbvf_defines.h.

E1000_GCR_CAP_VER2

#define E1000_GCR_CAP_VER2   0x00040000

Definition at line 922 of file igbvf_defines.h.

PCIE_NO_SNOOP_ALL

#define PCIE_NO_SNOOP_ALL

Value:

(E1000_GCR_RXD_NO_SNOOP         | \
                           E1000_GCR_RXDSCW_NO_SNOOP      | \
                           E1000_GCR_RXDSCR_NO_SNOOP      | \
                           E1000_GCR_TXD_NO_SNOOP         | \
                           E1000_GCR_TXDSCW_NO_SNOOP      | \
                           E1000_GCR_TXDSCR_NO_SNOOP)

Definition at line 924 of file igbvf_defines.h.

MII_CR_SPEED_SELECT_MSB

#define MII_CR_SPEED_SELECT_MSB   0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */

Definition at line 932 of file igbvf_defines.h.

MII_CR_COLL_TEST_ENABLE

#define MII_CR_COLL_TEST_ENABLE   0x0080 /* Collision test enable */

Definition at line 933 of file igbvf_defines.h.

MII_CR_FULL_DUPLEX

#define MII_CR_FULL_DUPLEX   0x0100 /* FDX =1, half duplex =0 */

Definition at line 934 of file igbvf_defines.h.

MII_CR_RESTART_AUTO_NEG

#define MII_CR_RESTART_AUTO_NEG   0x0200 /* Restart auto negotiation */

Definition at line 935 of file igbvf_defines.h.

MII_CR_ISOLATE

#define MII_CR_ISOLATE   0x0400 /* Isolate PHY from MII */

Definition at line 936 of file igbvf_defines.h.

MII_CR_POWER_DOWN

#define MII_CR_POWER_DOWN   0x0800 /* Power down */

Definition at line 937 of file igbvf_defines.h.

MII_CR_AUTO_NEG_EN

#define MII_CR_AUTO_NEG_EN   0x1000 /* Auto Neg Enable */

Definition at line 938 of file igbvf_defines.h.

MII_CR_SPEED_SELECT_LSB

#define MII_CR_SPEED_SELECT_LSB   0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */

Definition at line 939 of file igbvf_defines.h.

MII_CR_LOOPBACK

#define MII_CR_LOOPBACK   0x4000 /* 0 = normal, 1 = loopback */

Definition at line 940 of file igbvf_defines.h.

MII_CR_RESET

#define MII_CR_RESET   0x8000 /* 0 = normal, 1 = PHY reset */

Definition at line 941 of file igbvf_defines.h.

MII_CR_SPEED_1000

#define MII_CR_SPEED_1000   0x0040

Definition at line 942 of file igbvf_defines.h.

MII_CR_SPEED_100

#define MII_CR_SPEED_100   0x2000

Definition at line 943 of file igbvf_defines.h.

MII_CR_SPEED_10

#define MII_CR_SPEED_10   0x0000

Definition at line 944 of file igbvf_defines.h.

MII_SR_EXTENDED_CAPS

#define MII_SR_EXTENDED_CAPS   0x0001 /* Extended register capabilities */

Definition at line 947 of file igbvf_defines.h.

MII_SR_JABBER_DETECT

#define MII_SR_JABBER_DETECT   0x0002 /* Jabber Detected */

Definition at line 948 of file igbvf_defines.h.

MII_SR_LINK_STATUS

#define MII_SR_LINK_STATUS   0x0004 /* Link Status 1 = link */

Definition at line 949 of file igbvf_defines.h.

MII_SR_AUTONEG_CAPS

#define MII_SR_AUTONEG_CAPS   0x0008 /* Auto Neg Capable */

Definition at line 950 of file igbvf_defines.h.

MII_SR_REMOTE_FAULT

#define MII_SR_REMOTE_FAULT   0x0010 /* Remote Fault Detect */

Definition at line 951 of file igbvf_defines.h.

MII_SR_AUTONEG_COMPLETE

#define MII_SR_AUTONEG_COMPLETE   0x0020 /* Auto Neg Complete */

Definition at line 952 of file igbvf_defines.h.

MII_SR_PREAMBLE_SUPPRESS

#define MII_SR_PREAMBLE_SUPPRESS   0x0040 /* Preamble may be suppressed */

Definition at line 953 of file igbvf_defines.h.

MII_SR_EXTENDED_STATUS

#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */

Definition at line 954 of file igbvf_defines.h.

MII_SR_100T2_HD_CAPS

#define MII_SR_100T2_HD_CAPS   0x0200 /* 100T2 Half Duplex Capable */

Definition at line 955 of file igbvf_defines.h.

MII_SR_100T2_FD_CAPS

#define MII_SR_100T2_FD_CAPS   0x0400 /* 100T2 Full Duplex Capable */

Definition at line 956 of file igbvf_defines.h.

MII_SR_10T_HD_CAPS

#define MII_SR_10T_HD_CAPS   0x0800 /* 10T Half Duplex Capable */

Definition at line 957 of file igbvf_defines.h.

MII_SR_10T_FD_CAPS

#define MII_SR_10T_FD_CAPS   0x1000 /* 10T Full Duplex Capable */

Definition at line 958 of file igbvf_defines.h.

MII_SR_100X_HD_CAPS

#define MII_SR_100X_HD_CAPS   0x2000 /* 100X Half Duplex Capable */

Definition at line 959 of file igbvf_defines.h.

MII_SR_100X_FD_CAPS

#define MII_SR_100X_FD_CAPS   0x4000 /* 100X Full Duplex Capable */

Definition at line 960 of file igbvf_defines.h.

MII_SR_100T4_CAPS

#define MII_SR_100T4_CAPS   0x8000 /* 100T4 Capable */

Definition at line 961 of file igbvf_defines.h.

NWAY_AR_SELECTOR_FIELD

#define NWAY_AR_SELECTOR_FIELD   0x0001 /* indicates IEEE 802.3 CSMA/CD */

Definition at line 964 of file igbvf_defines.h.

NWAY_AR_10T_HD_CAPS

#define NWAY_AR_10T_HD_CAPS   0x0020 /* 10T Half Duplex Capable */

Definition at line 965 of file igbvf_defines.h.

NWAY_AR_10T_FD_CAPS

#define NWAY_AR_10T_FD_CAPS   0x0040 /* 10T Full Duplex Capable */

Definition at line 966 of file igbvf_defines.h.

NWAY_AR_100TX_HD_CAPS

#define NWAY_AR_100TX_HD_CAPS   0x0080 /* 100TX Half Duplex Capable */

Definition at line 967 of file igbvf_defines.h.

NWAY_AR_100TX_FD_CAPS

#define NWAY_AR_100TX_FD_CAPS   0x0100 /* 100TX Full Duplex Capable */

Definition at line 968 of file igbvf_defines.h.

NWAY_AR_100T4_CAPS

#define NWAY_AR_100T4_CAPS   0x0200 /* 100T4 Capable */

Definition at line 969 of file igbvf_defines.h.

NWAY_AR_PAUSE

#define NWAY_AR_PAUSE   0x0400 /* Pause operation desired */

Definition at line 970 of file igbvf_defines.h.

NWAY_AR_ASM_DIR

#define NWAY_AR_ASM_DIR   0x0800 /* Asymmetric Pause Direction bit */

Definition at line 971 of file igbvf_defines.h.

NWAY_AR_REMOTE_FAULT

#define NWAY_AR_REMOTE_FAULT   0x2000 /* Remote Fault detected */

Definition at line 972 of file igbvf_defines.h.

NWAY_AR_NEXT_PAGE

#define NWAY_AR_NEXT_PAGE   0x8000 /* Next Page ability supported */

Definition at line 973 of file igbvf_defines.h.

NWAY_LPAR_SELECTOR_FIELD

#define NWAY_LPAR_SELECTOR_FIELD   0x0000 /* LP protocol selector field */

Definition at line 976 of file igbvf_defines.h.

NWAY_LPAR_10T_HD_CAPS

#define NWAY_LPAR_10T_HD_CAPS   0x0020 /* LP is 10T Half Duplex Capable */

Definition at line 977 of file igbvf_defines.h.

NWAY_LPAR_10T_FD_CAPS

#define NWAY_LPAR_10T_FD_CAPS   0x0040 /* LP is 10T Full Duplex Capable */

Definition at line 978 of file igbvf_defines.h.

NWAY_LPAR_100TX_HD_CAPS

#define NWAY_LPAR_100TX_HD_CAPS   0x0080 /* LP is 100TX Half Duplex Capable */

Definition at line 979 of file igbvf_defines.h.

NWAY_LPAR_100TX_FD_CAPS

#define NWAY_LPAR_100TX_FD_CAPS   0x0100 /* LP is 100TX Full Duplex Capable */

Definition at line 980 of file igbvf_defines.h.

NWAY_LPAR_100T4_CAPS

#define NWAY_LPAR_100T4_CAPS   0x0200 /* LP is 100T4 Capable */

Definition at line 981 of file igbvf_defines.h.

NWAY_LPAR_PAUSE

#define NWAY_LPAR_PAUSE   0x0400 /* LP Pause operation desired */

Definition at line 982 of file igbvf_defines.h.

NWAY_LPAR_ASM_DIR

#define NWAY_LPAR_ASM_DIR   0x0800 /* LP Asymmetric Pause Direction bit */

Definition at line 983 of file igbvf_defines.h.

NWAY_LPAR_REMOTE_FAULT

#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */

Definition at line 984 of file igbvf_defines.h.

NWAY_LPAR_ACKNOWLEDGE

#define NWAY_LPAR_ACKNOWLEDGE   0x4000 /* LP has rx'd link code word */

Definition at line 985 of file igbvf_defines.h.

NWAY_LPAR_NEXT_PAGE

#define NWAY_LPAR_NEXT_PAGE   0x8000 /* Next Page ability supported */

Definition at line 986 of file igbvf_defines.h.

NWAY_ER_LP_NWAY_CAPS

#define NWAY_ER_LP_NWAY_CAPS   0x0001 /* LP has Auto Neg Capability */

Definition at line 989 of file igbvf_defines.h.

NWAY_ER_PAGE_RXD

#define NWAY_ER_PAGE_RXD   0x0002 /* LP is 10T Half Duplex Capable */

Definition at line 990 of file igbvf_defines.h.

NWAY_ER_NEXT_PAGE_CAPS

#define NWAY_ER_NEXT_PAGE_CAPS   0x0004 /* LP is 10T Full Duplex Capable */

Definition at line 991 of file igbvf_defines.h.

NWAY_ER_LP_NEXT_PAGE_CAPS

#define NWAY_ER_LP_NEXT_PAGE_CAPS   0x0008 /* LP is 100TX Half Duplex Capable */

Definition at line 992 of file igbvf_defines.h.

NWAY_ER_PAR_DETECT_FAULT

#define NWAY_ER_PAR_DETECT_FAULT   0x0010 /* LP is 100TX Full Duplex Capable */

Definition at line 993 of file igbvf_defines.h.

CR_1000T_ASYM_PAUSE

#define CR_1000T_ASYM_PAUSE   0x0080 /* Advertise asymmetric pause bit */

Definition at line 996 of file igbvf_defines.h.

CR_1000T_HD_CAPS

#define CR_1000T_HD_CAPS   0x0100 /* Advertise 1000T HD capability */

Definition at line 997 of file igbvf_defines.h.

CR_1000T_FD_CAPS

#define CR_1000T_FD_CAPS   0x0200 /* Advertise 1000T FD capability */

Definition at line 998 of file igbvf_defines.h.

CR_1000T_REPEATER_DTE

#define CR_1000T_REPEATER_DTE   0x0400 /* 1=Repeater/switch device port */

Definition at line 999 of file igbvf_defines.h.

CR_1000T_MS_VALUE

#define CR_1000T_MS_VALUE   0x0800 /* 1=Configure PHY as Master */

Definition at line 1001 of file igbvf_defines.h.

CR_1000T_MS_ENABLE

#define CR_1000T_MS_ENABLE   0x1000 /* 1=Master/Slave manual config value */

Definition at line 1003 of file igbvf_defines.h.

CR_1000T_TEST_MODE_NORMAL

#define CR_1000T_TEST_MODE_NORMAL   0x0000 /* Normal Operation */

Definition at line 1005 of file igbvf_defines.h.

CR_1000T_TEST_MODE_1

#define CR_1000T_TEST_MODE_1   0x2000 /* Transmit Waveform test */

Definition at line 1006 of file igbvf_defines.h.

CR_1000T_TEST_MODE_2

#define CR_1000T_TEST_MODE_2   0x4000 /* Master Transmit Jitter test */

Definition at line 1007 of file igbvf_defines.h.

CR_1000T_TEST_MODE_3

#define CR_1000T_TEST_MODE_3   0x6000 /* Slave Transmit Jitter test */

Definition at line 1008 of file igbvf_defines.h.

CR_1000T_TEST_MODE_4

#define CR_1000T_TEST_MODE_4   0x8000 /* Transmitter Distortion test */

Definition at line 1009 of file igbvf_defines.h.

SR_1000T_IDLE_ERROR_CNT

#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */

Definition at line 1012 of file igbvf_defines.h.

SR_1000T_ASYM_PAUSE_DIR

#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */

Definition at line 1013 of file igbvf_defines.h.

SR_1000T_LP_HD_CAPS

#define SR_1000T_LP_HD_CAPS   0x0400 /* LP is 1000T HD capable */

Definition at line 1014 of file igbvf_defines.h.

SR_1000T_LP_FD_CAPS

#define SR_1000T_LP_FD_CAPS   0x0800 /* LP is 1000T FD capable */

Definition at line 1015 of file igbvf_defines.h.

SR_1000T_REMOTE_RX_STATUS

#define SR_1000T_REMOTE_RX_STATUS   0x1000 /* Remote receiver OK */

Definition at line 1016 of file igbvf_defines.h.

SR_1000T_LOCAL_RX_STATUS

#define SR_1000T_LOCAL_RX_STATUS   0x2000 /* Local receiver OK */

Definition at line 1017 of file igbvf_defines.h.

SR_1000T_MS_CONFIG_RES

#define SR_1000T_MS_CONFIG_RES   0x4000 /* 1=Local Tx is Master, 0=Slave */

Definition at line 1018 of file igbvf_defines.h.

SR_1000T_MS_CONFIG_FAULT

#define SR_1000T_MS_CONFIG_FAULT   0x8000 /* Master/Slave config fault */

Definition at line 1019 of file igbvf_defines.h.

SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT

#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT   5

Definition at line 1021 of file igbvf_defines.h.

PHY_CONTROL

#define PHY_CONTROL   0x00 /* Control Register */

Definition at line 1025 of file igbvf_defines.h.

PHY_STATUS

#define PHY_STATUS   0x01 /* Status Register */

Definition at line 1026 of file igbvf_defines.h.

PHY_ID1

#define PHY_ID1   0x02 /* Phy Id Reg (word 1) */

Definition at line 1027 of file igbvf_defines.h.

PHY_ID2

#define PHY_ID2   0x03 /* Phy Id Reg (word 2) */

Definition at line 1028 of file igbvf_defines.h.

PHY_AUTONEG_ADV

#define PHY_AUTONEG_ADV   0x04 /* Autoneg Advertisement */

Definition at line 1029 of file igbvf_defines.h.

PHY_LP_ABILITY

#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */

Definition at line 1030 of file igbvf_defines.h.

PHY_AUTONEG_EXP

#define PHY_AUTONEG_EXP   0x06 /* Autoneg Expansion Reg */

Definition at line 1031 of file igbvf_defines.h.

PHY_NEXT_PAGE_TX

#define PHY_NEXT_PAGE_TX   0x07 /* Next Page Tx */

Definition at line 1032 of file igbvf_defines.h.

PHY_LP_NEXT_PAGE

#define PHY_LP_NEXT_PAGE   0x08 /* Link Partner Next Page */

Definition at line 1033 of file igbvf_defines.h.

PHY_1000T_CTRL

#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */

Definition at line 1034 of file igbvf_defines.h.

PHY_1000T_STATUS

#define PHY_1000T_STATUS   0x0A /* 1000Base-T Status Reg */

Definition at line 1035 of file igbvf_defines.h.

PHY_EXT_STATUS

#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */

Definition at line 1036 of file igbvf_defines.h.

PHY_CONTROL_LB

#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */

Definition at line 1038 of file igbvf_defines.h.

E1000_EECD_SK

#define E1000_EECD_SK   0x00000001 /* NVM Clock */

Definition at line 1041 of file igbvf_defines.h.

E1000_EECD_CS

#define E1000_EECD_CS   0x00000002 /* NVM Chip Select */

Definition at line 1042 of file igbvf_defines.h.

E1000_EECD_DI

#define E1000_EECD_DI   0x00000004 /* NVM Data In */

Definition at line 1043 of file igbvf_defines.h.

E1000_EECD_DO

#define E1000_EECD_DO   0x00000008 /* NVM Data Out */

Definition at line 1044 of file igbvf_defines.h.

E1000_EECD_FWE_MASK

#define E1000_EECD_FWE_MASK   0x00000030

Definition at line 1045 of file igbvf_defines.h.

E1000_EECD_FWE_DIS

#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */

Definition at line 1046 of file igbvf_defines.h.

E1000_EECD_FWE_EN

#define E1000_EECD_FWE_EN   0x00000020 /* Enable FLASH writes */

Definition at line 1047 of file igbvf_defines.h.

E1000_EECD_FWE_SHIFT

#define E1000_EECD_FWE_SHIFT   4

Definition at line 1048 of file igbvf_defines.h.

E1000_EECD_REQ

#define E1000_EECD_REQ   0x00000040 /* NVM Access Request */

Definition at line 1049 of file igbvf_defines.h.

E1000_EECD_GNT

#define E1000_EECD_GNT   0x00000080 /* NVM Access Grant */

Definition at line 1050 of file igbvf_defines.h.

E1000_EECD_PRES

#define E1000_EECD_PRES   0x00000100 /* NVM Present */

Definition at line 1051 of file igbvf_defines.h.

E1000_EECD_SIZE

#define E1000_EECD_SIZE   0x00000200 /* NVM Size (0=64 word 1=256 word) */

Definition at line 1052 of file igbvf_defines.h.

E1000_EECD_ADDR_BITS

#define E1000_EECD_ADDR_BITS   0x00000400

Definition at line 1054 of file igbvf_defines.h.

E1000_EECD_TYPE

#define E1000_EECD_TYPE   0x00002000 /* NVM Type (1-SPI, 0-Microwire) */

Definition at line 1055 of file igbvf_defines.h.

E1000_NVM_GRANT_ATTEMPTS

#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */

Definition at line 1056 of file igbvf_defines.h.

E1000_EECD_AUTO_RD

#define E1000_EECD_AUTO_RD   0x00000200 /* NVM Auto Read done */

Definition at line 1057 of file igbvf_defines.h.

E1000_EECD_SIZE_EX_MASK

#define E1000_EECD_SIZE_EX_MASK   0x00007800 /* NVM Size */

Definition at line 1058 of file igbvf_defines.h.

E1000_EECD_SIZE_EX_SHIFT

#define E1000_EECD_SIZE_EX_SHIFT   11

Definition at line 1059 of file igbvf_defines.h.

E1000_EECD_NVADDS

#define E1000_EECD_NVADDS   0x00018000 /* NVM Address Size */

Definition at line 1060 of file igbvf_defines.h.

E1000_EECD_SELSHAD

#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */

Definition at line 1061 of file igbvf_defines.h.

E1000_EECD_INITSRAM

#define E1000_EECD_INITSRAM   0x00040000 /* Initialize Shadow RAM */

Definition at line 1062 of file igbvf_defines.h.

E1000_EECD_FLUPD

#define E1000_EECD_FLUPD   0x00080000 /* Update FLASH */

Definition at line 1063 of file igbvf_defines.h.

E1000_EECD_AUPDEN

#define E1000_EECD_AUPDEN   0x00100000 /* Enable Autonomous FLASH update */

Definition at line 1064 of file igbvf_defines.h.

E1000_EECD_SHADV

#define E1000_EECD_SHADV   0x00200000 /* Shadow RAM Data Valid */

Definition at line 1065 of file igbvf_defines.h.

E1000_EECD_SEC1VAL

#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */

Definition at line 1066 of file igbvf_defines.h.

E1000_EECD_SECVAL_SHIFT

#define E1000_EECD_SECVAL_SHIFT   22

Definition at line 1067 of file igbvf_defines.h.

E1000_EECD_SEC1VAL_VALID_MASK

#define E1000_EECD_SEC1VAL_VALID_MASK   (E1000_EECD_AUTO_RD | E1000_EECD_PRES)

Definition at line 1068 of file igbvf_defines.h.

E1000_NVM_SWDPIN0

#define E1000_NVM_SWDPIN0   0x0001 /* SWDPIN 0 NVM Value */

Definition at line 1070 of file igbvf_defines.h.

E1000_NVM_LED_LOGIC

#define E1000_NVM_LED_LOGIC   0x0020 /* Led Logic Word */

Definition at line 1071 of file igbvf_defines.h.

E1000_NVM_RW_REG_DATA

#define E1000_NVM_RW_REG_DATA   16 /* Offset to data in NVM read/write regs */

Definition at line 1072 of file igbvf_defines.h.

E1000_NVM_RW_REG_DONE

#define E1000_NVM_RW_REG_DONE   2 /* Offset to READ/WRITE done bit */

Definition at line 1073 of file igbvf_defines.h.

E1000_NVM_RW_REG_START

#define E1000_NVM_RW_REG_START   1 /* Start operation */

Definition at line 1074 of file igbvf_defines.h.

E1000_NVM_RW_ADDR_SHIFT

#define E1000_NVM_RW_ADDR_SHIFT   2 /* Shift to the address bits */

Definition at line 1075 of file igbvf_defines.h.

E1000_NVM_POLL_WRITE

#define E1000_NVM_POLL_WRITE   1 /* Flag for polling for write complete */

Definition at line 1076 of file igbvf_defines.h.

E1000_NVM_POLL_READ

#define E1000_NVM_POLL_READ   0 /* Flag for polling for read complete */

Definition at line 1077 of file igbvf_defines.h.

E1000_FLASH_UPDATES

#define E1000_FLASH_UPDATES   2000

Definition at line 1078 of file igbvf_defines.h.

NVM_COMPAT

#define NVM_COMPAT   0x0003

Definition at line 1081 of file igbvf_defines.h.

NVM_ID_LED_SETTINGS

#define NVM_ID_LED_SETTINGS   0x0004

Definition at line 1082 of file igbvf_defines.h.

NVM_VERSION

#define NVM_VERSION   0x0005

Definition at line 1083 of file igbvf_defines.h.

NVM_SERDES_AMPLITUDE

#define NVM_SERDES_AMPLITUDE   0x0006 /* SERDES output amplitude */

Definition at line 1084 of file igbvf_defines.h.

NVM_PHY_CLASS_WORD

#define NVM_PHY_CLASS_WORD   0x0007

Definition at line 1085 of file igbvf_defines.h.

NVM_INIT_CONTROL1_REG

#define NVM_INIT_CONTROL1_REG   0x000A

Definition at line 1086 of file igbvf_defines.h.

NVM_INIT_CONTROL2_REG

#define NVM_INIT_CONTROL2_REG   0x000F

Definition at line 1087 of file igbvf_defines.h.

NVM_SWDEF_PINS_CTRL_PORT_1

#define NVM_SWDEF_PINS_CTRL_PORT_1   0x0010

Definition at line 1088 of file igbvf_defines.h.

NVM_INIT_CONTROL3_PORT_B

#define NVM_INIT_CONTROL3_PORT_B   0x0014

Definition at line 1089 of file igbvf_defines.h.

NVM_INIT_3GIO_3

#define NVM_INIT_3GIO_3   0x001A

Definition at line 1090 of file igbvf_defines.h.

NVM_SWDEF_PINS_CTRL_PORT_0

#define NVM_SWDEF_PINS_CTRL_PORT_0   0x0020

Definition at line 1091 of file igbvf_defines.h.

NVM_INIT_CONTROL3_PORT_A

#define NVM_INIT_CONTROL3_PORT_A   0x0024

Definition at line 1092 of file igbvf_defines.h.

NVM_CFG

#define NVM_CFG   0x0012

Definition at line 1093 of file igbvf_defines.h.

NVM_FLASH_VERSION

#define NVM_FLASH_VERSION   0x0032

Definition at line 1094 of file igbvf_defines.h.

NVM_ALT_MAC_ADDR_PTR

#define NVM_ALT_MAC_ADDR_PTR   0x0037

Definition at line 1095 of file igbvf_defines.h.

NVM_CHECKSUM_REG

#define NVM_CHECKSUM_REG   0x003F

Definition at line 1096 of file igbvf_defines.h.

E1000_NVM_CFG_DONE_PORT_0

#define E1000_NVM_CFG_DONE_PORT_0   0x040000 /* MNG config cycle done */

Definition at line 1098 of file igbvf_defines.h.

E1000_NVM_CFG_DONE_PORT_1

#define E1000_NVM_CFG_DONE_PORT_1   0x080000 /* ...for second port */

Definition at line 1099 of file igbvf_defines.h.

NVM_WORD0F_PAUSE_MASK

#define NVM_WORD0F_PAUSE_MASK   0x3000

Definition at line 1102 of file igbvf_defines.h.

NVM_WORD0F_PAUSE

#define NVM_WORD0F_PAUSE   0x1000

Definition at line 1103 of file igbvf_defines.h.

NVM_WORD0F_ASM_DIR

#define NVM_WORD0F_ASM_DIR   0x2000

Definition at line 1104 of file igbvf_defines.h.

NVM_WORD0F_ANE

#define NVM_WORD0F_ANE   0x0800

Definition at line 1105 of file igbvf_defines.h.

NVM_WORD0F_SWPDIO_EXT_MASK

#define NVM_WORD0F_SWPDIO_EXT_MASK   0x00F0

Definition at line 1106 of file igbvf_defines.h.

NVM_WORD0F_LPLU

#define NVM_WORD0F_LPLU   0x0001

Definition at line 1107 of file igbvf_defines.h.

NVM_WORD1A_ASPM_MASK

#define NVM_WORD1A_ASPM_MASK   0x000C

Definition at line 1110 of file igbvf_defines.h.

NVM_SUM

#define NVM_SUM   0xBABA

Definition at line 1113 of file igbvf_defines.h.

NVM_MAC_ADDR_OFFSET

#define NVM_MAC_ADDR_OFFSET   0

Definition at line 1115 of file igbvf_defines.h.

NVM_PBA_OFFSET_0

#define NVM_PBA_OFFSET_0   8

Definition at line 1116 of file igbvf_defines.h.

NVM_PBA_OFFSET_1

#define NVM_PBA_OFFSET_1   9

Definition at line 1117 of file igbvf_defines.h.

NVM_RESERVED_WORD

#define NVM_RESERVED_WORD   0xFFFF

Definition at line 1118 of file igbvf_defines.h.

NVM_PHY_CLASS_A

#define NVM_PHY_CLASS_A   0x8000

Definition at line 1119 of file igbvf_defines.h.

NVM_SERDES_AMPLITUDE_MASK

#define NVM_SERDES_AMPLITUDE_MASK   0x000F

Definition at line 1120 of file igbvf_defines.h.

NVM_SIZE_MASK

#define NVM_SIZE_MASK   0x1C00

Definition at line 1121 of file igbvf_defines.h.

NVM_SIZE_SHIFT

#define NVM_SIZE_SHIFT   10

Definition at line 1122 of file igbvf_defines.h.

NVM_WORD_SIZE_BASE_SHIFT

#define NVM_WORD_SIZE_BASE_SHIFT   6

Definition at line 1123 of file igbvf_defines.h.

NVM_SWDPIO_EXT_SHIFT

#define NVM_SWDPIO_EXT_SHIFT   4

Definition at line 1124 of file igbvf_defines.h.

NVM_MAX_RETRY_SPI

#define NVM_MAX_RETRY_SPI   5000 /* Max wait of 5ms, for RDY signal */

Definition at line 1127 of file igbvf_defines.h.

NVM_READ_OPCODE_SPI

#define NVM_READ_OPCODE_SPI   0x03 /* NVM read opcode */

Definition at line 1128 of file igbvf_defines.h.

NVM_WRITE_OPCODE_SPI

#define NVM_WRITE_OPCODE_SPI   0x02 /* NVM write opcode */

Definition at line 1129 of file igbvf_defines.h.

NVM_A8_OPCODE_SPI

#define NVM_A8_OPCODE_SPI   0x08 /* opcode bit-3 = address bit-8 */

Definition at line 1130 of file igbvf_defines.h.

NVM_WREN_OPCODE_SPI

#define NVM_WREN_OPCODE_SPI   0x06 /* NVM set Write Enable latch */

Definition at line 1131 of file igbvf_defines.h.

NVM_WRDI_OPCODE_SPI

#define NVM_WRDI_OPCODE_SPI   0x04 /* NVM reset Write Enable latch */

Definition at line 1132 of file igbvf_defines.h.

NVM_RDSR_OPCODE_SPI

#define NVM_RDSR_OPCODE_SPI   0x05 /* NVM read Status register */

Definition at line 1133 of file igbvf_defines.h.

NVM_WRSR_OPCODE_SPI

#define NVM_WRSR_OPCODE_SPI   0x01 /* NVM write Status register */

Definition at line 1134 of file igbvf_defines.h.

NVM_STATUS_RDY_SPI

#define NVM_STATUS_RDY_SPI   0x01

Definition at line 1137 of file igbvf_defines.h.

NVM_STATUS_WEN_SPI

#define NVM_STATUS_WEN_SPI   0x02

Definition at line 1138 of file igbvf_defines.h.

NVM_STATUS_BP0_SPI

#define NVM_STATUS_BP0_SPI   0x04

Definition at line 1139 of file igbvf_defines.h.

NVM_STATUS_BP1_SPI

#define NVM_STATUS_BP1_SPI   0x08

Definition at line 1140 of file igbvf_defines.h.

NVM_STATUS_WPEN_SPI

#define NVM_STATUS_WPEN_SPI   0x80

Definition at line 1141 of file igbvf_defines.h.

ID_LED_RESERVED_0000

#define ID_LED_RESERVED_0000   0x0000

Definition at line 1144 of file igbvf_defines.h.

ID_LED_RESERVED_FFFF

#define ID_LED_RESERVED_FFFF   0xFFFF

Definition at line 1145 of file igbvf_defines.h.

ID_LED_DEFAULT

#define ID_LED_DEFAULT

Value:

((ID_LED_OFF1_ON2  << 12) | \
                              (ID_LED_OFF1_OFF2 <<  8) | \
                              (ID_LED_DEF1_DEF2 <<  4) | \
                              (ID_LED_DEF1_DEF2))

Definition at line 1146 of file igbvf_defines.h.

ID_LED_DEF1_DEF2

#define ID_LED_DEF1_DEF2   0x1

Definition at line 1150 of file igbvf_defines.h.

ID_LED_DEF1_ON2

#define ID_LED_DEF1_ON2   0x2

Definition at line 1151 of file igbvf_defines.h.

ID_LED_DEF1_OFF2

#define ID_LED_DEF1_OFF2   0x3

Definition at line 1152 of file igbvf_defines.h.

ID_LED_ON1_DEF2

#define ID_LED_ON1_DEF2   0x4

Definition at line 1153 of file igbvf_defines.h.

ID_LED_ON1_ON2

#define ID_LED_ON1_ON2   0x5

Definition at line 1154 of file igbvf_defines.h.

ID_LED_ON1_OFF2

#define ID_LED_ON1_OFF2   0x6

Definition at line 1155 of file igbvf_defines.h.

ID_LED_OFF1_DEF2

#define ID_LED_OFF1_DEF2   0x7

Definition at line 1156 of file igbvf_defines.h.

ID_LED_OFF1_ON2

#define ID_LED_OFF1_ON2   0x8

Definition at line 1157 of file igbvf_defines.h.

ID_LED_OFF1_OFF2

#define ID_LED_OFF1_OFF2   0x9

Definition at line 1158 of file igbvf_defines.h.

IGP_ACTIVITY_LED_MASK

#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF

Definition at line 1160 of file igbvf_defines.h.

IGP_ACTIVITY_LED_ENABLE

#define IGP_ACTIVITY_LED_ENABLE   0x0300

Definition at line 1161 of file igbvf_defines.h.

IGP_LED3_MODE

#define IGP_LED3_MODE   0x07000000

Definition at line 1162 of file igbvf_defines.h.

PCI_HEADER_TYPE_REGISTER

#define PCI_HEADER_TYPE_REGISTER   0x0E

Definition at line 1165 of file igbvf_defines.h.

PCIE_LINK_STATUS

#define PCIE_LINK_STATUS   0x12

Definition at line 1166 of file igbvf_defines.h.

PCIE_DEVICE_CONTROL2

#define PCIE_DEVICE_CONTROL2   0x28

Definition at line 1167 of file igbvf_defines.h.

PCI_HEADER_TYPE_MULTIFUNC

#define PCI_HEADER_TYPE_MULTIFUNC   0x80

Definition at line 1169 of file igbvf_defines.h.

PCIE_LINK_WIDTH_MASK

#define PCIE_LINK_WIDTH_MASK   0x3F0

Definition at line 1170 of file igbvf_defines.h.

PCIE_LINK_WIDTH_SHIFT

#define PCIE_LINK_WIDTH_SHIFT   4

Definition at line 1171 of file igbvf_defines.h.

PCIE_DEVICE_CONTROL2_16ms

#define PCIE_DEVICE_CONTROL2_16ms   0x0005

Definition at line 1172 of file igbvf_defines.h.

ETH_ADDR_LEN

#define ETH_ADDR_LEN   6

Definition at line 1175 of file igbvf_defines.h.

PHY_REVISION_MASK

#define PHY_REVISION_MASK   0xFFFFFFF0

Definition at line 1178 of file igbvf_defines.h.

MAX_PHY_REG_ADDRESS

#define MAX_PHY_REG_ADDRESS   0x1F /* 5 bit address bus (0-0x1F) */

Definition at line 1179 of file igbvf_defines.h.

MAX_PHY_MULTI_PAGE_REG

#define MAX_PHY_MULTI_PAGE_REG   0xF

Definition at line 1180 of file igbvf_defines.h.

M88E1000_E_PHY_ID

#define M88E1000_E_PHY_ID   0x01410C50

Definition at line 1187 of file igbvf_defines.h.

M88E1000_I_PHY_ID

#define M88E1000_I_PHY_ID   0x01410C30

Definition at line 1188 of file igbvf_defines.h.

M88E1011_I_PHY_ID

#define M88E1011_I_PHY_ID   0x01410C20

Definition at line 1189 of file igbvf_defines.h.

IGP01E1000_I_PHY_ID

#define IGP01E1000_I_PHY_ID   0x02A80380

Definition at line 1190 of file igbvf_defines.h.

M88E1011_I_REV_4

#define M88E1011_I_REV_4   0x04

Definition at line 1191 of file igbvf_defines.h.

M88E1111_I_PHY_ID

#define M88E1111_I_PHY_ID   0x01410CC0

Definition at line 1192 of file igbvf_defines.h.

GG82563_E_PHY_ID

#define GG82563_E_PHY_ID   0x01410CA0

Definition at line 1193 of file igbvf_defines.h.

IGP03E1000_E_PHY_ID

#define IGP03E1000_E_PHY_ID   0x02A80390

Definition at line 1194 of file igbvf_defines.h.

IFE_E_PHY_ID

#define IFE_E_PHY_ID   0x02A80330

Definition at line 1195 of file igbvf_defines.h.

IFE_PLUS_E_PHY_ID

#define IFE_PLUS_E_PHY_ID   0x02A80320

Definition at line 1196 of file igbvf_defines.h.

IFE_C_E_PHY_ID

#define IFE_C_E_PHY_ID   0x02A80310

Definition at line 1197 of file igbvf_defines.h.

M88_VENDOR

#define M88_VENDOR   0x0141

Definition at line 1198 of file igbvf_defines.h.

M88E1000_PHY_SPEC_CTRL

#define M88E1000_PHY_SPEC_CTRL   0x10 /* PHY Specific Control Register */

Definition at line 1201 of file igbvf_defines.h.

M88E1000_PHY_SPEC_STATUS

#define M88E1000_PHY_SPEC_STATUS   0x11 /* PHY Specific Status Register */

Definition at line 1202 of file igbvf_defines.h.

M88E1000_INT_ENABLE

#define M88E1000_INT_ENABLE   0x12 /* Interrupt Enable Register */

Definition at line 1203 of file igbvf_defines.h.

M88E1000_INT_STATUS

#define M88E1000_INT_STATUS   0x13 /* Interrupt Status Register */

Definition at line 1204 of file igbvf_defines.h.

M88E1000_EXT_PHY_SPEC_CTRL

#define M88E1000_EXT_PHY_SPEC_CTRL   0x14 /* Extended PHY Specific Control */

Definition at line 1205 of file igbvf_defines.h.

M88E1000_RX_ERR_CNTR

#define M88E1000_RX_ERR_CNTR   0x15 /* Receive Error Counter */

Definition at line 1206 of file igbvf_defines.h.

M88E1000_PHY_EXT_CTRL

#define M88E1000_PHY_EXT_CTRL   0x1A /* PHY extend control register */

Definition at line 1208 of file igbvf_defines.h.

M88E1000_PHY_PAGE_SELECT

#define M88E1000_PHY_PAGE_SELECT   0x1D /* Reg 29 for page number setting */

Definition at line 1209 of file igbvf_defines.h.

M88E1000_PHY_GEN_CONTROL

#define M88E1000_PHY_GEN_CONTROL   0x1E /* Its meaning depends on reg 29 */

Definition at line 1210 of file igbvf_defines.h.

M88E1000_PHY_VCO_REG_BIT8

#define M88E1000_PHY_VCO_REG_BIT8   0x100 /* Bits 8 & 11 are adjusted for */

Definition at line 1211 of file igbvf_defines.h.

M88E1000_PHY_VCO_REG_BIT11

#define M88E1000_PHY_VCO_REG_BIT11   0x800 /* improved BER performance */

Definition at line 1212 of file igbvf_defines.h.

M88E1000_PSCR_JABBER_DISABLE

#define M88E1000_PSCR_JABBER_DISABLE   0x0001 /* 1=Jabber Function disabled */

Definition at line 1215 of file igbvf_defines.h.

M88E1000_PSCR_POLARITY_REVERSAL

#define M88E1000_PSCR_POLARITY_REVERSAL   0x0002 /* 1=Polarity Reverse enabled */

Definition at line 1216 of file igbvf_defines.h.

M88E1000_PSCR_SQE_TEST

#define M88E1000_PSCR_SQE_TEST   0x0004 /* 1=SQE Test enabled */

Definition at line 1217 of file igbvf_defines.h.

M88E1000_PSCR_CLK125_DISABLE

#define M88E1000_PSCR_CLK125_DISABLE   0x0010

Definition at line 1219 of file igbvf_defines.h.

M88E1000_PSCR_MDI_MANUAL_MODE

#define M88E1000_PSCR_MDI_MANUAL_MODE   0x0000 /* MDI Crossover Mode bits 6:5 */

Definition at line 1220 of file igbvf_defines.h.

M88E1000_PSCR_MDIX_MANUAL_MODE

#define M88E1000_PSCR_MDIX_MANUAL_MODE   0x0020 /* Manual MDIX configuration */