iPXE
Data Structures | Macros | Functions | Variables
epic100.c File Reference
#include "etherboot.h"
#include <ipxe/pci.h>
#include <ipxe/ethernet.h>
#include "nic.h"
#include "epic100.h"

Go to the source code of this file.

Data Structures

struct  epic_rx_desc
 
struct  epic_tx_desc
 

Macros

#define LINUX_OUT_MACROS
 
#define virt_to_le32desc(addr)   cpu_to_le32(virt_to_bus(addr))
 
#define le32desc_to_virt(addr)   bus_to_virt(le32_to_cpu(addr))
 
#define TX_RING_SIZE   2 /* use at least 2 buffers for TX */
 
#define RX_RING_SIZE   2
 
#define PKT_BUF_SZ   1536 /* Size of each temporary Tx/Rx buffer.*/
 
#define EPIC_DEBUG   0 /* debug level */
 
#define TD_STDFLAGS   TD_LASTDESC
 
#define delay(nanosec)
 
#define rx_ring   epic100_bufs.rx_ring
 
#define tx_ring   epic100_bufs.tx_ring
 
#define rx_packet   epic100_bufs.rx_packet
 
#define tx_packet   epic100_bufs.tx_packet
 
#define MII_READOP   1
 
#define MII_WRITEOP   2
 

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
static void epic100_open (void)
 
static void epic100_init_ring (void)
 
static void epic100_disable (struct nic *nic)
 
static int epic100_poll (struct nic *nic, int retrieve)
 
static void epic100_transmit (struct nic *nic, const char *destaddr, unsigned int type, unsigned int len, const char *data)
 
static int mii_read (int phy_id, int location)
 
static void epic100_irq (struct nic *nic, irq_action_t action)
 
static int epic100_probe (struct nic *nic, struct pci_device *pci)
 
static void set_rx_mode (void)
 
static void epic100_disable (struct nic *nic __unused)
 
static void epic100_irq (struct nic *nic __unused, irq_action_t action __unused)
 
 PCI_DRIVER (epic100_driver, epic100_nics, PCI_NO_CLASS)
 
 DRIVER ("EPIC100", nic_driver, pci_driver, epic100_driver, epic100_probe, epic100_disable)
 

Variables

static struct nic_operations epic100_operations
 
static int ioaddr
 
static int command
 
static int intstat
 
static int intmask
 
static int genctl
 
static int eectl
 
static int test
 
static int mmctl
 
static int mmdata
 
static int lan0
 
static int mc0
 
static int rxcon
 
static int txcon
 
static int prcdar
 
static int ptcdar
 
static int eththr
 
static unsigned int cur_rx
 
static unsigned int cur_tx
 
static signed char phys [4]
 
struct {
   struct epic_rx_desc   rx_ring [RX_RING_SIZE]
 
   struct epic_tx_desc   tx_ring [TX_RING_SIZE]
 
   unsigned char   rx_packet [PKT_BUF_SZ *RX_RING_SIZE]
 
   unsigned char   tx_packet [PKT_BUF_SZ *TX_RING_SIZE]
 
__shared
 
static struct pci_device_id epic100_nics []
 

Macro Definition Documentation

◆ LINUX_OUT_MACROS

#define LINUX_OUT_MACROS

Definition at line 7 of file epic100.c.

◆ virt_to_le32desc

#define virt_to_le32desc (   addr)    cpu_to_le32(virt_to_bus(addr))

Definition at line 16 of file epic100.c.

◆ le32desc_to_virt

#define le32desc_to_virt (   addr)    bus_to_virt(le32_to_cpu(addr))

Definition at line 17 of file epic100.c.

◆ TX_RING_SIZE

#define TX_RING_SIZE   2 /* use at least 2 buffers for TX */

Definition at line 19 of file epic100.c.

◆ RX_RING_SIZE

#define RX_RING_SIZE   2

Definition at line 20 of file epic100.c.

◆ PKT_BUF_SZ

#define PKT_BUF_SZ   1536 /* Size of each temporary Tx/Rx buffer.*/

Definition at line 22 of file epic100.c.

◆ EPIC_DEBUG

#define EPIC_DEBUG   0 /* debug level */

Definition at line 30 of file epic100.c.

◆ TD_STDFLAGS

#define TD_STDFLAGS   TD_LASTDESC

Definition at line 40 of file epic100.c.

◆ delay

#define delay (   nanosec)
Value:
do { int _i = 3; while (--_i > 0) \
{ __SLOW_DOWN_IO; }} while (0)

Definition at line 49 of file epic100.c.

◆ rx_ring

#define rx_ring   epic100_bufs.rx_ring

Definition at line 97 of file epic100.c.

◆ tx_ring

#define tx_ring   epic100_bufs.tx_ring

Definition at line 98 of file epic100.c.

◆ rx_packet

#define rx_packet   epic100_bufs.rx_packet

Definition at line 99 of file epic100.c.

◆ tx_packet

#define tx_packet   epic100_bufs.tx_packet

Definition at line 100 of file epic100.c.

◆ MII_READOP

#define MII_READOP   1

Definition at line 495 of file epic100.c.

◆ MII_WRITEOP

#define MII_WRITEOP   2

Definition at line 496 of file epic100.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ epic100_open()

static void epic100_open ( void  )
static

Definition at line 230 of file epic100.c.

231 {
232  int mii_reg5;
233  unsigned long tmp;
234 
236 
237  /* Pull the chip out of low-power mode, and set for PCI read multiple. */
239 
241 
243 
244  mii_reg5 = mii_read(phys[0], 5);
245  if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
246  printf(" full-duplex mode");
247  tmp |= TC_LM_FULL_DPX;
248  } else
249  tmp |= TC_LM_NORMAL;
250 
251  outl(tmp, txcon);
252 
253  /* Give address of RX and TX ring to the chip */
256 
257  /* Start the chip's Rx process: receive unicast and broadcast */
258  set_rx_mode();
260 
261  putchar('\n');
262 }
#define TX_SLOT_TIME
Definition: epic100.h:145
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
#define GC_RX_FIFO_THR_64
Definition: epic100.h:106
A command-line command.
Definition: command.h:9
void putchar(int character)
Write a single character to each console device.
Definition: console.c:27
#define GC_ONE_COPY
Definition: epic100.h:93
static signed char phys[4]
Definition: epic100.c:88
#define GC_MRC_READ_MULT
Definition: epic100.h:112
static void epic100_init_ring(void)
Definition: epic100.c:266
static int txcon
Definition: epic100.c:79
#define TC_LM_NORMAL
Definition: epic100.h:140
#define outl(data, io_addr)
Definition: io.h:329
uint8_t * tmp
Definition: entropy.h:156
#define TC_LM_FULL_DPX
Definition: epic100.h:143
static void set_rx_mode(void)
Definition: epic100.c:218
static int genctl
Definition: epic100.c:71
#define rx_ring
Definition: epic100.c:97
#define TC_EARLY_TX_ENABLE
Definition: epic100.h:137
#define CR_START_RX
Definition: epic100.h:47
static int eththr
Definition: epic100.c:82
#define tx_ring
Definition: epic100.c:98
static int ptcdar
Definition: epic100.c:81
#define virt_to_le32desc(addr)
Definition: epic100.c:16
static int prcdar
Definition: epic100.c:80
static int mii_read(int phy_id, int location)
Definition: epic100.c:499
#define CR_QUEUE_RX
Definition: epic100.h:49
#define TX_FIFO_THRESH
Definition: epic100.h:148

References CR_QUEUE_RX, CR_START_RX, epic100_init_ring(), eththr, GC_MRC_READ_MULT, GC_ONE_COPY, GC_RX_FIFO_THR_64, genctl, mii_read(), outl, phys, prcdar, printf(), ptcdar, putchar(), rx_ring, set_rx_mode(), TC_EARLY_TX_ENABLE, TC_LM_FULL_DPX, TC_LM_NORMAL, tmp, TX_FIFO_THRESH, tx_ring, TX_SLOT_TIME, txcon, and virt_to_le32desc.

Referenced by epic100_probe(), and epic100_transmit().

◆ epic100_init_ring()

static void epic100_init_ring ( void  )
static

Definition at line 266 of file epic100.c.

267 {
268  int i;
269 
270  cur_rx = cur_tx = 0;
271 
272  for (i = 0; i < RX_RING_SIZE; i++) {
273  rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
274  rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
275  rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
276  rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
277  }
278  /* Mark the last entry as wrapping the ring. */
279  rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
280 
281  /*
282  *The Tx buffer descriptor is filled in as needed,
283  * but we do need to clear the ownership bit.
284  */
285 
286  for (i = 0; i < TX_RING_SIZE; i++) {
287  tx_ring[i].status = 0x0000; /* Owned by CPU */
288  tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
289  tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
290  tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
291  }
292  tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
293 }
#define RRING_OWN
Definition: epic100.h:161
static unsigned int cur_tx
Definition: epic100.c:84
#define TX_RING_SIZE
Definition: epic100.c:19
#define RX_RING_SIZE
Definition: epic100.c:20
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define rx_packet
Definition: epic100.c:99
#define rx_ring
Definition: epic100.c:97
#define tx_ring
Definition: epic100.c:98
#define tx_packet
Definition: epic100.c:100
static unsigned int cur_rx
Definition: epic100.c:84
#define virt_to_le32desc(addr)
Definition: epic100.c:16
#define PKT_BUF_SZ
Definition: epic100.c:22
#define TD_STDFLAGS
Definition: epic100.c:40

References cpu_to_le32, cur_rx, cur_tx, PKT_BUF_SZ, RRING_OWN, rx_packet, rx_ring, RX_RING_SIZE, TD_STDFLAGS, tx_packet, tx_ring, TX_RING_SIZE, virt_to_bus(), and virt_to_le32desc.

Referenced by epic100_open().

◆ epic100_disable() [1/2]

static void epic100_disable ( struct nic nic)
static

◆ epic100_poll()

static int epic100_poll ( struct nic nic,
int  retrieve 
)
static

Definition at line 375 of file epic100.c.

376 {
377  int entry;
378  int retcode;
379  unsigned long status;
381 
383  return (0);
384 
385  if ( ! retrieve ) return 1;
386 
388  /* We own the next entry, it's a new packet. Send it up. */
389 
390 #if (EPIC_DEBUG > 4)
391  printf("epic_poll: entry %d status %hX\n", entry, status);
392 #endif
393 
394  cur_rx++;
395  if (status & 0x2000) {
396  printf("epic_poll: Giant packet\n");
397  retcode = 0;
398  } else if (status & 0x0006) {
399  /* Rx Frame errors are counted in hardware. */
400  printf("epic_poll: Frame received with errors\n");
401  retcode = 0;
402  } else {
403  /* Omit the four octet CRC from the length. */
404  nic->packetlen = (status >> 16) - 4;
406  retcode = 1;
407  }
408 
409  /* Clear all error sources. */
411 
412  /* Give the descriptor back to the chip */
413  rx_ring[entry].status = RRING_OWN;
414 
415  /* Restart Receiver */
417 
418  return retcode;
419 }
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
#define RRING_OWN
Definition: epic100.h:161
#define le32_to_cpu(value)
Definition: byteswap.h:113
A command-line command.
Definition: command.h:9
#define RX_RING_SIZE
Definition: epic100.c:20
uint8_t status
Status.
Definition: ena.h:16
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define rx_packet
Definition: epic100.c:99
unsigned int packetlen
Definition: nic.h:54
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
#define outl(data, io_addr)
Definition: io.h:329
Definition: nic.h:49
#define rx_ring
Definition: epic100.c:97
#define CR_START_RX
Definition: epic100.h:47
unsigned char * packet
Definition: nic.h:53
static unsigned int cur_rx
Definition: epic100.c:84
#define PKT_BUF_SZ
Definition: epic100.c:22
static int intstat
Definition: epic100.c:69
#define INTR_CLEARERRS
Definition: epic100.h:84
#define CR_QUEUE_RX
Definition: epic100.h:49

References cpu_to_le32, CR_QUEUE_RX, CR_START_RX, cur_rx, entry, INTR_CLEARERRS, intstat, le32_to_cpu, memcpy(), outl, nic::packet, nic::packetlen, PKT_BUF_SZ, printf(), RRING_OWN, rx_packet, rx_ring, RX_RING_SIZE, and status.

◆ epic100_transmit()

static void epic100_transmit ( struct nic nic,
const char *  destaddr,
unsigned int  type,
unsigned int  len,
const char *  data 
)
static

Definition at line 305 of file epic100.c.

307 {
308  unsigned short nstype;
309  unsigned char *txp;
310  int entry;
311  unsigned long ct;
312 
313  /* Calculate the next Tx descriptor entry. */
315 
316  if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
317  printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
318  tx_ring[entry].status);
319 
320  epic100_open();
321  return;
322  }
323 
324  txp = tx_packet + (entry * PKT_BUF_SZ);
325 
326  memcpy(txp, destaddr, ETH_ALEN);
328  nstype = htons(type);
329  memcpy(txp + 12, (char*)&nstype, 2);
330  memcpy(txp + ETH_HLEN, data, len);
331 
332  len += ETH_HLEN;
333  len &= 0x0FFF;
334  while(len < ETH_ZLEN)
335  txp[len++] = '\0';
336  /*
337  * Caution: the write order is important here,
338  * set the base address with the "ownership"
339  * bits last.
340  */
341 
342  tx_ring[entry].buflength |= cpu_to_le32(len);
343  tx_ring[entry].status = cpu_to_le32(len << 16) |
344  cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
345 
346  cur_tx++;
347 
348  /* Trigger an immediate transmit demand. */
350 
351  ct = currticks();
352  /* timeout 10 ms for transmit */
353  while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) &&
354  ct + 10*1000 < currticks())
355  /* Wait */;
356 
357  if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
358  printf("Oops, transmitter timeout, status=%4.4lX\n",
359  tx_ring[entry].status);
360 }
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
#define le32_to_cpu(value)
Definition: byteswap.h:113
A command-line command.
Definition: command.h:9
uint8_t type
Type.
Definition: ena.h:16
static unsigned int cur_tx
Definition: epic100.c:84
#define TX_RING_SIZE
Definition: epic100.c:19
uint8_t status
Status.
Definition: ena.h:16
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define ETH_HLEN
Definition: if_ether.h:9
#define TRING_OWN
Definition: epic100.h:177
#define cpu_to_le32(value)
Definition: byteswap.h:107
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
#define outl(data, io_addr)
Definition: io.h:329
#define ETH_ALEN
Definition: if_ether.h:8
#define ETH_ZLEN
Definition: if_ether.h:10
Definition: nic.h:49
unsigned char * node_addr
Definition: nic.h:52
#define tx_ring
Definition: epic100.c:98
#define tx_packet
Definition: epic100.c:100
uint32_t len
Length.
Definition: ena.h:14
#define PKT_BUF_SZ
Definition: epic100.c:22
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
#define CR_QUEUE_TX
Definition: epic100.h:48
#define htons(value)
Definition: byteswap.h:135
static void epic100_open(void)
Definition: epic100.c:230

References cpu_to_le32, CR_QUEUE_TX, cur_tx, currticks(), data, entry, epic100_open(), ETH_ALEN, ETH_HLEN, ETH_ZLEN, htons, le32_to_cpu, len, memcpy(), nic::node_addr, outl, PKT_BUF_SZ, printf(), status, TRING_OWN, tx_packet, tx_ring, TX_RING_SIZE, and type.

◆ mii_read()

static int mii_read ( int  phy_id,
int  location 
)
static

Definition at line 499 of file epic100.c.

500 {
501  int i;
502 
503  outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
504  /* Typical operation takes < 50 ticks. */
505 
506  for (i = 4000; i > 0; i--)
507  if ((inl(mmctl) & MII_READOP) == 0)
508  break;
509  return inw(mmdata);
510 }
#define MII_READOP
Definition: epic100.c:495
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
#define outl(data, io_addr)
Definition: io.h:329
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
static int mmctl
Definition: epic100.c:74
static int mmdata
Definition: epic100.c:75

References inl(), inw(), MII_READOP, mmctl, mmdata, and outl.

Referenced by epic100_open(), epic100_probe(), mii_check_link(), mii_find(), mii_reset(), mii_restart(), realtek_phy_speed(), rhine_probe(), smscusb_mii_check_link(), and velocity_set_link().

◆ epic100_irq() [1/2]

static void epic100_irq ( struct nic nic,
irq_action_t  action 
)
static

◆ epic100_probe()

static int epic100_probe ( struct nic nic,
struct pci_device pci 
)
static

Definition at line 108 of file epic100.c.

108  {
109 
110  int i;
111  unsigned short* ap;
112  unsigned int phy, phy_idx;
113 
114  if (pci->ioaddr == 0)
115  return 0;
116 
117  /* Ideally we would detect all network cards in slot order. That would
118  be best done a central PCI probe dispatch, which wouldn't work
119  well with the current structure. So instead we detect just the
120  Epic cards in slot order. */
121 
122  ioaddr = pci->ioaddr;
123 
124  nic->irqno = 0;
125  nic->ioaddr = pci->ioaddr & ~3;
126 
127  /* compute all used static epic100 registers address */
128  command = ioaddr + COMMAND; /* Control Register */
129  intstat = ioaddr + INTSTAT; /* Interrupt Status */
130  intmask = ioaddr + INTMASK; /* Interrupt Mask */
131  genctl = ioaddr + GENCTL; /* General Control */
132  eectl = ioaddr + EECTL; /* EEPROM Control */
133  test = ioaddr + TEST; /* Test register (clocks) */
134  mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
135  mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
136  lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
137  mc0 = ioaddr + MC0; /* Multicast Control */
138  rxcon = ioaddr + RXCON; /* Receive Control */
139  txcon = ioaddr + TXCON; /* Transmit Control */
140  prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
141  ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
142  eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
143 
144  /* Reset the chip & bring it out of low-power mode. */
146 
147  /* Disable ALL interrupts by setting the interrupt mask. */
149 
150  /*
151  * set the internal clocks:
152  * Application Note 7.15 says:
153  * In order to set the CLOCK TEST bit in the TEST register,
154  * perform the following:
155  *
156  * Write 0x0008 to the test register at least sixteen
157  * consecutive times.
158  *
159  * The CLOCK TEST bit is Write-Only. Writing it several times
160  * consecutively insures a successful write to the bit...
161  */
162 
163  for (i = 0; i < 16; i++) {
164  outl(0x00000008, test);
165  }
166 
167 #ifdef DEBUG_EEPROM
168 {
169  unsigned short sum = 0;
170  unsigned short value;
171  for (i = 0; i < 64; i++) {
172  value = read_eeprom(i);
173  eeprom[i] = value;
174  sum += value;
175  }
176 }
177 
178 #if (EPIC_DEBUG > 1)
179  printf("EEPROM contents\n");
180  for (i = 0; i < 64; i++) {
181  printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
182  }
183 #endif
184 #endif
185 
186  /* This could also be read from the EEPROM. */
187  ap = (unsigned short*)nic->node_addr;
188  for (i = 0; i < 3; i++)
189  *ap++ = inw(lan0 + i*4);
190 
191  DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
192 
193  /* Find the connected MII xcvrs. */
194  for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
195  int mii_status = mii_read(phy, 0);
196 
197  if (mii_status != 0xffff && mii_status != 0x0000) {
198  phys[phy_idx++] = phy;
199 #if (EPIC_DEBUG > 1)
200  printf("MII transceiver found at address %d.\n", phy);
201 #endif
202  }
203  }
204  if (phy_idx == 0) {
205 #if (EPIC_DEBUG > 1)
206  printf("***WARNING***: No MII transceiver found!\n");
207 #endif
208  /* Use the known PHY address of the EPII. */
209  phys[0] = 3;
210  }
211 
212  epic100_open();
214 
215  return 1;
216 }
static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
Definition: davicom.c:377
unsigned char irqno
Definition: nic.h:56
Definition: epic100.h:32
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
static int lan0
Definition: epic100.c:76
Definition: epic100.h:21
unsigned long ioaddr
I/O address.
Definition: pci.h:200
A command-line command.
Definition: command.h:9
static int mc0
Definition: epic100.c:77
#define GC_SOFT_RESET
Definition: epic100.h:89
Definition: epic100.h:23
Definition: epic100.h:42
Definition: epic100.h:35
#define INTR_DISABLE
Definition: epic100.h:83
Definition: epic100.h:34
static int rxcon
Definition: epic100.c:78
eeprom
Definition: 3c90x.h:232
unsigned int ioaddr
Definition: nic.h:55
static signed char phys[4]
Definition: epic100.c:88
Definition: epic100.h:29
static int txcon
Definition: epic100.c:79
Definition: epic100.h:28
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define outl(data, io_addr)
Definition: io.h:329
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
Definition: epic100.h:24
Definition: epic100.h:38
Definition: epic100.h:36
Definition: nic.h:49
static struct nic_operations epic100_operations
Definition: epic100.c:64
static int genctl
Definition: epic100.c:71
static int eththr
Definition: epic100.c:82
static int ioaddr
Definition: epic100.c:66
unsigned char * node_addr
Definition: nic.h:52
static int ptcdar
Definition: epic100.c:81
static int intstat
Definition: epic100.c:69
static int mmctl
Definition: epic100.c:74
Definition: epic100.h:41
static int prcdar
Definition: epic100.c:80
static int mii_read(int phy_id, int location)
Definition: epic100.c:499
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
static int mmdata
Definition: epic100.c:75
static int test
Definition: epic100.c:73
static int intmask
Definition: epic100.c:70
static int eectl
Definition: epic100.c:72
static void epic100_open(void)
Definition: epic100.c:230

References COMMAND, DBG, EECTL, eectl, epic100_open(), epic100_operations, eth_ntoa(), ETHTHR, eththr, GC_SOFT_RESET, GENCTL, genctl, INTMASK, intmask, INTR_DISABLE, INTSTAT, intstat, inw(), nic::ioaddr, ioaddr, pci_device::ioaddr, nic::irqno, LAN0, lan0, MC0, mc0, mii_read(), MMCTL, mmctl, MMDATA, mmdata, nic::nic_op, nic::node_addr, outl, phys, PRCDAR, prcdar, printf(), PTCDAR, ptcdar, read_eeprom(), RXCON, rxcon, TEST, test, TXCON, txcon, and value.

◆ set_rx_mode()

static void set_rx_mode ( void  )
static

Definition at line 218 of file epic100.c.

219 {
220  unsigned char mc_filter[8];
221  int i;
222  memset(mc_filter, 0xff, sizeof(mc_filter));
223  outl(0x0C, rxcon);
224  for(i = 0; i < 4; i++)
225  outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
226  return;
227 }
#define outw(data, io_addr)
Definition: io.h:319
static int mc0
Definition: epic100.c:77
static int rxcon
Definition: epic100.c:78
#define outl(data, io_addr)
Definition: io.h:329
void * memset(void *dest, int character, size_t len) __nonnull

References mc0, memset(), outl, outw, and rxcon.

Referenced by epic100_open().

◆ epic100_disable() [2/2]

static void epic100_disable ( struct nic *nic  __unused)
static

Definition at line 422 of file epic100.c.

422  {
423  /* Soft reset the chip. */
425 }
#define GC_SOFT_RESET
Definition: epic100.h:89
#define outl(data, io_addr)
Definition: io.h:329
static int genctl
Definition: epic100.c:71

References GC_SOFT_RESET, genctl, and outl.

◆ epic100_irq() [2/2]

static void epic100_irq ( struct nic *nic  __unused,
irq_action_t action  __unused 
)
static

Definition at line 427 of file epic100.c.

428 {
429  switch ( action ) {
430  case DISABLE :
431  break;
432  case ENABLE :
433  break;
434  case FORCE :
435  break;
436  }
437 }
Definition: nic.h:35
Definition: nic.h:37
Definition: nic.h:36

References DISABLE, ENABLE, and FORCE.

◆ PCI_DRIVER()

PCI_DRIVER ( epic100_driver  ,
epic100_nics  ,
PCI_NO_CLASS   
)

◆ DRIVER()

DRIVER ( "EPIC100"  ,
nic_driver  ,
pci_driver  ,
epic100_driver  ,
epic100_probe  ,
epic100_disable   
)

Variable Documentation

◆ epic100_operations

static struct nic_operations epic100_operations
static
Initial value:
= {
.connect = dummy_connect,
.poll = epic100_poll,
.transmit = epic100_transmit,
.irq = epic100_irq,
}
static int epic100_poll(struct nic *nic, int retrieve)
Definition: epic100.c:375
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
static void epic100_irq(struct nic *nic, irq_action_t action)
static void epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type, unsigned int len, const char *data)
Definition: epic100.c:305

Definition at line 64 of file epic100.c.

Referenced by epic100_probe().

◆ ioaddr

int ioaddr
static

Definition at line 66 of file epic100.c.

Referenced by epic100_probe().

◆ command

int command
static

Definition at line 68 of file epic100.c.

◆ intstat

int intstat
static

Definition at line 69 of file epic100.c.

Referenced by epic100_poll(), and epic100_probe().

◆ intmask

int intmask
static

Definition at line 70 of file epic100.c.

Referenced by epic100_probe().

◆ genctl

int genctl
static

Definition at line 71 of file epic100.c.

Referenced by epic100_disable(), epic100_open(), and epic100_probe().

◆ eectl

int eectl
static

Definition at line 72 of file epic100.c.

Referenced by epic100_probe().

◆ test

int test
static

◆ mmctl

int mmctl
static

Definition at line 74 of file epic100.c.

Referenced by epic100_probe(), and mii_read().

◆ mmdata

int mmdata
static

Definition at line 75 of file epic100.c.

Referenced by epic100_probe(), and mii_read().

◆ lan0

int lan0
static

Definition at line 76 of file epic100.c.

Referenced by epic100_probe().

◆ mc0

int mc0
static

Definition at line 77 of file epic100.c.

Referenced by epic100_probe(), and set_rx_mode().

◆ rxcon

int rxcon
static

Definition at line 78 of file epic100.c.

Referenced by epic100_probe(), and set_rx_mode().

◆ txcon

int txcon
static

Definition at line 79 of file epic100.c.

Referenced by epic100_open(), and epic100_probe().

◆ prcdar

int prcdar
static

Definition at line 80 of file epic100.c.

Referenced by epic100_open(), and epic100_probe().

◆ ptcdar

int ptcdar
static

Definition at line 81 of file epic100.c.

Referenced by epic100_open(), and epic100_probe().

◆ eththr

int eththr
static

Definition at line 82 of file epic100.c.

Referenced by epic100_open(), and epic100_probe().

◆ cur_rx

unsigned int cur_rx
static

◆ cur_tx

unsigned int cur_tx
static

Definition at line 84 of file epic100.c.

Referenced by epic100_init_ring(), and epic100_transmit().

◆ phys

signed char phys[4]
static

◆ rx_ring

struct epic_rx_desc rx_ring[RX_RING_SIZE]

Definition at line 90 of file epic100.c.

◆ tx_ring

struct epic_tx_desc tx_ring[TX_RING_SIZE]

Definition at line 92 of file epic100.c.

◆ rx_packet

unsigned char rx_packet[PKT_BUF_SZ *RX_RING_SIZE]

Definition at line 94 of file epic100.c.

◆ tx_packet

unsigned char tx_packet[PKT_BUF_SZ *TX_RING_SIZE]

Definition at line 95 of file epic100.c.

◆ __shared

struct { ... } __shared

◆ epic100_nics

struct pci_device_id epic100_nics[]
static
Initial value:
= {
PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII", 0),
PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175", 0),
}
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283

Definition at line 520 of file epic100.c.