iPXE
myri10ge.c
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00001 /************************************************* -*- linux-c -*-
00002  * Myricom 10Gb Network Interface Card Software
00003  * Copyright 2009, Myricom, Inc.
00004  *
00005  * This program is free software; you can redistribute it and/or
00006  * modify it under the terms of the GNU General Public License,
00007  * version 2, as published by the Free Software Foundation.
00008  *
00009  * This program is distributed in the hope that it will be useful,
00010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  * GNU General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00017  * 02110-1301, USA.
00018  ****************************************************************/
00019 
00020 FILE_LICENCE ( GPL2_ONLY );
00021 
00022 /*
00023  * Author: Glenn Brown <glenn@myri.com>
00024  */
00025 
00026 /*
00027  * General Theory of Operation
00028  *
00029  * This is a minimal Myricom 10 gigabit Ethernet driver for network
00030  * boot.
00031  *
00032  * Initialization
00033  *
00034  * myri10ge_pci_probe() is called by iPXE during initialization.
00035  * Minimal NIC initialization is performed to minimize resources
00036  * consumed when the driver is resident but unused.
00037  *
00038  * Network Boot
00039  *
00040  * myri10ge_net_open() is called by iPXE before attempting to network
00041  * boot from the card.  Packet buffers are allocated and the NIC
00042  * interface is initialized.
00043  *
00044  * Transmit
00045  *
00046  * myri10ge_net_transmit() enqueues frames for transmission by writing
00047  * discriptors to the NIC's tx ring.  For simplicity and to avoid
00048  * copies, we always have the NIC DMA up the packet.  The sent I/O
00049  * buffer is released once the NIC signals myri10ge_interrupt_handler()
00050  * that the send has completed.
00051  *
00052  * Receive
00053  *
00054  * Receives are posted to the NIC's receive ring.  The NIC fills a
00055  * DMAable receive_completion ring with completion notifications.
00056  * myri10ge_net_poll() polls for these receive notifications, posts
00057  * replacement receive buffers to the NIC, and passes received frames
00058  * to netdev_rx().
00059  *
00060  * NonVolatile Storage
00061  *
00062  * This driver supports NonVolatile Storage (nvs) in the NIC EEPROM.
00063  * If the last EEPROM block is not otherwise filled, we tell
00064  * iPXE it may store NonVolatile Options (nvo) there.
00065  */
00066 
00067 /*
00068  * Debugging levels:
00069  *      - DBG() is for any errors, i.e. failed alloc_iob(), malloc_dma(),
00070  *        TX overflow, corrupted packets, ...
00071  *      - DBG2() is for successful events, like packet received,
00072  *        packet transmitted, and other general notifications.
00073  *      - DBGP() prints the name of each called function on entry
00074  */
00075 
00076 #include <stdint.h>
00077 
00078 #include <byteswap.h>
00079 #include <errno.h>
00080 #include <ipxe/ethernet.h>
00081 #include <ipxe/if_ether.h>
00082 #include <ipxe/iobuf.h>
00083 #include <ipxe/malloc.h>
00084 #include <ipxe/netdevice.h>
00085 #include <ipxe/nvo.h>
00086 #include <ipxe/nvs.h>
00087 #include <ipxe/pci.h>
00088 #include <ipxe/timer.h>
00089 
00090 #include "myri10ge_mcp.h"
00091 
00092 /****************************************************************
00093  * Forward declarations
00094  ****************************************************************/
00095 
00096 /* PCI driver entry points */
00097 
00098 static int      myri10ge_pci_probe ( struct pci_device* );
00099 static void     myri10ge_pci_remove ( struct pci_device* );
00100 
00101 /* Network device operations */
00102 
00103 static void     myri10ge_net_close ( struct net_device* );
00104 static void     myri10ge_net_irq ( struct net_device*, int enable );
00105 static int      myri10ge_net_open ( struct net_device* );
00106 static void     myri10ge_net_poll ( struct net_device* );
00107 static int      myri10ge_net_transmit ( struct net_device*, struct io_buffer* );
00108 
00109 /****************************************************************
00110  * Constants
00111  ****************************************************************/
00112 
00113 /* Maximum ring indices, used to wrap ring indices.  These must be 2**N-1. */
00114 
00115 #define MYRI10GE_TRANSMIT_WRAP                  1U
00116 #define MYRI10GE_RECEIVE_WRAP                   7U
00117 #define MYRI10GE_RECEIVE_COMPLETION_WRAP        31U
00118 
00119 /****************************************************************
00120  * Driver internal data types.
00121  ****************************************************************/
00122 
00123 /* Structure holding all DMA buffers for a NIC, which we will
00124    allocated as contiguous read/write DMAable memory when the NIC is
00125    initialized. */
00126 
00127 struct myri10ge_dma_buffers
00128 {
00129         /* The NIC DMAs receive completion notifications into this ring */
00130 
00131         mcp_slot_t receive_completion[1+MYRI10GE_RECEIVE_COMPLETION_WRAP];
00132 
00133         /* Interrupt details are DMAd here before interrupting. */
00134 
00135         mcp_irq_data_t irq_data; /* 64B */
00136 
00137         /* NIC command completion status is DMAd here. */
00138 
00139         mcp_cmd_response_t command_response; /* 8B */
00140 };
00141 
00142 struct myri10ge_private
00143 {
00144         /* Interrupt support */
00145 
00146         uint32  *irq_claim;     /* in NIC SRAM */
00147         uint32  *irq_deassert;  /* in NIC SRAM */
00148 
00149         /* DMA buffers. */
00150 
00151         struct myri10ge_dma_buffers     *dma;
00152 
00153         /*
00154          * Transmit state.
00155          *
00156          * The counts here are uint32 for easy comparison with
00157          * priv->dma->irq_data.send_done_count and with each other.
00158          */
00159 
00160         mcp_kreq_ether_send_t   *transmit_ring; /* in NIC SRAM */
00161         uint32                   transmit_ring_wrap;
00162         uint32                   transmits_posted;
00163         uint32                   transmits_done;
00164         struct io_buffer        *transmit_iob[1 + MYRI10GE_TRANSMIT_WRAP];
00165 
00166         /*
00167          * Receive state.
00168          */
00169 
00170         mcp_kreq_ether_recv_t   *receive_post_ring;     /* in NIC SRAM */
00171         unsigned int             receive_post_ring_wrap;
00172         unsigned int             receives_posted;
00173         unsigned int             receives_done;
00174         struct io_buffer        *receive_iob[1 + MYRI10GE_RECEIVE_WRAP];
00175 
00176         /* Address for writing commands to the firmware.
00177            BEWARE: the value must be written 32 bits at a time. */
00178 
00179         mcp_cmd_t       *command;
00180 
00181         /*
00182          * Nonvolatile Storage for configuration options.
00183          */
00184 
00185         struct nvs_device       nvs;
00186         struct nvo_block        nvo;
00187         unsigned int            nvo_registered;
00188 
00189         /* Cached PCI capability locations. */
00190 
00191         uint8                   pci_cap_vs;
00192 };
00193 
00194 /****************************************************************
00195  * Driver internal functions.
00196  ****************************************************************/
00197 
00198 /* Print ring status when debugging.  Use this only after a printed
00199    value changes. */
00200 
00201 #define DBG2_RINGS( priv )                                              \
00202         DBG2 ( "tx %x/%x rx %x/%x in %s() \n",                          \
00203                ( priv ) ->transmits_done, ( priv ) -> transmits_posted, \
00204                ( priv ) ->receives_done, ( priv ) -> receives_posted,   \
00205                __FUNCTION__ )
00206 
00207 /*
00208  * Return a pointer to the driver private data for a network device.
00209  *
00210  * @v netdev    Network device created by this driver.
00211  * @ret priv    The corresponding driver private data.
00212  */
00213 static inline struct myri10ge_private *myri10ge_priv ( struct net_device *nd )
00214 {
00215         /* Our private data always follows the network device in memory,
00216            since we use alloc_netdev() to allocate the storage. */
00217 
00218         return ( struct myri10ge_private * ) ( nd + 1 );
00219 }
00220 
00221 /*
00222  * Convert a Myri10ge driver private data pointer to a netdev pointer.
00223  *
00224  * @v p         Myri10ge device private data.
00225  * @ret r       The corresponding network device.
00226  */
00227 static inline struct net_device *myri10ge_netdev ( struct myri10ge_private *p )
00228 {
00229         return ( ( struct net_device * ) p ) - 1;
00230 }
00231 
00232 /*
00233  * Convert a network device pointer to a PCI device pointer.
00234  *
00235  * @v netdev    A Network Device.
00236  * @ret r       The corresponding PCI device.
00237  */
00238 static inline struct pci_device *myri10ge_pcidev ( struct net_device *netdev )
00239 {
00240         return container_of (netdev->dev, struct pci_device, dev);
00241 }
00242 
00243 /*
00244  * Pass a receive buffer to the NIC to be filled.
00245  *
00246  * @v priv      The network device to receive the buffer.
00247  * @v iob       The I/O buffer to fill.
00248  *
00249  * Receive buffers are filled in FIFO order.
00250  */
00251 static void myri10ge_post_receive ( struct myri10ge_private *priv,
00252                                     struct io_buffer *iob )
00253 {
00254         unsigned int             receives_posted;
00255         mcp_kreq_ether_recv_t   *request;
00256 
00257         /* Record the posted I/O buffer, to be passed to netdev_rx() on
00258            receive. */
00259 
00260         receives_posted = priv->receives_posted;
00261         priv->receive_iob[receives_posted & MYRI10GE_RECEIVE_WRAP] = iob;
00262 
00263         /* Post the receive. */
00264 
00265         request = &priv->receive_post_ring[receives_posted
00266                                            & priv->receive_post_ring_wrap];
00267         request->addr_high = 0;
00268         wmb();
00269         request->addr_low = htonl ( virt_to_bus ( iob->data ) );
00270         priv->receives_posted = ++receives_posted;
00271 }
00272 
00273 /*
00274  * Execute a command on the NIC.
00275  *
00276  * @v priv      NIC to perform the command.
00277  * @v cmd       The command to perform.
00278  * @v data      I/O copy buffer for parameters/results
00279  * @ret rc      0 on success, else an error code.
00280  */
00281 static int myri10ge_command ( struct myri10ge_private *priv,
00282                               uint32 cmd,
00283                               uint32 data[3] )
00284 {
00285         int                              i;
00286         mcp_cmd_t                       *command;
00287         uint32                           result;
00288         unsigned int                     slept_ms;
00289         volatile mcp_cmd_response_t     *response;
00290 
00291         DBGP ( "myri10ge_command ( ,%d, ) \n", cmd );
00292         command = priv->command;
00293         response = &priv->dma->command_response;
00294 
00295         /* Mark the command as incomplete. */
00296 
00297         response->result = 0xFFFFFFFF;
00298 
00299         /* Pass the command to the NIC. */
00300 
00301         command->cmd                = htonl ( cmd );
00302         command->data0              = htonl ( data[0] );
00303         command->data1              = htonl ( data[1] );
00304         command->data2              = htonl ( data[2] );
00305         command->response_addr.high = 0;
00306         command->response_addr.low
00307                 = htonl ( virt_to_bus ( &priv->dma->command_response ) );
00308         for ( i=0; i<9; i++ )
00309                 command->pad[i] = 0;
00310         wmb();
00311         command->pad[9] = 0;
00312 
00313         /* Wait up to 2 seconds for a response. */
00314 
00315         for ( slept_ms=0; slept_ms<2000; slept_ms++ ) {
00316                 result = response->result;
00317                 if ( result == 0 ) {
00318                         data[0] = ntohl ( response->data );
00319                         return 0;
00320                 } else if ( result != 0xFFFFFFFF ) {
00321                         DBG ( "cmd%d:0x%x\n",
00322                               cmd,
00323                               ntohl ( response->result ) );
00324                         return -EIO;
00325                 }
00326                 udelay ( 1000 );
00327                 rmb();
00328         }
00329         DBG ( "cmd%d:timed out\n", cmd );
00330         return -ETIMEDOUT;
00331 }
00332 
00333 /*
00334  * Handle any pending interrupt.
00335  *
00336  * @v netdev            Device being polled for interrupts.
00337  *
00338  * This is called periodically to let the driver check for interrupts.
00339  */
00340 static void myri10ge_interrupt_handler ( struct net_device *netdev )
00341 {
00342         struct myri10ge_private *priv;
00343         mcp_irq_data_t          *irq_data;
00344         uint8                    valid;
00345 
00346         priv = myri10ge_priv ( netdev );
00347         irq_data = &priv->dma->irq_data;
00348 
00349         /* Return if there was no interrupt. */
00350 
00351         rmb();
00352         valid = irq_data->valid;
00353         if ( !valid )
00354                 return;
00355         DBG2 ( "irq " );
00356 
00357         /* Tell the NIC to deassert the interrupt and clear
00358            irq_data->valid.*/
00359 
00360         *priv->irq_deassert = 0;        /* any value is OK. */
00361         mb();
00362 
00363         /* Handle any new receives. */
00364 
00365         if ( valid & 1 ) {
00366 
00367                 /* Pass the receive interrupt token back to the NIC. */
00368 
00369                 DBG2 ( "rx " );
00370                 *priv->irq_claim = htonl ( 3 );
00371                 wmb();
00372         }
00373 
00374         /* Handle any sent packet by freeing its I/O buffer, now that
00375            we know it has been DMAd. */
00376 
00377         if ( valid & 2 ) {
00378                 unsigned int nic_done_count;
00379 
00380                 DBG2 ( "snt " );
00381                 nic_done_count = ntohl ( priv->dma->irq_data.send_done_count );
00382                 while ( priv->transmits_done != nic_done_count ) {
00383                         struct io_buffer *iob;
00384 
00385                         iob = priv->transmit_iob [priv->transmits_done
00386                                                   & MYRI10GE_TRANSMIT_WRAP];
00387                         DBG2 ( "%p ", iob );
00388                         netdev_tx_complete ( netdev, iob );
00389                         ++priv->transmits_done;
00390                 }
00391         }
00392 
00393         /* Record any statistics update. */
00394 
00395         if ( irq_data->stats_updated ) {
00396 
00397                 /* Update the link status. */
00398 
00399                 DBG2 ( "stats " );
00400                 if ( ntohl ( irq_data->link_up ) == MXGEFW_LINK_UP )
00401                         netdev_link_up ( netdev );
00402                 else
00403                         netdev_link_down ( netdev );
00404 
00405                 /* Ignore all error counters from the NIC. */
00406         }
00407 
00408         /* Wait for the interrupt to be deasserted, as indicated by
00409            irq_data->valid, which is set by the NIC after the deassert. */
00410 
00411         DBG2 ( "wait " );
00412         do {
00413                 mb();
00414         } while ( irq_data->valid );
00415 
00416         /* Claim the interrupt to enable future interrupt generation. */
00417 
00418         DBG2 ( "claim\n" );
00419         * ( priv->irq_claim + 1 ) = htonl ( 3 );
00420         mb();
00421 }
00422 
00423 /* Constants for reading the STRING_SPECS via the Myricom
00424    Vendor Specific PCI configuration space capability. */
00425 
00426 #define VS_EEPROM_READ_ADDR ( vs + 0x04 )
00427 #define VS_EEPROM_READ_DATA ( vs + 0x08 )
00428 #define VS_EEPROM_WRITE     ( vs + 0x0C )
00429 #define VS_ADDR ( vs + 0x18 )
00430 #define VS_DATA ( vs + 0x14 )
00431 #define VS_MODE ( vs + 0x10 )
00432 #define         VS_MODE_READ32 0x3
00433 #define         VS_MODE_LOCATE 0x8
00434 #define                 VS_LOCATE_STRING_SPECS 0x3
00435 #define         VS_MODE_EEPROM_STREAM_WRITE 0xB
00436 
00437 /*
00438  * Read MAC address from its 'string specs' via the vendor-specific
00439  * capability.  (This capability allows NIC SRAM and ROM to be read
00440  * before it is mapped.)
00441  *
00442  * @v pci               The device.
00443  * @v vs                Offset of the PCI Vendor-Specific Capability.
00444  * @v mac               Buffer to store the MAC address.
00445  * @ret rc              Returns 0 on success, else an error code.
00446  */
00447 static int mac_address_from_string_specs ( struct pci_device *pci,
00448                                            unsigned int vs,
00449                                            uint8 mac[ETH_ALEN] )
00450 {
00451         char string_specs[256];
00452         char *ptr, *limit;
00453         char *to = string_specs;
00454         uint32 addr;
00455         uint32 len;
00456         int mac_set = 0;
00457 
00458         /* Locate the String specs in LANai SRAM. */
00459 
00460         pci_write_config_byte ( pci, VS_MODE, VS_MODE_LOCATE );
00461         pci_write_config_dword ( pci, VS_ADDR, VS_LOCATE_STRING_SPECS );
00462         pci_read_config_dword ( pci, VS_ADDR, &addr );
00463         pci_read_config_dword ( pci, VS_DATA, &len );
00464         DBG2 ( "ss@%x,%x\n", addr, len );
00465 
00466         /* Copy in the string specs.  Use 32-bit reads for performance. */
00467 
00468         if ( len > sizeof ( string_specs ) || ( len & 3 ) ) {
00469                 pci_write_config_byte ( pci, VS_MODE, 0 );
00470                 DBG ( "SS too big\n" );
00471                 return -ENOTSUP;
00472         }
00473 
00474         pci_write_config_byte ( pci, VS_MODE, VS_MODE_READ32 );
00475         while ( len >= 4 ) {
00476                 uint32 tmp;
00477 
00478                 pci_write_config_byte ( pci, VS_ADDR, addr );
00479                 pci_read_config_dword ( pci, VS_DATA, &tmp );
00480                 tmp = ntohl ( tmp );
00481                 memcpy ( to, &tmp, 4 );
00482                 to += 4;
00483                 addr += 4;
00484                 len -= 4;
00485         }
00486         pci_write_config_byte ( pci, VS_MODE, 0 );
00487 
00488         /* Parse the string specs. */
00489 
00490         DBG2 ( "STRING_SPECS:\n" );
00491         ptr = string_specs;
00492         limit = string_specs + sizeof ( string_specs );
00493         while ( *ptr != '\0' && ptr < limit ) {
00494                 DBG2 ( "%s\n", ptr );
00495                 if ( memcmp ( ptr, "MAC=", 4 ) == 0 ) {
00496                         unsigned int i;
00497 
00498                         ptr += 4;
00499                         for ( i=0; i<6; i++ ) {
00500                                 if ( ( ptr + 2 ) > limit ) {
00501                                         DBG ( "bad MAC addr\n" );
00502                                         return -ENOTSUP;
00503                                 }
00504                                 mac[i] = strtoul ( ptr, &ptr, 16 );
00505                                 ptr += 1;
00506                         }
00507                         mac_set = 1;
00508                 }
00509                 else
00510                         while ( ptr < limit && *ptr++ );
00511         }
00512 
00513         /* Verify we parsed all we need. */
00514 
00515         if ( !mac_set ) {
00516                 DBG ( "no MAC addr\n" );
00517                 return -ENOTSUP;
00518         }
00519 
00520         DBG2 ( "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
00521                mac[0], mac[1], mac[2], mac[3], mac[4], mac[5] );
00522 
00523         return 0;
00524 }
00525 
00526 /****************************************************************
00527  * NonVolatile Storage support
00528  ****************************************************************/
00529 
00530 /*
00531  * Fill a buffer with data read from nonvolatile storage.
00532  *
00533  * @v nvs       The NonVolatile Storage device to be read.
00534  * @v addr      The first NonVolatile Storage address to be read.
00535  * @v _buf      Pointer to the data buffer to be filled.
00536  * @v len       The number of bytes to copy.
00537  * @ret rc      0 on success, else nonzero.
00538  */
00539 static int myri10ge_nvs_read ( struct nvs_device *nvs,
00540                                unsigned int addr,
00541                                void *_buf,
00542                                size_t len )
00543 {
00544         struct myri10ge_private *priv =
00545                 container_of (nvs, struct myri10ge_private, nvs);
00546         struct pci_device *pci = myri10ge_pcidev ( myri10ge_netdev ( priv ) );
00547         unsigned int vs = priv->pci_cap_vs;
00548         unsigned char *buf = (unsigned char *) _buf;
00549         unsigned int data;
00550         unsigned int i, j;
00551 
00552         DBGP ( "myri10ge_nvs_read\n" );
00553 
00554         /* Issue the first read address. */
00555 
00556         pci_write_config_byte ( pci, VS_EEPROM_READ_ADDR + 3, addr>>16 );
00557         pci_write_config_byte ( pci, VS_EEPROM_READ_ADDR + 2, addr>>8 );
00558         pci_write_config_byte ( pci, VS_EEPROM_READ_ADDR + 1, addr );
00559         addr++;
00560 
00561         /* Issue all the reads, and harvest the results every 4th issue. */
00562 
00563         for ( i=0; i<len; ++i,addr++ ) {
00564 
00565                 /* Issue the next read address, updating only the
00566                    bytes that need updating.  We always update the
00567                    LSB, which triggers the read. */
00568 
00569                 if ( ( addr & 0xff ) == 0 ) {
00570                         if ( ( addr & 0xffff ) == 0 ) {
00571                                 pci_write_config_byte ( pci,
00572                                                         VS_EEPROM_READ_ADDR + 3,
00573                                                         addr >> 16 );
00574                         }
00575                         pci_write_config_byte ( pci,
00576                                                 VS_EEPROM_READ_ADDR + 2,
00577                                                 addr >> 8 );
00578                 }
00579                 pci_write_config_byte ( pci, VS_EEPROM_READ_ADDR + 1, addr );
00580 
00581                 /* If 4 data bytes are available, read them with a single read. */
00582 
00583                 if ( ( i & 3 ) == 3 ) {
00584                         pci_read_config_dword ( pci,
00585                                                 VS_EEPROM_READ_DATA,
00586                                                 &data );
00587                         for ( j=0; j<4; j++ ) {
00588                                 buf[i-j] = data;
00589                                 data >>= 8;
00590                         }
00591                 }
00592         }
00593 
00594         /* Harvest any remaining results. */
00595 
00596         if ( ( i & 3 ) != 0 ) {
00597                 pci_read_config_dword ( pci, VS_EEPROM_READ_DATA, &data );
00598                 for ( j=1; j<=(i&3); j++ ) {
00599                         buf[i-j] = data;
00600                         data >>= 8;
00601                 }
00602         }
00603 
00604         DBGP_HDA ( addr - len, _buf, len );
00605         return 0;
00606 }
00607 
00608 /*
00609  * Write a buffer into nonvolatile storage.
00610  *
00611  * @v nvs       The NonVolatile Storage device to be written.
00612  * @v address   The NonVolatile Storage address to be written.
00613  * @v _buf      Pointer to the data to be written.
00614  * @v len       Length of the buffer to be written.
00615  * @ret rc      0 on success, else nonzero.
00616  */
00617 static int myri10ge_nvs_write ( struct nvs_device *nvs,
00618                                 unsigned int addr,
00619                                 const void *_buf,
00620                                 size_t len )
00621 {
00622         struct myri10ge_private *priv =
00623                 container_of (nvs, struct myri10ge_private, nvs);
00624         struct pci_device *pci = myri10ge_pcidev ( myri10ge_netdev ( priv ) );
00625         unsigned int vs = priv->pci_cap_vs;
00626         const unsigned char *buf = (const unsigned char *)_buf;
00627         unsigned int i;
00628         uint8 verify;
00629 
00630         DBGP ( "nvs_write " );
00631         DBGP_HDA ( addr, _buf, len );
00632 
00633         /* Start erase of the NonVolatile Options block. */
00634 
00635         DBGP ( "erasing " );
00636         pci_write_config_dword ( pci, VS_EEPROM_WRITE, ( addr << 8 ) | 0xff );
00637 
00638         /* Wait for erase to complete. */
00639 
00640         DBGP ( "waiting " );
00641         pci_read_config_byte ( pci, VS_EEPROM_READ_DATA, &verify );
00642         while ( verify != 0xff ) {
00643                 pci_write_config_byte ( pci, VS_EEPROM_READ_ADDR + 1, addr );
00644                 pci_read_config_byte ( pci, VS_EEPROM_READ_DATA, &verify );
00645         }
00646 
00647         /* Write the data one byte at a time. */
00648 
00649         DBGP ( "writing " );
00650         pci_write_config_byte ( pci, VS_MODE, VS_MODE_EEPROM_STREAM_WRITE );
00651         pci_write_config_dword ( pci, VS_ADDR, addr );
00652         for (i=0; i<len; i++, addr++)
00653                 pci_write_config_byte ( pci, VS_DATA, buf[i] );
00654         pci_write_config_dword ( pci, VS_ADDR, 0xffffffff );
00655         pci_write_config_byte ( pci, VS_MODE, 0 );
00656 
00657         DBGP ( "done\n" );
00658         return 0;
00659 }
00660 
00661 /*
00662  * Initialize NonVolatile storage support for a device.
00663  *
00664  * @v priv      Device private data for the device.
00665  * @ret rc      0 on success, else an error code.
00666  */
00667 
00668 static int myri10ge_nv_init ( struct myri10ge_private *priv )
00669 {
00670         int rc;
00671         struct myri10ge_eeprom_header
00672         {
00673                 uint8 __jump[8];
00674                 uint32 eeprom_len;
00675                 uint32 eeprom_segment_len;
00676                 uint32 mcp1_offset;
00677                 uint32 mcp2_offset;
00678                 uint32 version;
00679         } hdr;
00680         uint32 mcp2_len;
00681         unsigned int nvo_fragment_pos;
00682 
00683         DBGP ( "myri10ge_nv_init\n" );
00684 
00685         /* Read the EEPROM header, and byteswap the fields we will use.
00686            This is safe even though priv->nvs is not yet initialized. */
00687 
00688         rc = myri10ge_nvs_read ( &priv->nvs, 0, &hdr, sizeof ( hdr ) );
00689         if ( rc ) {
00690                 DBG ( "EEPROM header unreadable\n" );
00691                 return rc;
00692         }
00693         hdr.eeprom_len         = ntohl ( hdr.eeprom_len );
00694         hdr.eeprom_segment_len = ntohl ( hdr.eeprom_segment_len );
00695         hdr.mcp2_offset        = ntohl ( hdr.mcp2_offset );
00696         hdr.version            = ntohl ( hdr.version );
00697         DBG2 ( "eelen:%xh seglen:%xh mcp2@%xh ver%d\n", hdr.eeprom_len,
00698                hdr.eeprom_segment_len, hdr.mcp2_offset, hdr.version );
00699 
00700         /* If the firmware does not support EEPROM writes, simply return. */
00701 
00702         if ( hdr.version < 1 ) {
00703                 DBG ( "No EEPROM write support\n" );
00704                 return 0;
00705         }
00706 
00707         /* Read the length of MCP2. */
00708 
00709         rc = myri10ge_nvs_read ( &priv->nvs, hdr.mcp2_offset, &mcp2_len, 4 );
00710         mcp2_len = ntohl ( mcp2_len );
00711         DBG2 ( "mcp2len:%xh\n", mcp2_len );
00712 
00713         /* Determine the position of the NonVolatile Options fragment and
00714            simply return if it overlaps other data. */
00715 
00716         nvo_fragment_pos = hdr.eeprom_len -  hdr.eeprom_segment_len;
00717         if ( hdr.mcp2_offset + mcp2_len > nvo_fragment_pos ) {
00718                 DBG ( "EEPROM full\n" );
00719                 return 0;
00720         }
00721 
00722         /* Initialize NonVolatile Storage state. */
00723 
00724         priv->nvs.word_len_log2 = 0;
00725         priv->nvs.size          = hdr.eeprom_len;
00726         priv->nvs.block_size    = hdr.eeprom_segment_len;
00727         priv->nvs.read          = myri10ge_nvs_read;
00728         priv->nvs.write         = myri10ge_nvs_write;
00729 
00730         /* Register the NonVolatile Options storage. */
00731 
00732         nvo_init ( &priv->nvo,
00733                    &priv->nvs,
00734                    nvo_fragment_pos, 0x200,
00735                    NULL,
00736                    & myri10ge_netdev (priv) -> refcnt );
00737         rc = register_nvo ( &priv->nvo,
00738                             netdev_settings ( myri10ge_netdev ( priv ) ) );
00739         if ( rc ) {
00740                 DBG ("register_nvo failed");
00741                 return rc;
00742         }
00743 
00744         priv->nvo_registered = 1;
00745         DBG2 ( "NVO supported\n" );
00746         return 0;
00747 }
00748 
00749 void
00750 myri10ge_nv_fini ( struct myri10ge_private *priv )
00751 {
00752         /* Simply return if nonvolatile access is not supported. */
00753 
00754         if ( 0 == priv->nvo_registered )
00755                 return;
00756 
00757         unregister_nvo ( &priv->nvo );
00758 }
00759 
00760 /****************************************************************
00761  * iPXE PCI Device Driver API functions
00762  ****************************************************************/
00763 
00764 /*
00765  * Initialize the PCI device.
00766  *
00767  * @v pci               The device's associated pci_device structure.
00768  * @v id                The PCI device + vendor id.
00769  * @ret rc              Returns zero if successfully initialized.
00770  *
00771  * This function is called very early on, while iPXE is initializing.
00772  * This is a iPXE PCI Device Driver API function.
00773  */
00774 static int myri10ge_pci_probe ( struct pci_device *pci )
00775 {
00776         static struct net_device_operations myri10ge_operations = {
00777                 .open     = myri10ge_net_open,
00778                 .close    = myri10ge_net_close,
00779                 .transmit = myri10ge_net_transmit,
00780                 .poll     = myri10ge_net_poll,
00781                 .irq      = myri10ge_net_irq
00782         };
00783 
00784         const char *dbg;
00785         int rc;
00786         struct net_device *netdev;
00787         struct myri10ge_private *priv;
00788 
00789         DBGP ( "myri10ge_pci_probe: " );
00790 
00791         netdev = alloc_etherdev ( sizeof ( *priv ) );
00792         if ( !netdev ) {
00793                 rc = -ENOMEM;
00794                 dbg = "alloc_etherdev";
00795                 goto abort_with_nothing;
00796         }
00797 
00798         netdev_init ( netdev, &myri10ge_operations );
00799         priv = myri10ge_priv ( netdev );
00800 
00801         pci_set_drvdata ( pci, netdev );
00802         netdev->dev = &pci->dev;
00803 
00804         /* Make sure interrupts are disabled. */
00805 
00806         myri10ge_net_irq ( netdev, 0 );
00807 
00808         /* Find the PCI Vendor-Specific capability. */
00809 
00810         priv->pci_cap_vs = pci_find_capability ( pci , PCI_CAP_ID_VNDR );
00811         if ( 0 == priv->pci_cap_vs ) {
00812                 rc = -ENOTSUP;
00813                 dbg = "no_vs";
00814                 goto abort_with_netdev_init;
00815         }
00816 
00817         /* Read the NIC HW address. */
00818 
00819         rc = mac_address_from_string_specs ( pci,
00820                                              priv->pci_cap_vs,
00821                                              netdev->hw_addr );
00822         if ( rc ) {
00823                 dbg = "mac_from_ss";
00824                 goto abort_with_netdev_init;
00825         }
00826         DBGP ( "mac " );
00827 
00828         /* Enable bus master, etc. */
00829 
00830         adjust_pci_device ( pci );
00831         DBGP ( "pci " );
00832 
00833         /* Register the initialized network device. */
00834 
00835         rc = register_netdev ( netdev );
00836         if ( rc ) {
00837                 dbg = "register_netdev";
00838                 goto abort_with_netdev_init;
00839         }
00840 
00841         /* Initialize NonVolatile Storage support. */
00842 
00843         rc = myri10ge_nv_init ( priv );
00844         if ( rc ) {
00845                 dbg = "myri10ge_nv_init";
00846                 goto abort_with_registered_netdev;
00847         }
00848 
00849         DBGP ( "done\n" );
00850 
00851         return 0;
00852 
00853 abort_with_registered_netdev:
00854         unregister_netdev ( netdev );
00855 abort_with_netdev_init:
00856         netdev_nullify ( netdev );
00857         netdev_put ( netdev );
00858 abort_with_nothing:
00859         DBG ( "%s:%s\n", dbg, strerror ( rc ) );
00860         return rc;
00861 }
00862 
00863 /*
00864  * Remove a device from the PCI device list.
00865  *
00866  * @v pci               PCI device to remove.
00867  *
00868  * This is a PCI Device Driver API function.
00869  */
00870 static void myri10ge_pci_remove ( struct pci_device *pci )
00871 {
00872         struct net_device       *netdev;
00873 
00874         DBGP ( "myri10ge_pci_remove\n" );
00875         netdev = pci_get_drvdata ( pci );
00876 
00877         myri10ge_nv_fini ( myri10ge_priv ( netdev ) );
00878         unregister_netdev ( netdev );
00879         netdev_nullify ( netdev );
00880         netdev_put ( netdev );
00881 }
00882 
00883 /****************************************************************
00884  * iPXE Network Device Driver Operations
00885  ****************************************************************/
00886 
00887 /*
00888  * Close a network device.
00889  *
00890  * @v netdev            Device to close.
00891  *
00892  * This is a iPXE Network Device Driver API function.
00893  */
00894 static void myri10ge_net_close ( struct net_device *netdev )
00895 {
00896         struct myri10ge_private *priv;
00897         uint32                   data[3];
00898 
00899         DBGP ( "myri10ge_net_close\n" );
00900         priv = myri10ge_priv ( netdev );
00901 
00902         /* disable interrupts */
00903 
00904         myri10ge_net_irq ( netdev, 0 );
00905 
00906         /* Reset the NIC interface, so we won't get any more events from
00907            the NIC. */
00908 
00909         myri10ge_command ( priv, MXGEFW_CMD_RESET, data );
00910 
00911         /* Free receive buffers that were never filled. */
00912 
00913         while ( priv->receives_done != priv->receives_posted ) {
00914                 free_iob ( priv->receive_iob[priv->receives_done
00915                                              & MYRI10GE_RECEIVE_WRAP] );
00916                 ++priv->receives_done;
00917         }
00918 
00919         /* Release DMAable memory. */
00920 
00921         free_dma ( priv->dma, sizeof ( *priv->dma ) );
00922 
00923         /* Erase all state from the open. */
00924 
00925         memset ( priv, 0, sizeof ( *priv ) );
00926 
00927         DBG2_RINGS ( priv );
00928 }
00929 
00930 /*
00931  * Enable or disable IRQ masking.
00932  *
00933  * @v netdev            Device to control.
00934  * @v enable            Zero to mask off IRQ, non-zero to enable IRQ.
00935  *
00936  * This is a iPXE Network Driver API function.
00937  */
00938 static void myri10ge_net_irq ( struct net_device *netdev, int enable )
00939 {
00940         struct pci_device       *pci_dev;
00941         uint16                   val;
00942 
00943         DBGP ( "myri10ge_net_irq\n" );
00944         pci_dev = ( struct pci_device * ) netdev->dev;
00945 
00946         /* Adjust the Interrupt Disable bit in the Command register of the
00947            PCI Device. */
00948 
00949         pci_read_config_word ( pci_dev, PCI_COMMAND, &val );
00950         if ( enable )
00951                 val &= ~PCI_COMMAND_INTX_DISABLE;
00952         else
00953                 val |= PCI_COMMAND_INTX_DISABLE;
00954         pci_write_config_word ( pci_dev, PCI_COMMAND, val );
00955 }
00956 
00957 /*
00958  * Opens a network device.
00959  *
00960  * @v netdev            Device to be opened.
00961  * @ret rc              Non-zero if failed to open.
00962  *
00963  * This enables tx and rx on the device.
00964  * This is a iPXE Network Device Driver API function.
00965  */
00966 static int myri10ge_net_open ( struct net_device *netdev )
00967 {
00968         const char              *dbg;   /* printed upon error return */
00969         int                      rc;
00970         struct io_buffer        *iob;
00971         struct myri10ge_private *priv;
00972         uint32                   data[3];
00973         struct pci_device       *pci_dev;
00974         void                    *membase;
00975 
00976         DBGP ( "myri10ge_net_open\n" );
00977         priv    = myri10ge_priv ( netdev );
00978         pci_dev = ( struct pci_device * ) netdev->dev;
00979         membase = phys_to_virt ( pci_dev->membase );
00980 
00981         /* Compute address for passing commands to the firmware. */
00982 
00983         priv->command = membase + MXGEFW_ETH_CMD;
00984 
00985         /* Ensure interrupts are disabled. */
00986 
00987         myri10ge_net_irq ( netdev, 0 );
00988 
00989         /* Allocate cleared DMAable buffers. */
00990 
00991         priv->dma = malloc_dma ( sizeof ( *priv->dma ) , 128 );
00992         if ( !priv->dma ) {
00993                 rc = -ENOMEM;
00994                 dbg = "DMA";
00995                 goto abort_with_nothing;
00996         }
00997         memset ( priv->dma, 0, sizeof ( *priv->dma ) );
00998 
00999         /* Simplify following code. */
01000 
01001 #define TRY( prefix, base, suffix ) do {                \
01002                 rc = myri10ge_command ( priv,           \
01003                                         MXGEFW_         \
01004                                         ## prefix       \
01005                                         ## base         \
01006                                         ## suffix,      \
01007                                         data );         \
01008                 if ( rc ) {                             \
01009                         dbg = #base;                    \
01010                         goto abort_with_dma;            \
01011                 }                                       \
01012         } while ( 0 )
01013 
01014         /* Send a reset command to the card to see if it is alive,
01015            and to reset its queue state. */
01016 
01017         TRY ( CMD_, RESET , );
01018 
01019         /* Set the interrupt queue size. */
01020 
01021         data[0] = ( (uint32_t)( sizeof ( priv->dma->receive_completion ) )
01022                     | MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK );
01023         TRY ( CMD_SET_ , INTRQ_SIZE , );
01024 
01025         /* Set the interrupt queue DMA address. */
01026 
01027         data[0] = virt_to_bus ( &priv->dma->receive_completion );
01028         data[1] = 0;
01029         TRY ( CMD_SET_, INTRQ_DMA, );
01030 
01031         /* Get the NIC interrupt claim address. */
01032 
01033         TRY ( CMD_GET_, IRQ_ACK, _OFFSET );
01034         priv->irq_claim = membase + data[0];
01035 
01036         /* Get the NIC interrupt assert address. */
01037 
01038         TRY ( CMD_GET_, IRQ_DEASSERT, _OFFSET );
01039         priv->irq_deassert = membase + data[0];
01040 
01041         /* Disable interrupt coalescing, which is inappropriate for the
01042            minimal buffering we provide. */
01043 
01044         TRY ( CMD_GET_, INTR_COAL, _DELAY_OFFSET );
01045         * ( ( uint32 * ) ( membase + data[0] ) ) = 0;
01046 
01047         /* Set the NIC mac address. */
01048 
01049         data[0] = ( netdev->ll_addr[0] << 24
01050                     | netdev->ll_addr[1] << 16
01051                     | netdev->ll_addr[2] << 8
01052                     | netdev->ll_addr[3] );
01053         data[1] = ( ( netdev->ll_addr[4] << 8 )
01054                      | netdev->ll_addr[5] );
01055         TRY ( SET_ , MAC_ADDRESS , );
01056 
01057         /* Enable multicast receives, because some iPXE clients don't work
01058            without multicast. . */
01059 
01060         TRY ( ENABLE_ , ALLMULTI , );
01061 
01062         /* Disable Ethernet flow control, so the NIC cannot deadlock the
01063            network under any circumstances. */
01064 
01065         TRY ( DISABLE_ , FLOW , _CONTROL );
01066 
01067         /* Compute transmit ring sizes. */
01068 
01069         data[0] = 0;            /* slice 0 */
01070         TRY ( CMD_GET_, SEND_RING, _SIZE );
01071         priv->transmit_ring_wrap
01072                 = data[0] / sizeof ( mcp_kreq_ether_send_t ) - 1;
01073         if ( priv->transmit_ring_wrap
01074              & ( priv->transmit_ring_wrap + 1 ) ) {
01075                 rc = -EPROTO;
01076                 dbg = "TX_RING";
01077                 goto abort_with_dma;
01078         }
01079 
01080         /* Compute receive ring sizes. */
01081 
01082         data[0] = 0;            /* slice 0 */
01083         TRY ( CMD_GET_ , RX_RING , _SIZE );
01084         priv->receive_post_ring_wrap = data[0] / sizeof ( mcp_dma_addr_t ) - 1;
01085         if ( priv->receive_post_ring_wrap
01086              & ( priv->receive_post_ring_wrap + 1 ) ) {
01087                 rc = -EPROTO;
01088                 dbg = "RX_RING";
01089                 goto abort_with_dma;
01090         }
01091 
01092         /* Get NIC transmit ring address. */
01093 
01094         data[0] = 0;            /* slice 0. */
01095         TRY ( CMD_GET_, SEND, _OFFSET );
01096         priv->transmit_ring = membase + data[0];
01097 
01098         /* Get the NIC receive ring address. */
01099 
01100         data[0] = 0;            /* slice 0. */
01101         TRY ( CMD_GET_, SMALL_RX, _OFFSET );
01102         priv->receive_post_ring = membase + data[0];
01103 
01104         /* Set the Nic MTU. */
01105 
01106         data[0] = ETH_FRAME_LEN;
01107         TRY ( CMD_SET_, MTU, );
01108 
01109         /* Tell the NIC our buffer sizes. ( We use only small buffers, so we
01110            set both buffer sizes to the same value, which will force all
01111            received frames to use small buffers. ) */
01112 
01113         data[0] = MXGEFW_PAD + ETH_FRAME_LEN;
01114         TRY ( CMD_SET_, SMALL_BUFFER, _SIZE );
01115         data[0] = MXGEFW_PAD + ETH_FRAME_LEN;
01116         TRY ( CMD_SET_, BIG_BUFFER, _SIZE );
01117 
01118         /* Tell firmware where to DMA IRQ data */
01119 
01120         data[0] = virt_to_bus ( &priv->dma->irq_data );
01121         data[1] = 0;
01122         data[2] = sizeof ( priv->dma->irq_data );
01123         TRY ( CMD_SET_, STATS_DMA_V2, );
01124 
01125         /* Post receives. */
01126 
01127         while ( priv->receives_posted <= MYRI10GE_RECEIVE_WRAP ) {
01128 
01129                 /* Reserve 2 extra bytes at the start of packets, since
01130                    the firmware always skips the first 2 bytes of the buffer
01131                    so TCP headers will be aligned. */
01132 
01133                 iob = alloc_iob ( MXGEFW_PAD + ETH_FRAME_LEN );
01134                 if ( !iob ) {
01135                         rc = -ENOMEM;
01136                         dbg = "alloc_iob";
01137                         goto abort_with_receives_posted;
01138                 }
01139                 iob_reserve ( iob, MXGEFW_PAD );
01140                 myri10ge_post_receive ( priv, iob );
01141         }
01142 
01143         /* Bring up the link. */
01144 
01145         TRY ( CMD_, ETHERNET_UP, );
01146 
01147         DBG2_RINGS ( priv );
01148         return 0;
01149 
01150 abort_with_receives_posted:
01151         while ( priv->receives_posted-- )
01152                 free_iob ( priv->receive_iob[priv->receives_posted] );
01153 abort_with_dma:
01154         /* Because the link is not up, we don't have to reset the NIC here. */
01155         free_dma ( priv->dma, sizeof ( *priv->dma ) );
01156 abort_with_nothing:
01157         /* Erase all signs of the failed open. */
01158         memset ( priv, 0, sizeof ( *priv ) );
01159         DBG ( "%s: %s\n", dbg, strerror ( rc ) );
01160         return ( rc );
01161 }
01162 
01163 /*
01164  * This function allows a driver to process events during operation.
01165  *
01166  * @v netdev            Device being polled.
01167  *
01168  * This is called periodically by iPXE to let the driver check the status of
01169  * transmitted packets and to allow the driver to check for received packets.
01170  * This is a iPXE Network Device Driver API function.
01171  */
01172 static void myri10ge_net_poll ( struct net_device *netdev )
01173 {
01174         struct io_buffer                *iob;
01175         struct io_buffer                *replacement;
01176         struct myri10ge_dma_buffers     *dma;
01177         struct myri10ge_private         *priv;
01178         unsigned int                     length;
01179         unsigned int                     orig_receives_posted;
01180 
01181         DBGP ( "myri10ge_net_poll\n" );
01182         priv = myri10ge_priv ( netdev );
01183         dma  = priv->dma;
01184 
01185         /* Process any pending interrupt. */
01186 
01187         myri10ge_interrupt_handler ( netdev );
01188 
01189         /* Pass up received frames, but limit ourselves to receives posted
01190            before this function was called, so we cannot livelock if
01191            receives are arriving faster than we process them. */
01192 
01193         orig_receives_posted = priv->receives_posted;
01194         while ( priv->receives_done != orig_receives_posted ) {
01195 
01196                 /* Stop if there is no pending receive. */
01197 
01198                 length = ntohs ( dma->receive_completion
01199                                  [priv->receives_done
01200                                   & MYRI10GE_RECEIVE_COMPLETION_WRAP]
01201                                  .length );
01202                 if ( length == 0 )
01203                         break;
01204 
01205                 /* Allocate a replacement buffer.  If none is available,
01206                    stop passing up packets until a buffer is available.
01207 
01208                    Reserve 2 extra bytes at the start of packets, since
01209                    the firmware always skips the first 2 bytes of the buffer
01210                    so TCP headers will be aligned. */
01211 
01212                 replacement = alloc_iob ( MXGEFW_PAD + ETH_FRAME_LEN );
01213                 if ( !replacement ) {
01214                         DBG ( "NO RX BUF\n" );
01215                         break;
01216                 }
01217                 iob_reserve ( replacement, MXGEFW_PAD );
01218 
01219                 /* Pass up the received frame. */
01220 
01221                 iob = priv->receive_iob[priv->receives_done
01222                                         & MYRI10GE_RECEIVE_WRAP];
01223                 iob_put ( iob, length );
01224                 netdev_rx ( netdev, iob );
01225 
01226                 /* We have consumed the packet, so clear the receive
01227                    notification. */
01228 
01229                 dma->receive_completion [priv->receives_done
01230                                          & MYRI10GE_RECEIVE_COMPLETION_WRAP]
01231                         .length = 0;
01232                 wmb();
01233 
01234                 /* Replace the passed-up I/O buffer. */
01235 
01236                 myri10ge_post_receive ( priv, replacement );
01237                 ++priv->receives_done;
01238                 DBG2_RINGS ( priv );
01239         }
01240 }
01241 
01242 /*
01243  * This transmits a packet.
01244  *
01245  * @v netdev            Device to transmit from.
01246  * @v iobuf             Data to transmit.
01247  * @ret rc              Non-zero if failed to transmit.
01248  *
01249  * This is a iPXE Network Driver API function.
01250  */
01251 static int myri10ge_net_transmit ( struct net_device *netdev,
01252                                    struct io_buffer *iobuf )
01253 {
01254         mcp_kreq_ether_send_t   *kreq;
01255         size_t                   len;
01256         struct myri10ge_private *priv;
01257         uint32                   transmits_posted;
01258 
01259         DBGP ( "myri10ge_net_transmit\n" );
01260         priv = myri10ge_priv ( netdev );
01261 
01262         /* Confirm space in the send ring. */
01263 
01264         transmits_posted = priv->transmits_posted;
01265         if ( transmits_posted - priv->transmits_done
01266              > MYRI10GE_TRANSMIT_WRAP ) {
01267                 DBG ( "TX ring full\n" );
01268                 return -ENOBUFS;
01269         }
01270 
01271         DBG2 ( "TX %p+%zd ", iobuf->data, iob_len ( iobuf ) );
01272         DBG2_HD ( iobuf->data, 14 );
01273 
01274         /* Record the packet being transmitted, so we can later report
01275            send completion. */
01276 
01277         priv->transmit_iob[transmits_posted & MYRI10GE_TRANSMIT_WRAP] = iobuf;
01278 
01279         /* Copy and pad undersized frames, because the NIC does not pad,
01280            and we would rather copy small frames than do a gather. */
01281 
01282         len = iob_len ( iobuf );
01283         if ( len < ETH_ZLEN ) {
01284                 iob_pad ( iobuf, ETH_ZLEN );
01285                 len = ETH_ZLEN;
01286         }
01287 
01288         /* Enqueue the packet by writing a descriptor to the NIC.
01289            This is a bit tricky because the HW requires 32-bit writes,
01290            but the structure has smaller fields. */
01291 
01292         kreq = &priv->transmit_ring[transmits_posted
01293                                     & priv->transmit_ring_wrap];
01294         kreq->addr_high = 0;
01295         kreq->addr_low = htonl ( virt_to_bus ( iobuf->data ) );
01296         ( ( uint32 * ) kreq ) [2] = htonl (
01297                 0x0000 << 16     /* pseudo_header_offset */
01298                 | ( len & 0xFFFF ) /* length */
01299                 );
01300         wmb();
01301         ( ( uint32 * ) kreq ) [3] = htonl (
01302                 0x00 << 24      /* pad */
01303                 | 0x01 << 16    /* rdma_count */
01304                 | 0x00 << 8     /* cksum_offset */
01305                 | ( MXGEFW_FLAGS_SMALL
01306                     | MXGEFW_FLAGS_FIRST
01307                     | MXGEFW_FLAGS_NO_TSO ) /* flags */
01308                 );
01309         wmb();
01310 
01311         /* Mark the slot as consumed and return. */
01312 
01313         priv->transmits_posted = ++transmits_posted;
01314         DBG2_RINGS ( priv );
01315         return 0;
01316 }
01317 
01318 static struct pci_device_id myri10ge_nics[] = {
01319         /* Each of these macros must be a single line to satisfy a script. */
01320         PCI_ROM ( 0x14c1, 0x0008, "myri10ge", "Myricom 10Gb Ethernet Adapter", 0 ) ,
01321 };
01322 
01323 struct pci_driver myri10ge_driver __pci_driver = {
01324         .ids      = myri10ge_nics,
01325         .id_count = ( sizeof ( myri10ge_nics ) / sizeof ( myri10ge_nics[0] ) ) ,
01326         .probe    = myri10ge_pci_probe,
01327         .remove   = myri10ge_pci_remove
01328 };
01329 
01330 /*
01331  * Local variables:
01332  *  c-basic-offset: 8
01333  *  c-indent-level: 8
01334  *  tab-width: 8
01335  * End:
01336  */