iPXE
realtek.c
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00001 /*
00002  * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
00003  *
00004  * (EEPROM code originally implemented for rtl8139.c)
00005  *
00006  * This program is free software; you can redistribute it and/or
00007  * modify it under the terms of the GNU General Public License as
00008  * published by the Free Software Foundation; either version 2 of the
00009  * License, or (at your option) any later version.
00010  *
00011  * This program is distributed in the hope that it will be useful, but
00012  * WITHOUT ANY WARRANTY; without even the implied warranty of
00013  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00014  * General Public License for more details.
00015  *
00016  * You should have received a copy of the GNU General Public License
00017  * along with this program; if not, write to the Free Software
00018  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00019  * 02110-1301, USA.
00020  *
00021  * You can also choose to distribute this program under the terms of
00022  * the Unmodified Binary Distribution Licence (as given in the file
00023  * COPYING.UBDL), provided that you have satisfied its requirements.
00024  */
00025 
00026 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
00027 
00028 #include <stdint.h>
00029 #include <string.h>
00030 #include <unistd.h>
00031 #include <errno.h>
00032 #include <byteswap.h>
00033 #include <ipxe/netdevice.h>
00034 #include <ipxe/ethernet.h>
00035 #include <ipxe/if_ether.h>
00036 #include <ipxe/iobuf.h>
00037 #include <ipxe/malloc.h>
00038 #include <ipxe/pci.h>
00039 #include <ipxe/nvs.h>
00040 #include <ipxe/threewire.h>
00041 #include <ipxe/bitbash.h>
00042 #include <ipxe/mii.h>
00043 #include "realtek.h"
00044 
00045 /** @file
00046  *
00047  * Realtek 10/100/1000 network card driver
00048  *
00049  * Based on the following datasheets:
00050  *
00051  *    http://www.datasheetarchive.com/dl/Datasheets-8/DSA-153536.pdf
00052  *    http://www.datasheetarchive.com/indexdl/Datasheet-028/DSA00494723.pdf
00053  */
00054 
00055 /******************************************************************************
00056  *
00057  * Debugging
00058  *
00059  ******************************************************************************
00060  */
00061 
00062 /**
00063  * Dump all registers (for debugging)
00064  *
00065  * @v rtl               Realtek device
00066  */
00067 static __attribute__ (( unused )) void realtek_dump ( struct realtek_nic *rtl ){
00068         uint8_t regs[256];
00069         unsigned int i;
00070 
00071         /* Do nothing unless debug output is enabled */
00072         if ( ! DBG_LOG )
00073                 return;
00074 
00075         /* Dump registers (via byte accesses; may not work for all registers) */
00076         for ( i = 0 ; i < sizeof ( regs ) ; i++ )
00077                 regs[i] = readb ( rtl->regs + i );
00078         DBGC ( rtl, "REALTEK %p register dump:\n", rtl );
00079         DBGC_HDA ( rtl, 0, regs, sizeof ( regs ) );
00080 }
00081 
00082 /******************************************************************************
00083  *
00084  * EEPROM interface
00085  *
00086  ******************************************************************************
00087  */
00088 
00089 /** Pin mapping for SPI bit-bashing interface */
00090 static const uint8_t realtek_eeprom_bits[] = {
00091         [SPI_BIT_SCLK]  = RTL_9346CR_EESK,
00092         [SPI_BIT_MOSI]  = RTL_9346CR_EEDI,
00093         [SPI_BIT_MISO]  = RTL_9346CR_EEDO,
00094         [SPI_BIT_SS(0)] = RTL_9346CR_EECS,
00095 };
00096 
00097 /**
00098  * Open bit-bashing interface
00099  *
00100  * @v basher            Bit-bashing interface
00101  */
00102 static void realtek_spi_open_bit ( struct bit_basher *basher ) {
00103         struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
00104                                                  spibit.basher );
00105 
00106         /* Enable EEPROM access */
00107         writeb ( RTL_9346CR_EEM_EEPROM, rtl->regs + RTL_9346CR );
00108         readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
00109 }
00110 
00111 /**
00112  * Close bit-bashing interface
00113  *
00114  * @v basher            Bit-bashing interface
00115  */
00116 static void realtek_spi_close_bit ( struct bit_basher *basher ) {
00117         struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
00118                                                  spibit.basher );
00119 
00120         /* Disable EEPROM access */
00121         writeb ( RTL_9346CR_EEM_NORMAL, rtl->regs + RTL_9346CR );
00122         readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
00123 }
00124 
00125 /**
00126  * Read input bit
00127  *
00128  * @v basher            Bit-bashing interface
00129  * @v bit_id            Bit number
00130  * @ret zero            Input is a logic 0
00131  * @ret non-zero        Input is a logic 1
00132  */
00133 static int realtek_spi_read_bit ( struct bit_basher *basher,
00134                                   unsigned int bit_id ) {
00135         struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
00136                                                  spibit.basher );
00137         uint8_t mask = realtek_eeprom_bits[bit_id];
00138         uint8_t reg;
00139 
00140         DBG_DISABLE ( DBGLVL_IO );
00141         reg = readb ( rtl->regs + RTL_9346CR );
00142         DBG_ENABLE ( DBGLVL_IO );
00143         return ( reg & mask );
00144 }
00145 
00146 /**
00147  * Set/clear output bit
00148  *
00149  * @v basher            Bit-bashing interface
00150  * @v bit_id            Bit number
00151  * @v data              Value to write
00152  */
00153 static void realtek_spi_write_bit ( struct bit_basher *basher,
00154                                     unsigned int bit_id, unsigned long data ) {
00155         struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
00156                                                  spibit.basher );
00157         uint8_t mask = realtek_eeprom_bits[bit_id];
00158         uint8_t reg;
00159 
00160         DBG_DISABLE ( DBGLVL_IO );
00161         reg = readb ( rtl->regs + RTL_9346CR );
00162         reg &= ~mask;
00163         reg |= ( data & mask );
00164         writeb ( reg, rtl->regs + RTL_9346CR );
00165         readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
00166         DBG_ENABLE ( DBGLVL_IO );
00167 }
00168 
00169 /** SPI bit-bashing interface */
00170 static struct bit_basher_operations realtek_basher_ops = {
00171         .open = realtek_spi_open_bit,
00172         .close = realtek_spi_close_bit,
00173         .read = realtek_spi_read_bit,
00174         .write = realtek_spi_write_bit,
00175 };
00176 
00177 /**
00178  * Initialise EEPROM
00179  *
00180  * @v netdev            Network device
00181  * @ret rc              Return status code
00182  */
00183 static int realtek_init_eeprom ( struct net_device *netdev ) {
00184         struct realtek_nic *rtl = netdev->priv;
00185         uint16_t id;
00186         int rc;
00187 
00188         /* Initialise SPI bit-bashing interface */
00189         rtl->spibit.basher.op = &realtek_basher_ops;
00190         rtl->spibit.bus.mode = SPI_MODE_THREEWIRE;
00191         init_spi_bit_basher ( &rtl->spibit );
00192 
00193         /* Detect EEPROM type and initialise three-wire device */
00194         if ( readl ( rtl->regs + RTL_RCR ) & RTL_RCR_9356SEL ) {
00195                 DBGC ( rtl, "REALTEK %p EEPROM is a 93C56\n", rtl );
00196                 init_at93c56 ( &rtl->eeprom, 16 );
00197         } else {
00198                 DBGC ( rtl, "REALTEK %p EEPROM is a 93C46\n", rtl );
00199                 init_at93c46 ( &rtl->eeprom, 16 );
00200         }
00201 
00202         /* Check for EEPROM presence.  Some onboard NICs will have no
00203          * EEPROM connected, with the BIOS being responsible for
00204          * programming the initial register values.
00205          */
00206         if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_ID,
00207                                &id, sizeof ( id ) ) ) != 0 ) {
00208                 DBGC ( rtl, "REALTEK %p could not read EEPROM ID: %s\n",
00209                        rtl, strerror ( rc ) );
00210                 return rc;
00211         }
00212         if ( id != cpu_to_le16 ( RTL_EEPROM_ID_MAGIC ) ) {
00213                 DBGC ( rtl, "REALTEK %p EEPROM ID incorrect (%#04x); assuming "
00214                        "no EEPROM\n", rtl, le16_to_cpu ( id ) );
00215                 return -ENODEV;
00216         }
00217 
00218         /* Initialise space for non-volatile options, if available
00219          *
00220          * We use offset 0x40 (i.e. address 0x20), length 0x40.  This
00221          * block is marked as VPD in the Realtek datasheets, so we use
00222          * it only if we detect that the card is not supporting VPD.
00223          */
00224         if ( readb ( rtl->regs + RTL_CONFIG1 ) & RTL_CONFIG1_VPD ) {
00225                 DBGC ( rtl, "REALTEK %p EEPROM in use for VPD; cannot use "
00226                        "for options\n", rtl );
00227         } else {
00228                 nvo_init ( &rtl->nvo, &rtl->eeprom.nvs, RTL_EEPROM_VPD,
00229                            RTL_EEPROM_VPD_LEN, NULL, &netdev->refcnt );
00230         }
00231 
00232         return 0;
00233 }
00234 
00235 /******************************************************************************
00236  *
00237  * MII interface
00238  *
00239  ******************************************************************************
00240  */
00241 
00242 /**
00243  * Read from MII register
00244  *
00245  * @v mdio              MII interface
00246  * @v phy               PHY address
00247  * @v reg               Register address
00248  * @ret value           Data read, or negative error
00249  */
00250 static int realtek_mii_read ( struct mii_interface *mdio,
00251                               unsigned int phy __unused, unsigned int reg ) {
00252         struct realtek_nic *rtl =
00253                 container_of ( mdio, struct realtek_nic, mdio );
00254         unsigned int i;
00255         uint32_t value;
00256 
00257         /* Fail if PHYAR register is not present */
00258         if ( ! rtl->have_phy_regs )
00259                 return -ENOTSUP;
00260 
00261         /* Initiate read */
00262         writel ( RTL_PHYAR_VALUE ( 0, reg, 0 ), rtl->regs + RTL_PHYAR );
00263 
00264         /* Wait for read to complete */
00265         for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
00266 
00267                 /* If read is not complete, delay 1us and retry */
00268                 value = readl ( rtl->regs + RTL_PHYAR );
00269                 if ( ! ( value & RTL_PHYAR_FLAG ) ) {
00270                         udelay ( 1 );
00271                         continue;
00272                 }
00273 
00274                 /* Return register value */
00275                 return ( RTL_PHYAR_DATA ( value ) );
00276         }
00277 
00278         DBGC ( rtl, "REALTEK %p timed out waiting for MII read\n", rtl );
00279         return -ETIMEDOUT;
00280 }
00281 
00282 /**
00283  * Write to MII register
00284  *
00285  * @v mdio              MII interface
00286  * @v phy               PHY address
00287  * @v reg               Register address
00288  * @v data              Data to write
00289  * @ret rc              Return status code
00290  */
00291 static int realtek_mii_write ( struct mii_interface *mdio,
00292                                unsigned int phy __unused, unsigned int reg,
00293                                unsigned int data ) {
00294         struct realtek_nic *rtl =
00295                 container_of ( mdio, struct realtek_nic, mdio );
00296         unsigned int i;
00297 
00298         /* Fail if PHYAR register is not present */
00299         if ( ! rtl->have_phy_regs )
00300                 return -ENOTSUP;
00301 
00302         /* Initiate write */
00303         writel ( RTL_PHYAR_VALUE ( RTL_PHYAR_FLAG, reg, data ),
00304                  rtl->regs + RTL_PHYAR );
00305 
00306         /* Wait for write to complete */
00307         for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
00308 
00309                 /* If write is not complete, delay 1us and retry */
00310                 if ( readl ( rtl->regs + RTL_PHYAR ) & RTL_PHYAR_FLAG ) {
00311                         udelay ( 1 );
00312                         continue;
00313                 }
00314 
00315                 return 0;
00316         }
00317 
00318         DBGC ( rtl, "REALTEK %p timed out waiting for MII write\n", rtl );
00319         return -ETIMEDOUT;
00320 }
00321 
00322 /** Realtek MII operations */
00323 static struct mii_operations realtek_mii_operations = {
00324         .read = realtek_mii_read,
00325         .write = realtek_mii_write,
00326 };
00327 
00328 /******************************************************************************
00329  *
00330  * Device reset
00331  *
00332  ******************************************************************************
00333  */
00334 
00335 /**
00336  * Reset hardware
00337  *
00338  * @v rtl               Realtek device
00339  * @ret rc              Return status code
00340  */
00341 static int realtek_reset ( struct realtek_nic *rtl ) {
00342         unsigned int i;
00343 
00344         /* Issue reset */
00345         writeb ( RTL_CR_RST, rtl->regs + RTL_CR );
00346 
00347         /* Wait for reset to complete */
00348         for ( i = 0 ; i < RTL_RESET_MAX_WAIT_MS ; i++ ) {
00349 
00350                 /* If reset is not complete, delay 1ms and retry */
00351                 if ( readb ( rtl->regs + RTL_CR ) & RTL_CR_RST ) {
00352                         mdelay ( 1 );
00353                         continue;
00354                 }
00355 
00356                 return 0;
00357         }
00358 
00359         DBGC ( rtl, "REALTEK %p timed out waiting for reset\n", rtl );
00360         return -ETIMEDOUT;
00361 }
00362 
00363 /**
00364  * Configure PHY for Gigabit operation
00365  *
00366  * @v rtl               Realtek device
00367  * @ret rc              Return status code
00368  */
00369 static int realtek_phy_speed ( struct realtek_nic *rtl ) {
00370         int ctrl1000;
00371         int rc;
00372 
00373         /* Read CTRL1000 register */
00374         ctrl1000 = mii_read ( &rtl->mii, MII_CTRL1000 );
00375         if ( ctrl1000 < 0 ) {
00376                 rc = ctrl1000;
00377                 DBGC ( rtl, "REALTEK %p could not read CTRL1000: %s\n",
00378                        rtl, strerror ( rc ) );
00379                 return rc;
00380         }
00381 
00382         /* Advertise 1000Mbps speeds */
00383         ctrl1000 |= ( ADVERTISE_1000FULL | ADVERTISE_1000HALF );
00384         if ( ( rc = mii_write ( &rtl->mii, MII_CTRL1000, ctrl1000 ) ) != 0 ) {
00385                 DBGC ( rtl, "REALTEK %p could not write CTRL1000: %s\n",
00386                        rtl, strerror ( rc ) );
00387                 return rc;
00388         }
00389 
00390         return 0;
00391 }
00392 
00393 /**
00394  * Reset PHY
00395  *
00396  * @v rtl               Realtek device
00397  * @ret rc              Return status code
00398  */
00399 static int realtek_phy_reset ( struct realtek_nic *rtl ) {
00400         int rc;
00401 
00402         /* Do nothing if we have no separate PHY register access */
00403         if ( ! rtl->have_phy_regs )
00404                 return 0;
00405 
00406         /* Perform MII reset */
00407         if ( ( rc = mii_reset ( &rtl->mii ) ) != 0 ) {
00408                 DBGC ( rtl, "REALTEK %p could not reset MII: %s\n",
00409                        rtl, strerror ( rc ) );
00410                 return rc;
00411         }
00412 
00413         /* Some cards (e.g. RTL8169SC) do not advertise Gigabit by
00414          * default.  Try to enable advertisement of Gigabit speeds.
00415          */
00416         if ( ( rc = realtek_phy_speed ( rtl ) ) != 0 ) {
00417                 /* Ignore failures, since the register may not be
00418                  * present on non-Gigabit PHYs (e.g. RTL8101).
00419                  */
00420         }
00421 
00422         /* Restart autonegotiation */
00423         if ( ( rc = mii_restart ( &rtl->mii ) ) != 0 ) {
00424                 DBGC ( rtl, "REALTEK %p could not restart MII: %s\n",
00425                        rtl, strerror ( rc ) );
00426                 return rc;
00427         }
00428 
00429         return 0;
00430 }
00431 
00432 /******************************************************************************
00433  *
00434  * Link state
00435  *
00436  ******************************************************************************
00437  */
00438 
00439 /**
00440  * Check link state
00441  *
00442  * @v netdev            Network device
00443  */
00444 static void realtek_check_link ( struct net_device *netdev ) {
00445         struct realtek_nic *rtl = netdev->priv;
00446         uint8_t phystatus;
00447         uint8_t msr;
00448         int link_up;
00449 
00450         /* Determine link state */
00451         if ( rtl->have_phy_regs ) {
00452                 mii_dump ( &rtl->mii );
00453                 phystatus = readb ( rtl->regs + RTL_PHYSTATUS );
00454                 link_up = ( phystatus & RTL_PHYSTATUS_LINKSTS );
00455                 DBGC ( rtl, "REALTEK %p PHY status is %02x (%s%s%s%s%s%s, "
00456                        "Link%s, %sDuplex)\n", rtl, phystatus,
00457                        ( ( phystatus & RTL_PHYSTATUS_ENTBI ) ? "TBI" : "GMII" ),
00458                        ( ( phystatus & RTL_PHYSTATUS_TXFLOW ) ?
00459                          ", TxFlow" : "" ),
00460                        ( ( phystatus & RTL_PHYSTATUS_RXFLOW ) ?
00461                          ", RxFlow" : "" ),
00462                        ( ( phystatus & RTL_PHYSTATUS_1000MF ) ?
00463                          ", 1000Mbps" : "" ),
00464                        ( ( phystatus & RTL_PHYSTATUS_100M ) ?
00465                          ", 100Mbps" : "" ),
00466                        ( ( phystatus & RTL_PHYSTATUS_10M ) ?
00467                          ", 10Mbps" : "" ),
00468                        ( ( phystatus & RTL_PHYSTATUS_LINKSTS ) ?
00469                          "Up" : "Down" ),
00470                        ( ( phystatus & RTL_PHYSTATUS_FULLDUP ) ?
00471                          "Full" : "Half" ) );
00472         } else {
00473                 msr = readb ( rtl->regs + RTL_MSR );
00474                 link_up = ( ! ( msr & RTL_MSR_LINKB ) );
00475                 DBGC ( rtl, "REALTEK %p media status is %02x (Link%s, "
00476                        "%dMbps%s%s%s%s%s)\n", rtl, msr,
00477                        ( ( msr & RTL_MSR_LINKB ) ? "Down" : "Up" ),
00478                        ( ( msr & RTL_MSR_SPEED_10 ) ? 10 : 100 ),
00479                        ( ( msr & RTL_MSR_TXFCE ) ? ", TxFlow" : "" ),
00480                        ( ( msr & RTL_MSR_RXFCE ) ? ", RxFlow" : "" ),
00481                        ( ( msr & RTL_MSR_AUX_STATUS ) ? ", AuxPwr" : "" ),
00482                        ( ( msr & RTL_MSR_TXPF ) ? ", TxPause" : "" ),
00483                        ( ( msr & RTL_MSR_RXPF ) ? ", RxPause" : "" ) );
00484         }
00485 
00486         /* Report link state */
00487         if ( link_up ) {
00488                 netdev_link_up ( netdev );
00489         } else {
00490                 netdev_link_down ( netdev );
00491         }
00492 }
00493 
00494 /******************************************************************************
00495  *
00496  * Network device interface
00497  *
00498  ******************************************************************************
00499  */
00500 
00501 /**
00502  * Create receive buffer (legacy mode)
00503  *
00504  * @v rtl               Realtek device
00505  * @ret rc              Return status code
00506  */
00507 static int realtek_create_buffer ( struct realtek_nic *rtl ) {
00508         size_t len = ( RTL_RXBUF_LEN + RTL_RXBUF_PAD );
00509         physaddr_t address;
00510         int rc;
00511 
00512         /* Do nothing unless in legacy mode */
00513         if ( ! rtl->legacy )
00514                 return 0;
00515 
00516         /* Allocate buffer */
00517         rtl->rx_buffer = malloc_dma ( len, RTL_RXBUF_ALIGN );
00518         if ( ! rtl->rx_buffer ) {
00519                 rc = -ENOMEM;
00520                 goto err_alloc;
00521         }
00522         address = virt_to_bus ( rtl->rx_buffer );
00523 
00524         /* Check that card can support address */
00525         if ( address & ~0xffffffffULL ) {
00526                 DBGC ( rtl, "REALTEK %p cannot support 64-bit RX buffer "
00527                        "address\n", rtl );
00528                 rc = -ENOTSUP;
00529                 goto err_64bit;
00530         }
00531 
00532         /* Program buffer address */
00533         writel ( address, rtl->regs + RTL_RBSTART );
00534         DBGC ( rtl, "REALTEK %p receive buffer is at [%08llx,%08llx,%08llx)\n",
00535                rtl, ( ( unsigned long long ) address ),
00536                ( ( unsigned long long ) address + RTL_RXBUF_LEN ),
00537                ( ( unsigned long long ) address + len ) );
00538 
00539         return 0;
00540 
00541  err_64bit:
00542         free_dma ( rtl->rx_buffer, len );
00543         rtl->rx_buffer = NULL;
00544  err_alloc:
00545         return rc;
00546 }
00547 
00548 /**
00549  * Destroy receive buffer (legacy mode)
00550  *
00551  * @v rtl               Realtek device
00552  */
00553 static void realtek_destroy_buffer ( struct realtek_nic *rtl ) {
00554         size_t len = ( RTL_RXBUF_LEN + RTL_RXBUF_PAD );
00555 
00556         /* Do nothing unless in legacy mode */
00557         if ( ! rtl->legacy )
00558                 return;
00559 
00560         /* Clear buffer address */
00561         writel ( 0, rtl->regs + RTL_RBSTART );
00562 
00563         /* Free buffer */
00564         free_dma ( rtl->rx_buffer, len );
00565         rtl->rx_buffer = NULL;
00566         rtl->rx_offset = 0;
00567 }
00568 
00569 /**
00570  * Create descriptor ring
00571  *
00572  * @v rtl               Realtek device
00573  * @v ring              Descriptor ring
00574  * @ret rc              Return status code
00575  */
00576 static int realtek_create_ring ( struct realtek_nic *rtl,
00577                                  struct realtek_ring *ring ) {
00578         physaddr_t address;
00579 
00580         /* Do nothing in legacy mode */
00581         if ( rtl->legacy )
00582                 return 0;
00583 
00584         /* Allocate descriptor ring */
00585         ring->desc = malloc_dma ( ring->len, RTL_RING_ALIGN );
00586         if ( ! ring->desc )
00587                 return -ENOMEM;
00588 
00589         /* Initialise descriptor ring */
00590         memset ( ring->desc, 0, ring->len );
00591 
00592         /* Program ring address */
00593         address = virt_to_bus ( ring->desc );
00594         writel ( ( ( ( uint64_t ) address ) >> 32 ),
00595                  rtl->regs + ring->reg + 4 );
00596         writel ( ( address & 0xffffffffUL ), rtl->regs + ring->reg );
00597         DBGC ( rtl, "REALTEK %p ring %02x is at [%08llx,%08llx)\n",
00598                rtl, ring->reg, ( ( unsigned long long ) address ),
00599                ( ( unsigned long long ) address + ring->len ) );
00600 
00601         return 0;
00602 }
00603 
00604 /**
00605  * Destroy descriptor ring
00606  *
00607  * @v rtl               Realtek device
00608  * @v ring              Descriptor ring
00609  */
00610 static void realtek_destroy_ring ( struct realtek_nic *rtl,
00611                                    struct realtek_ring *ring ) {
00612 
00613         /* Reset producer and consumer counters */
00614         ring->prod = 0;
00615         ring->cons = 0;
00616 
00617         /* Do nothing more if in legacy mode */
00618         if ( rtl->legacy )
00619                 return;
00620 
00621         /* Clear ring address */
00622         writel ( 0, rtl->regs + ring->reg );
00623         writel ( 0, rtl->regs + ring->reg + 4 );
00624 
00625         /* Free descriptor ring */
00626         free_dma ( ring->desc, ring->len );
00627         ring->desc = NULL;
00628 }
00629 
00630 /**
00631  * Refill receive descriptor ring
00632  *
00633  * @v rtl               Realtek device
00634  */
00635 static void realtek_refill_rx ( struct realtek_nic *rtl ) {
00636         struct realtek_descriptor *rx;
00637         struct io_buffer *iobuf;
00638         unsigned int rx_idx;
00639         physaddr_t address;
00640         int is_last;
00641 
00642         /* Do nothing in legacy mode */
00643         if ( rtl->legacy )
00644                 return;
00645 
00646         while ( ( rtl->rx.prod - rtl->rx.cons ) < RTL_NUM_RX_DESC ) {
00647 
00648                 /* Allocate I/O buffer */
00649                 iobuf = alloc_iob ( RTL_RX_MAX_LEN );
00650                 if ( ! iobuf ) {
00651                         /* Wait for next refill */
00652                         return;
00653                 }
00654 
00655                 /* Get next receive descriptor */
00656                 rx_idx = ( rtl->rx.prod++ % RTL_NUM_RX_DESC );
00657                 is_last = ( rx_idx == ( RTL_NUM_RX_DESC - 1 ) );
00658                 rx = &rtl->rx.desc[rx_idx];
00659 
00660                 /* Populate receive descriptor */
00661                 address = virt_to_bus ( iobuf->data );
00662                 rx->address = cpu_to_le64 ( address );
00663                 rx->length = cpu_to_le16 ( RTL_RX_MAX_LEN );
00664                 wmb();
00665                 rx->flags = ( cpu_to_le16 ( RTL_DESC_OWN ) |
00666                               ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
00667                 wmb();
00668 
00669                 /* Record I/O buffer */
00670                 assert ( rtl->rx_iobuf[rx_idx] == NULL );
00671                 rtl->rx_iobuf[rx_idx] = iobuf;
00672 
00673                 DBGC2 ( rtl, "REALTEK %p RX %d is [%llx,%llx)\n", rtl, rx_idx,
00674                         ( ( unsigned long long ) address ),
00675                         ( ( unsigned long long ) address + RTL_RX_MAX_LEN ) );
00676         }
00677 }
00678 
00679 /**
00680  * Open network device
00681  *
00682  * @v netdev            Network device
00683  * @ret rc              Return status code
00684  */
00685 static int realtek_open ( struct net_device *netdev ) {
00686         struct realtek_nic *rtl = netdev->priv;
00687         uint32_t tcr;
00688         uint32_t rcr;
00689         int rc;
00690 
00691         /* Create transmit descriptor ring */
00692         if ( ( rc = realtek_create_ring ( rtl, &rtl->tx ) ) != 0 )
00693                 goto err_create_tx;
00694 
00695         /* Create receive descriptor ring */
00696         if ( ( rc = realtek_create_ring ( rtl, &rtl->rx ) ) != 0 )
00697                 goto err_create_rx;
00698 
00699         /* Create receive buffer */
00700         if ( ( rc = realtek_create_buffer ( rtl ) ) != 0 )
00701                 goto err_create_buffer;
00702 
00703         /* Accept all packets */
00704         writel ( 0xffffffffUL, rtl->regs + RTL_MAR0 );
00705         writel ( 0xffffffffUL, rtl->regs + RTL_MAR4 );
00706 
00707         /* Enable transmitter and receiver.  RTL8139 requires that
00708          * this happens before writing to RCR.
00709          */
00710         writeb ( ( RTL_CR_TE | RTL_CR_RE ), rtl->regs + RTL_CR );
00711 
00712         /* Configure transmitter */
00713         tcr = readl ( rtl->regs + RTL_TCR );
00714         tcr &= ~RTL_TCR_MXDMA_MASK;
00715         tcr |= RTL_TCR_MXDMA_DEFAULT;
00716         writel ( tcr, rtl->regs + RTL_TCR );
00717 
00718         /* Configure receiver */
00719         rcr = readl ( rtl->regs + RTL_RCR );
00720         rcr &= ~( RTL_RCR_STOP_WORKING | RTL_RCR_RXFTH_MASK |
00721                   RTL_RCR_RBLEN_MASK | RTL_RCR_MXDMA_MASK );
00722         rcr |= ( RTL_RCR_RXFTH_DEFAULT | RTL_RCR_RBLEN_DEFAULT |
00723                  RTL_RCR_MXDMA_DEFAULT | RTL_RCR_WRAP | RTL_RCR_AB |
00724                  RTL_RCR_AM | RTL_RCR_APM | RTL_RCR_AAP );
00725         writel ( rcr, rtl->regs + RTL_RCR );
00726 
00727         /* Fill receive ring */
00728         realtek_refill_rx ( rtl );
00729 
00730         /* Update link state */
00731         realtek_check_link ( netdev );
00732 
00733         return 0;
00734 
00735         realtek_destroy_buffer ( rtl );
00736  err_create_buffer:
00737         realtek_destroy_ring ( rtl, &rtl->rx );
00738  err_create_rx:
00739         realtek_destroy_ring ( rtl, &rtl->tx );
00740  err_create_tx:
00741         return rc;
00742 }
00743 
00744 /**
00745  * Close network device
00746  *
00747  * @v netdev            Network device
00748  */
00749 static void realtek_close ( struct net_device *netdev ) {
00750         struct realtek_nic *rtl = netdev->priv;
00751         unsigned int i;
00752 
00753         /* Disable receiver and transmitter */
00754         writeb ( 0, rtl->regs + RTL_CR );
00755 
00756         /* Destroy receive buffer */
00757         realtek_destroy_buffer ( rtl );
00758 
00759         /* Destroy receive descriptor ring */
00760         realtek_destroy_ring ( rtl, &rtl->rx );
00761 
00762         /* Discard any unused receive buffers */
00763         for ( i = 0 ; i < RTL_NUM_RX_DESC ; i++ ) {
00764                 if ( rtl->rx_iobuf[i] )
00765                         free_iob ( rtl->rx_iobuf[i] );
00766                 rtl->rx_iobuf[i] = NULL;
00767         }
00768 
00769         /* Destroy transmit descriptor ring */
00770         realtek_destroy_ring ( rtl, &rtl->tx );
00771 }
00772 
00773 /**
00774  * Transmit packet
00775  *
00776  * @v netdev            Network device
00777  * @v iobuf             I/O buffer
00778  * @ret rc              Return status code
00779  */
00780 static int realtek_transmit ( struct net_device *netdev,
00781                               struct io_buffer *iobuf ) {
00782         struct realtek_nic *rtl = netdev->priv;
00783         struct realtek_descriptor *tx;
00784         unsigned int tx_idx;
00785         physaddr_t address;
00786         int is_last;
00787 
00788         /* Get next transmit descriptor */
00789         if ( ( rtl->tx.prod - rtl->tx.cons ) >= RTL_NUM_TX_DESC ) {
00790                 netdev_tx_defer ( netdev, iobuf );
00791                 return 0;
00792         }
00793         tx_idx = ( rtl->tx.prod++ % RTL_NUM_TX_DESC );
00794 
00795         /* Transmit packet */
00796         if ( rtl->legacy ) {
00797 
00798                 /* Pad and align packet */
00799                 iob_pad ( iobuf, ETH_ZLEN );
00800                 address = virt_to_bus ( iobuf->data );
00801 
00802                 /* Check that card can support address */
00803                 if ( address & ~0xffffffffULL ) {
00804                         DBGC ( rtl, "REALTEK %p cannot support 64-bit TX "
00805                                "buffer address\n", rtl );
00806                         return -ENOTSUP;
00807                 }
00808 
00809                 /* Add to transmit ring */
00810                 writel ( address, rtl->regs + RTL_TSAD ( tx_idx ) );
00811                 writel ( ( RTL_TSD_ERTXTH_DEFAULT | iob_len ( iobuf ) ),
00812                          rtl->regs + RTL_TSD ( tx_idx ) );
00813 
00814         } else {
00815 
00816                 /* Populate transmit descriptor */
00817                 address = virt_to_bus ( iobuf->data );
00818                 is_last = ( tx_idx == ( RTL_NUM_TX_DESC - 1 ) );
00819                 tx = &rtl->tx.desc[tx_idx];
00820                 tx->address = cpu_to_le64 ( address );
00821                 tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
00822                 wmb();
00823                 tx->flags = ( cpu_to_le16 ( RTL_DESC_OWN | RTL_DESC_FS |
00824                                             RTL_DESC_LS ) |
00825                               ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
00826                 wmb();
00827 
00828                 /* Notify card that there are packets ready to transmit */
00829                 writeb ( RTL_TPPOLL_NPQ, rtl->regs + rtl->tppoll );
00830         }
00831 
00832         DBGC2 ( rtl, "REALTEK %p TX %d is [%llx,%llx)\n", rtl, tx_idx,
00833                 ( ( unsigned long long ) virt_to_bus ( iobuf->data ) ),
00834                 ( ( ( unsigned long long ) virt_to_bus ( iobuf->data ) ) +
00835                   iob_len ( iobuf ) ) );
00836 
00837         return 0;
00838 }
00839 
00840 /**
00841  * Poll for completed packets
00842  *
00843  * @v netdev            Network device
00844  */
00845 static void realtek_poll_tx ( struct net_device *netdev ) {
00846         struct realtek_nic *rtl = netdev->priv;
00847         struct realtek_descriptor *tx;
00848         unsigned int tx_idx;
00849 
00850         /* Check for completed packets */
00851         while ( rtl->tx.cons != rtl->tx.prod ) {
00852 
00853                 /* Get next transmit descriptor */
00854                 tx_idx = ( rtl->tx.cons % RTL_NUM_TX_DESC );
00855 
00856                 /* Stop if descriptor is still in use */
00857                 if ( rtl->legacy ) {
00858 
00859                         /* Check ownership bit in transmit status register */
00860                         if ( ! ( readl ( rtl->regs + RTL_TSD ( tx_idx ) ) &
00861                                  RTL_TSD_OWN ) )
00862                                 return;
00863 
00864                 } else {
00865 
00866                         /* Check ownership bit in descriptor */
00867                         tx = &rtl->tx.desc[tx_idx];
00868                         if ( tx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
00869                                 return;
00870                 }
00871 
00872                 DBGC2 ( rtl, "REALTEK %p TX %d complete\n", rtl, tx_idx );
00873 
00874                 /* Complete TX descriptor */
00875                 rtl->tx.cons++;
00876                 netdev_tx_complete_next ( netdev );
00877         }
00878 }
00879 
00880 /**
00881  * Poll for received packets (legacy mode)
00882  *
00883  * @v netdev            Network device
00884  */
00885 static void realtek_legacy_poll_rx ( struct net_device *netdev ) {
00886         struct realtek_nic *rtl = netdev->priv;
00887         struct realtek_legacy_header *rx;
00888         struct io_buffer *iobuf;
00889         size_t len;
00890 
00891         /* Check for received packets */
00892         while ( ! ( readb ( rtl->regs + RTL_CR ) & RTL_CR_BUFE ) ) {
00893 
00894                 /* Extract packet from receive buffer */
00895                 rx = ( rtl->rx_buffer + rtl->rx_offset );
00896                 len = le16_to_cpu ( rx->length );
00897                 if ( rx->status & cpu_to_le16 ( RTL_STAT_ROK ) ) {
00898 
00899                         DBGC2 ( rtl, "REALTEK %p RX offset %x+%zx\n",
00900                                 rtl, rtl->rx_offset, len );
00901 
00902                         /* Allocate I/O buffer */
00903                         iobuf = alloc_iob ( len );
00904                         if ( ! iobuf ) {
00905                                 netdev_rx_err ( netdev, NULL, -ENOMEM );
00906                                 /* Leave packet for next poll */
00907                                 break;
00908                         }
00909 
00910                         /* Copy data to I/O buffer */
00911                         memcpy ( iob_put ( iobuf, len ), rx->data, len );
00912                         iob_unput ( iobuf, 4 /* strip CRC */ );
00913 
00914                         /* Hand off to network stack */
00915                         netdev_rx ( netdev, iobuf );
00916 
00917                 } else {
00918 
00919                         DBGC ( rtl, "REALTEK %p RX offset %x+%zx error %04x\n",
00920                                rtl, rtl->rx_offset, len,
00921                                le16_to_cpu ( rx->status ) );
00922                         netdev_rx_err ( netdev, NULL, -EIO );
00923                 }
00924 
00925                 /* Update buffer offset */
00926                 rtl->rx_offset = ( rtl->rx_offset + sizeof ( *rx ) + len );
00927                 rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 );
00928                 rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN );
00929                 writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR );
00930 
00931                 /* Give chip time to react before rechecking RTL_CR */
00932                 readw ( rtl->regs + RTL_CAPR );
00933         }
00934 }
00935 
00936 /**
00937  * Poll for received packets
00938  *
00939  * @v netdev            Network device
00940  */
00941 static void realtek_poll_rx ( struct net_device *netdev ) {
00942         struct realtek_nic *rtl = netdev->priv;
00943         struct realtek_descriptor *rx;
00944         struct io_buffer *iobuf;
00945         unsigned int rx_idx;
00946         size_t len;
00947 
00948         /* Poll receive buffer if in legacy mode */
00949         if ( rtl->legacy ) {
00950                 realtek_legacy_poll_rx ( netdev );
00951                 return;
00952         }
00953 
00954         /* Check for received packets */
00955         while ( rtl->rx.cons != rtl->rx.prod ) {
00956 
00957                 /* Get next receive descriptor */
00958                 rx_idx = ( rtl->rx.cons % RTL_NUM_RX_DESC );
00959                 rx = &rtl->rx.desc[rx_idx];
00960 
00961                 /* Stop if descriptor is still in use */
00962                 if ( rx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
00963                         return;
00964 
00965                 /* Populate I/O buffer */
00966                 iobuf = rtl->rx_iobuf[rx_idx];
00967                 rtl->rx_iobuf[rx_idx] = NULL;
00968                 len = ( le16_to_cpu ( rx->length ) & RTL_DESC_SIZE_MASK );
00969                 iob_put ( iobuf, ( len - 4 /* strip CRC */ ) );
00970 
00971                 /* Hand off to network stack */
00972                 if ( rx->flags & cpu_to_le16 ( RTL_DESC_RES ) ) {
00973                         DBGC ( rtl, "REALTEK %p RX %d error (length %zd, "
00974                                "flags %04x)\n", rtl, rx_idx, len,
00975                                le16_to_cpu ( rx->flags ) );
00976                         netdev_rx_err ( netdev, iobuf, -EIO );
00977                 } else {
00978                         DBGC2 ( rtl, "REALTEK %p RX %d complete (length "
00979                                 "%zd)\n", rtl, rx_idx, len );
00980                         netdev_rx ( netdev, iobuf );
00981                 }
00982                 rtl->rx.cons++;
00983         }
00984 }
00985 
00986 /**
00987  * Poll for completed and received packets
00988  *
00989  * @v netdev            Network device
00990  */
00991 static void realtek_poll ( struct net_device *netdev ) {
00992         struct realtek_nic *rtl = netdev->priv;
00993         uint16_t isr;
00994 
00995         /* Check for and acknowledge interrupts */
00996         isr = readw ( rtl->regs + RTL_ISR );
00997         if ( ! isr )
00998                 return;
00999         writew ( isr, rtl->regs + RTL_ISR );
01000 
01001         /* Poll for TX completions, if applicable */
01002         if ( isr & ( RTL_IRQ_TER | RTL_IRQ_TOK ) )
01003                 realtek_poll_tx ( netdev );
01004 
01005         /* Poll for RX completionsm, if applicable */
01006         if ( isr & ( RTL_IRQ_RER | RTL_IRQ_ROK ) )
01007                 realtek_poll_rx ( netdev );
01008 
01009         /* Check link state, if applicable */
01010         if ( isr & RTL_IRQ_PUN_LINKCHG )
01011                 realtek_check_link ( netdev );
01012 
01013         /* Refill RX ring */
01014         realtek_refill_rx ( rtl );
01015 }
01016 
01017 /**
01018  * Enable or disable interrupts
01019  *
01020  * @v netdev            Network device
01021  * @v enable            Interrupts should be enabled
01022  */
01023 static void realtek_irq ( struct net_device *netdev, int enable ) {
01024         struct realtek_nic *rtl = netdev->priv;
01025         uint16_t imr;
01026 
01027         /* Set interrupt mask */
01028         imr = ( enable ? ( RTL_IRQ_PUN_LINKCHG | RTL_IRQ_TER | RTL_IRQ_TOK |
01029                            RTL_IRQ_RER | RTL_IRQ_ROK ) : 0 );
01030         writew ( imr, rtl->regs + RTL_IMR );
01031 }
01032 
01033 /** Realtek network device operations */
01034 static struct net_device_operations realtek_operations = {
01035         .open           = realtek_open,
01036         .close          = realtek_close,
01037         .transmit       = realtek_transmit,
01038         .poll           = realtek_poll,
01039         .irq            = realtek_irq,
01040 };
01041 
01042 /******************************************************************************
01043  *
01044  * PCI interface
01045  *
01046  ******************************************************************************
01047  */
01048 
01049 /**
01050  * Detect device type
01051  *
01052  * @v rtl               Realtek device
01053  */
01054 static void realtek_detect ( struct realtek_nic *rtl ) {
01055         uint16_t rms;
01056         uint16_t check_rms;
01057         uint16_t cpcr;
01058         uint16_t check_cpcr;
01059 
01060         /* The RX Packet Maximum Size register is present only on
01061          * 8169.  Try to set to our intended MTU.
01062          */
01063         rms = RTL_RX_MAX_LEN;
01064         writew ( rms, rtl->regs + RTL_RMS );
01065         check_rms = readw ( rtl->regs + RTL_RMS );
01066 
01067         /* The C+ Command register is present only on 8169 and 8139C+.
01068          * Try to enable C+ mode and PCI Dual Address Cycle (for
01069          * 64-bit systems), if supported.
01070          *
01071          * Note that enabling DAC seems to cause bizarre behaviour
01072          * (lockups, garbage data on the wire) on some systems, even
01073          * if only 32-bit addresses are used.
01074          */
01075         cpcr = readw ( rtl->regs + RTL_CPCR );
01076         cpcr |= ( RTL_CPCR_MULRW | RTL_CPCR_CPRX | RTL_CPCR_CPTX );
01077         if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) )
01078                 cpcr |= RTL_CPCR_DAC;
01079         writew ( cpcr, rtl->regs + RTL_CPCR );
01080         check_cpcr = readw ( rtl->regs + RTL_CPCR );
01081 
01082         /* Detect device type */
01083         if ( check_rms == rms ) {
01084                 DBGC ( rtl, "REALTEK %p appears to be an RTL8169\n", rtl );
01085                 rtl->have_phy_regs = 1;
01086                 rtl->tppoll = RTL_TPPOLL_8169;
01087         } else {
01088                 if ( ( check_cpcr == cpcr ) && ( cpcr != 0xffff ) ) {
01089                         DBGC ( rtl, "REALTEK %p appears to be an RTL8139C+\n",
01090                                rtl );
01091                         rtl->tppoll = RTL_TPPOLL_8139CP;
01092                 } else {
01093                         DBGC ( rtl, "REALTEK %p appears to be an RTL8139\n",
01094                                rtl );
01095                         rtl->legacy = 1;
01096                 }
01097                 rtl->eeprom.bus = &rtl->spibit.bus;
01098         }
01099 }
01100 
01101 /**
01102  * Probe PCI device
01103  *
01104  * @v pci               PCI device
01105  * @ret rc              Return status code
01106  */
01107 static int realtek_probe ( struct pci_device *pci ) {
01108         struct net_device *netdev;
01109         struct realtek_nic *rtl;
01110         unsigned int i;
01111         int rc;
01112 
01113         /* Allocate and initialise net device */
01114         netdev = alloc_etherdev ( sizeof ( *rtl ) );
01115         if ( ! netdev ) {
01116                 rc = -ENOMEM;
01117                 goto err_alloc;
01118         }
01119         netdev_init ( netdev, &realtek_operations );
01120         rtl = netdev->priv;
01121         pci_set_drvdata ( pci, netdev );
01122         netdev->dev = &pci->dev;
01123         memset ( rtl, 0, sizeof ( *rtl ) );
01124         realtek_init_ring ( &rtl->tx, RTL_NUM_TX_DESC, RTL_TNPDS );
01125         realtek_init_ring ( &rtl->rx, RTL_NUM_RX_DESC, RTL_RDSAR );
01126 
01127         /* Fix up PCI device */
01128         adjust_pci_device ( pci );
01129 
01130         /* Map registers */
01131         rtl->regs = ioremap ( pci->membase, RTL_BAR_SIZE );
01132         if ( ! rtl->regs ) {
01133                 rc = -ENODEV;
01134                 goto err_ioremap;
01135         }
01136 
01137         /* Reset the NIC */
01138         if ( ( rc = realtek_reset ( rtl ) ) != 0 )
01139                 goto err_reset;
01140 
01141         /* Detect device type */
01142         realtek_detect ( rtl );
01143 
01144         /* Initialise EEPROM */
01145         if ( rtl->eeprom.bus &&
01146              ( ( rc = realtek_init_eeprom ( netdev ) ) == 0 ) ) {
01147 
01148                 /* Read MAC address from EEPROM */
01149                 if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_MAC,
01150                                        netdev->hw_addr, ETH_ALEN ) ) != 0 ) {
01151                         DBGC ( rtl, "REALTEK %p could not read MAC address: "
01152                                "%s\n", rtl, strerror ( rc ) );
01153                         goto err_nvs_read;
01154                 }
01155 
01156         } else {
01157 
01158                 /* EEPROM not present.  Fall back to reading the
01159                  * current ID register value, which will hopefully
01160                  * have been programmed by the platform firmware.
01161                  */
01162                 for ( i = 0 ; i < ETH_ALEN ; i++ )
01163                         netdev->hw_addr[i] = readb ( rtl->regs + RTL_IDR0 + i );
01164         }
01165 
01166         /* Initialise and reset MII interface */
01167         mdio_init ( &rtl->mdio, &realtek_mii_operations );
01168         mii_init ( &rtl->mii, &rtl->mdio, 0 );
01169         if ( ( rc = realtek_phy_reset ( rtl ) ) != 0 )
01170                 goto err_phy_reset;
01171 
01172         /* Register network device */
01173         if ( ( rc = register_netdev ( netdev ) ) != 0 )
01174                 goto err_register_netdev;
01175 
01176         /* Set initial link state */
01177         realtek_check_link ( netdev );
01178 
01179         /* Register non-volatile options, if applicable */
01180         if ( rtl->nvo.nvs ) {
01181                 if ( ( rc = register_nvo ( &rtl->nvo,
01182                                            netdev_settings ( netdev ) ) ) != 0)
01183                         goto err_register_nvo;
01184         }
01185 
01186         return 0;
01187 
01188  err_register_nvo:
01189         unregister_netdev ( netdev );
01190  err_register_netdev:
01191  err_phy_reset:
01192  err_nvs_read:
01193         realtek_reset ( rtl );
01194  err_reset:
01195         iounmap ( rtl->regs );
01196  err_ioremap:
01197         netdev_nullify ( netdev );
01198         netdev_put ( netdev );
01199  err_alloc:
01200         return rc;
01201 }
01202 
01203 /**
01204  * Remove PCI device
01205  *
01206  * @v pci               PCI device
01207  */
01208 static void realtek_remove ( struct pci_device *pci ) {
01209         struct net_device *netdev = pci_get_drvdata ( pci );
01210         struct realtek_nic *rtl = netdev->priv;
01211 
01212         /* Unregister non-volatile options, if applicable */
01213         if ( rtl->nvo.nvs )
01214                 unregister_nvo ( &rtl->nvo );
01215 
01216         /* Unregister network device */
01217         unregister_netdev ( netdev );
01218 
01219         /* Reset card */
01220         realtek_reset ( rtl );
01221 
01222         /* Free network device */
01223         iounmap ( rtl->regs );
01224         netdev_nullify ( netdev );
01225         netdev_put ( netdev );
01226 }
01227 
01228 /** Realtek PCI device IDs */
01229 static struct pci_device_id realtek_nics[] = {
01230         PCI_ROM ( 0x0001, 0x8168, "clone8169",  "Cloned 8169", 0 ),
01231         PCI_ROM ( 0x018a, 0x0106, "fpc0106tx",  "LevelOne FPC-0106TX", 0 ),
01232         PCI_ROM ( 0x021b, 0x8139, "hne300",     "Compaq HNE-300", 0 ),
01233         PCI_ROM ( 0x02ac, 0x1012, "s1012",      "SpeedStream 1012", 0 ),
01234         PCI_ROM ( 0x0357, 0x000a, "ttpmon",     "TTTech TTP-Monitoring", 0 ),
01235         PCI_ROM ( 0x10ec, 0x8129, "rtl8129",    "RTL-8129", 0 ),
01236         PCI_ROM ( 0x10ec, 0x8136, "rtl8136",    "RTL8101E/RTL8102E", 0 ),
01237         PCI_ROM ( 0x10ec, 0x8138, "rtl8138",    "RT8139 (B/C)", 0 ),
01238         PCI_ROM ( 0x10ec, 0x8139, "rtl8139",    "RTL-8139/8139C/8139C+", 0 ),
01239         PCI_ROM ( 0x10ec, 0x8167, "rtl8167",    "RTL-8110SC/8169SC", 0 ),
01240         PCI_ROM ( 0x10ec, 0x8168, "rtl8168",    "RTL8111/8168B", 0 ),
01241         PCI_ROM ( 0x10ec, 0x8169, "rtl8169",    "RTL-8169", 0 ),
01242         PCI_ROM ( 0x1113, 0x1211, "smc1211",    "SMC2-1211TX", 0 ),
01243         PCI_ROM ( 0x1186, 0x1300, "dfe538",     "DFE530TX+/DFE538TX", 0 ),
01244         PCI_ROM ( 0x1186, 0x1340, "dfe690",     "DFE-690TXD", 0 ),
01245         PCI_ROM ( 0x1186, 0x4300, "dge528t",    "DGE-528T", 0 ),
01246         PCI_ROM ( 0x11db, 0x1234, "sega8139",   "Sega Enterprises 8139", 0 ),
01247         PCI_ROM ( 0x1259, 0xa117, "allied8139", "Allied Telesyn 8139", 0 ),
01248         PCI_ROM ( 0x1259, 0xa11e, "allied81xx", "Allied Telesyn 81xx", 0 ),
01249         PCI_ROM ( 0x1259, 0xc107, "allied8169", "Allied Telesyn 8169", 0 ),
01250         PCI_ROM ( 0x126c, 0x1211, "northen8139","Northern Telecom 8139", 0 ),
01251         PCI_ROM ( 0x13d1, 0xab06, "fe2000vx",   "Abocom FE2000VX", 0 ),
01252         PCI_ROM ( 0x1432, 0x9130, "edi8139",    "Edimax 8139", 0 ),
01253         PCI_ROM ( 0x14ea, 0xab06, "fnw3603tx",  "Planex FNW-3603-TX", 0 ),
01254         PCI_ROM ( 0x14ea, 0xab07, "fnw3800tx",  "Planex FNW-3800-TX", 0 ),
01255         PCI_ROM ( 0x1500, 0x1360, "delta8139",  "Delta Electronics 8139", 0 ),
01256         PCI_ROM ( 0x16ec, 0x0116, "usr997902",  "USR997902", 0 ),
01257         PCI_ROM ( 0x1737, 0x1032, "linksys8169","Linksys 8169", 0 ),
01258         PCI_ROM ( 0x1743, 0x8139, "rolf100",    "Peppercorn ROL/F-100", 0 ),
01259         PCI_ROM ( 0x4033, 0x1360, "addron8139", "Addtron 8139", 0 ),
01260         PCI_ROM ( 0xffff, 0x8139, "clonse8139", "Cloned 8139", 0 ),
01261 };
01262 
01263 /** Realtek PCI driver */
01264 struct pci_driver realtek_driver __pci_driver = {
01265         .ids = realtek_nics,
01266         .id_count = ( sizeof ( realtek_nics ) / sizeof ( realtek_nics[0] ) ),
01267         .probe = realtek_probe,
01268         .remove = realtek_remove,
01269 };