iPXE
epic100.c
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1 
2 /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
3 
4 FILE_LICENCE ( GPL2_OR_LATER );
5 
6 /* 05/06/2003 timlegge Fixed relocation and implemented Multicast */
7 #define LINUX_OUT_MACROS
8 
9 #include "etherboot.h"
10 #include <ipxe/pci.h>
11 #include <ipxe/ethernet.h>
12 #include "nic.h"
13 #include "epic100.h"
14 
15 /* Condensed operations for readability */
16 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
17 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
18 
19 #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
20 #define RX_RING_SIZE 2
21 
22 #define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/
23 
24 /*
25 #define DEBUG_RX
26 #define DEBUG_TX
27 #define DEBUG_EEPROM
28 */
29 
30 #define EPIC_DEBUG 0 /* debug level */
31 
32 /* The EPIC100 Rx and Tx buffer descriptors. */
33 struct epic_rx_desc {
34  unsigned long status;
35  unsigned long bufaddr;
36  unsigned long buflength;
37  unsigned long next;
38 };
39 /* description of the tx descriptors control bits commonly used */
40 #define TD_STDFLAGS TD_LASTDESC
41 
42 struct epic_tx_desc {
43  unsigned long status;
44  unsigned long bufaddr;
45  unsigned long buflength;
46  unsigned long next;
47 };
48 
49 #define delay(nanosec) do { int _i = 3; while (--_i > 0) \
50  { __SLOW_DOWN_IO; }} while (0)
51 
52 static void epic100_open(void);
53 static void epic100_init_ring(void);
54 static void epic100_disable(struct nic *nic);
55 static int epic100_poll(struct nic *nic, int retrieve);
56 static void epic100_transmit(struct nic *nic, const char *destaddr,
57  unsigned int type, unsigned int len, const char *data);
58 #ifdef DEBUG_EEPROM
59 static int read_eeprom(int location);
60 #endif
61 static int mii_read(int phy_id, int location);
62 static void epic100_irq(struct nic *nic, irq_action_t action);
63 
65 
66 static int ioaddr;
67 
68 static int command;
69 static int intstat;
70 static int intmask;
71 static int genctl ;
72 static int eectl ;
73 static int test ;
74 static int mmctl ;
75 static int mmdata ;
76 static int lan0 ;
77 static int mc0 ;
78 static int rxcon ;
79 static int txcon ;
80 static int prcdar ;
81 static int ptcdar ;
82 static int eththr ;
83 
84 static unsigned int cur_rx, cur_tx; /* The next free ring entry */
85 #ifdef DEBUG_EEPROM
86 static unsigned short eeprom[64];
87 #endif
88 static signed char phys[4]; /* MII device addresses. */
89 struct {
91  __attribute__ ((aligned(4)));
93  __attribute__ ((aligned(4)));
94  unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
95  unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
96 } epic100_bufs __shared;
97 #define rx_ring epic100_bufs.rx_ring
98 #define tx_ring epic100_bufs.tx_ring
99 #define rx_packet epic100_bufs.rx_packet
100 #define tx_packet epic100_bufs.tx_packet
101 
102 /***********************************************************************/
103 /* Externally visible functions */
104 /***********************************************************************/
105 
106 
107 static int
108 epic100_probe ( struct nic *nic, struct pci_device *pci ) {
109 
110  int i;
111  unsigned short* ap;
112  unsigned int phy, phy_idx;
113 
114  if (pci->ioaddr == 0)
115  return 0;
116 
117  /* Ideally we would detect all network cards in slot order. That would
118  be best done a central PCI probe dispatch, which wouldn't work
119  well with the current structure. So instead we detect just the
120  Epic cards in slot order. */
121 
122  ioaddr = pci->ioaddr;
123 
124  nic->irqno = 0;
125  nic->ioaddr = pci->ioaddr & ~3;
126 
127  /* compute all used static epic100 registers address */
128  command = ioaddr + COMMAND; /* Control Register */
129  intstat = ioaddr + INTSTAT; /* Interrupt Status */
130  intmask = ioaddr + INTMASK; /* Interrupt Mask */
131  genctl = ioaddr + GENCTL; /* General Control */
132  eectl = ioaddr + EECTL; /* EEPROM Control */
133  test = ioaddr + TEST; /* Test register (clocks) */
134  mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
135  mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
136  lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
137  mc0 = ioaddr + MC0; /* Multicast Control */
138  rxcon = ioaddr + RXCON; /* Receive Control */
139  txcon = ioaddr + TXCON; /* Transmit Control */
140  prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
141  ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
142  eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
143 
144  /* Reset the chip & bring it out of low-power mode. */
146 
147  /* Disable ALL interrupts by setting the interrupt mask. */
149 
150  /*
151  * set the internal clocks:
152  * Application Note 7.15 says:
153  * In order to set the CLOCK TEST bit in the TEST register,
154  * perform the following:
155  *
156  * Write 0x0008 to the test register at least sixteen
157  * consecutive times.
158  *
159  * The CLOCK TEST bit is Write-Only. Writing it several times
160  * consecutively insures a successful write to the bit...
161  */
162 
163  for (i = 0; i < 16; i++) {
164  outl(0x00000008, test);
165  }
166 
167 #ifdef DEBUG_EEPROM
168 {
169  unsigned short sum = 0;
170  unsigned short value;
171  for (i = 0; i < 64; i++) {
172  value = read_eeprom(i);
173  eeprom[i] = value;
174  sum += value;
175  }
176 }
177 
178 #if (EPIC_DEBUG > 1)
179  printf("EEPROM contents\n");
180  for (i = 0; i < 64; i++) {
181  printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
182  }
183 #endif
184 #endif
185 
186  /* This could also be read from the EEPROM. */
187  ap = (unsigned short*)nic->node_addr;
188  for (i = 0; i < 3; i++)
189  *ap++ = inw(lan0 + i*4);
190 
191  DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
192 
193  /* Find the connected MII xcvrs. */
194  for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
195  int mii_status = mii_read(phy, 0);
196 
197  if (mii_status != 0xffff && mii_status != 0x0000) {
198  phys[phy_idx++] = phy;
199 #if (EPIC_DEBUG > 1)
200  printf("MII transceiver found at address %d.\n", phy);
201 #endif
202  }
203  }
204  if (phy_idx == 0) {
205 #if (EPIC_DEBUG > 1)
206  printf("***WARNING***: No MII transceiver found!\n");
207 #endif
208  /* Use the known PHY address of the EPII. */
209  phys[0] = 3;
210  }
211 
212  epic100_open();
214 
215  return 1;
216 }
217 
218 static void set_rx_mode(void)
219 {
220  unsigned char mc_filter[8];
221  int i;
222  memset(mc_filter, 0xff, sizeof(mc_filter));
223  outl(0x0C, rxcon);
224  for(i = 0; i < 4; i++)
225  outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
226  return;
227 }
228 
229  static void
231 {
232  int mii_reg5;
233  unsigned long tmp;
234 
236 
237  /* Pull the chip out of low-power mode, and set for PCI read multiple. */
239 
241 
243 
244  mii_reg5 = mii_read(phys[0], 5);
245  if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
246  printf(" full-duplex mode");
247  tmp |= TC_LM_FULL_DPX;
248  } else
249  tmp |= TC_LM_NORMAL;
250 
251  outl(tmp, txcon);
252 
253  /* Give address of RX and TX ring to the chip */
256 
257  /* Start the chip's Rx process: receive unicast and broadcast */
258  set_rx_mode();
260 
261  putchar('\n');
262 }
263 
264 /* Initialize the Rx and Tx rings. */
265  static void
267 {
268  int i;
269 
270  cur_rx = cur_tx = 0;
271 
272  for (i = 0; i < RX_RING_SIZE; i++) {
273  rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
274  rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
275  rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
276  rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
277  }
278  /* Mark the last entry as wrapping the ring. */
279  rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
280 
281  /*
282  *The Tx buffer descriptor is filled in as needed,
283  * but we do need to clear the ownership bit.
284  */
285 
286  for (i = 0; i < TX_RING_SIZE; i++) {
287  tx_ring[i].status = 0x0000; /* Owned by CPU */
288  tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
289  tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
290  tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
291  }
292  tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
293 }
294 
295 /* function: epic100_transmit
296  * This transmits a packet.
297  *
298  * Arguments: char d[6]: destination ethernet address.
299  * unsigned short t: ethernet protocol type.
300  * unsigned short s: size of the data-part of the packet.
301  * char *p: the data for the packet.
302  * returns: void.
303  */
304  static void
305 epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
306  unsigned int len, const char *data)
307 {
308  unsigned short nstype;
309  unsigned char *txp;
310  int entry;
311  unsigned long ct;
312 
313  /* Calculate the next Tx descriptor entry. */
315 
316  if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
317  printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
318  tx_ring[entry].status);
319 
320  epic100_open();
321  return;
322  }
323 
324  txp = tx_packet + (entry * PKT_BUF_SZ);
325 
326  memcpy(txp, destaddr, ETH_ALEN);
328  nstype = htons(type);
329  memcpy(txp + 12, (char*)&nstype, 2);
330  memcpy(txp + ETH_HLEN, data, len);
331 
332  len += ETH_HLEN;
333  len &= 0x0FFF;
334  while(len < ETH_ZLEN)
335  txp[len++] = '\0';
336  /*
337  * Caution: the write order is important here,
338  * set the base address with the "ownership"
339  * bits last.
340  */
341 
342  tx_ring[entry].buflength |= cpu_to_le32(len);
343  tx_ring[entry].status = cpu_to_le32(len << 16) |
344  cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
345 
346  cur_tx++;
347 
348  /* Trigger an immediate transmit demand. */
350 
351  ct = currticks();
352  /* timeout 10 ms for transmit */
353  while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) &&
354  ct + 10*1000 < currticks())
355  /* Wait */;
356 
357  if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
358  printf("Oops, transmitter timeout, status=%4.4lX\n",
359  tx_ring[entry].status);
360 }
361 
362 /* function: epic100_poll / eth_poll
363  * This receives a packet from the network.
364  *
365  * Arguments: none
366  *
367  * returns: 1 if a packet was received.
368  * 0 if no packet was received.
369  * side effects:
370  * returns the packet in the array nic->packet.
371  * returns the length of the packet in nic->packetlen.
372  */
373 
374  static int
375 epic100_poll(struct nic *nic, int retrieve)
376 {
377  int entry;
378  int retcode;
379  unsigned long status;
381 
383  return (0);
384 
385  if ( ! retrieve ) return 1;
386 
388  /* We own the next entry, it's a new packet. Send it up. */
389 
390 #if (EPIC_DEBUG > 4)
391  printf("epic_poll: entry %d status %hX\n", entry, status);
392 #endif
393 
394  cur_rx++;
395  if (status & 0x2000) {
396  printf("epic_poll: Giant packet\n");
397  retcode = 0;
398  } else if (status & 0x0006) {
399  /* Rx Frame errors are counted in hardware. */
400  printf("epic_poll: Frame received with errors\n");
401  retcode = 0;
402  } else {
403  /* Omit the four octet CRC from the length. */
404  nic->packetlen = (status >> 16) - 4;
406  retcode = 1;
407  }
408 
409  /* Clear all error sources. */
411 
412  /* Give the descriptor back to the chip */
413  rx_ring[entry].status = RRING_OWN;
414 
415  /* Restart Receiver */
417 
418  return retcode;
419 }
420 
421 
422 static void epic100_disable ( struct nic *nic __unused ) {
423  /* Soft reset the chip. */
425 }
426 
427 static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
428 {
429  switch ( action ) {
430  case DISABLE :
431  break;
432  case ENABLE :
433  break;
434  case FORCE :
435  break;
436  }
437 }
438 
439 #ifdef DEBUG_EEPROM
440 /* Serial EEPROM section. */
441 
442 /* EEPROM_Ctrl bits. */
443 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
444 #define EE_CS 0x02 /* EEPROM chip select. */
445 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
446 #define EE_WRITE_0 0x01
447 #define EE_WRITE_1 0x09
448 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
449 #define EE_ENB (0x0001 | EE_CS)
450 
451 /* The EEPROM commands include the alway-set leading bit. */
452 #define EE_WRITE_CMD (5 << 6)
453 #define EE_READ_CMD (6 << 6)
454 #define EE_ERASE_CMD (7 << 6)
455 
456 #define eeprom_delay(n) delay(n)
457 
458  static int
459 read_eeprom(int location)
460 {
461  int i;
462  int retval = 0;
463  int read_cmd = location | EE_READ_CMD;
464 
465  outl(EE_ENB & ~EE_CS, eectl);
466  outl(EE_ENB, eectl);
467 
468  /* Shift the read command bits out. */
469  for (i = 10; i >= 0; i--) {
470  short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
471  outl(EE_ENB | dataval, eectl);
472  eeprom_delay(100);
473  outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
474  eeprom_delay(150);
475  outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */
476  eeprom_delay(250);
477  }
478  outl(EE_ENB, eectl);
479 
480  for (i = 16; i > 0; i--) {
482  eeprom_delay(100);
483  retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
484  outl(EE_ENB, eectl);
485  eeprom_delay(100);
486  }
487 
488  /* Terminate the EEPROM access. */
489  outl(EE_ENB & ~EE_CS, eectl);
490  return retval;
491 }
492 #endif
493 
494 
495 #define MII_READOP 1
496 #define MII_WRITEOP 2
497 
498  static int
499 mii_read(int phy_id, int location)
500 {
501  int i;
502 
503  outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
504  /* Typical operation takes < 50 ticks. */
505 
506  for (i = 4000; i > 0; i--)
507  if ((inl(mmctl) & MII_READOP) == 0)
508  break;
509  return inw(mmdata);
510 }
511 
512 static struct nic_operations epic100_operations = {
514  .poll = epic100_poll,
515  .transmit = epic100_transmit,
516  .irq = epic100_irq,
517 
518 };
519 
520 static struct pci_device_id epic100_nics[] = {
521 PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII", 0), /* SMC 83c170 EPIC/100 */
522 PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175", 0),
523 };
524 
525 PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS );
526 
527 DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver,
529 
530 /*
531  * Local variables:
532  * c-basic-offset: 8
533  * c-indent-level: 8
534  * tab-width: 8
535  * End:
536  */
static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
Definition: davicom.c:377
unsigned char irqno
Definition: nic.h:56
unsigned long buflength
Definition: epic100.c:36
#define EE_READ_CMD
Definition: davicom.c:71
Definition: nic.h:35
#define TX_SLOT_TIME
Definition: epic100.h:145
#define MII_READOP
Definition: epic100.c:495
Definition: epic100.h:32
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
static int lan0
Definition: epic100.c:76
Definition: epic100.h:21
A PCI driver.
Definition: pci.h:224
#define RRING_OWN
Definition: epic100.h:161
#define le32_to_cpu(value)
Definition: byteswap.h:113
#define outw(data, io_addr)
Definition: io.h:319
unsigned long bufaddr
Definition: epic100.c:35
unsigned long ioaddr
I/O address.
Definition: pci.h:200
#define GC_RX_FIFO_THR_64
Definition: epic100.h:106
#define EE_DATA_READ
Definition: davicom.c:80
A command-line command.
Definition: command.h:9
unsigned long bufaddr
Definition: epic100.c:44
static int mc0
Definition: epic100.c:77
uint8_t type
Type.
Definition: ena.h:16
unsigned long buflength
Definition: epic100.c:45
static int epic100_poll(struct nic *nic, int retrieve)
Definition: epic100.c:375
static void epic100_disable(struct nic *nic)
static unsigned int cur_tx
Definition: epic100.c:84
void putchar(int character)
Write a single character to each console device.
Definition: console.c:27
#define GC_SOFT_RESET
Definition: epic100.h:89
Definition: epic100.h:23
Definition: epic100.h:42
Definition: epic100.h:35
#define INTR_DISABLE
Definition: epic100.h:83
#define EE_ENB
Definition: davicom.c:81
#define TX_RING_SIZE
Definition: epic100.c:19
static int epic100_probe(struct nic *nic, struct pci_device *pci)
Definition: epic100.c:108
Definition: epic100.h:34
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
static int rxcon
Definition: epic100.c:78
eeprom
Definition: 3c90x.h:232
#define RX_RING_SIZE
Definition: epic100.c:20
uint8_t status
Status.
Definition: ena.h:16
#define GC_ONE_COPY
Definition: epic100.h:93
void * memcpy(void *dest, const void *src, size_t len) __nonnull
unsigned int ioaddr
Definition: nic.h:55
static signed char phys[4]
Definition: epic100.c:88
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define GC_MRC_READ_MULT
Definition: epic100.h:112
static void epic100_init_ring(void)
Definition: epic100.c:266
#define ETH_HLEN
Definition: if_ether.h:9
Ethernet protocol.
Definition: epic100.h:29
unsigned long next
Definition: epic100.c:46
#define TRING_OWN
Definition: epic100.h:177
struct @40 __shared
A 16-bit general register.
Definition: registers.h:24
DRIVER("EPIC100", nic_driver, pci_driver, epic100_driver, epic100_probe, epic100_disable)
static int txcon
Definition: epic100.c:79
irq_action_t
Definition: nic.h:34
Definition: epic100.h:28
#define EE_SHIFT_CLK
Definition: davicom.c:75
#define TC_LM_NORMAL
Definition: epic100.h:140
#define cpu_to_le32(value)
Definition: byteswap.h:107
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define rx_packet
Definition: epic100.c:99
unsigned int packetlen
Definition: nic.h:54
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
#define outl(data, io_addr)
Definition: io.h:329
#define eeprom_delay()
Definition: davicom.c:91
PCI bus.
A PCI device.
Definition: pci.h:187
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
uint8_t * tmp
Definition: entropy.h:156
Definition: epic100.h:24
unsigned long next
Definition: epic100.c:37
#define TC_LM_FULL_DPX
Definition: epic100.h:143
Definition: epic100.h:38
Definition: epic100.h:36
unsigned long status
Definition: epic100.c:34
#define ETH_ALEN
Definition: if_ether.h:8
#define ETH_ZLEN
Definition: if_ether.h:10
A PCI device ID list entry.
Definition: pci.h:151
static int command
Definition: epic100.c:68
static void set_rx_mode(void)
Definition: epic100.c:218
Definition: nic.h:37
Definition: nic.h:49
static struct nic_operations epic100_operations
Definition: epic100.c:64
static int genctl
Definition: epic100.c:71
#define rx_ring
Definition: epic100.c:97
unsigned long retval
Definition: xen.h:45
#define TC_EARLY_TX_ENABLE
Definition: epic100.h:137
#define CR_START_RX
Definition: epic100.h:47
static int eththr
Definition: epic100.c:82
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
static int ioaddr
Definition: epic100.c:66
Definition: nic.h:36
#define EE_CS
Definition: davicom.c:76
unsigned char * packet
Definition: nic.h:53
unsigned long status
Definition: epic100.c:43
unsigned char * node_addr
Definition: nic.h:52
#define tx_ring
Definition: epic100.c:98
#define tx_packet
Definition: epic100.c:100
uint32_t len
Length.
Definition: ena.h:14
static struct pci_device_id epic100_nics[]
Definition: epic100.c:520
static unsigned int cur_rx
Definition: epic100.c:84
static int ptcdar
Definition: epic100.c:81
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
static void epic100_irq(struct nic *nic, irq_action_t action)
#define virt_to_le32desc(addr)
Definition: epic100.c:16
#define PKT_BUF_SZ
Definition: epic100.c:22
static int intstat
Definition: epic100.c:69
static int mmctl
Definition: epic100.c:74
#define TD_STDFLAGS
Definition: epic100.c:40
Definition: epic100.h:41
static int prcdar
Definition: epic100.c:80
static int mii_read(int phy_id, int location)
Definition: epic100.c:499
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
#define EE_DATA_WRITE
Definition: davicom.c:77
int(* connect)(struct nic *)
Definition: nic.h:63
static void epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type, unsigned int len, const char *data)
Definition: epic100.c:305
#define INTR_CLEARERRS
Definition: epic100.h:84
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define CR_QUEUE_RX
Definition: epic100.h:49
static int mmdata
Definition: epic100.c:75
#define CR_QUEUE_TX
Definition: epic100.h:48
#define htons(value)
Definition: byteswap.h:135
static int test
Definition: epic100.c:73
FILE_LICENCE(GPL2_OR_LATER)
static int intmask
Definition: epic100.c:70
static int eectl
Definition: epic100.c:72
#define TX_FIFO_THRESH
Definition: epic100.h:148
void * memset(void *dest, int character, size_t len) __nonnull
static void epic100_open(void)
Definition: epic100.c:230
PCI_DRIVER(epic100_driver, epic100_nics, PCI_NO_CLASS)