iPXE
sky2.c
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1 /*
2  * iPXE driver for Marvell Yukon 2 chipset. Derived from Linux sky2 driver
3  * (v1.22), which was based on earlier sk98lin and skge drivers.
4  *
5  * This driver intentionally does not support all the features
6  * of the original driver such as link fail-over and link management because
7  * those should be done at higher levels.
8  *
9  * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10  *
11  * Modified for iPXE, April 2009 by Joshua Oreman
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25  * 02110-1301, USA.
26  */
27 
28 FILE_LICENCE ( GPL2_ONLY );
29 
30 #include <stdint.h>
31 #include <errno.h>
32 #include <stdio.h>
33 #include <unistd.h>
34 #include <ipxe/ethernet.h>
35 #include <ipxe/if_ether.h>
36 #include <ipxe/iobuf.h>
37 #include <ipxe/malloc.h>
38 #include <ipxe/pci.h>
39 #include <byteswap.h>
40 #include <mii.h>
41 
42 #include "sky2.h"
43 
44 #define DRV_NAME "sky2"
45 #define DRV_VERSION "1.22"
46 #define PFX DRV_NAME " "
47 
48 /*
49  * The Yukon II chipset takes 64 bit command blocks (called list elements)
50  * that are organized into three (receive, transmit, status) different rings
51  * similar to Tigon3.
52  *
53  * Each ring start must be aligned to a 4k boundary. You will get mysterious
54  * "invalid LE" errors if they're not.
55  *
56  * The card silently forces each ring size to be at least 128. If you
57  * act as though one of them is smaller (by setting the below
58  * #defines) you'll get bad bugs.
59  */
60 
61 #define RX_LE_SIZE 128
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_RING_ALIGN 4096
64 #define RX_PENDING (RX_LE_SIZE/6 - 2)
65 
66 #define TX_RING_SIZE 128
67 #define TX_PENDING (TX_RING_SIZE - 1)
68 #define TX_RING_ALIGN 4096
69 #define MAX_SKB_TX_LE 4
70 
71 #define STATUS_RING_SIZE 512 /* 2 ports * (TX + RX) */
72 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
73 #define STATUS_RING_ALIGN 4096
74 #define PHY_RETRIES 1000
75 
76 #define SKY2_EEPROM_MAGIC 0x9955aabb
77 
78 
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80 
81 static struct pci_device_id sky2_id_table[] = {
82  PCI_ROM(0x1148, 0x9000, "sk9sxx", "Syskonnect SK-9Sxx", 0),
83  PCI_ROM(0x1148, 0x9e00, "sk9exx", "Syskonnect SK-9Exx", 0),
84  PCI_ROM(0x1186, 0x4b00, "dge560t", "D-Link DGE-560T", 0),
85  PCI_ROM(0x1186, 0x4001, "dge550sx", "D-Link DGE-550SX", 0),
86  PCI_ROM(0x1186, 0x4b02, "dge560sx", "D-Link DGE-560SX", 0),
87  PCI_ROM(0x1186, 0x4b03, "dge550t", "D-Link DGE-550T", 0),
88  PCI_ROM(0x11ab, 0x4340, "m88e8021", "Marvell 88E8021", 0),
89  PCI_ROM(0x11ab, 0x4341, "m88e8022", "Marvell 88E8022", 0),
90  PCI_ROM(0x11ab, 0x4342, "m88e8061", "Marvell 88E8061", 0),
91  PCI_ROM(0x11ab, 0x4343, "m88e8062", "Marvell 88E8062", 0),
92  PCI_ROM(0x11ab, 0x4344, "m88e8021b", "Marvell 88E8021", 0),
93  PCI_ROM(0x11ab, 0x4345, "m88e8022b", "Marvell 88E8022", 0),
94  PCI_ROM(0x11ab, 0x4346, "m88e8061b", "Marvell 88E8061", 0),
95  PCI_ROM(0x11ab, 0x4347, "m88e8062b", "Marvell 88E8062", 0),
96  PCI_ROM(0x11ab, 0x4350, "m88e8035", "Marvell 88E8035", 0),
97  PCI_ROM(0x11ab, 0x4351, "m88e8036", "Marvell 88E8036", 0),
98  PCI_ROM(0x11ab, 0x4352, "m88e8038", "Marvell 88E8038", 0),
99  PCI_ROM(0x11ab, 0x4353, "m88e8039", "Marvell 88E8039", 0),
100  PCI_ROM(0x11ab, 0x4354, "m88e8040", "Marvell 88E8040", 0),
101  PCI_ROM(0x11ab, 0x4355, "m88e8040t", "Marvell 88E8040T", 0),
102  PCI_ROM(0x11ab, 0x4356, "m88ec033", "Marvel 88EC033", 0),
103  PCI_ROM(0x11ab, 0x4357, "m88e8042", "Marvell 88E8042", 0),
104  PCI_ROM(0x11ab, 0x435a, "m88e8048", "Marvell 88E8048", 0),
105  PCI_ROM(0x11ab, 0x4360, "m88e8052", "Marvell 88E8052", 0),
106  PCI_ROM(0x11ab, 0x4361, "m88e8050", "Marvell 88E8050", 0),
107  PCI_ROM(0x11ab, 0x4362, "m88e8053", "Marvell 88E8053", 0),
108  PCI_ROM(0x11ab, 0x4363, "m88e8055", "Marvell 88E8055", 0),
109  PCI_ROM(0x11ab, 0x4364, "m88e8056", "Marvell 88E8056", 0),
110  PCI_ROM(0x11ab, 0x4365, "m88e8070", "Marvell 88E8070", 0),
111  PCI_ROM(0x11ab, 0x4366, "m88ec036", "Marvell 88EC036", 0),
112  PCI_ROM(0x11ab, 0x4367, "m88ec032", "Marvell 88EC032", 0),
113  PCI_ROM(0x11ab, 0x4368, "m88ec034", "Marvell 88EC034", 0),
114  PCI_ROM(0x11ab, 0x4369, "m88ec042", "Marvell 88EC042", 0),
115  PCI_ROM(0x11ab, 0x436a, "m88e8058", "Marvell 88E8058", 0),
116  PCI_ROM(0x11ab, 0x436b, "m88e8071", "Marvell 88E8071", 0),
117  PCI_ROM(0x11ab, 0x436c, "m88e8072", "Marvell 88E8072", 0),
118  PCI_ROM(0x11ab, 0x436d, "m88e8055b", "Marvell 88E8055", 0),
119  PCI_ROM(0x11ab, 0x4370, "m88e8075", "Marvell 88E8075", 0),
120  PCI_ROM(0x11ab, 0x4380, "m88e8057", "Marvell 88E8057", 0)
121 };
122 
123 /* Avoid conditionals by using array */
124 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
125 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
126 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
127 
128 static void sky2_set_multicast(struct net_device *dev);
129 
130 /* Access to PHY via serial interconnect */
131 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
132 {
133  int i;
134 
138 
139  for (i = 0; i < PHY_RETRIES; i++) {
141  if (ctrl == 0xffff)
142  goto io_error;
143 
144  if (!(ctrl & GM_SMI_CT_BUSY))
145  return 0;
146 
147  udelay(10);
148  }
149 
150  DBG(PFX "%s: phy write timeout\n", hw->dev[port]->name);
151  return -ETIMEDOUT;
152 
153 io_error:
154  DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
155  return -EIO;
156 }
157 
158 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
159 {
160  int i;
161 
164 
165  for (i = 0; i < PHY_RETRIES; i++) {
167  if (ctrl == 0xffff)
168  goto io_error;
169 
170  if (ctrl & GM_SMI_CT_RD_VAL) {
172  return 0;
173  }
174 
175  udelay(10);
176  }
177 
178  DBG(PFX "%s: phy read timeout\n", hw->dev[port]->name);
179  return -ETIMEDOUT;
180 io_error:
181  DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
182  return -EIO;
183 }
184 
185 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
186 {
187  u16 v = 0;
188  __gm_phy_read(hw, port, reg, &v);
189  return v;
190 }
191 
192 
193 static void sky2_power_on(struct sky2_hw *hw)
194 {
195  /* switch power to VCC (WA for VAUX problem) */
198 
199  /* disable Core Clock Division, */
201 
202  if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
203  /* enable bits are inverted */
208  else
210 
211  if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
212  u32 reg;
213 
215 
217  /* set all bits to 0 except bits 15..12 and 8 */
220 
222  /* set all bits to 0 except bits 28 & 27 */
225 
227 
228  /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
232 
234  }
235 }
236 
237 static void sky2_power_aux(struct sky2_hw *hw)
238 {
239  if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
241  else
242  /* enable bits are inverted */
247 
248  /* switch power to VAUX */
253 }
254 
255 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
256 {
257  u16 reg;
258 
259  /* disable all GMAC IRQ's */
261 
262  gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
266 
270 }
271 
272 /* flow control to advertise bits */
273 static const u16 copper_fc_adv[] = {
274  [FC_NONE] = 0,
275  [FC_TX] = PHY_M_AN_ASP,
276  [FC_RX] = PHY_M_AN_PC,
278 };
279 
280 /* flow control to advertise bits when using 1000BaseX */
281 static const u16 fiber_fc_adv[] = {
286 };
287 
288 /* flow control to GMA disable bits */
289 static const u16 gm_fc_disable[] = {
293  [FC_BOTH] = 0,
294 };
295 
296 
297 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
298 {
299  struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
300  u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
301 
302  if (sky2->autoneg == AUTONEG_ENABLE &&
303  !(hw->flags & SKY2_HW_NEWER_PHY)) {
305 
309 
310  /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
311  if (hw->chip_id == CHIP_ID_YUKON_EC)
312  /* set downshift counter to 3x and enable downshift */
313  ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
314  else
315  /* set master & slave downshift counter to 1x */
316  ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
317 
319  }
320 
322  if (sky2_is_copper(hw)) {
323  if (!(hw->flags & SKY2_HW_GIGABIT)) {
324  /* enable automatic crossover */
326 
327  if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
328  hw->chip_rev == CHIP_REV_YU_FE2_A0) {
329  u16 spec;
330 
331  /* Enable Class A driver for FE+ A0 */
333  spec |= PHY_M_FESC_SEL_CL_A;
335  }
336  } else {
337  /* disable energy detect */
339 
340  /* enable automatic crossover */
342 
343  /* downshift on PHY 88E1112 and 88E1149 is changed */
344  if (sky2->autoneg == AUTONEG_ENABLE
345  && (hw->flags & SKY2_HW_NEWER_PHY)) {
346  /* set downshift counter to 3x and enable downshift */
349  }
350  }
351  } else {
352  /* workaround for deviation #4.88 (CRC errors) */
353  /* disable Automatic Crossover */
354 
356  }
357 
359 
360  /* special setup for PHY 88E1112 Fiber */
361  if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
363 
364  /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
370 
371  if (hw->pmd_type == 'P') {
372  /* select page 1 to access Fiber registers */
374 
375  /* for SFP-module set SIGDET polarity to low */
379  }
380 
382  }
383 
384  ctrl = PHY_CT_RESET;
385  ct1000 = 0;
386  adv = PHY_AN_CSMA;
387  reg = 0;
388 
389  if (sky2->autoneg == AUTONEG_ENABLE) {
390  if (sky2_is_copper(hw)) {
392  ct1000 |= PHY_M_1000C_AFD;
394  ct1000 |= PHY_M_1000C_AHD;
396  adv |= PHY_M_AN_100_FD;
398  adv |= PHY_M_AN_100_HD;
400  adv |= PHY_M_AN_10_FD;
402  adv |= PHY_M_AN_10_HD;
403 
404  adv |= copper_fc_adv[sky2->flow_mode];
405  } else { /* special defines for FIBER (88E1040S only) */
407  adv |= PHY_M_AN_1000X_AFD;
409  adv |= PHY_M_AN_1000X_AHD;
410 
411  adv |= fiber_fc_adv[sky2->flow_mode];
412  }
413 
414  /* Restart Auto-negotiation */
416  } else {
417  /* forced speed/duplex settings */
418  ct1000 = PHY_M_1000C_MSE;
419 
420  /* Disable auto update for duplex flow control and speed */
422 
423  switch (sky2->speed) {
424  case SPEED_1000:
425  ctrl |= PHY_CT_SP1000;
427  break;
428  case SPEED_100:
429  ctrl |= PHY_CT_SP100;
431  break;
432  }
433 
434  if (sky2->duplex == DUPLEX_FULL) {
436  ctrl |= PHY_CT_DUP_MD;
437  } else if (sky2->speed < SPEED_1000)
438  sky2->flow_mode = FC_NONE;
439 
440 
441  reg |= gm_fc_disable[sky2->flow_mode];
442 
443  /* Forward pause packets to GMAC? */
444  if (sky2->flow_mode & FC_RX)
446  else
448  }
449 
451 
452  if (hw->flags & SKY2_HW_GIGABIT)
454 
457 
458  /* Setup Phy LED's */
459  ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460  ledover = 0;
461 
462  switch (hw->chip_id) {
463  case CHIP_ID_YUKON_FE:
464  /* on 88E3082 these bits are at 11..9 (shifted left) */
465  ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466 
468 
469  /* delete ACT LED control bits */
471  /* change ACT LED control to blink mode */
474  break;
475 
476  case CHIP_ID_YUKON_FE_P:
477  /* Enable Link Partner Next Page */
480 
481  /* disable Energy Detect and enable scrambler */
484 
485  /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
489 
491  break;
492 
493  case CHIP_ID_YUKON_XL:
495 
496  /* select page 3 to access LED control register */
498 
499  /* set LED Function Control register */
501  (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
502  PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
503  PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
504  PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
505 
506  /* set Polarity Control register */
514 
515  /* restore page register */
517  break;
518 
519  case CHIP_ID_YUKON_EC_U:
520  case CHIP_ID_YUKON_EX:
521  case CHIP_ID_YUKON_SUPR:
523 
524  /* select page 3 to access LED control register */
526 
527  /* set LED Function Control register */
529  (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
530  PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
531  PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
532  PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
533 
534  /* set Blink Rate in LED Timer Control Register */
536  ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
537  /* restore page register */
539  break;
540 
541  default:
542  /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
544 
545  /* turn off the Rx LED (LED_RX) */
546  ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
547  }
548 
549  if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
550  /* apply fixes in PHY AFE */
552 
553  /* increase differential signal amplitude in 10BASE-T */
554  gm_phy_write(hw, port, 0x18, 0xaa99);
555  gm_phy_write(hw, port, 0x17, 0x2011);
556 
557  if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
558  /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
559  gm_phy_write(hw, port, 0x18, 0xa204);
560  gm_phy_write(hw, port, 0x17, 0x2002);
561  }
562 
563  /* set page register to 0 */
565  } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
566  hw->chip_rev == CHIP_REV_YU_FE2_A0) {
567  /* apply workaround for integrated resistors calibration */
570  } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
571  hw->chip_id < CHIP_ID_YUKON_SUPR) {
572  /* no effect on Yukon-XL */
574 
575  if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
576  /* turn on 100 Mbps LED (LED_LINK100) */
577  ledover |= PHY_M_LED_MO_100(MO_LED_ON);
578  }
579 
580  if (ledover)
582 
583  }
584 
585  /* Enable phy interrupt on auto-negotiation complete (or link up) */
586  if (sky2->autoneg == AUTONEG_ENABLE)
588  else
590 }
591 
594 
595 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
596 {
597  u32 reg1;
598 
601  reg1 &= ~phy_power[port];
602 
603  if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
604  reg1 |= coma_mode[port];
605 
609 
610  if (hw->chip_id == CHIP_ID_YUKON_FE)
612  else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
614 }
615 
616 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
617 {
618  u32 reg1;
619  u16 ctrl;
620 
621  /* release GPHY Control reset */
623 
624  /* release GMAC reset */
626 
627  if (hw->flags & SKY2_HW_NEWER_PHY) {
628  /* select page 2 to access MAC control register */
630 
632  /* allow GMII Power Down */
635 
636  /* set page register back to 0 */
638  }
639 
640  /* setup General Purpose Control Register */
643 
644  if (hw->chip_id != CHIP_ID_YUKON_EC) {
645  if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
646  /* select page 2 to access MAC control register */
648 
650  /* enable Power Down */
653 
654  /* set page register back to 0 */
656  }
657 
658  /* set IEEE compatible Power Down Mode (dev. #4.99) */
660  }
661 
664  reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
667 }
668 
669 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
670 {
671  if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
672  hw->chip_rev != CHIP_REV_YU_EX_A0) ||
673  hw->chip_id == CHIP_ID_YUKON_FE_P ||
674  hw->chip_id == CHIP_ID_YUKON_SUPR) {
675  /* disable jumbo frames on devices that support them */
678  } else {
680  }
681 }
682 
683 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
684 {
685  u16 reg;
686  u32 rx_reg;
687  int i;
688  const u8 *addr = hw->dev[port]->ll_addr;
689 
692 
694 
695  if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
696  /* WA DEV_472 -- looks like crossed wires on port 2 */
697  /* clear GMAC 1 Control reset */
699  do {
702  } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
704  gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
705  }
706 
708 
709  /* Enable Transmit FIFO Underrun */
711 
714 
715  /* MIB clear */
718 
719  for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
720  gma_read16(hw, port, i);
722 
723  /* transmit control */
725 
726  /* receive control reg: unicast + multicast + no FCS */
729 
730  /* transmit flow control */
731  gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
732 
733  /* transmit parameter */
739 
740  /* serial mode register */
743 
745 
746  /* virtual address for data */
748 
749  /* physical address: used for pause frames */
751 
752  /* ignore counter overflows */
756 
757  /* Configure Rx MAC FIFO */
759  rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
760  if (hw->chip_id == CHIP_ID_YUKON_EX ||
761  hw->chip_id == CHIP_ID_YUKON_FE_P)
762  rx_reg |= GMF_RX_OVER_ON;
763 
765 
766  if (hw->chip_id == CHIP_ID_YUKON_XL) {
767  /* Hardware errata - clear flush mask */
769  } else {
770  /* Flush Rx MAC FIFO on any flow control or error */
772  }
773 
774  /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
775  reg = RX_GMF_FL_THR_DEF + 1;
776  /* Another magic mystery workaround from sk98lin */
777  if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
778  hw->chip_rev == CHIP_REV_YU_FE2_A0)
779  reg = 0x178;
781 
782  /* Configure Tx MAC FIFO */
785 
786  /* On chips without ram buffer, pause is controlled by MAC level */
787  if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
789  sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
790 
792  }
793 
794  if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
795  hw->chip_rev == CHIP_REV_YU_FE2_A0) {
796  /* disable dynamic watermark */
798  reg &= ~TX_DYN_WM_ENA;
800  }
801 }
802 
803 /* Assign Ram Buffer allocation to queue */
804 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
805 {
806  u32 end;
807 
808  /* convert from K bytes to qwords used for hw register */
809  start *= 1024/8;
810  space *= 1024/8;
811  end = start + space - 1;
812 
818 
819  if (q == Q_R1 || q == Q_R2) {
820  u32 tp = space - space/4;
821 
822  /* On receive queue's set the thresholds
823  * give receiver priority when > 3/4 full
824  * send pause when down to 2K
825  */
827  sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
828 
829  tp = space - 2048/8;
831  sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
832  } else {
833  /* Enable store & forward on Tx queue's because
834  * Tx FIFO is only 1K on Yukon
835  */
837  }
838 
841 }
842 
843 /* Setup Bus Memory Interface */
844 static void sky2_qset(struct sky2_hw *hw, u16 q)
845 {
850 }
851 
852 /* Setup prefetch unit registers. This is the interface between
853  * hardware and driver list elements
854  */
855 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
856  u64 addr, u32 last)
857 {
860  sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
864 
866 }
867 
868 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
869 {
870  struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
871 
872  sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
873  le->ctrl = 0;
874  return le;
875 }
876 
877 static void tx_init(struct sky2_port *sky2)
878 {
879  struct sky2_tx_le *le;
880 
881  sky2->tx_prod = sky2->tx_cons = 0;
882 
883  le = get_tx_le(sky2);
884  le->addr = 0;
885  le->opcode = OP_ADDR64 | HW_OWNER;
886 }
887 
888 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
889  struct sky2_tx_le *le)
890 {
891  return sky2->tx_ring + (le - sky2->tx_le);
892 }
893 
894 /* Update chip's next pointer */
895 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
896 {
897  /* Make sure write' to descriptors are complete before we tell hardware */
898  wmb();
900  DBGIO(PFX "queue %#x idx <- %d\n", q, idx);
901 }
902 
903 
904 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
905 {
906  struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
907 
908  sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
909  le->ctrl = 0;
910  return le;
911 }
912 
913 /* Build description to hardware for one receive segment */
914 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
915  u32 map, unsigned len)
916 {
917  struct sky2_rx_le *le;
918 
919  le = sky2_next_rx(sky2);
920  le->addr = cpu_to_le32(map);
921  le->length = cpu_to_le16(len);
922  le->opcode = op | HW_OWNER;
923 }
924 
925 /* Build description to hardware for one possibly fragmented skb */
926 static void sky2_rx_submit(struct sky2_port *sky2,
927  const struct rx_ring_info *re)
928 {
929  sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
930 }
931 
932 
933 static void sky2_rx_map_iob(struct pci_device *pdev __unused,
934  struct rx_ring_info *re,
935  unsigned size __unused)
936 {
937  struct io_buffer *iob = re->iob;
938  re->data_addr = virt_to_bus(iob->data);
939 }
940 
941 /* Diable the checksum offloading.
942  */
943 static void rx_set_checksum(struct sky2_port *sky2)
944 {
945  struct sky2_rx_le *le = sky2_next_rx(sky2);
946 
947  le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
948  le->ctrl = 0;
949  le->opcode = OP_TCPSTART | HW_OWNER;
950 
951  sky2_write32(sky2->hw,
952  Q_ADDR(rxqaddr[sky2->port], Q_CSR),
954 }
955 
956 /*
957  * The RX Stop command will not work for Yukon-2 if the BMU does not
958  * reach the end of packet and since we can't make sure that we have
959  * incoming data, we must reset the BMU while it is not doing a DMA
960  * transfer. Since it is possible that the RX path is still active,
961  * the RX RAM buffer will be stopped first, so any possible incoming
962  * data will not trigger a DMA. After the RAM buffer is stopped, the
963  * BMU is polled until any DMA in progress is ended and only then it
964  * will be reset.
965  */
966 static void sky2_rx_stop(struct sky2_port *sky2)
967 {
968  struct sky2_hw *hw = sky2->hw;
969  unsigned rxq = rxqaddr[sky2->port];
970  int i;
971 
972  /* disable the RAM Buffer receive queue */
974 
975  for (i = 0; i < 0xffff; i++)
976  if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
977  == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
978  goto stopped;
979 
980  DBG(PFX "%s: receiver stop failed\n", sky2->netdev->name);
981 stopped:
983 
984  /* reset the Rx prefetch unit */
986  wmb();
987 }
988 
989 /* Clean out receive buffer area, assumes receiver hardware stopped */
990 static void sky2_rx_clean(struct sky2_port *sky2)
991 {
992  unsigned i;
993 
994  memset(sky2->rx_le, 0, RX_LE_BYTES);
995  for (i = 0; i < RX_PENDING; i++) {
996  struct rx_ring_info *re = sky2->rx_ring + i;
997 
998  if (re->iob) {
999  free_iob(re->iob);
1000  re->iob = NULL;
1001  }
1002  }
1003 }
1004 
1005 /*
1006  * Allocate an iob for receiving.
1007  */
1008 static struct io_buffer *sky2_rx_alloc(struct sky2_port *sky2)
1009 {
1010  struct io_buffer *iob;
1011 
1012  iob = alloc_iob(sky2->rx_data_size + ETH_DATA_ALIGN);
1013  if (!iob)
1014  return NULL;
1015 
1016  /*
1017  * Cards with a RAM buffer hang in the rx FIFO if the
1018  * receive buffer isn't aligned to (Linux module comments say
1019  * 64 bytes, Linux module code says 8 bytes). Since io_buffers
1020  * are always 2kb-aligned under iPXE, just leave it be
1021  * without ETH_DATA_ALIGN in those cases.
1022  *
1023  * XXX This causes unaligned access to the IP header,
1024  * which is undesirable, but it's less undesirable than the
1025  * card hanging.
1026  */
1027  if (!(sky2->hw->flags & SKY2_HW_RAM_BUFFER)) {
1029  }
1030 
1031  return iob;
1032 }
1033 
1034 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1035 {
1036  sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1037 }
1038 
1039 /*
1040  * Allocate and setup receiver buffer pool.
1041  * Normal case this ends up creating one list element for skb
1042  * in the receive ring. One element is used for checksum
1043  * enable/disable, and one extra to avoid wrap.
1044  */
1045 static int sky2_rx_start(struct sky2_port *sky2)
1046 {
1047  struct sky2_hw *hw = sky2->hw;
1048  struct rx_ring_info *re;
1049  unsigned rxq = rxqaddr[sky2->port];
1050  unsigned i, size, thresh;
1051 
1052  sky2->rx_put = sky2->rx_next = 0;
1053  sky2_qset(hw, rxq);
1054 
1055  /* On PCI express lowering the watermark gives better performance */
1058 
1059  /* These chips have no ram buffer?
1060  * MAC Rx RAM Read is controlled by hardware */
1061  if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1062  (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1063  || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1065 
1066  sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1067 
1068  if (!(hw->flags & SKY2_HW_NEW_LE))
1069  rx_set_checksum(sky2);
1070 
1071  /* Space needed for frame data + headers rounded up */
1072  size = (ETH_FRAME_LEN + 8) & ~7;
1073 
1074  /* Stopping point for hardware truncation */
1075  thresh = (size - 8) / sizeof(u32);
1076 
1077  sky2->rx_data_size = size;
1078 
1079  /* Fill Rx ring */
1080  for (i = 0; i < RX_PENDING; i++) {
1081  re = sky2->rx_ring + i;
1082 
1083  re->iob = sky2_rx_alloc(sky2);
1084  if (!re->iob)
1085  goto nomem;
1086 
1087  sky2_rx_map_iob(hw->pdev, re, sky2->rx_data_size);
1088  sky2_rx_submit(sky2, re);
1089  }
1090 
1091  /*
1092  * The receiver hangs if it receives frames larger than the
1093  * packet buffer. As a workaround, truncate oversize frames, but
1094  * the register is limited to 9 bits, so if you do frames > 2052
1095  * you better get the MTU right!
1096  */
1097  if (thresh > 0x1ff)
1099  else {
1100  sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1102  }
1103 
1104  /* Tell chip about available buffers */
1105  sky2_rx_update(sky2, rxq);
1106  return 0;
1107 nomem:
1108  sky2_rx_clean(sky2);
1109  return -ENOMEM;
1110 }
1111 
1112 /* Free the le and ring buffers */
1113 static void sky2_free_rings(struct sky2_port *sky2)
1114 {
1115  free_phys(sky2->rx_le, RX_LE_BYTES);
1116  free(sky2->rx_ring);
1117 
1118  free_phys(sky2->tx_le, TX_RING_SIZE * sizeof(struct sky2_tx_le));
1119  free(sky2->tx_ring);
1120 
1121  sky2->tx_le = NULL;
1122  sky2->rx_le = NULL;
1123 
1124  sky2->rx_ring = NULL;
1125  sky2->tx_ring = NULL;
1126 }
1127 
1128 /* Bring up network interface. */
1129 static int sky2_up(struct net_device *dev)
1130 {
1131  struct sky2_port *sky2 = netdev_priv(dev);
1132  struct sky2_hw *hw = sky2->hw;
1133  unsigned port = sky2->port;
1134  u32 imask, ramsize;
1135  int err = -ENOMEM;
1136 
1138 
1139  /* must be power of 2 */
1140  sky2->tx_le = malloc_phys(TX_RING_SIZE * sizeof(struct sky2_tx_le), TX_RING_ALIGN);
1141  sky2->tx_le_map = virt_to_bus(sky2->tx_le);
1142  if (!sky2->tx_le)
1143  goto err_out;
1144  memset(sky2->tx_le, 0, TX_RING_SIZE * sizeof(struct sky2_tx_le));
1145 
1146  sky2->tx_ring = zalloc(TX_RING_SIZE * sizeof(struct tx_ring_info));
1147  if (!sky2->tx_ring)
1148  goto err_out;
1149 
1150  tx_init(sky2);
1151 
1153  sky2->rx_le_map = virt_to_bus(sky2->rx_le);
1154  if (!sky2->rx_le)
1155  goto err_out;
1156  memset(sky2->rx_le, 0, RX_LE_BYTES);
1157 
1158  sky2->rx_ring = zalloc(RX_PENDING * sizeof(struct rx_ring_info));
1159  if (!sky2->rx_ring)
1160  goto err_out;
1161 
1162  sky2_mac_init(hw, port);
1163 
1164  /* Register is number of 4K blocks on internal RAM buffer. */
1165  ramsize = sky2_read8(hw, B2_E_0) * 4;
1166  if (ramsize > 0) {
1167  u32 rxspace;
1168 
1169  hw->flags |= SKY2_HW_RAM_BUFFER;
1170  DBG2(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1171  if (ramsize < 16)
1172  rxspace = ramsize / 2;
1173  else
1174  rxspace = 8 + (2*(ramsize - 16))/3;
1175 
1176  sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1177  sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1178 
1179  /* Make sure SyncQ is disabled */
1181  RB_RST_SET);
1182  }
1183 
1184  sky2_qset(hw, txqaddr[port]);
1185 
1186  /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1187  if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1189 
1190  /* Set almost empty threshold */
1191  if (hw->chip_id == CHIP_ID_YUKON_EC_U
1192  && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1194 
1196  TX_RING_SIZE - 1);
1197 
1198  err = sky2_rx_start(sky2);
1199  if (err)
1200  goto err_out;
1201 
1202  /* Enable interrupts from phy/mac for port */
1203  imask = sky2_read32(hw, B0_IMSK);
1204  imask |= portirq_msk[port];
1205  sky2_write32(hw, B0_IMSK, imask);
1206 
1207  DBGIO(PFX "%s: le bases: st %p [%x], rx %p [%x], tx %p [%x]\n",
1208  dev->name, hw->st_le, hw->st_dma, sky2->rx_le, sky2->rx_le_map,
1209  sky2->tx_le, sky2->tx_le_map);
1210 
1212  return 0;
1213 
1214 err_out:
1215  sky2_free_rings(sky2);
1216  return err;
1217 }
1218 
1219 /* Modular subtraction in ring */
1220 static inline int tx_dist(unsigned tail, unsigned head)
1221 {
1222  return (head - tail) & (TX_RING_SIZE - 1);
1223 }
1224 
1225 /* Number of list elements available for next tx */
1226 static inline int tx_avail(const struct sky2_port *sky2)
1227 {
1228  return TX_PENDING - tx_dist(sky2->tx_cons, sky2->tx_prod);
1229 }
1230 
1231 
1232 /*
1233  * Put one packet in ring for transmit.
1234  * A single packet can generate multiple list elements, and
1235  * the number of ring elements will probably be less than the number
1236  * of list elements used.
1237  */
1238 static int sky2_xmit_frame(struct net_device *dev, struct io_buffer *iob)
1239 {
1240  struct sky2_port *sky2 = netdev_priv(dev);
1241  struct sky2_hw *hw = sky2->hw;
1242  struct sky2_tx_le *le = NULL;
1243  struct tx_ring_info *re;
1244  unsigned len;
1245  u32 mapping;
1246  u8 ctrl;
1247 
1248  if (tx_avail(sky2) < 1)
1249  return -EBUSY;
1250 
1251  len = iob_len(iob);
1252  mapping = virt_to_bus(iob->data);
1253 
1254  DBGIO(PFX "%s: tx queued, slot %d, len %d\n", dev->name,
1255  sky2->tx_prod, len);
1256 
1257  ctrl = 0;
1258 
1259  le = get_tx_le(sky2);
1260  le->addr = cpu_to_le32((u32) mapping);
1261  le->length = cpu_to_le16(len);
1262  le->ctrl = ctrl;
1263  le->opcode = (OP_PACKET | HW_OWNER);
1264 
1265  re = tx_le_re(sky2, le);
1266  re->iob = iob;
1267 
1268  le->ctrl |= EOP;
1269 
1270  sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1271 
1272  return 0;
1273 }
1274 
1275 /*
1276  * Free ring elements from starting at tx_cons until "done"
1277  *
1278  * NB: the hardware will tell us about partial completion of multi-part
1279  * buffers so make sure not to free iob too early.
1280  */
1281 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1282 {
1283  struct net_device *dev = sky2->netdev;
1284  unsigned idx;
1285 
1287 
1288  for (idx = sky2->tx_cons; idx != done;
1289  idx = RING_NEXT(idx, TX_RING_SIZE)) {
1290  struct sky2_tx_le *le = sky2->tx_le + idx;
1291  struct tx_ring_info *re = sky2->tx_ring + idx;
1292 
1293  if (le->ctrl & EOP) {
1294  DBGIO(PFX "%s: tx done %d\n", dev->name, idx);
1295  netdev_tx_complete(dev, re->iob);
1296  }
1297  }
1298 
1299  sky2->tx_cons = idx;
1300  mb();
1301 }
1302 
1303 /* Cleanup all untransmitted buffers, assume transmitter not running */
1304 static void sky2_tx_clean(struct net_device *dev)
1305 {
1306  struct sky2_port *sky2 = netdev_priv(dev);
1307 
1308  sky2_tx_complete(sky2, sky2->tx_prod);
1309 }
1310 
1311 /* Network shutdown */
1312 static void sky2_down(struct net_device *dev)
1313 {
1314  struct sky2_port *sky2 = netdev_priv(dev);
1315  struct sky2_hw *hw = sky2->hw;
1316  unsigned port = sky2->port;
1317  u16 ctrl;
1318  u32 imask;
1319 
1320  /* Never really got started! */
1321  if (!sky2->tx_le)
1322  return;
1323 
1324  DBG2(PFX "%s: disabling interface\n", dev->name);
1325 
1326  /* Disable port IRQ */
1327  imask = sky2_read32(hw, B0_IMSK);
1328  imask &= ~portirq_msk[port];
1329  sky2_write32(hw, B0_IMSK, imask);
1330 
1332 
1333  /* Stop transmitter */
1336 
1339 
1343 
1345 
1346  /* Workaround shared GMAC reset */
1347  if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1348  && port == 0 && hw->dev[1]))
1350 
1351  /* Disable Force Sync bit and Enable Alloc bit */
1354 
1355  /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1358 
1359  /* Reset the PCI FIFO of the async Tx queue */
1362 
1363  /* Reset the Tx prefetch units */
1366 
1368 
1369  sky2_rx_stop(sky2);
1370 
1373 
1375 
1376  /* turn off LED's */
1378 
1379  sky2_tx_clean(dev);
1380  sky2_rx_clean(sky2);
1381 
1382  sky2_free_rings(sky2);
1383 
1384  return;
1385 }
1386 
1387 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1388 {
1389  if (hw->flags & SKY2_HW_FIBRE_PHY)
1390  return SPEED_1000;
1391 
1392  if (!(hw->flags & SKY2_HW_GIGABIT)) {
1393  if (aux & PHY_M_PS_SPEED_100)
1394  return SPEED_100;
1395  else
1396  return SPEED_10;
1397  }
1398 
1399  switch (aux & PHY_M_PS_SPEED_MSK) {
1400  case PHY_M_PS_SPEED_1000:
1401  return SPEED_1000;
1402  case PHY_M_PS_SPEED_100:
1403  return SPEED_100;
1404  default:
1405  return SPEED_10;
1406  }
1407 }
1408 
1409 static void sky2_link_up(struct sky2_port *sky2)
1410 {
1411  struct sky2_hw *hw = sky2->hw;
1412  unsigned port = sky2->port;
1413  u16 reg;
1414  static const char *fc_name[] = {
1415  [FC_NONE] = "none",
1416  [FC_TX] = "tx",
1417  [FC_RX] = "rx",
1418  [FC_BOTH] = "both",
1419  };
1420 
1421  /* enable Rx/Tx */
1425 
1427 
1428  netdev_link_up(sky2->netdev);
1429 
1430  /* Turn on link LED */
1433 
1434  DBG(PFX "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1435  sky2->netdev->name, sky2->speed,
1436  sky2->duplex == DUPLEX_FULL ? "full" : "half",
1437  fc_name[sky2->flow_status]);
1438 }
1439 
1440 static void sky2_link_down(struct sky2_port *sky2)
1441 {
1442  struct sky2_hw *hw = sky2->hw;
1443  unsigned port = sky2->port;
1444  u16 reg;
1445 
1447 
1451 
1452  netdev_link_down(sky2->netdev);
1453 
1454  /* Turn on link LED */
1456 
1457  DBG(PFX "%s: Link is down.\n", sky2->netdev->name);
1458 
1459  sky2_phy_init(hw, port);
1460 }
1461 
1462 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1463 {
1464  struct sky2_hw *hw = sky2->hw;
1465  unsigned port = sky2->port;
1466  u16 advert, lpa;
1467 
1468  advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1470  if (lpa & PHY_M_AN_RF) {
1471  DBG(PFX "%s: remote fault\n", sky2->netdev->name);
1472  return -1;
1473  }
1474 
1475  if (!(aux & PHY_M_PS_SPDUP_RES)) {
1476  DBG(PFX "%s: speed/duplex mismatch\n", sky2->netdev->name);
1477  return -1;
1478  }
1479 
1480  sky2->speed = sky2_phy_speed(hw, aux);
1481  sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1482 
1483  /* Since the pause result bits seem to in different positions on
1484  * different chips. look at registers.
1485  */
1486 
1487  sky2->flow_status = FC_NONE;
1488  if (advert & ADVERTISE_PAUSE_CAP) {
1489  if (lpa & LPA_PAUSE_CAP)
1490  sky2->flow_status = FC_BOTH;
1491  else if (advert & ADVERTISE_PAUSE_ASYM)
1492  sky2->flow_status = FC_RX;
1493  } else if (advert & ADVERTISE_PAUSE_ASYM) {
1494  if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1495  sky2->flow_status = FC_TX;
1496  }
1497 
1498  if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1499  && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1500  sky2->flow_status = FC_NONE;
1501 
1502  if (sky2->flow_status & FC_TX)
1504  else
1506 
1507  return 0;
1508 }
1509 
1510 /* Interrupt from PHY */
1511 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1512 {
1513  struct net_device *dev = hw->dev[port];
1514  struct sky2_port *sky2 = netdev_priv(dev);
1515  u16 istatus, phystat;
1516 
1517  istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1518  phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1519 
1520  DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
1521  sky2->netdev->name, istatus, phystat);
1522 
1523  if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1524  if (sky2_autoneg_done(sky2, phystat) == 0)
1525  sky2_link_up(sky2);
1526  return;
1527  }
1528 
1529  if (istatus & PHY_M_IS_LSP_CHANGE)
1530  sky2->speed = sky2_phy_speed(hw, phystat);
1531 
1532  if (istatus & PHY_M_IS_DUP_CHANGE)
1533  sky2->duplex =
1534  (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1535 
1536  if (istatus & PHY_M_IS_LST_CHANGE) {
1537  if (phystat & PHY_M_PS_LINK_UP)
1538  sky2_link_up(sky2);
1539  else
1540  sky2_link_down(sky2);
1541  }
1542 }
1543 
1544 /* Normal packet - take iob from ring element and put in a new one */
1545 static struct io_buffer *receive_new(struct sky2_port *sky2,
1546  struct rx_ring_info *re,
1547  unsigned int length)
1548 {
1549  struct io_buffer *iob, *niob;
1550  unsigned hdr_space = sky2->rx_data_size;
1551 
1552  /* Don't be tricky about reusing pages (yet) */
1553  niob = sky2_rx_alloc(sky2);
1554  if (!niob)
1555  return NULL;
1556 
1557  iob = re->iob;
1558 
1559  re->iob = niob;
1560  sky2_rx_map_iob(sky2->hw->pdev, re, hdr_space);
1561 
1562  iob_put(iob, length);
1563  return iob;
1564 }
1565 
1566 /*
1567  * Receive one packet.
1568  * For larger packets, get new buffer.
1569  */
1570 static struct io_buffer *sky2_receive(struct net_device *dev,
1571  u16 length, u32 status)
1572 {
1573  struct sky2_port *sky2 = netdev_priv(dev);
1574  struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
1575  struct io_buffer *iob = NULL;
1576  u16 count = (status & GMR_FS_LEN) >> 16;
1577 
1578  DBGIO(PFX "%s: rx slot %d status 0x%x len %d\n",
1579  dev->name, sky2->rx_next, status, length);
1580 
1581  sky2->rx_next = (sky2->rx_next + 1) % RX_PENDING;
1582 
1583  /* This chip has hardware problems that generates bogus status.
1584  * So do only marginal checking and expect higher level protocols
1585  * to handle crap frames.
1586  */
1587  if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
1588  sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
1589  length == count)
1590  goto okay;
1591 
1592  if (status & GMR_FS_ANY_ERR)
1593  goto error;
1594 
1595  if (!(status & GMR_FS_RX_OK))
1596  goto resubmit;
1597 
1598  /* if length reported by DMA does not match PHY, packet was truncated */
1599  if (length != count)
1600  goto len_error;
1601 
1602 okay:
1603  iob = receive_new(sky2, re, length);
1604 resubmit:
1605  sky2_rx_submit(sky2, re);
1606 
1607  return iob;
1608 
1609 len_error:
1610  /* Truncation of overlength packets
1611  causes PHY length to not match MAC length */
1612  DBG2(PFX "%s: rx length error: status %#x length %d\n",
1613  dev->name, status, length);
1614 
1615  /* Pass NULL as iob because we want to keep our iob in the
1616  ring for the next packet. */
1617  netdev_rx_err(dev, NULL, -EINVAL);
1618  goto resubmit;
1619 
1620 error:
1621  if (status & GMR_FS_RX_FF_OV) {
1622  DBG2(PFX "%s: FIFO overflow error\n", dev->name);
1623  netdev_rx_err(dev, NULL, -EBUSY);
1624  goto resubmit;
1625  }
1626 
1627  DBG2(PFX "%s: rx error, status 0x%x length %d\n",
1628  dev->name, status, length);
1629  netdev_rx_err(dev, NULL, -EIO);
1630 
1631  goto resubmit;
1632 }
1633 
1634 /* Transmit complete */
1635 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1636 {
1637  struct sky2_port *sky2 = netdev_priv(dev);
1638 
1639  sky2_tx_complete(sky2, last);
1640 }
1641 
1642 /* Process status response ring */
1643 static void sky2_status_intr(struct sky2_hw *hw, u16 idx)
1644 {
1645  unsigned rx[2] = { 0, 0 };
1646 
1647  rmb();
1648  do {
1649  struct sky2_status_le *le = hw->st_le + hw->st_idx;
1650  unsigned port;
1651  struct net_device *dev;
1652  struct io_buffer *iob;
1653  u32 status;
1654  u16 length;
1655  u8 opcode = le->opcode;
1656 
1657  if (!(opcode & HW_OWNER))
1658  break;
1659 
1660  port = le->css & CSS_LINK_BIT;
1661  dev = hw->dev[port];
1662  length = le16_to_cpu(le->length);
1663  status = le32_to_cpu(le->status);
1664 
1665  hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1666 
1667  le->opcode = 0;
1668  switch (opcode & ~HW_OWNER) {
1669  case OP_RXSTAT:
1670  ++rx[port];
1671  iob = sky2_receive(dev, length, status);
1672  if (!iob) {
1673  netdev_rx_err(dev, NULL, -ENOMEM);
1674  break;
1675  }
1676 
1677  netdev_rx(dev, iob);
1678  break;
1679 
1680  case OP_RXCHKS:
1681  DBG2(PFX "status OP_RXCHKS but checksum offloading disabled\n");
1682  break;
1683 
1684  case OP_TXINDEXLE:
1685  /* TX index reports status for both ports */
1686  assert(TX_RING_SIZE <= 0x1000);
1687  sky2_tx_done(hw->dev[0], status & 0xfff);
1688  if (hw->dev[1])
1689  sky2_tx_done(hw->dev[1],
1690  ((status >> 24) & 0xff)
1691  | (u16)(length & 0xf) << 8);
1692  break;
1693 
1694  default:
1695  DBG(PFX "unknown status opcode 0x%x\n", opcode);
1696  }
1697  } while (hw->st_idx != idx);
1698 
1699  /* Fully processed status ring so clear irq */
1701 
1702  if (rx[0])
1703  sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
1704 
1705  if (rx[1])
1706  sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
1707 }
1708 
1709 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1710 {
1711  struct net_device *dev = hw->dev[port];
1712 
1713  DBGIO(PFX "%s: hw error interrupt status 0x%x\n", dev->name, status);
1714 
1715  if (status & Y2_IS_PAR_RD1) {
1716  DBG(PFX "%s: ram data read parity error\n", dev->name);
1717  /* Clear IRQ */
1719  }
1720 
1721  if (status & Y2_IS_PAR_WR1) {
1722  DBG(PFX "%s: ram data write parity error\n", dev->name);
1724  }
1725 
1726  if (status & Y2_IS_PAR_MAC1) {
1727  DBG(PFX "%s: MAC parity error\n", dev->name);
1729  }
1730 
1731  if (status & Y2_IS_PAR_RX1) {
1732  DBG(PFX "%s: RX parity error\n", dev->name);
1734  }
1735 
1736  if (status & Y2_IS_TCP_TXA1) {
1737  DBG(PFX "%s: TCP segmentation error\n", dev->name);
1739  }
1740 }
1741 
1742 static void sky2_hw_intr(struct sky2_hw *hw)
1743 {
1745  u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1746 
1747  status &= hwmsk;
1748 
1749  if (status & Y2_IS_TIST_OV)
1751 
1752  if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1753  u16 pci_err;
1754 
1756  pci_err = sky2_pci_read16(hw, PCI_STATUS);
1757  DBG(PFX "PCI hardware error (0x%x)\n", pci_err);
1758 
1760  pci_err | PCI_STATUS_ERROR_BITS);
1762  }
1763 
1764  if (status & Y2_IS_PCI_EXP) {
1765  /* PCI-Express uncorrectable Error occurred */
1766  u32 err;
1767 
1771  0xfffffffful);
1772  DBG(PFX "PCI-Express error (0x%x)\n", err);
1773 
1776  }
1777 
1778  if (status & Y2_HWE_L1_MASK)
1779  sky2_hw_error(hw, 0, status);
1780  status >>= 8;
1781  if (status & Y2_HWE_L1_MASK)
1782  sky2_hw_error(hw, 1, status);
1783 }
1784 
1785 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1786 {
1787  struct net_device *dev = hw->dev[port];
1789 
1790  DBGIO(PFX "%s: mac interrupt status 0x%x\n", dev->name, status);
1791 
1792  if (status & GM_IS_RX_CO_OV)
1794 
1795  if (status & GM_IS_TX_CO_OV)
1797 
1798  if (status & GM_IS_RX_FF_OR) {
1800  }
1801 
1802  if (status & GM_IS_TX_FF_UR) {
1804  }
1805 }
1806 
1807 /* This should never happen it is a bug. */
1808 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
1809  u16 q, unsigned ring_size __unused)
1810 {
1811  struct net_device *dev = hw->dev[port];
1812  struct sky2_port *sky2 = netdev_priv(dev);
1813  int idx;
1814  const u64 *le = (q == Q_R1 || q == Q_R2)
1815  ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
1816 
1818  DBG(PFX "%s: descriptor error q=%#x get=%d [%llx] last=%d put=%d should be %d\n",
1819  dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
1822  le == (u64 *)sky2->rx_le? sky2->rx_put : sky2->tx_prod);
1823 
1825 }
1826 
1827 /* Hardware/software error handling */
1828 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
1829 {
1830  DBG(PFX "error interrupt status=%#x\n", status);
1831 
1832  if (status & Y2_IS_HW_ERR)
1833  sky2_hw_intr(hw);
1834 
1835  if (status & Y2_IS_IRQ_MAC1)
1836  sky2_mac_intr(hw, 0);
1837 
1838  if (status & Y2_IS_IRQ_MAC2)
1839  sky2_mac_intr(hw, 1);
1840 
1841  if (status & Y2_IS_CHK_RX1)
1843 
1844  if (status & Y2_IS_CHK_RX2)
1846 
1847  if (status & Y2_IS_CHK_TXA1)
1849 
1850  if (status & Y2_IS_CHK_TXA2)
1852 }
1853 
1854 static void sky2_poll(struct net_device *dev)
1855 {
1856  struct sky2_port *sky2 = netdev_priv(dev);
1857  struct sky2_hw *hw = sky2->hw;
1859  u16 idx;
1860 
1861  if (status & Y2_IS_ERROR)
1863 
1864  if (status & Y2_IS_IRQ_PHY1)
1865  sky2_phy_intr(hw, 0);
1866 
1867  if (status & Y2_IS_IRQ_PHY2)
1868  sky2_phy_intr(hw, 1);
1869 
1870  while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
1871  sky2_status_intr(hw, idx);
1872  }
1873 
1874  /* Bug/Errata workaround?
1875  * Need to kick the TX irq moderation timer.
1876  */
1880  }
1882 }
1883 
1884 /* Chip internal frequency for clock calculations */
1885 static u32 sky2_mhz(const struct sky2_hw *hw)
1886 {
1887  switch (hw->chip_id) {
1888  case CHIP_ID_YUKON_EC:
1889  case CHIP_ID_YUKON_EC_U:
1890  case CHIP_ID_YUKON_EX:
1891  case CHIP_ID_YUKON_SUPR:
1892  case CHIP_ID_YUKON_UL_2:
1893  return 125;
1894 
1895  case CHIP_ID_YUKON_FE:
1896  return 100;
1897 
1898  case CHIP_ID_YUKON_FE_P:
1899  return 50;
1900 
1901  case CHIP_ID_YUKON_XL:
1902  return 156;
1903 
1904  default:
1905  DBG(PFX "unknown chip ID!\n");
1906  return 100; /* bogus */
1907  }
1908 }
1909 
1910 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1911 {
1912  return sky2_mhz(hw) * us;
1913 }
1914 
1915 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
1916 {
1917  return clk / sky2_mhz(hw);
1918 }
1919 
1920 static int sky2_init(struct sky2_hw *hw)
1921 {
1922  u8 t8;
1923 
1924  /* Enable all clocks and check for bad PCI access */
1926 
1928 
1929  hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1930  hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1931 
1932  switch(hw->chip_id) {
1933  case CHIP_ID_YUKON_XL:
1935  break;
1936 
1937  case CHIP_ID_YUKON_EC_U:
1938  hw->flags = SKY2_HW_GIGABIT
1941  break;
1942 
1943  case CHIP_ID_YUKON_EX:
1944  hw->flags = SKY2_HW_GIGABIT
1946  | SKY2_HW_NEW_LE
1948  break;
1949 
1950  case CHIP_ID_YUKON_EC:
1951  /* This rev is really old, and requires untested workarounds */
1952  if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
1953  DBG(PFX "unsupported revision Yukon-EC rev A1\n");
1954  return -EOPNOTSUPP;
1955  }
1956  hw->flags = SKY2_HW_GIGABIT;
1957  break;
1958 
1959  case CHIP_ID_YUKON_FE:
1960  break;
1961 
1962  case CHIP_ID_YUKON_FE_P:
1963  hw->flags = SKY2_HW_NEWER_PHY
1964  | SKY2_HW_NEW_LE
1967  break;
1968 
1969  case CHIP_ID_YUKON_SUPR:
1970  hw->flags = SKY2_HW_GIGABIT
1972  | SKY2_HW_NEW_LE
1975  break;
1976 
1977  case CHIP_ID_YUKON_UL_2:
1978  hw->flags = SKY2_HW_GIGABIT
1980  break;
1981 
1982  default:
1983  DBG(PFX "unsupported chip type 0x%x\n", hw->chip_id);
1984  return -EOPNOTSUPP;
1985  }
1986 
1987  hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
1988  if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
1989  hw->flags |= SKY2_HW_FIBRE_PHY;
1990 
1991  hw->ports = 1;
1992  t8 = sky2_read8(hw, B2_Y2_HW_RES);
1993  if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1995  ++hw->ports;
1996  }
1997 
1998  return 0;
1999 }
2000 
2001 static void sky2_reset(struct sky2_hw *hw)
2002 {
2003  u16 status;
2004  int i, cap;
2005  u32 hwe_mask = Y2_HWE_ALL_MASK;
2006 
2007  /* disable ASF */
2008  if (hw->chip_id == CHIP_ID_YUKON_EX) {
2013  } else
2016 
2017  /* do a SW reset */
2020 
2021  /* allow writes to PCI config */
2023 
2024  /* clear PCI errors, if any */
2028 
2030 
2031  cap = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
2032  if (cap) {
2034  0xfffffffful);
2035 
2036  /* If an error bit is stuck on ignore it */
2038  DBG(PFX "ignoring stuck error report bit\n");
2039  else
2040  hwe_mask |= Y2_IS_PCI_EXP;
2041  }
2042 
2043  sky2_power_on(hw);
2045 
2046  for (i = 0; i < hw->ports; i++) {
2049 
2050  if (hw->chip_id == CHIP_ID_YUKON_EX ||
2051  hw->chip_id == CHIP_ID_YUKON_SUPR)
2054  | GMC_BYP_RETR_ON);
2055  }
2056 
2057  /* Clear I2C IRQ noise */
2058  sky2_write32(hw, B2_I2C_IRQ, 1);
2059 
2060  /* turn off hardware timer (unused) */
2063 
2065 
2066  /* Turn off descriptor polling */
2068 
2069  /* Turn off receive timestamp */
2072 
2073  /* enable the Tx Arbiters */
2074  for (i = 0; i < hw->ports; i++)
2076 
2077  /* Initialize ram interface */
2078  for (i = 0; i < hw->ports; i++) {
2080 
2093  }
2094 
2095  sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2096 
2097  for (i = 0; i < hw->ports; i++)
2098  sky2_gmac_reset(hw, i);
2099 
2100  memset(hw->st_le, 0, STATUS_LE_BYTES);
2101  hw->st_idx = 0;
2102 
2105 
2106  sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2107  sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2108 
2109  /* Set the list last index */
2111 
2113  sky2_write8(hw, STAT_FIFO_WM, 16);
2114 
2115  /* set Status-FIFO ISR watermark */
2116  if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2118  else
2120 
2124 
2125  /* enable status unit */
2127 
2131 }
2132 
2133 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2134 {
2135  if (sky2_is_copper(hw)) {
2136  u32 modes = SUPPORTED_10baseT_Half
2141 
2142  if (hw->flags & SKY2_HW_GIGABIT)
2143  modes |= SUPPORTED_1000baseT_Half
2145  return modes;
2146  } else
2150  | SUPPORTED_FIBRE;
2151 }
2152 
2153 static void sky2_set_multicast(struct net_device *dev)
2154 {
2155  struct sky2_port *sky2 = netdev_priv(dev);
2156  struct sky2_hw *hw = sky2->hw;
2157  unsigned port = sky2->port;
2158  u16 reg;
2159  u8 filter[8];
2160 
2162  reg |= GM_RXCR_UCF_ENA;
2163 
2164  memset(filter, 0xff, sizeof(filter));
2165 
2167  (u16) filter[0] | ((u16) filter[1] << 8));
2169  (u16) filter[2] | ((u16) filter[3] << 8));
2171  (u16) filter[4] | ((u16) filter[5] << 8));
2173  (u16) filter[6] | ((u16) filter[7] << 8));
2174 
2176 }
2177 
2178 /* Initialize network device */
2179 static struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2180  unsigned port)
2181 {
2182  struct sky2_port *sky2;
2183  struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2184 
2185  if (!dev) {
2186  DBG(PFX "etherdev alloc failed\n");
2187  return NULL;
2188  }
2189 
2190  dev->dev = &hw->pdev->dev;
2191 
2192  sky2 = netdev_priv(dev);
2193  sky2->netdev = dev;
2194  sky2->hw = hw;
2195 
2196  /* Auto speed and flow control */
2197  sky2->autoneg = AUTONEG_ENABLE;
2198  sky2->flow_mode = FC_BOTH;
2199 
2200  sky2->duplex = -1;
2201  sky2->speed = -1;
2203 
2204  hw->dev[port] = dev;
2205 
2206  sky2->port = port;
2207 
2208  /* read the mac address */
2209  memcpy(dev->hw_addr, (void *)(hw->regs + B2_MAC_1 + port * 8), ETH_ALEN);
2210 
2211  return dev;
2212 }
2213 
2214 static void sky2_show_addr(struct net_device *dev)
2215 {
2216  DBG2(PFX "%s: addr %s\n", dev->name, netdev_addr(dev));
2217 }
2218 
2219 #if DBGLVL_MAX
2220 /* This driver supports yukon2 chipset only */
2221 static const char *sky2_name(u8 chipid, char *buf, int sz)
2222 {
2223  const char *name[] = {
2224  "XL", /* 0xb3 */
2225  "EC Ultra", /* 0xb4 */
2226  "Extreme", /* 0xb5 */
2227  "EC", /* 0xb6 */
2228  "FE", /* 0xb7 */
2229  "FE+", /* 0xb8 */
2230  "Supreme", /* 0xb9 */
2231  "UL 2", /* 0xba */
2232  };
2233 
2234  if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_UL_2)
2235  strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
2236  else
2237  snprintf(buf, sz, "(chip %#x)", chipid);
2238  return buf;
2239 }
2240 #endif
2241 
2242 static void sky2_net_irq(struct net_device *dev, int enable)
2243 {
2244  struct sky2_port *sky2 = netdev_priv(dev);
2245  struct sky2_hw *hw = sky2->hw;
2246 
2247  u32 imask = sky2_read32(hw, B0_IMSK);
2248  if (enable)
2249  imask |= portirq_msk[sky2->port];
2250  else
2251  imask &= ~portirq_msk[sky2->port];
2252  sky2_write32(hw, B0_IMSK, imask);
2253 }
2254 
2256  .open = sky2_up,
2257  .close = sky2_down,
2258  .transmit = sky2_xmit_frame,
2259  .poll = sky2_poll,
2260  .irq = sky2_net_irq
2261 };
2262 
2263 static int sky2_probe(struct pci_device *pdev)
2264 {
2265  struct net_device *dev;
2266  struct sky2_hw *hw;
2267  int err;
2268  char buf1[16] __unused; /* only for debugging */
2269 
2271 
2272  err = -ENOMEM;
2273  hw = zalloc(sizeof(*hw));
2274  if (!hw) {
2275  DBG(PFX "cannot allocate hardware struct\n");
2276  goto err_out;
2277  }
2278 
2279  hw->pdev = pdev;
2280 
2281  hw->regs = (unsigned long)pci_ioremap(pdev, pci_bar_start(pdev, PCI_BASE_ADDRESS_0), 0x4000);
2282  if (!hw->regs) {
2283  DBG(PFX "cannot map device registers\n");
2284  goto err_out_free_hw;
2285  }
2286 
2287  /* ring for status responses */
2289  if (!hw->st_le)
2290  goto err_out_iounmap;
2291  hw->st_dma = virt_to_bus(hw->st_le);
2292  memset(hw->st_le, 0, STATUS_LE_BYTES);
2293 
2294  err = sky2_init(hw);
2295  if (err)
2296  goto err_out_iounmap;
2297 
2298 #if DBGLVL_MAX
2299  DBG2(PFX "Yukon-2 %s chip revision %d\n",
2300  sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
2301 #endif
2302 
2303  sky2_reset(hw);
2304 
2305  dev = sky2_init_netdev(hw, 0);
2306  if (!dev) {
2307  err = -ENOMEM;
2308  goto err_out_free_pci;
2309  }
2310 
2312 
2313  err = register_netdev(dev);
2314  if (err) {
2315  DBG(PFX "cannot register net device\n");
2316  goto err_out_free_netdev;
2317  }
2318 
2320 
2322 
2323  if (hw->ports > 1) {
2324  struct net_device *dev1;
2325 
2326  dev1 = sky2_init_netdev(hw, 1);
2327  if (!dev1)
2328  DBG(PFX "allocation for second device failed\n");
2329  else if ((err = register_netdev(dev1))) {
2330  DBG(PFX "register of second port failed (%d)\n", err);
2331  hw->dev[1] = NULL;
2332  netdev_nullify(dev1);
2333  netdev_put(dev1);
2334  } else
2335  sky2_show_addr(dev1);
2336  }
2337 
2338  pci_set_drvdata(pdev, hw);
2339 
2340  return 0;
2341 
2342 err_out_free_netdev:
2344  netdev_put(dev);
2345 err_out_free_pci:
2347  free_phys(hw->st_le, STATUS_LE_BYTES);
2348 err_out_iounmap:
2349  iounmap((void *)hw->regs);
2350 err_out_free_hw:
2351  free(hw);
2352 err_out:
2353  pci_set_drvdata(pdev, NULL);
2354  return err;
2355 }
2356 
2357 static void sky2_remove(struct pci_device *pdev)
2358 {
2359  struct sky2_hw *hw = pci_get_drvdata(pdev);
2360  int i;
2361 
2362  if (!hw)
2363  return;
2364 
2365  for (i = hw->ports-1; i >= 0; --i)
2366  unregister_netdev(hw->dev[i]);
2367 
2368  sky2_write32(hw, B0_IMSK, 0);
2369 
2370  sky2_power_aux(hw);
2371 
2374  sky2_read8(hw, B0_CTST);
2375 
2376  free_phys(hw->st_le, STATUS_LE_BYTES);
2377 
2378  for (i = hw->ports-1; i >= 0; --i) {
2379  netdev_nullify(hw->dev[i]);
2380  netdev_put(hw->dev[i]);
2381  }
2382 
2383  iounmap((void *)hw->regs);
2384  free(hw);
2385 
2387 }
2388 
2389 struct pci_driver sky2_driver __pci_driver = {
2390  .ids = sky2_id_table,
2391  .id_count = (sizeof (sky2_id_table) / sizeof (sky2_id_table[0])),
2392  .probe = sky2_probe,
2393  .remove = sky2_remove
2394 };
#define SPEED_1000
Definition: atl1e.h:52
u32 rx_le_map
Definition: sky2.h:2056
uint16_t u16
Definition: stdint.h:21
#define LPA_PAUSE_CAP
Definition: mii.h:104
Definition: skge.h:108
#define EINVAL
Invalid argument.
Definition: errno.h:428
u16 length
Definition: sky2.h:9
#define PHY_M_POLC_LS1_P_MIX(x)
Definition: sky2.h:1346
static u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
Definition: sky2.h:2101
#define PFX
Definition: sky2.c:46
static void * netdev_priv(struct net_device *netdev)
Get driver private area for this network device.
Definition: netdevice.h:572
static void sky2_free_rings(struct sky2_port *sky2)
Definition: sky2.c:1113
const char * name
Definition: ath9k_hw.c:1984
struct sky2_hw * hw
Definition: sky2.h:2040
static void netdev_tx_complete(struct net_device *netdev, struct io_buffer *iobuf)
Complete network transmission.
Definition: netdevice.h:752
#define SKY2_HW_NEWER_PHY
Definition: sky2.h:2074
static void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
Definition: sky2.c:1034
wmb()
static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
Definition: sky2.c:158
static struct sky2_tx_le * get_tx_le(struct sky2_port *sky2)
Definition: sky2.c:868
#define iob_put(iobuf, len)
Definition: iobuf.h:120
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:527
#define IPG_DATA_DEF
Definition: skge.h:1858
u8 chip_rev
Definition: sky2.h:2081
static void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
Definition: sky2.h:2111
Definition: sky2.h:637
A PCI driver.
Definition: pci.h:227
#define EBUSY
Device or resource busy.
Definition: errno.h:338
static void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
Definition: skge.h:2607
#define PHY_M_PC_DSC(x)
Definition: sky2.h:1304
static u32 sky2_supported_modes(const struct sky2_hw *hw)
Definition: sky2.c:2133
static const u16 copper_fc_adv[]
Definition: sky2.c:273
static unsigned int unsigned int reg
Definition: myson.h:162
#define GM_SMI_CT_PHY_AD(x)
Definition: skge.h:1869
#define PHY_M_LED_MO_RX(x)
Definition: skge.h:1567
#define SUPPORTED_1000baseT_Half
Definition: skge.h:62
static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:1785
Definition: sky2.h:432
Definition: sky2.h:2036
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:36
#define SKY2_HW_ADV_POWER_CTL
Definition: sky2.h:2078
uint8_t opcode
Opcode.
Definition: ena.h:16
#define RX_PENDING
Definition: sky2.c:64
#define RX_LE_BYTES
Definition: sky2.c:62
static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
Definition: sky2.c:1462
static const u32 portirq_msk[]
Definition: sky2.c:126
UINT8_t filter
Receive packet filter.
Definition: pxe_api.h:68
Error codes.
#define SUPPORTED_Autoneg
Definition: skge.h:64
#define TX_COL_THR(x)
Definition: skge.h:1818
u8 ctrl
Definition: sky2.h:2009
I/O buffers.
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:146
static struct tx_ring_info * tx_le_re(struct sky2_port *sky2, struct sky2_tx_le *le)
Definition: sky2.c:888
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:229
Definition: skge.h:540
#define ADVERTISED_100baseT_Half
Definition: bnx2.h:44
static u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
Definition: sky2.h:2157
struct arbelprm_completion_with_error error
Definition: arbel.h:12
#define SUPPORTED_100baseT_Full
Definition: skge.h:61
Definition: sky2.h:893
#define TX_BACK_OFF_LIM(x)
Definition: sky2.h:1657
static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:1511
static u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
Definition: sky2.h:2162
char name[40]
Name.
Definition: device.h:75
#define TX_PENDING
Definition: sky2.c:67
u8 opcode
Definition: sky2.h:2003
#define AUTONEG_ENABLE
Definition: bnx2.h:4584
static void sky2_net_irq(struct net_device *dev, int enable)
Definition: sky2.c:2242
static void sky2_tx_clean(struct net_device *dev)
Definition: sky2.c:1304
static void *__malloc malloc_phys(size_t size, size_t phys_align)
Allocate memory with specified physical alignment.
Definition: malloc.h:62
#define PCI_BASE_ADDRESS_0
Definition: pci.h:62
Definition: sky2.h:2034
static const u16 gm_fc_disable[]
Definition: sky2.c:289
#define PHY_M_LEDC_INIT_CTRL(x)
Definition: skge.h:1670
static void sky2_link_down(struct sky2_port *sky2)
Definition: sky2.c:1440
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
static void sky2_remove(struct pci_device *pdev)
Definition: sky2.c:2357
u16 rx_put
Definition: sky2.h:2053
static void sky2_status_intr(struct sky2_hw *hw, u16 idx)
Definition: sky2.c:1643
uint8_t head
Head number.
Definition: int13.h:34
Definition: skge.h:496
u16 length
Definition: sky2.h:2008
static u32 sky2_mhz(const struct sky2_hw *hw)
Definition: sky2.c:1885
#define SPEED_10
Definition: atl1e.h:50
static void sky2_err_intr(struct sky2_hw *hw, u32 status)
Definition: sky2.c:1828
#define PHY_M_MAC_MODE_SEL(x)
Definition: sky2.h:1472
#define RING_NEXT(x, s)
Definition: sky2.c:79
static u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
Definition: sky2.h:2096
#define PHY_RETRIES
Definition: sky2.c:74
Definition: sky2.h:1946
Definition: skge.h:558
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:129
static void sky2_rx_clean(struct sky2_port *sky2)
Definition: sky2.c:990
static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:683
struct pci_device * pdev
Definition: sky2.h:2068
static const char * netdev_addr(struct net_device *netdev)
Get printable network device link-layer address.
Definition: netdevice.h:527
Definition: hw.c:16
static const unsigned txqaddr[]
Definition: sky2.c:124
#define PHY_M_FELP_LED2_CTRL(x)
Definition: skge.h:1630
u16 speed
Definition: sky2.h:2059
#define SUPPORTED_10baseT_Half
Definition: skge.h:58
struct sky2_tx_le * tx_le
Definition: sky2.h:2045
static void sky2_rx_submit(struct sky2_port *sky2, const struct rx_ring_info *re)
Definition: sky2.c:926
static struct io_buffer * receive_new(struct sky2_port *sky2, struct rx_ring_info *re, unsigned int length)
Definition: sky2.c:1545
static u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
Definition: sky2.c:1915
static int sky2_probe(struct pci_device *pdev)
Definition: sky2.c:2263
static struct pci_device_id sky2_id_table[]
Definition: sky2.c:81
Dynamic memory allocation.
Definition: skge.h:550
#define ADVERTISED_1000baseT_Half
Definition: bnx2.h:46
#define RB_ADDR(offs, queue)
Definition: skge.h:590
#define PHY_M_POLC_STA0_CTRL(x)
Definition: sky2.h:1351
uint32_t start
Starting offset.
Definition: netvsc.h:12
#define PCI_ERR_UNCOR_STATUS
Uncorrectable error status.
Definition: pci.h:125
static void sky2_rx_add(struct sky2_port *sky2, u8 op, u32 map, unsigned len)
Definition: sky2.c:914
uint8_t status
Status.
Definition: ena.h:16
#define SPEED_100
Definition: atl1e.h:51
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:504
char * strncpy(char *dest, const char *src, size_t max)
Copy string.
Definition: string.c:332
static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
Definition: sky2.c:1281
#define TX_JAM_IPG_VAL(x)
Definition: skge.h:1841
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:341
u16 tx_cons
Definition: sky2.h:2046
#define rmb()
Definition: io.h:484
#define ENOMEM
Not enough space.
Definition: errno.h:534
u8 duplex
Definition: sky2.h:2061
static void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
Definition: sky2.h:2172
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define GM_GPCR_SPEED_1000
Definition: skge.h:1807
Definition: skge.h:82
#define PHY_M_EC_DSC_2(x)
Definition: sky2.h:1291
u8 port
Port number.
Definition: CIB_PRM.h:31
static const u16 fiber_fc_adv[]
Definition: sky2.c:281
static void sky2_set_multicast(struct net_device *dev)
Definition: sky2.c:2153
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, u64 addr, u32 last)
Definition: sky2.c:855
#define ETH_HLEN
Definition: if_ether.h:9
static struct sky2_rx_le * sky2_next_rx(struct sky2_port *sky2)
Definition: sky2.c:904
static void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
Definition: sky2.c:895
#define PHY_M_LEDC_STA0_CTRL(x)
Definition: skge.h:1672
#define PHY_M_LED_BLINK_RT(x)
Definition: skge.h:1528
static struct io_buffer * sky2_rx_alloc(struct sky2_port *sky2)
Definition: sky2.c:1008
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:561
Ethernet protocol.
struct net_device * netdev
Definition: sky2.h:2041
#define PHY_M_EC_M_DSC(x)
Definition: skge.h:1504
#define PCI_STATUS_ERROR_BITS
Definition: skge.h:70
#define ETH_FRAME_LEN
Definition: if_ether.h:11
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:774
#define GMAC_DEF_MSK
Definition: skge.h:2021
u32 addr
Definition: sky2.h:2000
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
u16 rx_data_size
Definition: sky2.h:2054
#define PHY_M_FELP_LED1_CTRL(x)
Definition: skge.h:1631
#define PHY_M_EC_S_DSC(x)
Definition: skge.h:1505
#define DUPLEX_FULL
Definition: bnx2.h:111
uint64_t u64
Definition: stdint.h:25
#define RX_LE_SIZE
Definition: sky2.c:61
static int sky2_up(struct net_device *dev)
Definition: sky2.c:1129
struct tx_ring_info * tx_ring
Definition: sky2.h:2044
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
#define TX_RING_SIZE
Definition: sky2.c:66
static struct tulip_private * tp
Definition: tulip.c:441
#define SUPPORTED_TP
Definition: skge.h:65
u8 autoneg
Definition: sky2.h:2060
#define Y2_QADDR(q, reg)
Definition: sky2.h:679
#define TX_IPG_JAM_DATA(x)
Definition: skge.h:1842
static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:669
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:874
static void sky2_poll(struct net_device *dev)
Definition: sky2.c:1854
#define DBGIO(...)
Definition: compiler.h:549
#define cpu_to_le32(value)
Definition: byteswap.h:107
Definition: skge.h:557
struct rx_ring_info * rx_ring
Definition: sky2.h:2049
static void sky2_rx_stop(struct sky2_port *sky2)
Definition: sky2.c:966
static void sky2_power_on(struct sky2_hw *hw)
Definition: sky2.c:193
#define ADVERTISE_PAUSE_ASYM
Definition: mii.h:82
Definition: skge.h:559
u8 ctrl
Definition: sky2.h:2002
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
#define LPA_PAUSE_ASYM
Definition: mii.h:105
#define PHY_M_POLC_IS0_P_MIX(x)
Definition: sky2.h:1347
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
#define IPG_DATA_VAL(x)
Definition: skge.h:1857
static int tx_dist(unsigned tail, unsigned head)
Definition: sky2.c:1220
static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:297
PCI bus.
#define PHY_M_LED_PULS_DUR(x)
Definition: skge.h:1527
#define SKY2_HW_GIGABIT
Definition: sky2.h:2073
A PCI device.
Definition: pci.h:188
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:697
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:155
static struct net_device * sky2_init_netdev(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:2179
static void sky2_rx_map_iob(struct pci_device *pdev __unused, struct rx_ring_info *re, unsigned size __unused)
Definition: sky2.c:933
#define EOPNOTSUPP
Operation not supported on socket.
Definition: errno.h:604
u16 rx_next
Definition: sky2.h:2052
A network device.
Definition: netdevice.h:352
static void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
Definition: sky2.h:2116
static void sky2_reset(struct sky2_hw *hw)
Definition: sky2.c:2001
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:517
#define TX_JAM_LEN_VAL(x)
Definition: skge.h:1840
static int sky2_is_copper(const struct sky2_hw *hw)
Definition: sky2.h:2090
u32 addr
Definition: sky2.h:8
Definition: sky2.h:192
#define SK_REG(port, reg)
Definition: skge.h:2548
static void rx_set_checksum(struct sky2_port *sky2)
Definition: sky2.c:943
static void sky2_tx_done(struct net_device *dev, u16 last)
Definition: sky2.c:1635
u8 opcode
Definition: sky2.h:2010
#define PCI_STATUS
PCI status.
Definition: pci.h:35
#define SUPPORTED_10baseT_Full
Definition: skge.h:59
#define PHY_M_POLC_LOS_CTRL(x)
Definition: sky2.h:1348
#define ETH_ALEN
Definition: if_ether.h:8
static __always_inline int struct dma_mapping * map
Definition: dma.h:181
A PCI device ID list entry.
Definition: pci.h:152
uint32_t last
Length to read in last segment, or zero.
Definition: pccrc.h:30
Definition: skge.h:523
#define SUPPORTED_100baseT_Half
Definition: skge.h:60
#define le16_to_cpu(value)
Definition: byteswap.h:112
Definition: skge.h:78
static void sky2_down(struct net_device *dev)
Definition: sky2.c:1312
static void sky2_show_addr(struct net_device *dev)
Definition: sky2.c:2214
Definition: skge.h:561
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:97
#define ETH_DATA_ALIGN
Definition: if_ether.h:12
FILE_LICENCE(GPL2_ONLY)
struct pci_driver sky2_driver __pci_driver
Definition: sky2.c:2389
Definition: skge.h:560
void __asmcall int val
Definition: setjmp.h:28
u8 chip_id
Definition: sky2.h:2080
Network device operations.
Definition: netdevice.h:213
#define SKY2_HW_AUTO_TX_SUM
Definition: sky2.h:2077
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:489
unsigned long flags
Definition: sky2.h:2070
struct device * dev
Underlying hardware device.
Definition: netdevice.h:364
enum flow_control flow_mode
Definition: sky2.h:2062
#define PHY_M_FELP_LED0_CTRL(x)
Definition: skge.h:1632
A Fibre Channel name.
Definition: fc.h:29
static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q, unsigned ring_size __unused)
Definition: sky2.c:1808
u32 data_addr
Definition: sky2.h:2028
static int sky2_init(struct sky2_hw *hw)
Definition: sky2.c:1920
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define STATUS_LE_BYTES
Definition: sky2.c:72
struct io_buffer * iob
Definition: sky2.h:2027
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:351
#define SKY2_HW_RAM_BUFFER
Definition: sky2.h:2075
#define SK_RI_TO_53
Definition: skge.h:442
#define PHY_M_LEDC_STA1_CTRL(x)
Definition: skge.h:1671
static u16 gma_read16(const struct skge_hw *hw, int port, int reg)
Definition: skge.h:2596
#define iob_reserve(iobuf, len)
Definition: iobuf.h:67
static uint16_t struct vmbus_xfer_pages_operations * op
Definition: netvsc.h:327
#define STATUS_RING_SIZE
Definition: sky2.c:71
Definition: sky2.h:2066
char name[NETDEV_NAME_LEN]
Name of this network device.
Definition: netdevice.h:362
static int sky2_xmit_frame(struct net_device *dev, struct io_buffer *iob)
Definition: sky2.c:1238
Definition: skge.h:542
uint32_t len
Length.
Definition: ena.h:14
u16 length
Definition: sky2.h:2015
static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:595
unsigned port
Definition: sky2.h:2042
Media Independent Interface constants.
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:240
#define TX_COL_DEF
Definition: skge.h:1819
Definition: sky2.h:2035
static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
Definition: sky2.c:1387
static const u32 coma_mode[]
Definition: sky2.c:593
static const u32 phy_power[]
Definition: sky2.c:592
u32 status
Definition: sky2.h:2014
#define TX_RING_ALIGN
Definition: sky2.c:68
void * data
Start of data.
Definition: iobuf.h:48
#define PHY_M_POLC_STA1_CTRL(x)
Definition: sky2.h:1350
#define EIO
Input/output error.
Definition: errno.h:433
Definition: skge.h:334
#define DATA_BLIND_DEF
Definition: skge.h:1855
#define SUPPORTED_FIBRE
Definition: skge.h:66
uint16_t count
Number of entries.
Definition: ena.h:22
u16 tx_prod
Definition: sky2.h:2047
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define Q_ADDR(reg, offs)
Definition: skge.h:534
u8 ctrl
Definition: sky2.h:10
#define cpu_to_le16(value)
Definition: byteswap.h:106
Definition: skge.h:128
Definition: skge.h:562
Definition: sky2.h:634
uint32_t end
Ending offset.
Definition: netvsc.h:18
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
static void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
Definition: sky2.h:2121
void iounmap(volatile const void *io_addr)
Unmap I/O address.
static void sky2_link_up(struct sky2_port *sky2)
Definition: sky2.c:1409
struct sky2_rx_le * rx_le
Definition: sky2.h:2050
#define SUPPORTED_1000baseT_Full
Definition: skge.h:63
#define ADVERTISED_10baseT_Full
Definition: bnx2.h:43
Definition: sky2.h:638
struct io_buffer * iob
Definition: sky2.h:2021
u32 addr
Definition: sky2.h:2007
static struct net_device_operations sky2_operations
Definition: sky2.c:2255
#define GM_SMI_CT_REG_AD(x)
Definition: skge.h:1870
#define AUTONEG_DISABLE
Definition: bnx2.h:4583
int snprintf(char *buf, size_t size, const char *fmt,...)
Write a formatted string to a buffer.
Definition: vsprintf.c:382
static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:255
u16 length
Definition: sky2.h:2001
static void free_phys(void *ptr, size_t size)
Free memory allocated with malloc_phys()
Definition: malloc.h:77
#define RX_RING_ALIGN
Definition: sky2.c:63
#define PHY_M_EC_MAC_S(x)
Definition: skge.h:1506
void mb(void)
Memory barrier.
static struct io_buffer * sky2_receive(struct net_device *dev, u16 length, u32 status)
Definition: sky2.c:1570
#define ADVERTISE_PAUSE_CAP
Definition: mii.h:81
u16 advertising
Definition: sky2.h:2058
#define DATA_BLIND_VAL(x)
Definition: skge.h:1854
#define STATUS_RING_ALIGN
Definition: sky2.c:73
static void tx_init(struct sky2_port *sky2)
Definition: sky2.c:877
static void gma_set_addr(struct skge_hw *hw, int port, int reg, const u8 *addr)
Definition: skge.h:2612
#define SKY2_HW_FIBRE_PHY
Definition: sky2.h:2072
static void sky2_qset(struct sky2_hw *hw, u16 q)
Definition: sky2.c:844
#define PHY_M_LEDC_LOS_CTRL(x)
Definition: skge.h:1669
#define RAM_BUFFER(port, reg)
Definition: sky2.h:245
static int sky2_rx_start(struct sky2_port *sky2)
Definition: sky2.c:1045
struct net_device * dev[2]
Definition: sky2.h:2069
#define PHY_M_PC_MDI_XMODE(x)
Definition: sky2.h:1185
static int tx_avail(const struct sky2_port *sky2)
Definition: sky2.c:1226
static void sky2_hw_intr(struct sky2_hw *hw)
Definition: sky2.c:1742
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define GM_GPCR_AU_ALL_DIS
Definition: skge.h:1808
static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
Definition: sky2.c:1709
static u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
Definition: sky2.h:2106
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static void sky2_power_aux(struct sky2_hw *hw)
Definition: sky2.c:237
#define PHY_M_LED_MO_100(x)
Definition: skge.h:1565
static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
Definition: sky2.c:616
Definition: skge.h:539
#define ADVERTISED_1000baseT_Full
Definition: bnx2.h:47
static const unsigned rxqaddr[]
Definition: sky2.c:125
static u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
Definition: sky2.c:1910
Definition: skge.h:541
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define ADVERTISED_100baseT_Full
Definition: bnx2.h:45
static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
Definition: sky2.c:131
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:286
static void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
Definition: sky2.h:2167
u32 tx_le_map
Definition: sky2.h:2057
struct bofm_section_header done
Definition: bofm_test.c:46
#define ADVERTISED_10baseT_Half
Definition: bnx2.h:42
Definition: sky2.h:642
uint8_t u8
Definition: stdint.h:19
Definition: sky2.h:2033
uint32_t u32
Definition: stdint.h:23
#define CFG_DUAL_MAC_MSK
Definition: sky2.h:525
Definition: skge.h:101
Definition: sky2.h:640
#define PHY_M_POLC_INIT_CTRL(x)
Definition: sky2.h:1349
static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
Definition: sky2.c:804
enum flow_control flow_status
Definition: sky2.h:2063
#define DBG2(...)
Definition: compiler.h:515
if(natsemi->flags &NATSEMI_64BIT) return 1
#define SKY2_HW_NEW_LE
Definition: sky2.h:2076
#define DUPLEX_HALF
Definition: bnx2.h:110
void * memset(void *dest, int character, size_t len) __nonnull
A persistent I/O buffer.
Definition: iobuf.h:33
Definition: sky2.h:771
static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
Definition: sky2.c:185