iPXE
ath5k_phy.c
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00001 /*
00002  * PHY functions
00003  *
00004  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
00005  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
00006  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
00007  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
00008  *
00009  * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
00010  *
00011  * Permission to use, copy, modify, and distribute this software for any
00012  * purpose with or without fee is hereby granted, provided that the above
00013  * copyright notice and this permission notice appear in all copies.
00014  *
00015  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00016  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00017  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00018  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00019  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00020  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00021  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00022  *
00023  */
00024 
00025 FILE_LICENCE ( MIT );
00026 
00027 #define _ATH5K_PHY
00028 
00029 #include <unistd.h>
00030 #include <stdlib.h>
00031 
00032 #include "ath5k.h"
00033 #include "reg.h"
00034 #include "base.h"
00035 #include "rfbuffer.h"
00036 #include "rfgain.h"
00037 
00038 static inline int min(int x, int y)
00039 {
00040         return (x < y) ? x : y;
00041 }
00042 
00043 static inline int max(int x, int y)
00044 {
00045         return (x > y) ? x : y;
00046 }
00047 
00048 /*
00049  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
00050  */
00051 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
00052                                         const struct ath5k_rf_reg *rf_regs,
00053                                         u32 val, u8 reg_id, int set)
00054 {
00055         const struct ath5k_rf_reg *rfreg = NULL;
00056         u8 offset, bank, num_bits, col, position;
00057         u16 entry;
00058         u32 mask, data, last_bit, bits_shifted, first_bit;
00059         u32 *rfb;
00060         s32 bits_left;
00061         unsigned i;
00062 
00063         data = 0;
00064         rfb = ah->ah_rf_banks;
00065 
00066         for (i = 0; i < ah->ah_rf_regs_count; i++) {
00067                 if (rf_regs[i].index == reg_id) {
00068                         rfreg = &rf_regs[i];
00069                         break;
00070                 }
00071         }
00072 
00073         if (rfb == NULL || rfreg == NULL) {
00074                 DBG("ath5k: RF register not found!\n");
00075                 /* should not happen */
00076                 return 0;
00077         }
00078 
00079         bank = rfreg->bank;
00080         num_bits = rfreg->field.len;
00081         first_bit = rfreg->field.pos;
00082         col = rfreg->field.col;
00083 
00084         /* first_bit is an offset from bank's
00085          * start. Since we have all banks on
00086          * the same array, we use this offset
00087          * to mark each bank's start */
00088         offset = ah->ah_offset[bank];
00089 
00090         /* Boundary check */
00091         if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
00092                 DBG("ath5k: RF invalid values at offset %d\n", offset);
00093                 return 0;
00094         }
00095 
00096         entry = ((first_bit - 1) / 8) + offset;
00097         position = (first_bit - 1) % 8;
00098 
00099         if (set)
00100                 data = ath5k_hw_bitswap(val, num_bits);
00101 
00102         for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
00103         position = 0, entry++) {
00104 
00105                 last_bit = (position + bits_left > 8) ? 8 :
00106                                         position + bits_left;
00107 
00108                 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
00109                                                                 (col * 8);
00110 
00111                 if (set) {
00112                         rfb[entry] &= ~mask;
00113                         rfb[entry] |= ((data << position) << (col * 8)) & mask;
00114                         data >>= (8 - position);
00115                 } else {
00116                         data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
00117                                 << bits_shifted;
00118                         bits_shifted += last_bit - position;
00119                 }
00120 
00121                 bits_left -= 8 - position;
00122         }
00123 
00124         data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
00125 
00126         return data;
00127 }
00128 
00129 /**********************\
00130 * RF Gain optimization *
00131 \**********************/
00132 
00133 /*
00134  * This code is used to optimize rf gain on different environments
00135  * (temprature mostly) based on feedback from a power detector.
00136  *
00137  * It's only used on RF5111 and RF5112, later RF chips seem to have
00138  * auto adjustment on hw -notice they have a much smaller BANK 7 and
00139  * no gain optimization ladder-.
00140  *
00141  * For more infos check out this patent doc
00142  * http://www.freepatentsonline.com/7400691.html
00143  *
00144  * This paper describes power drops as seen on the receiver due to
00145  * probe packets
00146  * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
00147  * %20of%20Power%20Control.pdf
00148  *
00149  * And this is the MadWiFi bug entry related to the above
00150  * http://madwifi-project.org/ticket/1659
00151  * with various measurements and diagrams
00152  *
00153  * TODO: Deal with power drops due to probes by setting an apropriate
00154  * tx power on the probe packets ! Make this part of the calibration process.
00155  */
00156 
00157 /* Initialize ah_gain durring attach */
00158 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
00159 {
00160         /* Initialize the gain optimization values */
00161         switch (ah->ah_radio) {
00162         case AR5K_RF5111:
00163                 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
00164                 ah->ah_gain.g_low = 20;
00165                 ah->ah_gain.g_high = 35;
00166                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
00167                 break;
00168         case AR5K_RF5112:
00169                 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
00170                 ah->ah_gain.g_low = 20;
00171                 ah->ah_gain.g_high = 85;
00172                 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
00173                 break;
00174         default:
00175                 return -EINVAL;
00176         }
00177 
00178         return 0;
00179 }
00180 
00181 /* Schedule a gain probe check on the next transmited packet.
00182  * That means our next packet is going to be sent with lower
00183  * tx power and a Peak to Average Power Detector (PAPD) will try
00184  * to measure the gain.
00185  *
00186  * TODO: Use propper tx power setting for the probe packet so
00187  * that we don't observe a serious power drop on the receiver
00188  *
00189  * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
00190  * just after we enable the probe so that we don't mess with
00191  * standard traffic ? Maybe it's time to use sw interrupts and
00192  * a probe tasklet !!!
00193  */
00194 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
00195 {
00196 
00197         /* Skip if gain calibration is inactive or
00198          * we already handle a probe request */
00199         if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
00200                 return;
00201 
00202         /* Send the packet with 2dB below max power as
00203          * patent doc suggest */
00204         ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max_pwr - 4,
00205                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
00206                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
00207 
00208         ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
00209 
00210 }
00211 
00212 /* Calculate gain_F measurement correction
00213  * based on the current step for RF5112 rev. 2 */
00214 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
00215 {
00216         u32 mix, step;
00217         const struct ath5k_gain_opt *go;
00218         const struct ath5k_gain_opt_step *g_step;
00219         const struct ath5k_rf_reg *rf_regs;
00220 
00221         /* Only RF5112 Rev. 2 supports it */
00222         if ((ah->ah_radio != AR5K_RF5112) ||
00223         (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
00224                 return 0;
00225 
00226         go = &rfgain_opt_5112;
00227         rf_regs = rf_regs_5112a;
00228         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
00229 
00230         g_step = &go->go_step[ah->ah_gain.g_step_idx];
00231 
00232         if (ah->ah_rf_banks == NULL)
00233                 return 0;
00234 
00235         ah->ah_gain.g_f_corr = 0;
00236 
00237         /* No VGA (Variable Gain Amplifier) override, skip */
00238         if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 0) != 1)
00239                 return 0;
00240 
00241         /* Mix gain stepping */
00242         step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, 0);
00243 
00244         /* Mix gain override */
00245         mix = g_step->gos_param[0];
00246 
00247         switch (mix) {
00248         case 3:
00249                 ah->ah_gain.g_f_corr = step * 2;
00250                 break;
00251         case 2:
00252                 ah->ah_gain.g_f_corr = (step - 5) * 2;
00253                 break;
00254         case 1:
00255                 ah->ah_gain.g_f_corr = step;
00256                 break;
00257         default:
00258                 ah->ah_gain.g_f_corr = 0;
00259                 break;
00260         }
00261 
00262         return ah->ah_gain.g_f_corr;
00263 }
00264 
00265 /* Check if current gain_F measurement is in the range of our
00266  * power detector windows. If we get a measurement outside range
00267  * we know it's not accurate (detectors can't measure anything outside
00268  * their detection window) so we must ignore it */
00269 static int ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
00270 {
00271         const struct ath5k_rf_reg *rf_regs;
00272         u32 step, mix_ovr, level[4];
00273 
00274         if (ah->ah_rf_banks == NULL)
00275                 return 0;
00276 
00277         if (ah->ah_radio == AR5K_RF5111) {
00278 
00279                 rf_regs = rf_regs_5111;
00280                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
00281 
00282                 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
00283                         0);
00284 
00285                 level[0] = 0;
00286                 level[1] = (step == 63) ? 50 : step + 4;
00287                 level[2] = (step != 63) ? 64 : level[0];
00288                 level[3] = level[2] + 50 ;
00289 
00290                 ah->ah_gain.g_high = level[3] -
00291                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
00292                 ah->ah_gain.g_low = level[0] +
00293                         (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
00294         } else {
00295 
00296                 rf_regs = rf_regs_5112;
00297                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
00298 
00299                 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
00300                         0);
00301 
00302                 level[0] = level[2] = 0;
00303 
00304                 if (mix_ovr == 1) {
00305                         level[1] = level[3] = 83;
00306                 } else {
00307                         level[1] = level[3] = 107;
00308                         ah->ah_gain.g_high = 55;
00309                 }
00310         }
00311 
00312         return (ah->ah_gain.g_current >= level[0] &&
00313                         ah->ah_gain.g_current <= level[1]) ||
00314                 (ah->ah_gain.g_current >= level[2] &&
00315                         ah->ah_gain.g_current <= level[3]);
00316 }
00317 
00318 /* Perform gain_F adjustment by choosing the right set
00319  * of parameters from rf gain optimization ladder */
00320 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
00321 {
00322         const struct ath5k_gain_opt *go;
00323         const struct ath5k_gain_opt_step *g_step;
00324         int ret = 0;
00325 
00326         switch (ah->ah_radio) {
00327         case AR5K_RF5111:
00328                 go = &rfgain_opt_5111;
00329                 break;
00330         case AR5K_RF5112:
00331                 go = &rfgain_opt_5112;
00332                 break;
00333         default:
00334                 return 0;
00335         }
00336 
00337         g_step = &go->go_step[ah->ah_gain.g_step_idx];
00338 
00339         if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
00340 
00341                 /* Reached maximum */
00342                 if (ah->ah_gain.g_step_idx == 0)
00343                         return -1;
00344 
00345                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
00346                                 ah->ah_gain.g_target >=  ah->ah_gain.g_high &&
00347                                 ah->ah_gain.g_step_idx > 0;
00348                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
00349                         ah->ah_gain.g_target -= 2 *
00350                             (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
00351                             g_step->gos_gain);
00352 
00353                 ret = 1;
00354                 goto done;
00355         }
00356 
00357         if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
00358 
00359                 /* Reached minimum */
00360                 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
00361                         return -2;
00362 
00363                 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
00364                                 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
00365                                 ah->ah_gain.g_step_idx < go->go_steps_count-1;
00366                                 g_step = &go->go_step[ah->ah_gain.g_step_idx])
00367                         ah->ah_gain.g_target -= 2 *
00368                             (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
00369                             g_step->gos_gain);
00370 
00371                 ret = 2;
00372                 goto done;
00373         }
00374 
00375 done:
00376         DBG2("ath5k RF adjust: ret %d, gain step %d, current gain %d, "
00377              "target gain %d\n", ret, ah->ah_gain.g_step_idx,
00378              ah->ah_gain.g_current, ah->ah_gain.g_target);
00379 
00380         return ret;
00381 }
00382 
00383 /* Main callback for thermal rf gain calibration engine
00384  * Check for a new gain reading and schedule an adjustment
00385  * if needed.
00386  *
00387  * TODO: Use sw interrupt to schedule reset if gain_F needs
00388  * adjustment */
00389 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
00390 {
00391         u32 data, type;
00392         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
00393 
00394         if (ah->ah_rf_banks == NULL ||
00395         ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
00396                 return AR5K_RFGAIN_INACTIVE;
00397 
00398         /* No check requested, either engine is inactive
00399          * or an adjustment is already requested */
00400         if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
00401                 goto done;
00402 
00403         /* Read the PAPD (Peak to Average Power Detector)
00404          * register */
00405         data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
00406 
00407         /* No probe is scheduled, read gain_F measurement */
00408         if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
00409                 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
00410                 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
00411 
00412                 /* If tx packet is CCK correct the gain_F measurement
00413                  * by cck ofdm gain delta */
00414                 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
00415                         if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
00416                                 ah->ah_gain.g_current +=
00417                                         ee->ee_cck_ofdm_gain_delta;
00418                         else
00419                                 ah->ah_gain.g_current +=
00420                                         AR5K_GAIN_CCK_PROBE_CORR;
00421                 }
00422 
00423                 /* Further correct gain_F measurement for
00424                  * RF5112A radios */
00425                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
00426                         ath5k_hw_rf_gainf_corr(ah);
00427                         ah->ah_gain.g_current =
00428                                 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
00429                                 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
00430                                 0;
00431                 }
00432 
00433                 /* Check if measurement is ok and if we need
00434                  * to adjust gain, schedule a gain adjustment,
00435                  * else switch back to the acive state */
00436                 if (ath5k_hw_rf_check_gainf_readback(ah) &&
00437                 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
00438                 ath5k_hw_rf_gainf_adjust(ah)) {
00439                         ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
00440                 } else {
00441                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
00442                 }
00443         }
00444 
00445 done:
00446         return ah->ah_gain.g_state;
00447 }
00448 
00449 /* Write initial rf gain table to set the RF sensitivity
00450  * this one works on all RF chips and has nothing to do
00451  * with gain_F calibration */
00452 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
00453 {
00454         const struct ath5k_ini_rfgain *ath5k_rfg;
00455         unsigned int i, size;
00456 
00457         switch (ah->ah_radio) {
00458         case AR5K_RF5111:
00459                 ath5k_rfg = rfgain_5111;
00460                 size = ARRAY_SIZE(rfgain_5111);
00461                 break;
00462         case AR5K_RF5112:
00463                 ath5k_rfg = rfgain_5112;
00464                 size = ARRAY_SIZE(rfgain_5112);
00465                 break;
00466         case AR5K_RF2413:
00467                 ath5k_rfg = rfgain_2413;
00468                 size = ARRAY_SIZE(rfgain_2413);
00469                 break;
00470         case AR5K_RF2316:
00471                 ath5k_rfg = rfgain_2316;
00472                 size = ARRAY_SIZE(rfgain_2316);
00473                 break;
00474         case AR5K_RF5413:
00475                 ath5k_rfg = rfgain_5413;
00476                 size = ARRAY_SIZE(rfgain_5413);
00477                 break;
00478         case AR5K_RF2317:
00479         case AR5K_RF2425:
00480                 ath5k_rfg = rfgain_2425;
00481                 size = ARRAY_SIZE(rfgain_2425);
00482                 break;
00483         default:
00484                 return -EINVAL;
00485         }
00486 
00487         switch (freq) {
00488         case AR5K_INI_RFGAIN_2GHZ:
00489         case AR5K_INI_RFGAIN_5GHZ:
00490                 break;
00491         default:
00492                 return -EINVAL;
00493         }
00494 
00495         for (i = 0; i < size; i++) {
00496                 AR5K_REG_WAIT(i);
00497                 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
00498                         (u32)ath5k_rfg[i].rfg_register);
00499         }
00500 
00501         return 0;
00502 }
00503 
00504 
00505 
00506 /********************\
00507 * RF Registers setup *
00508 \********************/
00509 
00510 
00511 /*
00512  * Setup RF registers by writing rf buffer on hw
00513  */
00514 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct net80211_channel *channel,
00515                 unsigned int mode)
00516 {
00517         const struct ath5k_rf_reg *rf_regs;
00518         const struct ath5k_ini_rfbuffer *ini_rfb;
00519         const struct ath5k_gain_opt *go = NULL;
00520         const struct ath5k_gain_opt_step *g_step;
00521         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
00522         u8 ee_mode = 0;
00523         u32 *rfb;
00524         int obdb = -1, bank = -1;
00525         unsigned i;
00526 
00527         switch (ah->ah_radio) {
00528         case AR5K_RF5111:
00529                 rf_regs = rf_regs_5111;
00530                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
00531                 ini_rfb = rfb_5111;
00532                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
00533                 go = &rfgain_opt_5111;
00534                 break;
00535         case AR5K_RF5112:
00536                 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
00537                         rf_regs = rf_regs_5112a;
00538                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
00539                         ini_rfb = rfb_5112a;
00540                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
00541                 } else {
00542                         rf_regs = rf_regs_5112;
00543                         ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
00544                         ini_rfb = rfb_5112;
00545                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
00546                 }
00547                 go = &rfgain_opt_5112;
00548                 break;
00549         case AR5K_RF2413:
00550                 rf_regs = rf_regs_2413;
00551                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
00552                 ini_rfb = rfb_2413;
00553                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
00554                 break;
00555         case AR5K_RF2316:
00556                 rf_regs = rf_regs_2316;
00557                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
00558                 ini_rfb = rfb_2316;
00559                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
00560                 break;
00561         case AR5K_RF5413:
00562                 rf_regs = rf_regs_5413;
00563                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
00564                 ini_rfb = rfb_5413;
00565                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
00566                 break;
00567         case AR5K_RF2317:
00568                 rf_regs = rf_regs_2425;
00569                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
00570                 ini_rfb = rfb_2317;
00571                 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
00572                 break;
00573         case AR5K_RF2425:
00574                 rf_regs = rf_regs_2425;
00575                 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
00576                 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
00577                         ini_rfb = rfb_2425;
00578                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
00579                 } else {
00580                         ini_rfb = rfb_2417;
00581                         ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
00582                 }
00583                 break;
00584         default:
00585                 return -EINVAL;
00586         }
00587 
00588         /* If it's the first time we set rf buffer, allocate
00589          * ah->ah_rf_banks based on ah->ah_rf_banks_size
00590          * we set above */
00591         if (ah->ah_rf_banks == NULL) {
00592                 ah->ah_rf_banks = malloc(sizeof(u32) * ah->ah_rf_banks_size);
00593                 if (ah->ah_rf_banks == NULL) {
00594                         return -ENOMEM;
00595                 }
00596         }
00597 
00598         /* Copy values to modify them */
00599         rfb = ah->ah_rf_banks;
00600 
00601         for (i = 0; i < ah->ah_rf_banks_size; i++) {
00602                 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
00603                         DBG("ath5k: invalid RF register bank\n");
00604                         return -EINVAL;
00605                 }
00606 
00607                 /* Bank changed, write down the offset */
00608                 if (bank != ini_rfb[i].rfb_bank) {
00609                         bank = ini_rfb[i].rfb_bank;
00610                         ah->ah_offset[bank] = i;
00611                 }
00612 
00613                 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
00614         }
00615 
00616         /* Set Output and Driver bias current (OB/DB) */
00617         if (channel->hw_value & CHANNEL_2GHZ) {
00618 
00619                 if (channel->hw_value & CHANNEL_CCK)
00620                         ee_mode = AR5K_EEPROM_MODE_11B;
00621                 else
00622                         ee_mode = AR5K_EEPROM_MODE_11G;
00623 
00624                 /* For RF511X/RF211X combination we
00625                  * use b_OB and b_DB parameters stored
00626                  * in eeprom on ee->ee_ob[ee_mode][0]
00627                  *
00628                  * For all other chips we use OB/DB for 2Ghz
00629                  * stored in the b/g modal section just like
00630                  * 802.11a on ee->ee_ob[ee_mode][1] */
00631                 if ((ah->ah_radio == AR5K_RF5111) ||
00632                 (ah->ah_radio == AR5K_RF5112))
00633                         obdb = 0;
00634                 else
00635                         obdb = 1;
00636 
00637                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
00638                                                 AR5K_RF_OB_2GHZ, 1);
00639 
00640                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
00641                                                 AR5K_RF_DB_2GHZ, 1);
00642 
00643         /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
00644         } else if ((channel->hw_value & CHANNEL_5GHZ) ||
00645                         (ah->ah_radio == AR5K_RF5111)) {
00646 
00647                 /* For 11a, Turbo and XR we need to choose
00648                  * OB/DB based on frequency range */
00649                 ee_mode = AR5K_EEPROM_MODE_11A;
00650                 obdb =   channel->center_freq >= 5725 ? 3 :
00651                         (channel->center_freq >= 5500 ? 2 :
00652                         (channel->center_freq >= 5260 ? 1 :
00653                          (channel->center_freq > 4000 ? 0 : -1)));
00654 
00655                 if (obdb < 0)
00656                         return -EINVAL;
00657 
00658                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
00659                                                 AR5K_RF_OB_5GHZ, 1);
00660 
00661                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
00662                                                 AR5K_RF_DB_5GHZ, 1);
00663         }
00664 
00665         g_step = &go->go_step[ah->ah_gain.g_step_idx];
00666 
00667         /* Bank Modifications (chip-specific) */
00668         if (ah->ah_radio == AR5K_RF5111) {
00669 
00670                 /* Set gain_F settings according to current step */
00671                 if (channel->hw_value & CHANNEL_OFDM) {
00672 
00673                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
00674                                         AR5K_PHY_FRAME_CTL_TX_CLIP,
00675                                         g_step->gos_param[0]);
00676 
00677                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
00678                                                         AR5K_RF_PWD_90, 1);
00679 
00680                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
00681                                                         AR5K_RF_PWD_84, 1);
00682 
00683                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
00684                                                 AR5K_RF_RFGAIN_SEL, 1);
00685 
00686                         /* We programmed gain_F parameters, switch back
00687                          * to active state */
00688                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
00689 
00690                 }
00691 
00692                 /* Bank 6/7 setup */
00693 
00694                 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
00695                                                 AR5K_RF_PWD_XPD, 1);
00696 
00697                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
00698                                                 AR5K_RF_XPD_GAIN, 1);
00699 
00700                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
00701                                                 AR5K_RF_GAIN_I, 1);
00702 
00703                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
00704                                                 AR5K_RF_PLO_SEL, 1);
00705 
00706                 /* TODO: Half/quarter channel support */
00707         }
00708 
00709         if (ah->ah_radio == AR5K_RF5112) {
00710 
00711                 /* Set gain_F settings according to current step */
00712                 if (channel->hw_value & CHANNEL_OFDM) {
00713 
00714                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
00715                                                 AR5K_RF_MIXGAIN_OVR, 1);
00716 
00717                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
00718                                                 AR5K_RF_PWD_138, 1);
00719 
00720                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
00721                                                 AR5K_RF_PWD_137, 1);
00722 
00723                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
00724                                                 AR5K_RF_PWD_136, 1);
00725 
00726                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
00727                                                 AR5K_RF_PWD_132, 1);
00728 
00729                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
00730                                                 AR5K_RF_PWD_131, 1);
00731 
00732                         ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
00733                                                 AR5K_RF_PWD_130, 1);
00734 
00735                         /* We programmed gain_F parameters, switch back
00736                          * to active state */
00737                         ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
00738                 }
00739 
00740                 /* Bank 6/7 setup */
00741 
00742                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
00743                                                 AR5K_RF_XPD_SEL, 1);
00744 
00745                 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
00746                         /* Rev. 1 supports only one xpd */
00747                         ath5k_hw_rfb_op(ah, rf_regs,
00748                                                 ee->ee_x_gain[ee_mode],
00749                                                 AR5K_RF_XPD_GAIN, 1);
00750 
00751                 } else {
00752                         /* TODO: Set high and low gain bits */
00753                         ath5k_hw_rfb_op(ah, rf_regs,
00754                                                 ee->ee_x_gain[ee_mode],
00755                                                 AR5K_RF_PD_GAIN_LO, 1);
00756                         ath5k_hw_rfb_op(ah, rf_regs,
00757                                                 ee->ee_x_gain[ee_mode],
00758                                                 AR5K_RF_PD_GAIN_HI, 1);
00759 
00760                         /* Lower synth voltage on Rev 2 */
00761                         ath5k_hw_rfb_op(ah, rf_regs, 2,
00762                                         AR5K_RF_HIGH_VC_CP, 1);
00763 
00764                         ath5k_hw_rfb_op(ah, rf_regs, 2,
00765                                         AR5K_RF_MID_VC_CP, 1);
00766 
00767                         ath5k_hw_rfb_op(ah, rf_regs, 2,
00768                                         AR5K_RF_LOW_VC_CP, 1);
00769 
00770                         ath5k_hw_rfb_op(ah, rf_regs, 2,
00771                                         AR5K_RF_PUSH_UP, 1);
00772 
00773                         /* Decrease power consumption on 5213+ BaseBand */
00774                         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
00775                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
00776                                                 AR5K_RF_PAD2GND, 1);
00777 
00778                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
00779                                                 AR5K_RF_XB2_LVL, 1);
00780 
00781                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
00782                                                 AR5K_RF_XB5_LVL, 1);
00783 
00784                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
00785                                                 AR5K_RF_PWD_167, 1);
00786 
00787                                 ath5k_hw_rfb_op(ah, rf_regs, 1,
00788                                                 AR5K_RF_PWD_166, 1);
00789                         }
00790                 }
00791 
00792                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
00793                                                 AR5K_RF_GAIN_I, 1);
00794 
00795                 /* TODO: Half/quarter channel support */
00796 
00797         }
00798 
00799         if (ah->ah_radio == AR5K_RF5413 &&
00800         channel->hw_value & CHANNEL_2GHZ) {
00801 
00802                 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
00803                                                                         1);
00804 
00805                 /* Set optimum value for early revisions (on pci-e chips) */
00806                 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
00807                 ah->ah_mac_srev < AR5K_SREV_AR5413)
00808                         ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
00809                                                 AR5K_RF_PWD_ICLOBUF_2G, 1);
00810 
00811         }
00812 
00813         /* Write RF banks on hw */
00814         for (i = 0; i < ah->ah_rf_banks_size; i++) {
00815                 AR5K_REG_WAIT(i);
00816                 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
00817         }
00818 
00819         return 0;
00820 }
00821 
00822 
00823 /**************************\
00824   PHY/RF channel functions
00825 \**************************/
00826 
00827 /*
00828  * Check if a channel is supported
00829  */
00830 int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
00831 {
00832         /* Check if the channel is in our supported range */
00833         if (flags & CHANNEL_2GHZ) {
00834                 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
00835                     (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
00836                         return 1;
00837         } else if (flags & CHANNEL_5GHZ)
00838                 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
00839                     (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
00840                         return 1;
00841 
00842         return 0;
00843 }
00844 
00845 /*
00846  * Convertion needed for RF5110
00847  */
00848 static u32 ath5k_hw_rf5110_chan2athchan(struct net80211_channel *channel)
00849 {
00850         u32 athchan;
00851 
00852         /*
00853          * Convert IEEE channel/MHz to an internal channel value used
00854          * by the AR5210 chipset. This has not been verified with
00855          * newer chipsets like the AR5212A who have a completely
00856          * different RF/PHY part.
00857          */
00858         athchan = (ath5k_hw_bitswap((ath5k_freq_to_channel(channel->center_freq)
00859                                      - 24) / 2, 5) << 1)
00860                 | (1 << 6) | 0x1;
00861         return athchan;
00862 }
00863 
00864 /*
00865  * Set channel on RF5110
00866  */
00867 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
00868                 struct net80211_channel *channel)
00869 {
00870         u32 data;
00871 
00872         /*
00873          * Set the channel and wait
00874          */
00875         data = ath5k_hw_rf5110_chan2athchan(channel);
00876         ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
00877         ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
00878         mdelay(1);
00879 
00880         return 0;
00881 }
00882 
00883 /*
00884  * Convertion needed for 5111
00885  */
00886 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
00887                 struct ath5k_athchan_2ghz *athchan)
00888 {
00889         int channel;
00890 
00891         /* Cast this value to catch negative channel numbers (>= -19) */
00892         channel = (int)ieee;
00893 
00894         /*
00895          * Map 2GHz IEEE channel to 5GHz Atheros channel
00896          */
00897         if (channel <= 13) {
00898                 athchan->a2_athchan = 115 + channel;
00899                 athchan->a2_flags = 0x46;
00900         } else if (channel == 14) {
00901                 athchan->a2_athchan = 124;
00902                 athchan->a2_flags = 0x44;
00903         } else if (channel >= 15 && channel <= 26) {
00904                 athchan->a2_athchan = ((channel - 14) * 4) + 132;
00905                 athchan->a2_flags = 0x46;
00906         } else
00907                 return -EINVAL;
00908 
00909         return 0;
00910 }
00911 
00912 /*
00913  * Set channel on 5111
00914  */
00915 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
00916                 struct net80211_channel *channel)
00917 {
00918         struct ath5k_athchan_2ghz ath5k_channel_2ghz;
00919         unsigned int ath5k_channel = ath5k_freq_to_channel(channel->center_freq);
00920         u32 data0, data1, clock;
00921         int ret;
00922 
00923         /*
00924          * Set the channel on the RF5111 radio
00925          */
00926         data0 = data1 = 0;
00927 
00928         if (channel->hw_value & CHANNEL_2GHZ) {
00929                 /* Map 2GHz channel to 5GHz Atheros channel ID */
00930                 ret = ath5k_hw_rf5111_chan2athchan(ath5k_channel,
00931                                                    &ath5k_channel_2ghz);
00932                 if (ret)
00933                         return ret;
00934 
00935                 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
00936                 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
00937                     << 5) | (1 << 4);
00938         }
00939 
00940         if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
00941                 clock = 1;
00942                 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
00943                         (clock << 1) | (1 << 10) | 1;
00944         } else {
00945                 clock = 0;
00946                 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
00947                         << 2) | (clock << 1) | (1 << 10) | 1;
00948         }
00949 
00950         ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
00951                         AR5K_RF_BUFFER);
00952         ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
00953                         AR5K_RF_BUFFER_CONTROL_3);
00954 
00955         return 0;
00956 }
00957 
00958 /*
00959  * Set channel on 5112 and newer
00960  */
00961 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
00962                 struct net80211_channel *channel)
00963 {
00964         u32 data, data0, data1, data2;
00965         u16 c;
00966 
00967         data = data0 = data1 = data2 = 0;
00968         c = channel->center_freq;
00969 
00970         if (c < 4800) {
00971                 if (!((c - 2224) % 5)) {
00972                         data0 = ((2 * (c - 704)) - 3040) / 10;
00973                         data1 = 1;
00974                 } else if (!((c - 2192) % 5)) {
00975                         data0 = ((2 * (c - 672)) - 3040) / 10;
00976                         data1 = 0;
00977                 } else
00978                         return -EINVAL;
00979 
00980                 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
00981         } else if ((c - (c % 5)) != 2 || c > 5435) {
00982                 if (!(c % 20) && c >= 5120) {
00983                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
00984                         data2 = ath5k_hw_bitswap(3, 2);
00985                 } else if (!(c % 10)) {
00986                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
00987                         data2 = ath5k_hw_bitswap(2, 2);
00988                 } else if (!(c % 5)) {
00989                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
00990                         data2 = ath5k_hw_bitswap(1, 2);
00991                 } else
00992                         return -EINVAL;
00993         } else {
00994                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
00995                 data2 = ath5k_hw_bitswap(0, 2);
00996         }
00997 
00998         data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
00999 
01000         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
01001         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
01002 
01003         return 0;
01004 }
01005 
01006 /*
01007  * Set the channel on the RF2425
01008  */
01009 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
01010                 struct net80211_channel *channel)
01011 {
01012         u32 data, data0, data2;
01013         u16 c;
01014 
01015         data = data0 = data2 = 0;
01016         c = channel->center_freq;
01017 
01018         if (c < 4800) {
01019                 data0 = ath5k_hw_bitswap((c - 2272), 8);
01020                 data2 = 0;
01021         /* ? 5GHz ? */
01022         } else if ((c - (c % 5)) != 2 || c > 5435) {
01023                 if (!(c % 20) && c < 5120)
01024                         data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
01025                 else if (!(c % 10))
01026                         data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
01027                 else if (!(c % 5))
01028                         data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
01029                 else
01030                         return -EINVAL;
01031                 data2 = ath5k_hw_bitswap(1, 2);
01032         } else {
01033                 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
01034                 data2 = ath5k_hw_bitswap(0, 2);
01035         }
01036 
01037         data = (data0 << 4) | data2 << 2 | 0x1001;
01038 
01039         ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
01040         ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
01041 
01042         return 0;
01043 }
01044 
01045 /*
01046  * Set a channel on the radio chip
01047  */
01048 int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
01049 {
01050         int ret;
01051         /*
01052          * Check bounds supported by the PHY (we don't care about regultory
01053          * restrictions at this point). Note: hw_value already has the band
01054          * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
01055          * of the band by that */
01056         if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
01057                 DBG("ath5k: channel frequency (%d MHz) out of supported "
01058                     "range\n", channel->center_freq);
01059                 return -EINVAL;
01060         }
01061 
01062         /*
01063          * Set the channel and wait
01064          */
01065         switch (ah->ah_radio) {
01066         case AR5K_RF5110:
01067                 ret = ath5k_hw_rf5110_channel(ah, channel);
01068                 break;
01069         case AR5K_RF5111:
01070                 ret = ath5k_hw_rf5111_channel(ah, channel);
01071                 break;
01072         case AR5K_RF2425:
01073                 ret = ath5k_hw_rf2425_channel(ah, channel);
01074                 break;
01075         default:
01076                 ret = ath5k_hw_rf5112_channel(ah, channel);
01077                 break;
01078         }
01079 
01080         if (ret) {
01081                 DBG("ath5k: setting channel failed: %s\n", strerror(ret));
01082                 return ret;
01083         }
01084 
01085         /* Set JAPAN setting for channel 14 */
01086         if (channel->center_freq == 2484) {
01087                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
01088                                 AR5K_PHY_CCKTXCTL_JAPAN);
01089         } else {
01090                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
01091                                 AR5K_PHY_CCKTXCTL_WORLD);
01092         }
01093 
01094         ah->ah_current_channel = channel;
01095         ah->ah_turbo = (channel->hw_value == CHANNEL_T ? 1 : 0);
01096 
01097         return 0;
01098 }
01099 
01100 /*****************\
01101   PHY calibration
01102 \*****************/
01103 
01104 /**
01105  * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
01106  *
01107  * @ah: struct ath5k_hw pointer we are operating on
01108  * @freq: the channel frequency, just used for error logging
01109  *
01110  * This function performs a noise floor calibration of the PHY and waits for
01111  * it to complete. Then the noise floor value is compared to some maximum
01112  * noise floor we consider valid.
01113  *
01114  * Note that this is different from what the madwifi HAL does: it reads the
01115  * noise floor and afterwards initiates the calibration. Since the noise floor
01116  * calibration can take some time to finish, depending on the current channel
01117  * use, that avoids the occasional timeout warnings we are seeing now.
01118  *
01119  * See the following link for an Atheros patent on noise floor calibration:
01120  * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
01121  * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
01122  *
01123  * XXX: Since during noise floor calibration antennas are detached according to
01124  * the patent, we should stop tx queues here.
01125  */
01126 int
01127 ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
01128 {
01129         int ret;
01130         unsigned int i;
01131         s32 noise_floor;
01132 
01133         /*
01134          * Enable noise floor calibration
01135          */
01136         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
01137                                 AR5K_PHY_AGCCTL_NF);
01138 
01139         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
01140                         AR5K_PHY_AGCCTL_NF, 0, 0);
01141 
01142         if (ret) {
01143                 DBG("ath5k: noise floor calibration timeout (%d MHz)\n", freq);
01144                 return -EAGAIN;
01145         }
01146 
01147         /* Wait until the noise floor is calibrated and read the value */
01148         for (i = 20; i > 0; i--) {
01149                 mdelay(1);
01150                 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
01151                 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
01152                 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
01153                         noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
01154 
01155                         if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
01156                                 break;
01157                 }
01158         }
01159 
01160         DBG2("ath5k: noise floor %d\n", noise_floor);
01161 
01162         if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
01163                 DBG("ath5k: noise floor calibration failed (%d MHz)\n", freq);
01164                 return -EAGAIN;
01165         }
01166 
01167         ah->ah_noise_floor = noise_floor;
01168 
01169         return 0;
01170 }
01171 
01172 /*
01173  * Perform a PHY calibration on RF5110
01174  * -Fix BPSK/QAM Constellation (I/Q correction)
01175  * -Calculate Noise Floor
01176  */
01177 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
01178                 struct net80211_channel *channel)
01179 {
01180         u32 phy_sig, phy_agc, phy_sat, beacon;
01181         int ret;
01182 
01183         /*
01184          * Disable beacons and RX/TX queues, wait
01185          */
01186         AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
01187                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
01188         beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
01189         ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
01190 
01191         mdelay(2);
01192 
01193         /*
01194          * Set the channel (with AGC turned off)
01195          */
01196         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
01197         udelay(10);
01198         ret = ath5k_hw_channel(ah, channel);
01199 
01200         /*
01201          * Activate PHY and wait
01202          */
01203         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
01204         mdelay(1);
01205 
01206         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
01207 
01208         if (ret)
01209                 return ret;
01210 
01211         /*
01212          * Calibrate the radio chip
01213          */
01214 
01215         /* Remember normal state */
01216         phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
01217         phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
01218         phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
01219 
01220         /* Update radio registers */
01221         ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
01222                 AR5K_REG_SM(-1U, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
01223 
01224         ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
01225                         AR5K_PHY_AGCCOARSE_LO)) |
01226                 AR5K_REG_SM(-1U, AR5K_PHY_AGCCOARSE_HI) |
01227                 AR5K_REG_SM(-127U, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
01228 
01229         ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
01230                         AR5K_PHY_ADCSAT_THR)) |
01231                 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
01232                 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
01233 
01234         udelay(20);
01235 
01236         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
01237         udelay(10);
01238         ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
01239         AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
01240 
01241         mdelay(1);
01242 
01243         /*
01244          * Enable calibration and wait until completion
01245          */
01246         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
01247 
01248         ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
01249                         AR5K_PHY_AGCCTL_CAL, 0, 0);
01250 
01251         /* Reset to normal state */
01252         ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
01253         ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
01254         ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
01255 
01256         if (ret) {
01257                 DBG("ath5k: calibration timeout (%d MHz)\n",
01258                     channel->center_freq);
01259                 return ret;
01260         }
01261 
01262         ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
01263 
01264         /*
01265          * Re-enable RX/TX and beacons
01266          */
01267         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
01268                 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
01269         ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
01270 
01271         return 0;
01272 }
01273 
01274 /*
01275  * Perform a PHY calibration on RF5111/5112 and newer chips
01276  */
01277 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
01278                 struct net80211_channel *channel)
01279 {
01280         u32 i_pwr, q_pwr;
01281         s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
01282         int i;
01283 
01284         if (!ah->ah_calibration ||
01285                 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
01286                 goto done;
01287 
01288         /* Calibration has finished, get the results and re-run */
01289         for (i = 0; i <= 10; i++) {
01290                 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
01291                 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
01292                 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
01293         }
01294 
01295         i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
01296         q_coffd = q_pwr >> 7;
01297 
01298         /* No correction */
01299         if (i_coffd == 0 || q_coffd == 0)
01300                 goto done;
01301 
01302         i_coff = ((-iq_corr) / i_coffd) & 0x3f;
01303 
01304         /* Boundary check */
01305         if (i_coff > 31)
01306                 i_coff = 31;
01307         if (i_coff < -32)
01308                 i_coff = -32;
01309 
01310         q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
01311 
01312         /* Boundary check */
01313         if (q_coff > 15)
01314                 q_coff = 15;
01315         if (q_coff < -16)
01316                 q_coff = -16;
01317 
01318         /* Commit new I/Q value */
01319         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
01320                 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
01321 
01322         /* Re-enable calibration -if we don't we'll commit
01323          * the same values again and again */
01324         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
01325                         AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
01326         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
01327 
01328 done:
01329 
01330         /* TODO: Separate noise floor calibration from I/Q calibration
01331          * since noise floor calibration interrupts rx path while I/Q
01332          * calibration doesn't. We don't need to run noise floor calibration
01333          * as often as I/Q calibration.*/
01334         ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
01335 
01336         /* Initiate a gain_F calibration */
01337         ath5k_hw_request_rfgain_probe(ah);
01338 
01339         return 0;
01340 }
01341 
01342 /*
01343  * Perform a PHY calibration
01344  */
01345 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
01346                 struct net80211_channel *channel)
01347 {
01348         int ret;
01349 
01350         if (ah->ah_radio == AR5K_RF5110)
01351                 ret = ath5k_hw_rf5110_calibrate(ah, channel);
01352         else
01353                 ret = ath5k_hw_rf511x_calibrate(ah, channel);
01354 
01355         return ret;
01356 }
01357 
01358 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
01359 {
01360         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
01361 
01362         return 0;
01363 }
01364 
01365 /********************\
01366   Misc PHY functions
01367 \********************/
01368 
01369 /*
01370  * Get the PHY Chip revision
01371  */
01372 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
01373 {
01374         unsigned int i;
01375         u32 srev;
01376         u16 ret;
01377 
01378         /*
01379          * Set the radio chip access register
01380          */
01381         switch (chan) {
01382         case CHANNEL_2GHZ:
01383                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
01384                 break;
01385         case CHANNEL_5GHZ:
01386                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
01387                 break;
01388         default:
01389                 return 0;
01390         }
01391 
01392         mdelay(2);
01393 
01394         /* ...wait until PHY is ready and read the selected radio revision */
01395         ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
01396 
01397         for (i = 0; i < 8; i++)
01398                 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
01399 
01400         if (ah->ah_version == AR5K_AR5210) {
01401                 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
01402                 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
01403         } else {
01404                 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
01405                 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
01406                                 ((srev & 0x0f) << 4), 8);
01407         }
01408 
01409         /* Reset to the 5GHz mode */
01410         ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
01411 
01412         return ret;
01413 }
01414 
01415 void /*TODO:Boundary check*/
01416 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
01417 {
01418         if (ah->ah_version != AR5K_AR5210)
01419                 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
01420 }
01421 
01422 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
01423 {
01424         if (ah->ah_version != AR5K_AR5210)
01425                 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
01426 
01427         return 0; /*XXX: What do we return for 5210 ?*/
01428 }
01429 
01430 
01431 /****************\
01432 * TX power setup *
01433 \****************/
01434 
01435 /*
01436  * Helper functions
01437  */
01438 
01439 /*
01440  * Do linear interpolation between two given (x, y) points
01441  */
01442 static s16
01443 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
01444                                         s16 y_left, s16 y_right)
01445 {
01446         s16 ratio, result;
01447 
01448         /* Avoid divide by zero and skip interpolation
01449          * if we have the same point */
01450         if ((x_left == x_right) || (y_left == y_right))
01451                 return y_left;
01452 
01453         /*
01454          * Since we use ints and not fps, we need to scale up in
01455          * order to get a sane ratio value (or else we 'll eg. get
01456          * always 1 instead of 1.25, 1.75 etc). We scale up by 100
01457          * to have some accuracy both for 0.5 and 0.25 steps.
01458          */
01459         ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
01460 
01461         /* Now scale down to be in range */
01462         result = y_left + (ratio * (target - x_left) / 100);
01463 
01464         return result;
01465 }
01466 
01467 /*
01468  * Find vertical boundary (min pwr) for the linear PCDAC curve.
01469  *
01470  * Since we have the top of the curve and we draw the line below
01471  * until we reach 1 (1 pcdac step) we need to know which point
01472  * (x value) that is so that we don't go below y axis and have negative
01473  * pcdac values when creating the curve, or fill the table with zeroes.
01474  */
01475 static s16
01476 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
01477                                 const s16 *pwrL, const s16 *pwrR)
01478 {
01479         s8 tmp;
01480         s16 min_pwrL, min_pwrR;
01481         s16 pwr_i;
01482 
01483         if (pwrL[0] == pwrL[1])
01484                 min_pwrL = pwrL[0];
01485         else {
01486                 pwr_i = pwrL[0];
01487                 do {
01488                         pwr_i--;
01489                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
01490                                                         pwrL[0], pwrL[1],
01491                                                         stepL[0], stepL[1]);
01492                 } while (tmp > 1);
01493 
01494                 min_pwrL = pwr_i;
01495         }
01496 
01497         if (pwrR[0] == pwrR[1])
01498                 min_pwrR = pwrR[0];
01499         else {
01500                 pwr_i = pwrR[0];
01501                 do {
01502                         pwr_i--;
01503                         tmp = (s8) ath5k_get_interpolated_value(pwr_i,
01504                                                         pwrR[0], pwrR[1],
01505                                                         stepR[0], stepR[1]);
01506                 } while (tmp > 1);
01507 
01508                 min_pwrR = pwr_i;
01509         }
01510 
01511         /* Keep the right boundary so that it works for both curves */
01512         return max(min_pwrL, min_pwrR);
01513 }
01514 
01515 /*
01516  * Interpolate (pwr,vpd) points to create a Power to PDADC or a
01517  * Power to PCDAC curve.
01518  *
01519  * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
01520  * steps (offsets) on y axis. Power can go up to 31.5dB and max
01521  * PCDAC/PDADC step for each curve is 64 but we can write more than
01522  * one curves on hw so we can go up to 128 (which is the max step we
01523  * can write on the final table).
01524  *
01525  * We write y values (PCDAC/PDADC steps) on hw.
01526  */
01527 static void
01528 ath5k_create_power_curve(s16 pmin, s16 pmax,
01529                         const s16 *pwr, const u8 *vpd,
01530                         u8 num_points,
01531                         u8 *vpd_table, u8 type)
01532 {
01533         u8 idx[2] = { 0, 1 };
01534         s16 pwr_i = 2*pmin;
01535         int i;
01536 
01537         if (num_points < 2)
01538                 return;
01539 
01540         /* We want the whole line, so adjust boundaries
01541          * to cover the entire power range. Note that
01542          * power values are already 0.25dB so no need
01543          * to multiply pwr_i by 2 */
01544         if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
01545                 pwr_i = pmin;
01546                 pmin = 0;
01547                 pmax = 63;
01548         }
01549 
01550         /* Find surrounding turning points (TPs)
01551          * and interpolate between them */
01552         for (i = 0; (i <= (u16) (pmax - pmin)) &&
01553         (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
01554 
01555                 /* We passed the right TP, move to the next set of TPs
01556                  * if we pass the last TP, extrapolate above using the last
01557                  * two TPs for ratio */
01558                 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
01559                         idx[0]++;
01560                         idx[1]++;
01561                 }
01562 
01563                 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
01564                                                 pwr[idx[0]], pwr[idx[1]],
01565                                                 vpd[idx[0]], vpd[idx[1]]);
01566 
01567                 /* Increase by 0.5dB
01568                  * (0.25 dB units) */
01569                 pwr_i += 2;
01570         }
01571 }
01572 
01573 /*
01574  * Get the surrounding per-channel power calibration piers
01575  * for a given frequency so that we can interpolate between
01576  * them and come up with an apropriate dataset for our current
01577  * channel.
01578  */
01579 static void
01580 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
01581                         struct net80211_channel *channel,
01582                         struct ath5k_chan_pcal_info **pcinfo_l,
01583                         struct ath5k_chan_pcal_info **pcinfo_r)
01584 {
01585         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
01586         struct ath5k_chan_pcal_info *pcinfo;
01587         u8 idx_l, idx_r;
01588         u8 mode, max, i;
01589         u32 target = channel->center_freq;
01590 
01591         idx_l = 0;
01592         idx_r = 0;
01593 
01594         if (!(channel->hw_value & CHANNEL_OFDM)) {
01595                 pcinfo = ee->ee_pwr_cal_b;
01596                 mode = AR5K_EEPROM_MODE_11B;
01597         } else if (channel->hw_value & CHANNEL_2GHZ) {
01598                 pcinfo = ee->ee_pwr_cal_g;
01599                 mode = AR5K_EEPROM_MODE_11G;
01600         } else {
01601                 pcinfo = ee->ee_pwr_cal_a;
01602                 mode = AR5K_EEPROM_MODE_11A;
01603         }
01604         max = ee->ee_n_piers[mode] - 1;
01605 
01606         /* Frequency is below our calibrated
01607          * range. Use the lowest power curve
01608          * we have */
01609         if (target < pcinfo[0].freq) {
01610                 idx_l = idx_r = 0;
01611                 goto done;
01612         }
01613 
01614         /* Frequency is above our calibrated
01615          * range. Use the highest power curve
01616          * we have */
01617         if (target > pcinfo[max].freq) {
01618                 idx_l = idx_r = max;
01619                 goto done;
01620         }
01621 
01622         /* Frequency is inside our calibrated
01623          * channel range. Pick the surrounding
01624          * calibration piers so that we can
01625          * interpolate */
01626         for (i = 0; i <= max; i++) {
01627 
01628                 /* Frequency matches one of our calibration
01629                  * piers, no need to interpolate, just use
01630                  * that calibration pier */
01631                 if (pcinfo[i].freq == target) {
01632                         idx_l = idx_r = i;
01633                         goto done;
01634                 }
01635 
01636                 /* We found a calibration pier that's above
01637                  * frequency, use this pier and the previous
01638                  * one to interpolate */
01639                 if (target < pcinfo[i].freq) {
01640                         idx_r = i;
01641                         idx_l = idx_r - 1;
01642                         goto done;
01643                 }
01644         }
01645 
01646 done:
01647         *pcinfo_l = &pcinfo[idx_l];
01648         *pcinfo_r = &pcinfo[idx_r];
01649 
01650         return;
01651 }
01652 
01653 /*
01654  * Get the surrounding per-rate power calibration data
01655  * for a given frequency and interpolate between power
01656  * values to set max target power supported by hw for
01657  * each rate.
01658  */
01659 static void
01660 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
01661                         struct net80211_channel *channel,
01662                         struct ath5k_rate_pcal_info *rates)
01663 {
01664         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
01665         struct ath5k_rate_pcal_info *rpinfo;
01666         u8 idx_l, idx_r;
01667         u8 mode, max, i;
01668         u32 target = channel->center_freq;
01669 
01670         idx_l = 0;
01671         idx_r = 0;
01672 
01673         if (!(channel->hw_value & CHANNEL_OFDM)) {
01674                 rpinfo = ee->ee_rate_tpwr_b;
01675                 mode = AR5K_EEPROM_MODE_11B;
01676         } else if (channel->hw_value & CHANNEL_2GHZ) {
01677                 rpinfo = ee->ee_rate_tpwr_g;
01678                 mode = AR5K_EEPROM_MODE_11G;
01679         } else {
01680                 rpinfo = ee->ee_rate_tpwr_a;
01681                 mode = AR5K_EEPROM_MODE_11A;
01682         }
01683         max = ee->ee_rate_target_pwr_num[mode] - 1;
01684 
01685         /* Get the surrounding calibration
01686          * piers - same as above */
01687         if (target < rpinfo[0].freq) {
01688                 idx_l = idx_r = 0;
01689                 goto done;
01690         }
01691 
01692         if (target > rpinfo[max].freq) {
01693                 idx_l = idx_r = max;
01694                 goto done;
01695         }
01696 
01697         for (i = 0; i <= max; i++) {
01698 
01699                 if (rpinfo[i].freq == target) {
01700                         idx_l = idx_r = i;
01701                         goto done;
01702                 }
01703 
01704                 if (target < rpinfo[i].freq) {
01705                         idx_r = i;
01706                         idx_l = idx_r - 1;
01707                         goto done;
01708                 }
01709         }
01710 
01711 done:
01712         /* Now interpolate power value, based on the frequency */
01713         rates->freq = target;
01714 
01715         rates->target_power_6to24 =
01716                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
01717                                         rpinfo[idx_r].freq,
01718                                         rpinfo[idx_l].target_power_6to24,
01719                                         rpinfo[idx_r].target_power_6to24);
01720 
01721         rates->target_power_36 =
01722                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
01723                                         rpinfo[idx_r].freq,
01724                                         rpinfo[idx_l].target_power_36,
01725                                         rpinfo[idx_r].target_power_36);
01726 
01727         rates->target_power_48 =
01728                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
01729                                         rpinfo[idx_r].freq,
01730                                         rpinfo[idx_l].target_power_48,
01731                                         rpinfo[idx_r].target_power_48);
01732 
01733         rates->target_power_54 =
01734                 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
01735                                         rpinfo[idx_r].freq,
01736                                         rpinfo[idx_l].target_power_54,
01737                                         rpinfo[idx_r].target_power_54);
01738 }
01739 
01740 /*
01741  * Get the max edge power for this channel if
01742  * we have such data from EEPROM's Conformance Test
01743  * Limits (CTL), and limit max power if needed.
01744  *
01745  * FIXME: Only works for world regulatory domains
01746  */
01747 static void
01748 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
01749                         struct net80211_channel *channel)
01750 {
01751         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
01752         struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
01753         u8 *ctl_val = ee->ee_ctl;
01754         s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
01755         s16 edge_pwr = 0;
01756         u8 rep_idx;
01757         u8 i, ctl_mode;
01758         u8 ctl_idx = 0xFF;
01759         u32 target = channel->center_freq;
01760 
01761         /* Find out a CTL for our mode that's not mapped
01762          * on a specific reg domain.
01763          *
01764          * TODO: Map our current reg domain to one of the 3 available
01765          * reg domain ids so that we can support more CTLs. */
01766         switch (channel->hw_value & CHANNEL_MODES) {
01767         case CHANNEL_A:
01768                 ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN;
01769                 break;
01770         case CHANNEL_G:
01771                 ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN;
01772                 break;
01773         case CHANNEL_B:
01774                 ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN;
01775                 break;
01776         case CHANNEL_T:
01777                 ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN;
01778                 break;
01779         case CHANNEL_TG:
01780                 ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN;
01781                 break;
01782         case CHANNEL_XR:
01783                 /* Fall through */
01784         default:
01785                 return;
01786         }
01787 
01788         for (i = 0; i < ee->ee_ctls; i++) {
01789                 if (ctl_val[i] == ctl_mode) {
01790                         ctl_idx = i;
01791                         break;
01792                 }
01793         }
01794 
01795         /* If we have a CTL dataset available grab it and find the
01796          * edge power for our frequency */
01797         if (ctl_idx == 0xFF)
01798                 return;
01799 
01800         /* Edge powers are sorted by frequency from lower
01801          * to higher. Each CTL corresponds to 8 edge power
01802          * measurements. */
01803         rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
01804 
01805         /* Don't do boundaries check because we
01806          * might have more that one bands defined
01807          * for this mode */
01808 
01809         /* Get the edge power that's closer to our
01810          * frequency */
01811         for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
01812                 rep_idx += i;
01813                 if (target <= rep[rep_idx].freq)
01814                         edge_pwr = (s16) rep[rep_idx].edge;
01815         }
01816 
01817         if (edge_pwr) {
01818                 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
01819         }
01820 }
01821 
01822 
01823 /*
01824  * Power to PCDAC table functions
01825  */
01826 
01827 /*
01828  * Fill Power to PCDAC table on RF5111
01829  *
01830  * No further processing is needed for RF5111, the only thing we have to
01831  * do is fill the values below and above calibration range since eeprom data
01832  * may not cover the entire PCDAC table.
01833  */
01834 static void
01835 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
01836                                                         s16 *table_max)
01837 {
01838         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
01839         u8      *pcdac_tmp = ah->ah_txpower.tmpL[0];
01840         u8      pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
01841         s16     min_pwr, max_pwr;
01842 
01843         /* Get table boundaries */
01844         min_pwr = table_min[0];
01845         pcdac_0 = pcdac_tmp[0];
01846 
01847         max_pwr = table_max[0];
01848         pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
01849 
01850         /* Extrapolate below minimum using pcdac_0 */
01851         pcdac_i = 0;
01852         for (i = 0; i < min_pwr; i++)
01853                 pcdac_out[pcdac_i++] = pcdac_0;
01854 
01855         /* Copy values from pcdac_tmp */
01856         pwr_idx = min_pwr;
01857         for (i = 0 ; pwr_idx <= max_pwr &&
01858         pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
01859                 pcdac_out[pcdac_i++] = pcdac_tmp[i];
01860                 pwr_idx++;
01861         }
01862 
01863         /* Extrapolate above maximum */
01864         while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
01865                 pcdac_out[pcdac_i++] = pcdac_n;
01866 
01867 }
01868 
01869 /*
01870  * Combine available XPD Curves and fill Linear Power to PCDAC table
01871  * on RF5112
01872  *
01873  * RFX112 can have up to 2 curves (one for low txpower range and one for
01874  * higher txpower range). We need to put them both on pcdac_out and place
01875  * them in the correct location. In case we only have one curve available
01876  * just fit it on pcdac_out (it's supposed to cover the entire range of
01877  * available pwr levels since it's always the higher power curve). Extrapolate
01878  * below and above final table if needed.
01879  */
01880 static void
01881 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
01882                                                 s16 *table_max, u8 pdcurves)
01883 {
01884         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
01885         u8      *pcdac_low_pwr;
01886         u8      *pcdac_high_pwr;
01887         u8      *pcdac_tmp;
01888         u8      pwr;
01889         s16     max_pwr_idx;
01890         s16     min_pwr_idx;
01891         s16     mid_pwr_idx = 0;
01892         /* Edge flag turs on the 7nth bit on the PCDAC
01893          * to delcare the higher power curve (force values
01894          * to be greater than 64). If we only have one curve
01895          * we don't need to set this, if we have 2 curves and
01896          * fill the table backwards this can also be used to
01897          * switch from higher power curve to lower power curve */
01898         u8      edge_flag;
01899         int     i;
01900 
01901         /* When we have only one curve available
01902          * that's the higher power curve. If we have
01903          * two curves the first is the high power curve
01904          * and the next is the low power curve. */
01905         if (pdcurves > 1) {
01906                 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
01907                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
01908                 mid_pwr_idx = table_max[1] - table_min[1] - 1;
01909                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
01910 
01911                 /* If table size goes beyond 31.5dB, keep the
01912                  * upper 31.5dB range when setting tx power.
01913                  * Note: 126 = 31.5 dB in quarter dB steps */
01914                 if (table_max[0] - table_min[1] > 126)
01915                         min_pwr_idx = table_max[0] - 126;
01916                 else
01917                         min_pwr_idx = table_min[1];
01918 
01919                 /* Since we fill table backwards
01920                  * start from high power curve */
01921                 pcdac_tmp = pcdac_high_pwr;
01922 
01923                 edge_flag = 0x40;
01924         } else {
01925                 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
01926                 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
01927                 min_pwr_idx = table_min[0];
01928                 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
01929                 pcdac_tmp = pcdac_high_pwr;
01930                 edge_flag = 0;
01931         }
01932 
01933         /* This is used when setting tx power*/
01934         ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
01935 
01936         /* Fill Power to PCDAC table backwards */
01937         pwr = max_pwr_idx;
01938         for (i = 63; i >= 0; i--) {
01939                 /* Entering lower power range, reset
01940                  * edge flag and set pcdac_tmp to lower
01941                  * power curve.*/
01942                 if (edge_flag == 0x40 &&
01943                 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
01944                         edge_flag = 0x00;
01945                         pcdac_tmp = pcdac_low_pwr;
01946                         pwr = mid_pwr_idx/2;
01947                 }
01948 
01949                 /* Don't go below 1, extrapolate below if we have
01950                  * already swithced to the lower power curve -or
01951                  * we only have one curve and edge_flag is zero
01952                  * anyway */
01953                 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
01954                         while (i >= 0) {
01955                                 pcdac_out[i] = pcdac_out[i + 1];
01956                                 i--;
01957                         }
01958                         break;
01959                 }
01960 
01961                 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
01962 
01963                 /* Extrapolate above if pcdac is greater than
01964                  * 126 -this can happen because we OR pcdac_out
01965                  * value with edge_flag on high power curve */
01966                 if (pcdac_out[i] > 126)
01967                         pcdac_out[i] = 126;
01968 
01969                 /* Decrease by a 0.5dB step */
01970                 pwr--;
01971         }
01972 }
01973 
01974 /* Write PCDAC values on hw */
01975 static void
01976 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
01977 {
01978         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
01979         int     i;
01980 
01981         /*
01982          * Write TX power values
01983          */
01984         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
01985                 ath5k_hw_reg_write(ah,
01986                         (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
01987                         (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
01988                         AR5K_PHY_PCDAC_TXPOWER(i));
01989         }
01990 }
01991 
01992 
01993 /*
01994  * Power to PDADC table functions
01995  */
01996 
01997 /*
01998  * Set the gain boundaries and create final Power to PDADC table
01999  *
02000  * We can have up to 4 pd curves, we need to do a simmilar process
02001  * as we do for RF5112. This time we don't have an edge_flag but we
02002  * set the gain boundaries on a separate register.
02003  */
02004 static void
02005 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
02006                         s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
02007 {
02008         u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
02009         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
02010         u8 *pdadc_tmp;
02011         s16 pdadc_0;
02012         u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
02013         u8 pd_gain_overlap;
02014 
02015         /* Note: Register value is initialized on initvals
02016          * there is no feedback from hw.
02017          * XXX: What about pd_gain_overlap from EEPROM ? */
02018         pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
02019                 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
02020 
02021         /* Create final PDADC table */
02022         for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
02023                 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
02024 
02025                 if (pdg == pdcurves - 1)
02026                         /* 2 dB boundary stretch for last
02027                          * (higher power) curve */
02028                         gain_boundaries[pdg] = pwr_max[pdg] + 4;
02029                 else
02030                         /* Set gain boundary in the middle
02031                          * between this curve and the next one */
02032                         gain_boundaries[pdg] =
02033                                 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
02034 
02035                 /* Sanity check in case our 2 db stretch got out of
02036                  * range. */
02037                 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
02038                         gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
02039 
02040                 /* For the first curve (lower power)
02041                  * start from 0 dB */
02042                 if (pdg == 0)
02043                         pdadc_0 = 0;
02044                 else
02045                         /* For the other curves use the gain overlap */
02046                         pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
02047                                                         pd_gain_overlap;
02048 
02049                 /* Force each power step to be at least 0.5 dB */
02050                 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
02051                         pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
02052                 else
02053                         pwr_step = 1;
02054 
02055                 /* If pdadc_0 is negative, we need to extrapolate
02056                  * below this pdgain by a number of pwr_steps */
02057                 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
02058                         s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
02059                         pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
02060                         pdadc_0++;
02061                 }
02062 
02063                 /* Set last pwr level, using gain boundaries */
02064                 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
02065                 /* Limit it to be inside pwr range */
02066                 table_size = pwr_max[pdg] - pwr_min[pdg];
02067                 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
02068 
02069                 /* Fill pdadc_out table */
02070                 while (pdadc_0 < max_idx)
02071                         pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
02072 
02073                 /* Need to extrapolate above this pdgain? */
02074                 if (pdadc_n <= max_idx)
02075                         continue;
02076 
02077                 /* Force each power step to be at least 0.5 dB */
02078                 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
02079                         pwr_step = pdadc_tmp[table_size - 1] -
02080                                                 pdadc_tmp[table_size - 2];
02081                 else
02082                         pwr_step = 1;
02083 
02084                 /* Extrapolate above */
02085                 while ((pdadc_0 < (s16) pdadc_n) &&
02086                 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
02087                         s16 tmp = pdadc_tmp[table_size - 1] +
02088                                         (pdadc_0 - max_idx) * pwr_step;
02089                         pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
02090                         pdadc_0++;
02091                 }
02092         }
02093 
02094         while (pdg < AR5K_EEPROM_N_PD_GAINS) {
02095                 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
02096                 pdg++;
02097         }
02098 
02099         while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
02100                 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
02101                 pdadc_i++;
02102         }
02103 
02104         /* Set gain boundaries */
02105         ath5k_hw_reg_write(ah,
02106                 AR5K_REG_SM(pd_gain_overlap,
02107                         AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
02108                 AR5K_REG_SM(gain_boundaries[0],
02109                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
02110                 AR5K_REG_SM(gain_boundaries[1],
02111                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
02112                 AR5K_REG_SM(gain_boundaries[2],
02113                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
02114                 AR5K_REG_SM(gain_boundaries[3],
02115                         AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
02116                 AR5K_PHY_TPC_RG5);
02117 
02118         /* Used for setting rate power table */
02119         ah->ah_txpower.txp_min_idx = pwr_min[0];
02120 
02121 }
02122 
02123 /* Write PDADC values on hw */
02124 static void
02125 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
02126                         u8 pdcurves, u8 *pdg_to_idx)
02127 {
02128         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
02129         u32 reg;
02130         u8 i;
02131 
02132         /* Select the right pdgain curves */
02133 
02134         /* Clear current settings */
02135         reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
02136         reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
02137                 AR5K_PHY_TPC_RG1_PDGAIN_2 |
02138                 AR5K_PHY_TPC_RG1_PDGAIN_3 |
02139                 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
02140 
02141         /*
02142          * Use pd_gains curve from eeprom
02143          *
02144          * This overrides the default setting from initvals
02145          * in case some vendors (e.g. Zcomax) don't use the default
02146          * curves. If we don't honor their settings we 'll get a
02147          * 5dB (1 * gain overlap ?) drop.
02148          */
02149         reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
02150 
02151         switch (pdcurves) {
02152         case 3:
02153                 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
02154                 /* Fall through */
02155         case 2:
02156                 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
02157                 /* Fall through */
02158         case 1:
02159                 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
02160                 break;
02161         }
02162         ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
02163 
02164         /*
02165          * Write TX power values
02166          */
02167         for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
02168                 ath5k_hw_reg_write(ah,
02169                         ((pdadc_out[4*i + 0] & 0xff) << 0) |
02170                         ((pdadc_out[4*i + 1] & 0xff) << 8) |
02171                         ((pdadc_out[4*i + 2] & 0xff) << 16) |
02172                         ((pdadc_out[4*i + 3] & 0xff) << 24),
02173                         AR5K_PHY_PDADC_TXPOWER(i));
02174         }
02175 }
02176 
02177 
02178 /*
02179  * Common code for PCDAC/PDADC tables
02180  */
02181 
02182 /*
02183  * This is the main function that uses all of the above
02184  * to set PCDAC/PDADC table on hw for the current channel.
02185  * This table is used for tx power calibration on the basband,
02186  * without it we get weird tx power levels and in some cases
02187  * distorted spectral mask
02188  */
02189 static int
02190 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
02191                         struct net80211_channel *channel,
02192                         u8 ee_mode, u8 type)
02193 {
02194         struct ath5k_pdgain_info *pdg_L, *pdg_R;
02195         struct ath5k_chan_pcal_info *pcinfo_L;
02196         struct ath5k_chan_pcal_info *pcinfo_R;
02197         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
02198         u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
02199         s16 table_min[AR5K_EEPROM_N_PD_GAINS];
02200         s16 table_max[AR5K_EEPROM_N_PD_GAINS];
02201         u8 *tmpL;
02202         u8 *tmpR;
02203         u32 target = channel->center_freq;
02204         int pdg, i;
02205 
02206         /* Get surounding freq piers for this channel */
02207         ath5k_get_chan_pcal_surrounding_piers(ah, channel,
02208                                                 &pcinfo_L,
02209                                                 &pcinfo_R);
02210 
02211         /* Loop over pd gain curves on
02212          * surounding freq piers by index */
02213         for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
02214 
02215                 /* Fill curves in reverse order
02216                  * from lower power (max gain)
02217                  * to higher power. Use curve -> idx
02218                  * backmaping we did on eeprom init */
02219                 u8 idx = pdg_curve_to_idx[pdg];
02220 
02221                 /* Grab the needed curves by index */
02222                 pdg_L = &pcinfo_L->pd_curves[idx];
02223                 pdg_R = &pcinfo_R->pd_curves[idx];
02224 
02225                 /* Initialize the temp tables */
02226                 tmpL = ah->ah_txpower.tmpL[pdg];
02227                 tmpR = ah->ah_txpower.tmpR[pdg];
02228 
02229                 /* Set curve's x boundaries and create
02230                  * curves so that they cover the same
02231                  * range (if we don't do that one table
02232                  * will have values on some range and the
02233                  * other one won't have any so interpolation
02234                  * will fail) */
02235                 table_min[pdg] = min(pdg_L->pd_pwr[0],
02236                                         pdg_R->pd_pwr[0]) / 2;
02237 
02238                 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
02239                                 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
02240 
02241                 /* Now create the curves on surrounding channels
02242                  * and interpolate if needed to get the final
02243                  * curve for this gain on this channel */
02244                 switch (type) {
02245                 case AR5K_PWRTABLE_LINEAR_PCDAC:
02246                         /* Override min/max so that we don't loose
02247                          * accuracy (don't divide by 2) */
02248                         table_min[pdg] = min(pdg_L->pd_pwr[0],
02249                                                 pdg_R->pd_pwr[0]);
02250 
02251                         table_max[pdg] =
02252                                 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
02253                                         pdg_R->pd_pwr[pdg_R->pd_points - 1]);
02254 
02255                         /* Override minimum so that we don't get
02256                          * out of bounds while extrapolating
02257                          * below. Don't do this when we have 2
02258                          * curves and we are on the high power curve
02259                          * because table_min is ok in this case */
02260                         if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
02261 
02262                                 table_min[pdg] =
02263                                         ath5k_get_linear_pcdac_min(pdg_L->pd_step,
02264                                                                 pdg_R->pd_step,
02265                                                                 pdg_L->pd_pwr,
02266                                                                 pdg_R->pd_pwr);
02267 
02268                                 /* Don't go too low because we will
02269                                  * miss the upper part of the curve.
02270                                  * Note: 126 = 31.5dB (max power supported)
02271                                  * in 0.25dB units */
02272                                 if (table_max[pdg] - table_min[pdg] > 126)
02273                                         table_min[pdg] = table_max[pdg] - 126;
02274                         }
02275 
02276                         /* Fall through */
02277                 case AR5K_PWRTABLE_PWR_TO_PCDAC:
02278                 case AR5K_PWRTABLE_PWR_TO_PDADC:
02279 
02280                         ath5k_create_power_curve(table_min[pdg],
02281                                                 table_max[pdg],
02282                                                 pdg_L->pd_pwr,
02283                                                 pdg_L->pd_step,
02284                                                 pdg_L->pd_points, tmpL, type);
02285 
02286                         /* We are in a calibration
02287                          * pier, no need to interpolate
02288                          * between freq piers */
02289                         if (pcinfo_L == pcinfo_R)
02290                                 continue;
02291 
02292                         ath5k_create_power_curve(table_min[pdg],
02293                                                 table_max[pdg],
02294                                                 pdg_R->pd_pwr,
02295                                                 pdg_R->pd_step,
02296                                                 pdg_R->pd_points, tmpR, type);
02297                         break;
02298                 default:
02299                         return -EINVAL;
02300                 }
02301 
02302                 /* Interpolate between curves
02303                  * of surounding freq piers to
02304                  * get the final curve for this
02305                  * pd gain. Re-use tmpL for interpolation
02306                  * output */
02307                 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
02308                 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
02309                         tmpL[i] = (u8) ath5k_get_interpolated_value(target,
02310                                                         (s16) pcinfo_L->freq,
02311                                                         (s16) pcinfo_R->freq,
02312                                                         (s16) tmpL[i],
02313                                                         (s16) tmpR[i]);
02314                 }
02315         }
02316 
02317         /* Now we have a set of curves for this
02318          * channel on tmpL (x range is table_max - table_min
02319          * and y values are tmpL[pdg][]) sorted in the same
02320          * order as EEPROM (because we've used the backmaping).
02321          * So for RF5112 it's from higher power to lower power
02322          * and for RF2413 it's from lower power to higher power.
02323          * For RF5111 we only have one curve. */
02324 
02325         /* Fill min and max power levels for this
02326          * channel by interpolating the values on
02327          * surounding channels to complete the dataset */
02328         ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
02329                                         (s16) pcinfo_L->freq,
02330                                         (s16) pcinfo_R->freq,
02331                                         pcinfo_L->min_pwr, pcinfo_R->min_pwr);
02332 
02333         ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
02334                                         (s16) pcinfo_L->freq,
02335                                         (s16) pcinfo_R->freq,
02336                                         pcinfo_L->max_pwr, pcinfo_R->max_pwr);
02337 
02338         /* We are ready to go, fill PCDAC/PDADC
02339          * table and write settings on hardware */
02340         switch (type) {
02341         case AR5K_PWRTABLE_LINEAR_PCDAC:
02342                 /* For RF5112 we can have one or two curves
02343                  * and each curve covers a certain power lvl
02344                  * range so we need to do some more processing */
02345                 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
02346                                                 ee->ee_pd_gains[ee_mode]);
02347 
02348                 /* Set txp.offset so that we can
02349                  * match max power value with max
02350                  * table index */
02351                 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
02352 
02353                 /* Write settings on hw */
02354                 ath5k_setup_pcdac_table(ah);
02355                 break;
02356         case AR5K_PWRTABLE_PWR_TO_PCDAC:
02357                 /* We are done for RF5111 since it has only
02358                  * one curve, just fit the curve on the table */
02359                 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
02360 
02361                 /* No rate powertable adjustment for RF5111 */
02362                 ah->ah_txpower.txp_min_idx = 0;
02363                 ah->ah_txpower.txp_offset = 0;
02364 
02365                 /* Write settings on hw */
02366                 ath5k_setup_pcdac_table(ah);
02367                 break;
02368         case AR5K_PWRTABLE_PWR_TO_PDADC:
02369                 /* Set PDADC boundaries and fill
02370                  * final PDADC table */
02371                 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
02372                                                 ee->ee_pd_gains[ee_mode]);
02373 
02374                 /* Write settings on hw */
02375                 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
02376 
02377                 /* Set txp.offset, note that table_min
02378                  * can be negative */
02379                 ah->ah_txpower.txp_offset = table_min[0];
02380                 break;
02381         default:
02382                 return -EINVAL;
02383         }
02384 
02385         return 0;
02386 }
02387 
02388 
02389 /*
02390  * Per-rate tx power setting
02391  *
02392  * This is the code that sets the desired tx power (below
02393  * maximum) on hw for each rate (we also have TPC that sets
02394  * power per packet). We do that by providing an index on the
02395  * PCDAC/PDADC table we set up.
02396  */
02397 
02398 /*
02399  * Set rate power table
02400  *
02401  * For now we only limit txpower based on maximum tx power
02402  * supported by hw (what's inside rate_info). We need to limit
02403  * this even more, based on regulatory domain etc.
02404  *
02405  * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
02406  * and is indexed as follows:
02407  * rates[0] - rates[7] -> OFDM rates
02408  * rates[8] - rates[14] -> CCK rates
02409  * rates[15] -> XR rates (they all have the same power)
02410  */
02411 static void
02412 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
02413                         struct ath5k_rate_pcal_info *rate_info,
02414                         u8 ee_mode)
02415 {
02416         unsigned int i;
02417         u16 *rates;
02418 
02419         /* max_pwr is power level we got from driver/user in 0.5dB
02420          * units, switch to 0.25dB units so we can compare */
02421         max_pwr *= 2;
02422         max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
02423 
02424         /* apply rate limits */
02425         rates = ah->ah_txpower.txp_rates_power_table;
02426 
02427         /* OFDM rates 6 to 24Mb/s */
02428         for (i = 0; i < 5; i++)
02429                 rates[i] = min(max_pwr, rate_info->target_power_6to24);
02430 
02431         /* Rest OFDM rates */
02432         rates[5] = min(rates[0], rate_info->target_power_36);
02433         rates[6] = min(rates[0], rate_info->target_power_48);
02434         rates[7] = min(rates[0], rate_info->target_power_54);
02435 
02436         /* CCK rates */
02437         /* 1L */
02438         rates[8] = min(rates[0], rate_info->target_power_6to24);
02439         /* 2L */
02440         rates[9] = min(rates[0], rate_info->target_power_36);
02441         /* 2S */
02442         rates[10] = min(rates[0], rate_info->target_power_36);
02443         /* 5L */
02444         rates[11] = min(rates[0], rate_info->target_power_48);
02445         /* 5S */
02446         rates[12] = min(rates[0], rate_info->target_power_48);
02447         /* 11L */
02448         rates[13] = min(rates[0], rate_info->target_power_54);
02449         /* 11S */
02450         rates[14] = min(rates[0], rate_info->target_power_54);
02451 
02452         /* XR rates */
02453         rates[15] = min(rates[0], rate_info->target_power_6to24);
02454 
02455         /* CCK rates have different peak to average ratio
02456          * so we have to tweak their power so that gainf
02457          * correction works ok. For this we use OFDM to
02458          * CCK delta from eeprom */
02459         if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
02460         (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
02461                 for (i = 8; i <= 15; i++)
02462                         rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
02463 
02464         ah->ah_txpower.txp_min_pwr = rates[7];
02465         ah->ah_txpower.txp_max_pwr = rates[0];
02466         ah->ah_txpower.txp_ofdm = rates[7];
02467 }
02468 
02469 
02470 /*
02471  * Set transmition power
02472  */
02473 int
02474 ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel,
02475                 u8 ee_mode, u8 txpower)
02476 {
02477         struct ath5k_rate_pcal_info rate_info;
02478         u8 type;
02479         int ret;
02480 
02481         if (txpower > AR5K_TUNE_MAX_TXPOWER) {
02482                 DBG("ath5k: invalid tx power %d\n", txpower);
02483                 return -EINVAL;
02484         }
02485         if (txpower == 0)
02486                 txpower = AR5K_TUNE_DEFAULT_TXPOWER;
02487 
02488         /* Reset TX power values */
02489         memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
02490         ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
02491         ah->ah_txpower.txp_min_pwr = 0;
02492         ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
02493 
02494         /* Initialize TX power table */
02495         switch (ah->ah_radio) {
02496         case AR5K_RF5111:
02497                 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
02498                 break;
02499         case AR5K_RF5112:
02500                 type = AR5K_PWRTABLE_LINEAR_PCDAC;
02501                 break;
02502         case AR5K_RF2413:
02503         case AR5K_RF5413:
02504         case AR5K_RF2316:
02505         case AR5K_RF2317:
02506         case AR5K_RF2425:
02507                 type = AR5K_PWRTABLE_PWR_TO_PDADC;
02508                 break;
02509         default:
02510                 return -EINVAL;
02511         }
02512 
02513         /* FIXME: Only on channel/mode change */
02514         ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
02515         if (ret)
02516                 return ret;
02517 
02518         /* Limit max power if we have a CTL available */
02519         ath5k_get_max_ctl_power(ah, channel);
02520 
02521         /* FIXME: Tx power limit for this regdomain
02522          * XXX: Mac80211/CRDA will do that anyway ? */
02523 
02524         /* FIXME: Antenna reduction stuff */
02525 
02526         /* FIXME: Limit power on turbo modes */
02527 
02528         /* FIXME: TPC scale reduction */
02529 
02530         /* Get surounding channels for per-rate power table
02531          * calibration */
02532         ath5k_get_rate_pcal_data(ah, channel, &rate_info);
02533 
02534         /* Setup rate power table */
02535         ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
02536 
02537         /* Write rate power table on hw */
02538         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
02539                 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
02540                 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
02541 
02542         ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
02543                 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
02544                 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
02545 
02546         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
02547                 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
02548                 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
02549 
02550         ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
02551                 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
02552                 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
02553 
02554         /* FIXME: TPC support */
02555         if (ah->ah_txpower.txp_tpc) {
02556                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
02557                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
02558 
02559                 ath5k_hw_reg_write(ah,
02560                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
02561                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
02562                         AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
02563                         AR5K_TPC);
02564         } else {
02565                 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
02566                         AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
02567         }
02568 
02569         return 0;
02570 }
02571 
02572 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower)
02573 {
02574         struct net80211_channel *channel = ah->ah_current_channel;
02575 
02576         DBG2("ath5k: changing txpower to %d\n", txpower);
02577 
02578         return ath5k_hw_txpower(ah, channel, mode, txpower);
02579 }
02580 
02581 #undef _ATH5K_PHY