iPXE
ath9k_ar9002_phy.c
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00001 /*
00002  * Copyright (c) 2008-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 
00020 /**
00021  * DOC: Programming Atheros 802.11n analog front end radios
00022  *
00023  * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
00024  * devices have either an external AR2133 analog front end radio for single
00025  * band 2.4 GHz communication or an AR5133 analog front end radio for dual
00026  * band 2.4 GHz / 5 GHz communication.
00027  *
00028  * All devices after the AR5416 and AR5418 family starting with the AR9280
00029  * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
00030  * into a single-chip and require less programming.
00031  *
00032  * The following single-chips exist with a respective embedded radio:
00033  *
00034  * AR9280 - 11n dual-band 2x2 MIMO for PCIe
00035  * AR9281 - 11n single-band 1x2 MIMO for PCIe
00036  * AR9285 - 11n single-band 1x1 for PCIe
00037  * AR9287 - 11n single-band 2x2 MIMO for PCIe
00038  *
00039  * AR9220 - 11n dual-band 2x2 MIMO for PCI
00040  * AR9223 - 11n single-band 2x2 MIMO for PCI
00041  *
00042  * AR9287 - 11n single-band 1x1 MIMO for USB
00043  */
00044 
00045 #include <ipxe/io.h>
00046 
00047 #include "hw.h"
00048 #include "ar9002_phy.h"
00049 
00050 /**
00051  * ar9002_hw_set_channel - set channel on single-chip device
00052  * @ah: atheros hardware structure
00053  * @chan:
00054  *
00055  * This is the function to change channel on single-chip devices, that is
00056  * all devices after ar9280.
00057  *
00058  * This function takes the channel value in MHz and sets
00059  * hardware channel value. Assumes writes have been enabled to analog bus.
00060  *
00061  * Actual Expression,
00062  *
00063  * For 2GHz channel,
00064  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
00065  * (freq_ref = 40MHz)
00066  *
00067  * For 5GHz channel,
00068  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
00069  * (freq_ref = 40MHz/(24>>amodeRefSel))
00070  */
00071 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
00072 {
00073         u16 bMode, fracMode, aModeRefSel = 0;
00074         u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
00075         struct chan_centers centers;
00076         u32 refDivA = 24;
00077 
00078         ath9k_hw_get_channel_centers(ah, chan, &centers);
00079         freq = centers.synth_center;
00080 
00081         reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
00082         reg32 &= 0xc0000000;
00083 
00084         if (freq < 4800) { /* 2 GHz, fractional mode */
00085                 u32 txctl;
00086                 unsigned int regWrites = 0;
00087 
00088                 bMode = 1;
00089                 fracMode = 1;
00090                 aModeRefSel = 0;
00091                 channelSel = CHANSEL_2G(freq);
00092 
00093                 if (AR_SREV_9287_11_OR_LATER(ah)) {
00094                         if (freq == 2484) {
00095                                 /* Enable channel spreading for channel 14 */
00096                                 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
00097                                                 1, regWrites);
00098                         } else {
00099                                 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
00100                                                 1, regWrites);
00101                         }
00102                 } else {
00103                         txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
00104                         if (freq == 2484) {
00105                                 /* Enable channel spreading for channel 14 */
00106                                 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
00107                                           txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
00108                         } else {
00109                                 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
00110                                           txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
00111                         }
00112                 }
00113         } else {
00114                 bMode = 0;
00115                 fracMode = 0;
00116 
00117                 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
00118                 case 0:
00119                         if ((freq % 20) == 0)
00120                                 aModeRefSel = 3;
00121                         else if ((freq % 10) == 0)
00122                                 aModeRefSel = 2;
00123                         if (aModeRefSel)
00124                                 break;
00125                         /* Fall through */
00126                 case 1:
00127                 default:
00128                         aModeRefSel = 0;
00129                         /*
00130                          * Enable 2G (fractional) mode for channels
00131                          * which are 5MHz spaced.
00132                          */
00133                         fracMode = 1;
00134                         refDivA = 1;
00135                         channelSel = CHANSEL_5G(freq);
00136 
00137                         /* RefDivA setting */
00138                         REG_RMW_FIELD(ah, AR_AN_SYNTH9,
00139                                       AR_AN_SYNTH9_REFDIVA, refDivA);
00140 
00141                 }
00142 
00143                 if (!fracMode) {
00144                         ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
00145                         channelSel = ndiv & 0x1ff;
00146                         channelFrac = (ndiv & 0xfffffe00) * 2;
00147                         channelSel = (channelSel << 17) | channelFrac;
00148                 }
00149         }
00150 
00151         reg32 = reg32 |
00152             (bMode << 29) |
00153             (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
00154 
00155         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
00156 
00157         ah->curchan = chan;
00158         ah->curchan_rad_index = -1;
00159 
00160         return 0;
00161 }
00162 
00163 /**
00164  * ar9002_hw_spur_mitigate - convert baseband spur frequency
00165  * @ah: atheros hardware structure
00166  * @chan:
00167  *
00168  * For single-chip solutions. Converts to baseband spur frequency given the
00169  * input channel frequency and compute register settings below.
00170  */
00171 static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
00172                                     struct ath9k_channel *chan)
00173 {
00174         int bb_spur = AR_NO_SPUR;
00175         int freq;
00176         int bin, cur_bin;
00177         int bb_spur_off, spur_subchannel_sd;
00178         int spur_freq_sd;
00179         int spur_delta_phase;
00180         int denominator;
00181         int upper, lower, cur_vit_mask;
00182         int tmp, newVal;
00183         int i;
00184         static const int pilot_mask_reg[4] = {
00185                 AR_PHY_TIMING7, AR_PHY_TIMING8,
00186                 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
00187         };
00188         static const int chan_mask_reg[4] = {
00189                 AR_PHY_TIMING9, AR_PHY_TIMING10,
00190                 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
00191         };
00192         static const int inc[4] = { 0, 100, 0, 0 };
00193         struct chan_centers centers;
00194 
00195         int8_t mask_m[123];
00196         int8_t mask_p[123];
00197         int8_t mask_amt;
00198         int tmp_mask;
00199         int cur_bb_spur;
00200         int is2GHz = IS_CHAN_2GHZ(chan);
00201 
00202         memset(&mask_m, 0, sizeof(int8_t) * 123);
00203         memset(&mask_p, 0, sizeof(int8_t) * 123);
00204 
00205         ath9k_hw_get_channel_centers(ah, chan, &centers);
00206         freq = centers.synth_center;
00207 
00208         ah->config.spurmode = SPUR_ENABLE_EEPROM;
00209         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
00210                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
00211 
00212                 if (AR_NO_SPUR == cur_bb_spur)
00213                         break;
00214 
00215                 if (is2GHz)
00216                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
00217                 else
00218                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
00219 
00220                 cur_bb_spur = cur_bb_spur - freq;
00221 
00222                 if (IS_CHAN_HT40(chan)) {
00223                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
00224                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
00225                                 bb_spur = cur_bb_spur;
00226                                 break;
00227                         }
00228                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
00229                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
00230                         bb_spur = cur_bb_spur;
00231                         break;
00232                 }
00233         }
00234 
00235         if (AR_NO_SPUR == bb_spur) {
00236                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
00237                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
00238                 return;
00239         } else {
00240                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
00241                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
00242         }
00243 
00244         bin = bb_spur * 320;
00245 
00246         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
00247 
00248         ENABLE_REGWRITE_BUFFER(ah);
00249 
00250         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
00251                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
00252                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
00253                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
00254         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
00255 
00256         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
00257                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
00258                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
00259                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
00260                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
00261         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
00262 
00263         if (IS_CHAN_HT40(chan)) {
00264                 if (bb_spur < 0) {
00265                         spur_subchannel_sd = 1;
00266                         bb_spur_off = bb_spur + 10;
00267                 } else {
00268                         spur_subchannel_sd = 0;
00269                         bb_spur_off = bb_spur - 10;
00270                 }
00271         } else {
00272                 spur_subchannel_sd = 0;
00273                 bb_spur_off = bb_spur;
00274         }
00275 
00276         if (IS_CHAN_HT40(chan))
00277                 spur_delta_phase =
00278                         ((bb_spur * 262144) /
00279                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
00280         else
00281                 spur_delta_phase =
00282                         ((bb_spur * 524288) /
00283                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
00284 
00285         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
00286         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
00287 
00288         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
00289                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
00290                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
00291         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
00292 
00293         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
00294         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
00295 
00296         cur_bin = -6000;
00297         upper = bin + 100;
00298         lower = bin - 100;
00299 
00300         for (i = 0; i < 4; i++) {
00301                 int pilot_mask = 0;
00302                 int chan_mask = 0;
00303                 int bp = 0;
00304                 for (bp = 0; bp < 30; bp++) {
00305                         if ((cur_bin > lower) && (cur_bin < upper)) {
00306                                 pilot_mask = pilot_mask | 0x1 << bp;
00307                                 chan_mask = chan_mask | 0x1 << bp;
00308                         }
00309                         cur_bin += 100;
00310                 }
00311                 cur_bin += inc[i];
00312                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
00313                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
00314         }
00315 
00316         cur_vit_mask = 6100;
00317         upper = bin + 120;
00318         lower = bin - 120;
00319 
00320         for (i = 0; i < 123; i++) {
00321                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
00322 
00323                         /* workaround for gcc bug #37014 */
00324                         volatile int tmp_v = abs(cur_vit_mask - bin);
00325 
00326                         if (tmp_v < 75)
00327                                 mask_amt = 1;
00328                         else
00329                                 mask_amt = 0;
00330                         if (cur_vit_mask < 0)
00331                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
00332                         else
00333                                 mask_p[cur_vit_mask / 100] = mask_amt;
00334                 }
00335                 cur_vit_mask -= 100;
00336         }
00337 
00338         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
00339                 | (mask_m[48] << 26) | (mask_m[49] << 24)
00340                 | (mask_m[50] << 22) | (mask_m[51] << 20)
00341                 | (mask_m[52] << 18) | (mask_m[53] << 16)
00342                 | (mask_m[54] << 14) | (mask_m[55] << 12)
00343                 | (mask_m[56] << 10) | (mask_m[57] << 8)
00344                 | (mask_m[58] << 6) | (mask_m[59] << 4)
00345                 | (mask_m[60] << 2) | (mask_m[61] << 0);
00346         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
00347         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
00348 
00349         tmp_mask = (mask_m[31] << 28)
00350                 | (mask_m[32] << 26) | (mask_m[33] << 24)
00351                 | (mask_m[34] << 22) | (mask_m[35] << 20)
00352                 | (mask_m[36] << 18) | (mask_m[37] << 16)
00353                 | (mask_m[48] << 14) | (mask_m[39] << 12)
00354                 | (mask_m[40] << 10) | (mask_m[41] << 8)
00355                 | (mask_m[42] << 6) | (mask_m[43] << 4)
00356                 | (mask_m[44] << 2) | (mask_m[45] << 0);
00357         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
00358         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
00359 
00360         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
00361                 | (mask_m[18] << 26) | (mask_m[18] << 24)
00362                 | (mask_m[20] << 22) | (mask_m[20] << 20)
00363                 | (mask_m[22] << 18) | (mask_m[22] << 16)
00364                 | (mask_m[24] << 14) | (mask_m[24] << 12)
00365                 | (mask_m[25] << 10) | (mask_m[26] << 8)
00366                 | (mask_m[27] << 6) | (mask_m[28] << 4)
00367                 | (mask_m[29] << 2) | (mask_m[30] << 0);
00368         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
00369         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
00370 
00371         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
00372                 | (mask_m[2] << 26) | (mask_m[3] << 24)
00373                 | (mask_m[4] << 22) | (mask_m[5] << 20)
00374                 | (mask_m[6] << 18) | (mask_m[7] << 16)
00375                 | (mask_m[8] << 14) | (mask_m[9] << 12)
00376                 | (mask_m[10] << 10) | (mask_m[11] << 8)
00377                 | (mask_m[12] << 6) | (mask_m[13] << 4)
00378                 | (mask_m[14] << 2) | (mask_m[15] << 0);
00379         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
00380         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
00381 
00382         tmp_mask = (mask_p[15] << 28)
00383                 | (mask_p[14] << 26) | (mask_p[13] << 24)
00384                 | (mask_p[12] << 22) | (mask_p[11] << 20)
00385                 | (mask_p[10] << 18) | (mask_p[9] << 16)
00386                 | (mask_p[8] << 14) | (mask_p[7] << 12)
00387                 | (mask_p[6] << 10) | (mask_p[5] << 8)
00388                 | (mask_p[4] << 6) | (mask_p[3] << 4)
00389                 | (mask_p[2] << 2) | (mask_p[1] << 0);
00390         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
00391         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
00392 
00393         tmp_mask = (mask_p[30] << 28)
00394                 | (mask_p[29] << 26) | (mask_p[28] << 24)
00395                 | (mask_p[27] << 22) | (mask_p[26] << 20)
00396                 | (mask_p[25] << 18) | (mask_p[24] << 16)
00397                 | (mask_p[23] << 14) | (mask_p[22] << 12)
00398                 | (mask_p[21] << 10) | (mask_p[20] << 8)
00399                 | (mask_p[19] << 6) | (mask_p[18] << 4)
00400                 | (mask_p[17] << 2) | (mask_p[16] << 0);
00401         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
00402         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
00403 
00404         tmp_mask = (mask_p[45] << 28)
00405                 | (mask_p[44] << 26) | (mask_p[43] << 24)
00406                 | (mask_p[42] << 22) | (mask_p[41] << 20)
00407                 | (mask_p[40] << 18) | (mask_p[39] << 16)
00408                 | (mask_p[38] << 14) | (mask_p[37] << 12)
00409                 | (mask_p[36] << 10) | (mask_p[35] << 8)
00410                 | (mask_p[34] << 6) | (mask_p[33] << 4)
00411                 | (mask_p[32] << 2) | (mask_p[31] << 0);
00412         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
00413         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
00414 
00415         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
00416                 | (mask_p[59] << 26) | (mask_p[58] << 24)
00417                 | (mask_p[57] << 22) | (mask_p[56] << 20)
00418                 | (mask_p[55] << 18) | (mask_p[54] << 16)
00419                 | (mask_p[53] << 14) | (mask_p[52] << 12)
00420                 | (mask_p[51] << 10) | (mask_p[50] << 8)
00421                 | (mask_p[49] << 6) | (mask_p[48] << 4)
00422                 | (mask_p[47] << 2) | (mask_p[46] << 0);
00423         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
00424         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
00425 
00426         REGWRITE_BUFFER_FLUSH(ah);
00427 }
00428 
00429 static void ar9002_olc_init(struct ath_hw *ah)
00430 {
00431         u32 i;
00432 
00433         if (!OLC_FOR_AR9280_20_LATER)
00434                 return;
00435 
00436         if (OLC_FOR_AR9287_10_LATER) {
00437                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
00438                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
00439                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
00440                                 AR9287_AN_TXPC0_TXPCMODE,
00441                                 AR9287_AN_TXPC0_TXPCMODE_S,
00442                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
00443                 udelay(100);
00444         } else {
00445                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
00446                         ah->originalGain[i] =
00447                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
00448                                                 AR_PHY_TX_GAIN);
00449                 ah->PDADCdelta = 0;
00450         }
00451 }
00452 
00453 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
00454                                          struct ath9k_channel *chan)
00455 {
00456         u32 pll;
00457 
00458         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
00459 
00460         if (chan && IS_CHAN_HALF_RATE(chan))
00461                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
00462         else if (chan && IS_CHAN_QUARTER_RATE(chan))
00463                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
00464 
00465         if (chan && IS_CHAN_5GHZ(chan)) {
00466                 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
00467                         pll = 0x142c;
00468                 else if (AR_SREV_9280_20(ah))
00469                         pll = 0x2850;
00470                 else
00471                         pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
00472         } else {
00473                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
00474         }
00475 
00476         return pll;
00477 }
00478 
00479 static void ar9002_hw_do_getnf(struct ath_hw *ah,
00480                               int16_t nfarray[NUM_NF_READINGS])
00481 {
00482         int16_t nf;
00483 
00484         nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
00485         nfarray[0] = sign_extend32(nf, 8);
00486 
00487         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
00488         if (IS_CHAN_HT40(ah->curchan))
00489                 nfarray[3] = sign_extend32(nf, 8);
00490 
00491         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
00492                 return;
00493 
00494         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
00495         nfarray[1] = sign_extend32(nf, 8);
00496 
00497         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
00498         if (IS_CHAN_HT40(ah->curchan))
00499                 nfarray[4] = sign_extend32(nf, 8);
00500 }
00501 
00502 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
00503 {
00504         if (AR_SREV_9285(ah)) {
00505                 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
00506                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
00507                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
00508         } else if (AR_SREV_9287(ah)) {
00509                 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
00510                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
00511                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
00512         } else if (AR_SREV_9271(ah)) {
00513                 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
00514                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
00515                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
00516         } else {
00517                 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
00518                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
00519                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
00520                 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
00521                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
00522                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
00523         }
00524 }
00525 
00526 static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah,
00527                                    struct ath_hw_antcomb_conf *antconf)
00528 {
00529         u32 regval;
00530 
00531         regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
00532         antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
00533                                   AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
00534         antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
00535                                  AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
00536         antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
00537                                   AR_PHY_9285_FAST_DIV_BIAS_S;
00538         antconf->lna1_lna2_delta = -3;
00539         antconf->div_group = 0;
00540 }
00541 
00542 static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah,
00543                                    struct ath_hw_antcomb_conf *antconf)
00544 {
00545         u32 regval;
00546 
00547         regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
00548         regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
00549                     AR_PHY_9285_ANT_DIV_ALT_LNACONF |
00550                     AR_PHY_9285_FAST_DIV_BIAS);
00551         regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
00552                    & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
00553         regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
00554                    & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
00555         regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
00556                    & AR_PHY_9285_FAST_DIV_BIAS);
00557 
00558         REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
00559 }
00560 
00561 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
00562 {
00563         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
00564         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
00565 
00566         priv_ops->set_rf_regs = NULL;
00567         priv_ops->rf_alloc_ext_banks = NULL;
00568         priv_ops->rf_free_ext_banks = NULL;
00569         priv_ops->rf_set_freq = ar9002_hw_set_channel;
00570         priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
00571         priv_ops->olc_init = ar9002_olc_init;
00572         priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
00573         priv_ops->do_getnf = ar9002_hw_do_getnf;
00574 
00575         ops->antdiv_comb_conf_get = ar9002_hw_antdiv_comb_conf_get;
00576         ops->antdiv_comb_conf_set = ar9002_hw_antdiv_comb_conf_set;
00577 
00578         ar9002_hw_set_nf_limits(ah);
00579 }