iPXE
Data Structures | Defines | Enumerations | Functions | Variables
hw.h File Reference
#include <errno.h>
#include "mac.h"
#include "ani.h"
#include "eeprom.h"
#include "calib.h"
#include "reg.h"
#include "phy.h"
#include "../regd.h"

Go to the source code of this file.

Data Structures

struct  ath9k_hw_capabilities
struct  ath9k_ops_config
struct  ath9k_hw_cal_data
struct  ath9k_channel
struct  ath9k_beacon_state
struct  chan_centers
struct  ath9k_hw_version
struct  ath_gen_timer_configuration
struct  ath_gen_timer
struct  ath_gen_timer_table
struct  ath_hw_antcomb_conf
struct  ath_hw_radar_conf
 struct ath_hw_radar_conf - radar detection initialization parameters More...
struct  ath_hw_private_ops
 struct ath_hw_private_ops - callbacks used internally by hardware code More...
struct  ath_hw_ops
 struct ath_hw_ops - callbacks used by hardware code and driver code More...
struct  ath_nf_limits
struct  ath_hw
struct  ath_bus_ops

Defines

#define ERRFILE   ERRFILE_ath9k
#define ATHEROS_VENDOR_ID   0x168c
#define AR5416_DEVID_PCI   0x0023
#define AR5416_DEVID_PCIE   0x0024
#define AR9160_DEVID_PCI   0x0027
#define AR9280_DEVID_PCI   0x0029
#define AR9280_DEVID_PCIE   0x002a
#define AR9285_DEVID_PCIE   0x002b
#define AR2427_DEVID_PCIE   0x002c
#define AR9287_DEVID_PCI   0x002d
#define AR9287_DEVID_PCIE   0x002e
#define AR9300_DEVID_PCIE   0x0030
#define AR9300_DEVID_AR9340   0x0031
#define AR9300_DEVID_AR9485_PCIE   0x0032
#define AR5416_AR9100_DEVID   0x000b
#define AR_SUBVENDOR_ID_NOG   0x0e11
#define AR_SUBVENDOR_ID_NEW_A   0x7065
#define AR5416_MAGIC   0x19641014
#define AR9280_COEX2WIRE_SUBSYSID   0x309b
#define AT9285_COEX3WIRE_SA_SUBSYSID   0x30aa
#define AT9285_COEX3WIRE_DA_SUBSYSID   0x30ab
#define AR9300_NUM_BT_WEIGHTS   4
#define AR9300_NUM_WLAN_WEIGHTS   4
#define ATH_AMPDU_LIMIT_MAX   (64 * 1024 - 1)
#define ATH_DEFAULT_NOISE_FLOOR   -95
#define ATH9K_RSSI_BAD   -128
#define ATH9K_NUM_CHANNELS   38
#define REG_WRITE(_ah, _reg, _val)   (_ah)->reg_ops.write((_ah), (_val), (_reg))
#define REG_READ(_ah, _reg)   (_ah)->reg_ops.read((_ah), (_reg))
#define REG_READ_MULTI(_ah, _addr, _val, _cnt)   (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
#define REG_RMW(_ah, _reg, _set, _clr)   (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
#define ENABLE_REGWRITE_BUFFER(_ah)
#define REGWRITE_BUFFER_FLUSH(_ah)
#define SM(_v, _f)   (((_v) << _f##_S) & _f)
#define MS(_v, _f)   (((_v) & _f) >> _f##_S)
#define REG_RMW_FIELD(_a, _r, _f, _v)   REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
#define REG_READ_FIELD(_a, _r, _f)   (((REG_READ(_a, _r) & _f) >> _f##_S))
#define REG_SET_BIT(_a, _r, _f)   REG_RMW(_a, _r, (_f), 0)
#define REG_CLR_BIT(_a, _r, _f)   REG_RMW(_a, _r, 0, (_f))
#define DO_DELAY(x)
#define REG_WRITE_ARRAY(iniarray, column, regWr)   ath9k_hw_write_array(ah, iniarray, column, &(regWr))
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT   0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED   1
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED   2
#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME   3
#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL   4
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED   5
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED   6
#define AR_GPIOD_MASK   0x00001FFF
#define AR_GPIO_BIT(_gpio)   (1 << (_gpio))
#define BASE_ACTIVATE_DELAY   100
#define RTC_PLL_SETTLE_DELAY   (AR_SREV_9340(ah) ? 1000 : 100)
#define COEF_SCALE_S   24
#define HT40_CHANNEL_CENTER_SHIFT   10
#define ATH9K_ANTENNA0_CHAINMASK   0x1
#define ATH9K_ANTENNA1_CHAINMASK   0x2
#define ATH9K_NUM_DMA_DEBUG_REGS   8
#define ATH9K_NUM_QUEUES   10
#define MAX_RATE_POWER   63
#define AH_WAIT_TIMEOUT   100000 /* (us) */
#define AH_TSF_WRITE_TIMEOUT   100 /* (us) */
#define AH_TIME_QUANTUM   10
#define AR_KEYTABLE_SIZE   128
#define POWER_UP_TIME   10000
#define SPUR_RSSI_THRESH   40
#define CAB_TIMEOUT_VAL   10
#define BEACON_TIMEOUT_VAL   10
#define MIN_BEACON_TIMEOUT_VAL   1
#define SLEEP_SLOP   3
#define INIT_CONFIG_STATUS   0x00000000
#define INIT_RSSI_THR   0x00000700
#define INIT_BCON_CNTRL_REG   0x00000000
#define TU_TO_USEC(_tu)   ((_tu) << 10)
#define ATH9K_HW_RX_HP_QDEPTH   16
#define ATH9K_HW_RX_LP_QDEPTH   128
#define PAPRD_GAIN_TABLE_ENTRIES   32
#define PAPRD_TABLE_SZ   24
#define SPUR_DISABLE   0
#define SPUR_ENABLE_IOCTL   1
#define SPUR_ENABLE_EEPROM   2
#define AR_SPUR_5413_1   1640
#define AR_SPUR_5413_2   1200
#define AR_NO_SPUR   0x8000
#define AR_BASE_FREQ_2GHZ   2300
#define AR_BASE_FREQ_5GHZ   4900
#define AR_SPUR_FEEQ_BOUND_HT40   19
#define AR_SPUR_FEEQ_BOUND_HT20   10
#define CHANNEL_CW_INT   0x00002
#define CHANNEL_CCK   0x00020
#define CHANNEL_OFDM   0x00040
#define CHANNEL_2GHZ   0x00080
#define CHANNEL_5GHZ   0x00100
#define CHANNEL_PASSIVE   0x00200
#define CHANNEL_DYN   0x00400
#define CHANNEL_HALF   0x04000
#define CHANNEL_QUARTER   0x08000
#define CHANNEL_HT20   0x10000
#define CHANNEL_HT40PLUS   0x20000
#define CHANNEL_HT40MINUS   0x40000
#define CHANNEL_A   (CHANNEL_5GHZ|CHANNEL_OFDM)
#define CHANNEL_B   (CHANNEL_2GHZ|CHANNEL_CCK)
#define CHANNEL_G   (CHANNEL_2GHZ|CHANNEL_OFDM)
#define CHANNEL_G_HT20   (CHANNEL_2GHZ|CHANNEL_HT20)
#define CHANNEL_A_HT20   (CHANNEL_5GHZ|CHANNEL_HT20)
#define CHANNEL_G_HT40PLUS   (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
#define CHANNEL_G_HT40MINUS   (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
#define CHANNEL_A_HT40PLUS   (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
#define CHANNEL_A_HT40MINUS   (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
#define CHANNEL_ALL
#define IS_CHAN_G(_c)
#define IS_CHAN_OFDM(_c)   (((_c)->channelFlags & CHANNEL_OFDM) != 0)
#define IS_CHAN_5GHZ(_c)   (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
#define IS_CHAN_2GHZ(_c)   (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
#define IS_CHAN_HALF_RATE(_c)   (((_c)->channelFlags & CHANNEL_HALF) != 0)
#define IS_CHAN_QUARTER_RATE(_c)   (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
#define IS_CHAN_B(_c)   ((_c)->chanmode == CHANNEL_B)
#define IS_CHAN_HT20(_c)
#define IS_CHAN_HT40(_c)
#define IS_CHAN_HT(_c)   (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
#define ATH9K_BEACON_PERIOD   0x0000ffff
#define ATH9K_TSFOOR_THRESHOLD   0x00004240 /* 16k us */
#define ATH_MAX_GEN_TIMER   16
#define AR_GENTMR_BIT(_index)   (1 << (_index))
#define debruijn32   0x077CB531U
#define AH_USE_EEPROM   0x1
#define AH_UNPLUGGED   0x2 /* The card has been physically removed. */
#define totalPowerMeasI   meas0.unsign
#define totalPowerMeasQ   meas1.unsign
#define totalIqCorrMeas   meas2.sign
#define totalAdcIOddPhase   meas0.unsign
#define totalAdcIEvenPhase   meas1.unsign
#define totalAdcQOddPhase   meas2.unsign
#define totalAdcQEvenPhase   meas3.unsign
#define totalAdcDcOffsetIOddPhase   meas0.sign
#define totalAdcDcOffsetIEvenPhase   meas1.sign
#define totalAdcDcOffsetQOddPhase   meas2.sign
#define totalAdcDcOffsetQEvenPhase   meas3.sign
#define ATH_PCIE_CAP_LINK_CTRL   0x70
#define ATH_PCIE_CAP_LINK_L0S   1
#define ATH_PCIE_CAP_LINK_L1   2
#define ATH9K_CLOCK_RATE_CCK   22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM   40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM   44
#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM   44

Enumerations

enum  ath_hw_txq_subtype { ATH_TXQ_AC_BE = 0 }
enum  ath_ini_subsys { ATH_INI_PRE = 0, ATH_INI_CORE, ATH_INI_POST, ATH_INI_NUM_SPLIT }
enum  ath9k_hw_caps {
  ATH9K_HW_CAP_HT = BIT(0), ATH9K_HW_CAP_RFSILENT = BIT(1), ATH9K_HW_CAP_CST = BIT(2), ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
  ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), ATH9K_HW_CAP_EDMA = BIT(6), ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), ATH9K_HW_CAP_LDPC = BIT(8),
  ATH9K_HW_CAP_FASTCLOCK = BIT(9), ATH9K_HW_CAP_SGI_20 = BIT(10), ATH9K_HW_CAP_PAPRD = BIT(11), ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
  ATH9K_HW_CAP_2GHZ = BIT(13), ATH9K_HW_CAP_5GHZ = BIT(14), ATH9K_HW_CAP_APM = BIT(15)
}
enum  ath9k_int {
  ATH9K_INT_RX = 0x00000001, ATH9K_INT_RXDESC = 0x00000002, ATH9K_INT_RXHP = 0x00000001, ATH9K_INT_RXLP = 0x00000002,
  ATH9K_INT_RXNOFRM = 0x00000008, ATH9K_INT_RXEOL = 0x00000010, ATH9K_INT_RXORN = 0x00000020, ATH9K_INT_TX = 0x00000040,
  ATH9K_INT_TXDESC = 0x00000080, ATH9K_INT_TIM_TIMER = 0x00000100, ATH9K_INT_BB_WATCHDOG = 0x00000400, ATH9K_INT_TXURN = 0x00000800,
  ATH9K_INT_MIB = 0x00001000, ATH9K_INT_RXPHY = 0x00004000, ATH9K_INT_RXKCM = 0x00008000, ATH9K_INT_SWBA = 0x00010000,
  ATH9K_INT_BMISS = 0x00040000, ATH9K_INT_BNR = 0x00100000, ATH9K_INT_TIM = 0x00200000, ATH9K_INT_DTIM = 0x00400000,
  ATH9K_INT_DTIMSYNC = 0x00800000, ATH9K_INT_GPIO = 0x01000000, ATH9K_INT_CABEND = 0x02000000, ATH9K_INT_TSFOOR = 0x04000000,
  ATH9K_INT_GENTIMER = 0x08000000, ATH9K_INT_CST = 0x10000000, ATH9K_INT_GTT = 0x20000000, ATH9K_INT_FATAL = 0x40000000,
  ATH9K_INT_GLOBAL = 0x80000000, ATH9K_INT_BMISC, ATH9K_INT_COMMON, ATH9K_INT_NOCARD = 0xffffffff
}
enum  ath9k_power_mode { ATH9K_PM_AWAKE = 0, ATH9K_PM_FULL_SLEEP, ATH9K_PM_NETWORK_SLEEP, ATH9K_PM_UNDEFINED }
enum  ath9k_tp_scale {
  ATH9K_TP_SCALE_MAX = 0, ATH9K_TP_SCALE_50, ATH9K_TP_SCALE_25, ATH9K_TP_SCALE_12,
  ATH9K_TP_SCALE_MIN
}
enum  ser_reg_mode { SER_REG_MODE_OFF = 0, SER_REG_MODE_ON = 1, SER_REG_MODE_AUTO = 2 }
enum  ath9k_rx_qtype { ATH9K_RX_QUEUE_HP, ATH9K_RX_QUEUE_LP, ATH9K_RX_QUEUE_MAX }
enum  { ATH9K_RESET_POWER_ON, ATH9K_RESET_WARM, ATH9K_RESET_COLD }

Functions

 FILE_LICENCE (BSD2)
static struct ath_commonath9k_hw_common (struct ath_hw *ah)
static struct ath_regulatoryath9k_hw_regulatory (struct ath_hw *ah)
static struct ath_hw_private_opsath9k_hw_private_ops (struct ath_hw *ah)
static struct ath_hw_opsath9k_hw_ops (struct ath_hw *ah)
static u8 get_streams (int mask)
const char * ath9k_hw_probe (u16 vendorid, u16 devid)
void ath9k_hw_deinit (struct ath_hw *ah)
int ath9k_hw_init (struct ath_hw *ah)
int ath9k_hw_reset (struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
int ath9k_hw_fill_cap_info (struct ath_hw *ah)
u32 ath9k_regd_get_ctl (struct ath_regulatory *reg, struct ath9k_channel *chan)
void ath9k_hw_cfg_gpio_input (struct ath_hw *ah, u32 gpio)
u32 ath9k_hw_gpio_get (struct ath_hw *ah, u32 gpio)
void ath9k_hw_cfg_output (struct ath_hw *ah, u32 gpio, u32 ah_signal_type)
void ath9k_hw_set_gpio (struct ath_hw *ah, u32 gpio, u32 val)
u32 ath9k_hw_getdefantenna (struct ath_hw *ah)
void ath9k_hw_setantenna (struct ath_hw *ah, u32 antenna)
int ath9k_hw_wait (struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
void ath9k_hw_write_array (struct ath_hw *ah, struct ar5416IniArray *array, int column, unsigned int *writecnt)
u32 ath9k_hw_reverse_bits (u32 val, u32 n)
u16 ath9k_hw_computetxtime (struct ath_hw *ah, u8 phy, int kbps, u32 frameLen, u16 rateix, int shortPreamble)
void ath9k_hw_get_channel_centers (struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers)
u32 ath9k_hw_getrxfilter (struct ath_hw *ah)
void ath9k_hw_setrxfilter (struct ath_hw *ah, u32 bits)
int ath9k_hw_phy_disable (struct ath_hw *ah)
int ath9k_hw_disable (struct ath_hw *ah)
void ath9k_hw_set_txpowerlimit (struct ath_hw *ah, u32 limit, int test)
void ath9k_hw_setopmode (struct ath_hw *ah)
void ath9k_hw_setmcastfilter (struct ath_hw *ah, u32 filter0, u32 filter1)
void ath9k_hw_setbssidmask (struct ath_hw *ah)
void ath9k_hw_write_associd (struct ath_hw *ah)
void ath9k_hw_init_global_settings (struct ath_hw *ah)
u32 ar9003_get_pll_sqsum_dvc (struct ath_hw *ah)
void ath9k_hw_set11nmac2040 (struct ath_hw *ah)
int ath9k_hw_check_alive (struct ath_hw *ah)
int ath9k_hw_setpower (struct ath_hw *ah, enum ath9k_power_mode mode)
void ath9k_hw_name (struct ath_hw *ah, char *hw_name, size_t len)
void ath9k_hw_htc_resetinit (struct ath_hw *ah)
void ath9k_hw_get_delta_slope_vals (struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
void ar9002_hw_cck_chan14_spread (struct ath_hw *ah)
int ar9002_hw_rf_claim (struct ath_hw *ah)
void ar9002_hw_enable_async_fifo (struct ath_hw *ah)
void ar9002_hw_update_async_fifo (struct ath_hw *ah)
void ar9002_hw_enable_wep_aggregation (struct ath_hw *ah)
void ar9003_hw_disable_phy_restart (struct ath_hw *ah)
void ar5008_hw_attach_phy_ops (struct ath_hw *ah)
void ar9002_hw_attach_phy_ops (struct ath_hw *ah)
void ar9003_hw_attach_phy_ops (struct ath_hw *ah)
void ar9002_hw_attach_calib_ops (struct ath_hw *ah)
void ar9003_hw_attach_calib_ops (struct ath_hw *ah)
void ar9002_hw_attach_ops (struct ath_hw *ah)
void ar9003_hw_attach_ops (struct ath_hw *ah)
void ar9002_hw_load_ani_reg (struct ath_hw *ah, struct ath9k_channel *chan)
void ath9k_ani_reset (struct ath_hw *ah, int is_scanning)
void ath9k_hw_proc_mib_event (struct ath_hw *ah)
void ath9k_hw_ani_monitor (struct ath_hw *ah, struct ath9k_channel *chan)

Variables

int modparam_force_new_ani

Define Documentation

#define ERRFILE   ERRFILE_ath9k

Definition at line 38 of file hw.h.

#define ATHEROS_VENDOR_ID   0x168c

Definition at line 40 of file hw.h.

Referenced by ar9003_hw_fill_txdesc(), and ar9003_hw_proc_txdesc().

#define AR5416_DEVID_PCI   0x0023

Definition at line 42 of file hw.h.

Referenced by ath9k_hw_fill_cap_info(), and ath9k_hw_init().

#define AR5416_DEVID_PCIE   0x0024

Definition at line 43 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9160_DEVID_PCI   0x0027

Definition at line 44 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9280_DEVID_PCI   0x0029

Definition at line 45 of file hw.h.

Referenced by ath9k_hw_def_check_eeprom(), and ath9k_hw_init().

#define AR9280_DEVID_PCIE   0x002a

Definition at line 46 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9285_DEVID_PCIE   0x002b

Definition at line 47 of file hw.h.

Referenced by ath9k_hw_init().

#define AR2427_DEVID_PCIE   0x002c

Definition at line 48 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9287_DEVID_PCI   0x002d

Definition at line 49 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9287_DEVID_PCIE   0x002e

Definition at line 50 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9300_DEVID_PCIE   0x0030

Definition at line 51 of file hw.h.

Referenced by ath9k_hw_init().

#define AR9300_DEVID_AR9340   0x0031

Definition at line 52 of file hw.h.

Referenced by ath9k_hw_init(), and ath9k_hw_read_revisions().

#define AR9300_DEVID_AR9485_PCIE   0x0032

Definition at line 53 of file hw.h.

Referenced by ath9k_hw_init().

#define AR5416_AR9100_DEVID   0x000b

Definition at line 55 of file hw.h.

Referenced by ath9k_hw_init(), and ath9k_hw_read_revisions().

#define AR_SUBVENDOR_ID_NOG   0x0e11

Definition at line 57 of file hw.h.

#define AR_SUBVENDOR_ID_NEW_A   0x7065

Definition at line 58 of file hw.h.

Referenced by ath9k_hw_fill_cap_info().

#define AR5416_MAGIC   0x19641014

Definition at line 59 of file hw.h.

Referenced by ath9k_hw_init_defaults().

#define AR9280_COEX2WIRE_SUBSYSID   0x309b

Definition at line 61 of file hw.h.

#define AT9285_COEX3WIRE_SA_SUBSYSID   0x30aa

Definition at line 62 of file hw.h.

#define AT9285_COEX3WIRE_DA_SUBSYSID   0x30ab

Definition at line 63 of file hw.h.

#define AR9300_NUM_BT_WEIGHTS   4

Definition at line 65 of file hw.h.

#define AR9300_NUM_WLAN_WEIGHTS   4

Definition at line 66 of file hw.h.

#define ATH_AMPDU_LIMIT_MAX   (64 * 1024 - 1)

Definition at line 68 of file hw.h.

Referenced by ath9k_hw_fill_cap_info().

#define ATH_DEFAULT_NOISE_FLOOR   -95

Definition at line 70 of file hw.h.

#define ATH9K_RSSI_BAD   -128

Definition at line 72 of file hw.h.

Referenced by ath9k_hw_rxprocdesc().

#define ATH9K_NUM_CHANNELS   38

Definition at line 74 of file hw.h.

#define REG_WRITE (   _ah,
  _reg,
  _val 
)    (_ah)->reg_ops.write((_ah), (_val), (_reg))

Definition at line 77 of file hw.h.

Referenced by ar5008_hw_init_bb(), ar5008_hw_init_chain_masks(), ar5008_hw_mark_phy_inactive(), ar5008_hw_override_ini(), ar5008_hw_process_ini(), ar5008_hw_rfbus_done(), ar5008_hw_rfbus_req(), ar5008_hw_set_channel(), ar5008_hw_set_channel_regs(), ar5008_hw_set_radar_params(), ar5008_hw_set_rfmode(), ar5008_hw_spur_mitigate(), ar5008_restore_chainmask(), ar5008_set_diversity(), ar5008_write_rf_array(), ar9002_hw_adc_dccal_calibrate(), ar9002_hw_adc_gaincal_calibrate(), ar9002_hw_antdiv_comb_conf_set(), ar9002_hw_configpcipowersave(), ar9002_hw_get_isr(), ar9002_hw_get_radiorev(), ar9002_hw_init_cal(), ar9002_hw_load_ani_reg(), ar9002_hw_rf_claim(), ar9002_hw_rx_enable(), ar9002_hw_set_channel(), ar9002_hw_setup_calibration(), ar9002_hw_spur_mitigate(), ar9002_hw_update_async_fifo(), ar9003_hw_ant_ctrl_apply(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_configpcipowersave(), ar9003_hw_disable_phy_restart(), ar9003_hw_drive_strength_apply(), ar9003_hw_get_isr(), ar9003_hw_init_bb(), ar9003_hw_init_cal(), ar9003_hw_internal_regulator_apply(), ar9003_hw_mark_phy_inactive(), ar9003_hw_override_ini(), ar9003_hw_prog_ini(), ar9003_hw_rfbus_done(), ar9003_hw_rfbus_req(), ar9003_hw_rx_enable(), ar9003_hw_set_chain_masks(), ar9003_hw_set_channel(), ar9003_hw_set_channel_regs(), ar9003_hw_set_diversity(), ar9003_hw_set_radar_params(), ar9003_hw_set_rfmode(), ar9003_hw_setup_calibration(), ar9003_hw_tx_power_regwrite(), ar9271_hw_pa_cal(), ar9285_hw_clc(), ar9285_hw_pa_cal(), ar9287_eeprom_olpc_set_pdadcs(), ath9k_ani_reset(), ath9k_ani_reset_old(), ath9k_ani_restart(), ath9k_hw_4k_set_board_values(), ath9k_hw_4k_set_gain(), ath9k_hw_4k_set_txpower(), ath9k_hw_abort_tx_dma(), ath9k_hw_addrxbuf_edma(), ath9k_hw_analog_shift_regwrite(), ath9k_hw_analog_shift_rmw(), ath9k_hw_ani_read_counters(), ath9k_hw_ar9287_set_board_values(), ath9k_hw_ar9287_set_txpower(), ath9k_hw_chip_test(), ath9k_hw_def_set_board_values(), ath9k_hw_def_set_gain(), ath9k_hw_def_set_txpower(), ath9k_hw_disable_interrupts(), ath9k_hw_disablepcie(), ath9k_hw_enable_interrupts(), ath9k_hw_gpio_cfg_output_mux(), ath9k_hw_init_interrupt_masks(), ath9k_hw_init_pll(), ath9k_hw_loadnf(), ath9k_hw_putrxbuf(), ath9k_hw_puttxbuf(), ath9k_hw_reset(), ath9k_hw_reset_txstatus_ring(), ath9k_hw_resettxqueue(), ath9k_hw_set11nmac2040(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ar9287_power_cal_table(), ath9k_hw_set_def_power_cal_table(), ath9k_hw_set_dma(), ath9k_hw_set_interrupts(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_set_reset_reg(), ath9k_hw_set_rx_bufsize(), ath9k_hw_set_txq_interrupts(), ath9k_hw_setantenna(), ath9k_hw_setmcastfilter(), ath9k_hw_setrxfilter(), ath9k_hw_setslottime(), ath9k_hw_stopdmarecv(), ath9k_hw_txstart(), ath9k_hw_updatetxtriglevel(), ath9k_hw_write_array(), ath9k_hw_write_associd(), ath9k_set_power_sleep(), and is_pmu_set().

#define REG_READ (   _ah,
  _reg 
)    (_ah)->reg_ops.read((_ah), (_reg))

Definition at line 80 of file hw.h.

Referenced by __ath9k_hw_init(), ar5008_hw_ani_cache_ini_regs(), ar5008_hw_do_getnf(), ar5008_hw_init_bb(), ar5008_hw_init_chain_masks(), ar5008_hw_override_ini(), ar5008_hw_rfbus_done(), ar5008_hw_set_channel(), ar5008_hw_set_channel_regs(), ar5008_hw_spur_mitigate(), ar5008_set_diversity(), ar9002_hw_adc_dccal_calibrate(), ar9002_hw_adc_dccal_collect(), ar9002_hw_adc_gaincal_calibrate(), ar9002_hw_adc_gaincal_collect(), ar9002_hw_antdiv_comb_conf_get(), ar9002_hw_antdiv_comb_conf_set(), ar9002_hw_calibrate(), ar9002_hw_configpcipowersave(), ar9002_hw_do_getnf(), ar9002_hw_get_isr(), ar9002_hw_get_radiorev(), ar9002_hw_init_cal(), ar9002_hw_iqcal_collect(), ar9002_hw_load_ani_reg(), ar9002_hw_per_calibration(), ar9002_hw_set_channel(), ar9002_hw_spur_mitigate(), ar9002_olc_init(), ar9003_get_pll_sqsum_dvc(), ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ant_ctrl_apply(), ar9003_hw_antdiv_comb_conf_get(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_disable_phy_restart(), ar9003_hw_do_getnf(), ar9003_hw_drive_strength_apply(), ar9003_hw_get_isr(), ar9003_hw_init_bb(), ar9003_hw_init_cal(), ar9003_hw_internal_regulator_apply(), ar9003_hw_iqcal_collect(), ar9003_hw_iqcalibrate(), ar9003_hw_override_ini(), ar9003_hw_per_calibration(), ar9003_hw_rfbus_done(), ar9003_hw_set_channel_regs(), ar9003_hw_set_diversity(), ar9003_hw_tx_iq_cal_post_proc(), ar9271_hw_pa_cal(), ar9280_hw_olc_temp_compensation(), ar9285_hw_clc(), ar9285_hw_pa_cal(), ar9287_eeprom_olpc_set_pdadcs(), ar9287_hw_olc_temp_compensation(), ar9300_otp_read_word(), ath9k_hw_4k_set_board_values(), ath9k_hw_4k_set_gain(), ath9k_hw_analog_shift_rmw(), ath9k_hw_ani_read_counters(), ath9k_hw_ar9287_set_board_values(), ath9k_hw_check_alive(), ath9k_hw_chip_test(), ath9k_hw_def_set_board_values(), ath9k_hw_def_set_gain(), ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ath9k_hw_fill_cap_info(), ath9k_hw_getdefantenna(), ath9k_hw_getnf(), ath9k_hw_getrxfilter(), ath9k_hw_gpio_cfg_output_mux(), ath9k_hw_gpio_get(), ath9k_hw_init_pll(), ath9k_hw_intrpend(), ath9k_hw_loadnf(), ath9k_hw_numtxpending(), ath9k_hw_read_revisions(), ath9k_hw_reset(), ath9k_hw_set_4k_power_cal_table(), ath9k_hw_set_ar9287_power_cal_table(), ath9k_hw_set_def_power_cal_table(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_setrxabort(), ath9k_hw_stopdmarecv(), ath9k_hw_update_mibstats(), ath9k_hw_updatetxtriglevel(), ath9k_hw_wait(), and is_pmu_set().

#define REG_READ_MULTI (   _ah,
  _addr,
  _val,
  _cnt 
)    (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))

Definition at line 83 of file hw.h.

Referenced by ath9k_hw_usb_gen_fill_eeprom().

#define REG_RMW (   _ah,
  _reg,
  _set,
  _clr 
)    (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
#define ENABLE_REGWRITE_BUFFER (   _ah)
#define REGWRITE_BUFFER_FLUSH (   _ah)
#define SM (   _v,
  _f 
)    (((_v) << _f##_S) & _f)
#define MS (   _v,
  _f 
)    (((_v) & _f) >> _f##_S)
#define REG_RMW_FIELD (   _a,
  _r,
  _f,
  _v 
)    REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
#define REG_READ_FIELD (   _a,
  _r,
  _f 
)    (((REG_READ(_a, _r) & _f) >> _f##_S))
#define REG_SET_BIT (   _a,
  _r,
  _f 
)    REG_RMW(_a, _r, (_f), 0)
#define REG_CLR_BIT (   _a,
  _r,
  _f 
)    REG_RMW(_a, _r, 0, (_f))
#define DO_DELAY (   x)
Value:
do {                                    \
                if (((++(x) % 64) == 0) &&                      \
                    (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
                        != ATH_USB))                            \
                        udelay(1);                              \
        } while (0)

Definition at line 112 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar5008_write_rf_array(), ar9003_hw_prog_ini(), and ath9k_hw_write_array().

#define REG_WRITE_ARRAY (   iniarray,
  column,
  regWr 
)    ath9k_hw_write_array(ah, iniarray, column, &(regWr))

Definition at line 119 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar9002_hw_set_channel(), and ar9003_hw_process_ini().

Definition at line 122 of file hw.h.

Referenced by ath9k_hw_apply_gpio_override().

Definition at line 123 of file hw.h.

Definition at line 124 of file hw.h.

Definition at line 125 of file hw.h.

Definition at line 126 of file hw.h.

Definition at line 127 of file hw.h.

Definition at line 128 of file hw.h.

#define AR_GPIOD_MASK   0x00001FFF

Definition at line 130 of file hw.h.

#define AR_GPIO_BIT (   _gpio)    (1 << (_gpio))

Definition at line 131 of file hw.h.

Referenced by ath9k_hw_gpio_get(), and ath9k_hw_set_gpio().

#define BASE_ACTIVATE_DELAY   100
#define RTC_PLL_SETTLE_DELAY   (AR_SREV_9340(ah) ? 1000 : 100)

Definition at line 134 of file hw.h.

Referenced by ath9k_hw_init_pll().

#define COEF_SCALE_S   24

Definition at line 135 of file hw.h.

Referenced by ath9k_hw_get_delta_slope_vals().

#define HT40_CHANNEL_CENTER_SHIFT   10

Definition at line 136 of file hw.h.

Referenced by ath9k_hw_get_channel_centers().

#define ATH9K_ANTENNA0_CHAINMASK   0x1

Definition at line 138 of file hw.h.

#define ATH9K_ANTENNA1_CHAINMASK   0x2

Definition at line 139 of file hw.h.

#define ATH9K_NUM_DMA_DEBUG_REGS   8

Definition at line 141 of file hw.h.

#define ATH9K_NUM_QUEUES   10

Definition at line 142 of file hw.h.

#define MAX_RATE_POWER   63
#define AH_WAIT_TIMEOUT   100000 /* (us) */
#define AH_TSF_WRITE_TIMEOUT   100 /* (us) */

Definition at line 146 of file hw.h.

#define AH_TIME_QUANTUM   10

Definition at line 147 of file hw.h.

Referenced by ath9k_hw_stopdmarecv(), and ath9k_hw_wait().

#define AR_KEYTABLE_SIZE   128

Definition at line 148 of file hw.h.

Referenced by ath9k_init_crypto().

#define POWER_UP_TIME   10000

Definition at line 149 of file hw.h.

Referenced by ath9k_hw_set_power_awake().

#define SPUR_RSSI_THRESH   40

Definition at line 150 of file hw.h.

Referenced by ar5008_hw_spur_mitigate(), and ar9002_hw_spur_mitigate().

#define CAB_TIMEOUT_VAL   10

Definition at line 152 of file hw.h.

#define BEACON_TIMEOUT_VAL   10

Definition at line 153 of file hw.h.

#define MIN_BEACON_TIMEOUT_VAL   1

Definition at line 154 of file hw.h.

#define SLEEP_SLOP   3

Definition at line 155 of file hw.h.

#define INIT_CONFIG_STATUS   0x00000000

Definition at line 157 of file hw.h.

Referenced by ath9k_hw_reset().

#define INIT_RSSI_THR   0x00000700

Definition at line 158 of file hw.h.

Referenced by ath9k_hw_reset().

#define INIT_BCON_CNTRL_REG   0x00000000

Definition at line 159 of file hw.h.

#define TU_TO_USEC (   _tu)    ((_tu) << 10)

Definition at line 161 of file hw.h.

#define ATH9K_HW_RX_HP_QDEPTH   16

Definition at line 163 of file hw.h.

Referenced by ath9k_hw_fill_cap_info().

#define ATH9K_HW_RX_LP_QDEPTH   128

Definition at line 164 of file hw.h.

Referenced by ath9k_hw_fill_cap_info().

#define PAPRD_GAIN_TABLE_ENTRIES   32

Definition at line 166 of file hw.h.

#define PAPRD_TABLE_SZ   24

Definition at line 167 of file hw.h.

#define SPUR_DISABLE   0
#define SPUR_ENABLE_IOCTL   1
#define SPUR_ENABLE_EEPROM   2
#define AR_SPUR_5413_1   1640

Definition at line 238 of file hw.h.

#define AR_SPUR_5413_2   1200

Definition at line 239 of file hw.h.

#define AR_NO_SPUR   0x8000
#define AR_BASE_FREQ_2GHZ   2300

Definition at line 241 of file hw.h.

Referenced by ar9002_hw_spur_mitigate().

#define AR_BASE_FREQ_5GHZ   4900

Definition at line 242 of file hw.h.

Referenced by ar9002_hw_spur_mitigate().

#define AR_SPUR_FEEQ_BOUND_HT40   19

Definition at line 243 of file hw.h.

Referenced by ar9002_hw_spur_mitigate().

#define AR_SPUR_FEEQ_BOUND_HT20   10

Definition at line 244 of file hw.h.

Referenced by ar9002_hw_spur_mitigate().

#define CHANNEL_CW_INT   0x00002

Definition at line 301 of file hw.h.

#define CHANNEL_CCK   0x00020

Definition at line 302 of file hw.h.

#define CHANNEL_OFDM   0x00040

Definition at line 303 of file hw.h.

#define CHANNEL_2GHZ   0x00080

Definition at line 304 of file hw.h.

#define CHANNEL_5GHZ   0x00100

Definition at line 305 of file hw.h.

#define CHANNEL_PASSIVE   0x00200

Definition at line 306 of file hw.h.

#define CHANNEL_DYN   0x00400

Definition at line 307 of file hw.h.

#define CHANNEL_HALF   0x04000

Definition at line 308 of file hw.h.

#define CHANNEL_QUARTER   0x08000

Definition at line 309 of file hw.h.

#define CHANNEL_HT20   0x10000

Definition at line 310 of file hw.h.

#define CHANNEL_HT40PLUS   0x20000

Definition at line 311 of file hw.h.

#define CHANNEL_HT40MINUS   0x40000

Definition at line 312 of file hw.h.

Definition at line 314 of file hw.h.

Definition at line 315 of file hw.h.

Definition at line 316 of file hw.h.

Definition at line 317 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar9002_hw_load_ani_reg(), and ar9003_hw_process_ini().

Definition at line 318 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar9002_hw_load_ani_reg(), and ar9003_hw_process_ini().

Definition at line 320 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar9002_hw_load_ani_reg(), and ar9003_hw_process_ini().

Definition at line 322 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar9002_hw_load_ani_reg(), and ar9003_hw_process_ini().

#define CHANNEL_ALL
Value:
(CHANNEL_OFDM|                          \
         CHANNEL_CCK|                           \
         CHANNEL_2GHZ |                         \
         CHANNEL_5GHZ |                         \
         CHANNEL_HT20 |                         \
         CHANNEL_HT40PLUS |                     \
         CHANNEL_HT40MINUS)

Definition at line 323 of file hw.h.

#define IS_CHAN_G (   _c)
Value:

Definition at line 355 of file hw.h.

Referenced by ar5008_hw_set_rfmode(), ar9003_hw_set_rfmode(), and ath9k_regd_get_ctl().

#define IS_CHAN_OFDM (   _c)    (((_c)->channelFlags & CHANNEL_OFDM) != 0)

Definition at line 359 of file hw.h.

Referenced by ath9k_hw_channel_change(), and ath9k_hw_reset().

#define IS_CHAN_5GHZ (   _c)    (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
#define IS_CHAN_2GHZ (   _c)    (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
#define IS_CHAN_HALF_RATE (   _c)    (((_c)->channelFlags & CHANNEL_HALF) != 0)
#define IS_CHAN_QUARTER_RATE (   _c)    (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
#define IS_CHAN_A_FAST_CLOCK (   _ah,
  _c 
)
Value:
((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
         ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))

Definition at line 364 of file hw.h.

Referenced by ar5008_hw_process_ini(), ar5008_hw_set_rfmode(), ar9002_hw_compute_pll_control(), ar9003_hw_process_ini(), and ar9003_hw_set_rfmode().

#define IS_CHAN_B (   _c)    ((_c)->chanmode == CHANNEL_B)

Definition at line 369 of file hw.h.

#define IS_CHAN_HT20 (   _c)
#define IS_CHAN_HT40 (   _c)
#define IS_CHAN_HT (   _c)    (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))

Definition at line 376 of file hw.h.

Referenced by ath9k_hw_channel_change(), and ath9k_hw_reset().

#define ATH9K_BEACON_PERIOD   0x0000ffff

Definition at line 409 of file hw.h.

#define ATH9K_TSFOOR_THRESHOLD   0x00004240 /* 16k us */

Definition at line 410 of file hw.h.

#define ATH_MAX_GEN_TIMER   16

Definition at line 448 of file hw.h.

#define AR_GENTMR_BIT (   _index)    (1 << (_index))

Definition at line 450 of file hw.h.

#define debruijn32   0x077CB531U

Definition at line 456 of file hw.h.

#define AH_USE_EEPROM   0x1

Definition at line 653 of file hw.h.

Referenced by ath9k_init_softc().

#define AH_UNPLUGGED   0x2 /* The card has been physically removed. */

Definition at line 654 of file hw.h.

Referenced by ath_pci_remove(), and ath_stoprecv().

#define totalPowerMeasI   meas0.unsign

Definition at line 719 of file hw.h.

#define totalPowerMeasQ   meas1.unsign

Definition at line 720 of file hw.h.

#define totalIqCorrMeas   meas2.sign

Definition at line 721 of file hw.h.

#define totalAdcIOddPhase   meas0.unsign

Definition at line 722 of file hw.h.

#define totalAdcIEvenPhase   meas1.unsign

Definition at line 723 of file hw.h.

#define totalAdcQOddPhase   meas2.unsign

Definition at line 724 of file hw.h.

#define totalAdcQEvenPhase   meas3.unsign

Definition at line 725 of file hw.h.

#define totalAdcDcOffsetIOddPhase   meas0.sign

Definition at line 726 of file hw.h.

#define totalAdcDcOffsetIEvenPhase   meas1.sign

Definition at line 727 of file hw.h.

#define totalAdcDcOffsetQOddPhase   meas2.sign

Definition at line 728 of file hw.h.

#define totalAdcDcOffsetQEvenPhase   meas3.sign

Definition at line 729 of file hw.h.

#define ATH_PCIE_CAP_LINK_CTRL   0x70

Definition at line 988 of file hw.h.

#define ATH_PCIE_CAP_LINK_L0S   1

Definition at line 989 of file hw.h.

#define ATH_PCIE_CAP_LINK_L1   2

Definition at line 990 of file hw.h.

#define ATH9K_CLOCK_RATE_CCK   22

Definition at line 992 of file hw.h.

Referenced by ath9k_hw_set_clockrate().

#define ATH9K_CLOCK_RATE_5GHZ_OFDM   40

Definition at line 993 of file hw.h.

Referenced by ath9k_hw_set_clockrate().

#define ATH9K_CLOCK_RATE_2GHZ_OFDM   44

Definition at line 994 of file hw.h.

Referenced by ath9k_hw_set_clockrate().

Definition at line 995 of file hw.h.

Referenced by ath9k_hw_set_clockrate().


Enumeration Type Documentation

Enumerator:
ATH_TXQ_AC_BE 

Definition at line 169 of file hw.h.

                        {
        ATH_TXQ_AC_BE = 0,
};
Enumerator:
ATH_INI_PRE 
ATH_INI_CORE 
ATH_INI_POST 
ATH_INI_NUM_SPLIT 

Definition at line 173 of file hw.h.

Enumerator:
ATH9K_HW_CAP_HT 
ATH9K_HW_CAP_RFSILENT 
ATH9K_HW_CAP_CST 
ATH9K_HW_CAP_AUTOSLEEP 
ATH9K_HW_CAP_4KB_SPLITTRANS 
ATH9K_HW_CAP_EDMA 
ATH9K_HW_CAP_RAC_SUPPORTED 
ATH9K_HW_CAP_LDPC 
ATH9K_HW_CAP_FASTCLOCK 
ATH9K_HW_CAP_SGI_20 
ATH9K_HW_CAP_PAPRD 
ATH9K_HW_CAP_ANT_DIV_COMB 
ATH9K_HW_CAP_2GHZ 
ATH9K_HW_CAP_5GHZ 
ATH9K_HW_CAP_APM 

Definition at line 180 of file hw.h.

enum ath9k_int
Enumerator:
ATH9K_INT_RX 
ATH9K_INT_RXDESC 
ATH9K_INT_RXHP 
ATH9K_INT_RXLP 
ATH9K_INT_RXNOFRM 
ATH9K_INT_RXEOL 
ATH9K_INT_RXORN 
ATH9K_INT_TX 
ATH9K_INT_TXDESC 
ATH9K_INT_TIM_TIMER 
ATH9K_INT_BB_WATCHDOG 
ATH9K_INT_TXURN 
ATH9K_INT_MIB 
ATH9K_INT_RXPHY 
ATH9K_INT_RXKCM 
ATH9K_INT_SWBA 
ATH9K_INT_BMISS 
ATH9K_INT_BNR 
ATH9K_INT_TIM 
ATH9K_INT_DTIM 
ATH9K_INT_DTIMSYNC 
ATH9K_INT_GPIO 
ATH9K_INT_CABEND 
ATH9K_INT_TSFOOR 
ATH9K_INT_GENTIMER 
ATH9K_INT_CST 
ATH9K_INT_GTT 
ATH9K_INT_FATAL 
ATH9K_INT_GLOBAL 
ATH9K_INT_BMISC 
ATH9K_INT_COMMON 
ATH9K_INT_NOCARD 

Definition at line 251 of file hw.h.

               {
        ATH9K_INT_RX = 0x00000001,
        ATH9K_INT_RXDESC = 0x00000002,
        ATH9K_INT_RXHP = 0x00000001,
        ATH9K_INT_RXLP = 0x00000002,
        ATH9K_INT_RXNOFRM = 0x00000008,
        ATH9K_INT_RXEOL = 0x00000010,
        ATH9K_INT_RXORN = 0x00000020,
        ATH9K_INT_TX = 0x00000040,
        ATH9K_INT_TXDESC = 0x00000080,
        ATH9K_INT_TIM_TIMER = 0x00000100,
        ATH9K_INT_BB_WATCHDOG = 0x00000400,
        ATH9K_INT_TXURN = 0x00000800,
        ATH9K_INT_MIB = 0x00001000,
        ATH9K_INT_RXPHY = 0x00004000,
        ATH9K_INT_RXKCM = 0x00008000,
        ATH9K_INT_SWBA = 0x00010000,
        ATH9K_INT_BMISS = 0x00040000,
        ATH9K_INT_BNR = 0x00100000,
        ATH9K_INT_TIM = 0x00200000,
        ATH9K_INT_DTIM = 0x00400000,
        ATH9K_INT_DTIMSYNC = 0x00800000,
        ATH9K_INT_GPIO = 0x01000000,
        ATH9K_INT_CABEND = 0x02000000,
        ATH9K_INT_TSFOOR = 0x04000000,
        ATH9K_INT_GENTIMER = 0x08000000,
        ATH9K_INT_CST = 0x10000000,
        ATH9K_INT_GTT = 0x20000000,
        ATH9K_INT_FATAL = 0x40000000,
        ATH9K_INT_GLOBAL = 0x80000000,
        ATH9K_INT_BMISC = ATH9K_INT_TIM |
                ATH9K_INT_DTIM |
                ATH9K_INT_DTIMSYNC |
                ATH9K_INT_TSFOOR |
                ATH9K_INT_CABEND,
        ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
                ATH9K_INT_RXDESC |
                ATH9K_INT_RXEOL |
                ATH9K_INT_RXORN |
                ATH9K_INT_TXURN |
                ATH9K_INT_TXDESC |
                ATH9K_INT_MIB |
                ATH9K_INT_RXPHY |
                ATH9K_INT_RXKCM |
                ATH9K_INT_SWBA |
                ATH9K_INT_BMISS |
                ATH9K_INT_GPIO,
        ATH9K_INT_NOCARD = 0xffffffff
};
Enumerator:
ATH9K_PM_AWAKE 
ATH9K_PM_FULL_SLEEP 
ATH9K_PM_NETWORK_SLEEP 
ATH9K_PM_UNDEFINED 

Definition at line 378 of file hw.h.

Enumerator:
ATH9K_TP_SCALE_MAX 
ATH9K_TP_SCALE_50 
ATH9K_TP_SCALE_25 
ATH9K_TP_SCALE_12 
ATH9K_TP_SCALE_MIN 

Definition at line 385 of file hw.h.

Enumerator:
SER_REG_MODE_OFF 
SER_REG_MODE_ON 
SER_REG_MODE_AUTO 

Definition at line 393 of file hw.h.

Enumerator:
ATH9K_RX_QUEUE_HP 
ATH9K_RX_QUEUE_LP 
ATH9K_RX_QUEUE_MAX 

Definition at line 399 of file hw.h.

anonymous enum
Enumerator:
ATH9K_RESET_POWER_ON 
ATH9K_RESET_WARM 
ATH9K_RESET_COLD 

Definition at line 427 of file hw.h.


Function Documentation

FILE_LICENCE ( BSD2  )
static struct ath_common* ath9k_hw_common ( struct ath_hw ah) [static, read]
static struct ath_regulatory* ath9k_hw_regulatory ( struct ath_hw ah) [static, read]
static struct ath_hw_private_ops* ath9k_hw_private_ops ( struct ath_hw ah) [static, read]
static struct ath_hw_ops* ath9k_hw_ops ( struct ath_hw ah) [static, read]
static u8 get_streams ( int  mask) [inline, static]

Definition at line 889 of file hw.h.

References BIT.

{
        return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
}
const char* ath9k_hw_probe ( u16  vendorid,
u16  devid 
)
void ath9k_hw_deinit ( struct ath_hw ah)
int ath9k_hw_init ( struct ath_hw ah)

Definition at line 569 of file ath9k_hw.c.

References __ath9k_hw_init(), AR2427_DEVID_PCIE, AR5416_AR9100_DEVID, AR5416_DEVID_PCI, AR5416_DEVID_PCIE, AR9160_DEVID_PCI, AR9280_DEVID_PCI, AR9280_DEVID_PCIE, AR9285_DEVID_PCIE, AR9287_DEVID_PCI, AR9287_DEVID_PCIE, AR9300_DEVID_AR9340, AR9300_DEVID_AR9485_PCIE, AR9300_DEVID_PCIE, ath9k_hw_common(), ath_bus_ops::ath_bus_type, ATH_USB, ath_common::bus_ops, common, DBG, ath9k_hw_version::devid, EOPNOTSUPP, ath_hw::hw_version, and ret.

Referenced by ath9k_init_softc().

{
        int ret;
        struct ath_common *common = ath9k_hw_common(ah);

        /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
        switch (ah->hw_version.devid) {
        case AR5416_DEVID_PCI:
        case AR5416_DEVID_PCIE:
        case AR5416_AR9100_DEVID:
        case AR9160_DEVID_PCI:
        case AR9280_DEVID_PCI:
        case AR9280_DEVID_PCIE:
        case AR9285_DEVID_PCIE:
        case AR9287_DEVID_PCI:
        case AR9287_DEVID_PCIE:
        case AR2427_DEVID_PCIE:
        case AR9300_DEVID_PCIE:
        case AR9300_DEVID_AR9485_PCIE:
        case AR9300_DEVID_AR9340:
                break;
        default:
                if (common->bus_ops->ath_bus_type == ATH_USB)
                        break;
                DBG("ath9k: Hardware device ID 0x%04x not supported\n",
                        ah->hw_version.devid);
                return -EOPNOTSUPP;
        }

        ret = __ath9k_hw_init(ah);
        if (ret) {
                DBG("ath9k: "
                        "Unable to initialize hardware; initialization status: %d\n",
                        ret);
                return ret;
        }

        return 0;
}
int ath9k_hw_reset ( struct ath_hw ah,
struct ath9k_channel chan,
struct ath9k_hw_cal_data caldata,
int  bChannelChange 
)

Definition at line 1216 of file ath9k_hw.c.

References ar9002_hw_enable_async_fifo(), ar9002_hw_enable_wep_aggregation(), ar9002_hw_load_ani_reg(), ar9002_hw_update_async_fifo(), ar9003_hw_disable_phy_restart(), AR9271_GATE_MAC_CTL, AR9271_RADIO_RF_RST, AR9271_RESET_POWER_DOWN_CONTROL, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, AR_CFG, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, AR_CFG_LED_BLINK_SLOW, AR_CFG_LED_BLINK_THRESH_SEL, AR_CFG_LED_MODE_SEL, AR_CFG_SCLK_32KHZ, AR_CFG_SWRB, AR_CFG_SWRD, AR_CFG_SWRG, AR_CFG_SWTB, AR_CFG_SWTD, AR_DEF_ANTENNA, AR_DEVID_7010, AR_DQCUMASK, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE, AR_ISR, AR_NUM_DCU, AR_OBS, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE, AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT, AR_RIMT, AR_RIMT_FIRST, AR_RIMT_LAST, AR_RSSI_THR, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20_OR_LATER, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, AR_STA_ID0, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB, AR_STA_ID1_BASE_RATE_11B, AR_STA_ID1_PRESERVE_SEQNUM, AR_STA_ID1_RTS_USE_DEF, AR_TIMT, AR_TIMT_FIRST, AR_TIMT_LAST, ath9k_hw_ani_cache_ini_regs(), ath9k_hw_apply_gpio_override(), ATH9K_HW_CAP_RFSILENT, ath9k_hw_cfg_gpio_input(), ath9k_hw_channel_change(), ath9k_hw_chip_reset(), ath9k_hw_common(), ath9k_hw_getnf(), ath9k_hw_init_bb(), ath9k_hw_init_cal(), ath9k_hw_init_global_settings(), ath9k_hw_init_interrupt_masks(), ath9k_hw_loadnf(), ath9k_hw_mark_phy_inactive(), ath9k_hw_process_ini(), ath9k_hw_resettxqueue(), ath9k_hw_restore_chainmask(), ath9k_hw_rf_set_freq(), ath9k_hw_set_clockrate(), ath9k_hw_set_delta_slope(), ath9k_hw_set_dma(), ath9k_hw_set_operating_mode(), ath9k_hw_setpower(), ath9k_hw_spur_mitigate_freq(), ath9k_hw_start_nfcal(), ath9k_hw_write_associd(), ath9k_init_nfcal_hist_buffer(), ATH9K_NUM_TX_QUEUES, ATH9K_PM_AWAKE, ath_bus_ops::ath_bus_type, ath_hw_setbssidmask(), ATH_USB, ath_common::bus_ops, ath_hw::caldata, ath_hw::caps, ath9k_hw_cal_data::channel, ath9k_channel::channel, CHANNEL_ALL, CHANNEL_CW_INT, ath9k_hw_cal_data::channelFlags, ath9k_channel::channelFlags, ath_hw::chip_fullsleep, common, ath_hw::config, ath_hw::curchan, DBG, DBG2, ath_hw::eep_ops, EINVAL, EIO, ENABLE_REGWRITE_BUFFER, get_unaligned_le16(), get_unaligned_le32(), ath_hw::htc_reset_init, ath9k_hw_capabilities::hw_caps, INIT_CONFIG_STATUS, INIT_RSSI_THR, ath_hw::intr_txqs, IS_CHAN_HT, IS_CHAN_OFDM, ath_common::macaddr, memset(), NULL, ath_hw::paprd_table_write_done, r, REG_CLR_BIT, REG_READ, REG_RMW, REG_RMW_FIELD, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, ath_hw::rfkill_gpio, ath_common::rx_chainmask, ath9k_ops_config::rx_intr_mitigation, ath_hw::rxchainmask, eeprom_ops::set_board_values, ath_hw::sta_id1_defaults, ath_hw::sw_mgmt_crypto, ath_common::tx_chainmask, ath9k_ops_config::tx_intr_mitigation, ath_hw::txchainmask, and udelay().

Referenced by ath9k_start(), ath_radio_disable(), ath_reset(), and ath_set_channel().

{
        struct ath_common *common = ath9k_hw_common(ah);
        u32 saveLedState;
        struct ath9k_channel *curchan = ah->curchan;
        u32 saveDefAntenna;
        u32 macStaId1;
        int i, r;

        ah->txchainmask = common->tx_chainmask;
        ah->rxchainmask = common->rx_chainmask;

        if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                return -EIO;

        if (curchan && !ah->chip_fullsleep)
                ath9k_hw_getnf(ah, curchan);

        ah->caldata = caldata;
        if (caldata &&
            (chan->channel != caldata->channel ||
             (chan->channelFlags & ~CHANNEL_CW_INT) !=
             (caldata->channelFlags & ~CHANNEL_CW_INT))) {
                /* Operating channel changed, reset channel calibration data */
                memset(caldata, 0, sizeof(*caldata));
                ath9k_init_nfcal_hist_buffer(ah, chan);
        }

        if (bChannelChange &&
            (ah->chip_fullsleep != 1) &&
            (ah->curchan != NULL) &&
            (chan->channel != ah->curchan->channel) &&
            ((chan->channelFlags & CHANNEL_ALL) ==
             (ah->curchan->channelFlags & CHANNEL_ALL)) &&
            (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {

                if (ath9k_hw_channel_change(ah, chan)) {
                        ath9k_hw_loadnf(ah, ah->curchan);
                        ath9k_hw_start_nfcal(ah, 1);
                        if (AR_SREV_9271(ah))
                                ar9002_hw_load_ani_reg(ah, chan);
                        return 0;
                }
        }

        saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
        if (saveDefAntenna == 0)
                saveDefAntenna = 1;

        macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

        saveLedState = REG_READ(ah, AR_CFG_LED) &
                (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
                 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

        ath9k_hw_mark_phy_inactive(ah);

        ah->paprd_table_write_done = 0;

        /* Only required on the first reset */
        if (AR_SREV_9271(ah) && ah->htc_reset_init) {
                REG_WRITE(ah,
                          AR9271_RESET_POWER_DOWN_CONTROL,
                          AR9271_RADIO_RF_RST);
                udelay(50);
        }

        if (!ath9k_hw_chip_reset(ah, chan)) {
                DBG("ath9k: Chip reset failed\n");
                return -EINVAL;
        }

        /* Only required on the first reset */
        if (AR_SREV_9271(ah) && ah->htc_reset_init) {
                ah->htc_reset_init = 0;
                REG_WRITE(ah,
                          AR9271_RESET_POWER_DOWN_CONTROL,
                          AR9271_GATE_MAC_CTL);
                udelay(50);
        }

        if (AR_SREV_9280_20_OR_LATER(ah))
                REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);

        if (!AR_SREV_9300_20_OR_LATER(ah))
                ar9002_hw_enable_async_fifo(ah);

        r = ath9k_hw_process_ini(ah, chan);
        if (r)
                return r;

        /* Setup MFP options for CCMP */
        if (AR_SREV_9280_20_OR_LATER(ah)) {
                /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
                 * frames when constructing CCMP AAD. */
                REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
                              0xc7ff);
                ah->sw_mgmt_crypto = 0;
        } else if (AR_SREV_9160_10_OR_LATER(ah)) {
                /* Disable hardware crypto for management frames */
                REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
                            AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
                REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
                            AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
                ah->sw_mgmt_crypto = 1;
        } else
                ah->sw_mgmt_crypto = 1;

        if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
                ath9k_hw_set_delta_slope(ah, chan);

        ath9k_hw_spur_mitigate_freq(ah, chan);
        ah->eep_ops->set_board_values(ah, chan);

        ENABLE_REGWRITE_BUFFER(ah);

        REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
        REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
                  | macStaId1
                  | AR_STA_ID1_RTS_USE_DEF
                  | (ah->config.
                     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
                  | ah->sta_id1_defaults);
        ath_hw_setbssidmask(common);
        REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
        ath9k_hw_write_associd(ah);
        REG_WRITE(ah, AR_ISR, ~0);
        REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

        REGWRITE_BUFFER_FLUSH(ah);

        ath9k_hw_set_operating_mode(ah);

        r = ath9k_hw_rf_set_freq(ah, chan);
        if (r)
                return r;

        ath9k_hw_set_clockrate(ah);

        ENABLE_REGWRITE_BUFFER(ah);

        for (i = 0; i < AR_NUM_DCU; i++)
                REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

        REGWRITE_BUFFER_FLUSH(ah);

        ah->intr_txqs = 0;
        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
                ath9k_hw_resettxqueue(ah, i);

        ath9k_hw_init_interrupt_masks(ah);
        ath9k_hw_ani_cache_ini_regs(ah);

        if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
                ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);

        ath9k_hw_init_global_settings(ah);

        if (!AR_SREV_9300_20_OR_LATER(ah)) {
                ar9002_hw_update_async_fifo(ah);
                ar9002_hw_enable_wep_aggregation(ah);
        }

        REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);

        ath9k_hw_set_dma(ah);

        REG_WRITE(ah, AR_OBS, 8);

        if (ah->config.rx_intr_mitigation) {
                REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
                REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
        }

        if (ah->config.tx_intr_mitigation) {
                REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
                REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
        }

        ath9k_hw_init_bb(ah, chan);

        if (!ath9k_hw_init_cal(ah, chan))
                return -EIO;

        ENABLE_REGWRITE_BUFFER(ah);

        ath9k_hw_restore_chainmask(ah);
        REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

        REGWRITE_BUFFER_FLUSH(ah);

        /*
         * For big endian systems turn on swapping for descriptors
         */
        if (AR_SREV_9100(ah)) {
                u32 mask;
                mask = REG_READ(ah, AR_CFG);
                if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
                        DBG2("ath9k: "
                                "CFG Byte Swap Set 0x%x\n", mask);
                } else {
                        mask =
                                INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
                        REG_WRITE(ah, AR_CFG, mask);
                        DBG2("ath9k: "
                                "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
                }
        } else {
                if (common->bus_ops->ath_bus_type == ATH_USB) {
                        /* Configure AR9271 target WLAN */
                        if (AR_SREV_9271(ah))
                                REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
                        else
                                REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
                }
#if __BYTE_ORDER == __BIG_ENDIAN
                else if (AR_SREV_9340(ah))
                        REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
                else
                        REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
#endif
        }

        if (AR_SREV_9300_20_OR_LATER(ah)) {
                ar9003_hw_disable_phy_restart(ah);
        }

        ath9k_hw_apply_gpio_override(ah);

        return 0;
}
int ath9k_hw_fill_cap_info ( struct ath_hw ah)

Definition at line 1569 of file ath9k_hw.c.

References AR5416_DEVID_PCI, AR5416_EEP_MINOR_VER_16, AR5416_OPFLAGS_11A, AR5416_OPFLAGS_11G, AR7010_NUM_GPIO, AR9271_NUM_GPIO, AR9285_NUM_GPIO, AR9285_RDEXT_DEFAULT, AR928X_NUM_GPIO, AR_DEVID_7010, AR_ENT_OTP, AR_NUM_GPIO, AR_PCU_ALWAYS_PERFORM_KEYSEARCH, AR_PCU_MIC_NEW_LOC_ENA, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, AR_SREV_9271, AR_SREV_9280, AR_SREV_9280_20, AR_SREV_9280_20_OR_LATER, AR_SREV_9285, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, AR_SREV_9300_20_OR_LATER, AR_SREV_9485, AR_SREV_9485_10, AR_SUBVENDOR_ID_NEW_A, ATH9K_HW_CAP_2GHZ, ATH9K_HW_CAP_4KB_SPLITTRANS, ATH9K_HW_CAP_5GHZ, ATH9K_HW_CAP_ANT_DIV_COMB, ATH9K_HW_CAP_APM, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_HW_CAP_CST, ATH9K_HW_CAP_FASTCLOCK, ATH9K_HW_CAP_HT, ATH9K_HW_CAP_LDPC, ATH9K_HW_CAP_PAPRD, ATH9K_HW_CAP_RAC_SUPPORTED, ATH9K_HW_CAP_RFSILENT, ATH9K_HW_CAP_SGI_20, ath9k_hw_common(), ath9k_hw_gpio_get(), ath9k_hw_regulatory(), ATH9K_HW_RX_HP_QDEPTH, ATH9K_HW_RX_LP_QDEPTH, ATH_AMPDU_LIMIT_MAX, ATH_CRYPT_CAP_CIPHER_AESCCM, BIT, ath_hw::caps, common, ath_hw::config, ath_common::crypt_caps, ath_regulatory::current_rd, ath_regulatory::current_rd_ext, DBG, DBG2, ath9k_hw_version::devid, EEP_ANT_DIV_CTL1, EEP_CHAIN_MASK_REDUCE, EEP_FSTCLK_5G, EEP_MINOR_REV, EEP_MODAL_VER, EEP_OP_MODE, ath_hw::eep_ops, EEP_PAPRD, EEP_REG_0, EEP_REG_1, EEP_RF_SILENT, EEP_RFSILENT_ENABLED, EEP_RFSILENT_GPIO_SEL, EEP_RFSILENT_POLARITY, EEP_RX_MASK, EEP_TX_MASK, EINVAL, ath_hw::ent_mode, eeprom_ops::get_eeprom, ath9k_hw_capabilities::hw_caps, ath_hw::hw_version, ath9k_hw_capabilities::max_rxchains, ath9k_hw_capabilities::max_txchains, ath_hw::misc_mode, MS, ath9k_hw_capabilities::num_gpio_pins, ath9k_ops_config::paprd_disable, ath9k_hw_capabilities::pcie_lcr_extsync_en, ath9k_hw_capabilities::pcie_lcr_offset, REG_READ, ath_hw::rfkill_gpio, ath_hw::rfkill_polarity, ath_hw::rfsilent, ath9k_hw_capabilities::rts_aggr_limit, ath9k_hw_capabilities::rx_chainmask, ath_common::rx_chainmask, ath9k_hw_capabilities::rx_hp_qdepth, ath9k_hw_capabilities::rx_lp_qdepth, ath9k_hw_capabilities::rx_status_len, ath9k_hw_version::subvendorid, ath9k_hw_capabilities::tx_chainmask, ath_common::tx_chainmask, ath9k_hw_capabilities::tx_desc_len, and ath9k_hw_capabilities::txs_len.

Referenced by __ath9k_hw_init().

{
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ath_common *common = ath9k_hw_common(ah);

        u16 eeval;
        u8 ant_div_ctl1, tx_chainmask, rx_chainmask;

        eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
        regulatory->current_rd = eeval;

        eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
        if (AR_SREV_9285_12_OR_LATER(ah))
                eeval |= AR9285_RDEXT_DEFAULT;
        regulatory->current_rd_ext = eeval;

        if (ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
                if (regulatory->current_rd == 0x64 ||
                    regulatory->current_rd == 0x65)
                        regulatory->current_rd += 5;
                else if (regulatory->current_rd == 0x41)
                        regulatory->current_rd = 0x43;
                DBG2("ath9k: "
                        "regdomain mapped to 0x%x\n", regulatory->current_rd);
        }

        eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
        if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
                DBG("ath9k: "
                        "no band has been marked as supported in EEPROM\n");
                return -EINVAL;
        }

        if (eeval & AR5416_OPFLAGS_11A)
                pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;

        if (eeval & AR5416_OPFLAGS_11G)
                pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;

        pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
        /*
         * For AR9271 we will temporarilly uses the rx chainmax as read from
         * the EEPROM.
         */
        if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
            !(eeval & AR5416_OPFLAGS_11A) &&
            !(AR_SREV_9271(ah)))
                /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
                pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
        else if (AR_SREV_9100(ah))
                pCap->rx_chainmask = 0x7;
        else
                /* Use rx_chainmask from EEPROM. */
                pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);

        ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;

        /* enable key search for every frame in an aggregate */
        if (AR_SREV_9300_20_OR_LATER(ah))
                ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;

        common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;

        pCap->hw_caps &= ~ATH9K_HW_CAP_HT;

        if (AR_SREV_9271(ah))
                pCap->num_gpio_pins = AR9271_NUM_GPIO;
        else if (AR_DEVID_7010(ah))
                pCap->num_gpio_pins = AR7010_NUM_GPIO;
        else if (AR_SREV_9285_12_OR_LATER(ah))
                pCap->num_gpio_pins = AR9285_NUM_GPIO;
        else if (AR_SREV_9280_20_OR_LATER(ah))
                pCap->num_gpio_pins = AR928X_NUM_GPIO;
        else
                pCap->num_gpio_pins = AR_NUM_GPIO;

        if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
                pCap->hw_caps |= ATH9K_HW_CAP_CST;
                pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
        } else {
                pCap->rts_aggr_limit = (8 * 1024);
        }

        ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
        if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
                ah->rfkill_gpio =
                        MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
                ah->rfkill_polarity =
                        MS(ah->rfsilent, EEP_RFSILENT_POLARITY);

                pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
        }

        pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;

        if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
                pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
        else
                pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;

        if (AR_SREV_9300_20_OR_LATER(ah)) {
                pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
                if (!AR_SREV_9485(ah))
                        pCap->hw_caps |= ATH9K_HW_CAP_LDPC;

                pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
                pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
                pCap->rx_status_len = sizeof(struct ar9003_rxs);
                pCap->tx_desc_len = sizeof(struct ar9003_txc);
                pCap->txs_len = sizeof(struct ar9003_txs);
                if (!ah->config.paprd_disable &&
                    ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
                        pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
        } else {
                pCap->tx_desc_len = sizeof(struct ath_desc);
                if (AR_SREV_9280_20(ah) &&
                    ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
                      AR5416_EEP_MINOR_VER_16) ||
                     ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
                        pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
        }

        if (AR_SREV_9300_20_OR_LATER(ah))
                pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;

        if (AR_SREV_9300_20_OR_LATER(ah))
                ah->ent_mode = REG_READ(ah, AR_ENT_OTP);

        if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
                pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;

        if (AR_SREV_9285(ah))
                if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
                        ant_div_ctl1 =
                                ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
                        if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
                                pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
                }
        if (AR_SREV_9300_20_OR_LATER(ah)) {
                if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
                        pCap->hw_caps |= ATH9K_HW_CAP_APM;
        }


        if (AR_SREV_9485(ah)) {
                ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
                /*
                 * enable the diversity-combining algorithm only when
                 * both enable_lna_div and enable_fast_div are set
                 *              Table for Diversity
                 * ant_div_alt_lnaconf          bit 0-1
                 * ant_div_main_lnaconf         bit 2-3
                 * ant_div_alt_gaintb           bit 4
                 * ant_div_main_gaintb          bit 5
                 * enable_ant_div_lnadiv        bit 6
                 * enable_ant_fast_div          bit 7
                 */
                if ((ant_div_ctl1 >> 0x6) == 0x3)
                        pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
        }

        if (AR_SREV_9485_10(ah)) {
                pCap->pcie_lcr_extsync_en = 1;
                pCap->pcie_lcr_offset = 0x80;
        }

        tx_chainmask = pCap->tx_chainmask;
        rx_chainmask = pCap->rx_chainmask;
        while (tx_chainmask || rx_chainmask) {
                if (tx_chainmask & BIT(0))
                        pCap->max_txchains++;
                if (rx_chainmask & BIT(0))
                        pCap->max_rxchains++;

                tx_chainmask >>= 1;
                rx_chainmask >>= 1;
        }

        return 0;
}
u32 ath9k_regd_get_ctl ( struct ath_regulatory reg,
struct ath9k_channel chan 
)
void ath9k_hw_cfg_gpio_input ( struct ath_hw ah,
u32  gpio 
)

Definition at line 1783 of file ath9k_hw.c.

References AR7010_GPIO_OE, AR7010_GPIO_OE_AS_INPUT, AR7010_GPIO_OE_MASK, AR_DEVID_7010, AR_GPIO_OE_OUT, AR_GPIO_OE_OUT_DRV, AR_GPIO_OE_OUT_DRV_NO, gpio, and REG_RMW.

Referenced by ath9k_hw_reset(), and ath_radio_disable().

{
        u32 gpio_shift;

        if (AR_DEVID_7010(ah)) {
                gpio_shift = gpio;
                REG_RMW(ah, AR7010_GPIO_OE,
                        (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
                        (AR7010_GPIO_OE_MASK << gpio_shift));
                return;
        }

        gpio_shift = gpio << 1;
        REG_RMW(ah,
                AR_GPIO_OE_OUT,
                (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
                (AR_GPIO_OE_OUT_DRV << gpio_shift));
}
u32 ath9k_hw_gpio_get ( struct ath_hw ah,
u32  gpio 
)

Definition at line 1802 of file ath9k_hw.c.

References AR7010_GPIO_IN, AR7010_GPIO_IN_VAL, AR9300_GPIO_IN_VAL, AR_DEVID_7010, AR_GPIO_BIT, AR_GPIO_IN, AR_SREV_9271, AR_SREV_9280_20_OR_LATER, AR_SREV_9285_12_OR_LATER, AR_SREV_9287_11_OR_LATER, AR_SREV_9300_20_OR_LATER, ath_hw::caps, MS, MS_REG_READ, ath9k_hw_capabilities::num_gpio_pins, REG_READ, and val.

Referenced by ath9k_hw_fill_cap_info().

{
#define MS_REG_READ(x, y) \
        (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

        if (gpio >= ah->caps.num_gpio_pins)
                return 0xffffffff;

        if (AR_DEVID_7010(ah)) {
                u32 val;
                val = REG_READ(ah, AR7010_GPIO_IN);
                return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
        } else if (AR_SREV_9300_20_OR_LATER(ah))
                return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
                        AR_GPIO_BIT(gpio)) != 0;
        else if (AR_SREV_9271(ah))
                return MS_REG_READ(AR9271, gpio) != 0;
        else if (AR_SREV_9287_11_OR_LATER(ah))
                return MS_REG_READ(AR9287, gpio) != 0;
        else if (AR_SREV_9285_12_OR_LATER(ah))
                return MS_REG_READ(AR9285, gpio) != 0;
        else if (AR_SREV_9280_20_OR_LATER(ah))
                return MS_REG_READ(AR928X, gpio) != 0;
        else
                return MS_REG_READ(AR, gpio) != 0;
}
void ath9k_hw_cfg_output ( struct ath_hw ah,
u32  gpio,
u32  ah_signal_type 
)

Definition at line 1829 of file ath9k_hw.c.

References AR7010_GPIO_OE, AR7010_GPIO_OE_AS_OUTPUT, AR7010_GPIO_OE_MASK, AR_DEVID_7010, AR_GPIO_OE_OUT, AR_GPIO_OE_OUT_DRV, AR_GPIO_OE_OUT_DRV_ALL, ath9k_hw_gpio_cfg_output_mux(), gpio, and REG_RMW.

Referenced by ath9k_hw_apply_gpio_override().

{
        u32 gpio_shift;

        if (AR_DEVID_7010(ah)) {
                gpio_shift = gpio;
                REG_RMW(ah, AR7010_GPIO_OE,
                        (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
                        (AR7010_GPIO_OE_MASK << gpio_shift));
                return;
        }

        ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
        gpio_shift = 2 * gpio;
        REG_RMW(ah,
                AR_GPIO_OE_OUT,
                (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
                (AR_GPIO_OE_OUT_DRV << gpio_shift));
}
void ath9k_hw_set_gpio ( struct ath_hw ah,
u32  gpio,
u32  val 
)

Definition at line 1850 of file ath9k_hw.c.

References AR7010_GPIO_OUT, AR_DEVID_7010, AR_GPIO_BIT, AR_GPIO_IN_OUT, AR_SREV_9271, and REG_RMW.

Referenced by ath9k_hw_apply_gpio_override(), and ath_radio_disable().

{
        if (AR_DEVID_7010(ah)) {
                val = val ? 0 : 1;
                REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
                        AR_GPIO_BIT(gpio));
                return;
        }

        if (AR_SREV_9271(ah))
                val = ~val;

        REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
                AR_GPIO_BIT(gpio));
}
u32 ath9k_hw_getdefantenna ( struct ath_hw ah)

Definition at line 1866 of file ath9k_hw.c.

References AR_DEF_ANTENNA, and REG_READ.

Referenced by ath9k_init_misc().

{
        return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
}
void ath9k_hw_setantenna ( struct ath_hw ah,
u32  antenna 
)

Definition at line 1871 of file ath9k_hw.c.

References AR_DEF_ANTENNA, and REG_WRITE.

Referenced by ath_setdefantenna().

{
        REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
}
int ath9k_hw_wait ( struct ath_hw ah,
u32  reg,
u32  mask,
u32  val,
u32  timeout 
)

Definition at line 93 of file ath9k_hw.c.

References AH_TIME_QUANTUM, DBG, REG_READ, udelay(), and val.

Referenced by ar5008_hw_rfbus_req(), ar9002_hw_init_cal(), ar9003_hw_init_cal(), ar9003_hw_rfbus_req(), ar9003_hw_tx_iq_cal_run(), ar9285_hw_cl_cal(), ar9300_otp_read_word(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_setrxabort(), and ath_pci_eeprom_read().

{
        unsigned int i;

        for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
                if ((REG_READ(ah, reg) & mask) == val)
                        return 1;

                udelay(AH_TIME_QUANTUM);
        }

        DBG("ath9k: "
                "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
                timeout, reg, REG_READ(ah, reg), mask, val);

        return 0;
}
void ath9k_hw_write_array ( struct ath_hw ah,
struct ar5416IniArray array,
int  column,
unsigned int *  writecnt 
)

Definition at line 111 of file ath9k_hw.c.

References DO_DELAY, ENABLE_REGWRITE_BUFFER, ar5416IniArray::ia_rows, INI_RA, r, REG_WRITE, and REGWRITE_BUFFER_FLUSH.

{
        unsigned int r;

        ENABLE_REGWRITE_BUFFER(ah);
        for (r = 0; r < array->ia_rows; r++) {
                REG_WRITE(ah, INI_RA(array, r, 0),
                          INI_RA(array, r, column));
                DO_DELAY(*writecnt);
        }
        REGWRITE_BUFFER_FLUSH(ah);
}
u32 ath9k_hw_reverse_bits ( u32  val,
u32  n 
)

Definition at line 125 of file ath9k_hw.c.

Referenced by ar5008_hw_force_bias(), ar5008_hw_phy_modify_rx_buffer(), ar5008_hw_set_channel(), and ar9002_hw_get_radiorev().

{
        u32 retval;
        unsigned int i;

        for (i = 0, retval = 0; i < n; i++) {
                retval = (retval << 1) | (val & 1);
                val >>= 1;
        }
        return retval;
}
u16 ath9k_hw_computetxtime ( struct ath_hw ah,
u8  phy,
int  kbps,
u32  frameLen,
u16  rateix,
int  shortPreamble 
)

Definition at line 137 of file ath9k_hw.c.

References CCK_PLCP_BITS, CCK_PREAMBLE_BITS, CCK_SIFS_TIME, CHANNEL_CCK, CHANNEL_OFDM, ath_hw::curchan, DBG, DIV_ROUND_UP, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, OFDM_PLCP_BITS, OFDM_PREAMBLE_TIME, OFDM_PREAMBLE_TIME_HALF, OFDM_PREAMBLE_TIME_QUARTER, OFDM_SIFS_TIME, OFDM_SIFS_TIME_HALF, OFDM_SIFS_TIME_QUARTER, OFDM_SYMBOL_TIME, OFDM_SYMBOL_TIME_HALF, and OFDM_SYMBOL_TIME_QUARTER.

Referenced by ath_buf_set_rate().

{
        u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;

        if (kbps == 0)
                return 0;

        switch (phy) {
        case CHANNEL_CCK:
                phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
                if (shortPreamble)
                        phyTime >>= 1;
                numBits = frameLen << 3;
                txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
                break;
        case CHANNEL_OFDM:
                if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
                        bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
                        numBits = OFDM_PLCP_BITS + (frameLen << 3);
                        numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
                        txTime = OFDM_SIFS_TIME_QUARTER
                                + OFDM_PREAMBLE_TIME_QUARTER
                                + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
                } else if (ah->curchan &&
                           IS_CHAN_HALF_RATE(ah->curchan)) {
                        bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
                        numBits = OFDM_PLCP_BITS + (frameLen << 3);
                        numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
                        txTime = OFDM_SIFS_TIME_HALF +
                                OFDM_PREAMBLE_TIME_HALF
                                + (numSymbols * OFDM_SYMBOL_TIME_HALF);
                } else {
                        bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
                        numBits = OFDM_PLCP_BITS + (frameLen << 3);
                        numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
                        txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
                                + (numSymbols * OFDM_SYMBOL_TIME);
                }
                break;
        default:
                DBG("ath9k: "
                        "Unknown phy %d (rate ix %d)\n", phy, rateix);
                txTime = 0;
                break;
        }

        return txTime;
}
void ath9k_hw_get_channel_centers ( struct ath_hw ah,
struct ath9k_channel chan,
struct chan_centers centers 
)
u32 ath9k_hw_getrxfilter ( struct ath_hw ah)
void ath9k_hw_setrxfilter ( struct ath_hw ah,
u32  bits 
)
int ath9k_hw_phy_disable ( struct ath_hw ah)

Definition at line 1916 of file ath9k_hw.c.

References ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ATH9K_RESET_WARM, and NULL.

Referenced by ath9k_stop(), and ath_radio_disable().

{
        if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
                return 0;

        ath9k_hw_init_pll(ah, NULL);
        return 1;
}
int ath9k_hw_disable ( struct ath_hw ah)

Definition at line 1925 of file ath9k_hw.c.

References ath9k_hw_init_pll(), ath9k_hw_set_reset_reg(), ath9k_hw_setpower(), ATH9K_PM_AWAKE, ATH9K_RESET_COLD, and NULL.

Referenced by ath9k_stop().

{
        if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                return 0;

        if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
                return 0;

        ath9k_hw_init_pll(ah, NULL);
        return 1;
}
void ath9k_hw_set_txpowerlimit ( struct ath_hw ah,
u32  limit,
int  test 
)
void ath9k_hw_setopmode ( struct ath_hw ah)

Definition at line 1953 of file ath9k_hw.c.

References ath9k_hw_set_operating_mode().

Referenced by ath_opmode_init().

void ath9k_hw_setmcastfilter ( struct ath_hw ah,
u32  filter0,
u32  filter1 
)

Definition at line 1958 of file ath9k_hw.c.

References AR_MCAST_FIL0, AR_MCAST_FIL1, and REG_WRITE.

Referenced by ath_opmode_init().

{
        REG_WRITE(ah, AR_MCAST_FIL0, filter0);
        REG_WRITE(ah, AR_MCAST_FIL1, filter1);
}
void ath9k_hw_setbssidmask ( struct ath_hw ah)
void ath9k_hw_write_associd ( struct ath_hw ah)
void ath9k_hw_init_global_settings ( struct ath_hw ah)

Definition at line 812 of file ath9k_hw.c.

References AR_PCU_MISC, ath9k_hw_set_ack_timeout(), ath9k_hw_set_cts_timeout(), ath9k_hw_set_global_txtimeout(), ath9k_hw_setslottime(), net80211_device::channel, net80211_device::channels, ath_hw::coverage_class, DBG2, ath_hw::dev, ath_hw::globaltxtimeout, ath_hw::misc_mode, NET80211_BAND_2GHZ, NET80211_BAND_5GHZ, REG_SET_BIT, and ath_hw::slottime.

Referenced by ath9k_bss_info_changed(), and ath9k_hw_reset().

{
        int acktimeout;
        int slottime;
        int sifstime;

        DBG2("ath9k: ah->misc_mode 0x%x\n",
                ah->misc_mode);

        if (ah->misc_mode != 0)
                REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);

        if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_5GHZ)
                sifstime = 16;
        else
                sifstime = 10;

        /* As defined by IEEE 802.11-2007 17.3.8.6 */
        slottime = ah->slottime + 3 * ah->coverage_class;
        acktimeout = slottime + sifstime;

        /*
         * Workaround for early ACK timeouts, add an offset to match the
         * initval's 64us ack timeout value.
         * This was initially only meant to work around an issue with delayed
         * BA frames in some implementations, but it has been found to fix ACK
         * timeout issues in other cases as well.
         */
        if ((ah->dev->channels + ah->dev->channel)->band == NET80211_BAND_2GHZ)
                acktimeout += 64 - sifstime - ah->slottime;

        ath9k_hw_setslottime(ah, ah->slottime);
        ath9k_hw_set_ack_timeout(ah, acktimeout);
        ath9k_hw_set_cts_timeout(ah, acktimeout);
        if (ah->globaltxtimeout != (u32) -1)
                ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
}

Definition at line 609 of file ath9k_hw.c.

References PLL3, PLL3_DO_MEAS_MASK, PLL4, PLL4_MEAS_DONE, REG_CLR_BIT, REG_READ, REG_SET_BIT, SQSUM_DVC_MASK, and udelay().

Referenced by ath_hw_pll_work().

{
        REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
        udelay(100);
        REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);

        while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
                udelay(100);

        return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
}
void ath9k_hw_set11nmac2040 ( struct ath_hw ah)

Definition at line 1973 of file ath9k_hw.c.

References AR_2040_MODE, and REG_WRITE.

Referenced by ar5008_hw_set_channel_regs(), and ar9003_hw_set_channel_regs().

{
        u32 macmode;

        macmode = 0;

        REG_WRITE(ah, AR_2040_MODE, macmode);
}
int ath9k_hw_check_alive ( struct ath_hw ah)

Definition at line 1189 of file ath9k_hw.c.

References AR_OBS_BUS_1, AR_SREV_9285_12_OR_LATER, count, reg, and REG_READ.

Referenced by ath_hw_check(), and ath_set_channel().

{
        int count = 50;
        u32 reg;

        if (AR_SREV_9285_12_OR_LATER(ah))
                return 1;

        do {
                reg = REG_READ(ah, AR_OBS_BUS_1);

                if ((reg & 0x7E7FFFEF) == 0x00702400)
                        continue;

                switch (reg & 0x7E000B00) {
                case 0x1E000000:
                case 0x52000B00:
                case 0x18000B00:
                        continue;
                default:
                        return 1;
                }
        } while (count-- > 0);

        return 0;
}
int ath9k_hw_setpower ( struct ath_hw ah,
enum ath9k_power_mode  mode 
)

Definition at line 1532 of file ath9k_hw.c.

References ath9k_hw_set_power_awake(), ATH9K_PM_AWAKE, ATH9K_PM_FULL_SLEEP, ath9k_set_power_sleep(), ath_hw::chip_fullsleep, DBG, DBG2, ath_hw::power_mode, and status.

Referenced by __ath9k_hw_init(), ath9k_hw_chip_reset(), ath9k_hw_deinit(), ath9k_hw_disable(), ath9k_hw_reset(), and ath9k_setpower().

{
        int status = 1, setChip = 1;
        static const char *modes[] = {
                "AWAKE",
                "FULL-SLEEP",
                "NETWORK SLEEP",
                "UNDEFINED"
        };

        if (ah->power_mode == mode)
                return status;

        DBG2("ath9k: %s -> %s\n",
                modes[ah->power_mode], modes[mode]);

        switch (mode) {
        case ATH9K_PM_AWAKE:
                status = ath9k_hw_set_power_awake(ah, setChip);
                break;
        case ATH9K_PM_FULL_SLEEP:
                ath9k_set_power_sleep(ah, setChip);
                ah->chip_fullsleep = 1;
                break;
        default:
                DBG("ath9k: Unknown power mode %d\n", mode);
                return 0;
        }
        ah->power_mode = mode;

        return status;
}
void ath9k_hw_name ( struct ath_hw ah,
char *  hw_name,
size_t  len 
)

Definition at line 2045 of file ath9k_hw.c.

References ath9k_hw_version::analog5GhzRev, AR_RADIO_SREV_MAJOR, AR_SREV_9280_20_OR_LATER, ath9k_hw_mac_bb_name(), ath9k_hw_rf_name(), ath_hw::hw_version, ath9k_hw_version::macRev, ath9k_hw_version::macVersion, ath9k_hw_version::phyRev, and snprintf().

Referenced by ath_pci_probe().

{
        int used;

        /* chipsets >= AR9280 are single-chip */
        if (AR_SREV_9280_20_OR_LATER(ah)) {
                used = snprintf(hw_name, len,
                               "Atheros AR%s Rev:%x",
                               ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
                               ah->hw_version.macRev);
        }
        else {
                used = snprintf(hw_name, len,
                               "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
                               ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
                               ah->hw_version.macRev,
                               ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
                                                AR_RADIO_SREV_MAJOR)),
                               ah->hw_version.phyRev);
        }

        hw_name[used] = '\0';
}
void ath9k_hw_htc_resetinit ( struct ath_hw ah)
void ath9k_hw_get_delta_slope_vals ( struct ath_hw ah,
u32  coef_scaled,
u32 coef_mantissa,
u32 coef_exponent 
)
void ar9002_hw_cck_chan14_spread ( struct ath_hw ah)
int ar9002_hw_rf_claim ( struct ath_hw ah)

Definition at line 464 of file ath9k_ar9002_hw.c.

References ath9k_hw_version::analog5GhzRev, ar9002_hw_get_radiorev(), AR_PHY, AR_RAD2122_SREV_MAJOR, AR_RAD2133_SREV_MAJOR, AR_RAD5122_SREV_MAJOR, AR_RAD5133_SREV_MAJOR, AR_RADIO_SREV_MAJOR, DBG, EOPNOTSUPP, ath_hw::hw_version, REG_WRITE, and val.

Referenced by ath9k_hw_post_init().

{
        u32 val;

        REG_WRITE(ah, AR_PHY(0), 0x00000007);

        val = ar9002_hw_get_radiorev(ah);
        switch (val & AR_RADIO_SREV_MAJOR) {
        case 0:
                val = AR_RAD5133_SREV_MAJOR;
                break;
        case AR_RAD5133_SREV_MAJOR:
        case AR_RAD5122_SREV_MAJOR:
        case AR_RAD2133_SREV_MAJOR:
        case AR_RAD2122_SREV_MAJOR:
                break;
        default:
                DBG("ath9k: "
                        "Radio Chip Rev 0x%02X not supported\n",
                        val & AR_RADIO_SREV_MAJOR);
                return -EOPNOTSUPP;
        }

        ah->hw_version.analog5GhzRev = val;

        return 0;
}
void ar9002_hw_enable_async_fifo ( struct ath_hw ah)
void ar9002_hw_update_async_fifo ( struct ath_hw ah)
void ar9003_hw_disable_phy_restart ( struct ath_hw ah)

Definition at line 1270 of file ath9k_ar9003_phy.c.

References AR_PHY_RESTART, AR_PHY_RESTART_ENA, REG_READ, REG_WRITE, and val.

Referenced by ath9k_hw_reset().

void ar5008_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 1618 of file ath9k_ar5008_phy.c.

References ath_hw_private_ops::ani_cache_ini_regs, ath_hw_private_ops::ani_control, ar5008_hw_ani_cache_ini_regs(), ar5008_hw_ani_control_new(), ar5008_hw_ani_control_old(), ar5008_hw_compute_pll_control(), ar5008_hw_do_getnf(), ar5008_hw_init_bb(), ar5008_hw_mark_phy_inactive(), ar5008_hw_process_ini(), ar5008_hw_rf_alloc_ext_banks(), ar5008_hw_rf_free_ext_banks(), ar5008_hw_rfbus_done(), ar5008_hw_rfbus_req(), ar5008_hw_set_channel(), ar5008_hw_set_channel_regs(), ar5008_hw_set_delta_slope(), ar5008_hw_set_nf_limits(), ar5008_hw_set_radar_conf(), ar5008_hw_set_radar_params(), ar5008_hw_set_rf_regs(), ar5008_hw_set_rfmode(), ar5008_hw_spur_mitigate(), ar5008_restore_chainmask(), ar5008_set_diversity(), ar9100_hw_compute_pll_control(), ar9160_hw_compute_pll_control(), AR_PHY_CCA, AR_PHY_CH1_CCA, AR_PHY_CH1_EXT_CCA, AR_PHY_CH2_CCA, AR_PHY_CH2_EXT_CCA, AR_PHY_EXT_CCA, AR_SREV_9100, AR_SREV_9160_10_OR_LATER, ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, ath_hw_private_ops::init_bb, ath_hw_private_ops::mark_phy_inactive, memcpy(), modparam_force_new_ani, ath_hw::nf_regs, ath_hw_private_ops::process_ini, ath_hw_private_ops::restore_chainmask, ath_hw_private_ops::rf_alloc_ext_banks, ath_hw_private_ops::rf_free_ext_banks, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::rfbus_done, ath_hw_private_ops::rfbus_req, ath_hw_private_ops::set_channel_regs, ath_hw_private_ops::set_delta_slope, ath_hw_private_ops::set_diversity, ath_hw_private_ops::set_radar_params, ath_hw_private_ops::set_rf_regs, ath_hw_private_ops::set_rfmode, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9002_hw_attach_ops().

{
        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
        static const u32 ar5416_cca_regs[6] = {
                AR_PHY_CCA,
                AR_PHY_CH1_CCA,
                AR_PHY_CH2_CCA,
                AR_PHY_EXT_CCA,
                AR_PHY_CH1_EXT_CCA,
                AR_PHY_CH2_EXT_CCA
        };

        priv_ops->rf_set_freq = ar5008_hw_set_channel;
        priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;

        priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
        priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
        priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
        priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
        priv_ops->init_bb = ar5008_hw_init_bb;
        priv_ops->process_ini = ar5008_hw_process_ini;
        priv_ops->set_rfmode = ar5008_hw_set_rfmode;
        priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
        priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
        priv_ops->rfbus_req = ar5008_hw_rfbus_req;
        priv_ops->rfbus_done = ar5008_hw_rfbus_done;
        priv_ops->restore_chainmask = ar5008_restore_chainmask;
        priv_ops->set_diversity = ar5008_set_diversity;
        priv_ops->do_getnf = ar5008_hw_do_getnf;
        priv_ops->set_radar_params = ar5008_hw_set_radar_params;

        if (modparam_force_new_ani) {
                priv_ops->ani_control = ar5008_hw_ani_control_new;
                priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
        } else
                priv_ops->ani_control = ar5008_hw_ani_control_old;

        if (AR_SREV_9100(ah))
                priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
        else if (AR_SREV_9160_10_OR_LATER(ah))
                priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
        else
                priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;

        ar5008_hw_set_nf_limits(ah);
        ar5008_hw_set_radar_conf(ah);
        memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
}
void ar9002_hw_attach_phy_ops ( struct ath_hw ah)
void ar9003_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 1232 of file ath9k_ar9003_phy.c.

References ath_hw_private_ops::ani_cache_ini_regs, ath_hw_private_ops::ani_control, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ani_control(), ar9003_hw_antdiv_comb_conf_get(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_compute_pll_control(), ar9003_hw_do_getnf(), ar9003_hw_init_bb(), ar9003_hw_mark_phy_inactive(), ar9003_hw_process_ini(), ar9003_hw_rfbus_done(), ar9003_hw_rfbus_req(), ar9003_hw_set_channel(), ar9003_hw_set_channel_regs(), ar9003_hw_set_delta_slope(), ar9003_hw_set_diversity(), ar9003_hw_set_nf_limits(), ar9003_hw_set_radar_conf(), ar9003_hw_set_radar_params(), ar9003_hw_set_rfmode(), ar9003_hw_spur_mitigate(), AR_PHY_CCA_0, AR_PHY_CCA_1, AR_PHY_CCA_2, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_1, AR_PHY_EXT_CCA_2, ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, ath_hw_private_ops::init_bb, ath_hw_private_ops::mark_phy_inactive, memcpy(), ath_hw::nf_regs, ath_hw_private_ops::process_ini, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::rfbus_done, ath_hw_private_ops::rfbus_req, ath_hw_private_ops::set_channel_regs, ath_hw_private_ops::set_delta_slope, ath_hw_private_ops::set_diversity, ath_hw_private_ops::set_radar_params, ath_hw_private_ops::set_rfmode, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9003_hw_attach_ops().

void ar9002_hw_attach_calib_ops ( struct ath_hw ah)
void ar9003_hw_attach_calib_ops ( struct ath_hw ah)
void ar9002_hw_attach_ops ( struct ath_hw ah)
void ar9003_hw_attach_ops ( struct ath_hw ah)
void ar9002_hw_load_ani_reg ( struct ath_hw ah,
struct ath9k_channel chan 
)

Definition at line 563 of file ath9k_ar9002_hw.c.

References AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, ath9k_channel::chanmode, CHANNEL_A, CHANNEL_A_HT20, CHANNEL_A_HT40MINUS, CHANNEL_A_HT40PLUS, CHANNEL_B, CHANNEL_G, CHANNEL_G_HT20, CHANNEL_G_HT40MINUS, CHANNEL_G_HT40PLUS, ENABLE_REGWRITE_BUFFER, ar5416IniArray::ia_rows, INI_RA, ath_hw::iniModes_9271_ANI_reg, reg, REG_READ, REG_WRITE, REGWRITE_BUFFER_FLUSH, and val.

Referenced by ath9k_hw_reset().

{
        u32 modesIndex;
        unsigned int i;

        switch (chan->chanmode) {
        case CHANNEL_A:
        case CHANNEL_A_HT20:
                modesIndex = 1;
                break;
        case CHANNEL_A_HT40PLUS:
        case CHANNEL_A_HT40MINUS:
                modesIndex = 2;
                break;
        case CHANNEL_G:
        case CHANNEL_G_HT20:
        case CHANNEL_B:
                modesIndex = 4;
                break;
        case CHANNEL_G_HT40PLUS:
        case CHANNEL_G_HT40MINUS:
                modesIndex = 3;
                break;

        default:
                return;
        }

        ENABLE_REGWRITE_BUFFER(ah);

        for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
                u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
                u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
                u32 val_orig;

                if (reg == AR_PHY_CCK_DETECT) {
                        val_orig = REG_READ(ah, reg);
                        val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
                        val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;

                        REG_WRITE(ah, reg, val|val_orig);
                } else
                        REG_WRITE(ah, reg, val);
        }

        REGWRITE_BUFFER_FLUSH(ah);
}
void ath9k_ani_reset ( struct ath_hw ah,
int  is_scanning 
)

Definition at line 466 of file ath9k_ani.c.

References ath9k_channel::ani, ath_hw::ani_function, AR_PHY_ERR_CCK_TIMING, AR_PHY_ERR_MASK_1, AR_PHY_ERR_MASK_2, AR_PHY_ERR_OFDM_TIMING, ar5416Stats::ast_ani_reset, ATH9K_ANI_CCK_DEF_LEVEL, ATH9K_ANI_MODE, ATH9K_ANI_OFDM_DEF_LEVEL, ath9k_ani_reset_old(), ath9k_ani_restart(), ath9k_hw_set_cck_nil(), ath9k_hw_set_ofdm_nil(), ar5416AniState::cckNoiseImmunityLevel, ath9k_channel::chan, ath9k_channel::channel, ath9k_channel::channelFlags, ath_hw::curchan, DBG, DBG2, DO_ANI, ENABLE_REGWRITE_BUFFER, ar5416AniState::ofdmNoiseImmunityLevel, REG_WRITE, REGWRITE_BUFFER_FLUSH, ath_hw::stats, and use_new_ani().

Referenced by ath9k_hw_startpcureceive().

{
        struct ar5416AniState *aniState = &ah->curchan->ani;
        struct ath9k_channel *chan = ah->curchan;

        if (!DO_ANI(ah))
                return;

        if (!use_new_ani(ah))
                return ath9k_ani_reset_old(ah);

        ah->stats.ast_ani_reset++;

        /* always allow mode (on/off) to be controlled */
        ah->ani_function |= ATH9K_ANI_MODE;

        if (is_scanning) {
                /*
                 * If we're scanning or in AP mode, the defaults (ini)
                 * should be in place. For an AP we assume the historical
                 * levels for this channel are probably outdated so start
                 * from defaults instead.
                 */
                if (aniState->ofdmNoiseImmunityLevel !=
                    ATH9K_ANI_OFDM_DEF_LEVEL ||
                    aniState->cckNoiseImmunityLevel !=
                    ATH9K_ANI_CCK_DEF_LEVEL) {
                        DBG("ath9k: "
                                "Restore defaults: chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
                                chan->channel,
                                chan->channelFlags,
                                is_scanning,
                                aniState->ofdmNoiseImmunityLevel,
                                aniState->cckNoiseImmunityLevel);

                        ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
                        ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
                }
        } else {
                /*
                 * restore historical levels for this channel
                 */
                DBG2("ath9k: "
                        "Restore history: chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
                        chan->channel,
                        chan->channelFlags,
                        is_scanning,
                        aniState->ofdmNoiseImmunityLevel,
                        aniState->cckNoiseImmunityLevel);

                        ath9k_hw_set_ofdm_nil(ah,
                                              aniState->ofdmNoiseImmunityLevel);
                        ath9k_hw_set_cck_nil(ah,
                                             aniState->cckNoiseImmunityLevel);
        }

        /*
         * enable phy counters if hw supports or if not, enable phy
         * interrupts (so we can count each one)
         */
        ath9k_ani_restart(ah);

        ENABLE_REGWRITE_BUFFER(ah);

        REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
        REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);

        REGWRITE_BUFFER_FLUSH(ah);
}
void ath9k_hw_proc_mib_event ( struct ath_hw ah)
void ath9k_hw_ani_monitor ( struct ath_hw ah,
struct ath9k_channel chan 
)

Variable Documentation

Definition at line 28 of file ath9k_ar9002_hw.c.

Referenced by ar5008_hw_attach_phy_ops(), and use_new_ani().