iPXE
forcedeth.c
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00001 /*
00002  *    forcedeth.c -- Driver for NVIDIA nForce media access controllers for iPXE
00003  *    Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
00004  *
00005  *    This program is free software; you can redistribute it and/or
00006  *    modify it under the terms of the GNU General Public License as
00007  *    published by the Free Software Foundation; either version 2 of the
00008  *    License, or any later version.
00009  *
00010  *    This program is distributed in the hope that it will be useful, but
00011  *    WITHOUT ANY WARRANTY; without even the implied warranty of
00012  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013  *    General Public License for more details.
00014  *
00015  *    You should have received a copy of the GNU General Public License
00016  *    along with this program; if not, write to the Free Software
00017  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00018  *    02110-1301, USA.
00019  *
00020  * Portions of this code are taken from the Linux forcedeth driver that was
00021  * based on a cleanroom reimplementation which was based on reverse engineered
00022  * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
00023  * Copyright (C) 2003,4,5 Manfred Spraul
00024  * Copyright (C) 2004 Andrew de Quincey (wol support)
00025  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
00026  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
00027  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
00028  *
00029  * The probe, remove, open and close functions, along with the functions they
00030  * call, are direct copies of the above mentioned driver, modified where
00031  * necessary to make them work for iPXE.
00032  *
00033  * The poll and transmit functions were completely rewritten to make use of
00034  * the iPXE API. This process was aided by constant referencing of the above
00035  * mentioned Linux driver. This driver would not have been possible without this
00036  * prior work.
00037  *
00038  */
00039 
00040 FILE_LICENCE ( GPL2_OR_LATER );
00041 
00042 #include <stdint.h>
00043 #include <stdio.h>
00044 #include <stdlib.h>
00045 #include <string.h>
00046 #include <unistd.h>
00047 #include <assert.h>
00048 #include <byteswap.h>
00049 #include <errno.h>
00050 #include <ipxe/ethernet.h>
00051 #include <ipxe/if_ether.h>
00052 #include <ipxe/io.h>
00053 #include <ipxe/iobuf.h>
00054 #include <ipxe/malloc.h>
00055 #include <ipxe/netdevice.h>
00056 #include <ipxe/crypto.h>
00057 #include <ipxe/pci.h>
00058 #include <ipxe/timer.h>
00059 #include <mii.h>
00060 #include "forcedeth.h"
00061 
00062 static inline void pci_push ( void *ioaddr )
00063 {
00064         /* force out pending posted writes */
00065         wmb();
00066         readl ( ioaddr );
00067 }
00068 
00069 static int
00070 reg_delay ( struct forcedeth_private *priv, int offset, u32 mask,
00071             u32 target, int delay, int delaymax, const char *msg )
00072 {
00073         void *ioaddr = priv->mmio_addr;
00074 
00075         pci_push ( ioaddr );
00076         do {
00077                 udelay ( delay );
00078                 delaymax -= delay;
00079                 if ( delaymax < 0 ) {
00080                         if ( msg )
00081                                 DBG ( "%s\n", msg );
00082                         return 1;
00083                 }
00084         } while ( ( readl ( ioaddr + offset ) & mask ) != target );
00085 
00086         return 0;
00087 }
00088 
00089 /* read/write a register on the PHY */
00090 static int
00091 mii_rw ( struct forcedeth_private *priv, int addr, int miireg, int value )
00092 {
00093         void *ioaddr = priv->mmio_addr;
00094         u32 reg;
00095         int retval;
00096 
00097         writel ( NVREG_MIISTAT_MASK_RW, ioaddr + NvRegMIIStatus );
00098 
00099         reg = readl ( ioaddr + NvRegMIIControl );
00100         if ( reg & NVREG_MIICTL_INUSE ) {
00101                 writel ( NVREG_MIICTL_INUSE, ioaddr + NvRegMIIControl );
00102                 udelay ( NV_MIIBUSY_DELAY );
00103         }
00104 
00105         reg = ( addr << NVREG_MIICTL_ADDRSHIFT ) | miireg;
00106         if ( value != MII_READ ) {
00107                 writel ( value, ioaddr + NvRegMIIData );
00108                 reg |= NVREG_MIICTL_WRITE;
00109         }
00110         writel ( reg, ioaddr + NvRegMIIControl );
00111 
00112         if ( reg_delay ( priv, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
00113                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL ) ) {
00114                 DBG ( "mii_rw of reg %d at PHY %d timed out.\n",
00115                         miireg, addr );
00116                 retval = -1;
00117         } else if ( value != MII_READ ) {
00118                 /* it was a write operation - fewer failures are detectable */
00119                 DBG ( "mii_rw wrote 0x%x to reg %d at PHY %d\n",
00120                         value, miireg, addr );
00121                 retval = 0;
00122         } else if ( readl ( ioaddr + NvRegMIIStatus ) & NVREG_MIISTAT_ERROR ) {
00123                 DBG ( "mii_rw of reg %d at PHY %d failed.\n",
00124                         miireg, addr );
00125                 retval = -1;
00126         } else {
00127                 retval = readl ( ioaddr + NvRegMIIData );
00128                 DBG ( "mii_rw read from reg %d at PHY %d: 0x%x.\n",
00129                         miireg, addr, retval );
00130         }
00131 
00132         return retval;
00133 }
00134 
00135 static void
00136 nv_txrx_gate ( struct forcedeth_private *priv, int gate )
00137 {
00138         void *ioaddr = priv->mmio_addr;
00139         u32 powerstate;
00140 
00141         if ( ! priv->mac_in_use &&
00142              ( priv->driver_data & DEV_HAS_POWER_CNTRL ) ) {
00143                 powerstate = readl ( ioaddr + NvRegPowerState2 );
00144                 if ( gate )
00145                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
00146                 else
00147                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
00148                 writel ( powerstate, ioaddr + NvRegPowerState2 );
00149         }
00150 }
00151 
00152 static void
00153 nv_mac_reset ( struct forcedeth_private * priv )
00154 {
00155         void *ioaddr = priv->mmio_addr;
00156         u32 temp1, temp2, temp3;
00157 
00158         writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | NVREG_TXRXCTL_DESC_1,
00159                  ioaddr + NvRegTxRxControl );
00160         pci_push ( ioaddr );
00161 
00162         /* save registers since they will be cleared on reset */
00163         temp1 = readl ( ioaddr + NvRegMacAddrA );
00164         temp2 = readl ( ioaddr + NvRegMacAddrB );
00165         temp3 = readl ( ioaddr + NvRegTransmitPoll );
00166 
00167         writel ( NVREG_MAC_RESET_ASSERT, ioaddr + NvRegMacReset );
00168         pci_push ( ioaddr );
00169         udelay ( NV_MAC_RESET_DELAY );
00170         writel ( 0, ioaddr + NvRegMacReset );
00171         pci_push ( ioaddr );
00172         udelay ( NV_MAC_RESET_DELAY );
00173 
00174         /* restore saved registers */
00175         writel ( temp1, ioaddr + NvRegMacAddrA );
00176         writel ( temp2, ioaddr + NvRegMacAddrB );
00177         writel ( temp3, ioaddr + NvRegTransmitPoll );
00178 
00179         writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_DESC_1,
00180                  ioaddr + NvRegTxRxControl );
00181         pci_push ( ioaddr );
00182 }
00183 
00184 static void
00185 nv_init_tx_ring ( struct forcedeth_private *priv )
00186 {
00187         int i;
00188 
00189         for ( i = 0; i < TX_RING_SIZE; i++ ) {
00190                 priv->tx_ring[i].flaglen = 0;
00191                 priv->tx_ring[i].buf = 0;
00192                 priv->tx_iobuf[i] = NULL;
00193         }
00194 
00195         priv->tx_fill_ctr = 0;
00196         priv->tx_curr = 0;
00197         priv->tx_tail = 0;
00198 }
00199 
00200 /**
00201  * nv_alloc_rx - Allocates iobufs for every Rx descriptor
00202  * that doesn't have one and isn't in use by the hardware
00203  *
00204  * @v priv      Driver private structure
00205  */
00206 static void
00207 nv_alloc_rx ( struct forcedeth_private *priv )
00208 {
00209         struct ring_desc *rx_curr_desc;
00210         int i;
00211         u32 status;
00212 
00213         DBGP ( "nv_alloc_rx\n" );
00214 
00215         for ( i = 0; i < RX_RING_SIZE; i++ ) {
00216                 rx_curr_desc = priv->rx_ring + i;
00217                 status = le32_to_cpu ( rx_curr_desc->flaglen );
00218 
00219                 /* Don't touch the descriptors owned by the hardware */
00220                 if ( status & NV_RX_AVAIL )
00221                         continue;
00222 
00223                 /* Descriptors with iobufs still need to be processed */
00224                 if ( priv->rx_iobuf[i] != NULL )
00225                         continue;
00226 
00227                 /* If alloc_iob fails, try again later (next poll) */
00228                 if ( ! ( priv->rx_iobuf[i] = alloc_iob ( RX_BUF_SZ ) ) ) {
00229                         DBG ( "Refill rx_ring failed, size %d\n", RX_BUF_SZ );
00230                         break;
00231                 }
00232 
00233                 rx_curr_desc->buf =
00234                         cpu_to_le32 ( virt_to_bus ( priv->rx_iobuf[i]->data ) );
00235                 wmb();
00236                 rx_curr_desc->flaglen =
00237                         cpu_to_le32 ( RX_BUF_SZ | NV_RX_AVAIL );
00238         }
00239 }
00240 
00241 static void
00242 nv_init_rx_ring ( struct forcedeth_private *priv )
00243 {
00244         int i;
00245 
00246         for ( i = 0; i < RX_RING_SIZE; i++ ) {
00247                 priv->rx_ring[i].flaglen = 0;
00248                 priv->rx_ring[i].buf = 0;
00249                 priv->rx_iobuf[i] = NULL;
00250         }
00251 
00252         priv->rx_curr = 0;
00253 }
00254 
00255 /**
00256  * nv_init_rings - Allocate and intialize descriptor rings
00257  *
00258  * @v priv      Driver private structure
00259  *
00260  * @ret rc      Return status code
00261  **/
00262 static int
00263 nv_init_rings ( struct forcedeth_private *priv )
00264 {
00265         void *ioaddr = priv->mmio_addr;
00266         int rc = -ENOMEM;
00267 
00268         /* Allocate ring for both TX and RX */
00269         priv->rx_ring =
00270                 malloc_dma ( sizeof(struct ring_desc) * RXTX_RING_SIZE, 32 );
00271         if ( ! priv->rx_ring )
00272                 goto err_malloc;
00273         priv->tx_ring = &priv->rx_ring[RX_RING_SIZE];
00274 
00275         /* Initialize rings */
00276         nv_init_tx_ring ( priv );
00277         nv_init_rx_ring ( priv );
00278 
00279         /* Allocate iobufs for RX */
00280         nv_alloc_rx ( priv );
00281 
00282         /* Give hw rings */
00283         writel ( cpu_to_le32 ( virt_to_bus ( priv->rx_ring ) ),
00284                  ioaddr + NvRegRxRingPhysAddr );
00285         writel ( cpu_to_le32 ( virt_to_bus ( priv->tx_ring ) ),
00286                  ioaddr + NvRegTxRingPhysAddr );
00287 
00288         DBG ( "RX ring at phys addr: %#08lx\n",
00289                 virt_to_bus ( priv->rx_ring ) );
00290         DBG ( "TX ring at phys addr: %#08lx\n",
00291                 virt_to_bus ( priv->tx_ring ) );
00292 
00293         writel ( ( ( RX_RING_SIZE - 1 ) << NVREG_RINGSZ_RXSHIFT ) +
00294                  ( ( TX_RING_SIZE - 1 ) << NVREG_RINGSZ_TXSHIFT ),
00295                  ioaddr + NvRegRingSizes );
00296 
00297         return 0;
00298 
00299 err_malloc:
00300         DBG ( "Could not allocate descriptor rings\n");
00301         return rc;
00302 }
00303 
00304 static void
00305 nv_free_rxtx_resources ( struct forcedeth_private *priv )
00306 {
00307         int i;
00308 
00309         DBGP ( "nv_free_rxtx_resources\n" );
00310 
00311         free_dma ( priv->rx_ring, sizeof(struct ring_desc) * RXTX_RING_SIZE );
00312 
00313         for ( i = 0; i < RX_RING_SIZE; i++ ) {
00314                 free_iob ( priv->rx_iobuf[i] );
00315                 priv->rx_iobuf[i] = NULL;
00316         }
00317 }
00318 
00319 static void
00320 nv_txrx_reset ( struct forcedeth_private *priv )
00321 {
00322         void *ioaddr = priv->mmio_addr;
00323 
00324         writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | NVREG_TXRXCTL_DESC_1,
00325                  ioaddr + NvRegTxRxControl );
00326         pci_push ( ioaddr );
00327         udelay ( NV_TXRX_RESET_DELAY );
00328         writel ( NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_DESC_1,
00329                  ioaddr + NvRegTxRxControl );
00330         pci_push ( ioaddr );
00331 }
00332 
00333 static void
00334 nv_disable_hw_interrupts ( struct forcedeth_private *priv )
00335 {
00336         void *ioaddr = priv->mmio_addr;
00337 
00338         writel ( 0, ioaddr + NvRegIrqMask );
00339         pci_push ( ioaddr );
00340 }
00341 
00342 static void
00343 nv_enable_hw_interrupts ( struct forcedeth_private *priv )
00344 {
00345         void *ioaddr = priv->mmio_addr;
00346 
00347         writel ( NVREG_IRQMASK_THROUGHPUT, ioaddr + NvRegIrqMask );
00348 }
00349 
00350 static void
00351 nv_start_rx ( struct forcedeth_private *priv )
00352 {
00353         void *ioaddr = priv->mmio_addr;
00354         u32 rx_ctrl = readl ( ioaddr + NvRegReceiverControl );
00355 
00356         DBGP ( "nv_start_rx\n" );
00357         /* Already running? Stop it. */
00358         if ( ( readl ( ioaddr + NvRegReceiverControl ) & NVREG_RCVCTL_START ) && !priv->mac_in_use ) {
00359                 rx_ctrl &= ~NVREG_RCVCTL_START;
00360                 writel ( rx_ctrl, ioaddr + NvRegReceiverControl );
00361                 pci_push ( ioaddr );
00362         }
00363         writel ( priv->linkspeed, ioaddr + NvRegLinkSpeed );
00364         pci_push ( ioaddr );
00365         rx_ctrl |= NVREG_RCVCTL_START;
00366         if ( priv->mac_in_use )
00367                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
00368         writel ( rx_ctrl, ioaddr + NvRegReceiverControl );
00369         DBG ( "nv_start_rx to duplex %d, speed 0x%08x.\n",
00370                 priv->duplex, priv->linkspeed);
00371         pci_push ( ioaddr );
00372 }
00373 
00374 static void
00375 nv_stop_rx ( struct forcedeth_private *priv )
00376 {
00377         void *ioaddr = priv->mmio_addr;
00378         u32 rx_ctrl = readl ( ioaddr + NvRegReceiverControl );
00379 
00380         DBGP ( "nv_stop_rx\n" );
00381         if ( ! priv->mac_in_use )
00382                 rx_ctrl &= ~NVREG_RCVCTL_START;
00383         else
00384                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
00385         writel ( rx_ctrl, ioaddr + NvRegReceiverControl );
00386         reg_delay ( priv, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
00387                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
00388                         "nv_stop_rx: ReceiverStatus remained busy");
00389 
00390         udelay ( NV_RXSTOP_DELAY2 );
00391         if ( ! priv->mac_in_use )
00392                 writel ( 0, priv + NvRegLinkSpeed );
00393 }
00394 
00395 static void
00396 nv_start_tx ( struct forcedeth_private *priv )
00397 {
00398         void *ioaddr = priv->mmio_addr;
00399         u32 tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
00400 
00401         DBGP ( "nv_start_tx\n" );
00402         tx_ctrl |= NVREG_XMITCTL_START;
00403         if ( priv->mac_in_use )
00404                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
00405         writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
00406         pci_push ( ioaddr );
00407 }
00408 
00409 static void
00410 nv_stop_tx ( struct forcedeth_private *priv )
00411 {
00412         void *ioaddr = priv->mmio_addr;
00413         u32 tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
00414 
00415         DBGP ( "nv_stop_tx");
00416 
00417         if ( ! priv->mac_in_use )
00418                 tx_ctrl &= ~NVREG_XMITCTL_START;
00419         else
00420                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
00421         writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
00422         reg_delay ( priv, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
00423                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
00424                         "nv_stop_tx: TransmitterStatus remained busy");
00425 
00426         udelay ( NV_TXSTOP_DELAY2 );
00427         if ( ! priv->mac_in_use )
00428                 writel( readl ( ioaddr + NvRegTransmitPoll) &
00429                                 NVREG_TRANSMITPOLL_MAC_ADDR_REV,
00430                         ioaddr + NvRegTransmitPoll);
00431 }
00432 
00433 
00434 static void
00435 nv_update_pause ( struct forcedeth_private *priv, u32 pause_flags )
00436 {
00437         void *ioaddr = priv->mmio_addr;
00438 
00439         priv->pause_flags &= ~ ( NV_PAUSEFRAME_TX_ENABLE |
00440                                  NV_PAUSEFRAME_RX_ENABLE );
00441 
00442         if ( priv->pause_flags & NV_PAUSEFRAME_RX_CAPABLE ) {
00443                 u32 pff = readl ( ioaddr + NvRegPacketFilterFlags ) & ~NVREG_PFF_PAUSE_RX;
00444                 if ( pause_flags & NV_PAUSEFRAME_RX_ENABLE ) {
00445                         writel ( pff | NVREG_PFF_PAUSE_RX, ioaddr + NvRegPacketFilterFlags );
00446                         priv->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
00447                 } else {
00448                         writel ( pff, ioaddr + NvRegPacketFilterFlags );
00449                 }
00450         }
00451         if ( priv->pause_flags & NV_PAUSEFRAME_TX_CAPABLE ) {
00452                 u32 regmisc = readl ( ioaddr + NvRegMisc1 ) & ~NVREG_MISC1_PAUSE_TX;
00453                 if ( pause_flags & NV_PAUSEFRAME_TX_ENABLE ) {
00454                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
00455                         if ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V2 )
00456                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
00457                         if ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V3 ) {
00458                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
00459                                 /* limit the number of tx pause frames to a default of 8 */
00460                                 writel ( readl ( ioaddr + NvRegTxPauseFrameLimit ) |
00461                                                 NVREG_TX_PAUSEFRAMELIMIT_ENABLE,
00462                                          ioaddr + NvRegTxPauseFrameLimit );
00463                         }
00464                         writel ( pause_enable, ioaddr + NvRegTxPauseFrame );
00465                         writel ( regmisc | NVREG_MISC1_PAUSE_TX, ioaddr + NvRegMisc1 );
00466                         priv->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
00467                 } else {
00468                         writel ( NVREG_TX_PAUSEFRAME_DISABLE, ioaddr + NvRegTxPauseFrame );
00469                         writel ( regmisc, ioaddr + NvRegMisc1 );
00470                 }
00471         }
00472 }
00473 
00474 static int
00475 nv_update_linkspeed ( struct forcedeth_private *priv )
00476 {
00477         void *ioaddr = priv->mmio_addr;
00478         int adv = 0;
00479         int lpa = 0;
00480         int adv_lpa, adv_pause, lpa_pause;
00481         u32 newls = priv->linkspeed;
00482         int newdup = priv->duplex;
00483         int mii_status;
00484         int retval = 0;
00485         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
00486         u32 txrxFlags = 0;
00487         u32 phy_exp;
00488 
00489         /* BMSR_LSTATUS is latched, read it twice:
00490          * we want the current value.
00491          */
00492         mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
00493         mii_status = mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
00494 
00495         if ( ! ( mii_status & BMSR_LSTATUS ) ) {
00496                 DBG ( "No link detected by phy - falling back to 10HD.\n" );
00497                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
00498                 newdup = 0;
00499                 retval = 0;
00500                 goto set_speed;
00501         }
00502 
00503         /* check auto negotiation is complete */
00504         if ( ! ( mii_status & BMSR_ANEGCOMPLETE ) ) {
00505                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
00506                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
00507                 newdup = 0;
00508                 retval = 0;
00509                 DBG ( "autoneg not completed - falling back to 10HD.\n" );
00510                 goto set_speed;
00511         }
00512 
00513         adv = mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, MII_READ );
00514         lpa = mii_rw ( priv, priv->phyaddr, MII_LPA, MII_READ );
00515         DBG ( "nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", adv, lpa );
00516 
00517         retval = 1;
00518         if ( priv->gigabit == PHY_GIGABIT ) {
00519                 control_1000 = mii_rw ( priv, priv->phyaddr, MII_CTRL1000, MII_READ);
00520                 status_1000 = mii_rw ( priv, priv->phyaddr, MII_STAT1000, MII_READ);
00521 
00522                 if ( ( control_1000 & ADVERTISE_1000FULL ) &&
00523                         ( status_1000 & LPA_1000FULL ) ) {
00524                         DBG ( "nv_update_linkspeed: GBit ethernet detected.\n" );
00525                         newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_1000;
00526                         newdup = 1;
00527                         goto set_speed;
00528                 }
00529         }
00530 
00531         /* FIXME: handle parallel detection properly */
00532         adv_lpa = lpa & adv;
00533         if ( adv_lpa & LPA_100FULL ) {
00534                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
00535                 newdup = 1;
00536         } else if ( adv_lpa & LPA_100HALF ) {
00537                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_100;
00538                 newdup = 0;
00539         } else if ( adv_lpa & LPA_10FULL ) {
00540                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
00541                 newdup = 1;
00542         } else if ( adv_lpa & LPA_10HALF ) {
00543                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
00544                 newdup = 0;
00545         } else {
00546                 DBG ( "bad ability %04x - falling back to 10HD.\n", adv_lpa);
00547                 newls = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
00548                 newdup = 0;
00549         }
00550 
00551 set_speed:
00552         if ( priv->duplex == newdup && priv->linkspeed == newls )
00553                 return retval;
00554 
00555         DBG ( "changing link setting from %d/%d to %d/%d.\n",
00556                 priv->linkspeed, priv->duplex, newls, newdup);
00557 
00558         priv->duplex = newdup;
00559         priv->linkspeed = newls;
00560 
00561         /* The transmitter and receiver must be restarted for safe update */
00562         if ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_START ) {
00563                 txrxFlags |= NV_RESTART_TX;
00564                 nv_stop_tx ( priv );
00565         }
00566         if ( readl ( ioaddr + NvRegReceiverControl ) & NVREG_RCVCTL_START) {
00567                 txrxFlags |= NV_RESTART_RX;
00568                 nv_stop_rx ( priv );
00569         }
00570 
00571         if ( priv->gigabit == PHY_GIGABIT ) {
00572                 phyreg = readl ( ioaddr + NvRegSlotTime );
00573                 phyreg &= ~(0x3FF00);
00574                 if ( ( ( priv->linkspeed & 0xFFF ) == NVREG_LINKSPEED_10 ) ||
00575                      ( ( priv->linkspeed & 0xFFF ) == NVREG_LINKSPEED_100) )
00576                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
00577                 else if ( ( priv->linkspeed & 0xFFF ) == NVREG_LINKSPEED_1000 )
00578                         phyreg |= NVREG_SLOTTIME_1000_FULL;
00579                 writel( phyreg, priv + NvRegSlotTime );
00580         }
00581 
00582         phyreg = readl ( ioaddr + NvRegPhyInterface );
00583         phyreg &= ~( PHY_HALF | PHY_100 | PHY_1000 );
00584         if ( priv->duplex == 0 )
00585                 phyreg |= PHY_HALF;
00586         if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_100 )
00587                 phyreg |= PHY_100;
00588         else if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_1000 )
00589                 phyreg |= PHY_1000;
00590         writel ( phyreg, ioaddr + NvRegPhyInterface );
00591 
00592         phy_exp = mii_rw ( priv, priv->phyaddr, MII_EXPANSION, MII_READ ) & EXPANSION_NWAY; /* autoneg capable */
00593         if ( phyreg & PHY_RGMII ) {
00594                 if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_1000 ) {
00595                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
00596                 } else {
00597                         if ( !phy_exp && !priv->duplex && ( priv->driver_data & DEV_HAS_COLLISION_FIX ) ) {
00598                                 if ( ( priv->linkspeed & NVREG_LINKSPEED_MASK ) == NVREG_LINKSPEED_10 )
00599                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
00600                                 else
00601                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
00602                         } else {
00603                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
00604                         }
00605                 }
00606         } else {
00607                 if ( !phy_exp && !priv->duplex && ( priv->driver_data & DEV_HAS_COLLISION_FIX ) )
00608                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
00609                 else
00610                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
00611         }
00612         writel ( txreg, ioaddr + NvRegTxDeferral );
00613 
00614         txreg = NVREG_TX_WM_DESC1_DEFAULT;
00615         writel ( txreg, ioaddr + NvRegTxWatermark );
00616 
00617         writel ( NVREG_MISC1_FORCE | ( priv->duplex ? 0 : NVREG_MISC1_HD ), ioaddr + NvRegMisc1 );
00618         pci_push ( ioaddr );
00619         writel ( priv->linkspeed, priv + NvRegLinkSpeed);
00620         pci_push ( ioaddr );
00621 
00622         pause_flags = 0;
00623         /* setup pause frame */
00624         if ( priv->duplex != 0 ) {
00625                 if ( priv->pause_flags & NV_PAUSEFRAME_AUTONEG ) {
00626                         adv_pause = adv & ( ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM );
00627                         lpa_pause = lpa & ( LPA_PAUSE_CAP | LPA_PAUSE_ASYM );
00628 
00629                         switch ( adv_pause ) {
00630                         case ADVERTISE_PAUSE_CAP:
00631                                 if ( lpa_pause & LPA_PAUSE_CAP ) {
00632                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
00633                                         if ( priv->pause_flags & NV_PAUSEFRAME_TX_REQ )
00634                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
00635                                 }
00636                                 break;
00637                         case ADVERTISE_PAUSE_ASYM:
00638                                 if ( lpa_pause == ( LPA_PAUSE_CAP | LPA_PAUSE_ASYM ) )
00639                                 {
00640                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
00641                                 }
00642                                 break;
00643                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
00644                                 if ( lpa_pause & LPA_PAUSE_CAP )
00645                                 {
00646                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
00647                                         if ( priv->pause_flags & NV_PAUSEFRAME_TX_REQ )
00648                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
00649                                 }
00650                                 if ( lpa_pause == LPA_PAUSE_ASYM )
00651                                 {
00652                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
00653                                 }
00654                                 break;
00655                         }
00656                 } else {
00657                         pause_flags = priv->pause_flags;
00658                 }
00659         }
00660         nv_update_pause ( priv, pause_flags );
00661 
00662         if ( txrxFlags & NV_RESTART_TX )
00663                 nv_start_tx ( priv );
00664         if ( txrxFlags & NV_RESTART_RX )
00665                 nv_start_rx ( priv );
00666 
00667         return retval;
00668 }
00669 
00670 
00671 /**
00672  * open - Called when a network interface is made active
00673  *
00674  * @v netdev    Network device
00675  * @ret rc      Return status code, 0 on success, negative value on failure
00676  **/
00677 static int
00678 forcedeth_open ( struct net_device *netdev )
00679 {
00680         struct forcedeth_private *priv = netdev_priv ( netdev );
00681         void *ioaddr = priv->mmio_addr;
00682         int i;
00683         int rc;
00684         u32 low;
00685 
00686         DBGP ( "forcedeth_open\n" );
00687 
00688         /* Power up phy */
00689         mii_rw ( priv, priv->phyaddr, MII_BMCR,
00690                  mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ ) & ~BMCR_PDOWN );
00691 
00692         nv_txrx_gate ( priv, 0 );
00693 
00694         /* Erase previous misconfiguration */
00695         if ( priv->driver_data & DEV_HAS_POWER_CNTRL )
00696                 nv_mac_reset ( priv );
00697 
00698         /* Clear multicast masks and addresses, enter promiscuous mode */
00699         writel ( 0, ioaddr + NvRegMulticastAddrA );
00700         writel ( 0, ioaddr + NvRegMulticastAddrB );
00701         writel ( NVREG_MCASTMASKA_NONE, ioaddr + NvRegMulticastMaskA );
00702         writel ( NVREG_MCASTMASKB_NONE, ioaddr + NvRegMulticastMaskB );
00703         writel ( NVREG_PFF_PROMISC, ioaddr + NvRegPacketFilterFlags );
00704 
00705         writel ( 0, ioaddr + NvRegTransmitterControl );
00706         writel ( 0, ioaddr + NvRegReceiverControl );
00707 
00708         writel ( 0, ioaddr + NvRegAdapterControl );
00709 
00710         writel ( 0, ioaddr + NvRegLinkSpeed );
00711         writel ( readl ( ioaddr + NvRegTransmitPoll ) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
00712                  ioaddr + NvRegTransmitPoll );
00713         nv_txrx_reset ( priv );
00714         writel ( 0, ioaddr + NvRegUnknownSetupReg6 );
00715 
00716         /* Initialize descriptor rings */
00717         if ( ( rc = nv_init_rings ( priv ) ) != 0 )
00718                 goto err_init_rings;
00719 
00720         writel ( priv->linkspeed, ioaddr + NvRegLinkSpeed );
00721         writel ( NVREG_TX_WM_DESC1_DEFAULT, ioaddr + NvRegTxWatermark );
00722         writel ( NVREG_TXRXCTL_DESC_1, ioaddr + NvRegTxRxControl );
00723         writel ( 0 , ioaddr + NvRegVlanControl );
00724         pci_push ( ioaddr );
00725         writel ( NVREG_TXRXCTL_BIT1 | NVREG_TXRXCTL_DESC_1,
00726                  ioaddr + NvRegTxRxControl );
00727         reg_delay ( priv, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
00728                     NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
00729                     "open: SetupReg5, Bit 31 remained off\n" );
00730 
00731         writel ( 0, ioaddr + NvRegMIIMask );
00732         writel ( NVREG_IRQSTAT_MASK, ioaddr + NvRegIrqStatus );
00733         writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
00734 
00735         writel ( NVREG_MISC1_FORCE | NVREG_MISC1_HD, ioaddr + NvRegMisc1 );
00736         writel ( readl ( ioaddr + NvRegTransmitterStatus ),
00737                  ioaddr + NvRegTransmitterStatus );
00738         writel ( RX_BUF_SZ, ioaddr + NvRegOffloadConfig );
00739 
00740         writel ( readl ( ioaddr + NvRegReceiverStatus),
00741                  ioaddr + NvRegReceiverStatus );
00742 
00743         /* Set up slot time */
00744         low = ( random() & NVREG_SLOTTIME_MASK );
00745         writel ( low | NVREG_SLOTTIME_DEFAULT, ioaddr + NvRegSlotTime );
00746 
00747         writel ( NVREG_TX_DEFERRAL_DEFAULT , ioaddr + NvRegTxDeferral );
00748         writel ( NVREG_RX_DEFERRAL_DEFAULT , ioaddr + NvRegRxDeferral );
00749 
00750         writel ( NVREG_POLL_DEFAULT_THROUGHPUT, ioaddr + NvRegPollingInterval );
00751 
00752         writel ( NVREG_UNKSETUP6_VAL, ioaddr + NvRegUnknownSetupReg6 );
00753         writel ( ( priv->phyaddr << NVREG_ADAPTCTL_PHYSHIFT ) |
00754                  NVREG_ADAPTCTL_PHYVALID | NVREG_ADAPTCTL_RUNNING,
00755                  ioaddr + NvRegAdapterControl );
00756         writel ( NVREG_MIISPEED_BIT8 | NVREG_MIIDELAY, ioaddr + NvRegMIISpeed );
00757         writel ( NVREG_MII_LINKCHANGE, ioaddr + NvRegMIIMask );
00758 
00759         i = readl ( ioaddr + NvRegPowerState );
00760         if ( ( i & NVREG_POWERSTATE_POWEREDUP ) == 0 )
00761                 writel ( NVREG_POWERSTATE_POWEREDUP | i, ioaddr + NvRegPowerState );
00762 
00763         pci_push ( ioaddr );
00764         udelay ( 10 );
00765         writel ( readl ( ioaddr + NvRegPowerState ) | NVREG_POWERSTATE_VALID,
00766                  ioaddr + NvRegPowerState );
00767 
00768         nv_disable_hw_interrupts ( priv );
00769         writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
00770         writel ( NVREG_IRQSTAT_MASK, ioaddr + NvRegIrqStatus );
00771         pci_push ( ioaddr );
00772 
00773         readl ( ioaddr + NvRegMIIStatus );
00774         writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
00775         priv->linkspeed = 0;
00776         nv_update_linkspeed ( priv );
00777         nv_start_rx ( priv );
00778         nv_start_tx ( priv );
00779 
00780         return 0;
00781 
00782 err_init_rings:
00783         return rc;
00784 }
00785 
00786 /**
00787  * transmit - Transmit a packet
00788  *
00789  * @v netdev    Network device
00790  * @v iobuf     I/O buffer
00791  *
00792  * @ret rc      Returns 0 on success, negative on failure
00793  */
00794 static int
00795 forcedeth_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
00796 {
00797         struct forcedeth_private *priv = netdev_priv ( netdev );
00798         void *ioaddr = priv->mmio_addr;
00799         struct ring_desc *tx_curr_desc;
00800         u32 size = iob_len ( iobuf );
00801 
00802         DBGP ( "forcedeth_transmit\n" );
00803 
00804         /* NOTE: Some NICs have a hw bug that causes them to malfunction
00805          * when there are more than 16 outstanding TXs. Increasing the TX
00806          * ring size might trigger this bug */
00807         if ( priv->tx_fill_ctr == TX_RING_SIZE ) {
00808                 DBG ( "Tx overflow\n" );
00809                 return -ENOBUFS;
00810         }
00811 
00812         /* Pad small packets to minimum length */
00813         iob_pad ( iobuf, ETH_ZLEN );
00814 
00815         priv->tx_iobuf[priv->tx_curr] = iobuf;
00816 
00817         tx_curr_desc = priv->tx_ring + priv->tx_curr;
00818 
00819         /* Configure current descriptor to transmit packet
00820          * ( NV_TX_VALID sets the ownership bit ) */
00821         tx_curr_desc->buf =
00822                 cpu_to_le32 ( virt_to_bus ( iobuf->data ) );
00823         wmb();
00824         /* Since we don't do fragmentation offloading, we always have
00825          * the last packet bit set */
00826         tx_curr_desc->flaglen =
00827                 cpu_to_le32 ( ( size - 1 ) | NV_TX_VALID | NV_TX_LASTPACKET );
00828 
00829         DBG ( "forcedeth_transmit: flaglen = %#04x\n",
00830                 ( size - 1 ) | NV_TX_VALID | NV_TX_LASTPACKET );
00831         DBG ( "forcedeth_transmit: tx_fill_ctr = %d\n",
00832                 priv->tx_fill_ctr );
00833 
00834         writel ( NVREG_TXRXCTL_KICK | NVREG_TXRXCTL_DESC_1,
00835                  ioaddr + NvRegTxRxControl );
00836         pci_push ( ioaddr );
00837 
00838         /* Point to the next free descriptor */
00839         priv->tx_curr = ( priv->tx_curr + 1 ) % TX_RING_SIZE;
00840 
00841         /* Increment number of descriptors in use */
00842         priv->tx_fill_ctr++;
00843 
00844         return 0;
00845 }
00846 
00847 /**
00848  * nv_process_tx_packets - Checks for successfully sent packets,
00849  * reports them to iPXE with netdev_tx_complete()
00850  *
00851  * @v netdev    Network device
00852  */
00853 static void
00854 nv_process_tx_packets ( struct net_device *netdev )
00855 {
00856         struct forcedeth_private *priv = netdev_priv ( netdev );
00857         struct ring_desc *tx_curr_desc;
00858         u32 flaglen;
00859 
00860         DBGP ( "nv_process_tx_packets\n" );
00861 
00862         while ( priv->tx_tail != priv->tx_curr ) {
00863 
00864                 tx_curr_desc = priv->tx_ring + priv->tx_tail;
00865                 flaglen = le32_to_cpu ( tx_curr_desc->flaglen );
00866                 rmb();
00867 
00868                 /* Skip this descriptor if hardware still owns it */
00869                 if ( flaglen & NV_TX_VALID )
00870                         break;
00871 
00872                 DBG ( "Transmitted packet.\n" );
00873                 DBG ( "priv->tx_fill_ctr= %d\n", priv->tx_fill_ctr );
00874                 DBG ( "priv->tx_tail    = %d\n", priv->tx_tail );
00875                 DBG ( "priv->tx_curr    = %d\n", priv->tx_curr );
00876                 DBG ( "flaglen          = %#04x\n", flaglen );
00877 
00878                 /* This packet is ready for completion */
00879                 netdev_tx_complete ( netdev, priv->tx_iobuf[priv->tx_tail] );
00880 
00881                 /* Clear the descriptor */
00882                 memset ( tx_curr_desc, 0, sizeof(*tx_curr_desc) );
00883 
00884                 /* Reduce the number of tx descriptors in use */
00885                 priv->tx_fill_ctr--;
00886 
00887                 /* Go to next available descriptor */
00888                 priv->tx_tail = ( priv->tx_tail + 1 ) % TX_RING_SIZE;
00889         }
00890 }
00891 
00892 /**
00893  * nv_process_rx_packets - Checks for received packets, reports them
00894  * to iPXE with netdev_rx() or netdev_rx_err() if there was an error receiving
00895  * the packet
00896  *
00897  * @v netdev    Network device
00898  */
00899 static void
00900 nv_process_rx_packets ( struct net_device *netdev )
00901 {
00902         struct forcedeth_private *priv = netdev_priv ( netdev );
00903         struct io_buffer *curr_iob;
00904         struct ring_desc *rx_curr_desc;
00905         u32 flags, len;
00906         int i;
00907 
00908         DBGP ( "nv_process_rx_packets\n" );
00909 
00910         for ( i = 0; i < RX_RING_SIZE; i++ ) {
00911 
00912                 rx_curr_desc = priv->rx_ring + priv->rx_curr;
00913                 flags = le32_to_cpu ( rx_curr_desc->flaglen );
00914                 rmb();
00915 
00916                 /* Skip this descriptor if hardware still owns it */
00917                 if ( flags & NV_RX_AVAIL )
00918                         break;
00919 
00920                 /* We own the descriptor, but it has not been refilled yet */
00921                 curr_iob = priv->rx_iobuf[priv->rx_curr];
00922                 DBG ( "%p %p\n", curr_iob, priv->rx_iobuf[priv->rx_curr] );
00923                 if ( curr_iob == NULL )
00924                         break;
00925 
00926                 DBG ( "Received packet.\n" );
00927                 DBG ( "priv->rx_curr    = %d\n", priv->rx_curr );
00928                 DBG ( "flags            = %#04x\n", flags );
00929 
00930                 /* Check for errors */
00931                 if ( ( flags & NV_RX_DESCRIPTORVALID ) &&
00932                      ( flags & NV_RX_ERROR ) ) {
00933                                 netdev_rx_err ( netdev, curr_iob, -EINVAL );
00934                                 DBG ( " Corrupted packet received!\n" );
00935                 } else {
00936                         len = flags & LEN_MASK_V1;
00937 
00938                         iob_put ( curr_iob, len );
00939                         netdev_rx ( netdev, curr_iob );
00940                 }
00941 
00942                 /* Invalidate iobuf */
00943                 priv->rx_iobuf[priv->rx_curr] = NULL;
00944 
00945                 /* Invalidate descriptor */
00946                 memset ( rx_curr_desc, 0, sizeof(*rx_curr_desc) );
00947 
00948                 /* Point to the next free descriptor */
00949                 priv->rx_curr = ( priv->rx_curr + 1 ) % RX_RING_SIZE;
00950         }
00951 
00952         nv_alloc_rx ( priv );
00953 }
00954 
00955 /**
00956  * check_link - Check for link status change
00957  *
00958  * @v netdev    Network device
00959  */
00960 static void
00961 forcedeth_link_status ( struct net_device *netdev )
00962 {
00963         struct forcedeth_private *priv = netdev_priv ( netdev );
00964         void *ioaddr = priv->mmio_addr;
00965 
00966         /* Clear the MII link change status by reading the MIIStatus register */
00967         readl ( ioaddr + NvRegMIIStatus );
00968         writel ( NVREG_MIISTAT_LINKCHANGE, ioaddr + NvRegMIIStatus );
00969 
00970         if ( nv_update_linkspeed ( priv ) == 1 )
00971                 netdev_link_up ( netdev );
00972         else
00973                 netdev_link_down ( netdev );
00974 }
00975 
00976 /**
00977  * poll - Poll for received packets
00978  *
00979  * @v netdev    Network device
00980  */
00981 static void
00982 forcedeth_poll ( struct net_device *netdev )
00983 {
00984         struct forcedeth_private *priv = netdev_priv ( netdev );
00985         void *ioaddr = priv->mmio_addr;
00986         u32 status;
00987 
00988         DBGP ( "forcedeth_poll\n" );
00989 
00990         status = readl ( ioaddr + NvRegIrqStatus ) & NVREG_IRQSTAT_MASK;
00991 
00992         /* Return when no interrupts have been triggered */
00993         if ( ! status )
00994                 return;
00995 
00996         /* Clear interrupts */
00997         writel ( NVREG_IRQSTAT_MASK, ioaddr + NvRegIrqStatus );
00998 
00999         DBG ( "forcedeth_poll: status = %#04x\n", status );
01000 
01001         /* Link change interrupt occurred. Call always if link is down,
01002          * to give auto-neg a chance to finish */
01003         if ( ( status & NVREG_IRQ_LINK ) || ! ( netdev_link_ok ( netdev ) ) )
01004                 forcedeth_link_status ( netdev );
01005 
01006         /* Process transmitted packets */
01007         nv_process_tx_packets ( netdev );
01008 
01009         /* Process received packets */
01010         nv_process_rx_packets ( netdev );
01011 }
01012 
01013 /**
01014  * close - Disable network interface
01015  *
01016  * @v netdev    network interface device structure
01017  **/
01018 static void
01019 forcedeth_close ( struct net_device *netdev )
01020 {
01021         struct forcedeth_private *priv = netdev_priv ( netdev );
01022 
01023         DBGP ( "forcedeth_close\n" );
01024 
01025         nv_stop_rx ( priv );
01026         nv_stop_tx ( priv );
01027         nv_txrx_reset ( priv );
01028 
01029         /* Disable interrupts on the nic or we will lock up */
01030         nv_disable_hw_interrupts ( priv );
01031 
01032         nv_free_rxtx_resources ( priv );
01033 
01034         nv_txrx_gate ( priv, 0 );
01035 
01036         /* FIXME: power down nic */
01037 }
01038 
01039 /**
01040  * irq - enable or disable interrupts
01041  *
01042  * @v netdev    network adapter
01043  * @v action    requested interrupt action
01044  **/
01045 static void
01046 forcedeth_irq ( struct net_device *netdev, int action )
01047 {
01048         struct forcedeth_private *priv = netdev_priv ( netdev );
01049 
01050         DBGP ( "forcedeth_irq\n" );
01051 
01052         switch ( action ) {
01053         case 0:
01054                 nv_disable_hw_interrupts ( priv );
01055                 break;
01056         default:
01057                 nv_enable_hw_interrupts ( priv );
01058                 break;
01059         }
01060 }
01061 
01062 static struct net_device_operations forcedeth_operations  = {
01063         .open           = forcedeth_open,
01064         .transmit       = forcedeth_transmit,
01065         .poll           = forcedeth_poll,
01066         .close          = forcedeth_close,
01067         .irq            = forcedeth_irq,
01068 };
01069 
01070 static int
01071 nv_setup_mac_addr ( struct forcedeth_private *priv )
01072 {
01073         struct net_device *dev = priv->netdev;
01074         void *ioaddr = priv->mmio_addr;
01075         u32 orig_mac[2];
01076         u32 txreg;
01077 
01078         orig_mac[0] = readl ( ioaddr + NvRegMacAddrA );
01079         orig_mac[1] = readl ( ioaddr + NvRegMacAddrB );
01080 
01081         txreg = readl ( ioaddr + NvRegTransmitPoll );
01082 
01083         if ( ( priv->driver_data & DEV_HAS_CORRECT_MACADDR ) ||
01084              ( txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV ) ) {
01085                 /* mac address is already in correct order */
01086                 dev->hw_addr[0] = ( orig_mac[0] >> 0 ) & 0xff;
01087                 dev->hw_addr[1] = ( orig_mac[0] >> 8 ) & 0xff;
01088                 dev->hw_addr[2] = ( orig_mac[0] >> 16 ) & 0xff;
01089                 dev->hw_addr[3] = ( orig_mac[0] >> 24 ) & 0xff;
01090                 dev->hw_addr[4] = ( orig_mac[1] >> 0 ) & 0xff;
01091                 dev->hw_addr[5] = ( orig_mac[1] >> 8 ) & 0xff;
01092         } else {
01093                 /* need to reverse mac address to correct order */
01094                 dev->hw_addr[0] = ( orig_mac[1] >> 8 ) & 0xff;
01095                 dev->hw_addr[1] = ( orig_mac[1] >> 0 ) & 0xff;
01096                 dev->hw_addr[2] = ( orig_mac[0] >> 24 ) & 0xff;
01097                 dev->hw_addr[3] = ( orig_mac[0] >> 16 ) & 0xff;
01098                 dev->hw_addr[4] = ( orig_mac[0] >> 8 ) & 0xff;
01099                 dev->hw_addr[5] = ( orig_mac[0] >> 0 ) & 0xff;
01100         }
01101 
01102         if ( ! is_valid_ether_addr ( dev->hw_addr ) )
01103                 return -EADDRNOTAVAIL;
01104 
01105         DBG ( "MAC address is: %s\n", eth_ntoa ( dev->hw_addr ) );
01106 
01107         return 0;
01108 }
01109 
01110 static int
01111 nv_mgmt_acquire_sema ( struct forcedeth_private *priv )
01112 {
01113         void *ioaddr = priv->mmio_addr;
01114         int i;
01115         u32 tx_ctrl, mgmt_sema;
01116 
01117         for ( i = 0; i < 10; i++ ) {
01118                 mgmt_sema = readl ( ioaddr + NvRegTransmitterControl ) &
01119                         NVREG_XMITCTL_MGMT_SEMA_MASK;
01120                 if ( mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE )
01121                         break;
01122                 mdelay ( 500 );
01123         }
01124 
01125         if ( mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE )
01126                 return 0;
01127 
01128         for ( i = 0; i < 2; i++ ) {
01129                 tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
01130                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
01131                 writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
01132 
01133                 /* verify that the semaphore was acquired */
01134                 tx_ctrl = readl ( ioaddr + NvRegTransmitterControl );
01135                 if ( ( ( tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK ) ==
01136                        NVREG_XMITCTL_HOST_SEMA_ACQ ) &&
01137                      ( ( tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK ) ==
01138                        NVREG_XMITCTL_MGMT_SEMA_FREE ) ) {
01139                         priv->mgmt_sema = 1;
01140                         return 1;
01141                 } else {
01142                         udelay ( 50 );
01143                 }
01144         }
01145 
01146         return 0;
01147 }
01148 
01149 static void
01150 nv_mgmt_release_sema ( struct forcedeth_private *priv )
01151 {
01152         void *ioaddr = priv->mmio_addr;
01153         u32 tx_ctrl;
01154 
01155         if ( priv->driver_data & DEV_HAS_MGMT_UNIT ) {
01156                 if ( priv->mgmt_sema ) {
01157                         tx_ctrl = readl (ioaddr + NvRegTransmitterControl );
01158                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
01159                         writel ( tx_ctrl, ioaddr + NvRegTransmitterControl );
01160                 }
01161         }
01162 }
01163 
01164 static int
01165 nv_mgmt_get_version ( struct forcedeth_private *priv )
01166 {
01167         void *ioaddr = priv->mmio_addr;
01168         u32 data_ready = readl ( ioaddr + NvRegTransmitterControl );
01169         u32 data_ready2 = 0;
01170         unsigned long start;
01171         int ready = 0;
01172 
01173         writel ( NVREG_MGMTUNITGETVERSION,
01174                 ioaddr + NvRegMgmtUnitGetVersion );
01175         writel ( data_ready ^ NVREG_XMITCTL_DATA_START,
01176                 ioaddr + NvRegTransmitterControl );
01177         start = currticks();
01178 
01179         while ( currticks() > start + 5 * TICKS_PER_SEC ) {
01180                 data_ready2 = readl ( ioaddr + NvRegTransmitterControl );
01181                 if ( ( data_ready & NVREG_XMITCTL_DATA_READY ) !=
01182                      ( data_ready2 & NVREG_XMITCTL_DATA_READY ) ) {
01183                         ready = 1;
01184                         break;
01185                 }
01186                 mdelay ( 1000 );
01187         }
01188 
01189         if ( ! ready || ( data_ready2 & NVREG_XMITCTL_DATA_ERROR ) )
01190                 return 0;
01191 
01192         priv->mgmt_version =
01193                 readl ( ioaddr + NvRegMgmtUnitVersion ) & NVREG_MGMTUNITVERSION;
01194 
01195         return 1;
01196 }
01197 
01198 
01199 
01200 static int
01201 phy_reset ( struct forcedeth_private *priv, u32 bmcr_setup )
01202 {
01203         u32 miicontrol;
01204         unsigned int tries = 0;
01205 
01206         miicontrol = BMCR_RESET | bmcr_setup;
01207         if ( mii_rw ( priv, priv->phyaddr, MII_BMCR, miicontrol ) ) {
01208                 return -1;
01209         }
01210 
01211         mdelay ( 500 );
01212 
01213         /* must wait till reset is deasserted */
01214         while ( miicontrol & BMCR_RESET ) {
01215                 mdelay ( 10 );
01216                 miicontrol = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
01217                 if ( tries++ > 100 )
01218                         return -1;
01219         }
01220         return 0;
01221 }
01222 
01223 static int
01224 phy_init ( struct forcedeth_private *priv )
01225 {
01226         void *ioaddr = priv->mmio_addr;
01227         u32 phyinterface, phy_reserved, mii_status;
01228         u32 mii_control, mii_control_1000, reg;
01229 
01230         /* phy errata for E3016 phy */
01231         if ( priv->phy_model == PHY_MODEL_MARVELL_E3016 ) {
01232                 reg = mii_rw ( priv, priv->phyaddr, MII_NCONFIG, MII_READ );
01233                 reg &= ~PHY_MARVELL_E3016_INITMASK;
01234                 if ( mii_rw ( priv, priv->phyaddr, MII_NCONFIG, reg ) ) {
01235                         DBG ( "PHY write to errata reg failed.\n" );
01236                         return PHY_ERROR;
01237                 }
01238         }
01239 
01240         if ( priv->phy_oui == PHY_OUI_REALTEK ) {
01241                 if ( priv->phy_model == PHY_MODEL_REALTEK_8211 &&
01242                      priv->phy_rev == PHY_REV_REALTEK_8211B ) {
01243                         if ( mii_rw ( priv, priv->phyaddr,
01244                                 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
01245                                 DBG ( "PHY init failed.\n" );
01246                                 return PHY_ERROR;
01247                         }
01248                         if ( mii_rw ( priv, priv->phyaddr,
01249                                 PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 ) ) {
01250                                 DBG ( "PHY init failed.\n" );
01251                                 return PHY_ERROR;
01252                         }
01253                         if ( mii_rw ( priv, priv->phyaddr,
01254                                 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 ) ) {
01255                                 DBG ( "PHY init failed.\n" );
01256                                 return PHY_ERROR;
01257                         }
01258                         if ( mii_rw ( priv, priv->phyaddr,
01259                                 PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 ) ) {
01260                                 DBG ( "PHY init failed.\n" );
01261                                 return PHY_ERROR;
01262                         }
01263                         if ( mii_rw ( priv, priv->phyaddr,
01264                                 PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 ) ) {
01265                                 DBG ( "PHY init failed.\n" );
01266                                 return PHY_ERROR;
01267                         }
01268                         if ( mii_rw ( priv, priv->phyaddr,
01269                                 PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 ) ) {
01270                                 DBG ( "PHY init failed.\n" );
01271                                 return PHY_ERROR;
01272                         }
01273                         if ( mii_rw ( priv, priv->phyaddr,
01274                                 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
01275                                 DBG ( "PHY init failed.\n" );
01276                                 return PHY_ERROR;
01277                         }
01278                 }
01279 
01280                 if ( priv->phy_model == PHY_MODEL_REALTEK_8211 &&
01281                      priv->phy_rev == PHY_REV_REALTEK_8211C ) {
01282                         u32 powerstate = readl ( ioaddr + NvRegPowerState2 );
01283 
01284                         /* need to perform hw phy reset */
01285                         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
01286                         writel ( powerstate , ioaddr + NvRegPowerState2 );
01287                         mdelay ( 25 );
01288 
01289                         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
01290                         writel ( powerstate , ioaddr + NvRegPowerState2 );
01291                         mdelay ( 25 );
01292 
01293                         reg = mii_rw ( priv, priv->phyaddr,
01294                                 PHY_REALTEK_INIT_REG6, MII_READ );
01295                         reg |= PHY_REALTEK_INIT9;
01296                         if ( mii_rw ( priv, priv->phyaddr,
01297                                 PHY_REALTEK_INIT_REG6, reg ) ) {
01298                                 DBG ( "PHY init failed.\n" );
01299                                 return PHY_ERROR;
01300                         }
01301                         if ( mii_rw ( priv, priv->phyaddr,
01302                                 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10 ) ) {
01303                                 DBG ( "PHY init failed.\n" );
01304                                 return PHY_ERROR;
01305                         }
01306 
01307                         reg = mii_rw ( priv, priv->phyaddr,
01308                                 PHY_REALTEK_INIT_REG7, MII_READ );
01309                         if ( ! ( reg & PHY_REALTEK_INIT11 ) ) {
01310                                 reg |= PHY_REALTEK_INIT11;
01311                                 if ( mii_rw ( priv, priv->phyaddr,
01312                                         PHY_REALTEK_INIT_REG7, reg ) ) {
01313                                         DBG ( "PHY init failed.\n" );
01314                                         return PHY_ERROR;
01315                                 }
01316                         }
01317                         if ( mii_rw ( priv, priv->phyaddr,
01318                                 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
01319                                 DBG ( "PHY init failed.\n" );
01320                                 return PHY_ERROR;
01321                         }
01322                 }
01323                 if ( priv->phy_model == PHY_MODEL_REALTEK_8201 ) {
01324                         if ( priv->driver_data & DEV_NEED_PHY_INIT_FIX ) {
01325                                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01326                                                         PHY_REALTEK_INIT_REG6,
01327                                                         MII_READ );
01328                                 phy_reserved |= PHY_REALTEK_INIT7;
01329                                 if ( mii_rw ( priv, priv->phyaddr,
01330                                               PHY_REALTEK_INIT_REG6,
01331                                               phy_reserved ) ) {
01332                                         DBG ( "PHY init failed.\n" );
01333                                         return PHY_ERROR;
01334                                 }
01335                         }
01336                 }
01337         }
01338 
01339         /* set advertise register */
01340         reg = mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, MII_READ );
01341         reg |= ( ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF |
01342                  ADVERTISE_100FULL | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP );
01343         if ( mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, reg ) ) {
01344                 DBG ( "PHY init failed.\n" );
01345                 return PHY_ERROR;
01346         }
01347 
01348         /* get phy interface type */
01349         phyinterface = readl ( ioaddr + NvRegPhyInterface );
01350 
01351         /* see if gigabit phy */
01352         mii_status = mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
01353         if ( mii_status & PHY_GIGABIT ) {
01354                 priv->gigabit = PHY_GIGABIT;
01355                 mii_control_1000 =
01356                         mii_rw ( priv, priv->phyaddr, MII_CTRL1000, MII_READ );
01357                 mii_control_1000 &= ~ADVERTISE_1000HALF;
01358                 if ( phyinterface & PHY_RGMII )
01359                         mii_control_1000 |= ADVERTISE_1000FULL;
01360                 else
01361                         mii_control_1000 &= ~ADVERTISE_1000FULL;
01362 
01363                 if ( mii_rw ( priv, priv->phyaddr, MII_CTRL1000, mii_control_1000)) {
01364                         DBG ( "PHY init failed.\n" );
01365                         return PHY_ERROR;
01366                 }
01367         } else {
01368                 priv->gigabit = 0;
01369         }
01370 
01371         mii_control = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
01372         mii_control |= BMCR_ANENABLE;
01373 
01374         if ( priv->phy_oui == PHY_OUI_REALTEK &&
01375              priv->phy_model == PHY_MODEL_REALTEK_8211 &&
01376              priv->phy_rev == PHY_REV_REALTEK_8211C ) {
01377                 /* start autoneg since we already performed hw reset above */
01378                 mii_control |= BMCR_ANRESTART;
01379                 if ( mii_rw ( priv, priv->phyaddr, MII_BMCR, mii_control ) ) {
01380                         DBG ( "PHY init failed.\n" );
01381                         return PHY_ERROR;
01382                 }
01383         } else {
01384                 /* reset the phy
01385                  * (certain phys need bmcr to be setup with reset )
01386                  */
01387                 if ( phy_reset ( priv, mii_control ) ) {
01388                         DBG ( "PHY reset failed\n" );
01389                         return PHY_ERROR;
01390                 }
01391         }
01392 
01393         /* phy vendor specific configuration */
01394         if ( ( priv->phy_oui == PHY_OUI_CICADA ) && ( phyinterface & PHY_RGMII ) ) {
01395                 phy_reserved = mii_rw ( priv, priv->phyaddr, MII_RESV1, MII_READ );
01396                 phy_reserved &= ~( PHY_CICADA_INIT1 | PHY_CICADA_INIT2 );
01397                 phy_reserved |= ( PHY_CICADA_INIT3 | PHY_CICADA_INIT4 );
01398                 if ( mii_rw ( priv, priv->phyaddr, MII_RESV1, phy_reserved ) ) {
01399                         DBG ( "PHY init failed.\n" );
01400                         return PHY_ERROR;
01401                 }
01402                 phy_reserved = mii_rw ( priv, priv->phyaddr, MII_NCONFIG, MII_READ );
01403                 phy_reserved |= PHY_CICADA_INIT5;
01404                 if ( mii_rw ( priv, priv->phyaddr, MII_NCONFIG, phy_reserved ) ) {
01405                         DBG ( "PHY init failed.\n" );
01406                         return PHY_ERROR;
01407                 }
01408         }
01409         if ( priv->phy_oui == PHY_OUI_CICADA ) {
01410                 phy_reserved = mii_rw ( priv, priv->phyaddr, MII_SREVISION, MII_READ );
01411                 phy_reserved |= PHY_CICADA_INIT6;
01412                 if ( mii_rw ( priv, priv->phyaddr, MII_SREVISION, phy_reserved ) ) {
01413                         DBG ( "PHY init failed.\n" );
01414                         return PHY_ERROR;
01415                 }
01416         }
01417         if ( priv->phy_oui == PHY_OUI_VITESSE ) {
01418                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG1,
01419                                                    PHY_VITESSE_INIT1)) {
01420                         DBG ( "PHY init failed.\n" );
01421                         return PHY_ERROR;
01422                 }
01423                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
01424                                                    PHY_VITESSE_INIT2)) {
01425                         DBG ( "PHY init failed.\n" );
01426                         return PHY_ERROR;
01427                 }
01428                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01429                                         PHY_VITESSE_INIT_REG4, MII_READ);
01430                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG4,
01431                                                    phy_reserved ) ) {
01432                         DBG ( "PHY init failed.\n" );
01433                         return PHY_ERROR;
01434                 }
01435                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01436                                         PHY_VITESSE_INIT_REG3, MII_READ);
01437                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
01438                 phy_reserved |= PHY_VITESSE_INIT3;
01439                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG3,
01440                                                    phy_reserved ) ) {
01441                         DBG ( "PHY init failed.\n" );
01442                         return PHY_ERROR;
01443                 }
01444                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
01445                                                    PHY_VITESSE_INIT4 ) ) {
01446                         DBG ( "PHY init failed.\n" );
01447                         return PHY_ERROR;
01448                 }
01449                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
01450                                                    PHY_VITESSE_INIT5 ) ) {
01451                         DBG ( "PHY init failed.\n" );
01452                         return PHY_ERROR;
01453                 }
01454                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01455                                         PHY_VITESSE_INIT_REG4, MII_READ);
01456                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
01457                 phy_reserved |= PHY_VITESSE_INIT3;
01458                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG4,
01459                                                    phy_reserved ) ) {
01460                         DBG ( "PHY init failed.\n" );
01461                         return PHY_ERROR;
01462                 }
01463                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01464                                         PHY_VITESSE_INIT_REG3, MII_READ);
01465                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG3,
01466                                                    phy_reserved ) ) {
01467                         DBG ( "PHY init failed.\n" );
01468                         return PHY_ERROR;
01469                 }
01470                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
01471                                                    PHY_VITESSE_INIT6 ) ) {
01472                         DBG ( "PHY init failed.\n" );
01473                         return PHY_ERROR;
01474                 }
01475                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
01476                                                    PHY_VITESSE_INIT7 ) ) {
01477                         DBG ( "PHY init failed.\n" );
01478                         return PHY_ERROR;
01479                 }
01480                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01481                                         PHY_VITESSE_INIT_REG4, MII_READ);
01482                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG4,
01483                                                    phy_reserved ) ) {
01484                         DBG ( "PHY init failed.\n" );
01485                         return PHY_ERROR;
01486                 }
01487                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01488                                         PHY_VITESSE_INIT_REG3, MII_READ);
01489                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
01490                 phy_reserved |= PHY_VITESSE_INIT8;
01491                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG3,
01492                                                    phy_reserved ) ) {
01493                         DBG ( "PHY init failed.\n" );
01494                         return PHY_ERROR;
01495                 }
01496                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG2,
01497                                                    PHY_VITESSE_INIT9 ) ) {
01498                         DBG ( "PHY init failed.\n" );
01499                         return PHY_ERROR;
01500                 }
01501                 if ( mii_rw ( priv, priv->phyaddr, PHY_VITESSE_INIT_REG1,
01502                                                    PHY_VITESSE_INIT10 ) ) {
01503                         DBG ( "PHY init failed.\n" );
01504                         return PHY_ERROR;
01505                 }
01506         }
01507 
01508         if ( priv->phy_oui == PHY_OUI_REALTEK ) {
01509                 if ( priv->phy_model == PHY_MODEL_REALTEK_8211 &&
01510                      priv->phy_rev == PHY_REV_REALTEK_8211B ) {
01511                         /* reset could have cleared these out, set them back */
01512                         if ( mii_rw ( priv, priv->phyaddr,
01513                                       PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
01514                                 DBG ( "PHY init failed.\n" );
01515                                 return PHY_ERROR;
01516                         }
01517                         if ( mii_rw ( priv, priv->phyaddr,
01518                                       PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 ) ) {
01519                                 DBG ( "PHY init failed.\n" );
01520                                 return PHY_ERROR;
01521                         }
01522                         if ( mii_rw ( priv, priv->phyaddr,
01523                                       PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 ) ) {
01524                                 DBG ( "PHY init failed.\n" );
01525                                 return PHY_ERROR;
01526                         }
01527                         if ( mii_rw ( priv, priv->phyaddr,
01528                                       PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 ) ) {
01529                                 DBG ( "PHY init failed.\n" );
01530                                 return PHY_ERROR;
01531                         }
01532                         if ( mii_rw ( priv, priv->phyaddr,
01533                                       PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 ) ) {
01534                                 DBG ( "PHY init failed.\n" );
01535                                 return PHY_ERROR;
01536                         }
01537                         if ( mii_rw ( priv, priv->phyaddr,
01538                                       PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 ) ) {
01539                                 DBG ( "PHY init failed.\n" );
01540                                 return PHY_ERROR;
01541                         }
01542                         if ( mii_rw ( priv, priv->phyaddr,
01543                                       PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 ) ) {
01544                                 DBG ( "PHY init failed.\n" );
01545                                 return PHY_ERROR;
01546                         }
01547                 }
01548                 if ( priv->phy_model == PHY_MODEL_REALTEK_8201 ) {
01549                         if ( priv->driver_data & DEV_NEED_PHY_INIT_FIX ) {
01550                                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01551                                                         PHY_REALTEK_INIT_REG6,
01552                                                         MII_READ );
01553                                 phy_reserved |= PHY_REALTEK_INIT7;
01554                                 if ( mii_rw ( priv, priv->phyaddr,
01555                                               PHY_REALTEK_INIT_REG6,
01556                                               phy_reserved ) ) {
01557                                         DBG ( "PHY init failed.\n" );
01558                                         return PHY_ERROR;
01559                                 }
01560                         }
01561 
01562                         if ( mii_rw ( priv, priv->phyaddr,
01563                                       PHY_REALTEK_INIT_REG1,
01564                                       PHY_REALTEK_INIT3 ) ) {
01565                                 DBG ( "PHY init failed.\n" );
01566                                 return PHY_ERROR;
01567                         }
01568                         phy_reserved = mii_rw ( priv, priv->phyaddr,
01569                                                 PHY_REALTEK_INIT_REG2,
01570                                                 MII_READ );
01571                         phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
01572                         phy_reserved |= PHY_REALTEK_INIT3;
01573                         if ( mii_rw ( priv, priv->phyaddr,
01574                                       PHY_REALTEK_INIT_REG2,
01575                                       phy_reserved ) ) {
01576                                 DBG ( "PHY init failed.\n" );
01577                                 return PHY_ERROR;
01578                         }
01579                         if ( mii_rw ( priv, priv->phyaddr,
01580                                       PHY_REALTEK_INIT_REG1,
01581                                       PHY_REALTEK_INIT1 ) ) {
01582                                 DBG ( "PHY init failed.\n" );
01583                                 return PHY_ERROR;
01584                         }
01585                 }
01586         }
01587 
01588         /* some phys clear out pause advertisement on reset, set it back */
01589         mii_rw ( priv, priv->phyaddr, MII_ADVERTISE, reg );
01590 
01591         /* restart auto negotiation, power down phy */
01592         mii_control = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
01593         mii_control |= ( BMCR_ANRESTART | BMCR_ANENABLE );
01594         if ( mii_rw ( priv, priv->phyaddr, MII_BMCR, mii_control ) ) {
01595                 return PHY_ERROR;
01596         }
01597 
01598         return 0;
01599 }
01600 
01601 /**
01602  * nv_setup_phy - Find PHY and initialize it
01603  *
01604  * @v priv      Driver private structure
01605  *
01606  * @ret rc      Return status code
01607  **/
01608 static int
01609 nv_setup_phy ( struct forcedeth_private *priv )
01610 {
01611         void *ioaddr = priv->mmio_addr;
01612         u32 phystate_orig = 0, phystate;
01613         int phyinitialised = 0;
01614         u32 powerstate;
01615         int rc = 0;
01616         int i;
01617 
01618         if ( priv->driver_data & DEV_HAS_POWER_CNTRL ) {
01619                 /* take phy and nic out of low power mode */
01620                 powerstate = readl ( ioaddr + NvRegPowerState2 );
01621                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
01622                 if ( ( priv->driver_data & DEV_NEED_LOW_POWER_FIX ) &&
01623                      ( ( priv->pci_dev->class & 0xff ) >= 0xA3 ) )
01624                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
01625                 writel ( powerstate, ioaddr + NvRegPowerState2 );
01626         }
01627 
01628 
01629         /* clear phy state and temporarily halt phy interrupts */
01630         writel ( 0, ioaddr + NvRegMIIMask );
01631         phystate = readl ( ioaddr + NvRegAdapterControl );
01632         if ( phystate & NVREG_ADAPTCTL_RUNNING ) {
01633                 phystate_orig = 1;
01634                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
01635                 writel ( phystate, ioaddr + NvRegAdapterControl );
01636         }
01637         writel ( NVREG_MIISTAT_MASK_ALL, ioaddr + NvRegMIIStatus );
01638 
01639         if ( priv->driver_data & DEV_HAS_MGMT_UNIT ) {
01640                 /* management unit running on the mac? */
01641                 if ( ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_MGMT_ST ) &&
01642                      ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_SYNC_PHY_INIT ) &&
01643                      nv_mgmt_acquire_sema ( priv ) &&
01644                      nv_mgmt_get_version ( priv ) ) {
01645                         priv->mac_in_use = 1;
01646                         if ( priv->mgmt_version > 0 ) {
01647                                 priv->mac_in_use = readl ( ioaddr + NvRegMgmtUnitControl ) & NVREG_MGMTUNITCONTROL_INUSE;
01648                         }
01649 
01650                         DBG ( "mgmt unit is running. mac in use\n" );
01651 
01652                         /* management unit setup the phy already? */
01653                         if ( priv->mac_in_use &&
01654                            ( ( readl ( ioaddr + NvRegTransmitterControl ) & NVREG_XMITCTL_SYNC_MASK ) ==
01655                              NVREG_XMITCTL_SYNC_PHY_INIT ) ) {
01656                                 /* phy is inited by mgmt unit */
01657                                 phyinitialised = 1;
01658                                 DBG ( "Phy already initialized by mgmt unit" );
01659                         }
01660                 }
01661         }
01662 
01663         /* find a suitable phy */
01664         for ( i = 1; i <= 32; i++ ) {
01665                 int id1, id2;
01666                 int phyaddr = i & 0x1f;
01667 
01668                 id1 = mii_rw ( priv, phyaddr, MII_PHYSID1, MII_READ );
01669                 if ( id1 < 0 || id1 == 0xffff )
01670                         continue;
01671                 id2 = mii_rw ( priv, phyaddr, MII_PHYSID2, MII_READ );
01672                 if ( id2 < 0 || id2 == 0xffff )
01673                         continue;
01674 
01675                 priv->phy_model = id2 & PHYID2_MODEL_MASK;
01676                 id1 = ( id1 & PHYID1_OUI_MASK ) << PHYID1_OUI_SHFT;
01677                 id2 = ( id2 & PHYID2_OUI_MASK ) >> PHYID2_OUI_SHFT;
01678                 DBG ( "Found PHY: %04x:%04x at address %d\n", id1, id2, phyaddr );
01679                 priv->phyaddr = phyaddr;
01680                 priv->phy_oui = id1 | id2;
01681 
01682                 /* Realtek hardcoded phy id1 to all zeros on certain phys */
01683                 if ( priv->phy_oui == PHY_OUI_REALTEK2 )
01684                         priv->phy_oui = PHY_OUI_REALTEK;
01685                 /* Setup phy revision for Realtek */
01686                 if ( priv->phy_oui == PHY_OUI_REALTEK &&
01687                      priv->phy_model == PHY_MODEL_REALTEK_8211 )
01688                         priv->phy_rev = mii_rw ( priv, phyaddr, MII_RESV1,
01689                                                  MII_READ ) & PHY_REV_MASK;
01690                 break;
01691         }
01692         if ( i == 33 ) {
01693                 DBG ( "Could not find a valid PHY.\n" );
01694                 rc = -ENODEV;
01695                 goto err_phy;
01696         }
01697 
01698         if ( ! phyinitialised ) {
01699                 /* reset it */
01700                 phy_init ( priv );
01701         } else {
01702                 u32 mii_status = mii_rw ( priv, priv->phyaddr, MII_BMSR, MII_READ );
01703                 if ( mii_status & PHY_GIGABIT ) {
01704                         priv->gigabit = PHY_GIGABIT;
01705                 }
01706         }
01707 
01708         return 0;
01709 
01710 err_phy:
01711         if ( phystate_orig )
01712                 writel ( phystate | NVREG_ADAPTCTL_RUNNING,
01713                          ioaddr + NvRegAdapterControl );
01714         return rc;
01715 }
01716 
01717 /**
01718  * forcedeth_map_regs - Find a suitable BAR for the NIC and
01719  * map the registers in memory
01720  *
01721  * @v priv      Driver private structure
01722  *
01723  * @ret rc      Return status code
01724  **/
01725 static int
01726 forcedeth_map_regs ( struct forcedeth_private *priv )
01727 {
01728         void *ioaddr;
01729         uint32_t bar;
01730         unsigned long addr;
01731         u32 register_size;
01732         int reg;
01733         int rc;
01734 
01735         /* Set register size based on NIC */
01736         if ( priv->driver_data & ( DEV_HAS_VLAN | DEV_HAS_MSI_X |
01737                 DEV_HAS_POWER_CNTRL | DEV_HAS_STATISTICS_V2 |
01738                 DEV_HAS_STATISTICS_V3 ) ) {
01739                 register_size = NV_PCI_REGSZ_VER3;
01740         } else if ( priv->driver_data & DEV_HAS_STATISTICS_V1 ) {
01741                 register_size = NV_PCI_REGSZ_VER2;
01742         } else {
01743                 register_size = NV_PCI_REGSZ_VER1;
01744         }
01745 
01746         /* Find an appropriate region for all the registers */
01747         rc = -EINVAL;
01748         addr = 0;
01749         for ( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 ) {
01750                 pci_read_config_dword ( priv->pci_dev, reg, &bar );
01751 
01752                 if ( ( ! ( bar & PCI_BASE_ADDRESS_SPACE_IO ) ) &&
01753                      ( pci_bar_size ( priv->pci_dev, reg ) >= register_size ) ){
01754                         addr = pci_bar_start ( priv->pci_dev, reg );
01755                         break;
01756                 }
01757         }
01758 
01759         if ( reg > PCI_BASE_ADDRESS_5 ) {
01760                 DBG ( "Couldn't find register window\n" );
01761                 goto err_bar_sz;
01762         }
01763 
01764         rc = -ENOMEM;
01765         ioaddr = ioremap ( addr, register_size );
01766         if ( ! ioaddr ) {
01767                 DBG ( "Cannot remap MMIO\n" );
01768                 goto err_ioremap;
01769         }
01770 
01771         priv->mmio_addr = ioaddr;
01772 
01773         return 0;
01774 
01775 err_bar_sz:
01776 err_ioremap:
01777         return rc;
01778 }
01779 
01780 /**
01781  * probe - Initial configuration of NIC
01782  *
01783  * @v pdev      PCI device
01784  * @v ent       PCI IDs
01785  *
01786  * @ret rc      Return status code
01787  **/
01788 static int
01789 forcedeth_probe ( struct pci_device *pdev )
01790 {
01791         struct net_device *netdev;
01792         struct forcedeth_private *priv;
01793         void *ioaddr;
01794         int rc;
01795 
01796         DBGP ( "forcedeth_probe\n" );
01797 
01798         DBG ( "Found %s, vendor = %#04x, device = %#04x\n",
01799               pdev->id->name, pdev->id->vendor, pdev->id->device );
01800 
01801         /* Allocate our private data */
01802         netdev = alloc_etherdev ( sizeof ( *priv ) );
01803         if ( ! netdev ) {
01804                 rc = -ENOMEM;
01805                 DBG ( "Failed to allocate net device\n" );
01806                 goto err_alloc_etherdev;
01807         }
01808 
01809         /* Link our operations to the netdev struct */
01810         netdev_init ( netdev, &forcedeth_operations );
01811 
01812         /* Link the PCI device to the netdev struct */
01813         pci_set_drvdata ( pdev, netdev );
01814         netdev->dev = &pdev->dev;
01815 
01816         /* Get a reference to our private data */
01817         priv = netdev_priv ( netdev );
01818 
01819         /* We'll need these set up for the rest of the routines */
01820         priv->pci_dev = pdev;
01821         priv->netdev = netdev;
01822         priv->driver_data = pdev->id->driver_data;
01823 
01824         adjust_pci_device ( pdev );
01825 
01826         /* Use memory mapped I/O */
01827         if ( ( rc = forcedeth_map_regs ( priv ) ) != 0 )
01828                 goto err_map_regs;
01829         ioaddr = priv->mmio_addr;
01830 
01831         /* Verify and get MAC address */
01832         if ( ( rc = nv_setup_mac_addr ( priv ) ) != 0 ) {
01833                 DBG ( "Invalid MAC address detected\n" );
01834                 goto err_mac_addr;
01835         }
01836 
01837         /* Disable WOL */
01838         writel ( 0, ioaddr + NvRegWakeUpFlags );
01839 
01840         if ( ( rc = nv_setup_phy ( priv ) ) != 0 )
01841                 goto err_setup_phy;
01842 
01843         /* Set Pause Frame parameters */
01844         priv->pause_flags = NV_PAUSEFRAME_RX_CAPABLE |
01845                             NV_PAUSEFRAME_RX_REQ |
01846                             NV_PAUSEFRAME_AUTONEG;
01847         if ( ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V1 ) ||
01848              ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V2 ) ||
01849              ( priv->driver_data & DEV_HAS_PAUSEFRAME_TX_V3 ) ) {
01850                 priv->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
01851         }
01852 
01853         if ( priv->pause_flags & NV_PAUSEFRAME_TX_CAPABLE )
01854                 writel ( NVREG_TX_PAUSEFRAME_DISABLE, ioaddr + NvRegTxPauseFrame );
01855 
01856         /* Set default link speed settings */
01857         priv->linkspeed = NVREG_LINKSPEED_FORCE | NVREG_LINKSPEED_10;
01858         priv->duplex = 0;
01859 
01860         if ( ( rc = register_netdev ( netdev ) ) != 0 ) {
01861                 DBG ( "Error registering netdev\n" );
01862                 goto err_register_netdev;
01863         }
01864 
01865         forcedeth_link_status ( netdev );
01866 
01867         return 0;
01868 
01869 err_register_netdev:
01870 err_setup_phy:
01871 err_mac_addr:
01872         iounmap ( priv->mmio_addr );
01873 err_map_regs:
01874         netdev_nullify ( netdev );
01875         netdev_put ( netdev );
01876 err_alloc_etherdev:
01877         return rc;
01878 }
01879 
01880 static void
01881 nv_restore_phy ( struct forcedeth_private *priv )
01882 {
01883         u16 phy_reserved, mii_control;
01884 
01885         if ( priv->phy_oui == PHY_OUI_REALTEK &&
01886              priv->phy_model == PHY_MODEL_REALTEK_8201 ) {
01887                 mii_rw ( priv, priv->phyaddr, PHY_REALTEK_INIT_REG1,
01888                                               PHY_REALTEK_INIT3 );
01889                 phy_reserved = mii_rw ( priv, priv->phyaddr,
01890                                         PHY_REALTEK_INIT_REG2, MII_READ );
01891                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
01892                 phy_reserved |= PHY_REALTEK_INIT8;
01893                 mii_rw ( priv, priv->phyaddr, PHY_REALTEK_INIT_REG2,
01894                                               phy_reserved );
01895                 mii_rw ( priv, priv->phyaddr, PHY_REALTEK_INIT_REG1,
01896                                               PHY_REALTEK_INIT1 );
01897 
01898                 /* restart auto negotiation */
01899                 mii_control = mii_rw ( priv, priv->phyaddr, MII_BMCR, MII_READ );
01900                 mii_control |= ( BMCR_ANRESTART | BMCR_ANENABLE );
01901                 mii_rw ( priv, priv->phyaddr, MII_BMCR, mii_control );
01902         }
01903 }
01904 
01905 /**
01906  * remove - Device Removal Routine
01907  *
01908  * @v pdev PCI device information struct
01909  **/
01910 static void
01911 forcedeth_remove ( struct pci_device *pdev )
01912 {
01913         struct net_device *netdev = pci_get_drvdata ( pdev );
01914         struct forcedeth_private *priv = netdev->priv;
01915 
01916         DBGP ( "forcedeth_remove\n" );
01917 
01918         unregister_netdev ( netdev );
01919 
01920         nv_restore_phy ( priv );
01921 
01922         nv_mgmt_release_sema ( priv );
01923 
01924         iounmap ( priv->mmio_addr );
01925 
01926         netdev_nullify ( netdev );
01927         netdev_put ( netdev );
01928 }
01929 
01930 static struct pci_device_id forcedeth_nics[] = {
01931         PCI_ROM(0x10DE, 0x01C3, "nForce", "nForce Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
01932         PCI_ROM(0x10DE, 0x0066, "nForce2", "nForce2 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
01933         PCI_ROM(0x10DE, 0x00D6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER),
01934         PCI_ROM(0x10DE, 0x0086, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
01935         PCI_ROM(0x10DE, 0x008C, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
01936         PCI_ROM(0x10DE, 0x00E6, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
01937         PCI_ROM(0x10DE, 0x00DF, "nForce3", "nForce3 Ethernet Controller", DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC| DEV_HAS_CHECKSUM),
01938         PCI_ROM(0x10DE, 0x0056, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
01939         PCI_ROM(0x10DE, 0x0057, "CK804", "CK804 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
01940         PCI_ROM(0x10DE, 0x0037, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
01941         PCI_ROM(0x10DE, 0x0038, "MCP04", "MCP04 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT),
01942         PCI_ROM(0x10DE, 0x0268, "MCP51", "MCP51 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX),
01943         PCI_ROM(0x10DE, 0x0269, "MCP51", "MCP51 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX),
01944         PCI_ROM(0x10DE, 0x0372, "MCP55", "MCP55 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X| DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED| DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX),
01945         PCI_ROM(0x10DE, 0x0373, "MCP55", "MCP55 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X| DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX),
01946         PCI_ROM(0x10DE, 0x03E5, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
01947         PCI_ROM(0x10DE, 0x03E6, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
01948         PCI_ROM(0x10DE, 0x03EE, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
01949         PCI_ROM(0x10DE, 0x03EF, "MCP61", "MCP61 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_NEED_MSI_FIX),
01950         PCI_ROM(0x10DE, 0x0450, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
01951         PCI_ROM(0x10DE, 0x0451, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
01952         PCI_ROM(0x10DE, 0x0452, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
01953         PCI_ROM(0x10DE, 0x0453, "MCP65", "MCP65 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA| DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1| DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE| DEV_NEED_MSI_FIX),
01954         PCI_ROM(0x10DE, 0x054C, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01955         PCI_ROM(0x10DE, 0x054D, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01956         PCI_ROM(0x10DE, 0x054E, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01957         PCI_ROM(0x10DE, 0x054F, "MCP67", "MCP67 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01958         PCI_ROM(0x10DE, 0x07DC, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01959         PCI_ROM(0x10DE, 0x07DD, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01960         PCI_ROM(0x10DE, 0x07DE, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01961         PCI_ROM(0x10DE, 0x07DF, "MCP73", "MCP73 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL| DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2| DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX),
01962         PCI_ROM(0x10DE, 0x0760, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
01963         PCI_ROM(0x10DE, 0x0761, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
01964         PCI_ROM(0x10DE, 0x0762, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
01965         PCI_ROM(0x10DE, 0x0763, "MCP77", "MCP77 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA| DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2| DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT| DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX| DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX| DEV_NEED_MSI_FIX),
01966         PCI_ROM(0x10DE, 0x0AB0, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
01967         PCI_ROM(0x10DE, 0x0AB1, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
01968         PCI_ROM(0x10DE, 0x0AB2, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
01969         PCI_ROM(0x10DE, 0x0AB3, "MCP79", "MCP79 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE| DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX),
01970         PCI_ROM(0x10DE, 0x0D7D, "MCP89", "MCP89 Ethernet Controller", DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM| DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL| DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3| DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR| DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX),
01971 };
01972 
01973 struct pci_driver forcedeth_driver __pci_driver = {
01974         .ids            = forcedeth_nics,
01975         .id_count       = ARRAY_SIZE(forcedeth_nics),
01976         .probe          = forcedeth_probe,
01977         .remove         = forcedeth_remove,
01978 };