iPXE
etherfabric.c
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00001 /**************************************************************************
00002  *
00003  * Etherboot driver for Level 5 Etherfabric network cards
00004  *
00005  * Written by Michael Brown <mbrown@fensystems.co.uk>
00006  *
00007  * Copyright Fen Systems Ltd. 2005
00008  * Copyright Level 5 Networks Inc. 2005
00009  *
00010  * This software may be used and distributed according to the terms of
00011  * the GNU General Public License (GPL), incorporated herein by
00012  * reference.  Drivers based on or derived from this code fall under
00013  * the GPL and must retain the authorship, copyright and license
00014  * notice.
00015  *
00016  **************************************************************************
00017  */
00018 
00019 FILE_LICENCE ( GPL_ANY );
00020 
00021 #include <stdint.h>
00022 #include <stdlib.h>
00023 #include <stdio.h>
00024 #include <unistd.h>
00025 #include <errno.h>
00026 #include <assert.h>
00027 #include <byteswap.h>
00028 #include <ipxe/io.h>
00029 #include <ipxe/pci.h>
00030 #include <ipxe/malloc.h>
00031 #include <ipxe/ethernet.h>
00032 #include <ipxe/iobuf.h>
00033 #include <ipxe/netdevice.h>
00034 #include <ipxe/timer.h>
00035 #include <mii.h>
00036 #include "etherfabric.h"
00037 #include "etherfabric_nic.h"
00038 
00039 /**************************************************************************
00040  *
00041  * Constants and macros
00042  *
00043  **************************************************************************
00044  */
00045 
00046 #define EFAB_REGDUMP(...)
00047 #define EFAB_TRACE(...) DBGP(__VA_ARGS__)
00048 
00049 // printf() is not allowed within drivers.  Use DBG() instead.
00050 #define EFAB_LOG(...) DBG(__VA_ARGS__)
00051 #define EFAB_ERR(...) DBG(__VA_ARGS__)
00052 
00053 #define FALCON_USE_IO_BAR 0
00054 
00055 #define HZ 100
00056 #define EFAB_BYTE 1
00057 
00058 /**************************************************************************
00059  *
00060  * Hardware data structures and sizing
00061  *
00062  **************************************************************************
00063  */
00064 extern int __invalid_queue_size;
00065 #define FQS(_prefix, _x)                                        \
00066         ( ( (_x) == 512 ) ? _prefix ## _SIZE_512 :              \
00067           ( ( (_x) == 1024 ) ? _prefix ## _SIZE_1K :            \
00068             ( ( (_x) == 2048 ) ? _prefix ## _SIZE_2K :          \
00069               ( ( (_x) == 4096) ? _prefix ## _SIZE_4K :         \
00070                 __invalid_queue_size ) ) ) )
00071 
00072 
00073 #define EFAB_MAX_FRAME_LEN(mtu)                         \
00074         ( ( ( ( mtu ) + 4/* FCS */ ) + 7 ) & ~7 )
00075 
00076 /**************************************************************************
00077  *
00078  * GMII routines
00079  *
00080  **************************************************************************
00081  */
00082 
00083 static void falcon_mdio_write (struct efab_nic *efab, int device,
00084                                int location, int value );
00085 static int falcon_mdio_read ( struct efab_nic *efab, int device, int location );
00086 
00087 /* GMII registers */
00088 #define GMII_PSSR               0x11    /* PHY-specific status register */
00089 
00090 /* Pseudo extensions to the link partner ability register */
00091 #define LPA_EF_1000FULL         0x00020000
00092 #define LPA_EF_1000HALF         0x00010000
00093 #define LPA_EF_10000FULL                0x00040000
00094 #define LPA_EF_10000HALF                0x00080000
00095 
00096 #define LPA_EF_1000             ( LPA_EF_1000FULL | LPA_EF_1000HALF )
00097 #define LPA_EF_10000               ( LPA_EF_10000FULL | LPA_EF_10000HALF )
00098 #define LPA_EF_DUPLEX           ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \
00099                                   LPA_EF_10000FULL )
00100 
00101 /* Mask of bits not associated with speed or duplexity. */
00102 #define LPA_OTHER               ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \
00103                                    LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF )
00104 
00105 /* PHY-specific status register */
00106 #define PSSR_LSTATUS            0x0400  /* Bit 10 - link status */
00107 
00108 /**
00109  * Retrieve GMII autonegotiation advertised abilities
00110  *
00111  */
00112 static unsigned int
00113 gmii_autoneg_advertised ( struct efab_nic *efab )
00114 {
00115         unsigned int mii_advertise;
00116         unsigned int gmii_advertise;
00117 
00118         /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */
00119         mii_advertise = falcon_mdio_read ( efab, 0, MII_ADVERTISE );
00120         gmii_advertise = ( ( falcon_mdio_read ( efab, 0, MII_CTRL1000 ) >> 8 )
00121                            & 0x03 );
00122         return ( ( gmii_advertise << 16 ) | mii_advertise );
00123 }
00124 
00125 /**
00126  * Retrieve GMII autonegotiation link partner abilities
00127  *
00128  */
00129 static unsigned int
00130 gmii_autoneg_lpa ( struct efab_nic *efab )
00131 {
00132         unsigned int mii_lpa;
00133         unsigned int gmii_lpa;
00134 
00135         /* Extended bits are in bits 10 and 11 of MII_STAT1000 */
00136         mii_lpa = falcon_mdio_read ( efab, 0, MII_LPA );
00137         gmii_lpa = ( falcon_mdio_read ( efab, 0, MII_STAT1000 ) >> 10 ) & 0x03;
00138         return ( ( gmii_lpa << 16 ) | mii_lpa );
00139 }
00140 
00141 /**
00142  * Calculate GMII autonegotiated link technology
00143  *
00144  */
00145 static unsigned int
00146 gmii_nway_result ( unsigned int negotiated )
00147 {
00148         unsigned int other_bits;
00149 
00150         /* Mask out the speed and duplexity bits */
00151         other_bits = negotiated & LPA_OTHER;
00152 
00153         if ( negotiated & LPA_EF_1000FULL )
00154                 return ( other_bits | LPA_EF_1000FULL );
00155         else if ( negotiated & LPA_EF_1000HALF )
00156                 return ( other_bits | LPA_EF_1000HALF );
00157         else if ( negotiated & LPA_100FULL )
00158                 return ( other_bits | LPA_100FULL );
00159         else if ( negotiated & LPA_100BASE4 )
00160                 return ( other_bits | LPA_100BASE4 );
00161         else if ( negotiated & LPA_100HALF )
00162                 return ( other_bits | LPA_100HALF );
00163         else if ( negotiated & LPA_10FULL )
00164                 return ( other_bits | LPA_10FULL );
00165         else return ( other_bits | LPA_10HALF );
00166 }
00167 
00168 /**
00169  * Check GMII PHY link status
00170  *
00171  */
00172 static int
00173 gmii_link_ok ( struct efab_nic *efab )
00174 {
00175         int status;
00176         int phy_status;
00177 
00178         /* BMSR is latching - it returns "link down" if the link has
00179          * been down at any point since the last read.  To get a
00180          * real-time status, we therefore read the register twice and
00181          * use the result of the second read.
00182          */
00183         (void) falcon_mdio_read ( efab, 0, MII_BMSR );
00184         status = falcon_mdio_read ( efab, 0, MII_BMSR );
00185 
00186         /* Read the PHY-specific Status Register.  This is
00187          * non-latching, so we need do only a single read.
00188          */
00189         phy_status = falcon_mdio_read ( efab, 0, GMII_PSSR );
00190 
00191         return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) );
00192 }
00193 
00194 /**************************************************************************
00195  *
00196  * MDIO routines
00197  *
00198  **************************************************************************
00199  */
00200 
00201 /* Numbering of the MDIO Manageable Devices (MMDs) */
00202 /* Physical Medium Attachment/ Physical Medium Dependent sublayer */
00203 #define MDIO_MMD_PMAPMD (1)
00204 /* WAN Interface Sublayer */
00205 #define MDIO_MMD_WIS    (2)
00206 /* Physical Coding Sublayer */
00207 #define MDIO_MMD_PCS    (3)
00208 /* PHY Extender Sublayer */
00209 #define MDIO_MMD_PHYXS  (4)
00210 /* Extender Sublayer */
00211 #define MDIO_MMD_DTEXS  (5)
00212 /* Transmission convergence */
00213 #define MDIO_MMD_TC     (6)
00214 /* Auto negotiation */
00215 #define MDIO_MMD_AN     (7)
00216 
00217 /* Generic register locations */
00218 #define MDIO_MMDREG_CTRL1       (0)
00219 #define MDIO_MMDREG_STAT1       (1)
00220 #define MDIO_MMDREG_DEVS0       (5)
00221 #define MDIO_MMDREG_STAT2       (8)
00222 
00223 /* Bits in MMDREG_CTRL1 */
00224 /* Reset */
00225 #define MDIO_MMDREG_CTRL1_RESET_LBN     (15)
00226 #define MDIO_MMDREG_CTRL1_RESET_WIDTH   (1)
00227 
00228 /* Bits in MMDREG_STAT1 */
00229 #define MDIO_MMDREG_STAT1_FAULT_LBN     (7)
00230 #define MDIO_MMDREG_STAT1_FAULT_WIDTH   (1)
00231 
00232 /* Link state */
00233 #define MDIO_MMDREG_STAT1_LINK_LBN      (2)
00234 #define MDIO_MMDREG_STAT1_LINK_WIDTH    (1)
00235 
00236 /* Bits in MMDREG_DEVS0. */
00237 #define DEV_PRESENT_BIT(_b) (1 << _b)
00238 
00239 #define MDIO_MMDREG_DEVS0_DTEXS  DEV_PRESENT_BIT(MDIO_MMD_DTEXS)
00240 #define MDIO_MMDREG_DEVS0_PHYXS  DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
00241 #define MDIO_MMDREG_DEVS0_PCS    DEV_PRESENT_BIT(MDIO_MMD_PCS)
00242 #define MDIO_MMDREG_DEVS0_WIS    DEV_PRESENT_BIT(MDIO_MMD_WIS)
00243 #define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
00244 
00245 #define MDIO_MMDREG_DEVS0_AN     DEV_PRESENT_BIT(MDIO_MMD_AN)
00246 
00247 /* Bits in MMDREG_STAT2 */
00248 #define MDIO_MMDREG_STAT2_PRESENT_VAL   (2)
00249 #define MDIO_MMDREG_STAT2_PRESENT_LBN   (14)
00250 #define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
00251 
00252 /* PHY XGXS lane state */
00253 #define MDIO_PHYXS_LANE_STATE           (0x18) 
00254 #define MDIO_PHYXS_LANE_ALIGNED_LBN     (12)
00255 #define MDIO_PHYXS_LANE_SYNC0_LBN       (0)
00256 #define MDIO_PHYXS_LANE_SYNC1_LBN       (1)
00257 #define MDIO_PHYXS_LANE_SYNC2_LBN       (2)
00258 #define MDIO_PHYXS_LANE_SYNC3_LBN       (3)
00259 
00260 /* This ought to be ridiculous overkill. We expect it to fail rarely */
00261 #define MDIO45_RESET_TRIES      100
00262 #define MDIO45_RESET_SPINTIME   10
00263 
00264 static int
00265 mdio_clause45_wait_reset_mmds ( struct efab_nic* efab )
00266 {
00267         int tries = MDIO45_RESET_TRIES;
00268         int in_reset;
00269 
00270         while(tries) {
00271                 int mask = efab->phy_op->mmds;
00272                 int mmd = 0;
00273                 in_reset = 0;
00274                 while(mask) {
00275                         if (mask & 1) {
00276                                 int stat = falcon_mdio_read ( efab,  mmd,
00277                                                               MDIO_MMDREG_CTRL1 );
00278                                 if (stat < 0) {
00279                                         EFAB_ERR("Failed to read status of MMD %d\n",
00280                                                  mmd );
00281                                         in_reset = 1;
00282                                         break;
00283                                 }
00284                                 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
00285                                         in_reset |= (1 << mmd);
00286                         }
00287                         mask = mask >> 1;
00288                         mmd++;
00289                 }
00290                 if (!in_reset)
00291                         break;
00292                 tries--;
00293                 mdelay ( MDIO45_RESET_SPINTIME );
00294         }
00295         if (in_reset != 0) {
00296                 EFAB_ERR("Not all MMDs came out of reset in time. MMDs "
00297                          "still in reset: %x\n", in_reset);
00298                 return -ETIMEDOUT;
00299         }
00300         return 0;
00301 }
00302 
00303 static int
00304 mdio_clause45_reset_mmd ( struct efab_nic *efab, int mmd )
00305 {
00306         int tries = MDIO45_RESET_TRIES;
00307         int ctrl;
00308 
00309         falcon_mdio_write ( efab, mmd, MDIO_MMDREG_CTRL1,
00310                             ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) );
00311 
00312         /* Wait for the reset bit to clear. */
00313         do {
00314                 mdelay ( MDIO45_RESET_SPINTIME );
00315 
00316                 ctrl = falcon_mdio_read ( efab, mmd, MDIO_MMDREG_CTRL1 );
00317                 if ( ~ctrl & ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) )
00318                         return 0;
00319         } while ( --tries );
00320 
00321         EFAB_ERR ( "Failed to reset mmd %d\n", mmd );
00322 
00323         return -ETIMEDOUT;
00324 }
00325 
00326 static int
00327 mdio_clause45_links_ok(struct efab_nic *efab )
00328 {
00329         int status, good;
00330         int ok = 1;
00331         int mmd = 0;
00332         int mmd_mask = efab->phy_op->mmds;
00333 
00334         while (mmd_mask) {
00335                 if (mmd_mask & 1) {
00336                         /* Double reads because link state is latched, and a
00337                          * read moves the current state into the register */
00338                         status = falcon_mdio_read ( efab, mmd,
00339                                                     MDIO_MMDREG_STAT1 );
00340                         status = falcon_mdio_read ( efab, mmd,
00341                                                     MDIO_MMDREG_STAT1 );
00342 
00343                         good = status & (1 << MDIO_MMDREG_STAT1_LINK_LBN);
00344                         ok = ok && good;
00345                 }
00346                 mmd_mask = (mmd_mask >> 1);
00347                 mmd++;
00348         }
00349         return ok;
00350 }
00351 
00352 static int
00353 mdio_clause45_check_mmds ( struct efab_nic *efab )
00354 {
00355         int mmd = 0;
00356         int devices = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
00357                                          MDIO_MMDREG_DEVS0 );
00358         int mmd_mask = efab->phy_op->mmds;
00359 
00360         /* Check all the expected MMDs are present */
00361         if ( devices < 0 ) {
00362                 EFAB_ERR ( "Failed to read devices present\n" );
00363                 return -EIO;
00364         }
00365         if ( ( devices & mmd_mask ) != mmd_mask ) {
00366                 EFAB_ERR ( "required MMDs not present: got %x, wanted %x\n",
00367                            devices, mmd_mask );
00368                 return -EIO;
00369         }
00370 
00371         /* Check all required MMDs are responding and happy. */
00372         while ( mmd_mask ) {
00373                 if ( mmd_mask & 1 ) {
00374                         efab_dword_t reg;
00375                         int status;
00376                         reg.opaque = falcon_mdio_read ( efab, mmd,
00377                                                         MDIO_MMDREG_STAT2 );
00378                         status = EFAB_DWORD_FIELD ( reg,
00379                                                     MDIO_MMDREG_STAT2_PRESENT );
00380                         if ( status != MDIO_MMDREG_STAT2_PRESENT_VAL ) {
00381 
00382 
00383                                 return -EIO;
00384                         }
00385                 }
00386                 mmd_mask >>= 1;
00387                 mmd++;
00388         }
00389 
00390         return 0;
00391 }
00392 
00393 /* I/O BAR address register */
00394 #define FCN_IOM_IND_ADR_REG 0x0
00395 
00396 /* I/O BAR data register */
00397 #define FCN_IOM_IND_DAT_REG 0x4
00398 
00399 /* Address region register */
00400 #define FCN_ADR_REGION_REG_KER  0x00
00401 #define FCN_ADR_REGION0_LBN     0
00402 #define FCN_ADR_REGION0_WIDTH   18
00403 #define FCN_ADR_REGION1_LBN     32
00404 #define FCN_ADR_REGION1_WIDTH   18
00405 #define FCN_ADR_REGION2_LBN     64
00406 #define FCN_ADR_REGION2_WIDTH   18
00407 #define FCN_ADR_REGION3_LBN     96
00408 #define FCN_ADR_REGION3_WIDTH   18
00409 
00410 /* Interrupt enable register */
00411 #define FCN_INT_EN_REG_KER 0x0010
00412 #define FCN_MEM_PERR_INT_EN_KER_LBN 5
00413 #define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
00414 #define FCN_KER_INT_CHAR_LBN 4
00415 #define FCN_KER_INT_CHAR_WIDTH 1
00416 #define FCN_KER_INT_KER_LBN 3
00417 #define FCN_KER_INT_KER_WIDTH 1
00418 #define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
00419 #define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
00420 #define FCN_SRM_PERR_INT_EN_KER_LBN 1
00421 #define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
00422 #define FCN_DRV_INT_EN_KER_LBN 0
00423 #define FCN_DRV_INT_EN_KER_WIDTH 1
00424 
00425 /* Interrupt status register */
00426 #define FCN_INT_ADR_REG_KER     0x0030
00427 #define FCN_INT_ADR_KER_LBN 0
00428 #define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 )
00429 
00430 /* Interrupt status register (B0 only) */
00431 #define INT_ISR0_B0 0x90
00432 #define INT_ISR1_B0 0xA0
00433 
00434 /* Interrupt acknowledge register (A0/A1 only) */
00435 #define FCN_INT_ACK_KER_REG_A1 0x0050
00436 #define INT_ACK_DUMMY_DATA_LBN 0
00437 #define INT_ACK_DUMMY_DATA_WIDTH 32
00438 
00439 /* Interrupt acknowledge work-around register (A0/A1 only )*/
00440 #define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
00441 
00442 /* Hardware initialisation register */
00443 #define FCN_HW_INIT_REG_KER 0x00c0
00444 #define FCN_BCSR_TARGET_MASK_LBN 101
00445 #define FCN_BCSR_TARGET_MASK_WIDTH 4
00446 
00447 /* SPI host command register */
00448 #define FCN_EE_SPI_HCMD_REG 0x0100
00449 #define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
00450 #define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
00451 #define FCN_EE_WR_TIMER_ACTIVE_LBN 28
00452 #define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
00453 #define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
00454 #define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
00455 #define FCN_EE_SPI_EEPROM 0
00456 #define FCN_EE_SPI_FLASH 1
00457 #define FCN_EE_SPI_HCMD_DABCNT_LBN 16
00458 #define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
00459 #define FCN_EE_SPI_HCMD_READ_LBN 15
00460 #define FCN_EE_SPI_HCMD_READ_WIDTH 1
00461 #define FCN_EE_SPI_READ 1
00462 #define FCN_EE_SPI_WRITE 0
00463 #define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
00464 #define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
00465 #define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
00466 #define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
00467 #define FCN_EE_SPI_HCMD_ENC_LBN 0
00468 #define FCN_EE_SPI_HCMD_ENC_WIDTH 8
00469 
00470 /* SPI host address register */
00471 #define FCN_EE_SPI_HADR_REG 0x0110
00472 #define FCN_EE_SPI_HADR_DUBYTE_LBN 24
00473 #define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
00474 #define FCN_EE_SPI_HADR_ADR_LBN 0
00475 #define FCN_EE_SPI_HADR_ADR_WIDTH 24
00476 
00477 /* SPI host data register */
00478 #define FCN_EE_SPI_HDATA_REG 0x0120
00479 #define FCN_EE_SPI_HDATA3_LBN 96
00480 #define FCN_EE_SPI_HDATA3_WIDTH 32
00481 #define FCN_EE_SPI_HDATA2_LBN 64
00482 #define FCN_EE_SPI_HDATA2_WIDTH 32
00483 #define FCN_EE_SPI_HDATA1_LBN 32
00484 #define FCN_EE_SPI_HDATA1_WIDTH 32
00485 #define FCN_EE_SPI_HDATA0_LBN 0
00486 #define FCN_EE_SPI_HDATA0_WIDTH 32
00487 
00488 /* VPD Config 0 Register register */
00489 #define FCN_EE_VPD_CFG_REG 0x0140
00490 #define FCN_EE_VPD_EN_LBN 0
00491 #define FCN_EE_VPD_EN_WIDTH 1
00492 #define FCN_EE_VPD_EN_AD9_MODE_LBN 1
00493 #define FCN_EE_VPD_EN_AD9_MODE_WIDTH 1
00494 #define FCN_EE_EE_CLOCK_DIV_LBN 112
00495 #define FCN_EE_EE_CLOCK_DIV_WIDTH 7
00496 #define FCN_EE_SF_CLOCK_DIV_LBN 120
00497 #define FCN_EE_SF_CLOCK_DIV_WIDTH 7
00498 
00499 
00500 /* NIC status register */
00501 #define FCN_NIC_STAT_REG 0x0200
00502 #define FCN_ONCHIP_SRAM_LBN 16
00503 #define FCN_ONCHIP_SRAM_WIDTH 1
00504 #define FCN_SF_PRST_LBN 9
00505 #define FCN_SF_PRST_WIDTH 1
00506 #define FCN_EE_PRST_LBN 8
00507 #define FCN_EE_PRST_WIDTH 1
00508 #define FCN_EE_STRAP_LBN 7
00509 #define FCN_EE_STRAP_WIDTH 1
00510 #define FCN_PCI_PCIX_MODE_LBN 4
00511 #define FCN_PCI_PCIX_MODE_WIDTH 3
00512 #define FCN_PCI_PCIX_MODE_PCI33_DECODE 0
00513 #define FCN_PCI_PCIX_MODE_PCI66_DECODE 1
00514 #define FCN_PCI_PCIX_MODE_PCIX66_DECODE 5
00515 #define FCN_PCI_PCIX_MODE_PCIX100_DECODE 6
00516 #define FCN_PCI_PCIX_MODE_PCIX133_DECODE 7
00517 #define FCN_STRAP_ISCSI_EN_LBN 3
00518 #define FCN_STRAP_ISCSI_EN_WIDTH 1
00519 #define FCN_STRAP_PINS_LBN 0
00520 #define FCN_STRAP_PINS_WIDTH 3
00521 #define FCN_STRAP_10G_LBN 2
00522 #define FCN_STRAP_10G_WIDTH 1
00523 #define FCN_STRAP_DUAL_PORT_LBN 1
00524 #define FCN_STRAP_DUAL_PORT_WIDTH 1
00525 #define FCN_STRAP_PCIE_LBN 0
00526 #define FCN_STRAP_PCIE_WIDTH 1
00527 
00528 /* Falcon revisions */
00529 #define FALCON_REV_A0 0
00530 #define FALCON_REV_A1 1
00531 #define FALCON_REV_B0 2
00532 
00533 /* GPIO control register */
00534 #define FCN_GPIO_CTL_REG_KER 0x0210
00535 #define FCN_GPIO_CTL_REG_KER 0x0210
00536 
00537 #define FCN_GPIO3_OEN_LBN 27
00538 #define FCN_GPIO3_OEN_WIDTH 1
00539 #define FCN_GPIO2_OEN_LBN 26
00540 #define FCN_GPIO2_OEN_WIDTH 1
00541 #define FCN_GPIO1_OEN_LBN 25
00542 #define FCN_GPIO1_OEN_WIDTH 1
00543 #define FCN_GPIO0_OEN_LBN 24
00544 #define FCN_GPIO0_OEN_WIDTH 1
00545 
00546 #define FCN_GPIO3_OUT_LBN 19
00547 #define FCN_GPIO3_OUT_WIDTH 1
00548 #define FCN_GPIO2_OUT_LBN 18
00549 #define FCN_GPIO2_OUT_WIDTH 1
00550 #define FCN_GPIO1_OUT_LBN 17
00551 #define FCN_GPIO1_OUT_WIDTH 1
00552 #define FCN_GPIO0_OUT_LBN 16
00553 #define FCN_GPIO0_OUT_WIDTH 1
00554 
00555 #define FCN_GPIO3_IN_LBN 11
00556 #define FCN_GPIO3_IN_WIDTH 1
00557 #define FCN_GPIO2_IN_LBN 10
00558 #define FCN_GPIO2_IN_WIDTH 1
00559 #define FCN_GPIO1_IN_LBN 9
00560 #define FCN_GPIO1_IN_WIDTH 1
00561 #define FCN_GPIO0_IN_LBN 8
00562 #define FCN_GPIO0_IN_WIDTH 1
00563 
00564 #define FCN_FLASH_PRESENT_LBN 7
00565 #define FCN_FLASH_PRESENT_WIDTH 1
00566 #define FCN_EEPROM_PRESENT_LBN 6
00567 #define FCN_EEPROM_PRESENT_WIDTH 1
00568 #define FCN_BOOTED_USING_NVDEVICE_LBN 3
00569 #define FCN_BOOTED_USING_NVDEVICE_WIDTH 1
00570 
00571 /* Defines for extra non-volatile storage */
00572 #define FCN_NV_MAGIC_NUMBER 0xFA1C
00573 
00574 /* Global control register */
00575 #define FCN_GLB_CTL_REG_KER     0x0220
00576 #define FCN_EXT_PHY_RST_CTL_LBN 63
00577 #define FCN_EXT_PHY_RST_CTL_WIDTH 1
00578 #define FCN_PCIE_SD_RST_CTL_LBN 61
00579 #define FCN_PCIE_SD_RST_CTL_WIDTH 1
00580 #define FCN_PCIE_STCK_RST_CTL_LBN 59
00581 #define FCN_PCIE_STCK_RST_CTL_WIDTH 1
00582 #define FCN_PCIE_NSTCK_RST_CTL_LBN 58
00583 #define FCN_PCIE_NSTCK_RST_CTL_WIDTH 1
00584 #define FCN_PCIE_CORE_RST_CTL_LBN 57
00585 #define FCN_PCIE_CORE_RST_CTL_WIDTH 1
00586 #define FCN_EE_RST_CTL_LBN 49
00587 #define FCN_EE_RST_CTL_WIDTH 1
00588 #define FCN_RST_EXT_PHY_LBN 31
00589 #define FCN_RST_EXT_PHY_WIDTH 1
00590 #define FCN_EXT_PHY_RST_DUR_LBN 1
00591 #define FCN_EXT_PHY_RST_DUR_WIDTH 3
00592 #define FCN_SWRST_LBN 0
00593 #define FCN_SWRST_WIDTH 1
00594 #define INCLUDE_IN_RESET 0
00595 #define EXCLUDE_FROM_RESET 1
00596 
00597 /* FPGA build version */
00598 #define FCN_ALTERA_BUILD_REG_KER 0x0300
00599 #define FCN_VER_MAJOR_LBN 24
00600 #define FCN_VER_MAJOR_WIDTH 8
00601 #define FCN_VER_MINOR_LBN 16
00602 #define FCN_VER_MINOR_WIDTH 8
00603 #define FCN_VER_BUILD_LBN 0
00604 #define FCN_VER_BUILD_WIDTH 16
00605 #define FCN_VER_ALL_LBN 0
00606 #define FCN_VER_ALL_WIDTH 32
00607 
00608 /* Spare EEPROM bits register (flash 0x390) */
00609 #define FCN_SPARE_REG_KER 0x310
00610 #define FCN_MEM_PERR_EN_TX_DATA_LBN 72
00611 #define FCN_MEM_PERR_EN_TX_DATA_WIDTH 2
00612 
00613 /* Timer table for kernel access */
00614 #define FCN_TIMER_CMD_REG_KER 0x420
00615 #define FCN_TIMER_MODE_LBN 12
00616 #define FCN_TIMER_MODE_WIDTH 2
00617 #define FCN_TIMER_MODE_DIS 0
00618 #define FCN_TIMER_MODE_INT_HLDOFF 1
00619 #define FCN_TIMER_VAL_LBN 0
00620 #define FCN_TIMER_VAL_WIDTH 12
00621 
00622 /* Receive configuration register */
00623 #define FCN_RX_CFG_REG_KER 0x800
00624 #define FCN_RX_XOFF_EN_LBN 0
00625 #define FCN_RX_XOFF_EN_WIDTH 1
00626 
00627 /* SRAM receive descriptor cache configuration register */
00628 #define FCN_SRM_RX_DC_CFG_REG_KER 0x610
00629 #define FCN_SRM_RX_DC_BASE_ADR_LBN 0
00630 #define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
00631 
00632 /* SRAM transmit descriptor cache configuration register */
00633 #define FCN_SRM_TX_DC_CFG_REG_KER 0x620
00634 #define FCN_SRM_TX_DC_BASE_ADR_LBN 0
00635 #define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
00636 
00637 /* SRAM configuration register */
00638 #define FCN_SRM_CFG_REG_KER 0x630
00639 #define FCN_SRAM_OOB_ADR_INTEN_LBN 5
00640 #define FCN_SRAM_OOB_ADR_INTEN_WIDTH 1
00641 #define FCN_SRAM_OOB_BUF_INTEN_LBN 4
00642 #define FCN_SRAM_OOB_BUF_INTEN_WIDTH 1
00643 #define FCN_SRAM_OOB_BT_INIT_EN_LBN 3
00644 #define FCN_SRAM_OOB_BT_INIT_EN_WIDTH 1
00645 #define FCN_SRM_NUM_BANK_LBN 2
00646 #define FCN_SRM_NUM_BANK_WIDTH 1
00647 #define FCN_SRM_BANK_SIZE_LBN 0
00648 #define FCN_SRM_BANK_SIZE_WIDTH 2
00649 #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
00650 #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
00651 
00652 #define FCN_RX_CFG_REG_KER 0x800
00653 #define FCN_RX_INGR_EN_B0_LBN 47
00654 #define FCN_RX_INGR_EN_B0_WIDTH 1
00655 #define FCN_RX_USR_BUF_SIZE_B0_LBN 19
00656 #define FCN_RX_USR_BUF_SIZE_B0_WIDTH 9
00657 #define FCN_RX_XON_MAC_TH_B0_LBN 10
00658 #define FCN_RX_XON_MAC_TH_B0_WIDTH 9
00659 #define FCN_RX_XOFF_MAC_TH_B0_LBN 1
00660 #define FCN_RX_XOFF_MAC_TH_B0_WIDTH 9
00661 #define FCN_RX_XOFF_MAC_EN_B0_LBN 0
00662 #define FCN_RX_XOFF_MAC_EN_B0_WIDTH 1
00663 #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
00664 #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
00665 #define FCN_RX_XON_MAC_TH_A1_LBN 6
00666 #define FCN_RX_XON_MAC_TH_A1_WIDTH 5
00667 #define FCN_RX_XOFF_MAC_TH_A1_LBN 1
00668 #define FCN_RX_XOFF_MAC_TH_A1_WIDTH 5
00669 #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
00670 #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
00671 
00672 #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
00673 #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
00674 #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
00675 #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
00676 
00677 /* Receive filter control register */
00678 #define FCN_RX_FILTER_CTL_REG_KER 0x810
00679 #define FCN_UDP_FULL_SRCH_LIMIT_LBN 32
00680 #define FCN_UDP_FULL_SRCH_LIMIT_WIDTH 8
00681 #define FCN_NUM_KER_LBN 24
00682 #define FCN_NUM_KER_WIDTH 2
00683 #define FCN_UDP_WILD_SRCH_LIMIT_LBN 16
00684 #define FCN_UDP_WILD_SRCH_LIMIT_WIDTH 8
00685 #define FCN_TCP_WILD_SRCH_LIMIT_LBN 8
00686 #define FCN_TCP_WILD_SRCH_LIMIT_WIDTH 8
00687 #define FCN_TCP_FULL_SRCH_LIMIT_LBN 0
00688 #define FCN_TCP_FULL_SRCH_LIMIT_WIDTH 8
00689 
00690 /* RX queue flush register */
00691 #define FCN_RX_FLUSH_DESCQ_REG_KER 0x0820
00692 #define FCN_RX_FLUSH_DESCQ_CMD_LBN 24
00693 #define FCN_RX_FLUSH_DESCQ_CMD_WIDTH 1
00694 #define FCN_RX_FLUSH_DESCQ_LBN 0
00695 #define FCN_RX_FLUSH_DESCQ_WIDTH 12
00696 
00697 /* Receive descriptor update register */
00698 #define FCN_RX_DESC_UPD_REG_KER 0x0830
00699 #define FCN_RX_DESC_WPTR_LBN 96
00700 #define FCN_RX_DESC_WPTR_WIDTH 12
00701 #define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 )
00702 #define FCN_RX_DESC_WPTR_DWORD_LBN 0
00703 #define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
00704 
00705 /* Receive descriptor cache configuration register */
00706 #define FCN_RX_DC_CFG_REG_KER 0x840
00707 #define FCN_RX_DC_SIZE_LBN 0
00708 #define FCN_RX_DC_SIZE_WIDTH 2
00709 
00710 #define FCN_RX_SELF_RST_REG_KER 0x890
00711 #define FCN_RX_ISCSI_DIS_LBN 17
00712 #define FCN_RX_ISCSI_DIS_WIDTH 1
00713 #define FCN_RX_NODESC_WAIT_DIS_LBN 9
00714 #define FCN_RX_NODESC_WAIT_DIS_WIDTH 1
00715 #define FCN_RX_RECOVERY_EN_LBN 8
00716 #define FCN_RX_RECOVERY_EN_WIDTH 1
00717 
00718 /* TX queue flush register */
00719 #define FCN_TX_FLUSH_DESCQ_REG_KER 0x0a00
00720 #define FCN_TX_FLUSH_DESCQ_CMD_LBN 12
00721 #define FCN_TX_FLUSH_DESCQ_CMD_WIDTH 1
00722 #define FCN_TX_FLUSH_DESCQ_LBN 0
00723 #define FCN_TX_FLUSH_DESCQ_WIDTH 12
00724 
00725 /* Transmit configuration register 2 */
00726 #define FCN_TX_CFG2_REG_KER 0xa80
00727 #define FCN_TX_DIS_NON_IP_EV_LBN 17
00728 #define FCN_TX_DIS_NON_IP_EV_WIDTH 1
00729 
00730 /* Transmit descriptor update register */
00731 #define FCN_TX_DESC_UPD_REG_KER 0x0a10
00732 #define FCN_TX_DESC_WPTR_LBN 96
00733 #define FCN_TX_DESC_WPTR_WIDTH 12
00734 #define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 )
00735 #define FCN_TX_DESC_WPTR_DWORD_LBN 0
00736 #define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
00737 
00738 /* Transmit descriptor cache configuration register */
00739 #define FCN_TX_DC_CFG_REG_KER 0xa20
00740 #define FCN_TX_DC_SIZE_LBN 0
00741 #define FCN_TX_DC_SIZE_WIDTH 2
00742 
00743 /* PHY management transmit data register */
00744 #define FCN_MD_TXD_REG_KER 0xc00
00745 #define FCN_MD_TXD_LBN 0
00746 #define FCN_MD_TXD_WIDTH 16
00747 
00748 /* PHY management receive data register */
00749 #define FCN_MD_RXD_REG_KER 0xc10
00750 #define FCN_MD_RXD_LBN 0
00751 #define FCN_MD_RXD_WIDTH 16
00752 
00753 /* PHY management configuration & status register */
00754 #define FCN_MD_CS_REG_KER 0xc20
00755 #define FCN_MD_GC_LBN 4
00756 #define FCN_MD_GC_WIDTH 1
00757 #define FCN_MD_RIC_LBN 2
00758 #define FCN_MD_RIC_WIDTH 1
00759 #define FCN_MD_RDC_LBN 1
00760 #define FCN_MD_RDC_WIDTH 1
00761 #define FCN_MD_WRC_LBN 0
00762 #define FCN_MD_WRC_WIDTH 1
00763 
00764 /* PHY management PHY address register */
00765 #define FCN_MD_PHY_ADR_REG_KER 0xc30
00766 #define FCN_MD_PHY_ADR_LBN 0
00767 #define FCN_MD_PHY_ADR_WIDTH 16
00768 
00769 /* PHY management ID register */
00770 #define FCN_MD_ID_REG_KER 0xc40
00771 #define FCN_MD_PRT_ADR_LBN 11
00772 #define FCN_MD_PRT_ADR_WIDTH 5
00773 #define FCN_MD_DEV_ADR_LBN 6
00774 #define FCN_MD_DEV_ADR_WIDTH 5
00775 
00776 /* PHY management status & mask register */
00777 #define FCN_MD_STAT_REG_KER 0xc50
00778 #define FCN_MD_PINT_LBN 4
00779 #define FCN_MD_PINT_WIDTH 1
00780 #define FCN_MD_DONE_LBN 3
00781 #define FCN_MD_DONE_WIDTH 1
00782 #define FCN_MD_BSERR_LBN 2
00783 #define FCN_MD_BSERR_WIDTH 1
00784 #define FCN_MD_LNFL_LBN 1
00785 #define FCN_MD_LNFL_WIDTH 1
00786 #define FCN_MD_BSY_LBN 0
00787 #define FCN_MD_BSY_WIDTH 1
00788 
00789 /* Port 0 and 1 MAC control registers */
00790 #define FCN_MAC0_CTRL_REG_KER 0xc80
00791 #define FCN_MAC1_CTRL_REG_KER 0xc90
00792 #define FCN_MAC_XOFF_VAL_LBN 16
00793 #define FCN_MAC_XOFF_VAL_WIDTH 16
00794 #define FCN_MAC_BCAD_ACPT_LBN 4
00795 #define FCN_MAC_BCAD_ACPT_WIDTH 1
00796 #define FCN_MAC_UC_PROM_LBN 3
00797 #define FCN_MAC_UC_PROM_WIDTH 1
00798 #define FCN_MAC_LINK_STATUS_LBN 2
00799 #define FCN_MAC_LINK_STATUS_WIDTH 1
00800 #define FCN_MAC_SPEED_LBN 0
00801 #define FCN_MAC_SPEED_WIDTH 2
00802 
00803 /* 10Gig Xaui XGXS Default Values  */
00804 #define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
00805 #define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
00806 #define XX_SD_CTL_DRV_DEFAULT 0  /* 20mA */
00807 
00808 /* GMAC registers */
00809 #define FALCON_GMAC_REGBANK 0xe00
00810 #define FALCON_GMAC_REGBANK_SIZE 0x200
00811 #define FALCON_GMAC_REG_SIZE 0x10
00812 
00813 /* XGMAC registers */
00814 #define FALCON_XMAC_REGBANK 0x1200
00815 #define FALCON_XMAC_REGBANK_SIZE 0x200
00816 #define FALCON_XMAC_REG_SIZE 0x10
00817 
00818 /* XGMAC address register low */
00819 #define FCN_XM_ADR_LO_REG_MAC 0x00
00820 #define FCN_XM_ADR_3_LBN 24
00821 #define FCN_XM_ADR_3_WIDTH 8
00822 #define FCN_XM_ADR_2_LBN 16
00823 #define FCN_XM_ADR_2_WIDTH 8
00824 #define FCN_XM_ADR_1_LBN 8
00825 #define FCN_XM_ADR_1_WIDTH 8
00826 #define FCN_XM_ADR_0_LBN 0
00827 #define FCN_XM_ADR_0_WIDTH 8
00828 
00829 /* XGMAC address register high */
00830 #define FCN_XM_ADR_HI_REG_MAC 0x01
00831 #define FCN_XM_ADR_5_LBN 8
00832 #define FCN_XM_ADR_5_WIDTH 8
00833 #define FCN_XM_ADR_4_LBN 0
00834 #define FCN_XM_ADR_4_WIDTH 8
00835 
00836 /* XGMAC global configuration - port 0*/
00837 #define FCN_XM_GLB_CFG_REG_MAC 0x02
00838 #define FCN_XM_RX_STAT_EN_LBN 11
00839 #define FCN_XM_RX_STAT_EN_WIDTH 1
00840 #define FCN_XM_TX_STAT_EN_LBN 10
00841 #define FCN_XM_TX_STAT_EN_WIDTH 1
00842 #define FCN_XM_RX_JUMBO_MODE_LBN 6
00843 #define FCN_XM_RX_JUMBO_MODE_WIDTH 1
00844 #define FCN_XM_CORE_RST_LBN 0
00845 #define FCN_XM_CORE_RST_WIDTH 1
00846 
00847 /* XGMAC transmit configuration - port 0 */
00848 #define FCN_XM_TX_CFG_REG_MAC 0x03
00849 #define FCN_XM_IPG_LBN 16
00850 #define FCN_XM_IPG_WIDTH 4
00851 #define FCN_XM_FCNTL_LBN 10
00852 #define FCN_XM_FCNTL_WIDTH 1
00853 #define FCN_XM_TXCRC_LBN 8
00854 #define FCN_XM_TXCRC_WIDTH 1
00855 #define FCN_XM_AUTO_PAD_LBN 5
00856 #define FCN_XM_AUTO_PAD_WIDTH 1
00857 #define FCN_XM_TX_PRMBL_LBN 2
00858 #define FCN_XM_TX_PRMBL_WIDTH 1
00859 #define FCN_XM_TXEN_LBN 1
00860 #define FCN_XM_TXEN_WIDTH 1
00861 
00862 /* XGMAC receive configuration - port 0 */
00863 #define FCN_XM_RX_CFG_REG_MAC 0x04
00864 #define FCN_XM_PASS_CRC_ERR_LBN 25
00865 #define FCN_XM_PASS_CRC_ERR_WIDTH 1
00866 #define FCN_XM_AUTO_DEPAD_LBN 8
00867 #define FCN_XM_AUTO_DEPAD_WIDTH 1
00868 #define FCN_XM_RXEN_LBN 1
00869 #define FCN_XM_RXEN_WIDTH 1
00870 
00871 /* XGMAC management interrupt mask register */
00872 #define FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5
00873 #define FCN_XM_MSK_PRMBLE_ERR_LBN 2
00874 #define FCN_XM_MSK_PRMBLE_ERR_WIDTH 1
00875 #define FCN_XM_MSK_RMTFLT_LBN 1
00876 #define FCN_XM_MSK_RMTFLT_WIDTH 1
00877 #define FCN_XM_MSK_LCLFLT_LBN 0
00878 #define FCN_XM_MSK_LCLFLT_WIDTH 1
00879 
00880 /* XGMAC flow control register */
00881 #define FCN_XM_FC_REG_MAC 0x7
00882 #define FCN_XM_PAUSE_TIME_LBN 16
00883 #define FCN_XM_PAUSE_TIME_WIDTH 16
00884 #define FCN_XM_DIS_FCNTL_LBN 0
00885 #define FCN_XM_DIS_FCNTL_WIDTH 1
00886 
00887 /* XGMAC transmit parameter register */
00888 #define FCN_XM_TX_PARAM_REG_MAC 0x0d
00889 #define FCN_XM_TX_JUMBO_MODE_LBN 31
00890 #define FCN_XM_TX_JUMBO_MODE_WIDTH 1
00891 #define FCN_XM_MAX_TX_FRM_SIZE_LBN 16
00892 #define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14
00893 #define FCN_XM_ACPT_ALL_MCAST_LBN 11
00894 #define FCN_XM_ACPT_ALL_MCAST_WIDTH 1
00895 
00896 /* XGMAC receive parameter register */
00897 #define FCN_XM_RX_PARAM_REG_MAC 0x0e
00898 #define FCN_XM_MAX_RX_FRM_SIZE_LBN 0
00899 #define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14
00900 
00901 /* XGMAC management interrupt status register */
00902 #define FCN_XM_MGT_INT_REG_MAC_B0 0x0f
00903 #define FCN_XM_PRMBLE_ERR 2
00904 #define FCN_XM_PRMBLE_WIDTH 1
00905 #define FCN_XM_RMTFLT_LBN 1
00906 #define FCN_XM_RMTFLT_WIDTH 1
00907 #define FCN_XM_LCLFLT_LBN 0
00908 #define FCN_XM_LCLFLT_WIDTH 1
00909 
00910 /* XAUI XGXS core status register */
00911 #define FCN_XX_ALIGN_DONE_LBN 20
00912 #define FCN_XX_ALIGN_DONE_WIDTH 1
00913 #define FCN_XX_CORE_STAT_REG_MAC 0x16
00914 #define FCN_XX_SYNC_STAT_LBN 16
00915 #define FCN_XX_SYNC_STAT_WIDTH 4
00916 #define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf
00917 #define FCN_XX_COMMA_DET_LBN 12
00918 #define FCN_XX_COMMA_DET_WIDTH 4
00919 #define FCN_XX_COMMA_DET_RESET 0xf
00920 #define FCN_XX_CHARERR_LBN 4
00921 #define FCN_XX_CHARERR_WIDTH 4
00922 #define FCN_XX_CHARERR_RESET 0xf
00923 #define FCN_XX_DISPERR_LBN 0
00924 #define FCN_XX_DISPERR_WIDTH 4
00925 #define FCN_XX_DISPERR_RESET 0xf
00926 
00927 /* XGXS/XAUI powerdown/reset register */
00928 #define FCN_XX_PWR_RST_REG_MAC 0x10
00929 #define FCN_XX_PWRDND_EN_LBN 15
00930 #define FCN_XX_PWRDND_EN_WIDTH 1
00931 #define FCN_XX_PWRDNC_EN_LBN 14
00932 #define FCN_XX_PWRDNC_EN_WIDTH 1
00933 #define FCN_XX_PWRDNB_EN_LBN 13
00934 #define FCN_XX_PWRDNB_EN_WIDTH 1
00935 #define FCN_XX_PWRDNA_EN_LBN 12
00936 #define FCN_XX_PWRDNA_EN_WIDTH 1
00937 #define FCN_XX_RSTPLLCD_EN_LBN 9
00938 #define FCN_XX_RSTPLLCD_EN_WIDTH 1
00939 #define FCN_XX_RSTPLLAB_EN_LBN 8
00940 #define FCN_XX_RSTPLLAB_EN_WIDTH 1
00941 #define FCN_XX_RESETD_EN_LBN 7
00942 #define FCN_XX_RESETD_EN_WIDTH 1
00943 #define FCN_XX_RESETC_EN_LBN 6
00944 #define FCN_XX_RESETC_EN_WIDTH 1
00945 #define FCN_XX_RESETB_EN_LBN 5
00946 #define FCN_XX_RESETB_EN_WIDTH 1
00947 #define FCN_XX_RESETA_EN_LBN 4
00948 #define FCN_XX_RESETA_EN_WIDTH 1
00949 #define FCN_XX_RSTXGXSRX_EN_LBN 2
00950 #define FCN_XX_RSTXGXSRX_EN_WIDTH 1
00951 #define FCN_XX_RSTXGXSTX_EN_LBN 1
00952 #define FCN_XX_RSTXGXSTX_EN_WIDTH 1
00953 #define FCN_XX_RST_XX_EN_LBN 0
00954 #define FCN_XX_RST_XX_EN_WIDTH 1
00955 
00956 
00957 /* XGXS/XAUI powerdown/reset control register */
00958 #define FCN_XX_SD_CTL_REG_MAC 0x11
00959 #define FCN_XX_TERMADJ1_LBN 17
00960 #define FCN_XX_TERMADJ1_WIDTH 1
00961 #define FCN_XX_TERMADJ0_LBN 16
00962 #define FCN_XX_TERMADJ0_WIDTH 1
00963 #define FCN_XX_HIDRVD_LBN 15
00964 #define FCN_XX_HIDRVD_WIDTH 1
00965 #define FCN_XX_LODRVD_LBN 14
00966 #define FCN_XX_LODRVD_WIDTH 1
00967 #define FCN_XX_HIDRVC_LBN 13
00968 #define FCN_XX_HIDRVC_WIDTH 1
00969 #define FCN_XX_LODRVC_LBN 12
00970 #define FCN_XX_LODRVC_WIDTH 1
00971 #define FCN_XX_HIDRVB_LBN 11
00972 #define FCN_XX_HIDRVB_WIDTH 1
00973 #define FCN_XX_LODRVB_LBN 10
00974 #define FCN_XX_LODRVB_WIDTH 1
00975 #define FCN_XX_HIDRVA_LBN 9
00976 #define FCN_XX_HIDRVA_WIDTH 1
00977 #define FCN_XX_LODRVA_LBN 8
00978 #define FCN_XX_LODRVA_WIDTH 1
00979 #define FCN_XX_LPBKD_LBN 3
00980 #define FCN_XX_LPBKD_WIDTH 1
00981 #define FCN_XX_LPBKC_LBN 2
00982 #define FCN_XX_LPBKC_WIDTH 1
00983 #define FCN_XX_LPBKB_LBN 1
00984 #define FCN_XX_LPBKB_WIDTH 1
00985 #define FCN_XX_LPBKA_LBN 0
00986 #define FCN_XX_LPBKA_WIDTH 1
00987 
00988 #define FCN_XX_TXDRV_CTL_REG_MAC 0x12
00989 #define FCN_XX_DEQD_LBN 28
00990 #define FCN_XX_DEQD_WIDTH 4
00991 #define FCN_XX_DEQC_LBN 24
00992 #define FCN_XX_DEQC_WIDTH 4
00993 #define FCN_XX_DEQB_LBN 20
00994 #define FCN_XX_DEQB_WIDTH 4
00995 #define FCN_XX_DEQA_LBN 16
00996 #define FCN_XX_DEQA_WIDTH 4
00997 #define FCN_XX_DTXD_LBN 12
00998 #define FCN_XX_DTXD_WIDTH 4
00999 #define FCN_XX_DTXC_LBN 8
01000 #define FCN_XX_DTXC_WIDTH 4
01001 #define FCN_XX_DTXB_LBN 4
01002 #define FCN_XX_DTXB_WIDTH 4
01003 #define FCN_XX_DTXA_LBN 0
01004 #define FCN_XX_DTXA_WIDTH 4
01005 
01006 /* Receive filter table */
01007 #define FCN_RX_FILTER_TBL0 0xF00000 
01008 
01009 /* Receive descriptor pointer table */
01010 #define FCN_RX_DESC_PTR_TBL_KER_A1 0x11800
01011 #define FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000
01012 #define FCN_RX_ISCSI_DDIG_EN_LBN 88
01013 #define FCN_RX_ISCSI_DDIG_EN_WIDTH 1
01014 #define FCN_RX_ISCSI_HDIG_EN_LBN 87
01015 #define FCN_RX_ISCSI_HDIG_EN_WIDTH 1
01016 #define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
01017 #define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
01018 #define FCN_RX_DESCQ_EVQ_ID_LBN 24
01019 #define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
01020 #define FCN_RX_DESCQ_OWNER_ID_LBN 10
01021 #define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
01022 #define FCN_RX_DESCQ_SIZE_LBN 3
01023 #define FCN_RX_DESCQ_SIZE_WIDTH 2
01024 #define FCN_RX_DESCQ_SIZE_4K 3
01025 #define FCN_RX_DESCQ_SIZE_2K 2
01026 #define FCN_RX_DESCQ_SIZE_1K 1
01027 #define FCN_RX_DESCQ_SIZE_512 0
01028 #define FCN_RX_DESCQ_TYPE_LBN 2
01029 #define FCN_RX_DESCQ_TYPE_WIDTH 1
01030 #define FCN_RX_DESCQ_JUMBO_LBN 1
01031 #define FCN_RX_DESCQ_JUMBO_WIDTH 1
01032 #define FCN_RX_DESCQ_EN_LBN 0
01033 #define FCN_RX_DESCQ_EN_WIDTH 1
01034 
01035 /* Transmit descriptor pointer table */
01036 #define FCN_TX_DESC_PTR_TBL_KER_A1 0x11900
01037 #define FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000
01038 #define FCN_TX_NON_IP_DROP_DIS_B0_LBN 91
01039 #define FCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1
01040 #define FCN_TX_DESCQ_EN_LBN 88
01041 #define FCN_TX_DESCQ_EN_WIDTH 1
01042 #define FCN_TX_ISCSI_DDIG_EN_LBN 87
01043 #define FCN_TX_ISCSI_DDIG_EN_WIDTH 1
01044 #define FCN_TX_ISCSI_HDIG_EN_LBN 86
01045 #define FCN_TX_ISCSI_HDIG_EN_WIDTH 1
01046 #define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
01047 #define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
01048 #define FCN_TX_DESCQ_EVQ_ID_LBN 24
01049 #define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
01050 #define FCN_TX_DESCQ_OWNER_ID_LBN 10
01051 #define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
01052 #define FCN_TX_DESCQ_SIZE_LBN 3
01053 #define FCN_TX_DESCQ_SIZE_WIDTH 2
01054 #define FCN_TX_DESCQ_SIZE_4K 3
01055 #define FCN_TX_DESCQ_SIZE_2K 2
01056 #define FCN_TX_DESCQ_SIZE_1K 1
01057 #define FCN_TX_DESCQ_SIZE_512 0
01058 #define FCN_TX_DESCQ_TYPE_LBN 1
01059 #define FCN_TX_DESCQ_TYPE_WIDTH 2
01060 #define FCN_TX_DESCQ_FLUSH_LBN 0
01061 #define FCN_TX_DESCQ_FLUSH_WIDTH 1
01062 
01063 /* Event queue pointer */
01064 #define FCN_EVQ_PTR_TBL_KER_A1 0x11a00
01065 #define FCN_EVQ_PTR_TBL_KER_B0 0xf60000
01066 #define FCN_EVQ_EN_LBN 23
01067 #define FCN_EVQ_EN_WIDTH 1
01068 #define FCN_EVQ_SIZE_LBN 20
01069 #define FCN_EVQ_SIZE_WIDTH 3
01070 #define FCN_EVQ_SIZE_32K 6
01071 #define FCN_EVQ_SIZE_16K 5
01072 #define FCN_EVQ_SIZE_8K 4
01073 #define FCN_EVQ_SIZE_4K 3
01074 #define FCN_EVQ_SIZE_2K 2
01075 #define FCN_EVQ_SIZE_1K 1
01076 #define FCN_EVQ_SIZE_512 0
01077 #define FCN_EVQ_BUF_BASE_ID_LBN 0
01078 #define FCN_EVQ_BUF_BASE_ID_WIDTH 20
01079 
01080 /* RSS indirection table */
01081 #define FCN_RX_RSS_INDIR_TBL_B0 0xFB0000
01082 
01083 /* Event queue read pointer */
01084 #define FCN_EVQ_RPTR_REG_KER_A1 0x11b00
01085 #define FCN_EVQ_RPTR_REG_KER_B0 0xfa0000
01086 #define FCN_EVQ_RPTR_LBN 0
01087 #define FCN_EVQ_RPTR_WIDTH 14
01088 #define FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 )
01089 #define FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 )
01090 #define FCN_EVQ_RPTR_DWORD_LBN 0
01091 #define FCN_EVQ_RPTR_DWORD_WIDTH 14
01092 
01093 /* Special buffer descriptors */
01094 #define FCN_BUF_FULL_TBL_KER_A1 0x18000
01095 #define FCN_BUF_FULL_TBL_KER_B0 0x800000
01096 #define FCN_IP_DAT_BUF_SIZE_LBN 50
01097 #define FCN_IP_DAT_BUF_SIZE_WIDTH 1
01098 #define FCN_IP_DAT_BUF_SIZE_8K 1
01099 #define FCN_IP_DAT_BUF_SIZE_4K 0
01100 #define FCN_BUF_ADR_FBUF_LBN 14
01101 #define FCN_BUF_ADR_FBUF_WIDTH 34
01102 #define FCN_BUF_OWNER_ID_FBUF_LBN 0
01103 #define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
01104 
01105 /** Offset of a GMAC register within Falcon */
01106 #define FALCON_GMAC_REG( efab, mac_reg )                                \
01107         ( FALCON_GMAC_REGBANK +                                 \
01108           ( (mac_reg) * FALCON_GMAC_REG_SIZE ) )
01109 
01110 /** Offset of an XMAC register within Falcon */
01111 #define FALCON_XMAC_REG( efab_port, mac_reg )                   \
01112         ( FALCON_XMAC_REGBANK +                                 \
01113           ( (mac_reg) * FALCON_XMAC_REG_SIZE ) )
01114 
01115 #define FCN_MAC_DATA_LBN 0
01116 #define FCN_MAC_DATA_WIDTH 32
01117 
01118 /* Transmit descriptor */
01119 #define FCN_TX_KER_PORT_LBN 63
01120 #define FCN_TX_KER_PORT_WIDTH 1
01121 #define FCN_TX_KER_BYTE_CNT_LBN 48
01122 #define FCN_TX_KER_BYTE_CNT_WIDTH 14
01123 #define FCN_TX_KER_BUF_ADR_LBN 0
01124 #define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
01125 
01126 
01127 /* Receive descriptor */
01128 #define FCN_RX_KER_BUF_SIZE_LBN 48
01129 #define FCN_RX_KER_BUF_SIZE_WIDTH 14
01130 #define FCN_RX_KER_BUF_ADR_LBN 0
01131 #define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
01132 
01133 /* Event queue entries */
01134 #define FCN_EV_CODE_LBN 60
01135 #define FCN_EV_CODE_WIDTH 4
01136 #define FCN_RX_IP_EV_DECODE 0
01137 #define FCN_TX_IP_EV_DECODE 2
01138 #define FCN_DRIVER_EV_DECODE 5
01139 
01140 /* Receive events */
01141 #define FCN_RX_EV_PKT_OK_LBN 56
01142 #define FCN_RX_EV_PKT_OK_WIDTH 1
01143 #define FCN_RX_PORT_LBN 30
01144 #define FCN_RX_PORT_WIDTH 1
01145 #define FCN_RX_EV_BYTE_CNT_LBN 16
01146 #define FCN_RX_EV_BYTE_CNT_WIDTH 14
01147 #define FCN_RX_EV_DESC_PTR_LBN 0
01148 #define FCN_RX_EV_DESC_PTR_WIDTH 12
01149 
01150 /* Transmit events */
01151 #define FCN_TX_EV_DESC_PTR_LBN 0
01152 #define FCN_TX_EV_DESC_PTR_WIDTH 12
01153 
01154 /*******************************************************************************
01155  *
01156  *
01157  * Low-level hardware access
01158  *
01159  *
01160  *******************************************************************************/ 
01161 
01162 #define FCN_REVISION_REG(efab, reg) \
01163         ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 )
01164 
01165 #define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val)                 \
01166         if ( efab->pci_revision == FALCON_REV_B0 )                      \
01167                 EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val );        \
01168         else                                                            \
01169                 EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val );
01170 
01171 #if FALCON_USE_IO_BAR
01172 
01173 /* Write dword via the I/O BAR */
01174 static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value,
01175                                     unsigned int reg ) {
01176         outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
01177         outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG );
01178 }
01179 
01180 /* Read dword via the I/O BAR */
01181 static inline uint32_t _falcon_readl ( struct efab_nic *efab,
01182                                        unsigned int reg ) {
01183         outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
01184         return inl ( efab->iobase + FCN_IOM_IND_DAT_REG );
01185 }
01186 
01187 #else /* FALCON_USE_IO_BAR */
01188 
01189 #define _falcon_writel( efab, value, reg ) \
01190         writel ( (value), (efab)->membase + (reg) )
01191 #define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) )
01192 
01193 #endif /* FALCON_USE_IO_BAR */
01194 
01195 /**
01196  * Write to a Falcon register
01197  *
01198  */
01199 static inline void
01200 falcon_write ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
01201 {
01202 
01203         EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n",
01204                        reg, EFAB_OWORD_VAL ( *value ) );
01205 
01206         _falcon_writel ( efab, value->u32[0], reg + 0  );
01207         _falcon_writel ( efab, value->u32[1], reg + 4  );
01208         _falcon_writel ( efab, value->u32[2], reg + 8  );
01209         wmb();
01210         _falcon_writel ( efab, value->u32[3], reg + 12 );
01211         wmb();
01212 }
01213 
01214 /**
01215  * Write to Falcon SRAM
01216  *
01217  */
01218 static inline void
01219 falcon_write_sram ( struct efab_nic *efab, efab_qword_t *value,
01220                     unsigned int index )
01221 {
01222         unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
01223                              ( index * sizeof ( *value ) ) );
01224 
01225         EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n",
01226                        reg, EFAB_QWORD_VAL ( *value ) );
01227 
01228         _falcon_writel ( efab, value->u32[0], reg + 0  );
01229         _falcon_writel ( efab, value->u32[1], reg + 4  );
01230         wmb();
01231 }
01232 
01233 /**
01234  * Write dword to Falcon register that allows partial writes
01235  *
01236  */
01237 static inline void
01238 falcon_writel ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
01239 {
01240         EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n",
01241                        reg, EFAB_DWORD_VAL ( *value ) );
01242         _falcon_writel ( efab, value->u32[0], reg );
01243 }
01244 
01245 /**
01246  * Read from a Falcon register
01247  *
01248  */
01249 static inline void
01250 falcon_read ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
01251 {
01252         value->u32[0] = _falcon_readl ( efab, reg + 0  );
01253         wmb();
01254         value->u32[1] = _falcon_readl ( efab, reg + 4  );
01255         value->u32[2] = _falcon_readl ( efab, reg + 8  );
01256         value->u32[3] = _falcon_readl ( efab, reg + 12 );
01257 
01258         EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n",
01259                        reg, EFAB_OWORD_VAL ( *value ) );
01260 }
01261 
01262 /** 
01263  * Read from Falcon SRAM
01264  *
01265  */
01266 static inline void
01267 falcon_read_sram ( struct efab_nic *efab, efab_qword_t *value,
01268                    unsigned int index )
01269 {
01270         unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
01271                              ( index * sizeof ( *value ) ) );
01272 
01273         value->u32[0] = _falcon_readl ( efab, reg + 0 );
01274         value->u32[1] = _falcon_readl ( efab, reg + 4 );
01275         EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n",
01276                        reg, EFAB_QWORD_VAL ( *value ) );
01277 }
01278 
01279 /**
01280  * Read dword from a portion of a Falcon register
01281  *
01282  */
01283 static inline void
01284 falcon_readl ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
01285 {
01286         value->u32[0] = _falcon_readl ( efab, reg );
01287         EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
01288                        reg, EFAB_DWORD_VAL ( *value ) );
01289 }
01290 
01291 #define FCN_DUMP_REG( efab, _reg ) do {                         \
01292                 efab_oword_t reg;                               \
01293                 falcon_read ( efab, &reg, _reg );               \
01294                 EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n",     \
01295                            EFAB_OWORD_VAL ( reg ) );            \
01296         } while ( 0 );
01297 
01298 #define FCN_DUMP_MAC_REG( efab, _mac_reg ) do {                         \
01299                 efab_dword_t reg;                                       \
01300                 efab->mac_op->mac_readl ( efab, &reg, _mac_reg );       \
01301                 EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n",         \
01302                            EFAB_DWORD_VAL ( reg ) );                    \
01303         } while ( 0 );
01304 
01305 /**
01306  * See if an event is present
01307  *
01308  * @v event             Falcon event structure
01309  * @ret True            An event is pending
01310  * @ret False           No event is pending
01311  *
01312  * We check both the high and low dword of the event for all ones.  We
01313  * wrote all ones when we cleared the event, and no valid event can
01314  * have all ones in either its high or low dwords.  This approach is
01315  * robust against reordering.
01316  *
01317  * Note that using a single 64-bit comparison is incorrect; even
01318  * though the CPU read will be atomic, the DMA write may not be.
01319  */
01320 static inline int
01321 falcon_event_present ( falcon_event_t* event )
01322 {
01323         return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) |
01324                      EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) );
01325 }
01326 
01327 static void
01328 falcon_eventq_read_ack ( struct efab_nic *efab, struct efab_ev_queue *ev_queue )
01329 {
01330         efab_dword_t reg;
01331 
01332         EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD, ev_queue->read_ptr );
01333         falcon_writel ( efab, &reg,
01334                         FCN_REVISION_REG ( efab, FCN_EVQ_RPTR_REG_KER_DWORD ) );
01335 }
01336 
01337 #if 0
01338 /**
01339  * Dump register contents (for debugging)
01340  *
01341  * Marked as static inline so that it will not be compiled in if not
01342  * used.
01343  */
01344 static inline void
01345 falcon_dump_regs ( struct efab_nic *efab )
01346 {
01347         FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER );
01348         FCN_DUMP_REG ( efab, FCN_INT_ADR_REG_KER );
01349         FCN_DUMP_REG ( efab, FCN_GLB_CTL_REG_KER );
01350         FCN_DUMP_REG ( efab, FCN_TIMER_CMD_REG_KER );
01351         FCN_DUMP_REG ( efab, FCN_SRM_RX_DC_CFG_REG_KER );
01352         FCN_DUMP_REG ( efab, FCN_SRM_TX_DC_CFG_REG_KER );
01353         FCN_DUMP_REG ( efab, FCN_RX_FILTER_CTL_REG_KER );
01354         FCN_DUMP_REG ( efab, FCN_RX_DC_CFG_REG_KER );
01355         FCN_DUMP_REG ( efab, FCN_TX_DC_CFG_REG_KER );
01356         FCN_DUMP_REG ( efab, FCN_MAC0_CTRL_REG_KER );
01357         FCN_DUMP_REG ( efab, FCN_MAC1_CTRL_REG_KER );
01358         FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
01359         FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
01360         FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
01361         FCN_DUMP_MAC_REG ( efab, GM_CFG1_REG_MAC );
01362         FCN_DUMP_MAC_REG ( efab, GM_CFG2_REG_MAC );
01363         FCN_DUMP_MAC_REG ( efab, GM_MAX_FLEN_REG_MAC );
01364         FCN_DUMP_MAC_REG ( efab, GM_MII_MGMT_CFG_REG_MAC );
01365         FCN_DUMP_MAC_REG ( efab, GM_ADR1_REG_MAC );
01366         FCN_DUMP_MAC_REG ( efab, GM_ADR2_REG_MAC );
01367         FCN_DUMP_MAC_REG ( efab, GMF_CFG0_REG_MAC );
01368         FCN_DUMP_MAC_REG ( efab, GMF_CFG1_REG_MAC );
01369         FCN_DUMP_MAC_REG ( efab, GMF_CFG2_REG_MAC );
01370         FCN_DUMP_MAC_REG ( efab, GMF_CFG3_REG_MAC );
01371         FCN_DUMP_MAC_REG ( efab, GMF_CFG4_REG_MAC );
01372         FCN_DUMP_MAC_REG ( efab, GMF_CFG5_REG_MAC );
01373 }
01374 #endif
01375 
01376 static void
01377 falcon_interrupts ( struct efab_nic *efab, int enabled, int force )
01378 {
01379         efab_oword_t int_en_reg_ker;
01380 
01381         EFAB_POPULATE_OWORD_2 ( int_en_reg_ker,
01382                                 FCN_KER_INT_KER, force,
01383                                 FCN_DRV_INT_EN_KER, enabled );
01384         falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER );     
01385 }
01386 
01387 /*******************************************************************************
01388  *
01389  *
01390  * SPI access
01391  *
01392  *
01393  *******************************************************************************/ 
01394 
01395 
01396 /** Maximum length for a single SPI transaction */
01397 #define FALCON_SPI_MAX_LEN 16
01398 
01399 static int
01400 falcon_spi_wait ( struct efab_nic *efab )
01401 {
01402         efab_oword_t reg;
01403         int count;
01404 
01405         count = 0;
01406         do {
01407                 udelay ( 100 );
01408                 falcon_read ( efab, &reg, FCN_EE_SPI_HCMD_REG );
01409                 if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 )
01410                         return 0;
01411         } while ( ++count < 1000 );
01412 
01413         EFAB_ERR ( "Timed out waiting for SPI\n" );
01414         return -ETIMEDOUT;
01415 }
01416 
01417 static int
01418 falcon_spi_rw ( struct spi_bus* bus, struct spi_device *device,
01419                 unsigned int command, int address,
01420                 const void* data_out, void *data_in, size_t len )
01421 {
01422         struct efab_nic *efab = container_of ( bus, struct efab_nic, spi_bus );
01423         int address_len, rc, device_id, read_cmd;
01424         efab_oword_t reg;
01425 
01426         /* falcon_init_spi_device() should have reduced the block size
01427          * down so this constraint holds */
01428         assert ( len <= FALCON_SPI_MAX_LEN );
01429 
01430         /* Is this the FLASH or EEPROM device? */
01431         if ( device == &efab->spi_flash )
01432                 device_id = FCN_EE_SPI_FLASH;
01433         else if ( device == &efab->spi_eeprom )
01434                 device_id = FCN_EE_SPI_EEPROM;
01435         else {
01436                 EFAB_ERR ( "Unknown device %p\n", device );
01437                 return -EINVAL;
01438         }
01439 
01440         EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n",
01441                      command, device_id, address, len );
01442 
01443         /* The bus must be idle */
01444         rc = falcon_spi_wait ( efab );
01445         if ( rc )
01446                 goto fail1;
01447 
01448         /* Copy data out */
01449         if ( data_out ) {
01450                 memcpy ( &reg, data_out, len );
01451                 falcon_write ( efab, &reg, FCN_EE_SPI_HDATA_REG );
01452         }
01453 
01454         /* Program address register */
01455         if ( address >= 0 ) {
01456                 EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
01457                 falcon_write ( efab, &reg, FCN_EE_SPI_HADR_REG );
01458         }
01459 
01460         /* Issue command */
01461         address_len = ( address >= 0 ) ? device->address_len / 8 : 0;
01462         read_cmd = ( data_in ? FCN_EE_SPI_READ : FCN_EE_SPI_WRITE );
01463         EFAB_POPULATE_OWORD_7 ( reg,
01464                                 FCN_EE_SPI_HCMD_CMD_EN, 1,
01465                                 FCN_EE_SPI_HCMD_SF_SEL, device_id,
01466                                 FCN_EE_SPI_HCMD_DABCNT, len,
01467                                 FCN_EE_SPI_HCMD_READ, read_cmd,
01468                                 FCN_EE_SPI_HCMD_DUBCNT, 0,
01469                                 FCN_EE_SPI_HCMD_ADBCNT, address_len,
01470                                 FCN_EE_SPI_HCMD_ENC, command );
01471         falcon_write ( efab, &reg, FCN_EE_SPI_HCMD_REG );
01472 
01473         /* Wait for the command to complete */
01474         rc = falcon_spi_wait ( efab );
01475         if ( rc )
01476                 goto fail2;
01477 
01478         /* Copy data in */
01479         if ( data_in ) {
01480                 falcon_read ( efab, &reg, FCN_EE_SPI_HDATA_REG );
01481                 memcpy ( data_in, &reg, len );
01482         }
01483 
01484         return 0;
01485 
01486 fail2:
01487 fail1:
01488         EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n",
01489                    command, device_id, address, len );
01490 
01491         return rc;
01492 }
01493 
01494 /*******************************************************************************
01495  *
01496  *
01497  * Falcon bit-bashed I2C interface
01498  *
01499  *
01500  *******************************************************************************/ 
01501 
01502 static void
01503 falcon_i2c_bit_write ( struct bit_basher *basher, unsigned int bit_id,
01504                        unsigned long data )
01505 {
01506         struct efab_nic *efab = container_of ( basher, struct efab_nic,
01507                                                i2c_bb.basher );
01508         efab_oword_t reg;
01509 
01510         falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
01511         switch ( bit_id ) {
01512         case I2C_BIT_SCL:
01513                 EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO0_OEN, ( data ? 0 : 1 ) );
01514                 break;
01515         case I2C_BIT_SDA:
01516                 EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO3_OEN, ( data ? 0 : 1 ) );
01517                 break;
01518         default:
01519                 EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
01520                 break;
01521         }
01522 
01523         falcon_write ( efab, &reg,  FCN_GPIO_CTL_REG_KER );
01524 }
01525 
01526 static int
01527 falcon_i2c_bit_read ( struct bit_basher *basher, unsigned int bit_id )
01528 {
01529         struct efab_nic *efab = container_of ( basher, struct efab_nic,
01530                                                i2c_bb.basher );
01531         efab_oword_t reg;
01532         
01533         falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
01534         switch ( bit_id ) {
01535         case I2C_BIT_SCL:
01536                 return EFAB_OWORD_FIELD ( reg, FCN_GPIO0_IN );
01537                 break;
01538         case I2C_BIT_SDA:
01539                 return EFAB_OWORD_FIELD ( reg, FCN_GPIO3_IN );
01540                 break;
01541         default:
01542                 EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
01543                 break;
01544         }
01545 
01546         return -1;
01547 }
01548 
01549 static struct bit_basher_operations falcon_i2c_bit_ops = {
01550         .read           = falcon_i2c_bit_read,
01551         .write          = falcon_i2c_bit_write,
01552 };
01553 
01554 
01555 /*******************************************************************************
01556  *
01557  *
01558  * MDIO access
01559  *
01560  *
01561  *******************************************************************************/ 
01562 
01563 static int
01564 falcon_gmii_wait ( struct efab_nic *efab )
01565 {
01566         efab_dword_t md_stat;
01567         int count;
01568 
01569         /* wait up to 10ms */
01570         for (count = 0; count < 1000; count++) {
01571                 falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER );
01572                 if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) {
01573                         if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_LNFL ) != 0 ||
01574                              EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSERR ) != 0 ) {
01575                                 EFAB_ERR ( "Error from GMII access "
01576                                            EFAB_DWORD_FMT"\n",
01577                                            EFAB_DWORD_VAL ( md_stat ));
01578                                 return -EIO;
01579                         }
01580                         return 0;
01581                 }
01582                 udelay(10);
01583         }
01584 
01585         EFAB_ERR ( "Timed out waiting for GMII\n" );
01586         return -ETIMEDOUT;
01587 }
01588 
01589 static void
01590 falcon_mdio_write ( struct efab_nic *efab, int device,
01591                     int location, int value )
01592 {
01593         efab_oword_t reg;
01594 
01595         EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
01596                      device, location, value );
01597 
01598         /* Check MII not currently being accessed */
01599         if ( falcon_gmii_wait ( efab ) )
01600                 return;
01601 
01602         /* Write the address/ID register */
01603         EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
01604         falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
01605 
01606         if ( efab->phy_10g ) {
01607                 /* clause45 */
01608                 EFAB_POPULATE_OWORD_2 ( reg, 
01609                                         FCN_MD_PRT_ADR, efab->phy_addr,
01610                                         FCN_MD_DEV_ADR, device );
01611         }
01612         else {
01613                 /* clause22 */
01614                 assert ( device == 0 );
01615 
01616                 EFAB_POPULATE_OWORD_2 ( reg,
01617                                         FCN_MD_PRT_ADR, efab->phy_addr,
01618                                         FCN_MD_DEV_ADR, location );
01619         }
01620         falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
01621                 
01622 
01623         /* Write data */
01624         EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value );
01625         falcon_write ( efab, &reg, FCN_MD_TXD_REG_KER );
01626 
01627         EFAB_POPULATE_OWORD_2 ( reg,
01628                                 FCN_MD_WRC, 1,
01629                                 FCN_MD_GC, ( efab->phy_10g ? 0 : 1 ) );
01630         falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
01631                 
01632         /* Wait for data to be written */
01633         if ( falcon_gmii_wait ( efab ) ) {
01634                 /* Abort the write operation */
01635                 EFAB_POPULATE_OWORD_2 ( reg,
01636                                         FCN_MD_WRC, 0,
01637                                         FCN_MD_GC, 1);
01638                 falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
01639                 udelay(10);
01640         }
01641 }
01642 
01643 static int
01644 falcon_mdio_read ( struct efab_nic *efab, int device, int location )
01645 {
01646         efab_oword_t reg;
01647         int value;
01648 
01649         /* Check MII not currently being accessed */
01650         if ( falcon_gmii_wait ( efab ) ) 
01651                 return -1;
01652 
01653         if ( efab->phy_10g ) {
01654                 /* clause45 */
01655                 EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
01656                 falcon_write ( efab, &reg, FCN_MD_PHY_ADR_REG_KER );
01657 
01658                 EFAB_POPULATE_OWORD_2 ( reg,
01659                                         FCN_MD_PRT_ADR, efab->phy_addr,
01660                                         FCN_MD_DEV_ADR, device );
01661                 falcon_write ( efab, &reg, FCN_MD_ID_REG_KER);
01662 
01663                 /* request data to be read */
01664                 EFAB_POPULATE_OWORD_2 ( reg,
01665                                         FCN_MD_RDC, 1,
01666                                         FCN_MD_GC, 0 );
01667         }
01668         else {
01669                 /* clause22 */
01670                 assert ( device == 0 );
01671 
01672                 EFAB_POPULATE_OWORD_2 ( reg,
01673                                         FCN_MD_PRT_ADR, efab->phy_addr,
01674                                         FCN_MD_DEV_ADR, location );
01675                 falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
01676 
01677                 /* Request data to be read */
01678                 EFAB_POPULATE_OWORD_2 ( reg,
01679                                         FCN_MD_RIC, 1,
01680                                         FCN_MD_GC, 1 );
01681         }
01682 
01683         falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
01684                 
01685         /* Wait for data to become available */
01686         if ( falcon_gmii_wait ( efab ) ) {
01687                 /* Abort the read operation */
01688                 EFAB_POPULATE_OWORD_2 ( reg,
01689                                         FCN_MD_RIC, 0,
01690                                         FCN_MD_GC, 1 );
01691                 falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
01692                 udelay ( 10 );
01693                 value = -1;
01694         }
01695         else {
01696                 /* Read the data */
01697                 falcon_read ( efab, &reg, FCN_MD_RXD_REG_KER );
01698                 value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD );
01699         }
01700 
01701         EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
01702                      device, location, value );
01703 
01704         return value;
01705 }
01706 
01707 /*******************************************************************************
01708  *
01709  *
01710  * MAC wrapper
01711  *
01712  *
01713  *******************************************************************************/
01714 
01715 static void
01716 falcon_reconfigure_mac_wrapper ( struct efab_nic *efab )
01717 {
01718         efab_oword_t reg;
01719         int link_speed;
01720 
01721         if ( efab->link_options & LPA_EF_10000 ) {
01722                 link_speed = 0x3;
01723         } else if ( efab->link_options & LPA_EF_1000 ) {
01724                 link_speed = 0x2;
01725         } else if ( efab->link_options & LPA_100 ) {
01726                 link_speed = 0x1;
01727         } else {
01728                 link_speed = 0x0;
01729         }
01730         EFAB_POPULATE_OWORD_5 ( reg,
01731                                 FCN_MAC_XOFF_VAL, 0xffff /* datasheet */,
01732                                 FCN_MAC_BCAD_ACPT, 1,
01733                                 FCN_MAC_UC_PROM, 0,
01734                                 FCN_MAC_LINK_STATUS, 1,
01735                                 FCN_MAC_SPEED, link_speed );
01736 
01737         falcon_write ( efab, &reg, FCN_MAC0_CTRL_REG_KER );
01738 }
01739 
01740 /*******************************************************************************
01741  *
01742  *
01743  * GMAC handling
01744  *
01745  *
01746  *******************************************************************************/
01747 
01748 /* GMAC configuration register 1 */
01749 #define GM_CFG1_REG_MAC 0x00
01750 #define GM_SW_RST_LBN 31
01751 #define GM_SW_RST_WIDTH 1
01752 #define GM_RX_FC_EN_LBN 5
01753 #define GM_RX_FC_EN_WIDTH 1
01754 #define GM_TX_FC_EN_LBN 4
01755 #define GM_TX_FC_EN_WIDTH 1
01756 #define GM_RX_EN_LBN 2
01757 #define GM_RX_EN_WIDTH 1
01758 #define GM_TX_EN_LBN 0
01759 #define GM_TX_EN_WIDTH 1
01760 
01761 /* GMAC configuration register 2 */
01762 #define GM_CFG2_REG_MAC 0x01
01763 #define GM_PAMBL_LEN_LBN 12
01764 #define GM_PAMBL_LEN_WIDTH 4
01765 #define GM_IF_MODE_LBN 8
01766 #define GM_IF_MODE_WIDTH 2
01767 #define GM_PAD_CRC_EN_LBN 2
01768 #define GM_PAD_CRC_EN_WIDTH 1
01769 #define GM_FD_LBN 0
01770 #define GM_FD_WIDTH 1
01771 
01772 /* GMAC maximum frame length register */
01773 #define GM_MAX_FLEN_REG_MAC 0x04
01774 #define GM_MAX_FLEN_LBN 0
01775 #define GM_MAX_FLEN_WIDTH 16
01776 
01777 /* GMAC MII management configuration register */
01778 #define GM_MII_MGMT_CFG_REG_MAC 0x08
01779 #define GM_MGMT_CLK_SEL_LBN 0
01780 #define GM_MGMT_CLK_SEL_WIDTH 3
01781 
01782 /* GMAC MII management command register */
01783 #define GM_MII_MGMT_CMD_REG_MAC 0x09
01784 #define GM_MGMT_SCAN_CYC_LBN 1
01785 #define GM_MGMT_SCAN_CYC_WIDTH 1
01786 #define GM_MGMT_RD_CYC_LBN 0
01787 #define GM_MGMT_RD_CYC_WIDTH 1
01788 
01789 /* GMAC MII management address register */
01790 #define GM_MII_MGMT_ADR_REG_MAC 0x0a
01791 #define GM_MGMT_PHY_ADDR_LBN 8
01792 #define GM_MGMT_PHY_ADDR_WIDTH 5
01793 #define GM_MGMT_REG_ADDR_LBN 0
01794 #define GM_MGMT_REG_ADDR_WIDTH 5
01795 
01796 /* GMAC MII management control register */
01797 #define GM_MII_MGMT_CTL_REG_MAC 0x0b
01798 #define GM_MGMT_CTL_LBN 0
01799 #define GM_MGMT_CTL_WIDTH 16
01800 
01801 /* GMAC MII management status register */
01802 #define GM_MII_MGMT_STAT_REG_MAC 0x0c
01803 #define GM_MGMT_STAT_LBN 0
01804 #define GM_MGMT_STAT_WIDTH 16
01805 
01806 /* GMAC MII management indicators register */
01807 #define GM_MII_MGMT_IND_REG_MAC 0x0d
01808 #define GM_MGMT_BUSY_LBN 0
01809 #define GM_MGMT_BUSY_WIDTH 1
01810 
01811 /* GMAC station address register 1 */
01812 #define GM_ADR1_REG_MAC 0x10
01813 #define GM_HWADDR_5_LBN 24
01814 #define GM_HWADDR_5_WIDTH 8
01815 #define GM_HWADDR_4_LBN 16
01816 #define GM_HWADDR_4_WIDTH 8
01817 #define GM_HWADDR_3_LBN 8
01818 #define GM_HWADDR_3_WIDTH 8
01819 #define GM_HWADDR_2_LBN 0
01820 #define GM_HWADDR_2_WIDTH 8
01821 
01822 /* GMAC station address register 2 */
01823 #define GM_ADR2_REG_MAC 0x11
01824 #define GM_HWADDR_1_LBN 24
01825 #define GM_HWADDR_1_WIDTH 8
01826 #define GM_HWADDR_0_LBN 16
01827 #define GM_HWADDR_0_WIDTH 8
01828 
01829 /* GMAC FIFO configuration register 0 */
01830 #define GMF_CFG0_REG_MAC 0x12
01831 #define GMF_FTFENREQ_LBN 12
01832 #define GMF_FTFENREQ_WIDTH 1
01833 #define GMF_STFENREQ_LBN 11
01834 #define GMF_STFENREQ_WIDTH 1
01835 #define GMF_FRFENREQ_LBN 10
01836 #define GMF_FRFENREQ_WIDTH 1
01837 #define GMF_SRFENREQ_LBN 9
01838 #define GMF_SRFENREQ_WIDTH 1
01839 #define GMF_WTMENREQ_LBN 8
01840 #define GMF_WTMENREQ_WIDTH 1
01841 
01842 /* GMAC FIFO configuration register 1 */
01843 #define GMF_CFG1_REG_MAC 0x13
01844 #define GMF_CFGFRTH_LBN 16
01845 #define GMF_CFGFRTH_WIDTH 5
01846 #define GMF_CFGXOFFRTX_LBN 0
01847 #define GMF_CFGXOFFRTX_WIDTH 16
01848 
01849 /* GMAC FIFO configuration register 2 */
01850 #define GMF_CFG2_REG_MAC 0x14
01851 #define GMF_CFGHWM_LBN 16
01852 #define GMF_CFGHWM_WIDTH 6
01853 #define GMF_CFGLWM_LBN 0
01854 #define GMF_CFGLWM_WIDTH 6
01855 
01856 /* GMAC FIFO configuration register 3 */
01857 #define GMF_CFG3_REG_MAC 0x15
01858 #define GMF_CFGHWMFT_LBN 16
01859 #define GMF_CFGHWMFT_WIDTH 6
01860 #define GMF_CFGFTTH_LBN 0
01861 #define GMF_CFGFTTH_WIDTH 6
01862 
01863 /* GMAC FIFO configuration register 4 */
01864 #define GMF_CFG4_REG_MAC 0x16
01865 #define GMF_HSTFLTRFRM_PAUSE_LBN 12
01866 #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
01867 
01868 /* GMAC FIFO configuration register 5 */
01869 #define GMF_CFG5_REG_MAC 0x17
01870 #define GMF_CFGHDPLX_LBN 22
01871 #define GMF_CFGHDPLX_WIDTH 1
01872 #define GMF_CFGBYTMODE_LBN 19
01873 #define GMF_CFGBYTMODE_WIDTH 1
01874 #define GMF_HSTDRPLT64_LBN 18
01875 #define GMF_HSTDRPLT64_WIDTH 1
01876 #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
01877 #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
01878 
01879 static void
01880 falcon_gmac_writel ( struct efab_nic *efab, efab_dword_t *value,
01881                      unsigned int mac_reg )
01882 {
01883         efab_oword_t temp;
01884 
01885         EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
01886                                 EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
01887         falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
01888 }
01889 
01890 static void
01891 falcon_gmac_readl ( struct efab_nic *efab, efab_dword_t *value,
01892                     unsigned int mac_reg )
01893 {
01894         efab_oword_t temp;
01895 
01896         falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
01897         EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
01898                                 EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
01899 }
01900 
01901 static void
01902 mentormac_reset ( struct efab_nic *efab )
01903 {
01904         efab_dword_t reg;
01905 
01906         /* Take into reset */
01907         EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 );
01908         falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
01909         udelay ( 1000 );
01910 
01911         /* Take out of reset */
01912         EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 );
01913         falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
01914         udelay ( 1000 );
01915 
01916         /* Configure GMII interface so PHY is accessible.  Note that
01917          * GMII interface is connected only to port 0, and that on
01918          * Falcon this is a no-op.
01919          */
01920         EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 );
01921         falcon_gmac_writel ( efab, &reg, GM_MII_MGMT_CFG_REG_MAC );
01922         udelay ( 10 );
01923 }
01924 
01925 static void
01926 mentormac_init ( struct efab_nic *efab )
01927 {
01928         int pause, if_mode, full_duplex, bytemode, half_duplex;
01929         efab_dword_t reg;
01930 
01931         /* Configuration register 1 */
01932         pause = ( efab->link_options & LPA_PAUSE_CAP ) ? 1 : 0;
01933         if ( ! ( efab->link_options & LPA_EF_DUPLEX ) ) {
01934                 /* Half-duplex operation requires TX flow control */
01935                 pause = 1;
01936         }
01937         EFAB_POPULATE_DWORD_4 ( reg,
01938                                 GM_TX_EN, 1,
01939                                 GM_TX_FC_EN, pause,
01940                                 GM_RX_EN, 1,
01941                                 GM_RX_FC_EN, 1 );
01942         falcon_gmac_writel ( efab, &reg, GM_CFG1_REG_MAC );
01943         udelay ( 10 );
01944 
01945         /* Configuration register 2 */
01946         if_mode = ( efab->link_options & LPA_EF_1000 ) ? 2 : 1;
01947         full_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 1 : 0;
01948         EFAB_POPULATE_DWORD_4 ( reg,
01949                                 GM_IF_MODE, if_mode,
01950                                 GM_PAD_CRC_EN, 1,
01951                                 GM_FD, full_duplex,
01952                                 GM_PAMBL_LEN, 0x7 /* ? */ );
01953         falcon_gmac_writel ( efab, &reg, GM_CFG2_REG_MAC );
01954         udelay ( 10 );
01955 
01956         /* Max frame len register */
01957         EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN,
01958                                 EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN ) );
01959         falcon_gmac_writel ( efab, &reg, GM_MAX_FLEN_REG_MAC );
01960         udelay ( 10 );
01961 
01962         /* FIFO configuration register 0 */
01963         EFAB_POPULATE_DWORD_5 ( reg,
01964                                 GMF_FTFENREQ, 1,
01965                                 GMF_STFENREQ, 1,
01966                                 GMF_FRFENREQ, 1,
01967                                 GMF_SRFENREQ, 1,
01968                                 GMF_WTMENREQ, 1 );
01969         falcon_gmac_writel ( efab, &reg, GMF_CFG0_REG_MAC );
01970         udelay ( 10 );
01971 
01972         /* FIFO configuration register 1 */
01973         EFAB_POPULATE_DWORD_2 ( reg,
01974                                 GMF_CFGFRTH, 0x12,
01975                                 GMF_CFGXOFFRTX, 0xffff );
01976         falcon_gmac_writel ( efab, &reg, GMF_CFG1_REG_MAC );
01977         udelay ( 10 );
01978 
01979         /* FIFO configuration register 2 */
01980         EFAB_POPULATE_DWORD_2 ( reg,
01981                                 GMF_CFGHWM, 0x3f,
01982                                 GMF_CFGLWM, 0xa );
01983         falcon_gmac_writel ( efab, &reg, GMF_CFG2_REG_MAC );
01984         udelay ( 10 );
01985 
01986         /* FIFO configuration register 3 */
01987         EFAB_POPULATE_DWORD_2 ( reg,
01988                                 GMF_CFGHWMFT, 0x1c,
01989                                 GMF_CFGFTTH, 0x08 );
01990         falcon_gmac_writel ( efab, &reg, GMF_CFG3_REG_MAC );
01991         udelay ( 10 );
01992 
01993         /* FIFO configuration register 4 */
01994         EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 );
01995         falcon_gmac_writel ( efab, &reg, GMF_CFG4_REG_MAC );
01996         udelay ( 10 );
01997         
01998         /* FIFO configuration register 5 */
01999         bytemode = ( efab->link_options & LPA_EF_1000 ) ? 1 : 0;
02000         half_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 0 : 1;
02001         falcon_gmac_readl ( efab, &reg, GMF_CFG5_REG_MAC );
02002         EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode );
02003         EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex );
02004         EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex );
02005         EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 );
02006         falcon_gmac_writel ( efab, &reg, GMF_CFG5_REG_MAC );
02007         udelay ( 10 );
02008         
02009         /* MAC address */
02010         EFAB_POPULATE_DWORD_4 ( reg,
02011                                 GM_HWADDR_5, efab->mac_addr[5],
02012                                 GM_HWADDR_4, efab->mac_addr[4],
02013                                 GM_HWADDR_3, efab->mac_addr[3],
02014                                 GM_HWADDR_2, efab->mac_addr[2] );
02015         falcon_gmac_writel ( efab, &reg, GM_ADR1_REG_MAC );
02016         udelay ( 10 );
02017         EFAB_POPULATE_DWORD_2 ( reg,
02018                                 GM_HWADDR_1, efab->mac_addr[1],
02019                                 GM_HWADDR_0, efab->mac_addr[0] );
02020         falcon_gmac_writel ( efab, &reg, GM_ADR2_REG_MAC );
02021         udelay ( 10 );
02022 }
02023 
02024 static int
02025 falcon_init_gmac ( struct efab_nic *efab )
02026 {
02027         /* Reset the MAC */
02028         mentormac_reset ( efab );
02029 
02030         /* Initialise PHY */
02031         efab->phy_op->init ( efab );
02032 
02033         /* check the link is up */
02034         if ( !efab->link_up )
02035                 return -EAGAIN;
02036 
02037         /* Initialise MAC */
02038         mentormac_init ( efab );
02039 
02040         /* reconfigure the MAC wrapper */
02041         falcon_reconfigure_mac_wrapper ( efab );
02042 
02043         return 0;
02044 }
02045 
02046 static struct efab_mac_operations falcon_gmac_operations = {
02047         .init                   = falcon_init_gmac,
02048 };
02049 
02050 
02051 /*******************************************************************************
02052  *
02053  *
02054  * XMAC handling
02055  *
02056  *
02057  *******************************************************************************/
02058 
02059 /**
02060  * Write dword to a Falcon XMAC register
02061  *
02062  */
02063 static void
02064 falcon_xmac_writel ( struct efab_nic *efab, efab_dword_t *value,
02065                      unsigned int mac_reg )
02066 {
02067         efab_oword_t temp;
02068 
02069         EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
02070                                 EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
02071         falcon_write ( efab, &temp,
02072                        FALCON_XMAC_REG ( efab, mac_reg ) );
02073 }
02074 
02075 /**
02076  * Read dword from a Falcon XMAC register
02077  *
02078  */
02079 static void
02080 falcon_xmac_readl ( struct efab_nic *efab, efab_dword_t *value,
02081                     unsigned int mac_reg )
02082 {
02083         efab_oword_t temp;
02084 
02085         falcon_read ( efab, &temp,
02086                       FALCON_XMAC_REG ( efab, mac_reg ) );
02087         EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
02088                                 EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
02089 }
02090 
02091 /**
02092  * Configure Falcon XAUI output
02093  */
02094 static void
02095 falcon_setup_xaui ( struct efab_nic *efab )
02096 {
02097         efab_dword_t sdctl, txdrv;
02098 
02099         falcon_xmac_readl ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
02100         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT );
02101         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVD, XX_SD_CTL_DRV_DEFAULT );
02102         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT );
02103         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVC, XX_SD_CTL_DRV_DEFAULT );
02104         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT );
02105         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVB, XX_SD_CTL_DRV_DEFAULT );
02106         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT );
02107         EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVA, XX_SD_CTL_DRV_DEFAULT );
02108         falcon_xmac_writel ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
02109 
02110         EFAB_POPULATE_DWORD_8 ( txdrv,
02111                                 FCN_XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
02112                                 FCN_XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
02113                                 FCN_XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
02114                                 FCN_XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
02115                                 FCN_XX_DTXD, XX_TXDRV_DTX_DEFAULT,
02116                                 FCN_XX_DTXC, XX_TXDRV_DTX_DEFAULT,
02117                                 FCN_XX_DTXB, XX_TXDRV_DTX_DEFAULT,
02118                                 FCN_XX_DTXA, XX_TXDRV_DTX_DEFAULT);
02119         falcon_xmac_writel ( efab, &txdrv, FCN_XX_TXDRV_CTL_REG_MAC);
02120 }
02121 
02122 static int
02123 falcon_xgmii_status ( struct efab_nic *efab )
02124 {
02125         efab_dword_t reg;
02126 
02127         if ( efab->pci_revision  < FALCON_REV_B0 )
02128                 return 1;
02129         /* The ISR latches, so clear it and re-read */
02130         falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
02131         falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
02132 
02133         if ( EFAB_DWORD_FIELD ( reg, FCN_XM_LCLFLT ) ||
02134              EFAB_DWORD_FIELD ( reg, FCN_XM_RMTFLT ) ) {
02135                 EFAB_TRACE ( "MGT_INT: "EFAB_DWORD_FMT"\n",
02136                              EFAB_DWORD_VAL ( reg ) );
02137                 return 0;
02138         }
02139 
02140         return 1;
02141 }
02142 
02143 static void
02144 falcon_mask_status_intr ( struct efab_nic *efab, int enable )
02145 {
02146         efab_dword_t reg;
02147 
02148         if ( efab->pci_revision  < FALCON_REV_B0 )
02149                 return;
02150 
02151         /* Flush the ISR */
02152         if ( enable )
02153                 falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_REG_MAC_B0 );
02154 
02155         EFAB_POPULATE_DWORD_2 ( reg,
02156                                 FCN_XM_MSK_RMTFLT, !enable,
02157                                 FCN_XM_MSK_LCLFLT, !enable);
02158         falcon_xmac_readl ( efab, &reg, FCN_XM_MGT_INT_MSK_REG_MAC_B0 );
02159 }
02160 
02161 /**
02162  * Reset 10G MAC connected to port
02163  *
02164  */
02165 static int
02166 falcon_reset_xmac ( struct efab_nic *efab )
02167 {
02168         efab_dword_t reg;
02169         int count;
02170 
02171         EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 );
02172         falcon_xmac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
02173 
02174         for ( count = 0 ; count < 1000 ; count++ ) {
02175                 udelay ( 10 );
02176                 falcon_xmac_readl ( efab, &reg,
02177                                     FCN_XM_GLB_CFG_REG_MAC );
02178                 if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 )
02179                         return 0;
02180         }
02181         return -ETIMEDOUT;
02182 }
02183 
02184 
02185 static int
02186 falcon_reset_xaui ( struct efab_nic *efab )
02187 {
02188         efab_dword_t reg;
02189         int count;
02190 
02191         if (!efab->is_asic)
02192                 return 0;
02193 
02194         EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 );
02195         falcon_xmac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
02196 
02197         /* Give some time for the link to establish */
02198         for (count = 0; count < 1000; count++) { /* wait up to 10ms */
02199                 falcon_xmac_readl ( efab, &reg, FCN_XX_PWR_RST_REG_MAC );
02200                 if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) {
02201                         falcon_setup_xaui ( efab );
02202                         return 0;
02203                 }
02204                 udelay(10);
02205         }
02206         EFAB_ERR ( "timed out waiting for XAUI/XGXS reset\n" );
02207         return -ETIMEDOUT;
02208 }
02209 
02210 static int
02211 falcon_xaui_link_ok ( struct efab_nic *efab )
02212 {
02213         efab_dword_t reg;
02214         int align_done, lane_status, sync;
02215         int has_phyxs;
02216         int link_ok = 1;
02217 
02218         /* Read Falcon XAUI side */
02219         if ( efab->is_asic ) {
02220                 /* Read link status */
02221                 falcon_xmac_readl ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
02222                 align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE );
02223 
02224                 sync = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT );
02225                 sync = ( sync == FCN_XX_SYNC_STAT_DECODE_SYNCED );
02226                 
02227                 link_ok = align_done && sync;
02228         }
02229 
02230         /* Clear link status ready for next read */
02231         EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET );
02232         EFAB_SET_DWORD_FIELD ( reg, FCN_XX_CHARERR, FCN_XX_CHARERR_RESET);
02233         EFAB_SET_DWORD_FIELD ( reg, FCN_XX_DISPERR, FCN_XX_DISPERR_RESET);
02234         falcon_xmac_writel ( efab, &reg, FCN_XX_CORE_STAT_REG_MAC );
02235 
02236         has_phyxs = ( efab->phy_op->mmds & ( 1 << MDIO_MMD_PHYXS ) );
02237         if ( link_ok && has_phyxs ) {
02238                 lane_status = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
02239                                                  MDIO_PHYXS_LANE_STATE );
02240                 link_ok = ( lane_status & ( 1 << MDIO_PHYXS_LANE_ALIGNED_LBN ) );
02241 
02242                 if (!link_ok )
02243                         EFAB_LOG ( "XGXS lane status: %x\n", lane_status );
02244         }
02245 
02246         return link_ok;
02247 }
02248 
02249 /**
02250  * Initialise XMAC
02251  *
02252  */
02253 static void
02254 falcon_reconfigure_xmac ( struct efab_nic *efab )
02255 {
02256         efab_dword_t reg;
02257         int max_frame_len;
02258 
02259         /* Configure MAC - cut-thru mode is hard wired on */
02260         EFAB_POPULATE_DWORD_3 ( reg,
02261                                 FCN_XM_RX_JUMBO_MODE, 1,
02262                                 FCN_XM_TX_STAT_EN, 1,
02263                                 FCN_XM_RX_STAT_EN, 1);
02264         falcon_xmac_writel ( efab, &reg, FCN_XM_GLB_CFG_REG_MAC );
02265 
02266         /* Configure TX */
02267         EFAB_POPULATE_DWORD_6 ( reg, 
02268                                 FCN_XM_TXEN, 1,
02269                                 FCN_XM_TX_PRMBL, 1,
02270                                 FCN_XM_AUTO_PAD, 1,
02271                                 FCN_XM_TXCRC, 1,
02272                                 FCN_XM_FCNTL, 1,
02273                                 FCN_XM_IPG, 0x3 );
02274         falcon_xmac_writel ( efab, &reg, FCN_XM_TX_CFG_REG_MAC );
02275 
02276         /* Configure RX */
02277         EFAB_POPULATE_DWORD_4 ( reg,
02278                                 FCN_XM_RXEN, 1,
02279                                 FCN_XM_AUTO_DEPAD, 0,
02280                                 FCN_XM_ACPT_ALL_MCAST, 1,
02281                                 FCN_XM_PASS_CRC_ERR, 1 );
02282         falcon_xmac_writel ( efab, &reg, FCN_XM_RX_CFG_REG_MAC );
02283 
02284         /* Set frame length */
02285         max_frame_len = EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN );
02286         EFAB_POPULATE_DWORD_1 ( reg,
02287                                 FCN_XM_MAX_RX_FRM_SIZE, max_frame_len );
02288         falcon_xmac_writel ( efab, &reg, FCN_XM_RX_PARAM_REG_MAC );
02289         EFAB_POPULATE_DWORD_2 ( reg,
02290                                 FCN_XM_MAX_TX_FRM_SIZE, max_frame_len,
02291                                 FCN_XM_TX_JUMBO_MODE, 1 );
02292         falcon_xmac_writel ( efab, &reg, FCN_XM_TX_PARAM_REG_MAC );
02293 
02294         /* Enable flow control receipt */
02295         EFAB_POPULATE_DWORD_2 ( reg,
02296                                 FCN_XM_PAUSE_TIME, 0xfffe,
02297                                 FCN_XM_DIS_FCNTL, 0 );
02298         falcon_xmac_writel ( efab, &reg, FCN_XM_FC_REG_MAC );
02299 
02300         /* Set MAC address */
02301         EFAB_POPULATE_DWORD_4 ( reg,
02302                                 FCN_XM_ADR_0, efab->mac_addr[0],
02303                                 FCN_XM_ADR_1, efab->mac_addr[1],
02304                                 FCN_XM_ADR_2, efab->mac_addr[2],
02305                                 FCN_XM_ADR_3, efab->mac_addr[3] );
02306         falcon_xmac_writel ( efab, &reg, FCN_XM_ADR_LO_REG_MAC );
02307         EFAB_POPULATE_DWORD_2 ( reg,
02308                                 FCN_XM_ADR_4, efab->mac_addr[4],
02309                                 FCN_XM_ADR_5, efab->mac_addr[5] );
02310         falcon_xmac_writel ( efab, &reg, FCN_XM_ADR_HI_REG_MAC );
02311 }
02312 
02313 static int
02314 falcon_init_xmac ( struct efab_nic *efab )
02315 {
02316         int count, rc;
02317 
02318         /* Mask the PHY management interrupt */
02319         falcon_mask_status_intr ( efab, 0 );
02320 
02321         /* Initialise the PHY to instantiate the clock. */
02322         rc = efab->phy_op->init ( efab );
02323         if ( rc ) {
02324                 EFAB_ERR ( "unable to initialise PHY\n" );
02325                 goto fail1;
02326         }
02327 
02328         falcon_reset_xaui ( efab );
02329 
02330         /* Give the PHY and MAC time to faff */
02331         mdelay ( 100 );
02332 
02333         /* Reset and reconfigure the XMAC */
02334         rc = falcon_reset_xmac ( efab );
02335         if ( rc )
02336                 goto fail2;
02337         falcon_reconfigure_xmac ( efab );
02338         falcon_reconfigure_mac_wrapper ( efab );
02339         /**
02340          * Now wait for the link to come up. This may take a while
02341          * for some slower PHY's.
02342          */
02343         for (count=0; count<50; count++) {
02344                 int link_ok = 1;
02345 
02346                 /* Wait a while for the link to come up. */
02347                 mdelay ( 100 );
02348                 if ((count % 5) == 0)
02349                         putchar ( '.' );
02350 
02351                 /* Does the PHY think the wire-side link is up? */
02352                 link_ok = mdio_clause45_links_ok ( efab );
02353                 /* Ensure the XAUI link to the PHY is good */
02354                 if ( link_ok ) {
02355                         link_ok = falcon_xaui_link_ok ( efab );
02356                         if ( !link_ok )
02357                                 falcon_reset_xaui ( efab );
02358                 }
02359 
02360                 /* Check fault indication */
02361                 if ( link_ok )
02362                         link_ok = falcon_xgmii_status ( efab );
02363 
02364                 efab->link_up = link_ok;
02365                 if ( link_ok ) {
02366                         /* unmask the status interrupt */
02367                         falcon_mask_status_intr ( efab, 1 );
02368                         return 0;
02369                 }
02370         }
02371 
02372         /* Link failed to come up, but initialisation was fine. */
02373         rc = -ETIMEDOUT;
02374 
02375 fail2:
02376 fail1:
02377         return rc;
02378 }
02379 
02380 static struct efab_mac_operations falcon_xmac_operations = {
02381         .init                   = falcon_init_xmac,
02382 };
02383 
02384 /*******************************************************************************
02385  *
02386  *
02387  * Null PHY handling
02388  *
02389  *
02390  *******************************************************************************/
02391 
02392 static int
02393 falcon_xaui_phy_init ( struct efab_nic *efab )
02394 {
02395         /* CX4 is always 10000FD only */
02396         efab->link_options = LPA_EF_10000FULL;
02397 
02398         /* There is no PHY! */
02399         return 0;
02400 }
02401 
02402 static struct efab_phy_operations falcon_xaui_phy_ops = {
02403         .init                   = falcon_xaui_phy_init,
02404         .mmds                   = 0,
02405 };
02406 
02407 
02408 /*******************************************************************************
02409  *
02410  *
02411  * Alaska PHY
02412  *
02413  *
02414  *******************************************************************************/
02415 
02416 /**
02417  * Initialise Alaska PHY
02418  *
02419  */
02420 static int
02421 alaska_init ( struct efab_nic *efab )
02422 {
02423         unsigned int advertised, lpa;
02424 
02425         /* Read link up status */
02426         efab->link_up = gmii_link_ok ( efab );
02427 
02428         if ( ! efab->link_up )
02429                 return -EIO;
02430 
02431         /* Determine link options from PHY. */
02432         advertised = gmii_autoneg_advertised ( efab );
02433         lpa = gmii_autoneg_lpa ( efab );
02434         efab->link_options = gmii_nway_result ( advertised & lpa );
02435 
02436         return 0;
02437 }
02438 
02439 static struct efab_phy_operations falcon_alaska_phy_ops = {
02440         .init           = alaska_init,
02441 };
02442 
02443 /*******************************************************************************
02444  *
02445  *
02446  * xfp
02447  *
02448  *
02449  *******************************************************************************/
02450 
02451 #define XFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS    |          \
02452                             MDIO_MMDREG_DEVS0_PMAPMD |          \
02453                             MDIO_MMDREG_DEVS0_PHYXS )
02454 
02455 static int
02456 falcon_xfp_phy_init ( struct efab_nic *efab )
02457 {
02458         int rc;
02459 
02460         /* Optical link is always 10000FD only */
02461         efab->link_options = LPA_EF_10000FULL;
02462 
02463         /* Reset the PHY */
02464         rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PHYXS );
02465         if ( rc )
02466                 return rc;
02467 
02468         return 0;
02469 }
02470 
02471 static struct efab_phy_operations falcon_xfp_phy_ops = {
02472         .init                   = falcon_xfp_phy_init,
02473         .mmds                   = XFP_REQUIRED_DEVS,
02474 };
02475 
02476 /*******************************************************************************
02477  *
02478  *
02479  * txc43128
02480  *
02481  *
02482  *******************************************************************************/
02483 
02484 /* Command register */
02485 #define TXC_GLRGS_GLCMD         (0xc004)
02486 #define TXC_GLCMD_LMTSWRST_LBN  (14)
02487 
02488 /* Amplitude on lanes 0+1, 2+3 */
02489 #define  TXC_ALRGS_ATXAMP0      (0xc041)
02490 #define  TXC_ALRGS_ATXAMP1      (0xc042)
02491 /* Bit position of value for lane 0+2, 1+3 */
02492 #define TXC_ATXAMP_LANE02_LBN   (3)
02493 #define TXC_ATXAMP_LANE13_LBN   (11)
02494 
02495 #define TXC_ATXAMP_1280_mV      (0)
02496 #define TXC_ATXAMP_1200_mV      (8)
02497 #define TXC_ATXAMP_1120_mV      (12)
02498 #define TXC_ATXAMP_1060_mV      (14)
02499 #define TXC_ATXAMP_0820_mV      (25)
02500 #define TXC_ATXAMP_0720_mV      (26)
02501 #define TXC_ATXAMP_0580_mV      (27)
02502 #define TXC_ATXAMP_0440_mV      (28)
02503 
02504 #define TXC_ATXAMP_0820_BOTH    ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \
02505                                   (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) )
02506 
02507 #define TXC_ATXAMP_DEFAULT      (0x6060) /* From databook */
02508 
02509 /* Preemphasis on lanes 0+1, 2+3 */
02510 #define  TXC_ALRGS_ATXPRE0      (0xc043)
02511 #define  TXC_ALRGS_ATXPRE1      (0xc044)
02512 
02513 #define TXC_ATXPRE_NONE (0)
02514 #define TXC_ATXPRE_DEFAULT      (0x1010) /* From databook */
02515 
02516 #define TXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS    |         \
02517                             MDIO_MMDREG_DEVS0_PMAPMD |         \
02518                             MDIO_MMDREG_DEVS0_PHYXS )
02519 
02520 static int
02521 falcon_txc_logic_reset ( struct efab_nic *efab )
02522 {
02523         int val;
02524         int tries = 50;
02525 
02526         val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD );
02527         val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
02528         falcon_mdio_write ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD, val );
02529 
02530         while ( tries--) {
02531                 val = falcon_mdio_read ( efab, MDIO_MMD_PCS, TXC_GLRGS_GLCMD );
02532                 if ( ~val & ( 1 << TXC_GLCMD_LMTSWRST_LBN ) )
02533                         return 0;
02534                 udelay(1);
02535         }
02536 
02537         EFAB_ERR ( "logic reset failed\n" );
02538 
02539         return -ETIMEDOUT;
02540 }
02541 
02542 static int
02543 falcon_txc_phy_init ( struct efab_nic *efab )
02544 {
02545         int rc;
02546 
02547         /* CX4 is always 10000FD only */
02548         efab->link_options = LPA_EF_10000FULL;
02549 
02550         /* reset the phy */
02551         rc = mdio_clause45_reset_mmd ( efab, MDIO_MMD_PMAPMD );
02552         if ( rc )
02553                 goto fail1;
02554 
02555         rc = mdio_clause45_check_mmds ( efab );
02556         if ( rc )
02557                 goto fail2;
02558 
02559         /* Turn amplitude down and preemphasis off on the host side
02560          * (PHY<->MAC) as this is believed less likely to upset falcon
02561          * and no adverse effects have been noted. It probably also 
02562          * saves a picowatt or two */
02563 
02564         /* Turn off preemphasis */
02565         falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0,
02566                             TXC_ATXPRE_NONE );
02567         falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1,
02568                             TXC_ATXPRE_NONE );
02569 
02570         /* Turn down the amplitude */
02571         falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP0,
02572                             TXC_ATXAMP_0820_BOTH );
02573         falcon_mdio_write ( efab, MDIO_MMD_PHYXS, TXC_ALRGS_ATXAMP1,
02574                             TXC_ATXAMP_0820_BOTH );
02575 
02576         /* Set the line side amplitude and preemphasis to the databook
02577          * defaults as an erratum causes them to be 0 on at least some
02578          * PHY rev.s */
02579         falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE0,
02580                             TXC_ATXPRE_DEFAULT );
02581         falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXPRE1,
02582                             TXC_ATXPRE_DEFAULT );
02583         falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP0,
02584                             TXC_ATXAMP_DEFAULT );
02585         falcon_mdio_write ( efab, MDIO_MMD_PMAPMD, TXC_ALRGS_ATXAMP1,
02586                             TXC_ATXAMP_DEFAULT );
02587 
02588         rc = falcon_txc_logic_reset ( efab );
02589         if ( rc )
02590                 goto fail3;
02591 
02592         return 0;
02593 
02594 fail3:
02595 fail2:
02596 fail1:
02597         return rc;
02598 }
02599 
02600 static struct efab_phy_operations falcon_txc_phy_ops = {
02601         .init                   = falcon_txc_phy_init,
02602         .mmds                   = TXC_REQUIRED_DEVS,
02603 };
02604 
02605 /*******************************************************************************
02606  *
02607  *
02608  * tenxpress
02609  *
02610  *
02611  *******************************************************************************/
02612 
02613 
02614 #define TENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD |    \
02615                                   MDIO_MMDREG_DEVS0_PCS    |    \
02616                                   MDIO_MMDREG_DEVS0_PHYXS )
02617 
02618 #define PCS_TEST_SELECT_REG 0xd807      /* PRM 10.5.8 */
02619 #define CLK312_EN_LBN 3
02620 #define CLK312_EN_WIDTH 1
02621 
02622 #define PCS_CLOCK_CTRL_REG 0xd801
02623 #define PLL312_RST_N_LBN 2
02624 
02625 /* Special Software reset register */
02626 #define PMA_PMD_EXT_CTRL_REG 49152
02627 #define PMA_PMD_EXT_SSR_LBN 15
02628 
02629 /* Boot status register */
02630 #define PCS_BOOT_STATUS_REG     0xd000
02631 #define PCS_BOOT_FATAL_ERR_LBN  0
02632 #define PCS_BOOT_PROGRESS_LBN   1
02633 #define PCS_BOOT_PROGRESS_WIDTH 2
02634 #define PCS_BOOT_COMPLETE_LBN   3
02635 
02636 #define PCS_SOFT_RST2_REG 0xd806
02637 #define SERDES_RST_N_LBN 13
02638 #define XGXS_RST_N_LBN 12
02639 
02640 static int
02641 falcon_tenxpress_check_c11 ( struct efab_nic *efab )
02642 {
02643         int count;
02644         uint32_t boot_stat;
02645 
02646         /* Check that the C11 CPU has booted */
02647         for (count=0; count<10; count++) {
02648                 boot_stat = falcon_mdio_read ( efab, MDIO_MMD_PCS,
02649                                                PCS_BOOT_STATUS_REG );
02650                 if ( boot_stat & ( 1 << PCS_BOOT_COMPLETE_LBN ) )
02651                         return 0;
02652 
02653                 udelay(10);
02654         }
02655 
02656         EFAB_ERR ( "C11 failed to boot\n" );
02657         return -ETIMEDOUT;
02658 }
02659 
02660 static int
02661 falcon_tenxpress_phy_init ( struct efab_nic *efab )
02662 {
02663         int rc, reg;
02664 
02665         /* 10XPRESS is always 10000FD (at the moment) */
02666         efab->link_options = LPA_EF_10000FULL;
02667 
02668         /* Wait for the blocks to come out of reset */
02669         rc = mdio_clause45_wait_reset_mmds ( efab );
02670         if ( rc )
02671                 goto fail1;
02672 
02673         rc = mdio_clause45_check_mmds ( efab );
02674         if ( rc )
02675                 goto fail2;
02676 
02677         /* Turn on the clock  */
02678         reg = (1 << CLK312_EN_LBN);
02679         falcon_mdio_write ( efab, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
02680 
02681         /* Wait 200ms for the PHY to boot */
02682         mdelay(200);
02683 
02684         rc = falcon_tenxpress_check_c11 ( efab );
02685         if ( rc )
02686                 goto fail3;
02687 
02688         return 0;
02689 
02690 fail3:
02691 fail2:
02692 fail1:
02693         return rc;
02694 }
02695 
02696 static struct efab_phy_operations falcon_tenxpress_phy_ops = {
02697         .init                   = falcon_tenxpress_phy_init,
02698         .mmds                   = TENXPRESS_REQUIRED_DEVS,
02699 };
02700 
02701 /*******************************************************************************
02702  *
02703  *
02704  * PM8358
02705  *
02706  *
02707  *******************************************************************************/
02708 
02709 /* The PM8358 just presents a DTE XS */
02710 #define PM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS)
02711 
02712 /* PHY-specific definitions */
02713 /* Master ID and Global Performance Monitor Update */
02714 #define PMC_MASTER_REG (0xd000)
02715 /* Analog Tx Rx settings under software control */
02716 #define PMC_MASTER_ANLG_CTRL (1<< 11)
02717 
02718 /* Master Configuration register 2 */
02719 #define PMC_MCONF2_REG  (0xd002)
02720 /* Drive Tx off centre of data eye (1) vs. clock edge (0) */
02721 #define PMC_MCONF2_TEDGE (1 << 2) 
02722 /* Drive Rx off centre of data eye (1) vs. clock edge (0) */
02723 #define PMC_MCONF2_REDGE (1 << 3)
02724 
02725 /* Analog Rx settings */
02726 #define PMC_ANALOG_RX_CFG0   (0xd025)
02727 #define PMC_ANALOG_RX_CFG1   (0xd02d)
02728 #define PMC_ANALOG_RX_CFG2   (0xd035)
02729 #define PMC_ANALOG_RX_CFG3   (0xd03d)
02730 
02731 
02732 #define PMC_ANALOG_RX_TERM     (1 << 15) /* Bit 15 of RX CFG: 0 for 100 ohms float,
02733                                             1 for 50 to 1.2V */
02734 #define PMC_ANALOG_RX_EQ_MASK (3 << 8)
02735 #define PMC_ANALOG_RX_EQ_NONE (0 << 8)
02736 #define PMC_ANALOG_RX_EQ_HALF (1 << 8)
02737 #define PMC_ANALOG_RX_EQ_FULL (2 << 8)
02738 #define PMC_ANALOG_RX_EQ_RSVD (3 << 8)
02739 
02740 static int
02741 falcon_pm8358_phy_init ( struct efab_nic *efab )
02742 {
02743         int rc, reg, i;
02744 
02745         /* This is a XAUI retimer part */
02746         efab->link_options = LPA_EF_10000FULL;
02747 
02748         rc = mdio_clause45_reset_mmd ( efab, MDIO_MMDREG_DEVS0_DTEXS );
02749         if ( rc )
02750                 return rc;
02751         
02752         /* Enable software control of analogue settings */
02753         reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS,  PMC_MASTER_REG );
02754         reg |= PMC_MASTER_ANLG_CTRL;
02755         falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MASTER_REG, reg );
02756 
02757         /* Turn rx eq on for all channels */
02758         for (i=0; i< 3; i++) {
02759                 /* The analog CFG registers are evenly spaced 8 apart */
02760                 uint16_t addr = PMC_ANALOG_RX_CFG0 + 8*i;
02761                 reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, addr );
02762                 reg = ( reg & ~PMC_ANALOG_RX_EQ_MASK ) | PMC_ANALOG_RX_EQ_FULL;
02763                 falcon_mdio_write ( efab, MDIO_MMD_DTEXS, addr, reg );
02764         }
02765 
02766         /* Set TEDGE, clear REDGE */
02767         reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG );
02768         reg = ( reg & ~PMC_MCONF2_REDGE) | PMC_MCONF2_TEDGE;
02769         falcon_mdio_write ( efab, MDIO_MMD_DTEXS, PMC_MCONF2_REG, reg );
02770 
02771         return 0;
02772 }
02773 
02774 static struct efab_phy_operations falcon_pm8358_phy_ops = {
02775         .init                   = falcon_pm8358_phy_init,
02776         .mmds                   = PM8358_REQUIRED_DEVS,
02777 };
02778 
02779 /*******************************************************************************
02780  *
02781  *
02782  * SFE4001 support
02783  *
02784  *
02785  *******************************************************************************/
02786 
02787 #define MAX_TEMP_THRESH 90
02788 
02789 /* I2C Expander */
02790 #define PCA9539 0x74
02791 
02792 #define P0_IN 0x00
02793 #define P0_OUT 0x02
02794 #define P0_CONFIG 0x06
02795 
02796 #define P0_EN_1V0X_LBN 0
02797 #define P0_EN_1V0X_WIDTH 1
02798 #define P0_EN_1V2_LBN 1
02799 #define P0_EN_1V2_WIDTH 1
02800 #define P0_EN_2V5_LBN 2
02801 #define P0_EN_2V5_WIDTH 1
02802 #define P0_EN_3V3X_LBN 3
02803 #define P0_EN_3V3X_WIDTH 1
02804 #define P0_EN_5V_LBN 4
02805 #define P0_EN_5V_WIDTH 1
02806 #define P0_X_TRST_LBN 6
02807 #define P0_X_TRST_WIDTH 1
02808 
02809 #define P1_IN 0x01
02810 #define P1_CONFIG 0x07
02811 
02812 #define P1_AFE_PWD_LBN 0
02813 #define P1_AFE_PWD_WIDTH 1
02814 #define P1_DSP_PWD25_LBN 1
02815 #define P1_DSP_PWD25_WIDTH 1
02816 #define P1_SPARE_LBN 4
02817 #define P1_SPARE_WIDTH 4
02818 
02819 /* Temperature Sensor */
02820 #define MAX6647 0x4e
02821 
02822 #define RSL     0x02
02823 #define RLHN    0x05
02824 #define WLHO    0x0b
02825 
02826 static struct i2c_device i2c_pca9539 = {
02827         .dev_addr = PCA9539,
02828         .dev_addr_len = 1,
02829         .word_addr_len = 1,
02830 };
02831 
02832 
02833 static struct i2c_device i2c_max6647 = {
02834         .dev_addr = MAX6647,
02835         .dev_addr_len = 1,
02836         .word_addr_len = 1,
02837 };
02838 
02839 static int
02840 sfe4001_init ( struct efab_nic *efab )
02841 {
02842         struct i2c_interface *i2c = &efab->i2c_bb.i2c;
02843         efab_dword_t reg;
02844         uint8_t in, cfg, out;
02845         int count, rc;
02846 
02847         EFAB_LOG ( "Initialise SFE4001 board\n" );
02848 
02849         /* Ensure XGXS and XAUI SerDes are held in reset */
02850         EFAB_POPULATE_DWORD_7 ( reg,
02851                                 FCN_XX_PWRDNA_EN, 1,
02852                                 FCN_XX_PWRDNB_EN, 1,
02853                                 FCN_XX_RSTPLLAB_EN, 1,
02854                                 FCN_XX_RESETA_EN, 1,
02855                                 FCN_XX_RESETB_EN, 1,
02856                                 FCN_XX_RSTXGXSRX_EN, 1,
02857                                 FCN_XX_RSTXGXSTX_EN, 1 );
02858         falcon_xmac_writel ( efab, &reg, FCN_XX_PWR_RST_REG_MAC);
02859         udelay(10);
02860 
02861         /* Set DSP over-temperature alert threshold */
02862         cfg = MAX_TEMP_THRESH;
02863         rc = i2c->write ( i2c, &i2c_max6647, WLHO, &cfg, EFAB_BYTE );
02864         if ( rc )
02865                 goto fail1;
02866 
02867         /* Read it back and verify */
02868         rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE );
02869         if ( rc )
02870                 goto fail2;
02871 
02872         if ( in != MAX_TEMP_THRESH ) {
02873                 EFAB_ERR ( "Unable to verify MAX6647 limit (requested=%d "
02874                            "confirmed=%d)\n", cfg, in );
02875                 rc = -EIO;
02876                 goto fail3;
02877         }
02878 
02879         /* Clear any previous over-temperature alert */
02880         rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
02881         if ( rc )
02882                 goto fail4;
02883 
02884         /* Enable port 0 and 1 outputs on IO expander */
02885         cfg = 0x00;
02886         rc = i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
02887         if ( rc )
02888                 goto fail5;
02889         cfg = 0xff & ~(1 << P1_SPARE_LBN);
02890         rc = i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
02891         if ( rc )
02892                 goto fail6;
02893 
02894         /* Turn all power off then wait 1 sec. This ensures PHY is reset */
02895         out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) |
02896                        (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) |
02897                        (0 << P0_EN_1V0X_LBN));
02898 
02899         rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
02900         if ( rc )
02901                 goto fail7;
02902 
02903         mdelay(1000);
02904 
02905         for (count=0; count<20; count++) {
02906                 /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */
02907                 out = 0xff & ~( (1 << P0_EN_1V2_LBN)  | (1 << P0_EN_2V5_LBN) |
02908                                 (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN)  | 
02909                                 (1 << P0_X_TRST_LBN) );
02910 
02911                 rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
02912                 if ( rc )
02913                         goto fail8;
02914 
02915                 mdelay ( 10 );
02916                 
02917                 /* Turn on the 1V power rail */
02918                 out  &= ~( 1 << P0_EN_1V0X_LBN );
02919                 rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
02920                 if ( rc )
02921                         goto fail9;
02922 
02923                 EFAB_LOG ( "Waiting for power...(attempt %d)\n", count);
02924                 mdelay ( 1000 );
02925 
02926                 /* Check DSP is powered */
02927                 rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE );
02928                 if ( rc )
02929                         goto fail10;
02930 
02931                 if ( in & ( 1 << P1_AFE_PWD_LBN ) )
02932                         return 0;
02933         }
02934 
02935         rc = -ETIMEDOUT;
02936 
02937 fail10:
02938 fail9:
02939 fail8:
02940 fail7:
02941         /* Turn off power rails */
02942         out = 0xff;
02943         (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
02944         /* Disable port 1 outputs on IO expander */
02945         out = 0xff;
02946         (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
02947 fail6:
02948         /* Disable port 0 outputs */
02949         out = 0xff;
02950         (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
02951 fail5:
02952 fail4:
02953 fail3:
02954 fail2:
02955 fail1:
02956         EFAB_ERR ( "Failed initialising SFE4001 board\n" );
02957         return rc;
02958 }
02959 
02960 static void
02961 sfe4001_fini ( struct efab_nic *efab )
02962 {
02963         struct i2c_interface *i2c = &efab->i2c_bb.i2c;
02964         uint8_t in, cfg, out;
02965 
02966         EFAB_ERR ( "Turning off SFE4001\n" );
02967 
02968         /* Turn off all power rails */
02969         out = 0xff;
02970         (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
02971 
02972         /* Disable port 1 outputs on IO expander */
02973         cfg = 0xff;
02974         (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
02975 
02976         /* Disable port 0 outputs on IO expander */
02977         cfg = 0xff;
02978         (void) i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
02979 
02980         /* Clear any over-temperature alert */
02981         (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
02982 }
02983 
02984 struct efab_board_operations sfe4001_ops = {
02985         .init           = sfe4001_init,
02986         .fini           = sfe4001_fini,
02987 };
02988 
02989 static int sfe4002_init ( struct efab_nic *efab __attribute__((unused)) )
02990 {
02991         return 0;
02992 }
02993 static void sfe4002_fini ( struct efab_nic *efab __attribute__((unused)) )
02994 {
02995 }
02996 
02997 struct efab_board_operations sfe4002_ops = {
02998         .init           = sfe4002_init,
02999         .fini           = sfe4002_fini,
03000 };
03001 
03002 static int sfe4003_init ( struct efab_nic *efab __attribute__((unused)) )
03003 {
03004         return 0;
03005 }
03006 static void sfe4003_fini ( struct efab_nic *efab __attribute__((unused)) )
03007 {
03008 }
03009 
03010 struct efab_board_operations sfe4003_ops = {
03011         .init           = sfe4003_init,
03012         .fini           = sfe4003_fini,
03013 };
03014 
03015 /*******************************************************************************
03016  *
03017  *
03018  * Hardware initialisation
03019  *
03020  *
03021  *******************************************************************************/ 
03022 
03023 static void
03024 falcon_free_special_buffer ( void *p )
03025 {
03026         /* We don't bother cleaning up the buffer table entries -
03027          * we're hardly limited */
03028         free_dma ( p, EFAB_BUF_ALIGN );
03029 }
03030 
03031 static void*
03032 falcon_alloc_special_buffer ( struct efab_nic *efab, int bytes,
03033                               struct efab_special_buffer *entry )
03034 {
03035         void* buffer;
03036         int remaining;
03037         efab_qword_t buf_desc;
03038         unsigned long dma_addr;
03039 
03040         /* Allocate the buffer, aligned on a buffer address boundary */
03041         buffer = malloc_dma ( bytes, EFAB_BUF_ALIGN );
03042         if ( ! buffer )
03043                 return NULL;
03044 
03045         /* Push buffer table entries to back the buffer */
03046         entry->id = efab->buffer_head;
03047         entry->dma_addr = dma_addr = virt_to_bus ( buffer );
03048         assert ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 );
03049 
03050         remaining = bytes;
03051         while ( remaining > 0 ) {
03052                 EFAB_POPULATE_QWORD_3 ( buf_desc,
03053                                         FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K,
03054                                         FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ),
03055                                         FCN_BUF_OWNER_ID_FBUF, 0 );
03056 
03057                 falcon_write_sram ( efab, &buf_desc, efab->buffer_head );
03058 
03059                 ++efab->buffer_head;
03060                 dma_addr += EFAB_BUF_ALIGN;
03061                 remaining -= EFAB_BUF_ALIGN;
03062         }
03063 
03064         EFAB_TRACE ( "Allocated 0x%x bytes at %p backed by buffer table "
03065                      "entries 0x%x..0x%x\n", bytes, buffer, entry->id,
03066                      efab->buffer_head - 1 );
03067 
03068         return buffer;
03069 }
03070 
03071 static void
03072 clear_b0_fpga_memories ( struct efab_nic *efab)
03073 {
03074         efab_oword_t blanko, temp;
03075         int offset; 
03076 
03077         EFAB_ZERO_OWORD ( blanko );
03078 
03079         /* Clear the address region register */
03080         EFAB_POPULATE_OWORD_4 ( temp,
03081                                 FCN_ADR_REGION0, 0,
03082                                 FCN_ADR_REGION1, ( 1 << 16 ),
03083                                 FCN_ADR_REGION2, ( 2 << 16 ),
03084                                 FCN_ADR_REGION3, ( 3 << 16 ) );
03085         falcon_write ( efab, &temp, FCN_ADR_REGION_REG_KER );
03086         
03087         EFAB_TRACE ( "Clearing filter and RSS tables\n" );
03088 
03089         for ( offset = FCN_RX_FILTER_TBL0 ;
03090               offset < FCN_RX_RSS_INDIR_TBL_B0+0x800 ;
03091               offset += 0x10 ) {
03092                 falcon_write ( efab, &blanko, offset );
03093         }
03094 
03095         EFAB_TRACE ( "Wiping buffer tables\n" );
03096 
03097         /* Notice the 8 byte access mode */
03098         for ( offset = 0x2800000 ;
03099               offset < 0x3000000 ;
03100               offset += 0x8) {
03101                 _falcon_writel ( efab, 0, offset );
03102                 _falcon_writel ( efab, 0, offset + 4 );
03103                 wmb();
03104         }
03105 }
03106 
03107 static int
03108 falcon_reset ( struct efab_nic *efab )
03109 {
03110         efab_oword_t glb_ctl_reg_ker;
03111 
03112         /* Initiate software reset */
03113         EFAB_POPULATE_OWORD_6 ( glb_ctl_reg_ker,
03114                                 FCN_PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
03115                                 FCN_PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
03116                                 FCN_PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
03117                                 FCN_EE_RST_CTL, EXCLUDE_FROM_RESET,
03118                                 FCN_EXT_PHY_RST_DUR, 0x7, /* 10ms */
03119                                 FCN_SWRST, 1 );
03120 
03121         falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
03122 
03123         /* Allow 50ms for reset */
03124         mdelay ( 50 );
03125 
03126         /* Check for device reset complete */
03127         falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
03128         if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) {
03129                 EFAB_ERR ( "Reset failed\n" );
03130                 return -ETIMEDOUT;
03131         }
03132 
03133         if ( ( efab->pci_revision == FALCON_REV_B0 ) && !efab->is_asic ) {
03134                 clear_b0_fpga_memories ( efab );
03135         }
03136 
03137         return 0;
03138 }
03139 
03140 /** Offset of MAC address within EEPROM or Flash */
03141 #define FALCON_MAC_ADDRESS_OFFSET 0x310
03142 
03143 /*
03144  * Falcon EEPROM structure
03145  */
03146 #define SF_NV_CONFIG_BASE 0x300
03147 #define SF_NV_CONFIG_EXTRA 0xA0
03148 
03149 struct falcon_nv_config_ver2 {
03150         uint16_t nports;
03151         uint8_t  port0_phy_addr;
03152         uint8_t  port0_phy_type;
03153         uint8_t  port1_phy_addr;
03154         uint8_t  port1_phy_type;
03155         uint16_t asic_sub_revision;
03156         uint16_t board_revision;
03157         uint8_t mac_location;
03158 };
03159 
03160 struct falcon_nv_extra {
03161         uint16_t magicnumber;
03162         uint16_t structure_version;
03163         uint16_t checksum;
03164         union {
03165                 struct falcon_nv_config_ver2 ver2;
03166         } ver_specific;
03167 };
03168 
03169 #define BOARD_TYPE(_rev) (_rev >> 8)
03170 
03171 static void
03172 falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci )
03173 {
03174         efab_oword_t altera_build, nic_stat;
03175         int fpga_version;
03176         uint8_t revision;
03177 
03178         /* PCI revision */
03179         pci_read_config_byte ( pci, PCI_REVISION, &revision );
03180         efab->pci_revision = revision;
03181 
03182         /* Asic vs FPGA */
03183         falcon_read ( efab, &altera_build, FCN_ALTERA_BUILD_REG_KER );
03184         fpga_version = EFAB_OWORD_FIELD ( altera_build, FCN_VER_ALL );
03185         efab->is_asic = (fpga_version == 0);
03186 
03187         /* MAC and PCI type */
03188         falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
03189         if ( efab->pci_revision == FALCON_REV_B0 ) {
03190                 efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
03191         }
03192         else if ( efab->is_asic ) {
03193                 efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
03194         }
03195         else {
03196                 int minor = EFAB_OWORD_FIELD ( altera_build,  FCN_VER_MINOR );
03197                 efab->phy_10g = ( minor == 0x14 );
03198         }
03199 }
03200 
03201 static void
03202 falcon_init_spi_device ( struct efab_nic *efab, struct spi_device *spi )
03203 {
03204         /* Falcon's SPI interface only supports reads/writes of up to 16 bytes.
03205          * Reduce the nvs block size down to satisfy this - which means callers
03206          * should use the nvs_* functions rather than spi_*. */
03207         if ( spi->nvs.block_size > FALCON_SPI_MAX_LEN )
03208                 spi->nvs.block_size = FALCON_SPI_MAX_LEN;
03209 
03210         spi->bus = &efab->spi_bus;
03211         efab->spi = spi;
03212 }
03213 
03214 static int
03215 falcon_probe_spi ( struct efab_nic *efab )
03216 {
03217         efab_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
03218         int has_flash, has_eeprom, ad9bit;
03219 
03220         falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
03221         falcon_read ( efab, &gpio_ctl, FCN_GPIO_CTL_REG_KER );
03222         falcon_read ( efab, &ee_vpd_cfg, FCN_EE_VPD_CFG_REG );
03223 
03224         /* determine if FLASH / EEPROM is present */
03225         if ( ( efab->pci_revision >= FALCON_REV_B0 ) || efab->is_asic ) {
03226                 has_flash = EFAB_OWORD_FIELD ( nic_stat, FCN_SF_PRST );
03227                 has_eeprom = EFAB_OWORD_FIELD ( nic_stat, FCN_EE_PRST );
03228         } else {
03229                 has_flash = EFAB_OWORD_FIELD ( gpio_ctl, FCN_FLASH_PRESENT );
03230                 has_eeprom = EFAB_OWORD_FIELD ( gpio_ctl, FCN_EEPROM_PRESENT );
03231         }
03232         ad9bit = EFAB_OWORD_FIELD ( ee_vpd_cfg, FCN_EE_VPD_EN_AD9_MODE );
03233 
03234         /* Configure the SPI and I2C bus */
03235         efab->spi_bus.rw = falcon_spi_rw;
03236         init_i2c_bit_basher ( &efab->i2c_bb, &falcon_i2c_bit_ops );
03237 
03238         /* Configure the EEPROM SPI device. Generally, an Atmel 25040
03239          * (or similar) is used, but this is only possible if there is also
03240          * a flash device present to store the boot-time chip configuration.
03241          */
03242         if ( has_eeprom ) {
03243                 if ( has_flash && ad9bit )
03244                         init_at25040 ( &efab->spi_eeprom );
03245                 else
03246                         init_mc25xx640 ( &efab->spi_eeprom );
03247                 falcon_init_spi_device ( efab, &efab->spi_eeprom );
03248         }
03249 
03250         /* Configure the FLASH SPI device */
03251         if ( has_flash ) {
03252                 init_at25f1024 ( &efab->spi_flash );
03253                 falcon_init_spi_device ( efab, &efab->spi_flash );
03254         }
03255 
03256         EFAB_LOG ( "flash is %s, EEPROM is %s%s\n",
03257                    ( has_flash ? "present" : "absent" ),
03258                    ( has_eeprom ? "present " : "absent" ),
03259                    ( has_eeprom ? (ad9bit ? "(9bit)" : "(16bit)") : "") );
03260 
03261         /* The device MUST have flash or eeprom */
03262         if ( ! efab->spi ) {
03263                 EFAB_ERR ( "Device appears to have no flash or eeprom\n" );
03264                 return -EIO;
03265         }
03266 
03267         /* If the device has EEPROM attached, then advertise NVO space */
03268         if ( has_eeprom ) {
03269                 nvo_init ( &efab->nvo, &efab->spi_eeprom.nvs, 0x100, 0xf0,
03270                            NULL, &efab->netdev->refcnt );
03271         }
03272 
03273         return 0;
03274 }
03275 
03276 static int
03277 falcon_probe_nvram ( struct efab_nic *efab )
03278 {
03279         struct nvs_device *nvs = &efab->spi->nvs;
03280         struct falcon_nv_extra nv;
03281         int rc, board_revision;
03282 
03283         /* Read the MAC address */
03284         rc = nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET,
03285                         efab->mac_addr, ETH_ALEN );
03286         if ( rc )
03287                 return rc;
03288 
03289         /* Poke through the NVRAM structure for the PHY type. */
03290         rc = nvs_read ( nvs, SF_NV_CONFIG_BASE + SF_NV_CONFIG_EXTRA,
03291                         &nv, sizeof ( nv ) );
03292         if ( rc )
03293                 return rc;
03294 
03295         /* Handle each supported NVRAM version */
03296         if ( ( le16_to_cpu ( nv.magicnumber ) == FCN_NV_MAGIC_NUMBER ) &&
03297              ( le16_to_cpu ( nv.structure_version ) >= 2 ) ) {
03298                 struct falcon_nv_config_ver2* ver2 = &nv.ver_specific.ver2;
03299                 
03300                 /* Get the PHY type */
03301                 efab->phy_addr = le16_to_cpu ( ver2->port0_phy_addr );
03302                 efab->phy_type = le16_to_cpu ( ver2->port0_phy_type );
03303                 board_revision = le16_to_cpu ( ver2->board_revision );
03304         }
03305         else {
03306                 EFAB_ERR ( "NVram is not recognised\n" );
03307                 return -EINVAL;
03308         }
03309 
03310         efab->board_type = BOARD_TYPE ( board_revision );
03311         
03312         EFAB_TRACE ( "Falcon board %d phy %d @ addr %d\n",
03313                      efab->board_type, efab->phy_type, efab->phy_addr );
03314 
03315         /* Patch in the board operations */
03316         switch ( efab->board_type ) {
03317         case EFAB_BOARD_SFE4001:
03318                 efab->board_op = &sfe4001_ops;
03319                 break;
03320         case EFAB_BOARD_SFE4002:
03321                 efab->board_op = &sfe4002_ops;
03322                 break;
03323         case EFAB_BOARD_SFE4003:
03324                 efab->board_op = &sfe4003_ops;
03325                 break;
03326         default:
03327                 EFAB_ERR ( "Unrecognised board type\n" );
03328                 return -EINVAL;
03329         }
03330 
03331         /* Patch in MAC operations */
03332         if ( efab->phy_10g )
03333                 efab->mac_op = &falcon_xmac_operations;
03334         else
03335                 efab->mac_op = &falcon_gmac_operations;
03336 
03337         /* Hook in the PHY ops */
03338         switch ( efab->phy_type ) {
03339         case PHY_TYPE_10XPRESS:
03340                 efab->phy_op = &falcon_tenxpress_phy_ops;
03341                 break;
03342         case PHY_TYPE_CX4:
03343                 efab->phy_op = &falcon_xaui_phy_ops;
03344                 break;
03345         case PHY_TYPE_XFP:
03346                 efab->phy_op = &falcon_xfp_phy_ops;
03347                 break;
03348         case PHY_TYPE_CX4_RTMR:
03349                 efab->phy_op = &falcon_txc_phy_ops;
03350                 break;
03351         case PHY_TYPE_PM8358:
03352                 efab->phy_op = &falcon_pm8358_phy_ops;
03353                 break;
03354         case PHY_TYPE_1GIG_ALASKA:
03355                 efab->phy_op = &falcon_alaska_phy_ops;
03356                 break;
03357         default:
03358                 EFAB_ERR ( "Unknown PHY type: %d\n", efab->phy_type );
03359                 return -EINVAL;
03360         }
03361 
03362         return 0;
03363 }
03364 
03365 static int
03366 falcon_init_sram ( struct efab_nic *efab )
03367 {
03368         efab_oword_t reg;
03369         int count;
03370 
03371         /* use card in internal SRAM mode */
03372         falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
03373         EFAB_SET_OWORD_FIELD ( reg, FCN_ONCHIP_SRAM, 1 );
03374         falcon_write ( efab, &reg, FCN_NIC_STAT_REG );
03375 
03376         /* Deactivate any external SRAM that might be present */
03377         EFAB_POPULATE_OWORD_2 ( reg, 
03378                                 FCN_GPIO1_OEN, 1,
03379                                 FCN_GPIO1_OUT, 1 );
03380         falcon_write ( efab, &reg, FCN_GPIO_CTL_REG_KER );
03381 
03382         /* Initiate SRAM reset */
03383         EFAB_POPULATE_OWORD_2 ( reg,
03384                                 FCN_SRAM_OOB_BT_INIT_EN, 1,
03385                                 FCN_SRM_NUM_BANKS_AND_BANK_SIZE, 0 );
03386         falcon_write ( efab, &reg, FCN_SRM_CFG_REG_KER );
03387 
03388         /* Wait for SRAM reset to complete */
03389         count = 0;
03390         do {
03391                 /* SRAM reset is slow; expect around 16ms */
03392                 mdelay ( 20 );
03393 
03394                 /* Check for reset complete */
03395                 falcon_read ( efab, &reg, FCN_SRM_CFG_REG_KER );
03396                 if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) )
03397                         return 0;
03398         } while (++count < 20); /* wait up to 0.4 sec */
03399 
03400         EFAB_ERR ( "timed out waiting for SRAM reset\n");
03401         return -ETIMEDOUT;
03402 }
03403 
03404 static void
03405 falcon_setup_nic ( struct efab_nic *efab )
03406 {
03407         efab_dword_t timer_cmd;
03408         efab_oword_t reg;
03409         int tx_fc, xoff_thresh, xon_thresh;
03410 
03411         /* bug5129: Clear the parity enables on the TX data fifos as 
03412          * they produce false parity errors because of timing issues 
03413          */
03414         falcon_read ( efab, &reg, FCN_SPARE_REG_KER );
03415         EFAB_SET_OWORD_FIELD ( reg, FCN_MEM_PERR_EN_TX_DATA, 0 );
03416         falcon_write ( efab, &reg, FCN_SPARE_REG_KER );
03417         
03418         /* Set up TX and RX descriptor caches in SRAM */
03419         EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR, 0x130000 );
03420         falcon_write ( efab, &reg, FCN_SRM_TX_DC_CFG_REG_KER );
03421         EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 1 /* 16 descriptors */ );
03422         falcon_write ( efab, &reg, FCN_TX_DC_CFG_REG_KER );
03423         EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR, 0x100000 );
03424         falcon_write ( efab, &reg, FCN_SRM_RX_DC_CFG_REG_KER );
03425         EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ );
03426         falcon_write ( efab, &reg, FCN_RX_DC_CFG_REG_KER );
03427         
03428         /* Set number of RSS CPUs
03429          * bug7244: Increase filter depth to reduce RX_RESET likelihood
03430          */
03431         EFAB_POPULATE_OWORD_5 ( reg,
03432                                 FCN_NUM_KER, 0,
03433                                 FCN_UDP_FULL_SRCH_LIMIT, 8,
03434                                 FCN_UDP_WILD_SRCH_LIMIT, 8,
03435                                 FCN_TCP_WILD_SRCH_LIMIT, 8,
03436                                 FCN_TCP_FULL_SRCH_LIMIT, 8);
03437         falcon_write ( efab, &reg, FCN_RX_FILTER_CTL_REG_KER );
03438         udelay ( 1000 );
03439 
03440         /* Setup RX.  Wait for descriptor is broken and must
03441          * be disabled.  RXDP recovery shouldn't be needed, but is.
03442          * disable ISCSI parsing because we don't need it
03443          */
03444         falcon_read ( efab, &reg, FCN_RX_SELF_RST_REG_KER );
03445         EFAB_SET_OWORD_FIELD ( reg, FCN_RX_NODESC_WAIT_DIS, 1 );
03446         EFAB_SET_OWORD_FIELD ( reg, FCN_RX_RECOVERY_EN, 1 );
03447         EFAB_SET_OWORD_FIELD ( reg, FCN_RX_ISCSI_DIS, 1 );
03448         falcon_write ( efab, &reg, FCN_RX_SELF_RST_REG_KER );
03449         
03450         /* Determine recommended flow control settings. *
03451          * Flow control is qualified on B0 and A1/1G, not on A1/10G */
03452         if ( efab->pci_revision == FALCON_REV_B0 ) {
03453                 tx_fc = 1;
03454                 xoff_thresh = 54272;  /* ~80Kb - 3*max MTU */
03455                 xon_thresh = 27648; /* ~3*max MTU */
03456         }
03457         else if ( !efab->phy_10g ) {
03458                 tx_fc = 1;
03459                 xoff_thresh = 2048;
03460                 xon_thresh = 512;
03461         }
03462         else {
03463                 tx_fc = xoff_thresh = xon_thresh = 0;
03464         }
03465 
03466         /* Setup TX and RX */
03467         falcon_read ( efab, &reg, FCN_TX_CFG2_REG_KER );
03468         EFAB_SET_OWORD_FIELD ( reg, FCN_TX_DIS_NON_IP_EV, 1 );
03469         falcon_write ( efab, &reg, FCN_TX_CFG2_REG_KER );
03470 
03471         falcon_read ( efab, &reg, FCN_RX_CFG_REG_KER );
03472         EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_USR_BUF_SIZE,
03473                                    (3*4096) / 32 );
03474         if ( efab->pci_revision == FALCON_REV_B0)
03475                 EFAB_SET_OWORD_FIELD ( reg, FCN_RX_INGR_EN_B0, 1 );
03476         EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XON_MAC_TH,
03477                                    xon_thresh / 256);
03478         EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_TH,
03479                                    xoff_thresh / 256);
03480         EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_EN, tx_fc);
03481         falcon_write ( efab, &reg, FCN_RX_CFG_REG_KER );
03482 
03483         /* Set timer register */
03484         EFAB_POPULATE_DWORD_2 ( timer_cmd,
03485                                 FCN_TIMER_MODE, FCN_TIMER_MODE_DIS,
03486                                 FCN_TIMER_VAL, 0 );
03487         falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER );
03488 }
03489 
03490 static void
03491 falcon_init_resources ( struct efab_nic *efab )
03492 {
03493         struct efab_ev_queue *ev_queue = &efab->ev_queue;
03494         struct efab_rx_queue *rx_queue = &efab->rx_queue;
03495         struct efab_tx_queue *tx_queue = &efab->tx_queue;
03496 
03497         efab_oword_t reg;
03498         int jumbo;
03499 
03500         /* Initialise the ptrs */
03501         tx_queue->read_ptr = tx_queue->write_ptr = 0;
03502         rx_queue->read_ptr = rx_queue->write_ptr = 0;
03503         ev_queue->read_ptr = 0;
03504 
03505         /* Push the event queue to the hardware */
03506         EFAB_POPULATE_OWORD_3 ( reg,
03507                                 FCN_EVQ_EN, 1,
03508                                 FCN_EVQ_SIZE, FQS(FCN_EVQ, EFAB_EVQ_SIZE),
03509                                 FCN_EVQ_BUF_BASE_ID, ev_queue->entry.id );
03510         falcon_write ( efab, &reg, 
03511                        FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
03512         
03513         /* Push the tx queue to the hardware */
03514         EFAB_POPULATE_OWORD_8 ( reg,
03515                                 FCN_TX_DESCQ_EN, 1,
03516                                 FCN_TX_ISCSI_DDIG_EN, 0,
03517                                 FCN_TX_ISCSI_DDIG_EN, 0,
03518                                 FCN_TX_DESCQ_BUF_BASE_ID, tx_queue->entry.id,
03519                                 FCN_TX_DESCQ_EVQ_ID, 0,
03520                                 FCN_TX_DESCQ_SIZE, FQS(FCN_TX_DESCQ, EFAB_TXD_SIZE),
03521                                 FCN_TX_DESCQ_TYPE, 0 /* kernel queue */,
03522                                 FCN_TX_NON_IP_DROP_DIS_B0, 1 );
03523         falcon_write ( efab, &reg, 
03524                        FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
03525         
03526         /* Push the rx queue to the hardware */
03527         jumbo = ( efab->pci_revision == FALCON_REV_B0 ) ? 0 : 1;
03528         EFAB_POPULATE_OWORD_8 ( reg,
03529                                 FCN_RX_ISCSI_DDIG_EN, 0,
03530                                 FCN_RX_ISCSI_HDIG_EN, 0,
03531                                 FCN_RX_DESCQ_BUF_BASE_ID, rx_queue->entry.id,
03532                                 FCN_RX_DESCQ_EVQ_ID, 0,
03533                                 FCN_RX_DESCQ_SIZE, FQS(FCN_RX_DESCQ, EFAB_RXD_SIZE),
03534                                 FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
03535                                 FCN_RX_DESCQ_JUMBO, jumbo,
03536                                 FCN_RX_DESCQ_EN, 1 );
03537         falcon_write ( efab, &reg,
03538                        FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
03539 
03540         /* Program INT_ADR_REG_KER */
03541         EFAB_POPULATE_OWORD_1 ( reg,
03542                                 FCN_INT_ADR_KER, virt_to_bus ( &efab->int_ker ) );
03543         falcon_write ( efab, &reg, FCN_INT_ADR_REG_KER );
03544 
03545         /* Ack the event queue */
03546         falcon_eventq_read_ack ( efab, ev_queue );
03547 }
03548 
03549 static void
03550 falcon_fini_resources ( struct efab_nic *efab )
03551 {
03552         efab_oword_t cmd;
03553         
03554         /* Disable interrupts */
03555         falcon_interrupts ( efab, 0, 0 );
03556 
03557         /* Flush the dma queues */
03558         EFAB_POPULATE_OWORD_2 ( cmd,
03559                                 FCN_TX_FLUSH_DESCQ_CMD, 1,
03560                                 FCN_TX_FLUSH_DESCQ, 0 );
03561         falcon_write ( efab, &cmd, 
03562                        FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
03563 
03564         EFAB_POPULATE_OWORD_2 ( cmd,
03565                                 FCN_RX_FLUSH_DESCQ_CMD, 1,
03566                                 FCN_RX_FLUSH_DESCQ, 0 );
03567         falcon_write ( efab, &cmd,
03568                        FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
03569 
03570         mdelay ( 100 );
03571 
03572         /* Remove descriptor rings from card */
03573         EFAB_ZERO_OWORD ( cmd );
03574         falcon_write ( efab, &cmd, 
03575                        FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
03576         falcon_write ( efab, &cmd, 
03577                        FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
03578         falcon_write ( efab, &cmd, 
03579                        FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
03580 }
03581 
03582 /*******************************************************************************
03583  *
03584  *
03585  * Hardware rx path
03586  *
03587  *
03588  *******************************************************************************/
03589 
03590 static void
03591 falcon_build_rx_desc ( falcon_rx_desc_t *rxd, struct io_buffer *iob )
03592 {
03593         EFAB_POPULATE_QWORD_2 ( *rxd,
03594                                 FCN_RX_KER_BUF_SIZE, EFAB_RX_BUF_SIZE,
03595                                 FCN_RX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
03596 }
03597 
03598 static void
03599 falcon_notify_rx_desc ( struct efab_nic *efab, struct efab_rx_queue *rx_queue )
03600 {
03601         efab_dword_t reg;
03602         int ptr = rx_queue->write_ptr % EFAB_RXD_SIZE;
03603 
03604         EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD, ptr );
03605         falcon_writel ( efab, &reg, FCN_RX_DESC_UPD_REG_KER_DWORD );
03606 }
03607 
03608 
03609 /*******************************************************************************
03610  *
03611  *
03612  * Hardware tx path
03613  *
03614  *
03615  *******************************************************************************/
03616 
03617 static void
03618 falcon_build_tx_desc ( falcon_tx_desc_t *txd, struct io_buffer *iob )
03619 {
03620         EFAB_POPULATE_QWORD_2 ( *txd,
03621                                 FCN_TX_KER_BYTE_CNT, iob_len ( iob ),
03622                                 FCN_TX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
03623 }
03624 
03625 static void
03626 falcon_notify_tx_desc ( struct efab_nic *efab,
03627                         struct efab_tx_queue *tx_queue )
03628 {
03629         efab_dword_t reg;
03630         int ptr = tx_queue->write_ptr % EFAB_TXD_SIZE;
03631 
03632         EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD, ptr );
03633         falcon_writel ( efab, &reg, FCN_TX_DESC_UPD_REG_KER_DWORD );
03634 }
03635 
03636 
03637 /*******************************************************************************
03638  *
03639  *
03640  * Software receive interface
03641  *
03642  *
03643  *******************************************************************************/ 
03644 
03645 static int
03646 efab_fill_rx_queue ( struct efab_nic *efab,
03647                      struct efab_rx_queue *rx_queue )
03648 {
03649         int fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
03650         int space = EFAB_NUM_RX_DESC - fill_level - 1;
03651         int pushed = 0;
03652 
03653         while ( space ) {
03654                 int buf_id = rx_queue->write_ptr % EFAB_NUM_RX_DESC;
03655                 int desc_id = rx_queue->write_ptr % EFAB_RXD_SIZE;
03656                 struct io_buffer *iob;
03657                 falcon_rx_desc_t *rxd;
03658 
03659                 assert ( rx_queue->buf[buf_id] == NULL );
03660                 iob = alloc_iob ( EFAB_RX_BUF_SIZE );
03661                 if ( !iob )
03662                         break;
03663 
03664                 EFAB_TRACE ( "pushing rx_buf[%d] iob %p data %p\n",
03665                              buf_id, iob, iob->data );
03666 
03667                 rx_queue->buf[buf_id] = iob;
03668                 rxd = rx_queue->ring + desc_id;
03669                 falcon_build_rx_desc ( rxd, iob );
03670                 ++rx_queue->write_ptr;
03671                 ++pushed;
03672                 --space;
03673         }
03674 
03675         if ( pushed ) {
03676                 /* Push the ptr to hardware */
03677                 falcon_notify_rx_desc ( efab, rx_queue );
03678 
03679                 fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
03680                 EFAB_TRACE ( "pushed %d rx buffers to fill level %d\n",
03681                              pushed, fill_level );
03682         }
03683 
03684         if ( fill_level == 0 )
03685                 return -ENOMEM;
03686         return 0;
03687 }
03688         
03689 static void
03690 efab_receive ( struct efab_nic *efab, unsigned int id, int len, int drop )
03691 {
03692         struct efab_rx_queue *rx_queue = &efab->rx_queue;
03693         struct io_buffer *iob;
03694         unsigned int read_ptr = rx_queue->read_ptr % EFAB_RXD_SIZE;
03695         unsigned int buf_ptr = rx_queue->read_ptr % EFAB_NUM_RX_DESC;
03696 
03697         assert ( id == read_ptr );
03698         
03699         /* Pop this rx buffer out of the software ring */
03700         iob = rx_queue->buf[buf_ptr];
03701         rx_queue->buf[buf_ptr] = NULL;
03702 
03703         EFAB_TRACE ( "popping rx_buf[%d] iob %p data %p with %d bytes %s\n",
03704                      id, iob, iob->data, len, drop ? "bad" : "ok" );
03705 
03706         /* Pass the packet up if required */
03707         if ( drop )
03708                 free_iob ( iob );
03709         else {
03710                 iob_put ( iob, len );
03711                 netdev_rx ( efab->netdev, iob );
03712         }
03713 
03714         ++rx_queue->read_ptr;
03715 }
03716 
03717 /*******************************************************************************
03718  *
03719  *
03720  * Software transmit interface
03721  *
03722  *
03723  *******************************************************************************/ 
03724 
03725 static int
03726 efab_transmit ( struct net_device *netdev, struct io_buffer *iob )
03727 {
03728         struct efab_nic *efab = netdev_priv ( netdev );
03729         struct efab_tx_queue *tx_queue = &efab->tx_queue;
03730         int fill_level, space;
03731         falcon_tx_desc_t *txd;
03732         int buf_id;
03733 
03734         fill_level = tx_queue->write_ptr - tx_queue->read_ptr;
03735         space = EFAB_TXD_SIZE - fill_level - 1;
03736         if ( space < 1 )
03737                 return -ENOBUFS;
03738 
03739         /* Save the iobuffer for later completion */
03740         buf_id = tx_queue->write_ptr % EFAB_TXD_SIZE;
03741         assert ( tx_queue->buf[buf_id] == NULL );
03742         tx_queue->buf[buf_id] = iob;
03743 
03744         EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n",
03745                      buf_id, iob, iob->data, iob_len ( iob ) );
03746 
03747         /* Form the descriptor, and push it to hardware */
03748         txd = tx_queue->ring + buf_id;
03749         falcon_build_tx_desc ( txd, iob );
03750         ++tx_queue->write_ptr;
03751         falcon_notify_tx_desc ( efab, tx_queue );
03752 
03753         return 0;
03754 }
03755 
03756 static int
03757 efab_transmit_done ( struct efab_nic *efab, int id )
03758 {
03759         struct efab_tx_queue *tx_queue = &efab->tx_queue;
03760         unsigned int read_ptr, stop;
03761 
03762         /* Complete all buffers from read_ptr up to and including id */
03763         read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
03764         stop = ( id + 1 ) % EFAB_TXD_SIZE;
03765 
03766         while ( read_ptr != stop ) {
03767                 struct io_buffer *iob = tx_queue->buf[read_ptr];
03768                 assert ( iob );
03769 
03770                 /* Complete the tx buffer */
03771                 if ( iob )
03772                         netdev_tx_complete ( efab->netdev, iob );
03773                 tx_queue->buf[read_ptr] = NULL;
03774                 
03775                 ++tx_queue->read_ptr;
03776                 read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
03777         }
03778 
03779         return 0;
03780 }
03781 
03782 /*******************************************************************************
03783  *
03784  *
03785  * Hardware event path
03786  *
03787  *
03788  *******************************************************************************/
03789 
03790 static void
03791 falcon_clear_interrupts ( struct efab_nic *efab )
03792 {
03793         efab_dword_t reg;
03794 
03795         if ( efab->pci_revision == FALCON_REV_B0 ) {
03796                 /* read the ISR */
03797                 falcon_readl( efab, &reg, INT_ISR0_B0 );
03798         }
03799         else {
03800                 /* write to the INT_ACK register */
03801                 EFAB_ZERO_DWORD ( reg );
03802                 falcon_writel ( efab, &reg, FCN_INT_ACK_KER_REG_A1 );
03803                 mb();
03804                 falcon_readl ( efab, &reg,
03805                                WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 );
03806         }
03807 }
03808 
03809 static void
03810 falcon_handle_event ( struct efab_nic *efab, falcon_event_t *evt )
03811 {
03812         int ev_code, desc_ptr, len, drop;
03813 
03814         /* Decode event */
03815         ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE );
03816         switch ( ev_code ) {
03817         case FCN_TX_IP_EV_DECODE:
03818                 desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_TX_EV_DESC_PTR );
03819                 efab_transmit_done ( efab, desc_ptr );
03820                 break;
03821         
03822         case FCN_RX_IP_EV_DECODE:
03823                 desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR );
03824                 len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT );
03825                 drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK );
03826 
03827                 efab_receive ( efab, desc_ptr, len, drop );
03828                 break;
03829 
03830         default:
03831                 EFAB_TRACE ( "Unknown event type %d\n", ev_code );
03832                 break;
03833         }
03834 }
03835 
03836 /*******************************************************************************
03837  *
03838  *
03839  * Software (polling) interrupt handler
03840  *
03841  *
03842  *******************************************************************************/
03843 
03844 static void
03845 efab_poll ( struct net_device *netdev )
03846 {
03847         struct efab_nic *efab = netdev_priv ( netdev );
03848         struct efab_ev_queue *ev_queue = &efab->ev_queue;
03849         struct efab_rx_queue *rx_queue = &efab->rx_queue;
03850         falcon_event_t *evt;
03851 
03852         /* Read the event queue by directly looking for events
03853          * (we don't even bother to read the eventq write ptr) */
03854         evt = ev_queue->ring + ev_queue->read_ptr;
03855         while ( falcon_event_present ( evt ) ) {
03856                 
03857                 EFAB_TRACE ( "Event at index 0x%x address %p is "
03858                              EFAB_QWORD_FMT "\n", ev_queue->read_ptr,
03859                              evt, EFAB_QWORD_VAL ( *evt ) );
03860                 
03861                 falcon_handle_event ( efab, evt );
03862                 
03863                 /* Clear the event */
03864                 EFAB_SET_QWORD ( *evt );
03865         
03866                 /* Move to the next event. We don't ack the event
03867                  * queue until the end */
03868                 ev_queue->read_ptr = ( ( ev_queue->read_ptr + 1 ) %
03869                                        EFAB_EVQ_SIZE );
03870                 evt = ev_queue->ring + ev_queue->read_ptr;
03871         }
03872 
03873         /* Push more buffers if needed */
03874         (void) efab_fill_rx_queue ( efab, rx_queue );
03875 
03876         /* Clear any pending interrupts */
03877         falcon_clear_interrupts ( efab );
03878 
03879         /* Ack the event queue */
03880         falcon_eventq_read_ack ( efab, ev_queue );
03881 }
03882 
03883 static void
03884 efab_irq ( struct net_device *netdev, int enable )
03885 {
03886         struct efab_nic *efab = netdev_priv ( netdev );
03887         struct efab_ev_queue *ev_queue = &efab->ev_queue;
03888 
03889         switch ( enable ) {
03890         case 0:
03891                 falcon_interrupts ( efab, 0, 0 );
03892                 break;
03893         case 1:
03894                 falcon_interrupts ( efab, 1, 0 );
03895                 falcon_eventq_read_ack ( efab, ev_queue );
03896                 break;
03897         case 2:
03898                 falcon_interrupts ( efab, 1, 1 );
03899                 break;
03900         }
03901 }
03902 
03903 /*******************************************************************************
03904  *
03905  *
03906  * Software open/close
03907  *
03908  *
03909  *******************************************************************************/
03910 
03911 static void
03912 efab_free_resources ( struct efab_nic *efab )
03913 {
03914         struct efab_ev_queue *ev_queue = &efab->ev_queue;
03915         struct efab_rx_queue *rx_queue = &efab->rx_queue;
03916         struct efab_tx_queue *tx_queue = &efab->tx_queue;
03917         int i;
03918 
03919         for ( i = 0; i < EFAB_NUM_RX_DESC; i++ ) {
03920                 if ( rx_queue->buf[i] )
03921                         free_iob ( rx_queue->buf[i] );
03922         }
03923 
03924         for ( i = 0; i < EFAB_TXD_SIZE; i++ ) {
03925                 if ( tx_queue->buf[i] )
03926                         netdev_tx_complete ( efab->netdev,  tx_queue->buf[i] );
03927         }
03928 
03929         if ( rx_queue->ring )
03930                 falcon_free_special_buffer ( rx_queue->ring );
03931 
03932         if ( tx_queue->ring )
03933                 falcon_free_special_buffer ( tx_queue->ring );
03934 
03935         if ( ev_queue->ring )
03936                 falcon_free_special_buffer ( ev_queue->ring );
03937 
03938         memset ( rx_queue, 0, sizeof ( *rx_queue ) );
03939         memset ( tx_queue, 0, sizeof ( *tx_queue ) );
03940         memset ( ev_queue, 0, sizeof ( *ev_queue ) );
03941 
03942         /* Ensure subsequent buffer allocations start at id 0 */
03943         efab->buffer_head = 0;
03944 }
03945 
03946 static int
03947 efab_alloc_resources ( struct efab_nic *efab )
03948 {
03949         struct efab_ev_queue *ev_queue = &efab->ev_queue;
03950         struct efab_rx_queue *rx_queue = &efab->rx_queue;
03951         struct efab_tx_queue *tx_queue = &efab->tx_queue;
03952         size_t bytes;
03953 
03954         /* Allocate the hardware event queue */
03955         bytes = sizeof ( falcon_event_t ) * EFAB_TXD_SIZE;
03956         ev_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
03957                                                        &ev_queue->entry );
03958         if ( !ev_queue->ring )
03959                 goto fail1;
03960 
03961         /* Initialise the hardware event queue */
03962         memset ( ev_queue->ring, 0xff, bytes );
03963 
03964         /* Allocate the hardware tx queue */
03965         bytes = sizeof ( falcon_tx_desc_t ) * EFAB_TXD_SIZE;
03966         tx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
03967                                                        &tx_queue->entry );
03968         if ( ! tx_queue->ring )
03969                 goto fail2;
03970 
03971         /* Allocate the hardware rx queue */
03972         bytes = sizeof ( falcon_rx_desc_t ) * EFAB_RXD_SIZE;
03973         rx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
03974                                                        &rx_queue->entry );
03975         if ( ! rx_queue->ring )
03976                 goto fail3;
03977 
03978         return 0;
03979 
03980 fail3:
03981         falcon_free_special_buffer ( tx_queue->ring );
03982         tx_queue->ring = NULL;
03983 fail2:
03984         falcon_free_special_buffer ( ev_queue->ring );
03985         ev_queue->ring = NULL;
03986 fail1:
03987         return -ENOMEM;
03988 }
03989 
03990 static int
03991 efab_init_mac ( struct efab_nic *efab )
03992 {
03993         int count, rc;
03994 
03995         /* This can take several seconds */
03996         EFAB_LOG ( "Waiting for link..\n" );
03997         for ( count=0; count<5; count++ ) {
03998                 rc = efab->mac_op->init ( efab );
03999                 if ( rc ) {
04000                         EFAB_ERR ( "Failed reinitialising MAC, error %s\n",
04001                                 strerror ( rc ));
04002                         return rc;
04003                 }
04004 
04005                 /* Sleep for 2s to wait for the link to settle, either
04006                  * because we want to use it, or because we're about
04007                  * to reset the mac anyway
04008                  */
04009                 mdelay ( 2000 );
04010 
04011                 if ( ! efab->link_up ) {
04012                         EFAB_ERR ( "!\n" );
04013                         continue;
04014                 }
04015 
04016                 EFAB_LOG ( "\n%dMbps %s-duplex\n",
04017                            ( efab->link_options & LPA_EF_10000 ? 10000 :
04018                              ( efab->link_options & LPA_EF_1000 ? 1000 :
04019                                ( efab->link_options & LPA_100 ? 100 : 10 ) ) ),
04020                            ( efab->link_options & LPA_EF_DUPLEX ?
04021                              "full" : "half" ) );
04022 
04023                 /* TODO: Move link state handling to the poll() routine */
04024                 netdev_link_up ( efab->netdev );
04025                 return 0;
04026         }
04027 
04028         EFAB_ERR ( "timed initialising MAC\n" );
04029         return -ETIMEDOUT;
04030 }
04031 
04032 static void
04033 efab_close ( struct net_device *netdev )
04034 {
04035         struct efab_nic *efab = netdev_priv ( netdev );
04036 
04037         falcon_fini_resources ( efab );
04038         efab_free_resources ( efab );
04039         efab->board_op->fini ( efab );
04040         falcon_reset ( efab );
04041 }
04042 
04043 static int
04044 efab_open ( struct net_device *netdev )
04045 {
04046         struct efab_nic *efab = netdev_priv ( netdev );
04047         struct efab_rx_queue *rx_queue = &efab->rx_queue;
04048         int rc;
04049 
04050         rc = falcon_reset ( efab );
04051         if ( rc )
04052                 goto fail1;
04053 
04054         rc = efab->board_op->init ( efab );
04055         if ( rc )
04056                 goto fail2;
04057         
04058         rc = falcon_init_sram ( efab );
04059         if ( rc )
04060                 goto fail3;
04061 
04062         /* Configure descriptor caches before pushing hardware queues */
04063         falcon_setup_nic ( efab );
04064 
04065         rc = efab_alloc_resources ( efab );
04066         if ( rc )
04067                 goto fail4;
04068         
04069         falcon_init_resources ( efab );
04070 
04071         /* Push rx buffers */
04072         rc = efab_fill_rx_queue ( efab, rx_queue );
04073         if ( rc )
04074                 goto fail5;
04075 
04076         /* Try and bring the interface up */
04077         rc = efab_init_mac ( efab );
04078         if ( rc )
04079                 goto fail6;
04080 
04081         return 0;
04082 
04083 fail6:
04084 fail5:
04085         efab_free_resources ( efab );
04086 fail4:
04087 fail3:
04088         efab->board_op->fini ( efab );
04089 fail2:
04090         falcon_reset ( efab );
04091 fail1:
04092         return rc;
04093 }
04094 
04095 static struct net_device_operations efab_operations = {
04096         .open           = efab_open,
04097         .close          = efab_close,
04098         .transmit       = efab_transmit,
04099         .poll           = efab_poll,
04100         .irq            = efab_irq,
04101 };
04102 
04103 static void
04104 efab_remove ( struct pci_device *pci )
04105 {
04106         struct net_device *netdev = pci_get_drvdata ( pci );
04107         struct efab_nic *efab = netdev_priv ( netdev );
04108 
04109         if ( efab->membase ) {
04110                 falcon_reset ( efab );
04111 
04112                 iounmap ( efab->membase );
04113                 efab->membase = NULL;
04114         }
04115 
04116         if ( efab->nvo.nvs ) {
04117                 unregister_nvo ( &efab->nvo );
04118                 efab->nvo.nvs = NULL;
04119         }
04120 
04121         unregister_netdev ( netdev );
04122         netdev_nullify ( netdev );
04123         netdev_put ( netdev );
04124 }
04125 
04126 static int
04127 efab_probe ( struct pci_device *pci )
04128 {
04129         struct net_device *netdev;
04130         struct efab_nic *efab;
04131         unsigned long mmio_start, mmio_len;
04132         int rc;
04133 
04134         /* Create the network adapter */
04135         netdev = alloc_etherdev ( sizeof ( struct efab_nic ) );
04136         if ( ! netdev ) {
04137                 rc = -ENOMEM;
04138                 goto fail1;
04139         }
04140 
04141         /* Initialise the network adapter, and initialise private storage */
04142         netdev_init ( netdev, &efab_operations );
04143         pci_set_drvdata ( pci, netdev );
04144         netdev->dev = &pci->dev;
04145 
04146         efab = netdev_priv ( netdev );
04147         memset ( efab, 0, sizeof ( *efab ) );
04148         efab->netdev = netdev;
04149 
04150         /* Get iobase/membase */
04151         mmio_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_2 );
04152         mmio_len = pci_bar_size ( pci, PCI_BASE_ADDRESS_2 );
04153         efab->membase = ioremap ( mmio_start, mmio_len );
04154         EFAB_TRACE ( "BAR of %lx bytes at phys %lx mapped at %p\n",
04155                      mmio_len, mmio_start, efab->membase );
04156 
04157         /* Enable the PCI device */
04158         adjust_pci_device ( pci );
04159         efab->iobase = pci->ioaddr & ~3;
04160 
04161         /* Determine the NIC variant */
04162         falcon_probe_nic_variant ( efab, pci );
04163 
04164         /* Read the SPI interface and determine the MAC address,
04165          * and the board and phy variant. Hook in the op tables */
04166         rc = falcon_probe_spi ( efab );
04167         if ( rc )
04168                 goto fail2;
04169         rc = falcon_probe_nvram ( efab );
04170         if ( rc )
04171                 goto fail3;
04172 
04173         memcpy ( netdev->hw_addr, efab->mac_addr, ETH_ALEN );
04174 
04175         rc = register_netdev ( netdev );
04176         if ( rc )
04177                 goto fail4;
04178         netdev_link_up ( netdev );
04179 
04180         /* Advertise non-volatile storage */
04181         if ( efab->nvo.nvs ) {
04182                 rc = register_nvo ( &efab->nvo, netdev_settings ( netdev ) );
04183                 if ( rc )
04184                         goto fail5;
04185         }
04186 
04187         EFAB_LOG ( "Found %s EtherFabric %s %s revision %d\n", pci->id->name,
04188                    efab->is_asic ? "ASIC" : "FPGA",
04189                    efab->phy_10g ? "10G" : "1G",
04190                    efab->pci_revision );
04191 
04192         return 0;
04193 
04194 fail5:
04195         unregister_netdev ( netdev );
04196 fail4:
04197 fail3:
04198 fail2:
04199         iounmap ( efab->membase );
04200         efab->membase = NULL;
04201         netdev_put ( netdev );
04202 fail1:
04203         return rc;
04204 }
04205 
04206 
04207 static struct pci_device_id efab_nics[] = {
04208         PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon", 0),
04209         PCI_ROM(0x1924, 0x0710, "falconb0", "EtherFabric FalconB0", 0),
04210 };
04211 
04212 struct pci_driver etherfabric_driver __pci_driver = {
04213         .ids = efab_nics,
04214         .id_count = sizeof ( efab_nics ) / sizeof ( efab_nics[0] ),
04215         .probe = efab_probe,
04216         .remove = efab_remove,
04217 };
04218 
04219 /*
04220  * Local variables:
04221  *  c-basic-offset: 8
04222  *  c-indent-level: 8
04223  *  tab-width: 8
04224  * End:
04225  */