iPXE
rhine.c
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00001 /*
00002  * Copyright (C) 2012 Adrian Jamroz <adrian.jamroz@gmail.com>
00003  *
00004  * This program is free software; you can redistribute it and/or
00005  * modify it under the terms of the GNU General Public License as
00006  * published by the Free Software Foundation; either version 2 of the
00007  * License, or (at your option) any later version.
00008  *
00009  * This program is distributed in the hope that it will be useful, but
00010  * WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012  * General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00017  * 02110-1301, USA.
00018  */
00019 
00020 FILE_LICENCE ( GPL2_OR_LATER );
00021 
00022 #include <stdint.h>
00023 #include <string.h>
00024 #include <unistd.h>
00025 #include <errno.h>
00026 #include <byteswap.h>
00027 #include <ipxe/netdevice.h>
00028 #include <ipxe/ethernet.h>
00029 #include <ipxe/if_ether.h>
00030 #include <ipxe/iobuf.h>
00031 #include <ipxe/malloc.h>
00032 #include <ipxe/pci.h>
00033 #include <ipxe/mii.h>
00034 #include "rhine.h"
00035 
00036 /** @file
00037  *
00038  * VIA Rhine network driver
00039  *
00040  */
00041 
00042 /******************************************************************************
00043  *
00044  * MII interface
00045  *
00046  ******************************************************************************
00047  */
00048 
00049 /**
00050  * Read from MII register
00051  *
00052  * @v mdio              MII interface
00053  * @v phy               PHY address
00054  * @v reg               Register address
00055  * @ret value           Data read, or negative error
00056  */
00057 static int rhine_mii_read ( struct mii_interface *mdio,
00058                             unsigned int phy __unused, unsigned int reg ) {
00059         struct rhine_nic *rhn = container_of ( mdio, struct rhine_nic, mdio );
00060         unsigned int timeout = RHINE_TIMEOUT_US;
00061         uint8_t cr;
00062 
00063         DBGC2 ( rhn, "RHINE %p MII read reg %d\n", rhn, reg );
00064 
00065         /* Initiate read */
00066         writeb ( reg, rhn->regs + RHINE_MII_ADDR );
00067         cr = readb ( rhn->regs + RHINE_MII_CR );
00068         writeb ( ( cr | RHINE_MII_CR_RDEN ), rhn->regs + RHINE_MII_CR );
00069 
00070         /* Wait for read to complete */
00071         while ( timeout-- ) {
00072                 udelay ( 1 );
00073                 cr = readb ( rhn->regs + RHINE_MII_CR );
00074                 if ( ! ( cr & RHINE_MII_CR_RDEN ) )
00075                         return readw ( rhn->regs + RHINE_MII_RDWR );
00076         }
00077 
00078         DBGC ( rhn, "RHINE %p MII read timeout\n", rhn );
00079         return -ETIMEDOUT;
00080 }
00081 
00082 /**
00083  * Write to MII register
00084  *
00085  * @v mdio              MII interface
00086  * @v phy               PHY address
00087  * @v reg               Register address
00088  * @v data              Data to write
00089  * @ret rc              Return status code
00090  */
00091 static int rhine_mii_write ( struct mii_interface *mdio,
00092                              unsigned int phy __unused, unsigned int reg,
00093                              unsigned int data ) {
00094         struct rhine_nic *rhn = container_of ( mdio, struct rhine_nic, mdio );
00095         unsigned int timeout = RHINE_TIMEOUT_US;
00096         uint8_t cr;
00097 
00098         DBGC2 ( rhn, "RHINE %p MII write reg %d data 0x%04x\n",
00099                 rhn, reg, data );
00100 
00101         /* Initiate write */
00102         writeb ( reg, rhn->regs + RHINE_MII_ADDR );
00103         writew ( data, rhn->regs + RHINE_MII_RDWR );
00104         cr = readb ( rhn->regs + RHINE_MII_CR );
00105         writeb ( ( cr | RHINE_MII_CR_WREN ), rhn->regs + RHINE_MII_CR );
00106 
00107         /* Wait for write to complete */
00108         while ( timeout-- ) {
00109                 udelay ( 1 );
00110                 cr = readb ( rhn->regs + RHINE_MII_CR );
00111                 if ( ! ( cr & RHINE_MII_CR_WREN ) )
00112                         return 0;
00113         }
00114 
00115         DBGC ( rhn, "RHINE %p MII write timeout\n", rhn );
00116         return -ETIMEDOUT;
00117 }
00118 
00119 /** Rhine MII operations */
00120 static struct mii_operations rhine_mii_operations = {
00121         .read = rhine_mii_read,
00122         .write = rhine_mii_write,
00123 };
00124 
00125 /**
00126  * Enable auto-polling
00127  *
00128  * @v rhn               Rhine device
00129  * @ret rc              Return status code
00130  *
00131  * This is voodoo.  There seems to be no documentation on exactly what
00132  * we are waiting for, or why we have to do anything other than simply
00133  * turn the feature on.
00134  */
00135 static int rhine_mii_autopoll ( struct rhine_nic *rhn ) {
00136         unsigned int timeout = RHINE_TIMEOUT_US;
00137         uint8_t addr;
00138 
00139         /* Initiate auto-polling */
00140         writeb ( MII_BMSR, rhn->regs + RHINE_MII_ADDR );
00141         writeb ( RHINE_MII_CR_AUTOPOLL, rhn->regs + RHINE_MII_CR );
00142 
00143         /* Wait for auto-polling to complete */
00144         while ( timeout-- ) {
00145                 udelay ( 1 );
00146                 addr = readb ( rhn->regs + RHINE_MII_ADDR );
00147                 if ( ! ( addr & RHINE_MII_ADDR_MDONE ) ) {
00148                         writeb ( ( MII_BMSR | RHINE_MII_ADDR_MSRCEN ),
00149                                  rhn->regs + RHINE_MII_ADDR );
00150                         return 0;
00151                 }
00152         }
00153 
00154         DBGC ( rhn, "RHINE %p MII auto-poll timeout\n", rhn );
00155         return -ETIMEDOUT;
00156 }
00157 
00158 /******************************************************************************
00159  *
00160  * Device reset
00161  *
00162  ******************************************************************************
00163  */
00164 
00165 /**
00166  * Reset hardware
00167  *
00168  * @v rhn               Rhine device
00169  * @ret rc              Return status code
00170  *
00171  * We're using PIO because this might reset the MMIO enable bit.
00172  */
00173 static int rhine_reset ( struct rhine_nic *rhn ) {
00174         unsigned int timeout = RHINE_TIMEOUT_US;
00175         uint8_t cr1;
00176 
00177         DBGC ( rhn, "RHINE %p reset\n", rhn );
00178 
00179         /* Initiate reset */
00180         outb ( RHINE_CR1_RESET, rhn->ioaddr + RHINE_CR1 );
00181 
00182         /* Wait for reset to complete */
00183         while ( timeout-- ) {
00184                 udelay ( 1 );
00185                 cr1 = inb ( rhn->ioaddr + RHINE_CR1 );
00186                 if ( ! ( cr1 & RHINE_CR1_RESET ) )
00187                         return 0;
00188         }
00189 
00190         DBGC ( rhn, "RHINE %p reset timeout\n", rhn );
00191         return -ETIMEDOUT;
00192 }
00193 
00194 /**
00195  * Enable MMIO register access
00196  *
00197  * @v rhn               Rhine device
00198  * @v revision          Card revision
00199  */
00200 static void rhine_enable_mmio ( struct rhine_nic *rhn, int revision ) {
00201         uint8_t conf;
00202 
00203         if ( revision < RHINE_REVISION_OLD ) {
00204                 conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_A );
00205                 outb ( ( conf | RHINE_CHIPCFG_A_MMIO ),
00206                        rhn->ioaddr + RHINE_CHIPCFG_A );
00207         } else {
00208                 conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_D );
00209                 outb ( ( conf | RHINE_CHIPCFG_D_MMIO ),
00210                        rhn->ioaddr + RHINE_CHIPCFG_D );
00211         }
00212 }
00213 
00214 /**
00215  * Reload EEPROM contents
00216  *
00217  * @v rhn               Rhine device
00218  * @ret rc              Return status code
00219  *
00220  * We're using PIO because this might reset the MMIO enable bit.
00221  */
00222 static int rhine_reload_eeprom ( struct rhine_nic *rhn ) {
00223         unsigned int timeout = RHINE_TIMEOUT_US;
00224         uint8_t eeprom;
00225 
00226         /* Initiate reload */
00227         eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
00228         outb ( ( eeprom | RHINE_EEPROM_CTRL_RELOAD ),
00229                rhn->ioaddr + RHINE_EEPROM_CTRL );
00230 
00231         /* Wait for reload to complete */
00232         while ( timeout-- ) {
00233                 udelay ( 1 );
00234                 eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
00235                 if ( ! ( eeprom & RHINE_EEPROM_CTRL_RELOAD ) )
00236                         return 0;
00237         }
00238 
00239         DBGC ( rhn, "RHINE %p EEPROM reload timeout\n", rhn );
00240         return -ETIMEDOUT;
00241 }
00242 
00243 /******************************************************************************
00244  *
00245  * Link state
00246  *
00247  ******************************************************************************
00248  */
00249 
00250 /**
00251  * Check link state
00252  *
00253  * @v netdev            Network device
00254  */
00255 static void rhine_check_link ( struct net_device *netdev ) {
00256         struct rhine_nic *rhn = netdev->priv;
00257         uint8_t mii_sr;
00258 
00259         /* Read MII status register */
00260         mii_sr = readb ( rhn->regs + RHINE_MII_SR );
00261         DBGC ( rhn, "RHINE %p link status %02x\n", rhn, mii_sr );
00262 
00263         /* Report link state */
00264         if ( ! ( mii_sr & RHINE_MII_SR_LINKPOLL ) ) {
00265                 netdev_link_up ( netdev );
00266         } else if ( mii_sr & RHINE_MII_SR_PHYERR ) {
00267                 netdev_link_err ( netdev, -EIO );
00268         } else {
00269                 netdev_link_down ( netdev );
00270         }
00271 }
00272 
00273 /******************************************************************************
00274  *
00275  * Network device interface
00276  *
00277  ******************************************************************************
00278  */
00279 
00280 /**
00281  * Create descriptor ring
00282  *
00283  * @v rhn               Rhine device
00284  * @v ring              Descriptor ring
00285  * @ret rc              Return status code
00286  */
00287 static int rhine_create_ring ( struct rhine_nic *rhn,
00288                                struct rhine_ring *ring ) {
00289         size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
00290         struct rhine_descriptor *next;
00291         physaddr_t address;
00292         unsigned int i;
00293 
00294         /* Allocate descriptors */
00295         ring->desc = malloc_dma ( len, RHINE_RING_ALIGN );
00296         if ( ! ring->desc )
00297                 return -ENOMEM;
00298 
00299         /* Initialise descriptor ring */
00300         memset ( ring->desc, 0, len );
00301         for ( i = 0 ; i < ring->count ; i++ ) {
00302                 next = &ring->desc[ ( i + 1 ) % ring->count ];
00303                 ring->desc[i].next = cpu_to_le32 ( virt_to_bus ( next ) );
00304         }
00305 
00306         /* Program ring address */
00307         address = virt_to_bus ( ring->desc );
00308         writel ( address, rhn->regs + ring->reg );
00309 
00310         DBGC ( rhn, "RHINE %p ring %02x is at [%08llx,%08llx)\n",
00311                rhn, ring->reg, ( ( unsigned long long ) address ),
00312                ( ( unsigned long long ) address + len ) );
00313 
00314         return 0;
00315 }
00316 
00317 /**
00318  * Destroy descriptor ring
00319  *
00320  * @v rhn               Rhine device
00321  * @v ring              Descriptor ring
00322  */
00323 static void rhine_destroy_ring ( struct rhine_nic *rhn,
00324                                  struct rhine_ring *ring ) {
00325         size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
00326 
00327         /* Clear ring address */
00328         writel ( 0, rhn->regs + ring->reg );
00329 
00330         /* Free descriptor ring */
00331         free_dma ( ring->desc, len );
00332         ring->desc = NULL;
00333         ring->prod = 0;
00334         ring->cons = 0;
00335 }
00336 
00337 /**
00338  * Refill RX descriptor ring
00339  *
00340  * @v rhn               Rhine device
00341  */
00342 static void rhine_refill_rx ( struct rhine_nic *rhn ) {
00343         struct rhine_descriptor *desc;
00344         struct io_buffer *iobuf;
00345         unsigned int rx_idx;
00346         physaddr_t address;
00347 
00348         while ( ( rhn->rx.prod - rhn->rx.cons ) < RHINE_RXDESC_NUM ) {
00349 
00350                 /* Allocate I/O buffer */
00351                 iobuf = alloc_iob ( RHINE_RX_MAX_LEN );
00352                 if ( ! iobuf ) {
00353                         /* Wait for next refill */
00354                         return;
00355                 }
00356 
00357                 /* Populate next receive descriptor */
00358                 rx_idx = ( rhn->rx.prod++ % RHINE_RXDESC_NUM );
00359                 desc = &rhn->rx.desc[rx_idx];
00360                 address = virt_to_bus ( iobuf->data );
00361                 desc->buffer = cpu_to_le32 ( address );
00362                 desc->des1 =
00363                         cpu_to_le32 ( RHINE_DES1_SIZE ( RHINE_RX_MAX_LEN - 1) |
00364                                       RHINE_DES1_CHAIN | RHINE_DES1_IC );
00365                 wmb();
00366                 desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
00367 
00368                 /* Record I/O buffer */
00369                 rhn->rx_iobuf[rx_idx] = iobuf;
00370 
00371                 DBGC2 ( rhn, "RHINE %p RX %d is [%llx,%llx)\n", rhn, rx_idx,
00372                         ( ( unsigned long long ) address ),
00373                         ( ( unsigned long long ) address + RHINE_RX_MAX_LEN ) );
00374         }
00375 }
00376 
00377 /**
00378  * Open network device
00379  *
00380  * @v netdev            Network device
00381  * @ret rc              Return status code
00382  */
00383 static int rhine_open ( struct net_device *netdev ) {
00384         struct rhine_nic *rhn = netdev->priv;
00385         int rc;
00386 
00387         /* Create transmit ring */
00388         if ( ( rc = rhine_create_ring ( rhn, &rhn->tx ) ) != 0 )
00389                 goto err_create_tx;
00390 
00391         /* Create receive ring */
00392         if ( ( rc = rhine_create_ring ( rhn, &rhn->rx ) ) != 0 )
00393                 goto err_create_rx;
00394 
00395         /* Set receive configuration */
00396         writeb ( ( RHINE_RCR_PHYS_ACCEPT | RHINE_RCR_BCAST_ACCEPT |
00397                    RHINE_RCR_RUNT_ACCEPT ), rhn->regs + RHINE_RCR );
00398 
00399         /* Enable link status monitoring */
00400         if ( ( rc = rhine_mii_autopoll ( rhn ) ) != 0 )
00401                 goto err_mii_autopoll;
00402 
00403         /* Some cards need an extra delay(observed with VT6102) */
00404         mdelay ( 10 );
00405 
00406         /* Enable RX/TX of packets */
00407         writeb ( ( RHINE_CR0_STARTNIC | RHINE_CR0_RXEN | RHINE_CR0_TXEN ),
00408                  rhn->regs + RHINE_CR0 );
00409 
00410         /* Enable auto polling and full duplex operation */
00411         rhn->cr1 = RHINE_CR1_FDX;
00412         writeb ( rhn->cr1, rhn->regs + RHINE_CR1 );
00413 
00414         /* Refill RX ring */
00415         rhine_refill_rx ( rhn );
00416 
00417         /* Update link state */
00418         rhine_check_link ( netdev );
00419 
00420         return 0;
00421 
00422  err_mii_autopoll:
00423         rhine_destroy_ring ( rhn, &rhn->rx );
00424  err_create_rx:
00425         rhine_destroy_ring ( rhn, &rhn->tx );
00426  err_create_tx:
00427         return rc;
00428 }
00429 
00430 /**
00431  * Close network device
00432  *
00433  * @v netdev            Network device
00434  */
00435 static void rhine_close ( struct net_device *netdev ) {
00436         struct rhine_nic *rhn = netdev->priv;
00437         unsigned int i;
00438 
00439         /* Disable interrupts */
00440         writeb ( 0, RHINE_IMR0 );
00441         writeb ( 0, RHINE_IMR1 );
00442 
00443         /* Stop card, clear RXON and TXON bits */
00444         writeb ( RHINE_CR0_STOPNIC, rhn->regs + RHINE_CR0 );
00445 
00446         /* Destroy receive ring */
00447         rhine_destroy_ring ( rhn, &rhn->rx );
00448 
00449         /* Discard any unused receive buffers */
00450         for ( i = 0 ; i < RHINE_RXDESC_NUM ; i++ ) {
00451                 if ( rhn->rx_iobuf[i] )
00452                         free_iob ( rhn->rx_iobuf[i] );
00453                 rhn->rx_iobuf[i] = NULL;
00454         }
00455 
00456         /* Destroy transmit ring */
00457         rhine_destroy_ring ( rhn, &rhn->tx );
00458 }
00459 
00460 /**
00461  * Transmit packet
00462  *
00463  * @v netdev            Network device
00464  * @v iobuf             I/O buffer
00465  * @ret rc              Return status code
00466  */
00467 static int rhine_transmit ( struct net_device *netdev,
00468                             struct io_buffer *iobuf ) {
00469         struct rhine_nic *rhn = netdev->priv;
00470         struct rhine_descriptor *desc;
00471         physaddr_t address;
00472         unsigned int tx_idx;
00473 
00474         /* Get next transmit descriptor */
00475         if ( ( rhn->tx.prod - rhn->tx.cons ) >= RHINE_TXDESC_NUM )
00476                 return -ENOBUFS;
00477         tx_idx = ( rhn->tx.prod++ % RHINE_TXDESC_NUM );
00478         desc = &rhn->tx.desc[tx_idx];
00479 
00480         /* Pad and align packet */
00481         iob_pad ( iobuf, ETH_ZLEN );
00482         address = virt_to_bus ( iobuf->data );
00483 
00484         /* Populate transmit descriptor */
00485         desc->buffer = cpu_to_le32 ( address );
00486         desc->des1 = cpu_to_le32 ( RHINE_DES1_IC | RHINE_TDES1_STP |
00487                                    RHINE_TDES1_EDP | RHINE_DES1_CHAIN |
00488                                    RHINE_DES1_SIZE ( iob_len ( iobuf ) ) );
00489         wmb();
00490         desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
00491         wmb();
00492 
00493         /* Notify card that there are packets ready to transmit */
00494         writeb ( ( rhn->cr1 | RHINE_CR1_TXPOLL ), rhn->regs + RHINE_CR1 );
00495 
00496         DBGC2 ( rhn, "RHINE %p TX %d is [%llx,%llx)\n", rhn, tx_idx,
00497                 ( ( unsigned long long ) address ),
00498                 ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
00499 
00500         return 0;
00501 }
00502 
00503 /**
00504  * Poll for completed packets
00505  *
00506  * @v netdev            Network device
00507  */
00508 static void rhine_poll_tx ( struct net_device *netdev ) {
00509         struct rhine_nic *rhn = netdev->priv;
00510         struct rhine_descriptor *desc;
00511         unsigned int tx_idx;
00512         uint32_t des0;
00513 
00514         /* Check for completed packets */
00515         while ( rhn->tx.cons != rhn->tx.prod ) {
00516 
00517                 /* Get next transmit descriptor */
00518                 tx_idx = ( rhn->tx.cons % RHINE_TXDESC_NUM );
00519                 desc = &rhn->tx.desc[tx_idx];
00520 
00521                 /* Stop if descriptor is still in use */
00522                 if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
00523                         return;
00524 
00525                 /* Complete TX descriptor */
00526                 des0 = le32_to_cpu ( desc->des0 );
00527                 if ( des0 & RHINE_TDES0_TERR ) {
00528                         DBGC ( rhn, "RHINE %p TX %d error (DES0 %08x)\n",
00529                                rhn, tx_idx, des0 );
00530                         netdev_tx_complete_next_err ( netdev, -EIO );
00531                 } else {
00532                         DBGC2 ( rhn, "RHINE %p TX %d complete\n", rhn, tx_idx );
00533                         netdev_tx_complete_next ( netdev );
00534                 }
00535                 rhn->tx.cons++;
00536         }
00537 }
00538 
00539 /**
00540  * Poll for received packets
00541  *
00542  * @v netdev            Network device
00543  */
00544 static void rhine_poll_rx ( struct net_device *netdev ) {
00545         struct rhine_nic *rhn = netdev->priv;
00546         struct rhine_descriptor *desc;
00547         struct io_buffer *iobuf;
00548         unsigned int rx_idx;
00549         uint32_t des0;
00550         size_t len;
00551 
00552         /* Check for received packets */
00553         while ( rhn->rx.cons != rhn->rx.prod ) {
00554 
00555                 /* Get next receive descriptor */
00556                 rx_idx = ( rhn->rx.cons % RHINE_RXDESC_NUM );
00557                 desc = &rhn->rx.desc[rx_idx];
00558 
00559                 /* Stop if descriptor is still in use */
00560                 if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
00561                         return;
00562 
00563                 /* Populate I/O buffer */
00564                 iobuf = rhn->rx_iobuf[rx_idx];
00565                 rhn->rx_iobuf[rx_idx] = NULL;
00566                 des0 = le32_to_cpu ( desc->des0 );
00567                 len = ( RHINE_DES0_GETSIZE ( des0 ) - 4 /* strip CRC */ );
00568                 iob_put ( iobuf, len );
00569 
00570                 /* Hand off to network stack */
00571                 if ( des0 & RHINE_RDES0_RXOK ) {
00572                         DBGC2 ( rhn, "RHINE %p RX %d complete (length %zd)\n",
00573                                 rhn, rx_idx, len );
00574                         netdev_rx ( netdev, iobuf );
00575                 } else {
00576                         DBGC ( rhn, "RHINE %p RX %d error (length %zd, DES0 "
00577                                "%08x)\n", rhn, rx_idx, len, des0 );
00578                         netdev_rx_err ( netdev, iobuf, -EIO );
00579                 }
00580                 rhn->rx.cons++;
00581         }
00582 }
00583 
00584 /**
00585  * Poll for completed and received packets
00586  *
00587  * @v netdev            Network device
00588  */
00589 static void rhine_poll ( struct net_device *netdev ) {
00590         struct rhine_nic *rhn = netdev->priv;
00591         uint8_t isr0;
00592         uint8_t isr1;
00593 
00594         /* Read and acknowledge interrupts */
00595         isr0 = readb ( rhn->regs + RHINE_ISR0 );
00596         isr1 = readb ( rhn->regs + RHINE_ISR1 );
00597         if ( isr0 )
00598                 writeb ( isr0, rhn->regs + RHINE_ISR0 );
00599         if ( isr1 )
00600                 writeb ( isr1, rhn->regs + RHINE_ISR1 );
00601 
00602         /* Report unexpected errors */
00603         if ( ( isr0 & ( RHINE_ISR0_MIBOVFL | RHINE_ISR0_PCIERR |
00604                         RHINE_ISR0_RXRINGERR | RHINE_ISR0_TXRINGERR ) ) ||
00605              ( isr1 & ( RHINE_ISR1_GPI | RHINE_ISR1_TXABORT |
00606                         RHINE_ISR1_RXFIFOOVFL | RHINE_ISR1_RXFIFOUNFL |
00607                         RHINE_ISR1_TXFIFOUNFL ) ) ) {
00608                 DBGC ( rhn, "RHINE %p unexpected ISR0 %02x ISR1 %02x\n",
00609                        rhn, isr0, isr1 );
00610                 /* Report as a TX error */
00611                 netdev_tx_err ( netdev, NULL, -EIO );
00612         }
00613 
00614         /* Poll for TX completions, if applicable */
00615         if ( isr0 & ( RHINE_ISR0_TXDONE | RHINE_ISR0_TXERR ) )
00616                 rhine_poll_tx ( netdev );
00617 
00618         /* Poll for RX completions, if applicable */
00619         if ( isr0 & ( RHINE_ISR0_RXDONE | RHINE_ISR0_RXERR ) )
00620                 rhine_poll_rx ( netdev );
00621 
00622         /* Handle RX buffer exhaustion */
00623         if ( isr1 & RHINE_ISR1_RXNOBUF ) {
00624                 rhine_poll_rx ( netdev );
00625                 netdev_rx_err ( netdev, NULL, -ENOBUFS );
00626         }
00627 
00628         /* Check link state, if applicable */
00629         if ( isr1 & RHINE_ISR1_PORTSTATE )
00630                 rhine_check_link ( netdev );
00631 
00632         /* Refill RX ring */
00633         rhine_refill_rx ( rhn );
00634 }
00635 
00636 /**
00637  * Enable or disable interrupts
00638  *
00639  * @v netdev            Network device
00640  * @v enable            Interrupts should be enabled
00641  */
00642 static void rhine_irq ( struct net_device *netdev, int enable ) {
00643         struct rhine_nic *nic = netdev->priv;
00644 
00645         if ( enable ) {
00646                 /* Enable interrupts */
00647                 writeb ( 0xff, nic->regs + RHINE_IMR0 );
00648                 writeb ( 0xff, nic->regs + RHINE_IMR1 );
00649         } else {
00650                 /* Disable interrupts */
00651                 writeb ( 0, nic->regs + RHINE_IMR0 );
00652                 writeb ( 0, nic->regs + RHINE_IMR1 );
00653         }
00654 }
00655 
00656 /** Rhine network device operations */
00657 static struct net_device_operations rhine_operations = {
00658         .open           = rhine_open,
00659         .close          = rhine_close,
00660         .transmit       = rhine_transmit,
00661         .poll           = rhine_poll,
00662         .irq            = rhine_irq,
00663 };
00664 
00665 /******************************************************************************
00666  *
00667  * PCI interface
00668  *
00669  ******************************************************************************
00670  */
00671 
00672 /**
00673  * Probe PCI device
00674  *
00675  * @v pci               PCI device
00676  * @ret rc              Return status code
00677  */
00678 static int rhine_probe ( struct pci_device *pci ) {
00679         struct net_device *netdev;
00680         struct rhine_nic *rhn;
00681         uint8_t revision;
00682         unsigned int i;
00683         int rc;
00684 
00685         /* Allocate and initialise net device */
00686         netdev = alloc_etherdev ( sizeof ( *rhn ) );
00687         if ( ! netdev ) {
00688                 rc = -ENOMEM;
00689                 goto err_alloc;
00690         }
00691         netdev_init ( netdev, &rhine_operations );
00692         rhn = netdev->priv;
00693         pci_set_drvdata ( pci, netdev );
00694         netdev->dev = &pci->dev;
00695         memset ( rhn, 0, sizeof ( *rhn ) );
00696         rhine_init_ring ( &rhn->tx, RHINE_TXDESC_NUM, RHINE_TXQUEUE_BASE );
00697         rhine_init_ring ( &rhn->rx, RHINE_RXDESC_NUM, RHINE_RXQUEUE_BASE );
00698 
00699         /* Fix up PCI device */
00700         adjust_pci_device ( pci );
00701 
00702         /* Map registers */
00703         rhn->regs = ioremap ( pci->membase, RHINE_BAR_SIZE );
00704         rhn->ioaddr = pci->ioaddr;
00705         DBGC ( rhn, "RHINE %p regs at %08lx, I/O at %04lx\n", rhn,
00706                pci->membase, pci->ioaddr );
00707 
00708         /* Reset the NIC */
00709         if ( ( rc = rhine_reset ( rhn ) ) != 0 )
00710                 goto err_reset;
00711 
00712         /* Reload EEPROM */
00713         if ( ( rc = rhine_reload_eeprom ( rhn ) ) != 0 )
00714                 goto err_reload_eeprom;
00715 
00716         /* Read card revision and enable MMIO */
00717         pci_read_config_byte ( pci, PCI_REVISION, &revision );
00718         DBGC ( rhn, "RHINE %p revision %#02x detected\n", rhn, revision );
00719         rhine_enable_mmio ( rhn, revision );
00720 
00721         /* Read MAC address */
00722         for ( i = 0 ; i < ETH_ALEN ; i++ )
00723                 netdev->hw_addr[i] = readb ( rhn->regs + RHINE_MAC + i );
00724 
00725         /* Initialise and reset MII interface */
00726         mdio_init ( &rhn->mdio, &rhine_mii_operations );
00727         mii_init ( &rhn->mii, &rhn->mdio, 0 );
00728         if ( ( rc = mii_reset ( &rhn->mii ) ) != 0 ) {
00729                 DBGC ( rhn, "RHINE %p could not reset MII: %s\n",
00730                        rhn, strerror ( rc ) );
00731                 goto err_mii_reset;
00732         }
00733         DBGC ( rhn, "RHINE PHY vendor %04x device %04x\n",
00734                mii_read ( &rhn->mii, 0x02 ), mii_read ( &rhn->mii, 0x03 ) );
00735 
00736         /* Register network device */
00737         if ( ( rc = register_netdev ( netdev ) ) != 0 )
00738                 goto err_register_netdev;
00739 
00740         /* Set initial link state */
00741         rhine_check_link ( netdev );
00742 
00743         return 0;
00744 
00745  err_register_netdev:
00746  err_mii_reset:
00747  err_reload_eeprom:
00748         rhine_reset ( rhn );
00749  err_reset:
00750         netdev_nullify ( netdev );
00751         netdev_put ( netdev );
00752  err_alloc:
00753         return rc;
00754 }
00755 
00756 /**
00757  * Remove PCI device
00758  *
00759  * @v pci               PCI device
00760  */
00761 static void rhine_remove ( struct pci_device *pci ) {
00762         struct net_device *netdev = pci_get_drvdata ( pci );
00763         struct rhine_nic *nic = netdev->priv;
00764 
00765         /* Unregister network device */
00766         unregister_netdev ( netdev );
00767 
00768         /* Reset card */
00769         rhine_reset ( nic );
00770 
00771         /* Free network device */
00772         netdev_nullify ( netdev );
00773         netdev_put ( netdev );
00774 }
00775 
00776 /** Rhine PCI device IDs */
00777 static struct pci_device_id rhine_nics[] = {
00778         PCI_ROM ( 0x1106, 0x3065, "dlink-530tx", "VIA VT6102", 0 ),
00779         PCI_ROM ( 0x1106, 0x3106, "vt6105", "VIA VT6105", 0 ),
00780         PCI_ROM ( 0x1106, 0x3043, "dlink-530tx-old", "VIA VT3043", 0 ),
00781         PCI_ROM ( 0x1106, 0x3053, "vt6105m", "VIA VT6105M", 0 ),
00782         PCI_ROM ( 0x1106, 0x6100, "via-rhine-old", "VIA 86C100A", 0 )
00783 };
00784 
00785 /** Rhine PCI driver */
00786 struct pci_driver rhine_driver __pci_driver = {
00787         .ids = rhine_nics,
00788         .id_count = ( sizeof ( rhine_nics ) / sizeof ( rhine_nics[0] ) ),
00789         .probe = rhine_probe,
00790         .remove = rhine_remove,
00791 };