iPXE
skge.c
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00001 /*
00002  * iPXE driver for Marvell Yukon chipset and SysKonnect Gigabit
00003  * Ethernet adapters. Derived from Linux skge driver (v1.13), which was
00004  * based on earlier sk98lin, e100 and FreeBSD if_sk drivers.
00005  *
00006  * This driver intentionally does not support all the features of the
00007  * original driver such as link fail-over and link management because
00008  * those should be done at higher levels.
00009  *
00010  * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
00011  *
00012  * Modified for iPXE, July 2008 by Michael Decker <mrd999@gmail.com>
00013  * Tested and Modified in December 2009 by
00014  *    Thomas Miletich <thomas.miletich@gmail.com>
00015  *
00016  * This program is free software; you can redistribute it and/or modify
00017  * it under the terms of the GNU General Public License as published by
00018  * the Free Software Foundation; either version 2 of the License.
00019  *
00020  * This program is distributed in the hope that it will be useful,
00021  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00022  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00023  * GNU General Public License for more details.
00024  *
00025  * You should have received a copy of the GNU General Public License
00026  * along with this program; if not, write to the Free Software
00027  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00028  * 02110-1301, USA.
00029  */
00030 
00031 FILE_LICENCE ( GPL2_ONLY );
00032 
00033 #include <stdint.h>
00034 #include <errno.h>
00035 #include <stdio.h>
00036 #include <unistd.h>
00037 #include <ipxe/netdevice.h>
00038 #include <ipxe/ethernet.h>
00039 #include <ipxe/if_ether.h>
00040 #include <ipxe/iobuf.h>
00041 #include <ipxe/malloc.h>
00042 #include <ipxe/pci.h>
00043 
00044 #include "skge.h"
00045 
00046 static struct pci_device_id skge_id_table[] = {
00047         PCI_ROM(0x10b7, 0x1700,     "3C940",     "3COM 3C940", 0),
00048         PCI_ROM(0x10b7, 0x80eb,     "3C940B",    "3COM 3C940", 0),
00049         PCI_ROM(0x1148, 0x4300,     "GE",        "Syskonnect GE", 0),
00050         PCI_ROM(0x1148, 0x4320,     "YU",        "Syskonnect YU", 0),
00051         PCI_ROM(0x1186, 0x4C00,     "DGE510T",   "DLink DGE-510T", 0),
00052         PCI_ROM(0x1186, 0x4b01,     "DGE530T",   "DLink DGE-530T", 0),
00053         PCI_ROM(0x11ab, 0x4320,     "id4320",    "Marvell id4320", 0),
00054         PCI_ROM(0x11ab, 0x5005,     "id5005",    "Marvell id5005", 0), /* Belkin */
00055         PCI_ROM(0x1371, 0x434e,     "Gigacard",  "CNET Gigacard", 0),
00056         PCI_ROM(0x1737, 0x1064,     "EG1064",    "Linksys EG1064", 0),
00057         PCI_ROM(0x1737, 0xffff,     "id_any",    "Linksys [any]", 0)
00058 };
00059 
00060 static int skge_up(struct net_device *dev);
00061 static void skge_down(struct net_device *dev);
00062 static void skge_tx_clean(struct net_device *dev);
00063 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
00064 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
00065 static void yukon_init(struct skge_hw *hw, int port);
00066 static void genesis_mac_init(struct skge_hw *hw, int port);
00067 static void genesis_link_up(struct skge_port *skge);
00068 
00069 static void skge_phyirq(struct skge_hw *hw);
00070 static void skge_poll(struct net_device *dev);
00071 static int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob);
00072 static void skge_net_irq ( struct net_device *dev, int enable );
00073 
00074 static void skge_rx_refill(struct net_device *dev);
00075 
00076 static struct net_device_operations skge_operations = {
00077         .open     = skge_up,
00078         .close    = skge_down,
00079         .transmit = skge_xmit_frame,
00080         .poll     = skge_poll,
00081         .irq      = skge_net_irq
00082 };
00083 
00084 /* Avoid conditionals by using array */
00085 static const int txqaddr[] = { Q_XA1, Q_XA2 };
00086 static const int rxqaddr[] = { Q_R1, Q_R2 };
00087 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
00088 
00089 /* Determine supported/advertised modes based on hardware.
00090  * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
00091  */
00092 static u32 skge_supported_modes(const struct skge_hw *hw)
00093 {
00094         u32 supported;
00095 
00096         if (hw->copper) {
00097                 supported = SUPPORTED_10baseT_Half
00098                         | SUPPORTED_10baseT_Full
00099                         | SUPPORTED_100baseT_Half
00100                         | SUPPORTED_100baseT_Full
00101                         | SUPPORTED_1000baseT_Half
00102                         | SUPPORTED_1000baseT_Full
00103                         | SUPPORTED_Autoneg| SUPPORTED_TP;
00104 
00105                 if (hw->chip_id == CHIP_ID_GENESIS)
00106                         supported &= ~(SUPPORTED_10baseT_Half
00107                                              | SUPPORTED_10baseT_Full
00108                                              | SUPPORTED_100baseT_Half
00109                                              | SUPPORTED_100baseT_Full);
00110 
00111                 else if (hw->chip_id == CHIP_ID_YUKON)
00112                         supported &= ~SUPPORTED_1000baseT_Half;
00113         } else
00114                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
00115                         | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
00116 
00117         return supported;
00118 }
00119 
00120 /* Chip internal frequency for clock calculations */
00121 static inline u32 hwkhz(const struct skge_hw *hw)
00122 {
00123         return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
00124 }
00125 
00126 /* Microseconds to chip HZ */
00127 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
00128 {
00129         return hwkhz(hw) * usec / 1000;
00130 }
00131 
00132 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
00133 static void skge_led(struct skge_port *skge, enum led_mode mode)
00134 {
00135         struct skge_hw *hw = skge->hw;
00136         int port = skge->port;
00137 
00138         if (hw->chip_id == CHIP_ID_GENESIS) {
00139                 switch (mode) {
00140                 case LED_MODE_OFF:
00141                         if (hw->phy_type == SK_PHY_BCOM)
00142                                 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
00143                         else {
00144                                 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
00145                                 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
00146                         }
00147                         skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
00148                         skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
00149                         skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
00150                         break;
00151 
00152                 case LED_MODE_ON:
00153                         skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
00154                         skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
00155 
00156                         skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
00157                         skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
00158 
00159                         break;
00160 
00161                 case LED_MODE_TST:
00162                         skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
00163                         skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
00164                         skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
00165 
00166                         if (hw->phy_type == SK_PHY_BCOM)
00167                                 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
00168                         else {
00169                                 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
00170                                 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
00171                                 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
00172                         }
00173 
00174                 }
00175         } else {
00176                 switch (mode) {
00177                 case LED_MODE_OFF:
00178                         gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
00179                         gm_phy_write(hw, port, PHY_MARV_LED_OVER,
00180                                      PHY_M_LED_MO_DUP(MO_LED_OFF)  |
00181                                      PHY_M_LED_MO_10(MO_LED_OFF)   |
00182                                      PHY_M_LED_MO_100(MO_LED_OFF)  |
00183                                      PHY_M_LED_MO_1000(MO_LED_OFF) |
00184                                      PHY_M_LED_MO_RX(MO_LED_OFF));
00185                         break;
00186                 case LED_MODE_ON:
00187                         gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
00188                                      PHY_M_LED_PULS_DUR(PULS_170MS) |
00189                                      PHY_M_LED_BLINK_RT(BLINK_84MS) |
00190                                      PHY_M_LEDC_TX_CTRL |
00191                                      PHY_M_LEDC_DP_CTRL);
00192 
00193                         gm_phy_write(hw, port, PHY_MARV_LED_OVER,
00194                                      PHY_M_LED_MO_RX(MO_LED_OFF) |
00195                                      (skge->speed == SPEED_100 ?
00196                                       PHY_M_LED_MO_100(MO_LED_ON) : 0));
00197                         break;
00198                 case LED_MODE_TST:
00199                         gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
00200                         gm_phy_write(hw, port, PHY_MARV_LED_OVER,
00201                                      PHY_M_LED_MO_DUP(MO_LED_ON)  |
00202                                      PHY_M_LED_MO_10(MO_LED_ON)   |
00203                                      PHY_M_LED_MO_100(MO_LED_ON)  |
00204                                      PHY_M_LED_MO_1000(MO_LED_ON) |
00205                                      PHY_M_LED_MO_RX(MO_LED_ON));
00206                 }
00207         }
00208 }
00209 
00210 /*
00211  * I've left in these EEPROM and VPD functions, as someone may desire to
00212  * integrate them in the future. -mdeck
00213  *
00214  * static int skge_get_eeprom_len(struct net_device *dev)
00215  * {
00216  *      struct skge_port *skge = netdev_priv(dev);
00217  *      u32 reg2;
00218  *
00219  *      pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
00220  *      return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
00221  * }
00222  *
00223  * static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
00224  * {
00225  *      u32 val;
00226  *
00227  *      pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
00228  *
00229  *      do {
00230  *              pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
00231  *      } while (!(offset & PCI_VPD_ADDR_F));
00232  *
00233  *      pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
00234  *      return val;
00235  * }
00236  *
00237  * static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
00238  * {
00239  *      pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
00240  *      pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
00241  *                            offset | PCI_VPD_ADDR_F);
00242  *
00243  *      do {
00244  *              pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
00245  *      } while (offset & PCI_VPD_ADDR_F);
00246  * }
00247  *
00248  * static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
00249  *                         u8 *data)
00250  * {
00251  *      struct skge_port *skge = netdev_priv(dev);
00252  *      struct pci_dev *pdev = skge->hw->pdev;
00253  *      int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
00254  *      int length = eeprom->len;
00255  *      u16 offset = eeprom->offset;
00256  *
00257  *      if (!cap)
00258  *              return -EINVAL;
00259  *
00260  *      eeprom->magic = SKGE_EEPROM_MAGIC;
00261  *
00262  *      while (length > 0) {
00263  *              u32 val = skge_vpd_read(pdev, cap, offset);
00264  *              int n = min_t(int, length, sizeof(val));
00265  *
00266  *              memcpy(data, &val, n);
00267  *              length -= n;
00268  *              data += n;
00269  *              offset += n;
00270  *      }
00271  *      return 0;
00272  * }
00273  *
00274  * static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
00275  *                         u8 *data)
00276  * {
00277  *      struct skge_port *skge = netdev_priv(dev);
00278  *      struct pci_dev *pdev = skge->hw->pdev;
00279  *      int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
00280  *      int length = eeprom->len;
00281  *      u16 offset = eeprom->offset;
00282  *
00283  *      if (!cap)
00284  *              return -EINVAL;
00285  *
00286  *      if (eeprom->magic != SKGE_EEPROM_MAGIC)
00287  *              return -EINVAL;
00288  *
00289  *      while (length > 0) {
00290  *              u32 val;
00291  *              int n = min_t(int, length, sizeof(val));
00292  *
00293  *              if (n < sizeof(val))
00294  *                      val = skge_vpd_read(pdev, cap, offset);
00295  *              memcpy(&val, data, n);
00296  *
00297  *              skge_vpd_write(pdev, cap, offset, val);
00298  *
00299  *              length -= n;
00300  *              data += n;
00301  *              offset += n;
00302  *      }
00303  *      return 0;
00304  * }
00305  */
00306 
00307 /*
00308  * Allocate ring elements and chain them together
00309  * One-to-one association of board descriptors with ring elements
00310  */
00311 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base,
00312                            size_t num)
00313 {
00314         struct skge_tx_desc *d;
00315         struct skge_element *e;
00316         unsigned int i;
00317 
00318         ring->start = zalloc(num*sizeof(*e));
00319         if (!ring->start)
00320                 return -ENOMEM;
00321 
00322         for (i = 0, e = ring->start, d = vaddr; i < num; i++, e++, d++) {
00323                 e->desc = d;
00324                 if (i == num - 1) {
00325                         e->next = ring->start;
00326                         d->next_offset = base;
00327                 } else {
00328                         e->next = e + 1;
00329                         d->next_offset = base + (i+1) * sizeof(*d);
00330                 }
00331         }
00332         ring->to_use = ring->to_clean = ring->start;
00333 
00334         return 0;
00335 }
00336 
00337 /* Allocate and setup a new buffer for receiving */
00338 static void skge_rx_setup(struct skge_port *skge __unused,
00339                           struct skge_element *e,
00340                           struct io_buffer *iob, unsigned int bufsize)
00341 {
00342         struct skge_rx_desc *rd = e->desc;
00343         u64 map;
00344 
00345         map = ( iob != NULL ) ? virt_to_bus(iob->data) : 0;
00346 
00347         rd->dma_lo = map;
00348         rd->dma_hi = map >> 32;
00349         e->iob = iob;
00350         rd->csum1_start = ETH_HLEN;
00351         rd->csum2_start = ETH_HLEN;
00352         rd->csum1 = 0;
00353         rd->csum2 = 0;
00354 
00355         wmb();
00356 
00357         rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
00358 }
00359 
00360 /* Resume receiving using existing skb,
00361  * Note: DMA address is not changed by chip.
00362  *       MTU not changed while receiver active.
00363  */
00364 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
00365 {
00366         struct skge_rx_desc *rd = e->desc;
00367 
00368         rd->csum2 = 0;
00369         rd->csum2_start = ETH_HLEN;
00370 
00371         wmb();
00372 
00373         rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
00374 }
00375 
00376 
00377 /* Free all  buffers in receive ring, assumes receiver stopped */
00378 static void skge_rx_clean(struct skge_port *skge)
00379 {
00380         struct skge_ring *ring = &skge->rx_ring;
00381         struct skge_element *e;
00382 
00383         e = ring->start;
00384         do {
00385                 struct skge_rx_desc *rd = e->desc;
00386                 rd->control = 0;
00387                 if (e->iob) {
00388                         free_iob(e->iob);
00389                         e->iob = NULL;
00390                 }
00391         } while ((e = e->next) != ring->start);
00392 }
00393 
00394 static void skge_link_up(struct skge_port *skge)
00395 {
00396         skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
00397                     LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
00398 
00399         netdev_link_up(skge->netdev);
00400 
00401         DBG2(PFX "%s: Link is up at %d Mbps, %s duplex\n",
00402              skge->netdev->name, skge->speed,
00403              skge->duplex == DUPLEX_FULL ? "full" : "half");
00404 }
00405 
00406 static void skge_link_down(struct skge_port *skge)
00407 {
00408         skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
00409         netdev_link_down(skge->netdev);
00410 
00411         DBG2(PFX "%s: Link is down.\n", skge->netdev->name);
00412 }
00413 
00414 
00415 static void xm_link_down(struct skge_hw *hw, int port)
00416 {
00417         struct net_device *dev = hw->dev[port];
00418         struct skge_port *skge = netdev_priv(dev);
00419 
00420         xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
00421 
00422         if (netdev_link_ok(dev))
00423                 skge_link_down(skge);
00424 }
00425 
00426 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
00427 {
00428         int i;
00429 
00430         xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
00431         *val = xm_read16(hw, port, XM_PHY_DATA);
00432 
00433         if (hw->phy_type == SK_PHY_XMAC)
00434                 goto ready;
00435 
00436         for (i = 0; i < PHY_RETRIES; i++) {
00437                 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
00438                         goto ready;
00439                 udelay(1);
00440         }
00441 
00442         return -ETIMEDOUT;
00443  ready:
00444         *val = xm_read16(hw, port, XM_PHY_DATA);
00445 
00446         return 0;
00447 }
00448 
00449 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
00450 {
00451         u16 v = 0;
00452         if (__xm_phy_read(hw, port, reg, &v))
00453                 DBG(PFX "%s: phy read timed out\n",
00454                        hw->dev[port]->name);
00455         return v;
00456 }
00457 
00458 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
00459 {
00460         int i;
00461 
00462         xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
00463         for (i = 0; i < PHY_RETRIES; i++) {
00464                 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
00465                         goto ready;
00466                 udelay(1);
00467         }
00468         return -EIO;
00469 
00470  ready:
00471         xm_write16(hw, port, XM_PHY_DATA, val);
00472         for (i = 0; i < PHY_RETRIES; i++) {
00473                 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
00474                         return 0;
00475                 udelay(1);
00476         }
00477         return -ETIMEDOUT;
00478 }
00479 
00480 static void genesis_init(struct skge_hw *hw)
00481 {
00482         /* set blink source counter */
00483         skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
00484         skge_write8(hw, B2_BSC_CTRL, BSC_START);
00485 
00486         /* configure mac arbiter */
00487         skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
00488 
00489         /* configure mac arbiter timeout values */
00490         skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
00491         skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
00492         skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
00493         skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
00494 
00495         skge_write8(hw, B3_MA_RCINI_RX1, 0);
00496         skge_write8(hw, B3_MA_RCINI_RX2, 0);
00497         skge_write8(hw, B3_MA_RCINI_TX1, 0);
00498         skge_write8(hw, B3_MA_RCINI_TX2, 0);
00499 
00500         /* configure packet arbiter timeout */
00501         skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
00502         skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
00503         skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
00504         skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
00505         skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
00506 }
00507 
00508 static void genesis_reset(struct skge_hw *hw, int port)
00509 {
00510         const u8 zero[8]  = { 0 };
00511         u32 reg;
00512 
00513         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
00514 
00515         /* reset the statistics module */
00516         xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
00517         xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
00518         xm_write32(hw, port, XM_MODE, 0);               /* clear Mode Reg */
00519         xm_write16(hw, port, XM_TX_CMD, 0);     /* reset TX CMD Reg */
00520         xm_write16(hw, port, XM_RX_CMD, 0);     /* reset RX CMD Reg */
00521 
00522         /* disable Broadcom PHY IRQ */
00523         if (hw->phy_type == SK_PHY_BCOM)
00524                 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
00525 
00526         xm_outhash(hw, port, XM_HSM, zero);
00527 
00528         /* Flush TX and RX fifo */
00529         reg = xm_read32(hw, port, XM_MODE);
00530         xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
00531         xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
00532 }
00533 
00534 
00535 /* Convert mode to MII values  */
00536 static const u16 phy_pause_map[] = {
00537         [FLOW_MODE_NONE] =      0,
00538         [FLOW_MODE_LOC_SEND] =  PHY_AN_PAUSE_ASYM,
00539         [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
00540         [FLOW_MODE_SYM_OR_REM]  = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
00541 };
00542 
00543 /* special defines for FIBER (88E1011S only) */
00544 static const u16 fiber_pause_map[] = {
00545         [FLOW_MODE_NONE]        = PHY_X_P_NO_PAUSE,
00546         [FLOW_MODE_LOC_SEND]    = PHY_X_P_ASYM_MD,
00547         [FLOW_MODE_SYMMETRIC]   = PHY_X_P_SYM_MD,
00548         [FLOW_MODE_SYM_OR_REM]  = PHY_X_P_BOTH_MD,
00549 };
00550 
00551 
00552 /* Check status of Broadcom phy link */
00553 static void bcom_check_link(struct skge_hw *hw, int port)
00554 {
00555         struct net_device *dev = hw->dev[port];
00556         struct skge_port *skge = netdev_priv(dev);
00557         u16 status;
00558 
00559         /* read twice because of latch */
00560         xm_phy_read(hw, port, PHY_BCOM_STAT);
00561         status = xm_phy_read(hw, port, PHY_BCOM_STAT);
00562 
00563         if ((status & PHY_ST_LSYNC) == 0) {
00564                 xm_link_down(hw, port);
00565                 return;
00566         }
00567 
00568         if (skge->autoneg == AUTONEG_ENABLE) {
00569                 u16 lpa, aux;
00570 
00571                 if (!(status & PHY_ST_AN_OVER))
00572                         return;
00573 
00574                 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
00575                 if (lpa & PHY_B_AN_RF) {
00576                         DBG(PFX "%s: remote fault\n",
00577                                dev->name);
00578                         return;
00579                 }
00580 
00581                 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
00582 
00583                 /* Check Duplex mismatch */
00584                 switch (aux & PHY_B_AS_AN_RES_MSK) {
00585                 case PHY_B_RES_1000FD:
00586                         skge->duplex = DUPLEX_FULL;
00587                         break;
00588                 case PHY_B_RES_1000HD:
00589                         skge->duplex = DUPLEX_HALF;
00590                         break;
00591                 default:
00592                         DBG(PFX "%s: duplex mismatch\n",
00593                                dev->name);
00594                         return;
00595                 }
00596 
00597                 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
00598                 switch (aux & PHY_B_AS_PAUSE_MSK) {
00599                 case PHY_B_AS_PAUSE_MSK:
00600                         skge->flow_status = FLOW_STAT_SYMMETRIC;
00601                         break;
00602                 case PHY_B_AS_PRR:
00603                         skge->flow_status = FLOW_STAT_REM_SEND;
00604                         break;
00605                 case PHY_B_AS_PRT:
00606                         skge->flow_status = FLOW_STAT_LOC_SEND;
00607                         break;
00608                 default:
00609                         skge->flow_status = FLOW_STAT_NONE;
00610                 }
00611                 skge->speed = SPEED_1000;
00612         }
00613 
00614         if (!netdev_link_ok(dev))
00615                 genesis_link_up(skge);
00616 }
00617 
00618 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
00619  * Phy on for 100 or 10Mbit operation
00620  */
00621 static void bcom_phy_init(struct skge_port *skge)
00622 {
00623         struct skge_hw *hw = skge->hw;
00624         int port = skge->port;
00625         unsigned int i;
00626         u16 id1, r, ext, ctl;
00627 
00628         /* magic workaround patterns for Broadcom */
00629         static const struct {
00630                 u16 reg;
00631                 u16 val;
00632         } A1hack[] = {
00633                 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
00634                 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
00635                 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
00636                 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
00637         }, C0hack[] = {
00638                 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
00639                 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
00640         };
00641 
00642         /* read Id from external PHY (all have the same address) */
00643         id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
00644 
00645         /* Optimize MDIO transfer by suppressing preamble. */
00646         r = xm_read16(hw, port, XM_MMU_CMD);
00647         r |=  XM_MMU_NO_PRE;
00648         xm_write16(hw, port, XM_MMU_CMD,r);
00649 
00650         switch (id1) {
00651         case PHY_BCOM_ID1_C0:
00652                 /*
00653                  * Workaround BCOM Errata for the C0 type.
00654                  * Write magic patterns to reserved registers.
00655                  */
00656                 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
00657                         xm_phy_write(hw, port,
00658                                      C0hack[i].reg, C0hack[i].val);
00659 
00660                 break;
00661         case PHY_BCOM_ID1_A1:
00662                 /*
00663                  * Workaround BCOM Errata for the A1 type.
00664                  * Write magic patterns to reserved registers.
00665                  */
00666                 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
00667                         xm_phy_write(hw, port,
00668                                      A1hack[i].reg, A1hack[i].val);
00669                 break;
00670         }
00671 
00672         /*
00673          * Workaround BCOM Errata (#10523) for all BCom PHYs.
00674          * Disable Power Management after reset.
00675          */
00676         r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
00677         r |= PHY_B_AC_DIS_PM;
00678         xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
00679 
00680         /* Dummy read */
00681         xm_read16(hw, port, XM_ISRC);
00682 
00683         ext = PHY_B_PEC_EN_LTR; /* enable tx led */
00684         ctl = PHY_CT_SP1000;    /* always 1000mbit */
00685 
00686         if (skge->autoneg == AUTONEG_ENABLE) {
00687                 /*
00688                  * Workaround BCOM Errata #1 for the C5 type.
00689                  * 1000Base-T Link Acquisition Failure in Slave Mode
00690                  * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
00691                  */
00692                 u16 adv = PHY_B_1000C_RD;
00693                 if (skge->advertising & ADVERTISED_1000baseT_Half)
00694                         adv |= PHY_B_1000C_AHD;
00695                 if (skge->advertising & ADVERTISED_1000baseT_Full)
00696                         adv |= PHY_B_1000C_AFD;
00697                 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
00698 
00699                 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
00700         } else {
00701                 if (skge->duplex == DUPLEX_FULL)
00702                         ctl |= PHY_CT_DUP_MD;
00703                 /* Force to slave */
00704                 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
00705         }
00706 
00707         /* Set autonegotiation pause parameters */
00708         xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
00709                      phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
00710 
00711         xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
00712         xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
00713 
00714         /* Use link status change interrupt */
00715         xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
00716 }
00717 
00718 static void xm_phy_init(struct skge_port *skge)
00719 {
00720         struct skge_hw *hw = skge->hw;
00721         int port = skge->port;
00722         u16 ctrl = 0;
00723 
00724         if (skge->autoneg == AUTONEG_ENABLE) {
00725                 if (skge->advertising & ADVERTISED_1000baseT_Half)
00726                         ctrl |= PHY_X_AN_HD;
00727                 if (skge->advertising & ADVERTISED_1000baseT_Full)
00728                         ctrl |= PHY_X_AN_FD;
00729 
00730                 ctrl |= fiber_pause_map[skge->flow_control];
00731 
00732                 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
00733 
00734                 /* Restart Auto-negotiation */
00735                 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
00736         } else {
00737                 /* Set DuplexMode in Config register */
00738                 if (skge->duplex == DUPLEX_FULL)
00739                         ctrl |= PHY_CT_DUP_MD;
00740                 /*
00741                  * Do NOT enable Auto-negotiation here. This would hold
00742                  * the link down because no IDLEs are transmitted
00743                  */
00744         }
00745 
00746         xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
00747 
00748         /* Poll PHY for status changes */
00749         skge->use_xm_link_timer = 1;
00750 }
00751 
00752 static int xm_check_link(struct net_device *dev)
00753 {
00754         struct skge_port *skge = netdev_priv(dev);
00755         struct skge_hw *hw = skge->hw;
00756         int port = skge->port;
00757         u16 status;
00758 
00759         /* read twice because of latch */
00760         xm_phy_read(hw, port, PHY_XMAC_STAT);
00761         status = xm_phy_read(hw, port, PHY_XMAC_STAT);
00762 
00763         if ((status & PHY_ST_LSYNC) == 0) {
00764                 xm_link_down(hw, port);
00765                 return 0;
00766         }
00767 
00768         if (skge->autoneg == AUTONEG_ENABLE) {
00769                 u16 lpa, res;
00770 
00771                 if (!(status & PHY_ST_AN_OVER))
00772                         return 0;
00773 
00774                 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
00775                 if (lpa & PHY_B_AN_RF) {
00776                         DBG(PFX "%s: remote fault\n",
00777                                dev->name);
00778                         return 0;
00779                 }
00780 
00781                 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
00782 
00783                 /* Check Duplex mismatch */
00784                 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
00785                 case PHY_X_RS_FD:
00786                         skge->duplex = DUPLEX_FULL;
00787                         break;
00788                 case PHY_X_RS_HD:
00789                         skge->duplex = DUPLEX_HALF;
00790                         break;
00791                 default:
00792                         DBG(PFX "%s: duplex mismatch\n",
00793                                dev->name);
00794                         return 0;
00795                 }
00796 
00797                 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
00798                 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
00799                      skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
00800                     (lpa & PHY_X_P_SYM_MD))
00801                         skge->flow_status = FLOW_STAT_SYMMETRIC;
00802                 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
00803                          (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
00804                         /* Enable PAUSE receive, disable PAUSE transmit */
00805                         skge->flow_status  = FLOW_STAT_REM_SEND;
00806                 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
00807                          (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
00808                         /* Disable PAUSE receive, enable PAUSE transmit */
00809                         skge->flow_status = FLOW_STAT_LOC_SEND;
00810                 else
00811                         skge->flow_status = FLOW_STAT_NONE;
00812 
00813                 skge->speed = SPEED_1000;
00814         }
00815 
00816         if (!netdev_link_ok(dev))
00817                 genesis_link_up(skge);
00818         return 1;
00819 }
00820 
00821 /* Poll to check for link coming up.
00822  *
00823  * Since internal PHY is wired to a level triggered pin, can't
00824  * get an interrupt when carrier is detected, need to poll for
00825  * link coming up.
00826  */
00827 static void xm_link_timer(struct skge_port *skge)
00828 {
00829         struct net_device *dev = skge->netdev;
00830         struct skge_hw *hw = skge->hw;
00831         int port = skge->port;
00832         int i;
00833 
00834         /*
00835          * Verify that the link by checking GPIO register three times.
00836          * This pin has the signal from the link_sync pin connected to it.
00837          */
00838         for (i = 0; i < 3; i++) {
00839                 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
00840                         return;
00841         }
00842 
00843         /* Re-enable interrupt to detect link down */
00844         if (xm_check_link(dev)) {
00845                 u16 msk = xm_read16(hw, port, XM_IMSK);
00846                 msk &= ~XM_IS_INP_ASS;
00847                 xm_write16(hw, port, XM_IMSK, msk);
00848                 xm_read16(hw, port, XM_ISRC);
00849         }
00850 }
00851 
00852 static void genesis_mac_init(struct skge_hw *hw, int port)
00853 {
00854         struct net_device *dev = hw->dev[port];
00855         struct skge_port *skge = netdev_priv(dev);
00856         int i;
00857         u32 r;
00858         const u8 zero[6]  = { 0 };
00859 
00860         for (i = 0; i < 10; i++) {
00861                 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
00862                              MFF_SET_MAC_RST);
00863                 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
00864                         goto reset_ok;
00865                 udelay(1);
00866         }
00867 
00868         DBG(PFX "%s: genesis reset failed\n", dev->name);
00869 
00870  reset_ok:
00871         /* Unreset the XMAC. */
00872         skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
00873 
00874         /*
00875          * Perform additional initialization for external PHYs,
00876          * namely for the 1000baseTX cards that use the XMAC's
00877          * GMII mode.
00878          */
00879         if (hw->phy_type != SK_PHY_XMAC) {
00880                 /* Take external Phy out of reset */
00881                 r = skge_read32(hw, B2_GP_IO);
00882                 if (port == 0)
00883                         r |= GP_DIR_0|GP_IO_0;
00884                 else
00885                         r |= GP_DIR_2|GP_IO_2;
00886 
00887                 skge_write32(hw, B2_GP_IO, r);
00888 
00889                 /* Enable GMII interface */
00890                 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
00891         }
00892 
00893 
00894         switch(hw->phy_type) {
00895         case SK_PHY_XMAC:
00896                 xm_phy_init(skge);
00897                 break;
00898         case SK_PHY_BCOM:
00899                 bcom_phy_init(skge);
00900                 bcom_check_link(hw, port);
00901         }
00902 
00903         /* Set Station Address */
00904         xm_outaddr(hw, port, XM_SA, dev->ll_addr);
00905 
00906         /* We don't use match addresses so clear */
00907         for (i = 1; i < 16; i++)
00908                 xm_outaddr(hw, port, XM_EXM(i), zero);
00909 
00910         /* Clear MIB counters */
00911         xm_write16(hw, port, XM_STAT_CMD,
00912                         XM_SC_CLR_RXC | XM_SC_CLR_TXC);
00913         /* Clear two times according to Errata #3 */
00914         xm_write16(hw, port, XM_STAT_CMD,
00915                         XM_SC_CLR_RXC | XM_SC_CLR_TXC);
00916 
00917         /* configure Rx High Water Mark (XM_RX_HI_WM) */
00918         xm_write16(hw, port, XM_RX_HI_WM, 1450);
00919 
00920         /* We don't need the FCS appended to the packet. */
00921         r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
00922 
00923         if (skge->duplex == DUPLEX_HALF) {
00924                 /*
00925                  * If in manual half duplex mode the other side might be in
00926                  * full duplex mode, so ignore if a carrier extension is not seen
00927                  * on frames received
00928                  */
00929                 r |= XM_RX_DIS_CEXT;
00930         }
00931         xm_write16(hw, port, XM_RX_CMD, r);
00932 
00933         /* We want short frames padded to 60 bytes. */
00934         xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
00935 
00936         xm_write16(hw, port, XM_TX_THR, 512);
00937 
00938         /*
00939          * Enable the reception of all error frames. This is is
00940          * a necessary evil due to the design of the XMAC. The
00941          * XMAC's receive FIFO is only 8K in size, however jumbo
00942          * frames can be up to 9000 bytes in length. When bad
00943          * frame filtering is enabled, the XMAC's RX FIFO operates
00944          * in 'store and forward' mode. For this to work, the
00945          * entire frame has to fit into the FIFO, but that means
00946          * that jumbo frames larger than 8192 bytes will be
00947          * truncated. Disabling all bad frame filtering causes
00948          * the RX FIFO to operate in streaming mode, in which
00949          * case the XMAC will start transferring frames out of the
00950          * RX FIFO as soon as the FIFO threshold is reached.
00951          */
00952         xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
00953 
00954 
00955         /*
00956          * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
00957          *      - Enable all bits excepting 'Octets Rx OK Low CntOv'
00958          *        and 'Octets Rx OK Hi Cnt Ov'.
00959          */
00960         xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
00961 
00962         /*
00963          * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
00964          *      - Enable all bits excepting 'Octets Tx OK Low CntOv'
00965          *        and 'Octets Tx OK Hi Cnt Ov'.
00966          */
00967         xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
00968 
00969         /* Configure MAC arbiter */
00970         skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
00971 
00972         /* configure timeout values */
00973         skge_write8(hw, B3_MA_TOINI_RX1, 72);
00974         skge_write8(hw, B3_MA_TOINI_RX2, 72);
00975         skge_write8(hw, B3_MA_TOINI_TX1, 72);
00976         skge_write8(hw, B3_MA_TOINI_TX2, 72);
00977 
00978         skge_write8(hw, B3_MA_RCINI_RX1, 0);
00979         skge_write8(hw, B3_MA_RCINI_RX2, 0);
00980         skge_write8(hw, B3_MA_RCINI_TX1, 0);
00981         skge_write8(hw, B3_MA_RCINI_TX2, 0);
00982 
00983         /* Configure Rx MAC FIFO */
00984         skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
00985         skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
00986         skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
00987 
00988         /* Configure Tx MAC FIFO */
00989         skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
00990         skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
00991         skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
00992 
00993         /* enable timeout timers */
00994         skge_write16(hw, B3_PA_CTRL,
00995                      (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
00996 }
00997 
00998 static void genesis_stop(struct skge_port *skge)
00999 {
01000         struct skge_hw *hw = skge->hw;
01001         int port = skge->port;
01002         unsigned retries = 1000;
01003         u16 cmd;
01004 
01005         /* Disable Tx and Rx */
01006         cmd = xm_read16(hw, port, XM_MMU_CMD);
01007         cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
01008         xm_write16(hw, port, XM_MMU_CMD, cmd);
01009 
01010         genesis_reset(hw, port);
01011 
01012         /* Clear Tx packet arbiter timeout IRQ */
01013         skge_write16(hw, B3_PA_CTRL,
01014                      port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
01015 
01016         /* Reset the MAC */
01017         skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
01018         do {
01019                 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
01020                 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
01021                         break;
01022         } while (--retries > 0);
01023 
01024         /* For external PHYs there must be special handling */
01025         if (hw->phy_type != SK_PHY_XMAC) {
01026                 u32 reg = skge_read32(hw, B2_GP_IO);
01027                 if (port == 0) {
01028                         reg |= GP_DIR_0;
01029                         reg &= ~GP_IO_0;
01030                 } else {
01031                         reg |= GP_DIR_2;
01032                         reg &= ~GP_IO_2;
01033                 }
01034                 skge_write32(hw, B2_GP_IO, reg);
01035                 skge_read32(hw, B2_GP_IO);
01036         }
01037 
01038         xm_write16(hw, port, XM_MMU_CMD,
01039                         xm_read16(hw, port, XM_MMU_CMD)
01040                         & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
01041 
01042         xm_read16(hw, port, XM_MMU_CMD);
01043 }
01044 
01045 static void genesis_link_up(struct skge_port *skge)
01046 {
01047         struct skge_hw *hw = skge->hw;
01048         int port = skge->port;
01049         u16 cmd, msk;
01050         u32 mode;
01051 
01052         cmd = xm_read16(hw, port, XM_MMU_CMD);
01053 
01054         /*
01055          * enabling pause frame reception is required for 1000BT
01056          * because the XMAC is not reset if the link is going down
01057          */
01058         if (skge->flow_status == FLOW_STAT_NONE ||
01059             skge->flow_status == FLOW_STAT_LOC_SEND)
01060                 /* Disable Pause Frame Reception */
01061                 cmd |= XM_MMU_IGN_PF;
01062         else
01063                 /* Enable Pause Frame Reception */
01064                 cmd &= ~XM_MMU_IGN_PF;
01065 
01066         xm_write16(hw, port, XM_MMU_CMD, cmd);
01067 
01068         mode = xm_read32(hw, port, XM_MODE);
01069         if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
01070             skge->flow_status == FLOW_STAT_LOC_SEND) {
01071                 /*
01072                  * Configure Pause Frame Generation
01073                  * Use internal and external Pause Frame Generation.
01074                  * Sending pause frames is edge triggered.
01075                  * Send a Pause frame with the maximum pause time if
01076                  * internal oder external FIFO full condition occurs.
01077                  * Send a zero pause time frame to re-start transmission.
01078                  */
01079                 /* XM_PAUSE_DA = '010000C28001' (default) */
01080                 /* XM_MAC_PTIME = 0xffff (maximum) */
01081                 /* remember this value is defined in big endian (!) */
01082                 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
01083 
01084                 mode |= XM_PAUSE_MODE;
01085                 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
01086         } else {
01087                 /*
01088                  * disable pause frame generation is required for 1000BT
01089                  * because the XMAC is not reset if the link is going down
01090                  */
01091                 /* Disable Pause Mode in Mode Register */
01092                 mode &= ~XM_PAUSE_MODE;
01093 
01094                 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
01095         }
01096 
01097         xm_write32(hw, port, XM_MODE, mode);
01098 
01099         /* Turn on detection of Tx underrun */
01100         msk = xm_read16(hw, port, XM_IMSK);
01101         msk &= ~XM_IS_TXF_UR;
01102         xm_write16(hw, port, XM_IMSK, msk);
01103 
01104         xm_read16(hw, port, XM_ISRC);
01105 
01106         /* get MMU Command Reg. */
01107         cmd = xm_read16(hw, port, XM_MMU_CMD);
01108         if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
01109                 cmd |= XM_MMU_GMII_FD;
01110 
01111         /*
01112          * Workaround BCOM Errata (#10523) for all BCom Phys
01113          * Enable Power Management after link up
01114          */
01115         if (hw->phy_type == SK_PHY_BCOM) {
01116                 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
01117                              xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
01118                              & ~PHY_B_AC_DIS_PM);
01119                 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
01120         }
01121 
01122         /* enable Rx/Tx */
01123         xm_write16(hw, port, XM_MMU_CMD,
01124                         cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
01125         skge_link_up(skge);
01126 }
01127 
01128 
01129 static inline void bcom_phy_intr(struct skge_port *skge)
01130 {
01131         struct skge_hw *hw = skge->hw;
01132         int port = skge->port;
01133         u16 isrc;
01134 
01135         isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
01136         DBGIO(PFX "%s: phy interrupt status 0x%x\n",
01137              skge->netdev->name, isrc);
01138 
01139         if (isrc & PHY_B_IS_PSE)
01140                 DBG(PFX "%s: uncorrectable pair swap error\n",
01141                     hw->dev[port]->name);
01142 
01143         /* Workaround BCom Errata:
01144          *      enable and disable loopback mode if "NO HCD" occurs.
01145          */
01146         if (isrc & PHY_B_IS_NO_HDCL) {
01147                 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
01148                 xm_phy_write(hw, port, PHY_BCOM_CTRL,
01149                                   ctrl | PHY_CT_LOOP);
01150                 xm_phy_write(hw, port, PHY_BCOM_CTRL,
01151                                   ctrl & ~PHY_CT_LOOP);
01152         }
01153 
01154         if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
01155                 bcom_check_link(hw, port);
01156 
01157 }
01158 
01159 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
01160 {
01161         int i;
01162 
01163         gma_write16(hw, port, GM_SMI_DATA, val);
01164         gma_write16(hw, port, GM_SMI_CTRL,
01165                          GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
01166         for (i = 0; i < PHY_RETRIES; i++) {
01167                 udelay(1);
01168 
01169                 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
01170                         return 0;
01171         }
01172 
01173         DBG(PFX "%s: phy write timeout port %x reg %x val %x\n",
01174             hw->dev[port]->name,
01175             port, reg, val);
01176         return -EIO;
01177 }
01178 
01179 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
01180 {
01181         int i;
01182 
01183         gma_write16(hw, port, GM_SMI_CTRL,
01184                          GM_SMI_CT_PHY_AD(hw->phy_addr)
01185                          | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
01186 
01187         for (i = 0; i < PHY_RETRIES; i++) {
01188                 udelay(1);
01189                 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
01190                         goto ready;
01191         }
01192 
01193         return -ETIMEDOUT;
01194  ready:
01195         *val = gma_read16(hw, port, GM_SMI_DATA);
01196         return 0;
01197 }
01198 
01199 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
01200 {
01201         u16 v = 0;
01202         if (__gm_phy_read(hw, port, reg, &v))
01203                 DBG(PFX "%s: phy read timeout port %x reg %x val %x\n",
01204                hw->dev[port]->name,
01205                port, reg, v);
01206         return v;
01207 }
01208 
01209 /* Marvell Phy Initialization */
01210 static void yukon_init(struct skge_hw *hw, int port)
01211 {
01212         struct skge_port *skge = netdev_priv(hw->dev[port]);
01213         u16 ctrl, ct1000, adv;
01214 
01215         if (skge->autoneg == AUTONEG_ENABLE) {
01216                 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
01217 
01218                 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
01219                           PHY_M_EC_MAC_S_MSK);
01220                 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
01221 
01222                 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
01223 
01224                 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
01225         }
01226 
01227         ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
01228         if (skge->autoneg == AUTONEG_DISABLE)
01229                 ctrl &= ~PHY_CT_ANE;
01230 
01231         ctrl |= PHY_CT_RESET;
01232         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
01233 
01234         ctrl = 0;
01235         ct1000 = 0;
01236         adv = PHY_AN_CSMA;
01237 
01238         if (skge->autoneg == AUTONEG_ENABLE) {
01239                 if (hw->copper) {
01240                         if (skge->advertising & ADVERTISED_1000baseT_Full)
01241                                 ct1000 |= PHY_M_1000C_AFD;
01242                         if (skge->advertising & ADVERTISED_1000baseT_Half)
01243                                 ct1000 |= PHY_M_1000C_AHD;
01244                         if (skge->advertising & ADVERTISED_100baseT_Full)
01245                                 adv |= PHY_M_AN_100_FD;
01246                         if (skge->advertising & ADVERTISED_100baseT_Half)
01247                                 adv |= PHY_M_AN_100_HD;
01248                         if (skge->advertising & ADVERTISED_10baseT_Full)
01249                                 adv |= PHY_M_AN_10_FD;
01250                         if (skge->advertising & ADVERTISED_10baseT_Half)
01251                                 adv |= PHY_M_AN_10_HD;
01252 
01253                         /* Set Flow-control capabilities */
01254                         adv |= phy_pause_map[skge->flow_control];
01255                 } else {
01256                         if (skge->advertising & ADVERTISED_1000baseT_Full)
01257                                 adv |= PHY_M_AN_1000X_AFD;
01258                         if (skge->advertising & ADVERTISED_1000baseT_Half)
01259                                 adv |= PHY_M_AN_1000X_AHD;
01260 
01261                         adv |= fiber_pause_map[skge->flow_control];
01262                 }
01263 
01264                 /* Restart Auto-negotiation */
01265                 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
01266         } else {
01267                 /* forced speed/duplex settings */
01268                 ct1000 = PHY_M_1000C_MSE;
01269 
01270                 if (skge->duplex == DUPLEX_FULL)
01271                         ctrl |= PHY_CT_DUP_MD;
01272 
01273                 switch (skge->speed) {
01274                 case SPEED_1000:
01275                         ctrl |= PHY_CT_SP1000;
01276                         break;
01277                 case SPEED_100:
01278                         ctrl |= PHY_CT_SP100;
01279                         break;
01280                 }
01281 
01282                 ctrl |= PHY_CT_RESET;
01283         }
01284 
01285         gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
01286 
01287         gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
01288         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
01289 
01290         /* Enable phy interrupt on autonegotiation complete (or link up) */
01291         if (skge->autoneg == AUTONEG_ENABLE)
01292                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
01293         else
01294                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
01295 }
01296 
01297 static void yukon_reset(struct skge_hw *hw, int port)
01298 {
01299         gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
01300         gma_write16(hw, port, GM_MC_ADDR_H1, 0);        /* clear MC hash */
01301         gma_write16(hw, port, GM_MC_ADDR_H2, 0);
01302         gma_write16(hw, port, GM_MC_ADDR_H3, 0);
01303         gma_write16(hw, port, GM_MC_ADDR_H4, 0);
01304 
01305         gma_write16(hw, port, GM_RX_CTRL,
01306                          gma_read16(hw, port, GM_RX_CTRL)
01307                          | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
01308 }
01309 
01310 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
01311 static int is_yukon_lite_a0(struct skge_hw *hw)
01312 {
01313         u32 reg;
01314         int ret;
01315 
01316         if (hw->chip_id != CHIP_ID_YUKON)
01317                 return 0;
01318 
01319         reg = skge_read32(hw, B2_FAR);
01320         skge_write8(hw, B2_FAR + 3, 0xff);
01321         ret = (skge_read8(hw, B2_FAR + 3) != 0);
01322         skge_write32(hw, B2_FAR, reg);
01323         return ret;
01324 }
01325 
01326 static void yukon_mac_init(struct skge_hw *hw, int port)
01327 {
01328         struct skge_port *skge = netdev_priv(hw->dev[port]);
01329         int i;
01330         u32 reg;
01331         const u8 *addr = hw->dev[port]->ll_addr;
01332 
01333         /* WA code for COMA mode -- set PHY reset */
01334         if (hw->chip_id == CHIP_ID_YUKON_LITE &&
01335             hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
01336                 reg = skge_read32(hw, B2_GP_IO);
01337                 reg |= GP_DIR_9 | GP_IO_9;
01338                 skge_write32(hw, B2_GP_IO, reg);
01339         }
01340 
01341         /* hard reset */
01342         skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
01343         skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
01344 
01345         /* WA code for COMA mode -- clear PHY reset */
01346         if (hw->chip_id == CHIP_ID_YUKON_LITE &&
01347             hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
01348                 reg = skge_read32(hw, B2_GP_IO);
01349                 reg |= GP_DIR_9;
01350                 reg &= ~GP_IO_9;
01351                 skge_write32(hw, B2_GP_IO, reg);
01352         }
01353 
01354         /* Set hardware config mode */
01355         reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
01356                 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
01357         reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
01358 
01359         /* Clear GMC reset */
01360         skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
01361         skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
01362         skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
01363 
01364         if (skge->autoneg == AUTONEG_DISABLE) {
01365                 reg = GM_GPCR_AU_ALL_DIS;
01366                 gma_write16(hw, port, GM_GP_CTRL,
01367                                  gma_read16(hw, port, GM_GP_CTRL) | reg);
01368 
01369                 switch (skge->speed) {
01370                 case SPEED_1000:
01371                         reg &= ~GM_GPCR_SPEED_100;
01372                         reg |= GM_GPCR_SPEED_1000;
01373                         break;
01374                 case SPEED_100:
01375                         reg &= ~GM_GPCR_SPEED_1000;
01376                         reg |= GM_GPCR_SPEED_100;
01377                         break;
01378                 case SPEED_10:
01379                         reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
01380                         break;
01381                 }
01382 
01383                 if (skge->duplex == DUPLEX_FULL)
01384                         reg |= GM_GPCR_DUP_FULL;
01385         } else
01386                 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
01387 
01388         switch (skge->flow_control) {
01389         case FLOW_MODE_NONE:
01390                 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
01391                 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
01392                 break;
01393         case FLOW_MODE_LOC_SEND:
01394                 /* disable Rx flow-control */
01395                 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
01396                 break;
01397         case FLOW_MODE_SYMMETRIC:
01398         case FLOW_MODE_SYM_OR_REM:
01399                 /* enable Tx & Rx flow-control */
01400                 break;
01401         }
01402 
01403         gma_write16(hw, port, GM_GP_CTRL, reg);
01404         skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
01405 
01406         yukon_init(hw, port);
01407 
01408         /* MIB clear */
01409         reg = gma_read16(hw, port, GM_PHY_ADDR);
01410         gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
01411 
01412         for (i = 0; i < GM_MIB_CNT_SIZE; i++)
01413                 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
01414         gma_write16(hw, port, GM_PHY_ADDR, reg);
01415 
01416         /* transmit control */
01417         gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
01418 
01419         /* receive control reg: unicast + multicast + no FCS  */
01420         gma_write16(hw, port, GM_RX_CTRL,
01421                          GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
01422 
01423         /* transmit flow control */
01424         gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
01425 
01426         /* transmit parameter */
01427         gma_write16(hw, port, GM_TX_PARAM,
01428                          TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
01429                          TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
01430                          TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
01431 
01432         /* configure the Serial Mode Register */
01433         reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
01434                 | GM_SMOD_VLAN_ENA
01435                 | IPG_DATA_VAL(IPG_DATA_DEF);
01436 
01437         gma_write16(hw, port, GM_SERIAL_MODE, reg);
01438 
01439         /* physical address: used for pause frames */
01440         gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
01441         /* virtual address for data */
01442         gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
01443 
01444         /* enable interrupt mask for counter overflows */
01445         gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
01446         gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
01447         gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
01448 
01449         /* Initialize Mac Fifo */
01450 
01451         /* Configure Rx MAC FIFO */
01452         skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
01453         reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
01454 
01455         /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
01456         if (is_yukon_lite_a0(hw))
01457                 reg &= ~GMF_RX_F_FL_ON;
01458 
01459         skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
01460         skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
01461         /*
01462          * because Pause Packet Truncation in GMAC is not working
01463          * we have to increase the Flush Threshold to 64 bytes
01464          * in order to flush pause packets in Rx FIFO on Yukon-1
01465          */
01466         skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
01467 
01468         /* Configure Tx MAC FIFO */
01469         skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
01470         skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
01471 }
01472 
01473 /* Go into power down mode */
01474 static void yukon_suspend(struct skge_hw *hw, int port)
01475 {
01476         u16 ctrl;
01477 
01478         ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
01479         ctrl |= PHY_M_PC_POL_R_DIS;
01480         gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
01481 
01482         ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
01483         ctrl |= PHY_CT_RESET;
01484         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
01485 
01486         /* switch IEEE compatible power down mode on */
01487         ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
01488         ctrl |= PHY_CT_PDOWN;
01489         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
01490 }
01491 
01492 static void yukon_stop(struct skge_port *skge)
01493 {
01494         struct skge_hw *hw = skge->hw;
01495         int port = skge->port;
01496 
01497         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
01498         yukon_reset(hw, port);
01499 
01500         gma_write16(hw, port, GM_GP_CTRL,
01501                          gma_read16(hw, port, GM_GP_CTRL)
01502                          & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
01503         gma_read16(hw, port, GM_GP_CTRL);
01504 
01505         yukon_suspend(hw, port);
01506 
01507         /* set GPHY Control reset */
01508         skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
01509         skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
01510 }
01511 
01512 static u16 yukon_speed(const struct skge_hw *hw __unused, u16 aux)
01513 {
01514         switch (aux & PHY_M_PS_SPEED_MSK) {
01515         case PHY_M_PS_SPEED_1000:
01516                 return SPEED_1000;
01517         case PHY_M_PS_SPEED_100:
01518                 return SPEED_100;
01519         default:
01520                 return SPEED_10;
01521         }
01522 }
01523 
01524 static void yukon_link_up(struct skge_port *skge)
01525 {
01526         struct skge_hw *hw = skge->hw;
01527         int port = skge->port;
01528         u16 reg;
01529 
01530         /* Enable Transmit FIFO Underrun */
01531         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
01532 
01533         reg = gma_read16(hw, port, GM_GP_CTRL);
01534         if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
01535                 reg |= GM_GPCR_DUP_FULL;
01536 
01537         /* enable Rx/Tx */
01538         reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
01539         gma_write16(hw, port, GM_GP_CTRL, reg);
01540 
01541         gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
01542         skge_link_up(skge);
01543 }
01544 
01545 static void yukon_link_down(struct skge_port *skge)
01546 {
01547         struct skge_hw *hw = skge->hw;
01548         int port = skge->port;
01549         u16 ctrl;
01550 
01551         ctrl = gma_read16(hw, port, GM_GP_CTRL);
01552         ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
01553         gma_write16(hw, port, GM_GP_CTRL, ctrl);
01554 
01555         if (skge->flow_status == FLOW_STAT_REM_SEND) {
01556                 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
01557                 ctrl |= PHY_M_AN_ASP;
01558                 /* restore Asymmetric Pause bit */
01559                 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
01560         }
01561 
01562         skge_link_down(skge);
01563 
01564         yukon_init(hw, port);
01565 }
01566 
01567 static void yukon_phy_intr(struct skge_port *skge)
01568 {
01569         struct skge_hw *hw = skge->hw;
01570         int port = skge->port;
01571         const char *reason = NULL;
01572         u16 istatus, phystat;
01573 
01574         istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
01575         phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
01576 
01577         DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
01578              skge->netdev->name, istatus, phystat);
01579 
01580         if (istatus & PHY_M_IS_AN_COMPL) {
01581                 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
01582                     & PHY_M_AN_RF) {
01583                         reason = "remote fault";
01584                         goto failed;
01585                 }
01586 
01587                 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
01588                         reason = "master/slave fault";
01589                         goto failed;
01590                 }
01591 
01592                 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
01593                         reason = "speed/duplex";
01594                         goto failed;
01595                 }
01596 
01597                 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
01598                         ? DUPLEX_FULL : DUPLEX_HALF;
01599                 skge->speed = yukon_speed(hw, phystat);
01600 
01601                 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
01602                 switch (phystat & PHY_M_PS_PAUSE_MSK) {
01603                 case PHY_M_PS_PAUSE_MSK:
01604                         skge->flow_status = FLOW_STAT_SYMMETRIC;
01605                         break;
01606                 case PHY_M_PS_RX_P_EN:
01607                         skge->flow_status = FLOW_STAT_REM_SEND;
01608                         break;
01609                 case PHY_M_PS_TX_P_EN:
01610                         skge->flow_status = FLOW_STAT_LOC_SEND;
01611                         break;
01612                 default:
01613                         skge->flow_status = FLOW_STAT_NONE;
01614                 }
01615 
01616                 if (skge->flow_status == FLOW_STAT_NONE ||
01617                     (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
01618                         skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
01619                 else
01620                         skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
01621                 yukon_link_up(skge);
01622                 return;
01623         }
01624 
01625         if (istatus & PHY_M_IS_LSP_CHANGE)
01626                 skge->speed = yukon_speed(hw, phystat);
01627 
01628         if (istatus & PHY_M_IS_DUP_CHANGE)
01629                 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
01630         if (istatus & PHY_M_IS_LST_CHANGE) {
01631                 if (phystat & PHY_M_PS_LINK_UP)
01632                         yukon_link_up(skge);
01633                 else
01634                         yukon_link_down(skge);
01635         }
01636         return;
01637  failed:
01638         DBG(PFX "%s: autonegotiation failed (%s)\n",
01639                skge->netdev->name, reason);
01640 
01641         /* XXX restart autonegotiation? */
01642 }
01643 
01644 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
01645 {
01646         u32 end;
01647 
01648         start /= 8;
01649         len /= 8;
01650         end = start + len - 1;
01651 
01652         skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
01653         skge_write32(hw, RB_ADDR(q, RB_START), start);
01654         skge_write32(hw, RB_ADDR(q, RB_WP), start);
01655         skge_write32(hw, RB_ADDR(q, RB_RP), start);
01656         skge_write32(hw, RB_ADDR(q, RB_END), end);
01657 
01658         if (q == Q_R1 || q == Q_R2) {
01659                 /* Set thresholds on receive queue's */
01660                 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
01661                              start + (2*len)/3);
01662                 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
01663                              start + (len/3));
01664         } else {
01665                 /* Enable store & forward on Tx queue's because
01666                  * Tx FIFO is only 4K on Genesis and 1K on Yukon
01667                  */
01668                 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
01669         }
01670 
01671         skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
01672 }
01673 
01674 /* Setup Bus Memory Interface */
01675 static void skge_qset(struct skge_port *skge, u16 q,
01676                       const struct skge_element *e)
01677 {
01678         struct skge_hw *hw = skge->hw;
01679         u32 watermark = 0x600;
01680         u64 base = skge->dma + (e->desc - skge->mem);
01681 
01682         /* optimization to reduce window on 32bit/33mhz */
01683         if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
01684                 watermark /= 2;
01685 
01686         skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
01687         skge_write32(hw, Q_ADDR(q, Q_F), watermark);
01688         skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
01689         skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
01690 }
01691 
01692 void skge_free(struct net_device *dev)
01693 {
01694         struct skge_port *skge = netdev_priv(dev);
01695 
01696         free(skge->rx_ring.start);
01697         skge->rx_ring.start = NULL;
01698 
01699         free(skge->tx_ring.start);
01700         skge->tx_ring.start = NULL;
01701 
01702         free_dma(skge->mem, RING_SIZE);
01703         skge->mem = NULL;
01704         skge->dma = 0;
01705 }
01706 
01707 static int skge_up(struct net_device *dev)
01708 {
01709         struct skge_port *skge = netdev_priv(dev);
01710         struct skge_hw *hw = skge->hw;
01711         int port = skge->port;
01712         u32 chunk, ram_addr;
01713         int err;
01714 
01715         DBG2(PFX "%s: enabling interface\n", dev->name);
01716 
01717         skge->mem = malloc_dma(RING_SIZE, SKGE_RING_ALIGN);
01718         skge->dma = virt_to_bus(skge->mem);
01719         if (!skge->mem)
01720                 return -ENOMEM;
01721         memset(skge->mem, 0, RING_SIZE);
01722 
01723         assert(!(skge->dma & 7));
01724 
01725         /* FIXME: find out whether 64 bit iPXE will be loaded > 4GB */
01726         if ((u64)skge->dma >> 32 != ((u64) skge->dma + RING_SIZE) >> 32) {
01727                 DBG(PFX "pci_alloc_consistent region crosses 4G boundary\n");
01728                 err = -EINVAL;
01729                 goto err;
01730         }
01731 
01732         err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma, NUM_RX_DESC);
01733         if (err)
01734                 goto err;
01735 
01736         /* this call relies on e->iob and d->control to be 0
01737          * This is assured by calling memset() on skge->mem and using zalloc()
01738          * for the skge_element structures.
01739          */
01740         skge_rx_refill(dev);
01741 
01742         err = skge_ring_alloc(&skge->tx_ring, skge->mem + RX_RING_SIZE,
01743                               skge->dma + RX_RING_SIZE, NUM_TX_DESC);
01744         if (err)
01745                 goto err;
01746 
01747         /* Initialize MAC */
01748         if (hw->chip_id == CHIP_ID_GENESIS)
01749                 genesis_mac_init(hw, port);
01750         else
01751                 yukon_mac_init(hw, port);
01752 
01753         /* Configure RAMbuffers - equally between ports and tx/rx */
01754         chunk = (hw->ram_size  - hw->ram_offset) / (hw->ports * 2);
01755         ram_addr = hw->ram_offset + 2 * chunk * port;
01756 
01757         skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
01758         skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
01759 
01760         assert(!(skge->tx_ring.to_use != skge->tx_ring.to_clean));
01761         skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
01762         skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
01763 
01764         /* Start receiver BMU */
01765         wmb();
01766         skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
01767         skge_led(skge, LED_MODE_ON);
01768 
01769         hw->intr_mask |= portmask[port];
01770         skge_write32(hw, B0_IMSK, hw->intr_mask);
01771 
01772         return 0;
01773 
01774  err:
01775         skge_rx_clean(skge);
01776         skge_free(dev);
01777 
01778         return err;
01779 }
01780 
01781 /* stop receiver */
01782 static void skge_rx_stop(struct skge_hw *hw, int port)
01783 {
01784         skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
01785         skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
01786                      RB_RST_SET|RB_DIS_OP_MD);
01787         skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
01788 }
01789 
01790 static void skge_down(struct net_device *dev)
01791 {
01792         struct skge_port *skge = netdev_priv(dev);
01793         struct skge_hw *hw = skge->hw;
01794         int port = skge->port;
01795 
01796         if (skge->mem == NULL)
01797                 return;
01798 
01799         DBG2(PFX "%s: disabling interface\n", dev->name);
01800 
01801         if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
01802                 skge->use_xm_link_timer = 0;
01803 
01804         netdev_link_down(dev);
01805 
01806         hw->intr_mask &= ~portmask[port];
01807         skge_write32(hw, B0_IMSK, hw->intr_mask);
01808 
01809         skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
01810         if (hw->chip_id == CHIP_ID_GENESIS)
01811                 genesis_stop(skge);
01812         else
01813                 yukon_stop(skge);
01814 
01815         /* Stop transmitter */
01816         skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
01817         skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
01818                      RB_RST_SET|RB_DIS_OP_MD);
01819 
01820 
01821         /* Disable Force Sync bit and Enable Alloc bit */
01822         skge_write8(hw, SK_REG(port, TXA_CTRL),
01823                     TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
01824 
01825         /* Stop Interval Timer and Limit Counter of Tx Arbiter */
01826         skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
01827         skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
01828 
01829         /* Reset PCI FIFO */
01830         skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
01831         skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
01832 
01833         /* Reset the RAM Buffer async Tx queue */
01834         skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
01835 
01836         skge_rx_stop(hw, port);
01837 
01838         if (hw->chip_id == CHIP_ID_GENESIS) {
01839                 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
01840                 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
01841         } else {
01842                 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
01843                 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
01844         }
01845 
01846         skge_led(skge, LED_MODE_OFF);
01847 
01848         skge_tx_clean(dev);
01849 
01850         skge_rx_clean(skge);
01851 
01852         skge_free(dev);
01853         return;
01854 }
01855 
01856 static inline int skge_tx_avail(const struct skge_ring *ring)
01857 {
01858         mb();
01859         return ((ring->to_clean > ring->to_use) ? 0 : NUM_TX_DESC)
01860                 + (ring->to_clean - ring->to_use) - 1;
01861 }
01862 
01863 static int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob)
01864 {
01865         struct skge_port *skge = netdev_priv(dev);
01866         struct skge_hw *hw = skge->hw;
01867         struct skge_element *e;
01868         struct skge_tx_desc *td;
01869         u32 control, len;
01870         u64 map;
01871 
01872         if (skge_tx_avail(&skge->tx_ring) < 1)
01873                 return -EBUSY;
01874 
01875         e = skge->tx_ring.to_use;
01876         td = e->desc;
01877         assert(!(td->control & BMU_OWN));
01878         e->iob = iob;
01879         len = iob_len(iob);
01880         map = virt_to_bus(iob->data);
01881 
01882         td->dma_lo = map;
01883         td->dma_hi = map >> 32;
01884 
01885         control = BMU_CHECK;
01886 
01887         control |= BMU_EOF| BMU_IRQ_EOF;
01888         /* Make sure all the descriptors written */
01889         wmb();
01890         td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
01891         wmb();
01892 
01893         skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
01894 
01895         DBGIO(PFX "%s: tx queued, slot %td, len %d\n",
01896              dev->name, e - skge->tx_ring.start, (unsigned int)len);
01897 
01898         skge->tx_ring.to_use = e->next;
01899         wmb();
01900 
01901         if (skge_tx_avail(&skge->tx_ring) <= 1) {
01902                 DBG(PFX "%s: transmit queue full\n", dev->name);
01903         }
01904 
01905         return 0;
01906 }
01907 
01908 /* Free all buffers in transmit ring */
01909 static void skge_tx_clean(struct net_device *dev)
01910 {
01911         struct skge_port *skge = netdev_priv(dev);
01912         struct skge_element *e;
01913 
01914         for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
01915                 struct skge_tx_desc *td = e->desc;
01916                 td->control = 0;
01917         }
01918 
01919         skge->tx_ring.to_clean = e;
01920 }
01921 
01922 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
01923 {
01924         if (hw->chip_id == CHIP_ID_GENESIS)
01925                 return status >> XMR_FS_LEN_SHIFT;
01926         else
01927                 return status >> GMR_FS_LEN_SHIFT;
01928 }
01929 
01930 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
01931 {
01932         if (hw->chip_id == CHIP_ID_GENESIS)
01933                 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
01934         else
01935                 return (status & GMR_FS_ANY_ERR) ||
01936                         (status & GMR_FS_RX_OK) == 0;
01937 }
01938 
01939 /* Free all buffers in Tx ring which are no longer owned by device */
01940 static void skge_tx_done(struct net_device *dev)
01941 {
01942         struct skge_port *skge = netdev_priv(dev);
01943         struct skge_ring *ring = &skge->tx_ring;
01944         struct skge_element *e;
01945 
01946         skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
01947 
01948         for (e = ring->to_clean; e != ring->to_use; e = e->next) {
01949                 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
01950 
01951                 if (control & BMU_OWN)
01952                         break;
01953 
01954                 netdev_tx_complete(dev, e->iob);
01955         }
01956         skge->tx_ring.to_clean = e;
01957 
01958         /* Can run lockless until we need to synchronize to restart queue. */
01959         mb();
01960 }
01961 
01962 static void skge_rx_refill(struct net_device *dev)
01963 {
01964         struct skge_port *skge = netdev_priv(dev);
01965         struct skge_ring *ring = &skge->rx_ring;
01966         struct skge_element *e;
01967         struct io_buffer *iob;
01968         struct skge_rx_desc *rd;
01969         u32 control;
01970         int i;
01971 
01972         for (i = 0; i < NUM_RX_DESC; i++) {
01973                 e = ring->to_clean;
01974                 rd = e->desc;
01975                 iob = e->iob;
01976                 control = rd->control;
01977 
01978                 /* nothing to do here */
01979                 if (iob || (control & BMU_OWN))
01980                         continue;
01981 
01982                 DBG2("refilling rx desc %zd: ", (ring->to_clean - ring->start));
01983 
01984                 iob = alloc_iob(RX_BUF_SIZE);
01985                 if (iob) {
01986                         skge_rx_setup(skge, e, iob, RX_BUF_SIZE);
01987                 } else {
01988                         DBG("descr %zd: alloc_iob() failed\n",
01989                              (ring->to_clean - ring->start));
01990                         /* We pass the descriptor to the NIC even if the
01991                          * allocation failed. The card will stop as soon as it
01992                          * encounters a descriptor with the OWN bit set to 0,
01993                          * thus never getting to the next descriptor that might
01994                          * contain a valid io_buffer. This would effectively
01995                          * stall the receive.
01996                          */
01997                         skge_rx_setup(skge, e, NULL, 0);
01998                 }
01999 
02000                 ring->to_clean = e->next;
02001         }
02002 }
02003 
02004 static void skge_rx_done(struct net_device *dev)
02005 {
02006         struct skge_port *skge = netdev_priv(dev);
02007         struct skge_ring *ring = &skge->rx_ring;
02008         struct skge_rx_desc *rd;
02009         struct skge_element *e;
02010         struct io_buffer *iob;
02011         u32 control;
02012         u16 len;
02013         int i;
02014 
02015         e = ring->to_clean;
02016         for (i = 0; i < NUM_RX_DESC; i++) {
02017                 iob = e->iob;
02018                 rd = e->desc;
02019 
02020                 rmb();
02021                 control = rd->control;
02022 
02023                 if ((control & BMU_OWN))
02024                         break;
02025 
02026                 if (!iob)
02027                         continue;
02028 
02029                 len = control & BMU_BBC;
02030 
02031                 /* catch RX errors */
02032                 if ((bad_phy_status(skge->hw, rd->status)) ||
02033                    (phy_length(skge->hw, rd->status) != len)) {
02034                         /* report receive errors */
02035                         DBG("rx error\n");
02036                         netdev_rx_err(dev, iob, -EIO);
02037                 } else {
02038                         DBG2("received packet, len %d\n", len);
02039                         iob_put(iob, len);
02040                         netdev_rx(dev, iob);
02041                 }
02042 
02043                 /* io_buffer passed to core, make sure we don't reuse it */
02044                 e->iob = NULL;
02045 
02046                 e = e->next;
02047         }
02048         skge_rx_refill(dev);
02049 }
02050 
02051 static void skge_poll(struct net_device *dev)
02052 {
02053         struct skge_port *skge = netdev_priv(dev);
02054         struct skge_hw *hw = skge->hw;
02055         u32 status;
02056 
02057         /* reading this register ACKs interrupts */
02058         status = skge_read32(hw, B0_SP_ISRC);
02059 
02060         /* Link event? */
02061         if (status & IS_EXT_REG) {
02062                 skge_phyirq(hw);
02063                 if (skge->use_xm_link_timer)
02064                         xm_link_timer(skge);
02065         }
02066 
02067         skge_tx_done(dev);
02068 
02069         skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
02070 
02071         skge_rx_done(dev);
02072 
02073         /* restart receiver */
02074         wmb();
02075         skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
02076 
02077         skge_read32(hw, B0_IMSK);
02078 
02079         return;
02080 }
02081 
02082 static void skge_phyirq(struct skge_hw *hw)
02083 {
02084         int port;
02085 
02086         for (port = 0; port < hw->ports; port++) {
02087                 struct net_device *dev = hw->dev[port];
02088                 struct skge_port *skge = netdev_priv(dev);
02089 
02090                 if (hw->chip_id != CHIP_ID_GENESIS)
02091                         yukon_phy_intr(skge);
02092                 else if (hw->phy_type == SK_PHY_BCOM)
02093                         bcom_phy_intr(skge);
02094         }
02095 
02096         hw->intr_mask |= IS_EXT_REG;
02097         skge_write32(hw, B0_IMSK, hw->intr_mask);
02098         skge_read32(hw, B0_IMSK);
02099 }
02100 
02101 static const struct {
02102         u8 id;
02103         const char *name;
02104 } skge_chips[] = {
02105         { CHIP_ID_GENESIS,      "Genesis" },
02106         { CHIP_ID_YUKON,         "Yukon" },
02107         { CHIP_ID_YUKON_LITE,    "Yukon-Lite"},
02108         { CHIP_ID_YUKON_LP,      "Yukon-LP"},
02109 };
02110 
02111 static const char *skge_board_name(const struct skge_hw *hw)
02112 {
02113         unsigned int i;
02114         static char buf[16];
02115 
02116         for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
02117                 if (skge_chips[i].id == hw->chip_id)
02118                         return skge_chips[i].name;
02119 
02120         snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
02121         return buf;
02122 }
02123 
02124 
02125 /*
02126  * Setup the board data structure, but don't bring up
02127  * the port(s)
02128  */
02129 static int skge_reset(struct skge_hw *hw)
02130 {
02131         u32 reg;
02132         u16 ctst, pci_status;
02133         u8 t8, mac_cfg, pmd_type;
02134         int i;
02135 
02136         ctst = skge_read16(hw, B0_CTST);
02137 
02138         /* do a SW reset */
02139         skge_write8(hw, B0_CTST, CS_RST_SET);
02140         skge_write8(hw, B0_CTST, CS_RST_CLR);
02141 
02142         /* clear PCI errors, if any */
02143         skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
02144         skge_write8(hw, B2_TST_CTRL2, 0);
02145 
02146         pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
02147         pci_write_config_word(hw->pdev, PCI_STATUS,
02148                               pci_status | PCI_STATUS_ERROR_BITS);
02149         skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
02150         skge_write8(hw, B0_CTST, CS_MRST_CLR);
02151 
02152         /* restore CLK_RUN bits (for Yukon-Lite) */
02153         skge_write16(hw, B0_CTST,
02154                      ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
02155 
02156         hw->chip_id = skge_read8(hw, B2_CHIP_ID);
02157         hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
02158         pmd_type = skge_read8(hw, B2_PMD_TYP);
02159         hw->copper = (pmd_type == 'T' || pmd_type == '1');
02160 
02161         switch (hw->chip_id) {
02162         case CHIP_ID_GENESIS:
02163                 switch (hw->phy_type) {
02164                 case SK_PHY_XMAC:
02165                         hw->phy_addr = PHY_ADDR_XMAC;
02166                         break;
02167                 case SK_PHY_BCOM:
02168                         hw->phy_addr = PHY_ADDR_BCOM;
02169                         break;
02170                 default:
02171                         DBG(PFX "unsupported phy type 0x%x\n",
02172                                hw->phy_type);
02173                         return -EOPNOTSUPP;
02174                 }
02175                 break;
02176 
02177         case CHIP_ID_YUKON:
02178         case CHIP_ID_YUKON_LITE:
02179         case CHIP_ID_YUKON_LP:
02180                 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
02181                         hw->copper = 1;
02182 
02183                 hw->phy_addr = PHY_ADDR_MARV;
02184                 break;
02185 
02186         default:
02187                 DBG(PFX "unsupported chip type 0x%x\n",
02188                        hw->chip_id);
02189                 return -EOPNOTSUPP;
02190         }
02191 
02192         mac_cfg = skge_read8(hw, B2_MAC_CFG);
02193         hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
02194         hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
02195 
02196         /* read the adapters RAM size */
02197         t8 = skge_read8(hw, B2_E_0);
02198         if (hw->chip_id == CHIP_ID_GENESIS) {
02199                 if (t8 == 3) {
02200                         /* special case: 4 x 64k x 36, offset = 0x80000 */
02201                         hw->ram_size = 0x100000;
02202                         hw->ram_offset = 0x80000;
02203                 } else
02204                         hw->ram_size = t8 * 512;
02205         }
02206         else if (t8 == 0)
02207                 hw->ram_size = 0x20000;
02208         else
02209                 hw->ram_size = t8 * 4096;
02210 
02211         hw->intr_mask = IS_HW_ERR;
02212 
02213         /* Use PHY IRQ for all but fiber based Genesis board */
02214         if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
02215                 hw->intr_mask |= IS_EXT_REG;
02216 
02217         if (hw->chip_id == CHIP_ID_GENESIS)
02218                 genesis_init(hw);
02219         else {
02220                 /* switch power to VCC (WA for VAUX problem) */
02221                 skge_write8(hw, B0_POWER_CTRL,
02222                             PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
02223 
02224                 /* avoid boards with stuck Hardware error bits */
02225                 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
02226                     (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
02227                         DBG(PFX "stuck hardware sensor bit\n");
02228                         hw->intr_mask &= ~IS_HW_ERR;
02229                 }
02230 
02231                 /* Clear PHY COMA */
02232                 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
02233                 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
02234                 reg &= ~PCI_PHY_COMA;
02235                 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
02236                 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
02237 
02238 
02239                 for (i = 0; i < hw->ports; i++) {
02240                         skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
02241                         skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
02242                 }
02243         }
02244 
02245         /* turn off hardware timer (unused) */
02246         skge_write8(hw, B2_TI_CTRL, TIM_STOP);
02247         skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
02248         skge_write8(hw, B0_LED, LED_STAT_ON);
02249 
02250         /* enable the Tx Arbiters */
02251         for (i = 0; i < hw->ports; i++)
02252                 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
02253 
02254         /* Initialize ram interface */
02255         skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
02256 
02257         skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
02258         skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
02259         skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
02260         skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
02261         skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
02262         skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
02263         skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
02264         skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
02265         skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
02266         skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
02267         skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
02268         skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
02269 
02270         skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
02271 
02272         /* Set interrupt moderation for Transmit only
02273          * Receive interrupts avoided by NAPI
02274          */
02275         skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
02276         skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
02277         skge_write32(hw, B2_IRQM_CTRL, TIM_START);
02278 
02279         skge_write32(hw, B0_IMSK, hw->intr_mask);
02280 
02281         for (i = 0; i < hw->ports; i++) {
02282                 if (hw->chip_id == CHIP_ID_GENESIS)
02283                         genesis_reset(hw, i);
02284                 else
02285                         yukon_reset(hw, i);
02286         }
02287 
02288         return 0;
02289 }
02290 
02291 /* Initialize network device */
02292 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
02293                                        int highmem __unused)
02294 {
02295         struct skge_port *skge;
02296         struct net_device *dev = alloc_etherdev(sizeof(*skge));
02297 
02298         if (!dev) {
02299                 DBG(PFX "etherdev alloc failed\n");
02300                 return NULL;
02301         }
02302 
02303         dev->dev = &hw->pdev->dev;
02304 
02305         skge = netdev_priv(dev);
02306         skge->netdev = dev;
02307         skge->hw = hw;
02308 
02309         /* Auto speed and flow control */
02310         skge->autoneg = AUTONEG_ENABLE;
02311         skge->flow_control = FLOW_MODE_SYM_OR_REM;
02312         skge->duplex = -1;
02313         skge->speed = -1;
02314         skge->advertising = skge_supported_modes(hw);
02315 
02316         hw->dev[port] = dev;
02317 
02318         skge->port = port;
02319 
02320         /* read the mac address */
02321         memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN);
02322 
02323         return dev;
02324 }
02325 
02326 static void skge_show_addr(struct net_device *dev)
02327 {
02328         DBG2(PFX "%s: addr %s\n",
02329              dev->name, netdev_addr(dev));
02330 }
02331 
02332 static int skge_probe(struct pci_device *pdev)
02333 {
02334         struct net_device *dev, *dev1;
02335         struct skge_hw *hw;
02336         int err, using_dac = 0;
02337 
02338         adjust_pci_device(pdev);
02339 
02340         err = -ENOMEM;
02341         hw = zalloc(sizeof(*hw));
02342         if (!hw) {
02343                 DBG(PFX "cannot allocate hardware struct\n");
02344                 goto err_out_free_regions;
02345         }
02346 
02347         hw->pdev = pdev;
02348 
02349         hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0),
02350                                 SKGE_REG_SIZE);
02351         if (!hw->regs) {
02352                 DBG(PFX "cannot map device registers\n");
02353                 goto err_out_free_hw;
02354         }
02355 
02356         err = skge_reset(hw);
02357         if (err)
02358                 goto err_out_iounmap;
02359 
02360         DBG(PFX " addr 0x%llx irq %d chip %s rev %d\n",
02361             (unsigned long long)pdev->ioaddr, pdev->irq,
02362             skge_board_name(hw), hw->chip_rev);
02363 
02364         dev = skge_devinit(hw, 0, using_dac);
02365         if (!dev)
02366                 goto err_out_led_off;
02367 
02368         netdev_init ( dev, &skge_operations );
02369 
02370         err = register_netdev(dev);
02371         if (err) {
02372                 DBG(PFX "cannot register net device\n");
02373                 goto err_out_free_netdev;
02374         }
02375 
02376         skge_show_addr(dev);
02377 
02378         if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
02379                 if (register_netdev(dev1) == 0)
02380                         skge_show_addr(dev1);
02381                 else {
02382                         /* Failure to register second port need not be fatal */
02383                         DBG(PFX "register of second port failed\n");
02384                         hw->dev[1] = NULL;
02385                         netdev_nullify(dev1);
02386                         netdev_put(dev1);
02387                 }
02388         }
02389         pci_set_drvdata(pdev, hw);
02390 
02391         return 0;
02392 
02393 err_out_free_netdev:
02394         netdev_nullify(dev);
02395         netdev_put(dev);
02396 err_out_led_off:
02397         skge_write16(hw, B0_LED, LED_STAT_OFF);
02398 err_out_iounmap:
02399         iounmap((void*)hw->regs);
02400 err_out_free_hw:
02401         free(hw);
02402 err_out_free_regions:
02403         pci_set_drvdata(pdev, NULL);
02404         return err;
02405 }
02406 
02407 static void skge_remove(struct pci_device *pdev)
02408 {
02409         struct skge_hw *hw  = pci_get_drvdata(pdev);
02410         struct net_device *dev0, *dev1;
02411 
02412         if (!hw)
02413                 return;
02414 
02415         if ((dev1 = hw->dev[1]))
02416                 unregister_netdev(dev1);
02417         dev0 = hw->dev[0];
02418         unregister_netdev(dev0);
02419 
02420         hw->intr_mask = 0;
02421         skge_write32(hw, B0_IMSK, 0);
02422         skge_read32(hw, B0_IMSK);
02423 
02424         skge_write16(hw, B0_LED, LED_STAT_OFF);
02425         skge_write8(hw, B0_CTST, CS_RST_SET);
02426 
02427         if (dev1) {
02428                 netdev_nullify(dev1);
02429                 netdev_put(dev1);
02430         }
02431         netdev_nullify(dev0);
02432         netdev_put(dev0);
02433 
02434         iounmap((void*)hw->regs);
02435         free(hw);
02436         pci_set_drvdata(pdev, NULL);
02437 }
02438 
02439 /*
02440  * Enable or disable IRQ masking.
02441  *
02442  * @v netdev            Device to control.
02443  * @v enable            Zero to mask off IRQ, non-zero to enable IRQ.
02444  *
02445  * This is a iPXE Network Driver API function.
02446  */
02447 static void skge_net_irq ( struct net_device *dev, int enable ) {
02448         struct skge_port *skge = netdev_priv(dev);
02449         struct skge_hw *hw = skge->hw;
02450 
02451         if (enable)
02452                 hw->intr_mask |= portmask[skge->port];
02453         else
02454                 hw->intr_mask &= ~portmask[skge->port];
02455         skge_write32(hw, B0_IMSK, hw->intr_mask);
02456 }
02457 
02458 struct pci_driver skge_driver __pci_driver = {
02459         .ids      = skge_id_table,
02460         .id_count = ( sizeof (skge_id_table) / sizeof (skge_id_table[0]) ),
02461         .probe    = skge_probe,
02462         .remove   = skge_remove
02463 };
02464