85 val = (5 * bin) + 4800;
87 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
205 ah->ah_antenna[mode][0] =
243 ee->
ee_ob[mode][3] = (
val >> 5) & 0x7;
244 ee->
ee_db[mode][3] = (
val >> 2) & 0x7;
245 ee->
ee_ob[mode][2] = (
val << 1) & 0x7;
248 ee->
ee_ob[mode][2] |= (
val >> 15) & 0x1;
249 ee->
ee_db[mode][2] = (
val >> 12) & 0x7;
250 ee->
ee_ob[mode][1] = (
val >> 9) & 0x7;
251 ee->
ee_db[mode][1] = (
val >> 6) & 0x7;
252 ee->
ee_ob[mode][0] = (
val >> 3) & 0x7;
257 ee->
ee_ob[mode][1] = (
val >> 4) & 0x7;
276 if ((
val & 0xff) & 0x80)
301 ee->
ee_db[mode][0] = (
val >> 3) & 0x7;
482 offset = mode_offset[mode];
532 freq2 = (
val >> 8) & 0xff;
565 pcal[0].
freq = (
val >> 9) & mask;
566 pcal[1].
freq = (
val >> 2) & mask;
567 pcal[2].
freq = (
val << 5) & mask;
570 pcal[2].
freq |= (
val >> 11) & 0x1f;
571 pcal[3].
freq = (
val >> 4) & mask;
572 pcal[4].
freq = (
val << 3) & mask;
575 pcal[4].
freq |= (
val >> 13) & 0x7;
576 pcal[5].
freq = (
val >> 6) & mask;
577 pcal[6].
freq = (
val << 1) & mask;
580 pcal[6].
freq |= (
val >> 15) & 0x1;
581 pcal[7].
freq = (
val >> 8) & mask;
582 pcal[8].
freq = (
val >> 1) & mask;
583 pcal[9].
freq = (
val << 6) & mask;
586 pcal[9].
freq |= (
val >> 10) & 0x3f;
648 static const u16 intercepts3[] =
649 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
650 static const u16 intercepts3_2[] =
651 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
677 for (pier = 0; pier < ee->
ee_n_piers[mode]; pier++) {
686 if (!chinfo[pier].pd_curves)
695 if (!((ee->
ee_x_gain[mode] >> idx) & 0x1)) {
719 for (point = 0; point < pd->
pd_points; point++) {
722 pd->
pd_pwr[point] = 2 * pcinfo->
pwr[point];
802 cdata->
pwr[0] |= ((
val >> 14) & 0x3);
808 cdata->
pwr[3] |= ((
val >> 12) & 0xf);
818 cdata->
pwr[8] |= ((
val >> 14) & 0x3);
854 unsigned int pier, pdg, point;
857 for (pier = 0; pier < ee->
ee_n_piers[mode]; pier++) {
866 if (!chinfo[pier].pd_curves)
870 for (pdg = 0; pdg < ee->
ee_pd_gains[mode]; pdg++) {
872 u8 idx = pdgain_idx[pdg];
914 }
else if (pdg == 1) {
974 pdgain_idx[pd_gains++] = i;
978 if (pd_gains == 0 || pd_gains > 2)
1023 chan_pcal_info->
pwr_x0[++
c] = (
s8) ((
val >> 8) & 0xff);
1031 chan_pcal_info->
pcdac_x0[2] = ((
val >> 5) & 0x1f);
1032 chan_pcal_info->
pcdac_x0[3] = ((
val >> 10) & 0x1f);
1039 chan_pcal_info->
pwr_x3[1] = (
s8) ((
val >> 8) & 0xff);
1042 chan_pcal_info->
pwr_x3[2] = (
val & 0xff);
1052 chan_pcal_info->
pcdac_x0[0] = ((
val >> 8) & 0x3f);
1089 static inline unsigned int 1092 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1139 unsigned int pier, point;
1143 for (pier = 0; pier < ee->
ee_n_piers[mode]; pier++) {
1152 if (!chinfo[pier].pd_curves)
1156 for (pdg = 0; pdg < ee->
ee_pd_gains[mode]; pdg++) {
1158 u8 idx = pdgain_idx[pdg];
1186 for (point = 1; point < pd->
pd_points; point++) {
1189 2 * pcinfo->
pwr[pdg][point - 1];
1192 pcinfo->
pddac[pdg][point - 1];
1231 pdgain_idx[pd_gains++] = idx;
1279 pcinfo->
pwr[0][0] = (
val >> 12) & 0xf;
1283 pcinfo->
pwr[0][1] = (
val >> 6) & 0xf;
1284 pcinfo->
pddac[0][1] = (
val >> 10) & 0x3f;
1287 pcinfo->
pwr[0][2] =
val & 0xf;
1288 pcinfo->
pddac[0][2] = (
val >> 4) & 0x3f;
1290 pcinfo->
pwr[0][3] = 0;
1291 pcinfo->
pddac[0][3] = 0;
1299 pcinfo->
pwr_i[1] = (
val >> 10) & 0x1f;
1305 pcinfo->
pwr[1][0] = (
val >> 6) & 0xf;
1306 pcinfo->
pddac[1][0] = (
val >> 10) & 0x3f;
1309 pcinfo->
pwr[1][1] =
val & 0xf;
1310 pcinfo->
pddac[1][1] = (
val >> 4) & 0x3f;
1311 pcinfo->
pwr[1][2] = (
val >> 10) & 0xf;
1313 pcinfo->
pddac[1][2] = (
val >> 14) & 0x3;
1315 pcinfo->
pddac[1][2] |= (
val & 0xF) << 2;
1317 pcinfo->
pwr[1][3] = 0;
1318 pcinfo->
pddac[1][3] = 0;
1319 }
else if (pd_gains == 1) {
1324 pcinfo->
pwr[0][3] = (
val >> 10) & 0xf;
1326 pcinfo->
pddac[0][3] = (
val >> 14) & 0x3;
1328 pcinfo->
pddac[0][3] |= (
val & 0xF) << 2;
1336 pcinfo->
pwr_i[2] = (
val >> 4) & 0x1f;
1340 pcinfo->
pwr[2][0] = (
val >> 0) & 0xf;
1341 pcinfo->
pddac[2][0] = (
val >> 4) & 0x3f;
1342 pcinfo->
pwr[2][1] = (
val >> 10) & 0xf;
1344 pcinfo->
pddac[2][1] = (
val >> 14) & 0x3;
1346 pcinfo->
pddac[2][1] |= (
val & 0xF) << 2;
1348 pcinfo->
pwr[2][2] = (
val >> 4) & 0xf;
1349 pcinfo->
pddac[2][2] = (
val >> 8) & 0x3f;
1351 pcinfo->
pwr[2][3] = 0;
1352 pcinfo->
pddac[2][3] = 0;
1353 }
else if (pd_gains == 2) {
1354 pcinfo->
pwr[1][3] = (
val >> 4) & 0xf;
1355 pcinfo->
pddac[1][3] = (
val >> 8) & 0x3f;
1359 pcinfo->
pwr_i[3] = (
val >> 14) & 0x3;
1361 pcinfo->
pwr_i[3] |= ((
val >> 0) & 0x7) << 2;
1364 pcinfo->
pwr[3][0] = (
val >> 10) & 0xf;
1365 pcinfo->
pddac[3][0] = (
val >> 14) & 0x3;
1368 pcinfo->
pddac[3][0] |= (
val & 0xF) << 2;
1369 pcinfo->
pwr[3][1] = (
val >> 4) & 0xf;
1370 pcinfo->
pddac[3][1] = (
val >> 8) & 0x3f;
1372 pcinfo->
pwr[3][2] = (
val >> 14) & 0x3;
1374 pcinfo->
pwr[3][2] |= ((
val >> 0) & 0x3) << 2;
1376 pcinfo->
pddac[3][2] = (
val >> 2) & 0x3f;
1377 pcinfo->
pwr[3][3] = (
val >> 8) & 0xf;
1379 pcinfo->
pddac[3][3] = (
val >> 12) & 0xF;
1381 pcinfo->
pddac[3][3] |= ((
val >> 0) & 0x3) << 4;
1382 }
else if (pd_gains == 3) {
1383 pcinfo->
pwr[2][3] = (
val >> 14) & 0x3;
1385 pcinfo->
pwr[2][3] |= ((
val >> 0) & 0x3) << 2;
1387 pcinfo->
pddac[2][3] = (
val >> 2) & 0x3f;
1407 u8 *rate_target_pwr_num;
1436 for (i = 0; i < (*rate_target_pwr_num); i++) {
1438 rate_pcal_info[i].
freq =
1448 (*rate_target_pwr_num) = i;
1457 for (i = 0; i < (*rate_target_pwr_num); i++) {
1459 rate_pcal_info[i].
freq =
1469 (*rate_target_pwr_num) = i;
1500 int (*read_pcal)(
struct ath5k_hw *
hw,
int mode);
1516 err = read_pcal(
ah, mode);
1555 for (pier = 0; pier < ee->
ee_n_piers[mode]; pier++) {
1559 for (pdg = 0; pdg < ee->
ee_pd_gains[mode]; pdg++) {
1569 free(chinfo[pier].pd_curves);
1590 unsigned int fmask, pmask;
1591 unsigned int ctl_mode;
1600 for (i = 0; i < ee->
ee_ctls; i += 2) {
1614 for(i = 0; i < ee->
ee_ctls; i++) {
1624 if (ee->
ee_ctl[i] == 0) {
1635 rep[j].
freq = (
val >> 8) & fmask;
1636 rep[j + 1].
freq =
val & fmask;
1640 rep[j].
edge = (
val >> 8) & pmask;
1641 rep[j].
flag = (
val >> 14) & 1;
1642 rep[j + 1].
edge =
val & pmask;
1643 rep[j + 1].
flag = (
val >> 6) & 1;
1647 rep[0].
freq = (
val >> 9) & fmask;
1648 rep[1].
freq = (
val >> 2) & fmask;
1649 rep[2].
freq = (
val << 5) & fmask;
1652 rep[2].
freq |= (
val >> 11) & 0x1f;
1653 rep[3].
freq = (
val >> 4) & fmask;
1654 rep[4].
freq = (
val << 3) & fmask;
1657 rep[4].
freq |= (
val >> 13) & 0x7;
1658 rep[5].
freq = (
val >> 6) & fmask;
1659 rep[6].
freq = (
val << 1) & fmask;
1662 rep[6].
freq |= (
val >> 15) & 0x1;
1663 rep[7].
freq = (
val >> 8) & fmask;
1665 rep[0].
edge = (
val >> 2) & pmask;
1666 rep[1].
edge = (
val << 4) & pmask;
1669 rep[1].
edge |= (
val >> 12) & 0xf;
1670 rep[2].
edge = (
val >> 6) & pmask;
1674 rep[4].
edge = (
val >> 10) & pmask;
1675 rep[5].
edge = (
val >> 4) & pmask;
1676 rep[6].
edge = (
val << 2) & pmask;
1679 rep[6].
edge |= (
val >> 14) & 0x3;
1680 rep[7].
edge = (
val >> 8) & pmask;
1684 rep[j].
freq, ctl_mode);
1740 mac_d[octet + 1] =
data & 0xff;
1741 mac_d[octet] =
data >> 8;
1745 if (!total || total == 3 * 0xffff)
u16 ee_xr_power[AR5K_EEPROM_N_MODES]
#define EINVAL
Invalid argument.
u8 ee_pd_gains[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_HDR_11B(_v)
static int ath5k_eeprom_read_turbo_modes(struct ath5k_hw *ah, u32 *offset, unsigned int mode)
static __always_inline void off_t int c
#define AR5K_EEPROM_N_5GHZ_CHAN
#define AR5K_EEPROM_MISC5
#define AR5K_EEPROM_GROUP4_OFFSET
#define AR5K_EEPROM_VERSION_4_2
#define AR5K_EEPROM_IS_HB63
struct ath5k_pdgain_info * pd_curves
#define AR5K_EEPROM_MODE_11G
u16 ee_thr_62[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_N_PD_CURVES
s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES]
u8 ee_ctl[AR5K_EEPROM_MAX_CTLS]
#define AR5K_EEPROM_MODE_11A
#define AR5K_EEPROM_CAL_DATA_START(_v)
u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS]
#define AR5K_EEPROM_TARGET_PWRSTART(_v)
s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS]
#define AR5K_EEPROM_N_2GHZ_CHAN
#define AR5K_EEPROM_POWER_M
#define AR5K_EEPROM_N_XPD3_POINTS
u16 ee_false_detect[AR5K_EEPROM_N_MODES]
static int ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
#define AR5K_EEPROM_PROTECT
u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES]
u16 ee_x_gain[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_OBDB1_2GHZ
#define AR5K_REG_MS(_val, _flags)
uint8_t mac[ETH_ALEN]
MAC address.
#define AR5K_EEPROM_N_PWR_POINTS_5111
#define AR5K_EEPROM_CMD_READ
s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES]
u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111]
#define AR5K_EEPROM_MISC6
static unsigned int ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES]
ath5k_hw_get_isr - Get interrupt status
static unsigned int ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC]
#define AR5K_EEPROM_STAT_RDDONE
#define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)
u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]
s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS]
static int ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode, struct ath5k_chan_pcal_info *chinfo)
struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
#define ENOMEM
Not enough space.
void * memcpy(void *dest, const void *src, size_t len) __nonnull
s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_MAGIC
#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)
static int ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
#define AR5K_EEPROM_GROUP5_OFFSET
static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
struct ath5k_chan_pcal_info_rf5111 rf5111_info
struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
static int ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
static int ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
#define AR5K_EEPROM_GROUP1_OFFSET
static int ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode, struct ath5k_chan_pcal_info *chinfo)
#define AR5K_EEPROM_REG_DOMAIN
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
#define AR5K_EEPROM_VERSION_3_3
static void *__malloc calloc(size_t nmemb, size_t size)
Allocate cleared memory.
#define AR5K_EEPROM_CTL(_v)
int ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
#define AR5K_EEPROM_ANT_GAIN(_v)
s8 pwr[AR5K_EEPROM_N_PD_GAINS][AR5K_EEPROM_N_PD_POINTS]
#define AR5K_EEPROM_RFKILL_GPIO_SEL
#define AR5K_EEPROM_HDR_11A(_v)
#define AR5K_EEPROM_MISC4
#define AR5K_EEPROM_GROUPS_START(_v)
#define AR5K_EEPROM_N_CTLS(_v)
#define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)
static int ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max, struct ath5k_chan_pcal_info *pc, unsigned int mode)
u16 ee_xlna_gain[AR5K_EEPROM_N_MODES]
u8 ee_n_piers[AR5K_EEPROM_N_MODES]
int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
#define AR5K_EEPROM_VERSION_5_0
#define AR5K_TUNE_REGISTER_TIMEOUT
#define AR5K_EEPROM_VERSION_4_3
static void(* free)(struct refcnt *refcnt))
u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES]
void ath5k_eeprom_detach(struct ath5k_hw *ah)
#define AR5K_EEPROM_EEMAP(_v)
int ath5k_eeprom_init(struct ath5k_hw *ah)
u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES]
static int ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
#define AR5K_EEPROM_N_PD_POINTS
#define AR5K_EEPROM_MODES_11G(_v)
#define AR5K_EEPROM_STATUS
#define AR5K_EEPROM_VERSION_4_1
#define AR5K_EEPROM_N_EDGES
IP4_t ip
Destination IP address.
#define AR5K_EEPROM_MODE_11B
static void ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
u16 ee_i_gain[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_STAT_RDERR
#define AR5K_EEPROM_GROUP8_OFFSET
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
u8 pddac_i[AR5K_EEPROM_N_PD_GAINS]
#define AR5K_EEPROM_MODES_11B(_v)
static int ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS]
static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, unsigned int mode)
#define AR5K_EEPROM_CHANNEL_DIS
u16 ee_i_cal[AR5K_EEPROM_N_MODES]
u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES]
s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES]
static struct corkscrew_private * vp
struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN]
struct ath5k_chan_pcal_info_rf5112 rf5112_info
u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES]
u16 ee_xpd[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_PCDAC_M
#define AR5K_EEPROM_MISC3
struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN]
static int ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, unsigned int mode)
#define AR5K_EEPROM_VERSION_3_2
#define AR5K_EEPROM_VERSION
#define AR5K_EEPROM_MISC2
#define AR5K_EEPROM_N_XPD0_POINTS
#define AR5K_EEPROM_MISC1
u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS]
u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES]
u16 ee_cck_ofdm_power_delta
#define AR5K_EEPROM_OBDB0_2GHZ
#define EIO
Input/output error.
static int ath5k_eeprom_init_header(struct ath5k_hw *ah)
struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
#define AR5K_EEPROM_N_2GHZ_CHAN_2413
#define AR5K_EEPROM_GROUP2_OFFSET
u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES]
u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES]
uint8_t data[48]
Additional event data.
#define AR5K_EEPROM_RFKILL
uint16_t offset
Offset to command line.
#define AR5K_EEPROM_VERSION_4_6
u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]
u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111]
s8 pwr_i[AR5K_EEPROM_N_PD_GAINS]
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
struct ath5k_chan_pcal_info_rf2413 rf2413_info
#define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)
#define AR5K_EEPROM_GROUP3_OFFSET
struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES *AR5K_EEPROM_MAX_CTLS]
static int ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
#define AR5K_EEPROM_VERSION_3_0
#define AR5K_EEPROM_MODES_11A(_v)
static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin, unsigned int mode)
static int ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_READ(_o, _v)
#define AR5K_EEPROM_MISC0
#define AR5K_EEPROM_FREQ_M(_v)
u16 ee_cck_ofdm_gain_delta
u8 pddac[AR5K_EEPROM_N_PD_GAINS][AR5K_EEPROM_N_PD_POINTS]
#define NULL
NULL pointer (VOID *)
u16 ee_switch_settling[AR5K_EEPROM_N_MODES]
#define ETIMEDOUT
Connection timed out.
u16 ee_fixed_bias[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_HDR_11G(_v)
#define AR5K_EEPROM_RFKILL_POLARITY
static int ath5k_eeprom_init_modes(struct ath5k_hw *ah)
struct bofm_section_header done
#define AR5K_EEPROM_CCK_OFDM_DELTA
u16 ee_q_cal[AR5K_EEPROM_N_MODES]
#define AR5K_EEPROM_READ_HDR(_o, _v)
s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES]
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
#define AR5K_EEPROM_I_GAIN
#define AR5K_EEPROM_VERSION_3_4
static int ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode, struct ath5k_chan_pcal_info *chinfo)
#define AR5K_EEPROM_VERSION_4_0