iPXE
ath9k_ar9003_hw.c
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include "hw.h"
21 #include "ar9003_mac.h"
22 #include "ar9003_2p2_initvals.h"
23 #include "ar9485_initvals.h"
24 #include "ar9340_initvals.h"
25 
26 /* General hardware code for the AR9003 hadware family */
27 
28 /*
29  * The AR9003 family uses a new INI format (pre, core, post
30  * arrays per subsystem). This provides support for the
31  * AR9003 2.2 chipsets.
32  */
33 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
34 {
35  if (AR_SREV_9340(ah)) {
36  /* mac */
37  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
38  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
41  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
44 
45  /* bb */
46  INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
53 
54  /* radio */
55  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
56  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
59  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
62 
63  /* soc */
64  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
67  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
68  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
71 
72  /* rx/tx gain */
73  INIT_INI_ARRAY(&ah->iniModesRxGain,
76  5);
77  INIT_INI_ARRAY(&ah->iniModesTxGain,
80  5);
81 
82  INIT_INI_ARRAY(&ah->iniModesAdditional,
85  3);
86 
87  INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
90  2);
91  } else if (AR_SREV_9485_11(ah)) {
92  /* mac */
93  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
94  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
97  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
100 
101  /* bb */
103  ARRAY_SIZE(ar9485_1_1), 2);
104  INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
107  INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
110 
111  /* radio */
112  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
113  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
116  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
119 
120  /* soc */
121  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
124  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
125  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
126 
127  /* rx/tx gain */
128  INIT_INI_ARRAY(&ah->iniModesRxGain,
131  INIT_INI_ARRAY(&ah->iniModesTxGain,
134  5);
135 
136  /* Load PCIE SERDES settings from INI */
137 
138  /* Awake Setting */
139 
140  INIT_INI_ARRAY(&ah->iniPcieSerdes,
143  2);
144 
145  /* Sleep Setting */
146 
147  INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
150  2);
151  } else {
152  /* mac */
153  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
154  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
157  INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
160 
161  /* bb */
162  INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
163  INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
166  INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
169 
170  /* radio */
171  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
172  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
175  INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
178 
179  /* soc */
180  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
183  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
184  INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
187 
188  /* rx/tx gain */
189  INIT_INI_ARRAY(&ah->iniModesRxGain,
192  INIT_INI_ARRAY(&ah->iniModesTxGain,
195  5);
196 
197  /* Load PCIE SERDES settings from INI */
198 
199  /* Awake Setting */
200 
201  INIT_INI_ARRAY(&ah->iniPcieSerdes,
204  2);
205 
206  /* Sleep Setting */
207 
208  INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
211  2);
212 
213  /* Fast clock modal settings */
214  INIT_INI_ARRAY(&ah->iniModesAdditional,
217  3);
218  }
219 }
220 
222 {
223  switch (ar9003_hw_get_tx_gain_idx(ah)) {
224  case 0:
225  default:
226  if (AR_SREV_9340(ah))
227  INIT_INI_ARRAY(&ah->iniModesTxGain,
230  5);
231  else if (AR_SREV_9485_11(ah))
232  INIT_INI_ARRAY(&ah->iniModesTxGain,
235  5);
236  else
237  INIT_INI_ARRAY(&ah->iniModesTxGain,
240  5);
241  break;
242  case 1:
243  if (AR_SREV_9340(ah))
244  INIT_INI_ARRAY(&ah->iniModesTxGain,
247  5);
248  else if (AR_SREV_9485_11(ah))
249  INIT_INI_ARRAY(&ah->iniModesTxGain,
252  5);
253  else
254  INIT_INI_ARRAY(&ah->iniModesTxGain,
257  5);
258  break;
259  case 2:
260  if (AR_SREV_9340(ah))
261  INIT_INI_ARRAY(&ah->iniModesTxGain,
264  5);
265  else if (AR_SREV_9485_11(ah))
266  INIT_INI_ARRAY(&ah->iniModesTxGain,
269  5);
270  else
271  INIT_INI_ARRAY(&ah->iniModesTxGain,
274  5);
275  break;
276  case 3:
277  if (AR_SREV_9340(ah))
278  INIT_INI_ARRAY(&ah->iniModesTxGain,
281  5);
282  else if (AR_SREV_9485_11(ah))
283  INIT_INI_ARRAY(&ah->iniModesTxGain,
286  5);
287  else
288  INIT_INI_ARRAY(&ah->iniModesTxGain,
291  5);
292  break;
293  }
294 }
295 
297 {
298  switch (ar9003_hw_get_rx_gain_idx(ah)) {
299  case 0:
300  default:
301  if (AR_SREV_9340(ah))
302  INIT_INI_ARRAY(&ah->iniModesRxGain,
305  2);
306  else if (AR_SREV_9485_11(ah))
307  INIT_INI_ARRAY(&ah->iniModesRxGain,
310  2);
311  else
312  INIT_INI_ARRAY(&ah->iniModesRxGain,
315  2);
316  break;
317  case 1:
318  if (AR_SREV_9340(ah))
319  INIT_INI_ARRAY(&ah->iniModesRxGain,
322  2);
323  else if (AR_SREV_9485_11(ah))
324  INIT_INI_ARRAY(&ah->iniModesRxGain,
327  2);
328  else
329  INIT_INI_ARRAY(&ah->iniModesRxGain,
332  2);
333  break;
334  }
335 }
336 
337 /* set gain table pointers according to values read from the eeprom */
339 {
342 }
343 
344 /*
345  * Helper for ASPM support.
346  *
347  * Disable PLL when in L0s as well as receiver clock when in L1.
348  * This power saving option must be enabled through the SerDes.
349  *
350  * Programming the SerDes must go through the same 288 bit serial shift
351  * register as the other analog registers. Hence the 9 writes.
352  */
354  int restore,
355  int power_off)
356 {
357  if (ah->is_pciexpress != 1)
358  return;
359 
360  /* Do not touch SerDes registers */
361  if (ah->config.pcie_powersave_enable == 2)
362  return;
363 
364  /* Nothing to do on restore for 11N */
365  if (!restore) {
366  /* set bit 19 to allow forcing of pcie core into L1 state */
368 
369  /* Several PCIe massages to ensure proper behaviour */
370  if (ah->config.pcie_waen)
371  REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
372  else
373  REG_WRITE(ah, AR_WA, ah->WARegVal);
374  }
375 
376  /*
377  * Configire PCIE after Ini init. SERDES values now come from ini file
378  * This enables PCIe low power mode.
379  */
380  if (ah->config.pcieSerDesWrite) {
381  unsigned int i;
382  struct ar5416IniArray *array;
383 
384  array = power_off ? &ah->iniPcieSerdes :
385  &ah->iniPcieSerdesLowPower;
386 
387  for (i = 0; i < array->ia_rows; i++) {
388  REG_WRITE(ah,
389  INI_RA(array, i, 0),
390  INI_RA(array, i, 1));
391  }
392  }
393 }
394 
395 /* Sets up the AR9003 hardware familiy callbacks */
397 {
398  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
399  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
400 
403 
405 
409 }
static __unused const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2]
static __unused const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5]
static __unused const u32 ar9340_1p0_mac_postamble[][5]
Definition: hw.h:656
static __unused const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5]
static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
static __unused const u32 ar9300_2p2_mac_postamble[][5]
static __unused const u32 ar9340_1p0_soc_postamble[][5]
static __unused const u32 ar9340_1p0_radio_core[][2]
static __unused const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5]
#define INI_RA(iniarray, row, column)
Definition: calib.h:45
void ar9003_hw_attach_ops(struct ath_hw *ah)
static void ar9003_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
static __unused const u32 ar9300_2p2_radio_core[][2]
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
static __unused const u32 ar9300_2p2_radio_postamble[][5]
static __unused const u32 ar9300_2p2_baseband_core[][2]
static __unused const u32 ar9300_2p2_soc_preamble[][2]
static __unused const u32 ar9300_2p2_soc_postamble[][5]
static __unused const u32 ar9485_1_1_baseband_core[][2]
static __unused const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5]
static __unused const u32 ar9485_1_1_radio_postamble[][2]
uint32_t array
Array number.
Definition: edd.h:30
static __unused const u32 ar9340Common_rx_gain_table_1p0[][2]
static __unused const u32 ar9485_1_1_radio_core[][2]
static __unused const u32 ar9340Modes_fast_clock_1p0[][3]
static __unused const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5]
static __unused const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2]
static __unused const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2]
static __unused const u32 ar9300_2p2_mac_core[][2]
#define AR_SREV_9485_11(_ah)
Definition: reg.h:872
#define AR_SREV_9340(_ah)
Definition: reg.h:878
static __unused const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2]
static __unused const u32 ar9300Common_wo_xlna_rx_gain_table_2p2[][2]
static __unused const u32 ar9300_2p2_baseband_postamble[][5]
void(* init_mode_regs)(struct ath_hw *ah)
Definition: hw.h:555
#define AR_PCIE_PM_CTRL
Definition: reg.h:983
static __unused const u32 ar9485_1_1_mac_postamble[][5]
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
static __unused const u32 ar9485_1_1_soc_preamble[][2]
static __unused const u32 ar9485_1_1_baseband_postamble[][5]
static __unused const u32 ar9300Common_rx_gain_table_2p2[][2]
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
void(* config_pci_powersave)(struct ath_hw *ah, int restore, int power_off)
Definition: hw.h:604
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition: hw.h:556
void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
static __unused const u32 ar9340_1p0_soc_preamble[][2]
static __unused const u32 ar9340_1p0_radio_postamble[][5]
static __unused const u32 ar9340_1p0_baseband_postamble[][5]
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
static __unused const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5]
static __unused const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5]
#define INIT_INI_ARRAY(iniarray, array, rows, columns)
Definition: calib.h:39
void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
static __unused const u32 ar9340_1p0_mac_core[][2]
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
static __unused const u32 ar9300Modes_fast_clock_2p2[][3]
static __unused const u32 ar9485_1_1[][2]
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
static __unused const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5]
static __unused const u32 ar9340_1p0_radio_core_40M[][2]
static __unused const u32 ar9485_1_1_mac_core[][2]
#define AR_PCIE_PM_CTRL_ENA
Definition: reg.h:984
static __unused const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5]
static __unused const u32 ar9485Modes_high_power_tx_gain_1_1[][5]
#define AR_WA
Definition: reg.h:698
uint8_t ah
Definition: registers.h:85
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
static __unused const u32 ar9340_1p0_baseband_core[][2]
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)