iPXE
Functions
ath9k_ar9003_hw.c File Reference
#include "hw.h"
#include "ar9003_mac.h"
#include "ar9003_2p2_initvals.h"
#include "ar9485_initvals.h"
#include "ar9340_initvals.h"

Go to the source code of this file.

Functions

 FILE_SECBOOT (FORBIDDEN)
static void ar9003_hw_init_mode_regs (struct ath_hw *ah)
static void ar9003_tx_gain_table_apply (struct ath_hw *ah)
static void ar9003_rx_gain_table_apply (struct ath_hw *ah)
static void ar9003_hw_init_mode_gain_regs (struct ath_hw *ah)
static void ar9003_hw_configpcipowersave (struct ath_hw *ah, int restore, int power_off)
void ar9003_hw_attach_ops (struct ath_hw *ah)

Function Documentation

◆ FILE_SECBOOT()

FILE_SECBOOT ( FORBIDDEN )

◆ ar9003_hw_init_mode_regs()

void ar9003_hw_init_mode_regs ( struct ath_hw * ah)
static

Definition at line 35 of file ath9k_ar9003_hw.c.

36{
37 if (AR_SREV_9340(ah)) {
38 /* mac */
39 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
41 ar9340_1p0_mac_core,
42 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
44 ar9340_1p0_mac_postamble,
45 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
46
47 /* bb */
48 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
50 ar9340_1p0_baseband_core,
51 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
53 ar9340_1p0_baseband_postamble,
54 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
55
56 /* radio */
57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
59 ar9340_1p0_radio_core,
60 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
61 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
62 ar9340_1p0_radio_postamble,
63 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
64
65 /* soc */
66 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
67 ar9340_1p0_soc_preamble,
68 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
69 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
70 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
71 ar9340_1p0_soc_postamble,
72 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
73
74 /* rx/tx gain */
75 INIT_INI_ARRAY(&ah->iniModesRxGain,
76 ar9340Common_wo_xlna_rx_gain_table_1p0,
77 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
78 5);
79 INIT_INI_ARRAY(&ah->iniModesTxGain,
80 ar9340Modes_high_ob_db_tx_gain_table_1p0,
81 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
82 5);
83
84 INIT_INI_ARRAY(&ah->iniModesAdditional,
85 ar9340Modes_fast_clock_1p0,
86 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
87 3);
88
89 INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
90 ar9340_1p0_radio_core_40M,
91 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
92 2);
93 } else if (AR_SREV_9485_11(ah)) {
94 /* mac */
95 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
96 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
97 ar9485_1_1_mac_core,
98 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
99 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
100 ar9485_1_1_mac_postamble,
101 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
102
103 /* bb */
104 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
105 ARRAY_SIZE(ar9485_1_1), 2);
106 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
107 ar9485_1_1_baseband_core,
108 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
110 ar9485_1_1_baseband_postamble,
111 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
112
113 /* radio */
114 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
115 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
116 ar9485_1_1_radio_core,
117 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
119 ar9485_1_1_radio_postamble,
120 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
121
122 /* soc */
123 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
124 ar9485_1_1_soc_preamble,
125 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
126 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
127 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
128
129 /* rx/tx gain */
130 INIT_INI_ARRAY(&ah->iniModesRxGain,
131 ar9485Common_wo_xlna_rx_gain_1_1,
132 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
133 INIT_INI_ARRAY(&ah->iniModesTxGain,
134 ar9485_modes_lowest_ob_db_tx_gain_1_1,
135 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
136 5);
137
138 /* Load PCIE SERDES settings from INI */
139
140 /* Awake Setting */
141
142 INIT_INI_ARRAY(&ah->iniPcieSerdes,
143 ar9485_1_1_pcie_phy_clkreq_disable_L1,
144 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
145 2);
146
147 /* Sleep Setting */
148
149 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
150 ar9485_1_1_pcie_phy_clkreq_disable_L1,
151 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
152 2);
153 } else {
154 /* mac */
155 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
156 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
157 ar9300_2p2_mac_core,
158 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
159 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
160 ar9300_2p2_mac_postamble,
161 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
162
163 /* bb */
164 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
166 ar9300_2p2_baseband_core,
167 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
168 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
169 ar9300_2p2_baseband_postamble,
170 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
171
172 /* radio */
173 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
174 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
175 ar9300_2p2_radio_core,
176 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
177 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
178 ar9300_2p2_radio_postamble,
179 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
180
181 /* soc */
182 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
183 ar9300_2p2_soc_preamble,
184 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
185 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
186 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
187 ar9300_2p2_soc_postamble,
188 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
189
190 /* rx/tx gain */
191 INIT_INI_ARRAY(&ah->iniModesRxGain,
192 ar9300Common_rx_gain_table_2p2,
193 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
194 INIT_INI_ARRAY(&ah->iniModesTxGain,
195 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
196 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
197 5);
198
199 /* Load PCIE SERDES settings from INI */
200
201 /* Awake Setting */
202
203 INIT_INI_ARRAY(&ah->iniPcieSerdes,
204 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
205 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
206 2);
207
208 /* Sleep Setting */
209
210 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
211 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
212 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
213 2);
214
215 /* Fast clock modal settings */
216 INIT_INI_ARRAY(&ah->iniModesAdditional,
217 ar9300Modes_fast_clock_2p2,
218 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
219 3);
220 }
221}
NULL
#define NULL
NULL pointer (VOID *)
Definition Base.h:322
ar9300Common_rx_gain_table_2p2
static __unused const u32 ar9300Common_rx_gain_table_2p2[][2]
Definition ar9003_2p2_initvals.h:1050
ar9300_2p2_radio_core
static __unused const u32 ar9300_2p2_radio_core[][2]
Definition ar9003_2p2_initvals.h:156
ar9300_2p2_soc_postamble
static __unused const u32 ar9300_2p2_soc_postamble[][5]
Definition ar9003_2p2_initvals.h:572
ar9300_2p2_radio_postamble
static __unused const u32 ar9300_2p2_radio_postamble[][5]
Definition ar9003_2p2_initvals.h:24
ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
static __unused const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2]
Definition ar9003_2p2_initvals.h:1845
ar9300_2p2_soc_preamble
static __unused const u32 ar9300_2p2_soc_preamble[][2]
Definition ar9003_2p2_initvals.h:1835
ar9300_2p2_baseband_postamble
static __unused const u32 ar9300_2p2_baseband_postamble[][5]
Definition ar9003_2p2_initvals.h:619
ar9300_2p2_mac_postamble
static __unused const u32 ar9300_2p2_mac_postamble[][5]
Definition ar9003_2p2_initvals.h:560
ar9300_2p2_baseband_core
static __unused const u32 ar9300_2p2_baseband_core[][2]
Definition ar9003_2p2_initvals.h:675
ar9300_2p2_mac_core
static __unused const u32 ar9300_2p2_mac_core[][2]
Definition ar9003_2p2_initvals.h:1416
ar9300Modes_lowest_ob_db_tx_gain_table_2p2
static __unused const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5]
Definition ar9003_2p2_initvals.h:37
ar9300Modes_fast_clock_2p2
static __unused const u32 ar9300Modes_fast_clock_2p2[][3]
Definition ar9003_2p2_initvals.h:143
ar9340_1p0_baseband_core
static __unused const u32 ar9340_1p0_baseband_core[][2]
Definition ar9340_initvals.h:293
ar9340_1p0_radio_core_40M
static __unused const u32 ar9340_1p0_radio_core_40M[][2]
Definition ar9340_initvals.h:223
ar9340_1p0_mac_postamble
static __unused const u32 ar9340_1p0_mac_postamble[][5]
Definition ar9340_initvals.h:229
ar9340_1p0_radio_postamble
static __unused const u32 ar9340_1p0_radio_postamble[][5]
Definition ar9340_initvals.h:22
ar9340Modes_fast_clock_1p0
static __unused const u32 ar9340Modes_fast_clock_1p0[][3]
Definition ar9340_initvals.h:104
ar9340Common_wo_xlna_rx_gain_table_1p0
static __unused const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2]
Definition ar9340_initvals.h:1258
ar9340_1p0_mac_core
static __unused const u32 ar9340_1p0_mac_core[][2]
Definition ar9340_initvals.h:1094
ar9340_1p0_radio_core
static __unused const u32 ar9340_1p0_radio_core[][2]
Definition ar9340_initvals.h:117
ar9340_1p0_soc_postamble
static __unused const u32 ar9340_1p0_soc_postamble[][5]
Definition ar9340_initvals.h:241
ar9340Modes_high_ob_db_tx_gain_table_1p0
static __unused const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5]
Definition ar9340_initvals.h:542
ar9340_1p0_soc_preamble
static __unused const u32 ar9340_1p0_soc_preamble[][2]
Definition ar9340_initvals.h:1518
ar9340_1p0_baseband_postamble
static __unused const u32 ar9340_1p0_baseband_postamble[][5]
Definition ar9340_initvals.h:246
ar9485_1_1_pcie_phy_clkreq_disable_L1
static __unused const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2]
Definition ar9485_initvals.h:779
ar9485_1_1_radio_core
static __unused const u32 ar9485_1_1_radio_core[][2]
Definition ar9485_initvals.h:541
ar9485_modes_lowest_ob_db_tx_gain_1_1
static __unused const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5]
Definition ar9485_initvals.h:447
ar9485_1_1
static __unused const u32 ar9485_1_1[][2]
Definition ar9485_initvals.h:686
ar9485_1_1_mac_core
static __unused const u32 ar9485_1_1_mac_core[][2]
Definition ar9485_initvals.h:22
ar9485_1_1_radio_postamble
static __unused const u32 ar9485_1_1_radio_postamble[][2]
Definition ar9485_initvals.h:520
ar9485Common_wo_xlna_rx_gain_1_1
static __unused const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2]
Definition ar9485_initvals.h:1031
ar9485_1_1_soc_preamble
static __unused const u32 ar9485_1_1_soc_preamble[][2]
Definition ar9485_initvals.h:786
ar9485_1_1_baseband_postamble
static __unused const u32 ar9485_1_1_baseband_postamble[][5]
Definition ar9485_initvals.h:329
ar9485_1_1_baseband_core
static __unused const u32 ar9485_1_1_baseband_core[][2]
Definition ar9485_initvals.h:184
ar9485_1_1_mac_postamble
static __unused const u32 ar9485_1_1_mac_postamble[][5]
Definition ar9485_initvals.h:529
AR_SREV_9485_11
#define AR_SREV_9485_11(_ah)
Definition reg.h:873
AR_SREV_9340
#define AR_SREV_9340(_ah)
Definition reg.h:879
INIT_INI_ARRAY
#define INIT_INI_ARRAY(iniarray, array, rows, columns)
Definition calib.h:40
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition efx_common.h:43
ATH_INI_PRE
@ ATH_INI_PRE
Definition hw.h:175
ATH_INI_POST
@ ATH_INI_POST
Definition hw.h:177
ATH_INI_CORE
@ ATH_INI_CORE
Definition hw.h:176
ah
uint8_t ah
Definition registers.h:1

References ah, ar9300_2p2_baseband_core, ar9300_2p2_baseband_postamble, ar9300_2p2_mac_core, ar9300_2p2_mac_postamble, ar9300_2p2_radio_core, ar9300_2p2_radio_postamble, ar9300_2p2_soc_postamble, ar9300_2p2_soc_preamble, ar9300Common_rx_gain_table_2p2, ar9300Modes_fast_clock_2p2, ar9300Modes_lowest_ob_db_tx_gain_table_2p2, ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, ar9340_1p0_baseband_core, ar9340_1p0_baseband_postamble, ar9340_1p0_mac_core, ar9340_1p0_mac_postamble, ar9340_1p0_radio_core, ar9340_1p0_radio_core_40M, ar9340_1p0_radio_postamble, ar9340_1p0_soc_postamble, ar9340_1p0_soc_preamble, ar9340Common_wo_xlna_rx_gain_table_1p0, ar9340Modes_fast_clock_1p0, ar9340Modes_high_ob_db_tx_gain_table_1p0, ar9485_1_1, ar9485_1_1_baseband_core, ar9485_1_1_baseband_postamble, ar9485_1_1_mac_core, ar9485_1_1_mac_postamble, ar9485_1_1_pcie_phy_clkreq_disable_L1, ar9485_1_1_radio_core, ar9485_1_1_radio_postamble, ar9485_1_1_soc_preamble, ar9485_modes_lowest_ob_db_tx_gain_1_1, ar9485Common_wo_xlna_rx_gain_1_1, AR_SREV_9340, AR_SREV_9485_11, ARRAY_SIZE, ATH_INI_CORE, ATH_INI_POST, ATH_INI_PRE, INIT_INI_ARRAY, and NULL.

Referenced by ar9003_hw_attach_ops().

◆ ar9003_tx_gain_table_apply()

void ar9003_tx_gain_table_apply ( struct ath_hw * ah)
static

Definition at line 223 of file ath9k_ar9003_hw.c.

224{
225 switch (ar9003_hw_get_tx_gain_idx(ah)) {
226 case 0:
227 default:
228 if (AR_SREV_9340(ah))
229 INIT_INI_ARRAY(&ah->iniModesTxGain,
230 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
231 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
232 5);
233 else if (AR_SREV_9485_11(ah))
234 INIT_INI_ARRAY(&ah->iniModesTxGain,
235 ar9485_modes_lowest_ob_db_tx_gain_1_1,
236 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
237 5);
238 else
239 INIT_INI_ARRAY(&ah->iniModesTxGain,
240 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
241 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
242 5);
243 break;
244 case 1:
245 if (AR_SREV_9340(ah))
246 INIT_INI_ARRAY(&ah->iniModesTxGain,
247 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
248 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
249 5);
250 else if (AR_SREV_9485_11(ah))
251 INIT_INI_ARRAY(&ah->iniModesTxGain,
252 ar9485Modes_high_ob_db_tx_gain_1_1,
253 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
254 5);
255 else
256 INIT_INI_ARRAY(&ah->iniModesTxGain,
257 ar9300Modes_high_ob_db_tx_gain_table_2p2,
258 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
259 5);
260 break;
261 case 2:
262 if (AR_SREV_9340(ah))
263 INIT_INI_ARRAY(&ah->iniModesTxGain,
264 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
265 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
266 5);
267 else if (AR_SREV_9485_11(ah))
268 INIT_INI_ARRAY(&ah->iniModesTxGain,
269 ar9485Modes_low_ob_db_tx_gain_1_1,
270 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
271 5);
272 else
273 INIT_INI_ARRAY(&ah->iniModesTxGain,
274 ar9300Modes_low_ob_db_tx_gain_table_2p2,
275 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
276 5);
277 break;
278 case 3:
279 if (AR_SREV_9340(ah))
280 INIT_INI_ARRAY(&ah->iniModesTxGain,
281 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
282 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
283 5);
284 else if (AR_SREV_9485_11(ah))
285 INIT_INI_ARRAY(&ah->iniModesTxGain,
286 ar9485Modes_high_power_tx_gain_1_1,
287 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
288 5);
289 else
290 INIT_INI_ARRAY(&ah->iniModesTxGain,
291 ar9300Modes_high_power_tx_gain_table_2p2,
292 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
293 5);
294 break;
295 }
296}
ar9300Modes_high_ob_db_tx_gain_table_2p2
static __unused const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5]
Definition ar9003_2p2_initvals.h:944
ar9300Modes_high_power_tx_gain_table_2p2
static __unused const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5]
Definition ar9003_2p2_initvals.h:838
ar9300Modes_low_ob_db_tx_gain_table_2p2
static __unused const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5]
Definition ar9003_2p2_initvals.h:1310
ar9003_hw_get_tx_gain_idx
s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
Definition ath9k_ar9003_eeprom.c:4952
ar9340Modes_lowest_ob_db_tx_gain_table_1p0
static __unused const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5]
Definition ar9340_initvals.h:31
ar9485Modes_low_ob_db_tx_gain_1_1
static __unused const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5]
Definition ar9485_initvals.h:805
ar9485Modes_high_ob_db_tx_gain_1_1
static __unused const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5]
Definition ar9485_initvals.h:374
ar9485Modes_high_power_tx_gain_1_1
static __unused const u32 ar9485Modes_high_power_tx_gain_1_1[][5]
Definition ar9485_initvals.h:613

References ah, ar9003_hw_get_tx_gain_idx(), ar9300Modes_high_ob_db_tx_gain_table_2p2, ar9300Modes_high_power_tx_gain_table_2p2, ar9300Modes_low_ob_db_tx_gain_table_2p2, ar9300Modes_lowest_ob_db_tx_gain_table_2p2, ar9340Modes_lowest_ob_db_tx_gain_table_1p0, ar9485_modes_lowest_ob_db_tx_gain_1_1, ar9485Modes_high_ob_db_tx_gain_1_1, ar9485Modes_high_power_tx_gain_1_1, ar9485Modes_low_ob_db_tx_gain_1_1, AR_SREV_9340, AR_SREV_9485_11, ARRAY_SIZE, and INIT_INI_ARRAY.

Referenced by ar9003_hw_init_mode_gain_regs().

◆ ar9003_rx_gain_table_apply()

void ar9003_rx_gain_table_apply ( struct ath_hw * ah)
static

Definition at line 298 of file ath9k_ar9003_hw.c.

299{
300 switch (ar9003_hw_get_rx_gain_idx(ah)) {
301 case 0:
302 default:
303 if (AR_SREV_9340(ah))
304 INIT_INI_ARRAY(&ah->iniModesRxGain,
305 ar9340Common_rx_gain_table_1p0,
306 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
307 2);
308 else if (AR_SREV_9485_11(ah))
309 INIT_INI_ARRAY(&ah->iniModesRxGain,
310 ar9485Common_wo_xlna_rx_gain_1_1,
311 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
312 2);
313 else
314 INIT_INI_ARRAY(&ah->iniModesRxGain,
315 ar9300Common_rx_gain_table_2p2,
316 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
317 2);
318 break;
319 case 1:
320 if (AR_SREV_9340(ah))
321 INIT_INI_ARRAY(&ah->iniModesRxGain,
322 ar9340Common_wo_xlna_rx_gain_table_1p0,
323 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
324 2);
325 else if (AR_SREV_9485_11(ah))
326 INIT_INI_ARRAY(&ah->iniModesRxGain,
327 ar9485Common_wo_xlna_rx_gain_1_1,
328 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
329 2);
330 else
331 INIT_INI_ARRAY(&ah->iniModesRxGain,
332 ar9300Common_wo_xlna_rx_gain_table_2p2,
333 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
334 2);
335 break;
336 }
337}
ar9300Common_wo_xlna_rx_gain_table_2p2
static __unused const u32 ar9300Common_wo_xlna_rx_gain_table_2p2[][2]
Definition ar9003_2p2_initvals.h:1575
ar9003_hw_get_rx_gain_idx
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
Definition ath9k_ar9003_eeprom.c:4959
ar9340Common_rx_gain_table_1p0
static __unused const u32 ar9340Common_rx_gain_table_1p0[][2]
Definition ar9340_initvals.h:688

References ah, ar9003_hw_get_rx_gain_idx(), ar9300Common_rx_gain_table_2p2, ar9300Common_wo_xlna_rx_gain_table_2p2, ar9340Common_rx_gain_table_1p0, ar9340Common_wo_xlna_rx_gain_table_1p0, ar9485Common_wo_xlna_rx_gain_1_1, AR_SREV_9340, AR_SREV_9485_11, ARRAY_SIZE, and INIT_INI_ARRAY.

Referenced by ar9003_hw_init_mode_gain_regs().

◆ ar9003_hw_init_mode_gain_regs()

void ar9003_hw_init_mode_gain_regs ( struct ath_hw * ah)
static

Definition at line 340 of file ath9k_ar9003_hw.c.

341{
342 ar9003_tx_gain_table_apply(ah);
343 ar9003_rx_gain_table_apply(ah);
344}
ar9003_tx_gain_table_apply
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
Definition ath9k_ar9003_hw.c:223
ar9003_rx_gain_table_apply
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
Definition ath9k_ar9003_hw.c:298

References ah, ar9003_rx_gain_table_apply(), and ar9003_tx_gain_table_apply().

Referenced by ar9003_hw_attach_ops().

◆ ar9003_hw_configpcipowersave()

void ar9003_hw_configpcipowersave ( struct ath_hw * ah,
int restore,
int power_off )
static

Definition at line 355 of file ath9k_ar9003_hw.c.

358{
359 if (ah->is_pciexpress != 1)
360 return;
361
362 /* Do not touch SerDes registers */
363 if (ah->config.pcie_powersave_enable == 2)
364 return;
365
366 /* Nothing to do on restore for 11N */
367 if (!restore) {
368 /* set bit 19 to allow forcing of pcie core into L1 state */
369 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
370
371 /* Several PCIe massages to ensure proper behaviour */
372 if (ah->config.pcie_waen)
373 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
374 else
375 REG_WRITE(ah, AR_WA, ah->WARegVal);
376 }
377
378 /*
379 * Configire PCIE after Ini init. SERDES values now come from ini file
380 * This enables PCIe low power mode.
381 */
382 if (ah->config.pcieSerDesWrite) {
383 unsigned int i;
384 struct ar5416IniArray *array;
385
386 array = power_off ? &ah->iniPcieSerdes :
387 &ah->iniPcieSerdesLowPower;
388
389 for (i = 0; i < array->ia_rows; i++) {
390 REG_WRITE(ah,
391 INI_RA(array, i, 0),
392 INI_RA(array, i, 1));
393 }
394 }
395}
AR_PCIE_PM_CTRL_ENA
#define AR_PCIE_PM_CTRL_ENA
Definition reg.h:985
AR_PCIE_PM_CTRL
#define AR_PCIE_PM_CTRL
Definition reg.h:984
AR_WA
#define AR_WA
Definition reg.h:699
INI_RA
#define INI_RA(iniarray, row, column)
Definition calib.h:46
array
uint32_t array
Array number.
Definition edd.h:1
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition hw.h:78
REG_SET_BIT
#define REG_SET_BIT(_a, _r, _f)
Definition hw.h:108

References ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA, AR_WA, array, INI_RA, REG_SET_BIT, and REG_WRITE.

Referenced by ar9003_hw_attach_ops().

◆ ar9003_hw_attach_ops()

void ar9003_hw_attach_ops ( struct ath_hw * ah)

Definition at line 398 of file ath9k_ar9003_hw.c.

399{
400 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
401 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
402
403 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
404 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
405
406 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
407
408 ar9003_hw_attach_phy_ops(ah);
409 ar9003_hw_attach_calib_ops(ah);
410 ar9003_hw_attach_mac_ops(ah);
411}
ar9003_hw_attach_mac_ops
void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
Definition ath9k_ar9003_mac.c:503
ar9003_hw_attach_calib_ops
void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
Definition ath9k_ar9003_calib.c:924
ar9003_hw_configpcipowersave
static void ar9003_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
Definition ath9k_ar9003_hw.c:355
ar9003_hw_init_mode_regs
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
Definition ath9k_ar9003_hw.c:35
ar9003_hw_init_mode_gain_regs
static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
Definition ath9k_ar9003_hw.c:340
ar9003_hw_attach_phy_ops
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
Definition ath9k_ar9003_phy.c:1234
ath9k_hw_private_ops
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition hw.h:880
ath9k_hw_ops
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition hw.h:885
ath_hw_ops
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition hw.h:604
ath_hw_ops::config_pci_powersave
void(* config_pci_powersave)(struct ath_hw *ah, int restore, int power_off)
Definition hw.h:605
ath_hw_private_ops
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition hw.h:551
ath_hw_private_ops::init_mode_regs
void(* init_mode_regs)(struct ath_hw *ah)
Definition hw.h:556
ath_hw_private_ops::init_mode_gain_regs
void(* init_mode_gain_regs)(struct ath_hw *ah)
Definition hw.h:557

References ah, ar9003_hw_attach_calib_ops(), ar9003_hw_attach_mac_ops(), ar9003_hw_attach_phy_ops(), ar9003_hw_configpcipowersave(), ar9003_hw_init_mode_gain_regs(), ar9003_hw_init_mode_regs(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_ops::config_pci_powersave, ath_hw_private_ops::init_mode_gain_regs, and ath_hw_private_ops::init_mode_regs.

Referenced by ath9k_hw_attach_ops().

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