reg.h File Reference

#include "../reg.h"

Go to the source code of this file.

Macros
#define	AR_CR   0x0008
#define	AR_CR_RXE   (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
#define	AR_CR_RXD   0x00000020
#define	AR_CR_SWI   0x00000040
#define	AR_RXDP   0x000C
#define	AR_CFG   0x0014
#define	AR_CFG_SWTD   0x00000001
#define	AR_CFG_SWTB   0x00000002
#define	AR_CFG_SWRD   0x00000004
#define	AR_CFG_SWRB   0x00000008
#define	AR_CFG_SWRG   0x00000010
#define	AR_CFG_AP_ADHOC_INDICATION   0x00000020
#define	AR_CFG_PHOK   0x00000100
#define	AR_CFG_CLK_GATE_DIS   0x00000400
#define	AR_CFG_EEBS   0x00000200
#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH   0x00060000
#define	AR_CFG_PCI_MASTER_REQ_Q_THRESH_S   17
#define	AR_RXBP_THRESH   0x0018
#define	AR_RXBP_THRESH_HP   0x0000000f
#define	AR_RXBP_THRESH_HP_S   0
#define	AR_RXBP_THRESH_LP   0x00003f00
#define	AR_RXBP_THRESH_LP_S   8
#define	AR_MIRT   0x0020
#define	AR_MIRT_VAL   0x0000ffff
#define	AR_MIRT_VAL_S   16
#define	AR_IER   0x0024
#define	AR_IER_ENABLE   0x00000001
#define	AR_IER_DISABLE   0x00000000
#define	AR_TIMT   0x0028
#define	AR_TIMT_LAST   0x0000ffff
#define	AR_TIMT_LAST_S   0
#define	AR_TIMT_FIRST   0xffff0000
#define	AR_TIMT_FIRST_S   16
#define	AR_RIMT   0x002C
#define	AR_RIMT_LAST   0x0000ffff
#define	AR_RIMT_LAST_S   0
#define	AR_RIMT_FIRST   0xffff0000
#define	AR_RIMT_FIRST_S   16
#define	AR_DMASIZE_4B   0x00000000
#define	AR_DMASIZE_8B   0x00000001
#define	AR_DMASIZE_16B   0x00000002
#define	AR_DMASIZE_32B   0x00000003
#define	AR_DMASIZE_64B   0x00000004
#define	AR_DMASIZE_128B   0x00000005
#define	AR_DMASIZE_256B   0x00000006
#define	AR_DMASIZE_512B   0x00000007
#define	AR_TXCFG   0x0030
#define	AR_TXCFG_DMASZ_MASK   0x00000007
#define	AR_TXCFG_DMASZ_4B   0
#define	AR_TXCFG_DMASZ_8B   1
#define	AR_TXCFG_DMASZ_16B   2
#define	AR_TXCFG_DMASZ_32B   3
#define	AR_TXCFG_DMASZ_64B   4
#define	AR_TXCFG_DMASZ_128B   5
#define	AR_TXCFG_DMASZ_256B   6
#define	AR_TXCFG_DMASZ_512B   7
#define	AR_FTRIG   0x000003F0
#define	AR_FTRIG_S   4
#define	AR_FTRIG_IMMED   0x00000000
#define	AR_FTRIG_64B   0x00000010
#define	AR_FTRIG_128B   0x00000020
#define	AR_FTRIG_192B   0x00000030
#define	AR_FTRIG_256B   0x00000040
#define	AR_FTRIG_512B   0x00000080
#define	AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY   0x00000800
#define	AR_RXCFG   0x0034
#define	AR_RXCFG_CHIRP   0x00000008
#define	AR_RXCFG_ZLFDMA   0x00000010
#define	AR_RXCFG_DMASZ_MASK   0x00000007
#define	AR_RXCFG_DMASZ_4B   0
#define	AR_RXCFG_DMASZ_8B   1
#define	AR_RXCFG_DMASZ_16B   2
#define	AR_RXCFG_DMASZ_32B   3
#define	AR_RXCFG_DMASZ_64B   4
#define	AR_RXCFG_DMASZ_128B   5
#define	AR_RXCFG_DMASZ_256B   6
#define	AR_RXCFG_DMASZ_512B   7
#define	AR_TOPS   0x0044
#define	AR_TOPS_MASK   0x0000FFFF
#define	AR_RXNPTO   0x0048
#define	AR_RXNPTO_MASK   0x000003FF
#define	AR_TXNPTO   0x004C
#define	AR_TXNPTO_MASK   0x000003FF
#define	AR_TXNPTO_QCU_MASK   0x000FFC00
#define	AR_RPGTO   0x0050
#define	AR_RPGTO_MASK   0x000003FF
#define	AR_RPCNT   0x0054
#define	AR_RPCNT_MASK   0x0000001F
#define	AR_MACMISC   0x0058
#define	AR_MACMISC_PCI_EXT_FORCE   0x00000010
#define	AR_MACMISC_DMA_OBS   0x000001E0
#define	AR_MACMISC_DMA_OBS_S   5
#define	AR_MACMISC_DMA_OBS_LINE_0   0
#define	AR_MACMISC_DMA_OBS_LINE_1   1
#define	AR_MACMISC_DMA_OBS_LINE_2   2
#define	AR_MACMISC_DMA_OBS_LINE_3   3
#define	AR_MACMISC_DMA_OBS_LINE_4   4
#define	AR_MACMISC_DMA_OBS_LINE_5   5
#define	AR_MACMISC_DMA_OBS_LINE_6   6
#define	AR_MACMISC_DMA_OBS_LINE_7   7
#define	AR_MACMISC_DMA_OBS_LINE_8   8
#define	AR_MACMISC_MISC_OBS   0x00000E00
#define	AR_MACMISC_MISC_OBS_S   9
#define	AR_MACMISC_MISC_OBS_BUS_LSB   0x00007000
#define	AR_MACMISC_MISC_OBS_BUS_LSB_S   12
#define	AR_MACMISC_MISC_OBS_BUS_MSB   0x00038000
#define	AR_MACMISC_MISC_OBS_BUS_MSB_S   15
#define	AR_MACMISC_MISC_OBS_BUS_1   1
#define	AR_DATABUF_SIZE   0x0060
#define	AR_DATABUF_SIZE_MASK   0x00000FFF
#define	AR_GTXTO   0x0064
#define	AR_GTXTO_TIMEOUT_COUNTER   0x0000FFFF
#define	AR_GTXTO_TIMEOUT_LIMIT   0xFFFF0000
#define	AR_GTXTO_TIMEOUT_LIMIT_S   16
#define	AR_GTTM   0x0068
#define	AR_GTTM_USEC   0x00000001
#define	AR_GTTM_IGNORE_IDLE   0x00000002
#define	AR_GTTM_RESET_IDLE   0x00000004
#define	AR_GTTM_CST_USEC   0x00000008
#define	AR_CST   0x006C
#define	AR_CST_TIMEOUT_COUNTER   0x0000FFFF
#define	AR_CST_TIMEOUT_LIMIT   0xFFFF0000
#define	AR_CST_TIMEOUT_LIMIT_S   16
#define	AR_HP_RXDP   0x0074
#define	AR_LP_RXDP   0x0078
#define	AR_ISR   0x0080
#define	AR_ISR_RXOK   0x00000001
#define	AR_ISR_RXDESC   0x00000002
#define	AR_ISR_HP_RXOK   0x00000001
#define	AR_ISR_LP_RXOK   0x00000002
#define	AR_ISR_RXERR   0x00000004
#define	AR_ISR_RXNOPKT   0x00000008
#define	AR_ISR_RXEOL   0x00000010
#define	AR_ISR_RXORN   0x00000020
#define	AR_ISR_TXOK   0x00000040
#define	AR_ISR_TXDESC   0x00000080
#define	AR_ISR_TXERR   0x00000100
#define	AR_ISR_TXNOPKT   0x00000200
#define	AR_ISR_TXEOL   0x00000400
#define	AR_ISR_TXURN   0x00000800
#define	AR_ISR_MIB   0x00001000
#define	AR_ISR_SWI   0x00002000
#define	AR_ISR_RXPHY   0x00004000
#define	AR_ISR_RXKCM   0x00008000
#define	AR_ISR_SWBA   0x00010000
#define	AR_ISR_BRSSI   0x00020000
#define	AR_ISR_BMISS   0x00040000
#define	AR_ISR_BNR   0x00100000
#define	AR_ISR_RXCHIRP   0x00200000
#define	AR_ISR_BCNMISC   0x00800000
#define	AR_ISR_TIM   0x00800000
#define	AR_ISR_QCBROVF   0x02000000
#define	AR_ISR_QCBRURN   0x04000000
#define	AR_ISR_QTRIG   0x08000000
#define	AR_ISR_GENTMR   0x10000000
#define	AR_ISR_TXMINTR   0x00080000
#define	AR_ISR_RXMINTR   0x01000000
#define	AR_ISR_TXINTM   0x40000000
#define	AR_ISR_RXINTM   0x80000000
#define	AR_ISR_S0   0x0084
#define	AR_ISR_S0_QCU_TXOK   0x000003FF
#define	AR_ISR_S0_QCU_TXOK_S   0
#define	AR_ISR_S0_QCU_TXDESC   0x03FF0000
#define	AR_ISR_S0_QCU_TXDESC_S   16
#define	AR_ISR_S1   0x0088
#define	AR_ISR_S1_QCU_TXERR   0x000003FF
#define	AR_ISR_S1_QCU_TXERR_S   0
#define	AR_ISR_S1_QCU_TXEOL   0x03FF0000
#define	AR_ISR_S1_QCU_TXEOL_S   16
#define	AR_ISR_S2   0x008c
#define	AR_ISR_S2_QCU_TXURN   0x000003FF
#define	AR_ISR_S2_BB_WATCHDOG   0x00010000
#define	AR_ISR_S2_CST   0x00400000
#define	AR_ISR_S2_GTT   0x00800000
#define	AR_ISR_S2_TIM   0x01000000
#define	AR_ISR_S2_CABEND   0x02000000
#define	AR_ISR_S2_DTIMSYNC   0x04000000
#define	AR_ISR_S2_BCNTO   0x08000000
#define	AR_ISR_S2_CABTO   0x10000000
#define	AR_ISR_S2_DTIM   0x20000000
#define	AR_ISR_S2_TSFOOR   0x40000000
#define	AR_ISR_S2_TBTT_TIME   0x80000000
#define	AR_ISR_S3   0x0090
#define	AR_ISR_S3_QCU_QCBROVF   0x000003FF
#define	AR_ISR_S3_QCU_QCBRURN   0x03FF0000
#define	AR_ISR_S4   0x0094
#define	AR_ISR_S4_QCU_QTRIG   0x000003FF
#define	AR_ISR_S4_RESV0   0xFFFFFC00
#define	AR_ISR_S5   0x0098
#define	AR_ISR_S5_TIMER_TRIG   0x000000FF
#define	AR_ISR_S5_TIMER_THRESH   0x0007FE00
#define	AR_ISR_S5_TIM_TIMER   0x00000010
#define	AR_ISR_S5_DTIM_TIMER   0x00000020
#define	AR_IMR_S5   0x00b8
#define	AR_IMR_S5_TIM_TIMER   0x00000010
#define	AR_IMR_S5_DTIM_TIMER   0x00000020
#define	AR_ISR_S5_GENTIMER_TRIG   0x0000FF80
#define	AR_ISR_S5_GENTIMER_TRIG_S   0
#define	AR_ISR_S5_GENTIMER_THRESH   0xFF800000
#define	AR_ISR_S5_GENTIMER_THRESH_S   16
#define	AR_IMR_S5_GENTIMER_TRIG   0x0000FF80
#define	AR_IMR_S5_GENTIMER_TRIG_S   0
#define	AR_IMR_S5_GENTIMER_THRESH   0xFF800000
#define	AR_IMR_S5_GENTIMER_THRESH_S   16
#define	AR_IMR   0x00a0
#define	AR_IMR_RXOK   0x00000001
#define	AR_IMR_RXDESC   0x00000002
#define	AR_IMR_RXOK_HP   0x00000001
#define	AR_IMR_RXOK_LP   0x00000002
#define	AR_IMR_RXERR   0x00000004
#define	AR_IMR_RXNOPKT   0x00000008
#define	AR_IMR_RXEOL   0x00000010
#define	AR_IMR_RXORN   0x00000020
#define	AR_IMR_TXOK   0x00000040
#define	AR_IMR_TXDESC   0x00000080
#define	AR_IMR_TXERR   0x00000100
#define	AR_IMR_TXNOPKT   0x00000200
#define	AR_IMR_TXEOL   0x00000400
#define	AR_IMR_TXURN   0x00000800
#define	AR_IMR_MIB   0x00001000
#define	AR_IMR_SWI   0x00002000
#define	AR_IMR_RXPHY   0x00004000
#define	AR_IMR_RXKCM   0x00008000
#define	AR_IMR_SWBA   0x00010000
#define	AR_IMR_BRSSI   0x00020000
#define	AR_IMR_BMISS   0x00040000
#define	AR_IMR_BNR   0x00100000
#define	AR_IMR_RXCHIRP   0x00200000
#define	AR_IMR_BCNMISC   0x00800000
#define	AR_IMR_TIM   0x00800000
#define	AR_IMR_QCBROVF   0x02000000
#define	AR_IMR_QCBRURN   0x04000000
#define	AR_IMR_QTRIG   0x08000000
#define	AR_IMR_GENTMR   0x10000000
#define	AR_IMR_TXMINTR   0x00080000
#define	AR_IMR_RXMINTR   0x01000000
#define	AR_IMR_TXINTM   0x40000000
#define	AR_IMR_RXINTM   0x80000000
#define	AR_IMR_S0   0x00a4
#define	AR_IMR_S0_QCU_TXOK   0x000003FF
#define	AR_IMR_S0_QCU_TXOK_S   0
#define	AR_IMR_S0_QCU_TXDESC   0x03FF0000
#define	AR_IMR_S0_QCU_TXDESC_S   16
#define	AR_IMR_S1   0x00a8
#define	AR_IMR_S1_QCU_TXERR   0x000003FF
#define	AR_IMR_S1_QCU_TXERR_S   0
#define	AR_IMR_S1_QCU_TXEOL   0x03FF0000
#define	AR_IMR_S1_QCU_TXEOL_S   16
#define	AR_IMR_S2   0x00ac
#define	AR_IMR_S2_QCU_TXURN   0x000003FF
#define	AR_IMR_S2_QCU_TXURN_S   0
#define	AR_IMR_S2_CST   0x00400000
#define	AR_IMR_S2_GTT   0x00800000
#define	AR_IMR_S2_TIM   0x01000000
#define	AR_IMR_S2_CABEND   0x02000000
#define	AR_IMR_S2_DTIMSYNC   0x04000000
#define	AR_IMR_S2_BCNTO   0x08000000
#define	AR_IMR_S2_CABTO   0x10000000
#define	AR_IMR_S2_DTIM   0x20000000
#define	AR_IMR_S2_TSFOOR   0x40000000
#define	AR_IMR_S3   0x00b0
#define	AR_IMR_S3_QCU_QCBROVF   0x000003FF
#define	AR_IMR_S3_QCU_QCBRURN   0x03FF0000
#define	AR_IMR_S3_QCU_QCBRURN_S   16
#define	AR_IMR_S4   0x00b4
#define	AR_IMR_S4_QCU_QTRIG   0x000003FF
#define	AR_IMR_S4_RESV0   0xFFFFFC00
#define	AR_IMR_S5   0x00b8
#define	AR_IMR_S5_TIMER_TRIG   0x000000FF
#define	AR_IMR_S5_TIMER_THRESH   0x0000FF00
#define	AR_ISR_RAC   0x00c0
#define	AR_ISR_S0_S   0x00c4
#define	AR_ISR_S0_QCU_TXOK   0x000003FF
#define	AR_ISR_S0_QCU_TXOK_S   0
#define	AR_ISR_S0_QCU_TXDESC   0x03FF0000
#define	AR_ISR_S0_QCU_TXDESC_S   16
#define	AR_ISR_S1_S   0x00c8
#define	AR_ISR_S1_QCU_TXERR   0x000003FF
#define	AR_ISR_S1_QCU_TXERR_S   0
#define	AR_ISR_S1_QCU_TXEOL   0x03FF0000
#define	AR_ISR_S1_QCU_TXEOL_S   16
#define	AR_ISR_S2_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
#define	AR_ISR_S3_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
#define	AR_ISR_S4_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
#define	AR_ISR_S5_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
#define	AR_DMADBG_0   0x00e0
#define	AR_DMADBG_1   0x00e4
#define	AR_DMADBG_2   0x00e8
#define	AR_DMADBG_3   0x00ec
#define	AR_DMADBG_4   0x00f0
#define	AR_DMADBG_5   0x00f4
#define	AR_DMADBG_6   0x00f8
#define	AR_DMADBG_7   0x00fc
#define	AR_NUM_QCU   10
#define	AR_QCU_0   0x0001
#define	AR_QCU_1   0x0002
#define	AR_QCU_2   0x0004
#define	AR_QCU_3   0x0008
#define	AR_QCU_4   0x0010
#define	AR_QCU_5   0x0020
#define	AR_QCU_6   0x0040
#define	AR_QCU_7   0x0080
#define	AR_QCU_8   0x0100
#define	AR_QCU_9   0x0200
#define	AR_Q0_TXDP   0x0800
#define	AR_Q1_TXDP   0x0804
#define	AR_Q2_TXDP   0x0808
#define	AR_Q3_TXDP   0x080c
#define	AR_Q4_TXDP   0x0810
#define	AR_Q5_TXDP   0x0814
#define	AR_Q6_TXDP   0x0818
#define	AR_Q7_TXDP   0x081c
#define	AR_Q8_TXDP   0x0820
#define	AR_Q9_TXDP   0x0824
#define	AR_QTXDP(_i)
#define	AR_Q_STATUS_RING_START   0x830
#define	AR_Q_STATUS_RING_END   0x834
#define	AR_Q_TXE   0x0840
#define	AR_Q_TXE_M   0x000003FF
#define	AR_Q_TXD   0x0880
#define	AR_Q_TXD_M   0x000003FF
#define	AR_Q0_CBRCFG   0x08c0
#define	AR_Q1_CBRCFG   0x08c4
#define	AR_Q2_CBRCFG   0x08c8
#define	AR_Q3_CBRCFG   0x08cc
#define	AR_Q4_CBRCFG   0x08d0
#define	AR_Q5_CBRCFG   0x08d4
#define	AR_Q6_CBRCFG   0x08d8
#define	AR_Q7_CBRCFG   0x08dc
#define	AR_Q8_CBRCFG   0x08e0
#define	AR_Q9_CBRCFG   0x08e4
#define	AR_QCBRCFG(_i)
#define	AR_Q_CBRCFG_INTERVAL   0x00FFFFFF
#define	AR_Q_CBRCFG_INTERVAL_S   0
#define	AR_Q_CBRCFG_OVF_THRESH   0xFF000000
#define	AR_Q_CBRCFG_OVF_THRESH_S   24
#define	AR_Q0_RDYTIMECFG   0x0900
#define	AR_Q1_RDYTIMECFG   0x0904
#define	AR_Q2_RDYTIMECFG   0x0908
#define	AR_Q3_RDYTIMECFG   0x090c
#define	AR_Q4_RDYTIMECFG   0x0910
#define	AR_Q5_RDYTIMECFG   0x0914
#define	AR_Q6_RDYTIMECFG   0x0918
#define	AR_Q7_RDYTIMECFG   0x091c
#define	AR_Q8_RDYTIMECFG   0x0920
#define	AR_Q9_RDYTIMECFG   0x0924
#define	AR_QRDYTIMECFG(_i)
#define	AR_Q_RDYTIMECFG_DURATION   0x00FFFFFF
#define	AR_Q_RDYTIMECFG_DURATION_S   0
#define	AR_Q_RDYTIMECFG_EN   0x01000000
#define	AR_Q_ONESHOTARM_SC   0x0940
#define	AR_Q_ONESHOTARM_SC_M   0x000003FF
#define	AR_Q_ONESHOTARM_SC_RESV0   0xFFFFFC00
#define	AR_Q_ONESHOTARM_CC   0x0980
#define	AR_Q_ONESHOTARM_CC_M   0x000003FF
#define	AR_Q_ONESHOTARM_CC_RESV0   0xFFFFFC00
#define	AR_Q0_MISC   0x09c0
#define	AR_Q1_MISC   0x09c4
#define	AR_Q2_MISC   0x09c8
#define	AR_Q3_MISC   0x09cc
#define	AR_Q4_MISC   0x09d0
#define	AR_Q5_MISC   0x09d4
#define	AR_Q6_MISC   0x09d8
#define	AR_Q7_MISC   0x09dc
#define	AR_Q8_MISC   0x09e0
#define	AR_Q9_MISC   0x09e4
#define	AR_QMISC(_i)
#define	AR_Q_MISC_FSP   0x0000000F
#define	AR_Q_MISC_FSP_ASAP   0
#define	AR_Q_MISC_FSP_CBR   1
#define	AR_Q_MISC_FSP_DBA_GATED   2
#define	AR_Q_MISC_FSP_TIM_GATED   3
#define	AR_Q_MISC_FSP_BEACON_SENT_GATED   4
#define	AR_Q_MISC_FSP_BEACON_RCVD_GATED   5
#define	AR_Q_MISC_ONE_SHOT_EN   0x00000010
#define	AR_Q_MISC_CBR_INCR_DIS1   0x00000020
#define	AR_Q_MISC_CBR_INCR_DIS0   0x00000040
#define	AR_Q_MISC_BEACON_USE   0x00000080
#define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN   0x00000100
#define	AR_Q_MISC_RDYTIME_EXP_POLICY   0x00000200
#define	AR_Q_MISC_RESET_CBR_EXP_CTR   0x00000400
#define	AR_Q_MISC_DCU_EARLY_TERM_REQ   0x00000800
#define	AR_Q_MISC_RESV0   0xFFFFF000
#define	AR_Q0_STS   0x0a00
#define	AR_Q1_STS   0x0a04
#define	AR_Q2_STS   0x0a08
#define	AR_Q3_STS   0x0a0c
#define	AR_Q4_STS   0x0a10
#define	AR_Q5_STS   0x0a14
#define	AR_Q6_STS   0x0a18
#define	AR_Q7_STS   0x0a1c
#define	AR_Q8_STS   0x0a20
#define	AR_Q9_STS   0x0a24
#define	AR_QSTS(_i)
#define	AR_Q_STS_PEND_FR_CNT   0x00000003
#define	AR_Q_STS_RESV0   0x000000FC
#define	AR_Q_STS_CBR_EXP_CNT   0x0000FF00
#define	AR_Q_STS_RESV1   0xFFFF0000
#define	AR_Q_RDYTIMESHDN   0x0a40
#define	AR_Q_RDYTIMESHDN_M   0x000003FF
#define	AR_Q_DESC_CRCCHK   0xa44
#define	AR_Q_DESC_CRCCHK_EN   1
#define	AR_NUM_DCU   10
#define	AR_DCU_0   0x0001
#define	AR_DCU_1   0x0002
#define	AR_DCU_2   0x0004
#define	AR_DCU_3   0x0008
#define	AR_DCU_4   0x0010
#define	AR_DCU_5   0x0020
#define	AR_DCU_6   0x0040
#define	AR_DCU_7   0x0080
#define	AR_DCU_8   0x0100
#define	AR_DCU_9   0x0200
#define	AR_D0_QCUMASK   0x1000
#define	AR_D1_QCUMASK   0x1004
#define	AR_D2_QCUMASK   0x1008
#define	AR_D3_QCUMASK   0x100c
#define	AR_D4_QCUMASK   0x1010
#define	AR_D5_QCUMASK   0x1014
#define	AR_D6_QCUMASK   0x1018
#define	AR_D7_QCUMASK   0x101c
#define	AR_D8_QCUMASK   0x1020
#define	AR_D9_QCUMASK   0x1024
#define	AR_DQCUMASK(_i)
#define	AR_D_QCUMASK   0x000003FF
#define	AR_D_QCUMASK_RESV0   0xFFFFFC00
#define	AR_D_TXBLK_CMD   0x1038
#define	AR_D_TXBLK_DATA(i)
#define	AR_D0_LCL_IFS   0x1040
#define	AR_D1_LCL_IFS   0x1044
#define	AR_D2_LCL_IFS   0x1048
#define	AR_D3_LCL_IFS   0x104c
#define	AR_D4_LCL_IFS   0x1050
#define	AR_D5_LCL_IFS   0x1054
#define	AR_D6_LCL_IFS   0x1058
#define	AR_D7_LCL_IFS   0x105c
#define	AR_D8_LCL_IFS   0x1060
#define	AR_D9_LCL_IFS   0x1064
#define	AR_DLCL_IFS(_i)
#define	AR_D_LCL_IFS_CWMIN   0x000003FF
#define	AR_D_LCL_IFS_CWMIN_S   0
#define	AR_D_LCL_IFS_CWMAX   0x000FFC00
#define	AR_D_LCL_IFS_CWMAX_S   10
#define	AR_D_LCL_IFS_AIFS   0x0FF00000
#define	AR_D_LCL_IFS_AIFS_S   20
#define	AR_D_LCL_IFS_RESV0   0xF0000000
#define	AR_D0_RETRY_LIMIT   0x1080
#define	AR_D1_RETRY_LIMIT   0x1084
#define	AR_D2_RETRY_LIMIT   0x1088
#define	AR_D3_RETRY_LIMIT   0x108c
#define	AR_D4_RETRY_LIMIT   0x1090
#define	AR_D5_RETRY_LIMIT   0x1094
#define	AR_D6_RETRY_LIMIT   0x1098
#define	AR_D7_RETRY_LIMIT   0x109c
#define	AR_D8_RETRY_LIMIT   0x10a0
#define	AR_D9_RETRY_LIMIT   0x10a4
#define	AR_DRETRY_LIMIT(_i)
#define	AR_D_RETRY_LIMIT_FR_SH   0x0000000F
#define	AR_D_RETRY_LIMIT_FR_SH_S   0
#define	AR_D_RETRY_LIMIT_STA_SH   0x00003F00
#define	AR_D_RETRY_LIMIT_STA_SH_S   8
#define	AR_D_RETRY_LIMIT_STA_LG   0x000FC000
#define	AR_D_RETRY_LIMIT_STA_LG_S   14
#define	AR_D_RETRY_LIMIT_RESV0   0xFFF00000
#define	AR_D0_CHNTIME   0x10c0
#define	AR_D1_CHNTIME   0x10c4
#define	AR_D2_CHNTIME   0x10c8
#define	AR_D3_CHNTIME   0x10cc
#define	AR_D4_CHNTIME   0x10d0
#define	AR_D5_CHNTIME   0x10d4
#define	AR_D6_CHNTIME   0x10d8
#define	AR_D7_CHNTIME   0x10dc
#define	AR_D8_CHNTIME   0x10e0
#define	AR_D9_CHNTIME   0x10e4
#define	AR_DCHNTIME(_i)
#define	AR_D_CHNTIME_DUR   0x000FFFFF
#define	AR_D_CHNTIME_DUR_S   0
#define	AR_D_CHNTIME_EN   0x00100000
#define	AR_D_CHNTIME_RESV0   0xFFE00000
#define	AR_D0_MISC   0x1100
#define	AR_D1_MISC   0x1104
#define	AR_D2_MISC   0x1108
#define	AR_D3_MISC   0x110c
#define	AR_D4_MISC   0x1110
#define	AR_D5_MISC   0x1114
#define	AR_D6_MISC   0x1118
#define	AR_D7_MISC   0x111c
#define	AR_D8_MISC   0x1120
#define	AR_D9_MISC   0x1124
#define	AR_DMISC(_i)
#define	AR_D_MISC_BKOFF_THRESH   0x0000003F
#define	AR_D_MISC_RETRY_CNT_RESET_EN   0x00000040
#define	AR_D_MISC_CW_RESET_EN   0x00000080
#define	AR_D_MISC_FRAG_WAIT_EN   0x00000100
#define	AR_D_MISC_FRAG_BKOFF_EN   0x00000200
#define	AR_D_MISC_CW_BKOFF_EN   0x00001000
#define	AR_D_MISC_VIR_COL_HANDLING   0x0000C000
#define	AR_D_MISC_VIR_COL_HANDLING_S   14
#define	AR_D_MISC_VIR_COL_HANDLING_DEFAULT   0
#define	AR_D_MISC_VIR_COL_HANDLING_IGNORE   1
#define	AR_D_MISC_BEACON_USE   0x00010000
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL   0x00060000
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_S   17
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE   0
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR   1
#define	AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2
#define	AR_D_MISC_ARB_LOCKOUT_IGNORE   0x00080000
#define	AR_D_MISC_SEQ_NUM_INCR_DIS   0x00100000
#define	AR_D_MISC_POST_FR_BKOFF_DIS   0x00200000
#define	AR_D_MISC_VIT_COL_CW_BKOFF_EN   0x00400000
#define	AR_D_MISC_BLOWN_IFS_RETRY_EN   0x00800000
#define	AR_D_MISC_RESV0   0xFF000000
#define	AR_D_SEQNUM   0x1140
#define	AR_D_GBL_IFS_SIFS   0x1030
#define	AR_D_GBL_IFS_SIFS_M   0x0000FFFF
#define	AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR   0x000003AB
#define	AR_D_GBL_IFS_SIFS_RESV0   0xFFFFFFFF
#define	AR_D_TXBLK_BASE   0x1038
#define	AR_D_TXBLK_WRITE_BITMASK   0x0000FFFF
#define	AR_D_TXBLK_WRITE_BITMASK_S   0
#define	AR_D_TXBLK_WRITE_SLICE   0x000F0000
#define	AR_D_TXBLK_WRITE_SLICE_S   16
#define	AR_D_TXBLK_WRITE_DCU   0x00F00000
#define	AR_D_TXBLK_WRITE_DCU_S   20
#define	AR_D_TXBLK_WRITE_COMMAND   0x0F000000
#define	AR_D_TXBLK_WRITE_COMMAND_S   24
#define	AR_D_GBL_IFS_SLOT   0x1070
#define	AR_D_GBL_IFS_SLOT_M   0x0000FFFF
#define	AR_D_GBL_IFS_SLOT_RESV0   0xFFFF0000
#define	AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR   0x00000420
#define	AR_D_GBL_IFS_EIFS   0x10b0
#define	AR_D_GBL_IFS_EIFS_M   0x0000FFFF
#define	AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000
#define	AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR   0x0000A5EB
#define	AR_D_GBL_IFS_MISC   0x10f0
#define	AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL   0x00000007
#define	AR_D_GBL_IFS_MISC_TURBO_MODE   0x00000008
#define	AR_D_GBL_IFS_MISC_USEC_DURATION   0x000FFC00
#define	AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY   0x00300000
#define	AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS   0x01000000
#define	AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN   0x06000000
#define	AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND   0x08000000
#define	AR_D_GBL_IFS_MISC_IGNORE_BACKOFF   0x10000000
#define	AR_D_FPCTL   0x1230
#define	AR_D_FPCTL_DCU   0x0000000F
#define	AR_D_FPCTL_DCU_S   0
#define	AR_D_FPCTL_PREFETCH_EN   0x00000010
#define	AR_D_FPCTL_BURST_PREFETCH   0x00007FE0
#define	AR_D_FPCTL_BURST_PREFETCH_S   5
#define	AR_D_TXPSE   0x1270
#define	AR_D_TXPSE_CTRL   0x000003FF
#define	AR_D_TXPSE_RESV0   0x0000FC00
#define	AR_D_TXPSE_STATUS   0x00010000
#define	AR_D_TXPSE_RESV1   0xFFFE0000
#define	AR_D_TXSLOTMASK   0x12f0
#define	AR_D_TXSLOTMASK_NUM   0x0000000F
#define	AR_CFG_LED   0x1f04
#define	AR_CFG_SCLK_RATE_IND   0x00000003
#define	AR_CFG_SCLK_RATE_IND_S   0
#define	AR_CFG_SCLK_32MHZ   0x00000000
#define	AR_CFG_SCLK_4MHZ   0x00000001
#define	AR_CFG_SCLK_1MHZ   0x00000002
#define	AR_CFG_SCLK_32KHZ   0x00000003
#define	AR_CFG_LED_BLINK_SLOW   0x00000008
#define	AR_CFG_LED_BLINK_THRESH_SEL   0x00000070
#define	AR_CFG_LED_MODE_SEL   0x00000380
#define	AR_CFG_LED_MODE_SEL_S   7
#define	AR_CFG_LED_POWER   0x00000280
#define	AR_CFG_LED_POWER_S   7
#define	AR_CFG_LED_NETWORK   0x00000300
#define	AR_CFG_LED_NETWORK_S   7
#define	AR_CFG_LED_MODE_PROP   0x0
#define	AR_CFG_LED_MODE_RPROP   0x1
#define	AR_CFG_LED_MODE_SPLIT   0x2
#define	AR_CFG_LED_MODE_RAND   0x3
#define	AR_CFG_LED_MODE_POWER_OFF   0x4
#define	AR_CFG_LED_MODE_POWER_ON   0x5
#define	AR_CFG_LED_MODE_NETWORK_OFF   0x4
#define	AR_CFG_LED_MODE_NETWORK_ON   0x6
#define	AR_CFG_LED_ASSOC_CTL   0x00000c00
#define	AR_CFG_LED_ASSOC_CTL_S   10
#define	AR_CFG_LED_ASSOC_NONE   0x0
#define	AR_CFG_LED_ASSOC_ACTIVE   0x1
#define	AR_CFG_LED_ASSOC_PENDING   0x2
#define	AR_CFG_LED_BLINK_SLOW   0x00000008
#define	AR_CFG_LED_BLINK_SLOW_S   3
#define	AR_CFG_LED_BLINK_THRESH_SEL   0x00000070
#define	AR_CFG_LED_BLINK_THRESH_SEL_S   4
#define	AR_MAC_SLEEP   0x1f00
#define	AR_MAC_SLEEP_MAC_AWAKE   0x00000000
#define	AR_MAC_SLEEP_MAC_ASLEEP   0x00000001
#define	AR_RC   0x4000
#define	AR_RC_AHB   0x00000001
#define	AR_RC_APB   0x00000002
#define	AR_RC_HOSTIF   0x00000100
#define	AR_WA   (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
#define	AR_WA_BIT6   (1 << 6)
#define	AR_WA_BIT7   (1 << 7)
#define	AR_WA_BIT23   (1 << 23)
#define	AR_WA_D3_L1_DISABLE   (1 << 14)
#define	AR_WA_D3_TO_L1_DISABLE_REAL   (1 << 16)
#define	AR_WA_ASPM_TIMER_BASED_DISABLE   (1 << 17)
#define	AR_WA_RESET_EN   (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */
#define	AR_WA_ANALOG_SHIFT   (1 << 20)
#define	AR_WA_POR_SHORT   (1 << 21) /* PCI-E Phy reset control */
#define	AR_WA_BIT22   (1 << 22)
#define	AR9285_WA_DEFAULT   0x004a050b
#define	AR9280_WA_DEFAULT   0x0040073b
#define	AR_WA_DEFAULT   0x0000073f
#define	AR_PM_STATE   0x4008
#define	AR_PM_STATE_PME_D3COLD_VAUX   0x00100000
#define	AR_HOST_TIMEOUT   (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
#define	AR_HOST_TIMEOUT_APB_CNTR   0x0000FFFF
#define	AR_HOST_TIMEOUT_APB_CNTR_S   0
#define	AR_HOST_TIMEOUT_LCL_CNTR   0xFFFF0000
#define	AR_HOST_TIMEOUT_LCL_CNTR_S   16
#define	AR_EEPROM   0x401c
#define	AR_EEPROM_ABSENT   0x00000100
#define	AR_EEPROM_CORRUPT   0x00000200
#define	AR_EEPROM_PROT_MASK   0x03FFFC00
#define	AR_EEPROM_PROT_MASK_S   10
#define	EEPROM_PROTECT_RP_0_31   0x0001
#define	EEPROM_PROTECT_WP_0_31   0x0002
#define	EEPROM_PROTECT_RP_32_63   0x0004
#define	EEPROM_PROTECT_WP_32_63   0x0008
#define	EEPROM_PROTECT_RP_64_127   0x0010
#define	EEPROM_PROTECT_WP_64_127   0x0020
#define	EEPROM_PROTECT_RP_128_191   0x0040
#define	EEPROM_PROTECT_WP_128_191   0x0080
#define	EEPROM_PROTECT_RP_192_255   0x0100
#define	EEPROM_PROTECT_WP_192_255   0x0200
#define	EEPROM_PROTECT_RP_256_511   0x0400
#define	EEPROM_PROTECT_WP_256_511   0x0800
#define	EEPROM_PROTECT_RP_512_1023   0x1000
#define	EEPROM_PROTECT_WP_512_1023   0x2000
#define	EEPROM_PROTECT_RP_1024_2047   0x4000
#define	EEPROM_PROTECT_WP_1024_2047   0x8000
#define	AR_SREV
#define	AR_SREV_ID    ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
#define	AR_SREV_VERSION   0x000000F0
#define	AR_SREV_VERSION_S   4
#define	AR_SREV_REVISION   0x00000007
#define	AR_SREV_ID2   0xFFFFFFFF
#define	AR_SREV_VERSION2   0xFFFC0000
#define	AR_SREV_VERSION2_S   18
#define	AR_SREV_TYPE2   0x0003F000
#define	AR_SREV_TYPE2_S   12
#define	AR_SREV_TYPE2_CHAIN   0x00001000
#define	AR_SREV_TYPE2_HOST_MODE   0x00002000
#define	AR_SREV_REVISION2   0x00000F00
#define	AR_SREV_REVISION2_S   8
#define	AR_SREV_VERSION_5416_PCI   0xD
#define	AR_SREV_VERSION_5416_PCIE   0xC
#define	AR_SREV_REVISION_5416_10   0
#define	AR_SREV_REVISION_5416_20   1
#define	AR_SREV_REVISION_5416_22   2
#define	AR_SREV_VERSION_9100   0x14
#define	AR_SREV_VERSION_9160   0x40
#define	AR_SREV_REVISION_9160_10   0
#define	AR_SREV_REVISION_9160_11   1
#define	AR_SREV_VERSION_9280   0x80
#define	AR_SREV_REVISION_9280_10   0
#define	AR_SREV_REVISION_9280_20   1
#define	AR_SREV_REVISION_9280_21   2
#define	AR_SREV_VERSION_9285   0xC0
#define	AR_SREV_REVISION_9285_10   0
#define	AR_SREV_REVISION_9285_11   1
#define	AR_SREV_REVISION_9285_12   2
#define	AR_SREV_VERSION_9287   0x180
#define	AR_SREV_REVISION_9287_10   0
#define	AR_SREV_REVISION_9287_11   1
#define	AR_SREV_REVISION_9287_12   2
#define	AR_SREV_REVISION_9287_13   3
#define	AR_SREV_VERSION_9271   0x140
#define	AR_SREV_REVISION_9271_10   0
#define	AR_SREV_REVISION_9271_11   1
#define	AR_SREV_VERSION_9300   0x1c0
#define	AR_SREV_REVISION_9300_20   2 /* 2.0 and 2.1 */
#define	AR_SREV_VERSION_9485   0x240
#define	AR_SREV_REVISION_9485_10   0
#define	AR_SREV_REVISION_9485_11   1
#define	AR_SREV_VERSION_9340   0x300
#define	AR_SREV_5416(_ah)
#define	AR_SREV_5416_20_OR_LATER(_ah)
#define	AR_SREV_5416_22_OR_LATER(_ah)
#define	AR_SREV_9100(ah)
#define	AR_SREV_9100_OR_LATER(_ah)
#define	AR_SREV_9160(_ah)
#define	AR_SREV_9160_10_OR_LATER(_ah)
#define	AR_SREV_9160_11(_ah)
#define	AR_SREV_9280(_ah)
#define	AR_SREV_9280_20_OR_LATER(_ah)
#define	AR_SREV_9280_20(_ah)
#define	AR_SREV_9285(_ah)
#define	AR_SREV_9285_12_OR_LATER(_ah)
#define	AR_SREV_9287(_ah)
#define	AR_SREV_9287_11_OR_LATER(_ah)
#define	AR_SREV_9287_11(_ah)
#define	AR_SREV_9287_12(_ah)
#define	AR_SREV_9287_12_OR_LATER(_ah)
#define	AR_SREV_9287_13_OR_LATER(_ah)
#define	AR_SREV_9271(_ah)
#define	AR_SREV_9271_10(_ah)
#define	AR_SREV_9271_11(_ah)
#define	AR_SREV_9300(_ah)
#define	AR_SREV_9300_20_OR_LATER(_ah)
#define	AR_SREV_9485(_ah)
#define	AR_SREV_9485_10(_ah)
#define	AR_SREV_9485_11(_ah)
#define	AR_SREV_9485_OR_LATER(_ah)
#define	AR_SREV_9340(_ah)
#define	AR_SREV_9285E_20(_ah)
#define	AR_DEVID_7010(_ah)
#define	AR_RADIO_SREV_MAJOR   0xf0
#define	AR_RAD5133_SREV_MAJOR   0xc0
#define	AR_RAD2133_SREV_MAJOR   0xd0
#define	AR_RAD5122_SREV_MAJOR   0xe0
#define	AR_RAD2122_SREV_MAJOR   0xf0
#define	AR_AHB_MODE   0x4024
#define	AR_AHB_EXACT_WR_EN   0x00000000
#define	AR_AHB_BUF_WR_EN   0x00000001
#define	AR_AHB_EXACT_RD_EN   0x00000000
#define	AR_AHB_CACHELINE_RD_EN   0x00000002
#define	AR_AHB_PREFETCH_RD_EN   0x00000004
#define	AR_AHB_PAGE_SIZE_1K   0x00000000
#define	AR_AHB_PAGE_SIZE_2K   0x00000008
#define	AR_AHB_PAGE_SIZE_4K   0x00000010
#define	AR_AHB_CUSTOM_BURST_EN   0x000000C0
#define	AR_AHB_CUSTOM_BURST_EN_S   6
#define	AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL   3
#define	AR_INTR_RTC_IRQ   0x00000001
#define	AR_INTR_MAC_IRQ   0x00000002
#define	AR_INTR_EEP_PROT_ACCESS   0x00000004
#define	AR_INTR_MAC_AWAKE   0x00020000
#define	AR_INTR_MAC_ASLEEP   0x00040000
#define	AR_INTR_SPURIOUS   0xFFFFFFFF
#define	AR_INTR_SYNC_CAUSE   (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
#define	AR_INTR_SYNC_CAUSE_CLR   (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
#define	AR_INTR_SYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
#define	AR_INTR_SYNC_ENABLE_GPIO   0xFFFC0000
#define	AR_INTR_SYNC_ENABLE_GPIO_S   18
#define	AR_INTR_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
#define	AR_INTR_ASYNC_MASK_GPIO   0xFFFC0000
#define	AR_INTR_ASYNC_MASK_GPIO_S   18
#define	AR_INTR_SYNC_MASK   (AR_SREV_9340(ah) ? 0x401c : 0x4034)
#define	AR_INTR_SYNC_MASK_GPIO   0xFFFC0000
#define	AR_INTR_SYNC_MASK_GPIO_S   18
#define	AR_INTR_ASYNC_CAUSE_CLR   (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
#define	AR_INTR_ASYNC_CAUSE   (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
#define	AR_INTR_ASYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
#define	AR_INTR_ASYNC_ENABLE_GPIO   0xFFFC0000
#define	AR_INTR_ASYNC_ENABLE_GPIO_S   18
#define	AR_PCIE_SERDES   0x4040
#define	AR_PCIE_SERDES2   0x4044
#define	AR_PCIE_PM_CTRL   (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
#define	AR_PCIE_PM_CTRL_ENA   0x00080000
#define	AR_NUM_GPIO   14
#define	AR928X_NUM_GPIO   10
#define	AR9285_NUM_GPIO   12
#define	AR9287_NUM_GPIO   11
#define	AR9271_NUM_GPIO   16
#define	AR9300_NUM_GPIO   17
#define	AR7010_NUM_GPIO   16
#define	AR_GPIO_IN_OUT   (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
#define	AR_GPIO_IN_VAL   0x0FFFC000
#define	AR_GPIO_IN_VAL_S   14
#define	AR928X_GPIO_IN_VAL   0x000FFC00
#define	AR928X_GPIO_IN_VAL_S   10
#define	AR9285_GPIO_IN_VAL   0x00FFF000
#define	AR9285_GPIO_IN_VAL_S   12
#define	AR9287_GPIO_IN_VAL   0x003FF800
#define	AR9287_GPIO_IN_VAL_S   11
#define	AR9271_GPIO_IN_VAL   0xFFFF0000
#define	AR9271_GPIO_IN_VAL_S   16
#define	AR7010_GPIO_IN_VAL   0x0000FFFF
#define	AR7010_GPIO_IN_VAL_S   0
#define	AR_GPIO_IN   (AR_SREV_9340(ah) ? 0x402c : 0x404c)
#define	AR9300_GPIO_IN_VAL   0x0001FFFF
#define	AR9300_GPIO_IN_VAL_S   0
#define	AR_GPIO_OE_OUT
#define	AR_GPIO_OE_OUT_DRV   0x3
#define	AR_GPIO_OE_OUT_DRV_NO   0x0
#define	AR_GPIO_OE_OUT_DRV_LOW   0x1
#define	AR_GPIO_OE_OUT_DRV_HI   0x2
#define	AR_GPIO_OE_OUT_DRV_ALL   0x3
#define	AR7010_GPIO_OE   0x52000
#define	AR7010_GPIO_OE_MASK   0x1
#define	AR7010_GPIO_OE_AS_OUTPUT   0x0
#define	AR7010_GPIO_OE_AS_INPUT   0x1
#define	AR7010_GPIO_IN   0x52004
#define	AR7010_GPIO_OUT   0x52008
#define	AR7010_GPIO_SET   0x5200C
#define	AR7010_GPIO_CLEAR   0x52010
#define	AR7010_GPIO_INT   0x52014
#define	AR7010_GPIO_INT_TYPE   0x52018
#define	AR7010_GPIO_INT_POLARITY   0x5201C
#define	AR7010_GPIO_PENDING   0x52020
#define	AR7010_GPIO_INT_MASK   0x52024
#define	AR7010_GPIO_FUNCTION   0x52028
#define	AR_GPIO_INTR_POL
#define	AR_GPIO_INTR_POL_VAL   0x0001FFFF
#define	AR_GPIO_INTR_POL_VAL_S   0
#define	AR_GPIO_INPUT_EN_VAL
#define	AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF   0x00000004
#define	AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S   2
#define	AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF   0x00000008
#define	AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S   3
#define	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF   0x00000010
#define	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S   4
#define	AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF   0x00000080
#define	AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S   7
#define	AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB   0x00000400
#define	AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S   10
#define	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB   0x00001000
#define	AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S   12
#define	AR_GPIO_INPUT_EN_VAL_RFSILENT_BB   0x00008000
#define	AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S   15
#define	AR_GPIO_RTC_RESET_OVERRIDE_ENABLE   0x00010000
#define	AR_GPIO_JTAG_DISABLE   0x00020000
#define	AR_GPIO_INPUT_MUX1
#define	AR_GPIO_INPUT_MUX1_BT_ACTIVE   0x000f0000
#define	AR_GPIO_INPUT_MUX1_BT_ACTIVE_S   16
#define	AR_GPIO_INPUT_MUX1_BT_PRIORITY   0x00000f00
#define	AR_GPIO_INPUT_MUX1_BT_PRIORITY_S   8
#define	AR_GPIO_INPUT_MUX2
#define	AR_GPIO_INPUT_MUX2_CLK25   0x0000000f
#define	AR_GPIO_INPUT_MUX2_CLK25_S   0
#define	AR_GPIO_INPUT_MUX2_RFSILENT   0x000000f0
#define	AR_GPIO_INPUT_MUX2_RFSILENT_S   4
#define	AR_GPIO_INPUT_MUX2_RTC_RESET   0x00000f00
#define	AR_GPIO_INPUT_MUX2_RTC_RESET_S   8
#define	AR_GPIO_OUTPUT_MUX1
#define	AR_GPIO_OUTPUT_MUX2
#define	AR_GPIO_OUTPUT_MUX3
#define	AR_INPUT_STATE
#define	AR_EEPROM_STATUS_DATA
#define	AR_EEPROM_STATUS_DATA_VAL   0x0000ffff
#define	AR_EEPROM_STATUS_DATA_VAL_S   0
#define	AR_EEPROM_STATUS_DATA_BUSY   0x00010000
#define	AR_EEPROM_STATUS_DATA_BUSY_ACCESS   0x00020000
#define	AR_EEPROM_STATUS_DATA_PROT_ACCESS   0x00040000
#define	AR_EEPROM_STATUS_DATA_ABSENT_ACCESS   0x00080000
#define	AR_OBS
#define	AR_GPIO_PDPU   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
#define	AR_PCIE_MSI
#define	AR_PCIE_MSI_ENABLE   0x00000001
#define	AR_INTR_PRIO_SYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
#define	AR_INTR_PRIO_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
#define	AR_INTR_PRIO_SYNC_MASK   (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
#define	AR_INTR_PRIO_ASYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
#define	AR_ENT_OTP   0x40d8
#define	AR_ENT_OTP_CHAIN2_DISABLE   0x00020000
#define	AR_ENT_OTP_MPSD   0x00800000
#define	AR_CH0_BB_DPLL1   0x16180
#define	AR_CH0_BB_DPLL1_REFDIV   0xF8000000
#define	AR_CH0_BB_DPLL1_REFDIV_S   27
#define	AR_CH0_BB_DPLL1_NINI   0x07FC0000
#define	AR_CH0_BB_DPLL1_NINI_S   18
#define	AR_CH0_BB_DPLL1_NFRAC   0x0003FFFF
#define	AR_CH0_BB_DPLL1_NFRAC_S   0
#define	AR_CH0_BB_DPLL2   0x16184
#define	AR_CH0_BB_DPLL2_LOCAL_PLL   0x40000000
#define	AR_CH0_BB_DPLL2_LOCAL_PLL_S   30
#define	AR_CH0_DPLL2_KI   0x3C000000
#define	AR_CH0_DPLL2_KI_S   26
#define	AR_CH0_DPLL2_KD   0x03F80000
#define	AR_CH0_DPLL2_KD_S   19
#define	AR_CH0_BB_DPLL2_EN_NEGTRIG   0x00040000
#define	AR_CH0_BB_DPLL2_EN_NEGTRIG_S   18
#define	AR_CH0_BB_DPLL2_PLL_PWD   0x00010000
#define	AR_CH0_BB_DPLL2_PLL_PWD_S   16
#define	AR_CH0_BB_DPLL2_OUTDIV   0x0000E000
#define	AR_CH0_BB_DPLL2_OUTDIV_S   13
#define	AR_CH0_BB_DPLL3   0x16188
#define	AR_CH0_BB_DPLL3_PHASE_SHIFT   0x3F800000
#define	AR_CH0_BB_DPLL3_PHASE_SHIFT_S   23
#define	AR_CH0_DDR_DPLL2   0x16244
#define	AR_CH0_DDR_DPLL3   0x16248
#define	AR_CH0_DPLL3_PHASE_SHIFT   0x3F800000
#define	AR_CH0_DPLL3_PHASE_SHIFT_S   23
#define	AR_PHY_CCA_NOM_VAL_2GHZ   -118
#define	AR_RTC_9300_PLL_DIV   0x000003ff
#define	AR_RTC_9300_PLL_DIV_S   0
#define	AR_RTC_9300_PLL_REFDIV   0x00003C00
#define	AR_RTC_9300_PLL_REFDIV_S   10
#define	AR_RTC_9300_PLL_CLKSEL   0x0000C000
#define	AR_RTC_9300_PLL_CLKSEL_S   14
#define	AR_RTC_9160_PLL_DIV   0x000003ff
#define	AR_RTC_9160_PLL_DIV_S   0
#define	AR_RTC_9160_PLL_REFDIV   0x00003C00
#define	AR_RTC_9160_PLL_REFDIV_S   10
#define	AR_RTC_9160_PLL_CLKSEL   0x0000C000
#define	AR_RTC_9160_PLL_CLKSEL_S   14
#define	AR_RTC_BASE   0x00020000
#define	AR_RTC_RC    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
#define	AR_RTC_RC_M   0x00000003
#define	AR_RTC_RC_MAC_WARM   0x00000001
#define	AR_RTC_RC_MAC_COLD   0x00000002
#define	AR_RTC_RC_COLD_RESET   0x00000004
#define	AR_RTC_RC_WARM_RESET   0x00000008
#define	AR_RTC_XTAL_CONTROL   0x7004
#define	AR_RTC_REG_CONTROL0   0x7008
#define	AR_RTC_REG_CONTROL1   0x700c
#define	AR_RTC_REG_CONTROL1_SWREG_PROGRAM   0x00000001
#define	AR_RTC_PLL_CONTROL    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
#define	AR_RTC_PLL_CONTROL2   0x703c
#define	AR_RTC_PLL_DIV   0x0000001f
#define	AR_RTC_PLL_DIV_S   0
#define	AR_RTC_PLL_DIV2   0x00000020
#define	AR_RTC_PLL_REFDIV_5   0x000000c0
#define	AR_RTC_PLL_CLKSEL   0x00000300
#define	AR_RTC_PLL_CLKSEL_S   8
#define	AR_RTC_PLL_BYPASS   0x00010000
#define	PLL3   0x16188
#define	PLL3_DO_MEAS_MASK   0x40000000
#define	PLL4   0x1618c
#define	PLL4_MEAS_DONE   0x8
#define	SQSUM_DVC_MASK   0x007ffff8
#define	AR_RTC_RESET    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
#define	AR_RTC_RESET_EN   (0x00000001)
#define	AR_RTC_STATUS    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
#define	AR_RTC_STATUS_M    ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)
#define	AR_RTC_PM_STATUS_M   0x0000000f
#define	AR_RTC_STATUS_SHUTDOWN   0x00000001
#define	AR_RTC_STATUS_ON   0x00000002
#define	AR_RTC_STATUS_SLEEP   0x00000004
#define	AR_RTC_STATUS_WAKEUP   0x00000008
#define	AR_RTC_SLEEP_CLK    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
#define	AR_RTC_FORCE_DERIVED_CLK   0x2
#define	AR_RTC_FORCE_SWREG_PRD   0x00000004
#define	AR_RTC_FORCE_WAKE    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
#define	AR_RTC_FORCE_WAKE_EN   0x00000001
#define	AR_RTC_FORCE_WAKE_ON_INT   0x00000002
#define	AR_RTC_INTR_CAUSE    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)
#define	AR_RTC_INTR_ENABLE    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)
#define	AR_RTC_INTR_MASK    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
#define	AR_RTC_DERIVED_CLK    (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
#define	AR_RTC_DERIVED_CLK_PERIOD   0x0000fffe
#define	AR_RTC_DERIVED_CLK_PERIOD_S   1
#define	AR_SEQ_MASK   0x8060
#define	AR_AN_RF2G1_CH0   0x7810
#define	AR_AN_RF2G1_CH0_OB   0x03800000
#define	AR_AN_RF2G1_CH0_OB_S   23
#define	AR_AN_RF2G1_CH0_DB   0x1C000000
#define	AR_AN_RF2G1_CH0_DB_S   26
#define	AR_AN_RF5G1_CH0   0x7818
#define	AR_AN_RF5G1_CH0_OB5   0x00070000
#define	AR_AN_RF5G1_CH0_OB5_S   16
#define	AR_AN_RF5G1_CH0_DB5   0x00380000
#define	AR_AN_RF5G1_CH0_DB5_S   19
#define	AR_AN_RF2G1_CH1   0x7834
#define	AR_AN_RF2G1_CH1_OB   0x03800000
#define	AR_AN_RF2G1_CH1_OB_S   23
#define	AR_AN_RF2G1_CH1_DB   0x1C000000
#define	AR_AN_RF2G1_CH1_DB_S   26
#define	AR_AN_RF5G1_CH1   0x783C
#define	AR_AN_RF5G1_CH1_OB5   0x00070000
#define	AR_AN_RF5G1_CH1_OB5_S   16
#define	AR_AN_RF5G1_CH1_DB5   0x00380000
#define	AR_AN_RF5G1_CH1_DB5_S   19
#define	AR_AN_TOP1   0x7890
#define	AR_AN_TOP1_DACIPMODE   0x00040000
#define	AR_AN_TOP1_DACIPMODE_S   18
#define	AR_AN_TOP2   0x7894
#define	AR_AN_TOP2_XPABIAS_LVL   0xC0000000
#define	AR_AN_TOP2_XPABIAS_LVL_S   30
#define	AR_AN_TOP2_LOCALBIAS   0x00200000
#define	AR_AN_TOP2_LOCALBIAS_S   21
#define	AR_AN_TOP2_PWDCLKIND   0x00400000
#define	AR_AN_TOP2_PWDCLKIND_S   22
#define	AR_AN_SYNTH9   0x7868
#define	AR_AN_SYNTH9_REFDIVA   0xf8000000
#define	AR_AN_SYNTH9_REFDIVA_S   27
#define	AR9285_AN_RF2G1   0x7820
#define	AR9285_AN_RF2G1_ENPACAL   0x00000800
#define	AR9285_AN_RF2G1_ENPACAL_S   11
#define	AR9285_AN_RF2G1_PDPADRV1   0x02000000
#define	AR9285_AN_RF2G1_PDPADRV1_S   25
#define	AR9285_AN_RF2G1_PDPADRV2   0x01000000
#define	AR9285_AN_RF2G1_PDPADRV2_S   24
#define	AR9285_AN_RF2G1_PDPAOUT   0x00800000
#define	AR9285_AN_RF2G1_PDPAOUT_S   23
#define	AR9285_AN_RF2G2   0x7824
#define	AR9285_AN_RF2G2_OFFCAL   0x00001000
#define	AR9285_AN_RF2G2_OFFCAL_S   12
#define	AR9285_AN_RF2G3   0x7828
#define	AR9285_AN_RF2G3_PDVCCOMP   0x02000000
#define	AR9285_AN_RF2G3_PDVCCOMP_S   25
#define	AR9285_AN_RF2G3_OB_0   0x00E00000
#define	AR9285_AN_RF2G3_OB_0_S   21
#define	AR9285_AN_RF2G3_OB_1   0x001C0000
#define	AR9285_AN_RF2G3_OB_1_S   18
#define	AR9285_AN_RF2G3_OB_2   0x00038000
#define	AR9285_AN_RF2G3_OB_2_S   15
#define	AR9285_AN_RF2G3_OB_3   0x00007000
#define	AR9285_AN_RF2G3_OB_3_S   12
#define	AR9285_AN_RF2G3_OB_4   0x00000E00
#define	AR9285_AN_RF2G3_OB_4_S   9
#define	AR9285_AN_RF2G3_DB1_0   0x000001C0
#define	AR9285_AN_RF2G3_DB1_0_S   6
#define	AR9285_AN_RF2G3_DB1_1   0x00000038
#define	AR9285_AN_RF2G3_DB1_1_S   3
#define	AR9285_AN_RF2G3_DB1_2   0x00000007
#define	AR9285_AN_RF2G3_DB1_2_S   0
#define	AR9285_AN_RF2G4   0x782C
#define	AR9285_AN_RF2G4_DB1_3   0xE0000000
#define	AR9285_AN_RF2G4_DB1_3_S   29
#define	AR9285_AN_RF2G4_DB1_4   0x1C000000
#define	AR9285_AN_RF2G4_DB1_4_S   26
#define	AR9285_AN_RF2G4_DB2_0   0x03800000
#define	AR9285_AN_RF2G4_DB2_0_S   23
#define	AR9285_AN_RF2G4_DB2_1   0x00700000
#define	AR9285_AN_RF2G4_DB2_1_S   20
#define	AR9285_AN_RF2G4_DB2_2   0x000E0000
#define	AR9285_AN_RF2G4_DB2_2_S   17
#define	AR9285_AN_RF2G4_DB2_3   0x0001C000
#define	AR9285_AN_RF2G4_DB2_3_S   14
#define	AR9285_AN_RF2G4_DB2_4   0x00003800
#define	AR9285_AN_RF2G4_DB2_4_S   11
#define	AR9285_RF2G5   0x7830
#define	AR9285_RF2G5_IC50TX   0xfffff8ff
#define	AR9285_RF2G5_IC50TX_SET   0x00000400
#define	AR9285_RF2G5_IC50TX_XE_SET   0x00000500
#define	AR9285_RF2G5_IC50TX_CLEAR   0x00000700
#define	AR9285_RF2G5_IC50TX_CLEAR_S   8
#define	AR9271_AN_RF2G3_OB_cck   0x001C0000
#define	AR9271_AN_RF2G3_OB_cck_S   18
#define	AR9271_AN_RF2G3_OB_psk   0x00038000
#define	AR9271_AN_RF2G3_OB_psk_S   15
#define	AR9271_AN_RF2G3_OB_qam   0x00007000
#define	AR9271_AN_RF2G3_OB_qam_S   12
#define	AR9271_AN_RF2G3_DB_1   0x00E00000
#define	AR9271_AN_RF2G3_DB_1_S   21
#define	AR9271_AN_RF2G3_CCOMP   0xFFF
#define	AR9271_AN_RF2G3_CCOMP_S   0
#define	AR9271_AN_RF2G4_DB_2   0xE0000000
#define	AR9271_AN_RF2G4_DB_2_S   29
#define	AR9285_AN_RF2G6   0x7834
#define	AR9285_AN_RF2G6_CCOMP   0x00007800
#define	AR9285_AN_RF2G6_CCOMP_S   11
#define	AR9285_AN_RF2G6_OFFS   0x03f00000
#define	AR9285_AN_RF2G6_OFFS_S   20
#define	AR9271_AN_RF2G6_OFFS   0x07f00000
#define	AR9271_AN_RF2G6_OFFS_S   20
#define	AR9285_AN_RF2G7   0x7838
#define	AR9285_AN_RF2G7_PWDDB   0x00000002
#define	AR9285_AN_RF2G7_PWDDB_S   1
#define	AR9285_AN_RF2G7_PADRVGN2TAB0   0xE0000000
#define	AR9285_AN_RF2G7_PADRVGN2TAB0_S   29
#define	AR9285_AN_RF2G8   0x783C
#define	AR9285_AN_RF2G8_PADRVGN2TAB0   0x0001C000
#define	AR9285_AN_RF2G8_PADRVGN2TAB0_S   14
#define	AR9285_AN_RF2G9   0x7840
#define	AR9285_AN_RXTXBB1   0x7854
#define	AR9285_AN_RXTXBB1_PDRXTXBB1   0x00000020
#define	AR9285_AN_RXTXBB1_PDRXTXBB1_S   5
#define	AR9285_AN_RXTXBB1_PDV2I   0x00000080
#define	AR9285_AN_RXTXBB1_PDV2I_S   7
#define	AR9285_AN_RXTXBB1_PDDACIF   0x00000100
#define	AR9285_AN_RXTXBB1_PDDACIF_S   8
#define	AR9285_AN_RXTXBB1_SPARE9   0x00000001
#define	AR9285_AN_RXTXBB1_SPARE9_S   0
#define	AR9285_AN_TOP2   0x7868
#define	AR9285_AN_TOP3   0x786c
#define	AR9285_AN_TOP3_XPABIAS_LVL   0x0000000C
#define	AR9285_AN_TOP3_XPABIAS_LVL_S   2
#define	AR9285_AN_TOP3_PWDDAC   0x00800000
#define	AR9285_AN_TOP3_PWDDAC_S   23
#define	AR9285_AN_TOP4   0x7870
#define	AR9285_AN_TOP4_DEFAULT   0x10142c00
#define	AR9287_AN_RF2G3_CH0   0x7808
#define	AR9287_AN_RF2G3_CH1   0x785c
#define	AR9287_AN_RF2G3_DB1   0xE0000000
#define	AR9287_AN_RF2G3_DB1_S   29
#define	AR9287_AN_RF2G3_DB2   0x1C000000
#define	AR9287_AN_RF2G3_DB2_S   26
#define	AR9287_AN_RF2G3_OB_CCK   0x03800000
#define	AR9287_AN_RF2G3_OB_CCK_S   23
#define	AR9287_AN_RF2G3_OB_PSK   0x00700000
#define	AR9287_AN_RF2G3_OB_PSK_S   20
#define	AR9287_AN_RF2G3_OB_QAM   0x000E0000
#define	AR9287_AN_RF2G3_OB_QAM_S   17
#define	AR9287_AN_RF2G3_OB_PAL_OFF   0x0001C000
#define	AR9287_AN_RF2G3_OB_PAL_OFF_S   14
#define	AR9287_AN_TXPC0   0x7898
#define	AR9287_AN_TXPC0_TXPCMODE   0x0000C000
#define	AR9287_AN_TXPC0_TXPCMODE_S   14
#define	AR9287_AN_TXPC0_TXPCMODE_NORMAL   0
#define	AR9287_AN_TXPC0_TXPCMODE_TEST   1
#define	AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE   2
#define	AR9287_AN_TXPC0_TXPCMODE_ATBTEST   3
#define	AR9287_AN_TOP2   0x78b4
#define	AR9287_AN_TOP2_XPABIAS_LVL   0xC0000000
#define	AR9287_AN_TOP2_XPABIAS_LVL_S   30
#define	AR9271_RESET_POWER_DOWN_CONTROL   0x50044
#define	AR9271_RADIO_RF_RST   0x20
#define	AR9271_GATE_MAC_CTL   0x4000
#define	AR_STA_ID0   0x8000
#define	AR_STA_ID1   0x8004
#define	AR_STA_ID1_SADH_MASK   0x0000FFFF
#define	AR_STA_ID1_STA_AP   0x00010000
#define	AR_STA_ID1_ADHOC   0x00020000
#define	AR_STA_ID1_PWR_SAV   0x00040000
#define	AR_STA_ID1_KSRCHDIS   0x00080000
#define	AR_STA_ID1_PCF   0x00100000
#define	AR_STA_ID1_USE_DEFANT   0x00200000
#define	AR_STA_ID1_DEFANT_UPDATE   0x00400000
#define	AR_STA_ID1_AR9100_BA_FIX   0x00400000
#define	AR_STA_ID1_RTS_USE_DEF   0x00800000
#define	AR_STA_ID1_ACKCTS_6MB   0x01000000
#define	AR_STA_ID1_BASE_RATE_11B   0x02000000
#define	AR_STA_ID1_SECTOR_SELF_GEN   0x04000000
#define	AR_STA_ID1_CRPT_MIC_ENABLE   0x08000000
#define	AR_STA_ID1_KSRCH_MODE   0x10000000
#define	AR_STA_ID1_PRESERVE_SEQNUM   0x20000000
#define	AR_STA_ID1_CBCIV_ENDIAN   0x40000000
#define	AR_STA_ID1_MCAST_KSRCH   0x80000000
#define	AR_BSS_ID0   0x8008
#define	AR_BSS_ID1   0x800C
#define	AR_BSS_ID1_U16   0x0000FFFF
#define	AR_BSS_ID1_AID   0x07FF0000
#define	AR_BSS_ID1_AID_S   16
#define	AR_BCN_RSSI_AVE   0x8010
#define	AR_BCN_RSSI_AVE_MASK   0x00000FFF
#define	AR_TIME_OUT   0x8014
#define	AR_TIME_OUT_ACK   0x00003FFF
#define	AR_TIME_OUT_ACK_S   0
#define	AR_TIME_OUT_CTS   0x3FFF0000
#define	AR_TIME_OUT_CTS_S   16
#define	AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR   0x16001D56
#define	AR_RSSI_THR   0x8018
#define	AR_RSSI_THR_MASK   0x000000FF
#define	AR_RSSI_THR_BM_THR   0x0000FF00
#define	AR_RSSI_THR_BM_THR_S   8
#define	AR_RSSI_BCN_WEIGHT   0x1F000000
#define	AR_RSSI_BCN_WEIGHT_S   24
#define	AR_RSSI_BCN_RSSI_RST   0x20000000
#define	AR_USEC   0x801c
#define	AR_USEC_USEC   0x0000007F
#define	AR_USEC_TX_LAT   0x007FC000
#define	AR_USEC_TX_LAT_S   14
#define	AR_USEC_RX_LAT   0x1F800000
#define	AR_USEC_RX_LAT_S   23
#define	AR_USEC_ASYNC_FIFO_DUR   0x12e00074
#define	AR_RESET_TSF   0x8020
#define	AR_RESET_TSF_ONCE   0x01000000
#define	AR_MAX_CFP_DUR   0x8038
#define	AR_CFP_VAL   0x0000FFFF
#define	AR_RX_FILTER   0x803C
#define	AR_MCAST_FIL0   0x8040
#define	AR_MCAST_FIL1   0x8044
#define	AR_DIAG_SW   0x8048
#define	AR_DIAG_CACHE_ACK   0x00000001
#define	AR_DIAG_ACK_DIS   0x00000002
#define	AR_DIAG_CTS_DIS   0x00000004
#define	AR_DIAG_ENCRYPT_DIS   0x00000008
#define	AR_DIAG_DECRYPT_DIS   0x00000010
#define	AR_DIAG_RX_DIS   0x00000020 /* RX block */
#define	AR_DIAG_LOOP_BACK   0x00000040
#define	AR_DIAG_CORR_FCS   0x00000080
#define	AR_DIAG_CHAN_INFO   0x00000100
#define	AR_DIAG_SCRAM_SEED   0x0001FE00
#define	AR_DIAG_SCRAM_SEED_S   8
#define	AR_DIAG_FRAME_NV0   0x00020000
#define	AR_DIAG_OBS_PT_SEL1   0x000C0000
#define	AR_DIAG_OBS_PT_SEL1_S   18
#define	AR_DIAG_FORCE_RX_CLEAR   0x00100000 /* force rx_clear high */
#define	AR_DIAG_IGNORE_VIRT_CS   0x00200000
#define	AR_DIAG_FORCE_CH_IDLE_HIGH   0x00400000
#define	AR_DIAG_EIFS_CTRL_ENA   0x00800000
#define	AR_DIAG_DUAL_CHAIN_INFO   0x01000000
#define	AR_DIAG_RX_ABORT   0x02000000 /* Force RX abort */
#define	AR_DIAG_SATURATE_CYCLE_CNT   0x04000000
#define	AR_DIAG_OBS_PT_SEL2   0x08000000
#define	AR_DIAG_RX_CLEAR_CTL_LOW   0x10000000
#define	AR_DIAG_RX_CLEAR_EXT_LOW   0x20000000
#define	AR_TSF_L32   0x804c
#define	AR_TSF_U32   0x8050
#define	AR_TST_ADDAC   0x8054
#define	AR_DEF_ANTENNA   0x8058
#define	AR_AES_MUTE_MASK0   0x805c
#define	AR_AES_MUTE_MASK0_FC   0x0000FFFF
#define	AR_AES_MUTE_MASK0_QOS   0xFFFF0000
#define	AR_AES_MUTE_MASK0_QOS_S   16
#define	AR_AES_MUTE_MASK1   0x8060
#define	AR_AES_MUTE_MASK1_SEQ   0x0000FFFF
#define	AR_AES_MUTE_MASK1_FC_MGMT   0xFFFF0000
#define	AR_AES_MUTE_MASK1_FC_MGMT_S   16
#define	AR_GATED_CLKS   0x8064
#define	AR_GATED_CLKS_TX   0x00000002
#define	AR_GATED_CLKS_RX   0x00000004
#define	AR_GATED_CLKS_REG   0x00000008
#define	AR_OBS_BUS_CTRL   0x8068
#define	AR_OBS_BUS_SEL_1   0x00040000
#define	AR_OBS_BUS_SEL_2   0x00080000
#define	AR_OBS_BUS_SEL_3   0x000C0000
#define	AR_OBS_BUS_SEL_4   0x08040000
#define	AR_OBS_BUS_SEL_5   0x08080000
#define	AR_OBS_BUS_1   0x806c
#define	AR_OBS_BUS_1_PCU   0x00000001
#define	AR_OBS_BUS_1_RX_END   0x00000002
#define	AR_OBS_BUS_1_RX_WEP   0x00000004
#define	AR_OBS_BUS_1_RX_BEACON   0x00000008
#define	AR_OBS_BUS_1_RX_FILTER   0x00000010
#define	AR_OBS_BUS_1_TX_HCF   0x00000020
#define	AR_OBS_BUS_1_QUIET_TIME   0x00000040
#define	AR_OBS_BUS_1_CHAN_IDLE   0x00000080
#define	AR_OBS_BUS_1_TX_HOLD   0x00000100
#define	AR_OBS_BUS_1_TX_FRAME   0x00000200
#define	AR_OBS_BUS_1_RX_FRAME   0x00000400
#define	AR_OBS_BUS_1_RX_CLEAR   0x00000800
#define	AR_OBS_BUS_1_WEP_STATE   0x0003F000
#define	AR_OBS_BUS_1_WEP_STATE_S   12
#define	AR_OBS_BUS_1_RX_STATE   0x01F00000
#define	AR_OBS_BUS_1_RX_STATE_S   20
#define	AR_OBS_BUS_1_TX_STATE   0x7E000000
#define	AR_OBS_BUS_1_TX_STATE_S   25
#define	AR_LAST_TSTP   0x8080
#define	AR_NAV   0x8084
#define	AR_RTS_OK   0x8088
#define	AR_RTS_FAIL   0x808c
#define	AR_ACK_FAIL   0x8090
#define	AR_FCS_FAIL   0x8094
#define	AR_BEACON_CNT   0x8098
#define	AR_SLEEP1   0x80d4
#define	AR_SLEEP1_ASSUME_DTIM   0x00080000
#define	AR_SLEEP1_CAB_TIMEOUT   0xFFE00000
#define	AR_SLEEP1_CAB_TIMEOUT_S   21
#define	AR_SLEEP2   0x80d8
#define	AR_SLEEP2_BEACON_TIMEOUT   0xFFE00000
#define	AR_SLEEP2_BEACON_TIMEOUT_S   21
#define	AR_TPC   0x80e8
#define	AR_TPC_ACK   0x0000003f
#define	AR_TPC_ACK_S   0x00
#define	AR_TPC_CTS   0x00003f00
#define	AR_TPC_CTS_S   0x08
#define	AR_TPC_CHIRP   0x003f0000
#define	AR_TPC_CHIRP_S   0x16
#define	AR_QUIET1   0x80fc
#define	AR_QUIET1_NEXT_QUIET_S   0
#define	AR_QUIET1_NEXT_QUIET_M   0x0000ffff
#define	AR_QUIET1_QUIET_ENABLE   0x00010000
#define	AR_QUIET1_QUIET_ACK_CTS_ENABLE   0x00020000
#define	AR_QUIET1_QUIET_ACK_CTS_ENABLE_S   17
#define	AR_QUIET2   0x8100
#define	AR_QUIET2_QUIET_PERIOD_S   0
#define	AR_QUIET2_QUIET_PERIOD_M   0x0000ffff
#define	AR_QUIET2_QUIET_DUR_S   16
#define	AR_QUIET2_QUIET_DUR   0xffff0000
#define	AR_TSF_PARM   0x8104
#define	AR_TSF_INCREMENT_M   0x000000ff
#define	AR_TSF_INCREMENT_S   0x00
#define	AR_QOS_NO_ACK   0x8108
#define	AR_QOS_NO_ACK_TWO_BIT   0x0000000f
#define	AR_QOS_NO_ACK_TWO_BIT_S   0
#define	AR_QOS_NO_ACK_BIT_OFF   0x00000070
#define	AR_QOS_NO_ACK_BIT_OFF_S   4
#define	AR_QOS_NO_ACK_BYTE_OFF   0x00000180
#define	AR_QOS_NO_ACK_BYTE_OFF_S   7
#define	AR_PHY_ERR   0x810c
#define	AR_PHY_ERR_DCHIRP   0x00000008
#define	AR_PHY_ERR_RADAR   0x00000020
#define	AR_PHY_ERR_OFDM_TIMING   0x00020000
#define	AR_PHY_ERR_CCK_TIMING   0x02000000
#define	AR_RXFIFO_CFG   0x8114
#define	AR_MIC_QOS_CONTROL   0x8118
#define	AR_MIC_QOS_SELECT   0x811c
#define	AR_PCU_MISC   0x8120
#define	AR_PCU_FORCE_BSSID_MATCH   0x00000001
#define	AR_PCU_MIC_NEW_LOC_ENA   0x00000004
#define	AR_PCU_TX_ADD_TSF   0x00000008
#define	AR_PCU_CCK_SIFS_MODE   0x00000010
#define	AR_PCU_RX_ANT_UPDT   0x00000800
#define	AR_PCU_TXOP_TBTT_LIMIT_ENA   0x00001000
#define	AR_PCU_MISS_BCN_IN_SLEEP   0x00004000
#define	AR_PCU_BUG_12306_FIX_ENA   0x00020000
#define	AR_PCU_FORCE_QUIET_COLL   0x00040000
#define	AR_PCU_TBTT_PROTECT   0x00200000
#define	AR_PCU_CLEAR_VMF   0x01000000
#define	AR_PCU_CLEAR_BA_VALID   0x04000000
#define	AR_PCU_ALWAYS_PERFORM_KEYSEARCH   0x10000000
#define	AR_PCU_BT_ANT_PREVENT_RX   0x00100000
#define	AR_PCU_BT_ANT_PREVENT_RX_S   20
#define	AR_FILT_OFDM   0x8124
#define	AR_FILT_OFDM_COUNT   0x00FFFFFF
#define	AR_FILT_CCK   0x8128
#define	AR_FILT_CCK_COUNT   0x00FFFFFF
#define	AR_PHY_ERR_1   0x812c
#define	AR_PHY_ERR_1_COUNT   0x00FFFFFF
#define	AR_PHY_ERR_MASK_1   0x8130
#define	AR_PHY_ERR_2   0x8134
#define	AR_PHY_ERR_2_COUNT   0x00FFFFFF
#define	AR_PHY_ERR_MASK_2   0x8138
#define	AR_PHY_COUNTMAX   (3 << 22)
#define	AR_MIBCNT_INTRMASK   (3 << 22)
#define	AR_TSFOOR_THRESHOLD   0x813c
#define	AR_TSFOOR_THRESHOLD_VAL   0x0000FFFF
#define	AR_PHY_ERR_EIFS_MASK   0x8144
#define	AR_PHY_ERR_3   0x8168
#define	AR_PHY_ERR_3_COUNT   0x00FFFFFF
#define	AR_PHY_ERR_MASK_3   0x816c
#define	AR_BT_COEX_MODE   0x8170
#define	AR_BT_TIME_EXTEND   0x000000ff
#define	AR_BT_TIME_EXTEND_S   0
#define	AR_BT_TXSTATE_EXTEND   0x00000100
#define	AR_BT_TXSTATE_EXTEND_S   8
#define	AR_BT_TX_FRAME_EXTEND   0x00000200
#define	AR_BT_TX_FRAME_EXTEND_S   9
#define	AR_BT_MODE   0x00000c00
#define	AR_BT_MODE_S   10
#define	AR_BT_QUIET   0x00001000
#define	AR_BT_QUIET_S   12
#define	AR_BT_QCU_THRESH   0x0001e000
#define	AR_BT_QCU_THRESH_S   13
#define	AR_BT_RX_CLEAR_POLARITY   0x00020000
#define	AR_BT_RX_CLEAR_POLARITY_S   17
#define	AR_BT_PRIORITY_TIME   0x00fc0000
#define	AR_BT_PRIORITY_TIME_S   18
#define	AR_BT_FIRST_SLOT_TIME   0xff000000
#define	AR_BT_FIRST_SLOT_TIME_S   24
#define	AR_BT_COEX_WEIGHT   0x8174
#define	AR_BT_COEX_WGHT   0xff55
#define	AR_STOMP_ALL_WLAN_WGHT   0xfcfc
#define	AR_STOMP_LOW_WLAN_WGHT   0xa8a8
#define	AR_STOMP_NONE_WLAN_WGHT   0x0000
#define	AR_BTCOEX_BT_WGHT   0x0000ffff
#define	AR_BTCOEX_BT_WGHT_S   0
#define	AR_BTCOEX_WL_WGHT   0xffff0000
#define	AR_BTCOEX_WL_WGHT_S   16
#define	AR_BT_COEX_WL_WEIGHTS0   0x8174
#define	AR_BT_COEX_WL_WEIGHTS1   0x81c4
#define	AR_BT_COEX_BT_WEIGHTS0   0x83ac
#define	AR_BT_COEX_BT_WEIGHTS1   0x83b0
#define	AR_BT_COEX_BT_WEIGHTS2   0x83b4
#define	AR_BT_COEX_BT_WEIGHTS3   0x83b8
#define	AR9300_BT_WGHT   0xcccc4444
#define	AR9300_STOMP_ALL_WLAN_WGHT0   0xfffffff0
#define	AR9300_STOMP_ALL_WLAN_WGHT1   0xfffffff0
#define	AR9300_STOMP_LOW_WLAN_WGHT0   0x88888880
#define	AR9300_STOMP_LOW_WLAN_WGHT1   0x88888880
#define	AR9300_STOMP_NONE_WLAN_WGHT0   0x00000000
#define	AR9300_STOMP_NONE_WLAN_WGHT1   0x00000000
#define	AR_BT_COEX_MODE2   0x817c
#define	AR_BT_BCN_MISS_THRESH   0x000000ff
#define	AR_BT_BCN_MISS_THRESH_S   0
#define	AR_BT_BCN_MISS_CNT   0x0000ff00
#define	AR_BT_BCN_MISS_CNT_S   8
#define	AR_BT_HOLD_RX_CLEAR   0x00010000
#define	AR_BT_HOLD_RX_CLEAR_S   16
#define	AR_BT_DISABLE_BT_ANT   0x00100000
#define	AR_BT_DISABLE_BT_ANT_S   20
#define	AR_TXSIFS   0x81d0
#define	AR_TXSIFS_TIME   0x000000FF
#define	AR_TXSIFS_TX_LATENCY   0x00000F00
#define	AR_TXSIFS_TX_LATENCY_S   8
#define	AR_TXSIFS_ACK_SHIFT   0x00007000
#define	AR_TXSIFS_ACK_SHIFT_S   12
#define	AR_TXOP_X   0x81ec
#define	AR_TXOP_X_VAL   0x000000FF
#define	AR_TXOP_0_3   0x81f0
#define	AR_TXOP_4_7   0x81f4
#define	AR_TXOP_8_11   0x81f8
#define	AR_TXOP_12_15   0x81fc
#define	AR_NEXT_NDP2_TIMER   0x8180
#define	AR_FIRST_NDP_TIMER   7
#define	AR_NDP2_PERIOD   0x81a0
#define	AR_NDP2_TIMER_MODE   0x81c0
#define	AR_GEN_TIMERS(_i)
#define	AR_NEXT_TBTT_TIMER   AR_GEN_TIMERS(0)
#define	AR_NEXT_DMA_BEACON_ALERT   AR_GEN_TIMERS(1)
#define	AR_NEXT_SWBA   AR_GEN_TIMERS(2)
#define	AR_NEXT_CFP   AR_GEN_TIMERS(2)
#define	AR_NEXT_HCF   AR_GEN_TIMERS(3)
#define	AR_NEXT_TIM   AR_GEN_TIMERS(4)
#define	AR_NEXT_DTIM   AR_GEN_TIMERS(5)
#define	AR_NEXT_QUIET_TIMER   AR_GEN_TIMERS(6)
#define	AR_NEXT_NDP_TIMER   AR_GEN_TIMERS(7)
#define	AR_BEACON_PERIOD   AR_GEN_TIMERS(8)
#define	AR_DMA_BEACON_PERIOD   AR_GEN_TIMERS(9)
#define	AR_SWBA_PERIOD   AR_GEN_TIMERS(10)
#define	AR_HCF_PERIOD   AR_GEN_TIMERS(11)
#define	AR_TIM_PERIOD   AR_GEN_TIMERS(12)
#define	AR_DTIM_PERIOD   AR_GEN_TIMERS(13)
#define	AR_QUIET_PERIOD   AR_GEN_TIMERS(14)
#define	AR_NDP_PERIOD   AR_GEN_TIMERS(15)
#define	AR_TIMER_MODE   0x8240
#define	AR_TBTT_TIMER_EN   0x00000001
#define	AR_DBA_TIMER_EN   0x00000002
#define	AR_SWBA_TIMER_EN   0x00000004
#define	AR_HCF_TIMER_EN   0x00000008
#define	AR_TIM_TIMER_EN   0x00000010
#define	AR_DTIM_TIMER_EN   0x00000020
#define	AR_QUIET_TIMER_EN   0x00000040
#define	AR_NDP_TIMER_EN   0x00000080
#define	AR_TIMER_OVERFLOW_INDEX   0x00000700
#define	AR_TIMER_OVERFLOW_INDEX_S   8
#define	AR_TIMER_THRESH   0xFFFFF000
#define	AR_TIMER_THRESH_S   12
#define	AR_SLP32_MODE   0x8244
#define	AR_SLP32_HALF_CLK_LATENCY   0x000FFFFF
#define	AR_SLP32_ENA   0x00100000
#define	AR_SLP32_TSF_WRITE_STATUS   0x00200000
#define	AR_SLP32_WAKE   0x8248
#define	AR_SLP32_WAKE_XTL_TIME   0x0000FFFF
#define	AR_SLP32_INC   0x824c
#define	AR_SLP32_TST_INC   0x000FFFFF
#define	AR_SLP_CNT   0x8250
#define	AR_SLP_CYCLE_CNT   0x8254
#define	AR_SLP_MIB_CTRL   0x8258
#define	AR_SLP_MIB_CLEAR   0x00000001
#define	AR_SLP_MIB_PENDING   0x00000002
#define	AR_MAC_PCU_LOGIC_ANALYZER   0x8264
#define	AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768   0x20000000
#define	AR_2040_MODE   0x8318
#define	AR_2040_JOINED_RX_CLEAR   0x00000001
#define	AR_EXTRCCNT   0x8328
#define	AR_SELFGEN_MASK   0x832c
#define	AR_PCU_TXBUF_CTRL   0x8340
#define	AR_PCU_TXBUF_CTRL_SIZE_MASK   0x7FF
#define	AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
#define	AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380
#define	AR_PCU_MISC_MODE2   0x8344
#define	AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE   0x00000002
#define	AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT   0x00000004
#define	AR_PCU_MISC_MODE2_RESERVED   0x00000038
#define	AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE   0x00000040
#define	AR_PCU_MISC_MODE2_CFP_IGNORE   0x00000080
#define	AR_PCU_MISC_MODE2_MGMT_QOS   0x0000FF00
#define	AR_PCU_MISC_MODE2_MGMT_QOS_S   8
#define	AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION   0x00010000
#define	AR_PCU_MISC_MODE2_ENABLE_AGGWEP   0x00020000
#define	AR_PCU_MISC_MODE2_HWWAR1   0x00100000
#define	AR_PCU_MISC_MODE2_HWWAR2   0x02000000
#define	AR_PCU_MISC_MODE2_RESERVED2   0xFFFE0000
#define	AR_MAC_PCU_ASYNC_FIFO_REG3   0x8358
#define	AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL   0x00000400
#define	AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET   0x80000000
#define	AR_AES_MUTE_MASK0   0x805c
#define	AR_AES_MUTE_MASK0_FC   0x0000FFFF
#define	AR_AES_MUTE_MASK0_QOS   0xFFFF0000
#define	AR_AES_MUTE_MASK0_QOS_S   16
#define	AR_AES_MUTE_MASK1   0x8060
#define	AR_AES_MUTE_MASK1_SEQ   0x0000FFFF
#define	AR_AES_MUTE_MASK1_SEQ_S   0
#define	AR_AES_MUTE_MASK1_FC_MGMT   0xFFFF0000
#define	AR_AES_MUTE_MASK1_FC_MGMT_S   16
#define	AR_RATE_DURATION_0   0x8700
#define	AR_RATE_DURATION_31   0x87CC
#define	AR_RATE_DURATION_32   0x8780
#define	AR_RATE_DURATION(_n)
#define	AR_KEYTABLE_0   0x8800
#define	AR_KEYTABLE(_n)
#define	AR_KEY_CACHE_SIZE   128
#define	AR_RSVD_KEYTABLE_ENTRIES   4
#define	AR_KEY_TYPE   0x00000007
#define	AR_KEYTABLE_TYPE_40   0x00000000
#define	AR_KEYTABLE_TYPE_104   0x00000001
#define	AR_KEYTABLE_TYPE_128   0x00000003
#define	AR_KEYTABLE_TYPE_TKIP   0x00000004
#define	AR_KEYTABLE_TYPE_AES   0x00000005
#define	AR_KEYTABLE_TYPE_CCM   0x00000006
#define	AR_KEYTABLE_TYPE_CLR   0x00000007
#define	AR_KEYTABLE_ANT   0x00000008
#define	AR_KEYTABLE_VALID   0x00008000
#define	AR_KEYTABLE_KEY0(_n)
#define	AR_KEYTABLE_KEY1(_n)
#define	AR_KEYTABLE_KEY2(_n)
#define	AR_KEYTABLE_KEY3(_n)
#define	AR_KEYTABLE_KEY4(_n)
#define	AR_KEYTABLE_TYPE(_n)
#define	AR_KEYTABLE_MAC0(_n)
#define	AR_KEYTABLE_MAC1(_n)
#define	AR9271_CORE_CLOCK   117 /* clock to 117Mhz */
#define	AR9271_TARGET_BAUD_RATE   19200 /* 115200 */
#define	AR_AGG_WEP_ENABLE_FIX   0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
#define	AR_ADHOC_MCAST_KEYID_ENABLE
#define	AR_AGG_WEP_ENABLE
#define	AR9300_SM_BASE   0xa200
#define	AR9002_PHY_AGC_CONTROL   0x9860
#define	AR9003_PHY_AGC_CONTROL   AR9300_SM_BASE + 0xc4
#define	AR_PHY_AGC_CONTROL   (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
#define	AR_PHY_AGC_CONTROL_CAL   0x00000001 /* do internal calibration */
#define	AR_PHY_AGC_CONTROL_NF   0x00000002 /* do noise-floor calibration */
#define	AR_PHY_AGC_CONTROL_OFFSET_CAL   0x00000800 /* allow offset calibration */
#define	AR_PHY_AGC_CONTROL_ENABLE_NF   0x00008000 /* enable noise floor calibration to happen */
#define	AR_PHY_AGC_CONTROL_FLTR_CAL   0x00010000 /* allow tx filter calibration */
#define	AR_PHY_AGC_CONTROL_NO_UPDATE_NF   0x00020000 /* don't update noise floor automatically */
#define	AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS   0x00040000 /* extend noise floor power measurement */
#define	AR_PHY_AGC_CONTROL_CLC_SUCCESS   0x00080000 /* carrier leak calibration done */
#define	AR_PHY_AGC_CONTROL_YCOK_MAX   0x000003c0
#define	AR_PHY_AGC_CONTROL_YCOK_MAX_S   6

Enumerations
enum	ath_usb_dev { AR9280_USB = 1 , AR9287_USB = 2 , STORAGE_DEVICE = 3 }
enum	{   AR_INTR_SYNC_RTC_IRQ = 0x00000001 , AR_INTR_SYNC_MAC_IRQ = 0x00000002 , AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004 , AR_INTR_SYNC_APB_TIMEOUT = 0x00000008 ,   AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010 , AR_INTR_SYNC_HOST1_FATAL = 0x00000020 , AR_INTR_SYNC_HOST1_PERR = 0x00000040 , AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080 ,   AR_INTR_SYNC_RADM_CPL_EP = 0x00000100 , AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200 , AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400 , AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800 ,   AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000 , AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000 , AR_INTR_SYNC_PM_ACCESS = 0x00004000 , AR_INTR_SYNC_MAC_AWAKE = 0x00008000 ,   AR_INTR_SYNC_MAC_ASLEEP = 0x00010000 , AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000 , AR_INTR_SYNC_ALL = 0x0003FFFF , AR_INTR_SYNC_DEFAULT ,   AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF }

Functions
	FILE_LICENCE (BSD2)
	FILE_SECBOOT (FORBIDDEN)

Macro Definition Documentation

AR_CR

#define AR_CR   0x0008

Definition at line 25 of file reg.h.

Referenced by ar9002_hw_rx_enable(), ar9003_hw_rx_enable(), and ath9k_hw_stopdmarecv().

AR_CR_RXE

#define AR_CR_RXE   (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)

Definition at line 26 of file reg.h.

Referenced by ar9002_hw_rx_enable(), and ath9k_hw_stopdmarecv().

AR_CR_RXD

#define AR_CR_RXD   0x00000020

Definition at line 27 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_CR_SWI

#define AR_CR_SWI   0x00000040

Definition at line 28 of file reg.h.

AR_RXDP

#define AR_RXDP   0x000C

Definition at line 30 of file reg.h.

Referenced by ath9k_hw_putrxbuf().

AR_CFG

#define AR_CFG   0x0014

Definition at line 32 of file reg.h.

Referenced by ath9k_hw_reset(), and ath9k_hw_set_operating_mode().

AR_CFG_SWTD

#define AR_CFG_SWTD   0x00000001

Definition at line 33 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_SWTB

#define AR_CFG_SWTB   0x00000002

Definition at line 34 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_SWRD

#define AR_CFG_SWRD   0x00000004

Definition at line 35 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_SWRB

#define AR_CFG_SWRB   0x00000008

Definition at line 36 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_SWRG

#define AR_CFG_SWRG   0x00000010

Definition at line 37 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_AP_ADHOC_INDICATION

#define AR_CFG_AP_ADHOC_INDICATION   0x00000020

Definition at line 38 of file reg.h.

Referenced by ath9k_hw_set_operating_mode().

AR_CFG_PHOK

#define AR_CFG_PHOK   0x00000100

Definition at line 39 of file reg.h.

AR_CFG_CLK_GATE_DIS

#define AR_CFG_CLK_GATE_DIS   0x00000400

Definition at line 40 of file reg.h.

AR_CFG_EEBS

#define AR_CFG_EEBS   0x00000200

Definition at line 41 of file reg.h.

AR_CFG_PCI_MASTER_REQ_Q_THRESH

#define AR_CFG_PCI_MASTER_REQ_Q_THRESH   0x00060000

Definition at line 42 of file reg.h.

AR_CFG_PCI_MASTER_REQ_Q_THRESH_S

#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S   17

Definition at line 43 of file reg.h.

AR_RXBP_THRESH

#define AR_RXBP_THRESH   0x0018

Definition at line 45 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_RXBP_THRESH_HP

#define AR_RXBP_THRESH_HP   0x0000000f

Definition at line 46 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_RXBP_THRESH_HP_S

#define AR_RXBP_THRESH_HP_S   0

Definition at line 47 of file reg.h.

AR_RXBP_THRESH_LP

#define AR_RXBP_THRESH_LP   0x00003f00

Definition at line 48 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_RXBP_THRESH_LP_S

#define AR_RXBP_THRESH_LP_S   8

Definition at line 49 of file reg.h.

AR_MIRT

#define AR_MIRT   0x0020

Definition at line 51 of file reg.h.

AR_MIRT_VAL

#define AR_MIRT_VAL   0x0000ffff

Definition at line 52 of file reg.h.

AR_MIRT_VAL_S

#define AR_MIRT_VAL_S   16

Definition at line 53 of file reg.h.

AR_IER

#define AR_IER   0x0024

Definition at line 55 of file reg.h.

Referenced by ath9k_hw_disable_interrupts(), and ath9k_hw_enable_interrupts().

AR_IER_ENABLE

#define AR_IER_ENABLE   0x00000001

Definition at line 56 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_intrpend(), and ath9k_irq().

AR_IER_DISABLE

#define AR_IER_DISABLE   0x00000000

Definition at line 57 of file reg.h.

Referenced by ath9k_irq().

AR_TIMT

#define AR_TIMT   0x0028

Definition at line 59 of file reg.h.

Referenced by ath9k_hw_reset().

AR_TIMT_LAST

#define AR_TIMT_LAST   0x0000ffff

Definition at line 60 of file reg.h.

Referenced by ath9k_hw_reset().

AR_TIMT_LAST_S

#define AR_TIMT_LAST_S   0

Definition at line 61 of file reg.h.

AR_TIMT_FIRST

#define AR_TIMT_FIRST   0xffff0000

Definition at line 62 of file reg.h.

Referenced by ath9k_hw_reset().

AR_TIMT_FIRST_S

#define AR_TIMT_FIRST_S   16

Definition at line 63 of file reg.h.

AR_RIMT

#define AR_RIMT   0x002C

Definition at line 65 of file reg.h.

Referenced by ath9k_hw_reset().

AR_RIMT_LAST

#define AR_RIMT_LAST   0x0000ffff

Definition at line 66 of file reg.h.

Referenced by ath9k_hw_reset().

AR_RIMT_LAST_S

#define AR_RIMT_LAST_S   0

Definition at line 67 of file reg.h.

AR_RIMT_FIRST

#define AR_RIMT_FIRST   0xffff0000

Definition at line 68 of file reg.h.

Referenced by ath9k_hw_reset().

AR_RIMT_FIRST_S

#define AR_RIMT_FIRST_S   16

Definition at line 69 of file reg.h.

AR_DMASIZE_4B

#define AR_DMASIZE_4B   0x00000000

Definition at line 71 of file reg.h.

AR_DMASIZE_8B

#define AR_DMASIZE_8B   0x00000001

Definition at line 72 of file reg.h.

AR_DMASIZE_16B

#define AR_DMASIZE_16B   0x00000002

Definition at line 73 of file reg.h.

AR_DMASIZE_32B

#define AR_DMASIZE_32B   0x00000003

Definition at line 74 of file reg.h.

AR_DMASIZE_64B

#define AR_DMASIZE_64B   0x00000004

Definition at line 75 of file reg.h.

AR_DMASIZE_128B

#define AR_DMASIZE_128B   0x00000005

Definition at line 76 of file reg.h.

AR_DMASIZE_256B

#define AR_DMASIZE_256B   0x00000006

Definition at line 77 of file reg.h.

AR_DMASIZE_512B

#define AR_DMASIZE_512B   0x00000007

Definition at line 78 of file reg.h.

AR_TXCFG

#define AR_TXCFG   0x0030

Definition at line 80 of file reg.h.

Referenced by ath9k_hw_set_dma(), and ath9k_hw_updatetxtriglevel().

AR_TXCFG_DMASZ_MASK

#define AR_TXCFG_DMASZ_MASK   0x00000007

Definition at line 81 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_TXCFG_DMASZ_4B

#define AR_TXCFG_DMASZ_4B   0

Definition at line 82 of file reg.h.

AR_TXCFG_DMASZ_8B

#define AR_TXCFG_DMASZ_8B   1

Definition at line 83 of file reg.h.

AR_TXCFG_DMASZ_16B

#define AR_TXCFG_DMASZ_16B   2

Definition at line 84 of file reg.h.

AR_TXCFG_DMASZ_32B

#define AR_TXCFG_DMASZ_32B   3

Definition at line 85 of file reg.h.

AR_TXCFG_DMASZ_64B

#define AR_TXCFG_DMASZ_64B   4

Definition at line 86 of file reg.h.

AR_TXCFG_DMASZ_128B

#define AR_TXCFG_DMASZ_128B   5

Definition at line 87 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_TXCFG_DMASZ_256B

#define AR_TXCFG_DMASZ_256B   6

Definition at line 88 of file reg.h.

AR_TXCFG_DMASZ_512B

#define AR_TXCFG_DMASZ_512B   7

Definition at line 89 of file reg.h.

AR_FTRIG

#define AR_FTRIG   0x000003F0

Definition at line 90 of file reg.h.

Referenced by ath9k_hw_set_dma(), and ath9k_hw_updatetxtriglevel().

AR_FTRIG_S

#define AR_FTRIG_S   4

Definition at line 91 of file reg.h.

Referenced by __ath9k_hw_init().

AR_FTRIG_IMMED

#define AR_FTRIG_IMMED   0x00000000

Definition at line 92 of file reg.h.

AR_FTRIG_64B

#define AR_FTRIG_64B   0x00000010

Definition at line 93 of file reg.h.

AR_FTRIG_128B

#define AR_FTRIG_128B   0x00000020

Definition at line 94 of file reg.h.

AR_FTRIG_192B

#define AR_FTRIG_192B   0x00000030

Definition at line 95 of file reg.h.

AR_FTRIG_256B

#define AR_FTRIG_256B   0x00000040

Definition at line 96 of file reg.h.

Referenced by __ath9k_hw_init().

AR_FTRIG_512B

#define AR_FTRIG_512B   0x00000080

Definition at line 97 of file reg.h.

Referenced by __ath9k_hw_init().

AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY

#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY   0x00000800

Definition at line 98 of file reg.h.

AR_RXCFG

#define AR_RXCFG   0x0034

Definition at line 100 of file reg.h.

Referenced by ath9k_hw_set_dma(), and ath9k_hw_setrxfilter().

AR_RXCFG_CHIRP

#define AR_RXCFG_CHIRP   0x00000008

Definition at line 101 of file reg.h.

AR_RXCFG_ZLFDMA

#define AR_RXCFG_ZLFDMA   0x00000010

Definition at line 102 of file reg.h.

Referenced by ath9k_hw_setrxfilter().

AR_RXCFG_DMASZ_MASK

#define AR_RXCFG_DMASZ_MASK   0x00000007

Definition at line 103 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_RXCFG_DMASZ_4B

#define AR_RXCFG_DMASZ_4B   0

Definition at line 104 of file reg.h.

AR_RXCFG_DMASZ_8B

#define AR_RXCFG_DMASZ_8B   1

Definition at line 105 of file reg.h.

AR_RXCFG_DMASZ_16B

#define AR_RXCFG_DMASZ_16B   2

Definition at line 106 of file reg.h.

AR_RXCFG_DMASZ_32B

#define AR_RXCFG_DMASZ_32B   3

Definition at line 107 of file reg.h.

AR_RXCFG_DMASZ_64B

#define AR_RXCFG_DMASZ_64B   4

Definition at line 108 of file reg.h.

AR_RXCFG_DMASZ_128B

#define AR_RXCFG_DMASZ_128B   5

Definition at line 109 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_RXCFG_DMASZ_256B

#define AR_RXCFG_DMASZ_256B   6

Definition at line 110 of file reg.h.

AR_RXCFG_DMASZ_512B

#define AR_RXCFG_DMASZ_512B   7

Definition at line 111 of file reg.h.

AR_TOPS

#define AR_TOPS   0x0044

Definition at line 113 of file reg.h.

AR_TOPS_MASK

#define AR_TOPS_MASK   0x0000FFFF

Definition at line 114 of file reg.h.

AR_RXNPTO

#define AR_RXNPTO   0x0048

Definition at line 116 of file reg.h.

AR_RXNPTO_MASK

#define AR_RXNPTO_MASK   0x000003FF

Definition at line 117 of file reg.h.

AR_TXNPTO

#define AR_TXNPTO   0x004C

Definition at line 119 of file reg.h.

AR_TXNPTO_MASK

#define AR_TXNPTO_MASK   0x000003FF

Definition at line 120 of file reg.h.

AR_TXNPTO_QCU_MASK

#define AR_TXNPTO_QCU_MASK   0x000FFC00

Definition at line 121 of file reg.h.

AR_RPGTO

#define AR_RPGTO   0x0050

Definition at line 123 of file reg.h.

AR_RPGTO_MASK

#define AR_RPGTO_MASK   0x000003FF

Definition at line 124 of file reg.h.

AR_RPCNT

#define AR_RPCNT   0x0054

Definition at line 126 of file reg.h.

AR_RPCNT_MASK

#define AR_RPCNT_MASK   0x0000001F

Definition at line 127 of file reg.h.

AR_MACMISC

#define AR_MACMISC   0x0058

Definition at line 129 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_MACMISC_PCI_EXT_FORCE

#define AR_MACMISC_PCI_EXT_FORCE   0x00000010

Definition at line 130 of file reg.h.

AR_MACMISC_DMA_OBS

#define AR_MACMISC_DMA_OBS   0x000001E0

Definition at line 131 of file reg.h.

AR_MACMISC_DMA_OBS_S

#define AR_MACMISC_DMA_OBS_S   5

Definition at line 132 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_MACMISC_DMA_OBS_LINE_0

#define AR_MACMISC_DMA_OBS_LINE_0   0

Definition at line 133 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_1

#define AR_MACMISC_DMA_OBS_LINE_1   1

Definition at line 134 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_2

#define AR_MACMISC_DMA_OBS_LINE_2   2

Definition at line 135 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_3

#define AR_MACMISC_DMA_OBS_LINE_3   3

Definition at line 136 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_4

#define AR_MACMISC_DMA_OBS_LINE_4   4

Definition at line 137 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_5

#define AR_MACMISC_DMA_OBS_LINE_5   5

Definition at line 138 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_6

#define AR_MACMISC_DMA_OBS_LINE_6   6

Definition at line 139 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_7

#define AR_MACMISC_DMA_OBS_LINE_7   7

Definition at line 140 of file reg.h.

AR_MACMISC_DMA_OBS_LINE_8

#define AR_MACMISC_DMA_OBS_LINE_8   8

Definition at line 141 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_MACMISC_MISC_OBS

#define AR_MACMISC_MISC_OBS   0x00000E00

Definition at line 142 of file reg.h.

AR_MACMISC_MISC_OBS_S

#define AR_MACMISC_MISC_OBS_S   9

Definition at line 143 of file reg.h.

AR_MACMISC_MISC_OBS_BUS_LSB

#define AR_MACMISC_MISC_OBS_BUS_LSB   0x00007000

Definition at line 144 of file reg.h.

AR_MACMISC_MISC_OBS_BUS_LSB_S

#define AR_MACMISC_MISC_OBS_BUS_LSB_S   12

Definition at line 145 of file reg.h.

AR_MACMISC_MISC_OBS_BUS_MSB

#define AR_MACMISC_MISC_OBS_BUS_MSB   0x00038000

Definition at line 146 of file reg.h.

AR_MACMISC_MISC_OBS_BUS_MSB_S

#define AR_MACMISC_MISC_OBS_BUS_MSB_S   15

Definition at line 147 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_MACMISC_MISC_OBS_BUS_1

#define AR_MACMISC_MISC_OBS_BUS_1   1

Definition at line 148 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_DATABUF_SIZE

#define AR_DATABUF_SIZE   0x0060

Definition at line 150 of file reg.h.

Referenced by ath9k_hw_set_rx_bufsize().

AR_DATABUF_SIZE_MASK

#define AR_DATABUF_SIZE_MASK   0x00000FFF

Definition at line 151 of file reg.h.

Referenced by ath9k_hw_set_rx_bufsize().

AR_GTXTO

#define AR_GTXTO   0x0064

Definition at line 153 of file reg.h.

Referenced by ar5008_hw_set_channel_regs(), ar9003_hw_set_channel_regs(), and ath9k_hw_set_global_txtimeout().

AR_GTXTO_TIMEOUT_COUNTER

#define AR_GTXTO_TIMEOUT_COUNTER   0x0000FFFF

Definition at line 154 of file reg.h.

AR_GTXTO_TIMEOUT_LIMIT

#define AR_GTXTO_TIMEOUT_LIMIT   0xFFFF0000

Definition at line 155 of file reg.h.

Referenced by ath9k_hw_set_global_txtimeout().

AR_GTXTO_TIMEOUT_LIMIT_S

#define AR_GTXTO_TIMEOUT_LIMIT_S   16

Definition at line 156 of file reg.h.

Referenced by ar5008_hw_set_channel_regs(), and ar9003_hw_set_channel_regs().

AR_GTTM

#define AR_GTTM   0x0068

Definition at line 158 of file reg.h.

AR_GTTM_USEC

#define AR_GTTM_USEC   0x00000001

Definition at line 159 of file reg.h.

AR_GTTM_IGNORE_IDLE

#define AR_GTTM_IGNORE_IDLE   0x00000002

Definition at line 160 of file reg.h.

AR_GTTM_RESET_IDLE

#define AR_GTTM_RESET_IDLE   0x00000004

Definition at line 161 of file reg.h.

AR_GTTM_CST_USEC

#define AR_GTTM_CST_USEC   0x00000008

Definition at line 162 of file reg.h.

AR_CST

#define AR_CST   0x006C

Definition at line 164 of file reg.h.

Referenced by ar5008_hw_set_channel_regs(), and ar9003_hw_set_channel_regs().

AR_CST_TIMEOUT_COUNTER

#define AR_CST_TIMEOUT_COUNTER   0x0000FFFF

Definition at line 165 of file reg.h.

AR_CST_TIMEOUT_LIMIT

#define AR_CST_TIMEOUT_LIMIT   0xFFFF0000

Definition at line 166 of file reg.h.

AR_CST_TIMEOUT_LIMIT_S

#define AR_CST_TIMEOUT_LIMIT_S   16

Definition at line 167 of file reg.h.

Referenced by ar5008_hw_set_channel_regs(), and ar9003_hw_set_channel_regs().

AR_HP_RXDP

#define AR_HP_RXDP   0x0074

Definition at line 169 of file reg.h.

Referenced by ath9k_hw_addrxbuf_edma().

AR_LP_RXDP

#define AR_LP_RXDP   0x0078

Definition at line 170 of file reg.h.

Referenced by ath9k_hw_addrxbuf_edma().

AR_ISR

#define AR_ISR   0x0080

Definition at line 172 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), and ath9k_hw_reset().

AR_ISR_RXOK

#define AR_ISR_RXOK   0x00000001

Definition at line 173 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_RXDESC

#define AR_ISR_RXDESC   0x00000002

Definition at line 174 of file reg.h.

AR_ISR_HP_RXOK

#define AR_ISR_HP_RXOK   0x00000001

Definition at line 175 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_LP_RXOK

#define AR_ISR_LP_RXOK   0x00000002

Definition at line 176 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_RXERR

#define AR_ISR_RXERR   0x00000004

Definition at line 177 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_RXNOPKT

#define AR_ISR_RXNOPKT   0x00000008

Definition at line 178 of file reg.h.

AR_ISR_RXEOL

#define AR_ISR_RXEOL   0x00000010

Definition at line 179 of file reg.h.

AR_ISR_RXORN

#define AR_ISR_RXORN   0x00000020

Definition at line 180 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_TXOK

#define AR_ISR_TXOK   0x00000040

Definition at line 181 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_TXDESC

#define AR_ISR_TXDESC   0x00000080

Definition at line 182 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_TXERR

#define AR_ISR_TXERR   0x00000100

Definition at line 183 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_TXNOPKT

#define AR_ISR_TXNOPKT   0x00000200

Definition at line 184 of file reg.h.

AR_ISR_TXEOL

#define AR_ISR_TXEOL   0x00000400

Definition at line 185 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_TXURN

#define AR_ISR_TXURN   0x00000800

Definition at line 186 of file reg.h.

AR_ISR_MIB

#define AR_ISR_MIB   0x00001000

Definition at line 187 of file reg.h.

AR_ISR_SWI

#define AR_ISR_SWI   0x00002000

Definition at line 188 of file reg.h.

AR_ISR_RXPHY

#define AR_ISR_RXPHY   0x00004000

Definition at line 189 of file reg.h.

AR_ISR_RXKCM

#define AR_ISR_RXKCM   0x00008000

Definition at line 190 of file reg.h.

AR_ISR_SWBA

#define AR_ISR_SWBA   0x00010000

Definition at line 191 of file reg.h.

AR_ISR_BRSSI

#define AR_ISR_BRSSI   0x00020000

Definition at line 192 of file reg.h.

AR_ISR_BMISS

#define AR_ISR_BMISS   0x00040000

Definition at line 193 of file reg.h.

AR_ISR_BNR

#define AR_ISR_BNR   0x00100000

Definition at line 194 of file reg.h.

AR_ISR_RXCHIRP

#define AR_ISR_RXCHIRP   0x00200000

Definition at line 195 of file reg.h.

AR_ISR_BCNMISC

#define AR_ISR_BCNMISC   0x00800000

Definition at line 196 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_TIM

#define AR_ISR_TIM   0x00800000

Definition at line 197 of file reg.h.

AR_ISR_QCBROVF

#define AR_ISR_QCBROVF   0x02000000

Definition at line 198 of file reg.h.

AR_ISR_QCBRURN

#define AR_ISR_QCBRURN   0x04000000

Definition at line 199 of file reg.h.

AR_ISR_QTRIG

#define AR_ISR_QTRIG   0x08000000

Definition at line 200 of file reg.h.

AR_ISR_GENTMR

#define AR_ISR_GENTMR   0x10000000

Definition at line 201 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_TXMINTR

#define AR_ISR_TXMINTR   0x00080000

Definition at line 203 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_RXMINTR

#define AR_ISR_RXMINTR   0x01000000

Definition at line 204 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_TXINTM

#define AR_ISR_TXINTM   0x40000000

Definition at line 205 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_RXINTM

#define AR_ISR_RXINTM   0x80000000

Definition at line 206 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S0

#define AR_ISR_S0   0x0084

Definition at line 208 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_S0_QCU_TXOK [1/2]

#define AR_ISR_S0_QCU_TXOK   0x000003FF

Definition at line 209 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S0_QCU_TXOK_S [1/2]

#define AR_ISR_S0_QCU_TXOK_S   0

Definition at line 210 of file reg.h.

AR_ISR_S0_QCU_TXDESC [1/2]

#define AR_ISR_S0_QCU_TXDESC   0x03FF0000

Definition at line 211 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S0_QCU_TXDESC_S [1/2]

#define AR_ISR_S0_QCU_TXDESC_S   16

Definition at line 212 of file reg.h.

AR_ISR_S1

#define AR_ISR_S1   0x0088

Definition at line 214 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_S1_QCU_TXERR [1/2]

#define AR_ISR_S1_QCU_TXERR   0x000003FF

Definition at line 215 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S1_QCU_TXERR_S [1/2]

#define AR_ISR_S1_QCU_TXERR_S   0

Definition at line 216 of file reg.h.

AR_ISR_S1_QCU_TXEOL [1/2]

#define AR_ISR_S1_QCU_TXEOL   0x03FF0000

Definition at line 217 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S1_QCU_TXEOL_S [1/2]

#define AR_ISR_S1_QCU_TXEOL_S   16

Definition at line 218 of file reg.h.

AR_ISR_S2

#define AR_ISR_S2   0x008c

Definition at line 220 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_QCU_TXURN

#define AR_ISR_S2_QCU_TXURN   0x000003FF

Definition at line 221 of file reg.h.

AR_ISR_S2_BB_WATCHDOG

#define AR_ISR_S2_BB_WATCHDOG   0x00010000

Definition at line 222 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_S2_CST

#define AR_ISR_S2_CST   0x00400000

Definition at line 223 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_GTT

#define AR_ISR_S2_GTT   0x00800000

Definition at line 224 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_TIM

#define AR_ISR_S2_TIM   0x01000000

Definition at line 225 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_CABEND

#define AR_ISR_S2_CABEND   0x02000000

Definition at line 226 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_DTIMSYNC

#define AR_ISR_S2_DTIMSYNC   0x04000000

Definition at line 227 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_BCNTO

#define AR_ISR_S2_BCNTO   0x08000000

Definition at line 228 of file reg.h.

AR_ISR_S2_CABTO

#define AR_ISR_S2_CABTO   0x10000000

Definition at line 229 of file reg.h.

AR_ISR_S2_DTIM

#define AR_ISR_S2_DTIM   0x20000000

Definition at line 230 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_TSFOOR

#define AR_ISR_S2_TSFOOR   0x40000000

Definition at line 231 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S2_TBTT_TIME

#define AR_ISR_S2_TBTT_TIME   0x80000000

Definition at line 232 of file reg.h.

AR_ISR_S3

#define AR_ISR_S3   0x0090

Definition at line 234 of file reg.h.

AR_ISR_S3_QCU_QCBROVF

#define AR_ISR_S3_QCU_QCBROVF   0x000003FF

Definition at line 235 of file reg.h.

AR_ISR_S3_QCU_QCBRURN

#define AR_ISR_S3_QCU_QCBRURN   0x03FF0000

Definition at line 236 of file reg.h.

AR_ISR_S4

#define AR_ISR_S4   0x0094

Definition at line 238 of file reg.h.

AR_ISR_S4_QCU_QTRIG

#define AR_ISR_S4_QCU_QTRIG   0x000003FF

Definition at line 239 of file reg.h.

AR_ISR_S4_RESV0

#define AR_ISR_S4_RESV0   0xFFFFFC00

Definition at line 240 of file reg.h.

AR_ISR_S5

#define AR_ISR_S5   0x0098

Definition at line 242 of file reg.h.

Referenced by ar9003_hw_get_isr().

AR_ISR_S5_TIMER_TRIG

#define AR_ISR_S5_TIMER_TRIG   0x000000FF

Definition at line 243 of file reg.h.

AR_ISR_S5_TIMER_THRESH

#define AR_ISR_S5_TIMER_THRESH   0x0007FE00

Definition at line 244 of file reg.h.

AR_ISR_S5_TIM_TIMER

#define AR_ISR_S5_TIM_TIMER   0x00000010

Definition at line 245 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S5_DTIM_TIMER

#define AR_ISR_S5_DTIM_TIMER   0x00000020

Definition at line 246 of file reg.h.

AR_IMR_S5 [1/2]

#define AR_IMR_S5   0x00b8

Definition at line 247 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S5_TIM_TIMER

#define AR_IMR_S5_TIM_TIMER   0x00000010

Definition at line 248 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S5_DTIM_TIMER

#define AR_IMR_S5_DTIM_TIMER   0x00000020

Definition at line 249 of file reg.h.

AR_ISR_S5_GENTIMER_TRIG

#define AR_ISR_S5_GENTIMER_TRIG   0x0000FF80

Definition at line 250 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S5_GENTIMER_TRIG_S

#define AR_ISR_S5_GENTIMER_TRIG_S   0

Definition at line 251 of file reg.h.

AR_ISR_S5_GENTIMER_THRESH

#define AR_ISR_S5_GENTIMER_THRESH   0xFF800000

Definition at line 252 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S5_GENTIMER_THRESH_S

#define AR_ISR_S5_GENTIMER_THRESH_S   16

Definition at line 253 of file reg.h.

AR_IMR_S5_GENTIMER_TRIG

#define AR_IMR_S5_GENTIMER_TRIG   0x0000FF80

Definition at line 254 of file reg.h.

AR_IMR_S5_GENTIMER_TRIG_S

#define AR_IMR_S5_GENTIMER_TRIG_S   0

Definition at line 255 of file reg.h.

AR_IMR_S5_GENTIMER_THRESH

#define AR_IMR_S5_GENTIMER_THRESH   0xFF800000

Definition at line 256 of file reg.h.

AR_IMR_S5_GENTIMER_THRESH_S

#define AR_IMR_S5_GENTIMER_THRESH_S   16

Definition at line 257 of file reg.h.

AR_IMR

#define AR_IMR   0x00a0

Definition at line 259 of file reg.h.

Referenced by ath9k_hw_enable_interrupts(), ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXOK

#define AR_IMR_RXOK   0x00000001

Definition at line 260 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXDESC

#define AR_IMR_RXDESC   0x00000002

Definition at line 261 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_RXOK_HP

#define AR_IMR_RXOK_HP   0x00000001

Definition at line 262 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXOK_LP

#define AR_IMR_RXOK_LP   0x00000002

Definition at line 263 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXERR

#define AR_IMR_RXERR   0x00000004

Definition at line 264 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXNOPKT

#define AR_IMR_RXNOPKT   0x00000008

Definition at line 265 of file reg.h.

AR_IMR_RXEOL

#define AR_IMR_RXEOL   0x00000010

Definition at line 266 of file reg.h.

AR_IMR_RXORN

#define AR_IMR_RXORN   0x00000020

Definition at line 267 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks().

AR_IMR_TXOK

#define AR_IMR_TXOK   0x00000040

Definition at line 268 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_TXDESC

#define AR_IMR_TXDESC   0x00000080

Definition at line 269 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_TXERR

#define AR_IMR_TXERR   0x00000100

Definition at line 270 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_TXNOPKT

#define AR_IMR_TXNOPKT   0x00000200

Definition at line 271 of file reg.h.

AR_IMR_TXEOL

#define AR_IMR_TXEOL   0x00000400

Definition at line 272 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_TXURN

#define AR_IMR_TXURN   0x00000800

Definition at line 273 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks().

AR_IMR_MIB

#define AR_IMR_MIB   0x00001000

Definition at line 274 of file reg.h.

AR_IMR_SWI

#define AR_IMR_SWI   0x00002000

Definition at line 275 of file reg.h.

AR_IMR_RXPHY

#define AR_IMR_RXPHY   0x00004000

Definition at line 276 of file reg.h.

AR_IMR_RXKCM

#define AR_IMR_RXKCM   0x00008000

Definition at line 277 of file reg.h.

AR_IMR_SWBA

#define AR_IMR_SWBA   0x00010000

Definition at line 278 of file reg.h.

AR_IMR_BRSSI

#define AR_IMR_BRSSI   0x00020000

Definition at line 279 of file reg.h.

AR_IMR_BMISS

#define AR_IMR_BMISS   0x00040000

Definition at line 280 of file reg.h.

AR_IMR_BNR

#define AR_IMR_BNR   0x00100000

Definition at line 281 of file reg.h.

AR_IMR_RXCHIRP

#define AR_IMR_RXCHIRP   0x00200000

Definition at line 282 of file reg.h.

AR_IMR_BCNMISC

#define AR_IMR_BCNMISC   0x00800000

Definition at line 283 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_TIM

#define AR_IMR_TIM   0x00800000

Definition at line 284 of file reg.h.

AR_IMR_QCBROVF

#define AR_IMR_QCBROVF   0x02000000

Definition at line 285 of file reg.h.

AR_IMR_QCBRURN

#define AR_IMR_QCBRURN   0x04000000

Definition at line 286 of file reg.h.

AR_IMR_QTRIG

#define AR_IMR_QTRIG   0x08000000

Definition at line 287 of file reg.h.

AR_IMR_GENTMR

#define AR_IMR_GENTMR   0x10000000

Definition at line 288 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_TXMINTR

#define AR_IMR_TXMINTR   0x00080000

Definition at line 290 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXMINTR

#define AR_IMR_RXMINTR   0x01000000

Definition at line 291 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_TXINTM

#define AR_IMR_TXINTM   0x40000000

Definition at line 292 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_RXINTM

#define AR_IMR_RXINTM   0x80000000

Definition at line 293 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_interrupts().

AR_IMR_S0

#define AR_IMR_S0   0x00a4

Definition at line 295 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S0_QCU_TXOK

#define AR_IMR_S0_QCU_TXOK   0x000003FF

Definition at line 296 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S0_QCU_TXOK_S

#define AR_IMR_S0_QCU_TXOK_S   0

Definition at line 297 of file reg.h.

AR_IMR_S0_QCU_TXDESC

#define AR_IMR_S0_QCU_TXDESC   0x03FF0000

Definition at line 298 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S0_QCU_TXDESC_S

#define AR_IMR_S0_QCU_TXDESC_S   16

Definition at line 299 of file reg.h.

AR_IMR_S1

#define AR_IMR_S1   0x00a8

Definition at line 301 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S1_QCU_TXERR

#define AR_IMR_S1_QCU_TXERR   0x000003FF

Definition at line 302 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S1_QCU_TXERR_S

#define AR_IMR_S1_QCU_TXERR_S   0

Definition at line 303 of file reg.h.

AR_IMR_S1_QCU_TXEOL

#define AR_IMR_S1_QCU_TXEOL   0x03FF0000

Definition at line 304 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S1_QCU_TXEOL_S

#define AR_IMR_S1_QCU_TXEOL_S   16

Definition at line 305 of file reg.h.

AR_IMR_S2

#define AR_IMR_S2   0x00ac

Definition at line 307 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks(), ath9k_hw_set_interrupts(), and ath9k_hw_set_txq_interrupts().

AR_IMR_S2_QCU_TXURN

#define AR_IMR_S2_QCU_TXURN   0x000003FF

Definition at line 308 of file reg.h.

Referenced by ath9k_hw_set_txq_interrupts().

AR_IMR_S2_QCU_TXURN_S

#define AR_IMR_S2_QCU_TXURN_S   0

Definition at line 309 of file reg.h.

AR_IMR_S2_CST

#define AR_IMR_S2_CST   0x00400000

Definition at line 310 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_GTT

#define AR_IMR_S2_GTT   0x00800000

Definition at line 311 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_TIM

#define AR_IMR_S2_TIM   0x01000000

Definition at line 312 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_CABEND

#define AR_IMR_S2_CABEND   0x02000000

Definition at line 313 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_DTIMSYNC

#define AR_IMR_S2_DTIMSYNC   0x04000000

Definition at line 314 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_BCNTO

#define AR_IMR_S2_BCNTO   0x08000000

Definition at line 315 of file reg.h.

AR_IMR_S2_CABTO

#define AR_IMR_S2_CABTO   0x10000000

Definition at line 316 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_DTIM

#define AR_IMR_S2_DTIM   0x20000000

Definition at line 317 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S2_TSFOOR

#define AR_IMR_S2_TSFOOR   0x40000000

Definition at line 318 of file reg.h.

Referenced by ath9k_hw_set_interrupts().

AR_IMR_S3

#define AR_IMR_S3   0x00b0

Definition at line 320 of file reg.h.

AR_IMR_S3_QCU_QCBROVF

#define AR_IMR_S3_QCU_QCBROVF   0x000003FF

Definition at line 321 of file reg.h.

AR_IMR_S3_QCU_QCBRURN

#define AR_IMR_S3_QCU_QCBRURN   0x03FF0000

Definition at line 322 of file reg.h.

AR_IMR_S3_QCU_QCBRURN_S

#define AR_IMR_S3_QCU_QCBRURN_S   16

Definition at line 323 of file reg.h.

AR_IMR_S4

#define AR_IMR_S4   0x00b4

Definition at line 325 of file reg.h.

AR_IMR_S4_QCU_QTRIG

#define AR_IMR_S4_QCU_QTRIG   0x000003FF

Definition at line 326 of file reg.h.

AR_IMR_S4_RESV0

#define AR_IMR_S4_RESV0   0xFFFFFC00

Definition at line 327 of file reg.h.

AR_IMR_S5 [2/2]

#define AR_IMR_S5   0x00b8

Definition at line 247 of file reg.h.

AR_IMR_S5_TIMER_TRIG

#define AR_IMR_S5_TIMER_TRIG   0x000000FF

Definition at line 330 of file reg.h.

AR_IMR_S5_TIMER_THRESH

#define AR_IMR_S5_TIMER_THRESH   0x0000FF00

Definition at line 331 of file reg.h.

AR_ISR_RAC

#define AR_ISR_RAC   0x00c0

Definition at line 334 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_ISR_S0_S

#define AR_ISR_S0_S   0x00c4

Definition at line 335 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S0_QCU_TXOK [2/2]

#define AR_ISR_S0_QCU_TXOK   0x000003FF

Definition at line 209 of file reg.h.

AR_ISR_S0_QCU_TXOK_S [2/2]

#define AR_ISR_S0_QCU_TXOK_S   0

Definition at line 210 of file reg.h.

AR_ISR_S0_QCU_TXDESC [2/2]

#define AR_ISR_S0_QCU_TXDESC   0x03FF0000

Definition at line 211 of file reg.h.

AR_ISR_S0_QCU_TXDESC_S [2/2]

#define AR_ISR_S0_QCU_TXDESC_S   16

Definition at line 212 of file reg.h.

AR_ISR_S1_S

#define AR_ISR_S1_S   0x00c8

Definition at line 341 of file reg.h.

Referenced by ar9002_hw_get_isr().

AR_ISR_S1_QCU_TXERR [2/2]

#define AR_ISR_S1_QCU_TXERR   0x000003FF

Definition at line 215 of file reg.h.

AR_ISR_S1_QCU_TXERR_S [2/2]

#define AR_ISR_S1_QCU_TXERR_S   0

Definition at line 216 of file reg.h.

AR_ISR_S1_QCU_TXEOL [2/2]

#define AR_ISR_S1_QCU_TXEOL   0x03FF0000

Definition at line 217 of file reg.h.

AR_ISR_S1_QCU_TXEOL_S [2/2]

#define AR_ISR_S1_QCU_TXEOL_S   16

Definition at line 218 of file reg.h.

AR_ISR_S2_S

#define AR_ISR_S2_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)

Definition at line 347 of file reg.h.

AR_ISR_S3_S

#define AR_ISR_S3_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)

Definition at line 348 of file reg.h.

AR_ISR_S4_S

#define AR_ISR_S4_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)

Definition at line 349 of file reg.h.

AR_ISR_S5_S

#define AR_ISR_S5_S   (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)

Definition at line 350 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_DMADBG_0

#define AR_DMADBG_0   0x00e0

Definition at line 351 of file reg.h.

AR_DMADBG_1

#define AR_DMADBG_1   0x00e4

Definition at line 352 of file reg.h.

AR_DMADBG_2

#define AR_DMADBG_2   0x00e8

Definition at line 353 of file reg.h.

AR_DMADBG_3

#define AR_DMADBG_3   0x00ec

Definition at line 354 of file reg.h.

AR_DMADBG_4

#define AR_DMADBG_4   0x00f0

Definition at line 355 of file reg.h.

AR_DMADBG_5

#define AR_DMADBG_5   0x00f4

Definition at line 356 of file reg.h.

AR_DMADBG_6

#define AR_DMADBG_6   0x00f8

Definition at line 357 of file reg.h.

AR_DMADBG_7

#define AR_DMADBG_7   0x00fc

Definition at line 358 of file reg.h.

Referenced by ath9k_hw_stopdmarecv().

AR_NUM_QCU

#define AR_NUM_QCU   10

Definition at line 360 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma(), and ath9k_hw_channel_change().

AR_QCU_0

#define AR_QCU_0   0x0001

Definition at line 361 of file reg.h.

AR_QCU_1

#define AR_QCU_1   0x0002

Definition at line 362 of file reg.h.

AR_QCU_2

#define AR_QCU_2   0x0004

Definition at line 363 of file reg.h.

AR_QCU_3

#define AR_QCU_3   0x0008

Definition at line 364 of file reg.h.

AR_QCU_4

#define AR_QCU_4   0x0010

Definition at line 365 of file reg.h.

AR_QCU_5

#define AR_QCU_5   0x0020

Definition at line 366 of file reg.h.

AR_QCU_6

#define AR_QCU_6   0x0040

Definition at line 367 of file reg.h.

AR_QCU_7

#define AR_QCU_7   0x0080

Definition at line 368 of file reg.h.

AR_QCU_8

#define AR_QCU_8   0x0100

Definition at line 369 of file reg.h.

AR_QCU_9

#define AR_QCU_9   0x0200

Definition at line 370 of file reg.h.

AR_Q0_TXDP

#define AR_Q0_TXDP   0x0800

Definition at line 372 of file reg.h.

AR_Q1_TXDP

#define AR_Q1_TXDP   0x0804

Definition at line 373 of file reg.h.

AR_Q2_TXDP

#define AR_Q2_TXDP   0x0808

Definition at line 374 of file reg.h.

AR_Q3_TXDP

#define AR_Q3_TXDP   0x080c

Definition at line 375 of file reg.h.

AR_Q4_TXDP

#define AR_Q4_TXDP   0x0810

Definition at line 376 of file reg.h.

AR_Q5_TXDP

#define AR_Q5_TXDP   0x0814

Definition at line 377 of file reg.h.

AR_Q6_TXDP

#define AR_Q6_TXDP   0x0818

Definition at line 378 of file reg.h.

AR_Q7_TXDP

#define AR_Q7_TXDP   0x081c

Definition at line 379 of file reg.h.

AR_Q8_TXDP

#define AR_Q8_TXDP   0x0820

Definition at line 380 of file reg.h.

AR_Q9_TXDP

#define AR_Q9_TXDP   0x0824

Definition at line 381 of file reg.h.

AR_QTXDP

#define AR_QTXDP

(

_i

)

Value:

(AR_Q0_TXDP + ((_i)<<2))

Definition at line 382 of file reg.h.

Referenced by ath9k_hw_puttxbuf().

AR_Q_STATUS_RING_START

#define AR_Q_STATUS_RING_START   0x830

Definition at line 384 of file reg.h.

Referenced by ath9k_hw_reset_txstatus_ring().

AR_Q_STATUS_RING_END

#define AR_Q_STATUS_RING_END   0x834

Definition at line 385 of file reg.h.

Referenced by ath9k_hw_reset_txstatus_ring().

AR_Q_TXE

#define AR_Q_TXE   0x0840

Definition at line 387 of file reg.h.

Referenced by ath9k_hw_numtxpending(), and ath9k_hw_txstart().

AR_Q_TXE_M

#define AR_Q_TXE_M   0x000003FF

Definition at line 388 of file reg.h.

AR_Q_TXD

#define AR_Q_TXD   0x0880

Definition at line 390 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_Q_TXD_M

#define AR_Q_TXD_M   0x000003FF

Definition at line 391 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_Q0_CBRCFG

#define AR_Q0_CBRCFG   0x08c0

Definition at line 393 of file reg.h.

AR_Q1_CBRCFG

#define AR_Q1_CBRCFG   0x08c4

Definition at line 394 of file reg.h.

AR_Q2_CBRCFG

#define AR_Q2_CBRCFG   0x08c8

Definition at line 395 of file reg.h.

AR_Q3_CBRCFG

#define AR_Q3_CBRCFG   0x08cc

Definition at line 396 of file reg.h.

AR_Q4_CBRCFG

#define AR_Q4_CBRCFG   0x08d0

Definition at line 397 of file reg.h.

AR_Q5_CBRCFG

#define AR_Q5_CBRCFG   0x08d4

Definition at line 398 of file reg.h.

AR_Q6_CBRCFG

#define AR_Q6_CBRCFG   0x08d8

Definition at line 399 of file reg.h.

AR_Q7_CBRCFG

#define AR_Q7_CBRCFG   0x08dc

Definition at line 400 of file reg.h.

AR_Q8_CBRCFG

#define AR_Q8_CBRCFG   0x08e0

Definition at line 401 of file reg.h.

AR_Q9_CBRCFG

#define AR_Q9_CBRCFG   0x08e4

Definition at line 402 of file reg.h.

AR_QCBRCFG

#define AR_QCBRCFG

(

_i

)

Value:

(AR_Q0_CBRCFG + ((_i)<<2))

Definition at line 403 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_CBRCFG_INTERVAL

#define AR_Q_CBRCFG_INTERVAL   0x00FFFFFF

Definition at line 404 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_CBRCFG_INTERVAL_S

#define AR_Q_CBRCFG_INTERVAL_S   0

Definition at line 405 of file reg.h.

AR_Q_CBRCFG_OVF_THRESH

#define AR_Q_CBRCFG_OVF_THRESH   0xFF000000

Definition at line 406 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_CBRCFG_OVF_THRESH_S

#define AR_Q_CBRCFG_OVF_THRESH_S   24

Definition at line 407 of file reg.h.

AR_Q0_RDYTIMECFG

#define AR_Q0_RDYTIMECFG   0x0900

Definition at line 409 of file reg.h.

AR_Q1_RDYTIMECFG

#define AR_Q1_RDYTIMECFG   0x0904

Definition at line 410 of file reg.h.

AR_Q2_RDYTIMECFG

#define AR_Q2_RDYTIMECFG   0x0908

Definition at line 411 of file reg.h.

AR_Q3_RDYTIMECFG

#define AR_Q3_RDYTIMECFG   0x090c

Definition at line 412 of file reg.h.

AR_Q4_RDYTIMECFG

#define AR_Q4_RDYTIMECFG   0x0910

Definition at line 413 of file reg.h.

AR_Q5_RDYTIMECFG

#define AR_Q5_RDYTIMECFG   0x0914

Definition at line 414 of file reg.h.

AR_Q6_RDYTIMECFG

#define AR_Q6_RDYTIMECFG   0x0918

Definition at line 415 of file reg.h.

AR_Q7_RDYTIMECFG

#define AR_Q7_RDYTIMECFG   0x091c

Definition at line 416 of file reg.h.

AR_Q8_RDYTIMECFG

#define AR_Q8_RDYTIMECFG   0x0920

Definition at line 417 of file reg.h.

AR_Q9_RDYTIMECFG

#define AR_Q9_RDYTIMECFG   0x0924

Definition at line 418 of file reg.h.

AR_QRDYTIMECFG

#define AR_QRDYTIMECFG

(

_i

)

Value:

(AR_Q0_RDYTIMECFG + ((_i)<<2))

Definition at line 419 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_RDYTIMECFG_DURATION

#define AR_Q_RDYTIMECFG_DURATION   0x00FFFFFF

Definition at line 420 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_RDYTIMECFG_DURATION_S

#define AR_Q_RDYTIMECFG_DURATION_S   0

Definition at line 421 of file reg.h.

AR_Q_RDYTIMECFG_EN

#define AR_Q_RDYTIMECFG_EN   0x01000000

Definition at line 422 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_ONESHOTARM_SC

#define AR_Q_ONESHOTARM_SC   0x0940

Definition at line 424 of file reg.h.

AR_Q_ONESHOTARM_SC_M

#define AR_Q_ONESHOTARM_SC_M   0x000003FF

Definition at line 425 of file reg.h.

AR_Q_ONESHOTARM_SC_RESV0

#define AR_Q_ONESHOTARM_SC_RESV0   0xFFFFFC00

Definition at line 426 of file reg.h.

AR_Q_ONESHOTARM_CC

#define AR_Q_ONESHOTARM_CC   0x0980

Definition at line 428 of file reg.h.

AR_Q_ONESHOTARM_CC_M

#define AR_Q_ONESHOTARM_CC_M   0x000003FF

Definition at line 429 of file reg.h.

AR_Q_ONESHOTARM_CC_RESV0

#define AR_Q_ONESHOTARM_CC_RESV0   0xFFFFFC00

Definition at line 430 of file reg.h.

AR_Q0_MISC

#define AR_Q0_MISC   0x09c0

Definition at line 432 of file reg.h.

AR_Q1_MISC

#define AR_Q1_MISC   0x09c4

Definition at line 433 of file reg.h.

AR_Q2_MISC

#define AR_Q2_MISC   0x09c8

Definition at line 434 of file reg.h.

AR_Q3_MISC

#define AR_Q3_MISC   0x09cc

Definition at line 435 of file reg.h.

AR_Q4_MISC

#define AR_Q4_MISC   0x09d0

Definition at line 436 of file reg.h.

AR_Q5_MISC

#define AR_Q5_MISC   0x09d4

Definition at line 437 of file reg.h.

AR_Q6_MISC

#define AR_Q6_MISC   0x09d8

Definition at line 438 of file reg.h.

AR_Q7_MISC

#define AR_Q7_MISC   0x09dc

Definition at line 439 of file reg.h.

AR_Q8_MISC

#define AR_Q8_MISC   0x09e0

Definition at line 440 of file reg.h.

AR_Q9_MISC

#define AR_Q9_MISC   0x09e4

Definition at line 441 of file reg.h.

AR_QMISC

#define AR_QMISC

(

_i

)

Value:

(AR_Q0_MISC + ((_i)<<2))

Definition at line 442 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_MISC_FSP

#define AR_Q_MISC_FSP   0x0000000F

Definition at line 443 of file reg.h.

AR_Q_MISC_FSP_ASAP

#define AR_Q_MISC_FSP_ASAP   0

Definition at line 444 of file reg.h.

AR_Q_MISC_FSP_CBR

#define AR_Q_MISC_FSP_CBR   1

Definition at line 445 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_MISC_FSP_DBA_GATED

#define AR_Q_MISC_FSP_DBA_GATED   2

Definition at line 446 of file reg.h.

AR_Q_MISC_FSP_TIM_GATED

#define AR_Q_MISC_FSP_TIM_GATED   3

Definition at line 447 of file reg.h.

AR_Q_MISC_FSP_BEACON_SENT_GATED

#define AR_Q_MISC_FSP_BEACON_SENT_GATED   4

Definition at line 448 of file reg.h.

AR_Q_MISC_FSP_BEACON_RCVD_GATED

#define AR_Q_MISC_FSP_BEACON_RCVD_GATED   5

Definition at line 449 of file reg.h.

AR_Q_MISC_ONE_SHOT_EN

#define AR_Q_MISC_ONE_SHOT_EN   0x00000010

Definition at line 450 of file reg.h.

AR_Q_MISC_CBR_INCR_DIS1

#define AR_Q_MISC_CBR_INCR_DIS1   0x00000020

Definition at line 451 of file reg.h.

AR_Q_MISC_CBR_INCR_DIS0

#define AR_Q_MISC_CBR_INCR_DIS0   0x00000040

Definition at line 452 of file reg.h.

AR_Q_MISC_BEACON_USE

#define AR_Q_MISC_BEACON_USE   0x00000080

Definition at line 453 of file reg.h.

AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN

#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN   0x00000100

Definition at line 454 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_MISC_RDYTIME_EXP_POLICY

#define AR_Q_MISC_RDYTIME_EXP_POLICY   0x00000200

Definition at line 455 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_MISC_RESET_CBR_EXP_CTR

#define AR_Q_MISC_RESET_CBR_EXP_CTR   0x00000400

Definition at line 456 of file reg.h.

AR_Q_MISC_DCU_EARLY_TERM_REQ

#define AR_Q_MISC_DCU_EARLY_TERM_REQ   0x00000800

Definition at line 457 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_MISC_RESV0

#define AR_Q_MISC_RESV0   0xFFFFF000

Definition at line 458 of file reg.h.

AR_Q0_STS

#define AR_Q0_STS   0x0a00

Definition at line 460 of file reg.h.

AR_Q1_STS

#define AR_Q1_STS   0x0a04

Definition at line 461 of file reg.h.

AR_Q2_STS

#define AR_Q2_STS   0x0a08

Definition at line 462 of file reg.h.

AR_Q3_STS

#define AR_Q3_STS   0x0a0c

Definition at line 463 of file reg.h.

AR_Q4_STS

#define AR_Q4_STS   0x0a10

Definition at line 464 of file reg.h.

AR_Q5_STS

#define AR_Q5_STS   0x0a14

Definition at line 465 of file reg.h.

AR_Q6_STS

#define AR_Q6_STS   0x0a18

Definition at line 466 of file reg.h.

AR_Q7_STS

#define AR_Q7_STS   0x0a1c

Definition at line 467 of file reg.h.

AR_Q8_STS

#define AR_Q8_STS   0x0a20

Definition at line 468 of file reg.h.

AR_Q9_STS

#define AR_Q9_STS   0x0a24

Definition at line 469 of file reg.h.

AR_QSTS

#define AR_QSTS

(

_i

)

Value:

(AR_Q0_STS + ((_i)<<2))

Definition at line 470 of file reg.h.

Referenced by ath9k_hw_numtxpending().

AR_Q_STS_PEND_FR_CNT

#define AR_Q_STS_PEND_FR_CNT   0x00000003

Definition at line 471 of file reg.h.

Referenced by ath9k_hw_numtxpending().

AR_Q_STS_RESV0

#define AR_Q_STS_RESV0   0x000000FC

Definition at line 472 of file reg.h.

AR_Q_STS_CBR_EXP_CNT

#define AR_Q_STS_CBR_EXP_CNT   0x0000FF00

Definition at line 473 of file reg.h.

AR_Q_STS_RESV1

#define AR_Q_STS_RESV1   0xFFFF0000

Definition at line 474 of file reg.h.

AR_Q_RDYTIMESHDN

#define AR_Q_RDYTIMESHDN   0x0a40

Definition at line 476 of file reg.h.

AR_Q_RDYTIMESHDN_M

#define AR_Q_RDYTIMESHDN_M   0x000003FF

Definition at line 477 of file reg.h.

AR_Q_DESC_CRCCHK

#define AR_Q_DESC_CRCCHK   0xa44

Definition at line 480 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_Q_DESC_CRCCHK_EN

#define AR_Q_DESC_CRCCHK_EN   1

Definition at line 482 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_NUM_DCU

#define AR_NUM_DCU   10

Definition at line 484 of file reg.h.

Referenced by ath9k_hw_reset().

AR_DCU_0

#define AR_DCU_0   0x0001

Definition at line 485 of file reg.h.

AR_DCU_1

#define AR_DCU_1   0x0002

Definition at line 486 of file reg.h.

AR_DCU_2

#define AR_DCU_2   0x0004

Definition at line 487 of file reg.h.

AR_DCU_3

#define AR_DCU_3   0x0008

Definition at line 488 of file reg.h.

AR_DCU_4

#define AR_DCU_4   0x0010

Definition at line 489 of file reg.h.

AR_DCU_5

#define AR_DCU_5   0x0020

Definition at line 490 of file reg.h.

AR_DCU_6

#define AR_DCU_6   0x0040

Definition at line 491 of file reg.h.

AR_DCU_7

#define AR_DCU_7   0x0080

Definition at line 492 of file reg.h.

AR_DCU_8

#define AR_DCU_8   0x0100

Definition at line 493 of file reg.h.

AR_DCU_9

#define AR_DCU_9   0x0200

Definition at line 494 of file reg.h.

AR_D0_QCUMASK

#define AR_D0_QCUMASK   0x1000

Definition at line 496 of file reg.h.

AR_D1_QCUMASK

#define AR_D1_QCUMASK   0x1004

Definition at line 497 of file reg.h.

AR_D2_QCUMASK

#define AR_D2_QCUMASK   0x1008

Definition at line 498 of file reg.h.

AR_D3_QCUMASK

#define AR_D3_QCUMASK   0x100c

Definition at line 499 of file reg.h.

AR_D4_QCUMASK

#define AR_D4_QCUMASK   0x1010

Definition at line 500 of file reg.h.

AR_D5_QCUMASK

#define AR_D5_QCUMASK   0x1014

Definition at line 501 of file reg.h.

AR_D6_QCUMASK

#define AR_D6_QCUMASK   0x1018

Definition at line 502 of file reg.h.

AR_D7_QCUMASK

#define AR_D7_QCUMASK   0x101c

Definition at line 503 of file reg.h.

AR_D8_QCUMASK

#define AR_D8_QCUMASK   0x1020

Definition at line 504 of file reg.h.

AR_D9_QCUMASK

#define AR_D9_QCUMASK   0x1024

Definition at line 505 of file reg.h.

AR_DQCUMASK

#define AR_DQCUMASK

(

_i

)

Value:

(AR_D0_QCUMASK + ((_i)<<2))

Definition at line 506 of file reg.h.

Referenced by ath9k_hw_reset().

AR_D_QCUMASK

#define AR_D_QCUMASK   0x000003FF

Definition at line 507 of file reg.h.

AR_D_QCUMASK_RESV0

#define AR_D_QCUMASK_RESV0   0xFFFFFC00

Definition at line 508 of file reg.h.

AR_D_TXBLK_CMD

#define AR_D_TXBLK_CMD   0x1038

Definition at line 510 of file reg.h.

AR_D_TXBLK_DATA

#define AR_D_TXBLK_DATA

(

i

)

Value:

(AR_D_TXBLK_CMD+(i))

Definition at line 511 of file reg.h.

AR_D0_LCL_IFS

#define AR_D0_LCL_IFS   0x1040

Definition at line 513 of file reg.h.

AR_D1_LCL_IFS

#define AR_D1_LCL_IFS   0x1044

Definition at line 514 of file reg.h.

AR_D2_LCL_IFS

#define AR_D2_LCL_IFS   0x1048

Definition at line 515 of file reg.h.

AR_D3_LCL_IFS

#define AR_D3_LCL_IFS   0x104c

Definition at line 516 of file reg.h.

AR_D4_LCL_IFS

#define AR_D4_LCL_IFS   0x1050

Definition at line 517 of file reg.h.

AR_D5_LCL_IFS

#define AR_D5_LCL_IFS   0x1054

Definition at line 518 of file reg.h.

AR_D6_LCL_IFS

#define AR_D6_LCL_IFS   0x1058

Definition at line 519 of file reg.h.

AR_D7_LCL_IFS

#define AR_D7_LCL_IFS   0x105c

Definition at line 520 of file reg.h.

AR_D8_LCL_IFS

#define AR_D8_LCL_IFS   0x1060

Definition at line 521 of file reg.h.

AR_D9_LCL_IFS

#define AR_D9_LCL_IFS   0x1064

Definition at line 522 of file reg.h.

AR_DLCL_IFS

#define AR_DLCL_IFS

(

_i

)

Value:

(AR_D0_LCL_IFS + ((_i)<<2))

Definition at line 523 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_LCL_IFS_CWMIN

#define AR_D_LCL_IFS_CWMIN   0x000003FF

Definition at line 524 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_LCL_IFS_CWMIN_S

#define AR_D_LCL_IFS_CWMIN_S   0

Definition at line 525 of file reg.h.

AR_D_LCL_IFS_CWMAX

#define AR_D_LCL_IFS_CWMAX   0x000FFC00

Definition at line 526 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_LCL_IFS_CWMAX_S

#define AR_D_LCL_IFS_CWMAX_S   10

Definition at line 527 of file reg.h.

AR_D_LCL_IFS_AIFS

#define AR_D_LCL_IFS_AIFS   0x0FF00000

Definition at line 528 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_LCL_IFS_AIFS_S

#define AR_D_LCL_IFS_AIFS_S   20

Definition at line 529 of file reg.h.

AR_D_LCL_IFS_RESV0

#define AR_D_LCL_IFS_RESV0   0xF0000000

Definition at line 531 of file reg.h.

AR_D0_RETRY_LIMIT

#define AR_D0_RETRY_LIMIT   0x1080

Definition at line 533 of file reg.h.

AR_D1_RETRY_LIMIT

#define AR_D1_RETRY_LIMIT   0x1084

Definition at line 534 of file reg.h.

AR_D2_RETRY_LIMIT

#define AR_D2_RETRY_LIMIT   0x1088

Definition at line 535 of file reg.h.

AR_D3_RETRY_LIMIT

#define AR_D3_RETRY_LIMIT   0x108c

Definition at line 536 of file reg.h.

AR_D4_RETRY_LIMIT

#define AR_D4_RETRY_LIMIT   0x1090

Definition at line 537 of file reg.h.

AR_D5_RETRY_LIMIT

#define AR_D5_RETRY_LIMIT   0x1094

Definition at line 538 of file reg.h.

AR_D6_RETRY_LIMIT

#define AR_D6_RETRY_LIMIT   0x1098

Definition at line 539 of file reg.h.

AR_D7_RETRY_LIMIT

#define AR_D7_RETRY_LIMIT   0x109c

Definition at line 540 of file reg.h.

AR_D8_RETRY_LIMIT

#define AR_D8_RETRY_LIMIT   0x10a0

Definition at line 541 of file reg.h.

AR_D9_RETRY_LIMIT

#define AR_D9_RETRY_LIMIT   0x10a4

Definition at line 542 of file reg.h.

AR_DRETRY_LIMIT

#define AR_DRETRY_LIMIT

(

_i

)

Value:

(AR_D0_RETRY_LIMIT + ((_i)<<2))

Definition at line 543 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_RETRY_LIMIT_FR_SH

#define AR_D_RETRY_LIMIT_FR_SH   0x0000000F

Definition at line 544 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_RETRY_LIMIT_FR_SH_S

#define AR_D_RETRY_LIMIT_FR_SH_S   0

Definition at line 545 of file reg.h.

AR_D_RETRY_LIMIT_STA_SH

#define AR_D_RETRY_LIMIT_STA_SH   0x00003F00

Definition at line 546 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_RETRY_LIMIT_STA_SH_S

#define AR_D_RETRY_LIMIT_STA_SH_S   8

Definition at line 547 of file reg.h.

AR_D_RETRY_LIMIT_STA_LG

#define AR_D_RETRY_LIMIT_STA_LG   0x000FC000

Definition at line 548 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_RETRY_LIMIT_STA_LG_S

#define AR_D_RETRY_LIMIT_STA_LG_S   14

Definition at line 549 of file reg.h.

AR_D_RETRY_LIMIT_RESV0

#define AR_D_RETRY_LIMIT_RESV0   0xFFF00000

Definition at line 550 of file reg.h.

AR_D0_CHNTIME

#define AR_D0_CHNTIME   0x10c0

Definition at line 552 of file reg.h.

AR_D1_CHNTIME

#define AR_D1_CHNTIME   0x10c4

Definition at line 553 of file reg.h.

AR_D2_CHNTIME

#define AR_D2_CHNTIME   0x10c8

Definition at line 554 of file reg.h.

AR_D3_CHNTIME

#define AR_D3_CHNTIME   0x10cc

Definition at line 555 of file reg.h.

AR_D4_CHNTIME

#define AR_D4_CHNTIME   0x10d0

Definition at line 556 of file reg.h.

AR_D5_CHNTIME

#define AR_D5_CHNTIME   0x10d4

Definition at line 557 of file reg.h.

AR_D6_CHNTIME

#define AR_D6_CHNTIME   0x10d8

Definition at line 558 of file reg.h.

AR_D7_CHNTIME

#define AR_D7_CHNTIME   0x10dc

Definition at line 559 of file reg.h.

AR_D8_CHNTIME

#define AR_D8_CHNTIME   0x10e0

Definition at line 560 of file reg.h.

AR_D9_CHNTIME

#define AR_D9_CHNTIME   0x10e4

Definition at line 561 of file reg.h.

AR_DCHNTIME

#define AR_DCHNTIME

(

_i

)

Value:

(AR_D0_CHNTIME + ((_i)<<2))

Definition at line 562 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_CHNTIME_DUR

#define AR_D_CHNTIME_DUR   0x000FFFFF

Definition at line 563 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_CHNTIME_DUR_S

#define AR_D_CHNTIME_DUR_S   0

Definition at line 564 of file reg.h.

AR_D_CHNTIME_EN

#define AR_D_CHNTIME_EN   0x00100000

Definition at line 565 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_CHNTIME_RESV0

#define AR_D_CHNTIME_RESV0   0xFFE00000

Definition at line 566 of file reg.h.

AR_D0_MISC

#define AR_D0_MISC   0x1100

Definition at line 568 of file reg.h.

AR_D1_MISC

#define AR_D1_MISC   0x1104

Definition at line 569 of file reg.h.

AR_D2_MISC

#define AR_D2_MISC   0x1108

Definition at line 570 of file reg.h.

AR_D3_MISC

#define AR_D3_MISC   0x110c

Definition at line 571 of file reg.h.

AR_D4_MISC

#define AR_D4_MISC   0x1110

Definition at line 572 of file reg.h.

AR_D5_MISC

#define AR_D5_MISC   0x1114

Definition at line 573 of file reg.h.

AR_D6_MISC

#define AR_D6_MISC   0x1118

Definition at line 574 of file reg.h.

AR_D7_MISC

#define AR_D7_MISC   0x111c

Definition at line 575 of file reg.h.

AR_D8_MISC

#define AR_D8_MISC   0x1120

Definition at line 576 of file reg.h.

AR_D9_MISC

#define AR_D9_MISC   0x1124

Definition at line 577 of file reg.h.

AR_DMISC

#define AR_DMISC

(

_i

)

Value:

(AR_D0_MISC + ((_i)<<2))

Definition at line 578 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_BKOFF_THRESH

#define AR_D_MISC_BKOFF_THRESH   0x0000003F

Definition at line 579 of file reg.h.

AR_D_MISC_RETRY_CNT_RESET_EN

#define AR_D_MISC_RETRY_CNT_RESET_EN   0x00000040

Definition at line 580 of file reg.h.

AR_D_MISC_CW_RESET_EN

#define AR_D_MISC_CW_RESET_EN   0x00000080

Definition at line 581 of file reg.h.

AR_D_MISC_FRAG_WAIT_EN

#define AR_D_MISC_FRAG_WAIT_EN   0x00000100

Definition at line 582 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_FRAG_BKOFF_EN

#define AR_D_MISC_FRAG_BKOFF_EN   0x00000200

Definition at line 583 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_CW_BKOFF_EN

#define AR_D_MISC_CW_BKOFF_EN   0x00001000

Definition at line 584 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_VIR_COL_HANDLING

#define AR_D_MISC_VIR_COL_HANDLING   0x0000C000

Definition at line 585 of file reg.h.

AR_D_MISC_VIR_COL_HANDLING_S

#define AR_D_MISC_VIR_COL_HANDLING_S   14

Definition at line 586 of file reg.h.

AR_D_MISC_VIR_COL_HANDLING_DEFAULT

#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT   0

Definition at line 587 of file reg.h.

AR_D_MISC_VIR_COL_HANDLING_IGNORE

#define AR_D_MISC_VIR_COL_HANDLING_IGNORE   1

Definition at line 588 of file reg.h.

AR_D_MISC_BEACON_USE

#define AR_D_MISC_BEACON_USE   0x00010000

Definition at line 589 of file reg.h.

AR_D_MISC_ARB_LOCKOUT_CNTRL

#define AR_D_MISC_ARB_LOCKOUT_CNTRL   0x00060000

Definition at line 590 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_ARB_LOCKOUT_CNTRL_S

#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S   17

Definition at line 591 of file reg.h.

AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE

#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE   0

Definition at line 592 of file reg.h.

AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR

#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR   1

Definition at line 593 of file reg.h.

AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL

#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL   2

Definition at line 594 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_ARB_LOCKOUT_IGNORE

#define AR_D_MISC_ARB_LOCKOUT_IGNORE   0x00080000

Definition at line 595 of file reg.h.

AR_D_MISC_SEQ_NUM_INCR_DIS

#define AR_D_MISC_SEQ_NUM_INCR_DIS   0x00100000

Definition at line 596 of file reg.h.

AR_D_MISC_POST_FR_BKOFF_DIS

#define AR_D_MISC_POST_FR_BKOFF_DIS   0x00200000

Definition at line 597 of file reg.h.

Referenced by ath9k_hw_resettxqueue().

AR_D_MISC_VIT_COL_CW_BKOFF_EN

#define AR_D_MISC_VIT_COL_CW_BKOFF_EN   0x00400000

Definition at line 598 of file reg.h.

AR_D_MISC_BLOWN_IFS_RETRY_EN

#define AR_D_MISC_BLOWN_IFS_RETRY_EN   0x00800000

Definition at line 599 of file reg.h.

AR_D_MISC_RESV0

#define AR_D_MISC_RESV0   0xFF000000

Definition at line 600 of file reg.h.

AR_D_SEQNUM

#define AR_D_SEQNUM   0x1140

Definition at line 602 of file reg.h.

AR_D_GBL_IFS_SIFS

#define AR_D_GBL_IFS_SIFS   0x1030

Definition at line 604 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_D_GBL_IFS_SIFS_M

#define AR_D_GBL_IFS_SIFS_M   0x0000FFFF

Definition at line 605 of file reg.h.

AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR

#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR   0x000003AB

Definition at line 606 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_D_GBL_IFS_SIFS_RESV0

#define AR_D_GBL_IFS_SIFS_RESV0   0xFFFFFFFF

Definition at line 607 of file reg.h.

AR_D_TXBLK_BASE

#define AR_D_TXBLK_BASE   0x1038

Definition at line 609 of file reg.h.

AR_D_TXBLK_WRITE_BITMASK

#define AR_D_TXBLK_WRITE_BITMASK   0x0000FFFF

Definition at line 610 of file reg.h.

AR_D_TXBLK_WRITE_BITMASK_S

#define AR_D_TXBLK_WRITE_BITMASK_S   0

Definition at line 611 of file reg.h.

AR_D_TXBLK_WRITE_SLICE

#define AR_D_TXBLK_WRITE_SLICE   0x000F0000

Definition at line 612 of file reg.h.

AR_D_TXBLK_WRITE_SLICE_S

#define AR_D_TXBLK_WRITE_SLICE_S   16

Definition at line 613 of file reg.h.

AR_D_TXBLK_WRITE_DCU

#define AR_D_TXBLK_WRITE_DCU   0x00F00000

Definition at line 614 of file reg.h.

AR_D_TXBLK_WRITE_DCU_S

#define AR_D_TXBLK_WRITE_DCU_S   20

Definition at line 615 of file reg.h.

AR_D_TXBLK_WRITE_COMMAND

#define AR_D_TXBLK_WRITE_COMMAND   0x0F000000

Definition at line 616 of file reg.h.

AR_D_TXBLK_WRITE_COMMAND_S

#define AR_D_TXBLK_WRITE_COMMAND_S   24

Definition at line 617 of file reg.h.

AR_D_GBL_IFS_SLOT

#define AR_D_GBL_IFS_SLOT   0x1070

Definition at line 619 of file reg.h.

Referenced by ar9002_hw_update_async_fifo(), and ath9k_hw_setslottime().

AR_D_GBL_IFS_SLOT_M

#define AR_D_GBL_IFS_SLOT_M   0x0000FFFF

Definition at line 620 of file reg.h.

AR_D_GBL_IFS_SLOT_RESV0

#define AR_D_GBL_IFS_SLOT_RESV0   0xFFFF0000

Definition at line 621 of file reg.h.

AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR

#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR   0x00000420

Definition at line 622 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_D_GBL_IFS_EIFS

#define AR_D_GBL_IFS_EIFS   0x10b0

Definition at line 624 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_D_GBL_IFS_EIFS_M

#define AR_D_GBL_IFS_EIFS_M   0x0000FFFF

Definition at line 625 of file reg.h.

AR_D_GBL_IFS_EIFS_RESV0

#define AR_D_GBL_IFS_EIFS_RESV0   0xFFFF0000

Definition at line 626 of file reg.h.

AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR

#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR   0x0000A5EB

Definition at line 627 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_D_GBL_IFS_MISC

#define AR_D_GBL_IFS_MISC   0x10f0

Definition at line 629 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL

#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL   0x00000007

Definition at line 630 of file reg.h.

AR_D_GBL_IFS_MISC_TURBO_MODE

#define AR_D_GBL_IFS_MISC_TURBO_MODE   0x00000008

Definition at line 631 of file reg.h.

AR_D_GBL_IFS_MISC_USEC_DURATION

#define AR_D_GBL_IFS_MISC_USEC_DURATION   0x000FFC00

Definition at line 632 of file reg.h.

AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY

#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY   0x00300000

Definition at line 633 of file reg.h.

AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS

#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS   0x01000000

Definition at line 634 of file reg.h.

AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN

#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN   0x06000000

Definition at line 635 of file reg.h.

AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND

#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND   0x08000000

Definition at line 636 of file reg.h.

AR_D_GBL_IFS_MISC_IGNORE_BACKOFF

#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF   0x10000000

Definition at line 637 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_D_FPCTL

#define AR_D_FPCTL   0x1230

Definition at line 639 of file reg.h.

AR_D_FPCTL_DCU

#define AR_D_FPCTL_DCU   0x0000000F

Definition at line 640 of file reg.h.

AR_D_FPCTL_DCU_S

#define AR_D_FPCTL_DCU_S   0

Definition at line 641 of file reg.h.

AR_D_FPCTL_PREFETCH_EN

#define AR_D_FPCTL_PREFETCH_EN   0x00000010

Definition at line 642 of file reg.h.

AR_D_FPCTL_BURST_PREFETCH

#define AR_D_FPCTL_BURST_PREFETCH   0x00007FE0

Definition at line 643 of file reg.h.

AR_D_FPCTL_BURST_PREFETCH_S

#define AR_D_FPCTL_BURST_PREFETCH_S   5

Definition at line 644 of file reg.h.

AR_D_TXPSE

#define AR_D_TXPSE   0x1270

Definition at line 646 of file reg.h.

AR_D_TXPSE_CTRL

#define AR_D_TXPSE_CTRL   0x000003FF

Definition at line 647 of file reg.h.

AR_D_TXPSE_RESV0

#define AR_D_TXPSE_RESV0   0x0000FC00

Definition at line 648 of file reg.h.

AR_D_TXPSE_STATUS

#define AR_D_TXPSE_STATUS   0x00010000

Definition at line 649 of file reg.h.

AR_D_TXPSE_RESV1

#define AR_D_TXPSE_RESV1   0xFFFE0000

Definition at line 650 of file reg.h.

AR_D_TXSLOTMASK

#define AR_D_TXSLOTMASK   0x12f0

Definition at line 652 of file reg.h.

AR_D_TXSLOTMASK_NUM

#define AR_D_TXSLOTMASK_NUM   0x0000000F

Definition at line 653 of file reg.h.

AR_CFG_LED

#define AR_CFG_LED   0x1f04

Definition at line 655 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_SCLK_RATE_IND

#define AR_CFG_SCLK_RATE_IND   0x00000003

Definition at line 656 of file reg.h.

AR_CFG_SCLK_RATE_IND_S

#define AR_CFG_SCLK_RATE_IND_S   0

Definition at line 657 of file reg.h.

AR_CFG_SCLK_32MHZ

#define AR_CFG_SCLK_32MHZ   0x00000000

Definition at line 658 of file reg.h.

AR_CFG_SCLK_4MHZ

#define AR_CFG_SCLK_4MHZ   0x00000001

Definition at line 659 of file reg.h.

AR_CFG_SCLK_1MHZ

#define AR_CFG_SCLK_1MHZ   0x00000002

Definition at line 660 of file reg.h.

AR_CFG_SCLK_32KHZ

#define AR_CFG_SCLK_32KHZ   0x00000003

Definition at line 661 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_LED_BLINK_SLOW [1/2]

#define AR_CFG_LED_BLINK_SLOW   0x00000008

Definition at line 662 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_LED_BLINK_THRESH_SEL [1/2]

#define AR_CFG_LED_BLINK_THRESH_SEL   0x00000070

Definition at line 663 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_LED_MODE_SEL

#define AR_CFG_LED_MODE_SEL   0x00000380

Definition at line 664 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_LED_MODE_SEL_S

#define AR_CFG_LED_MODE_SEL_S   7

Definition at line 665 of file reg.h.

AR_CFG_LED_POWER

#define AR_CFG_LED_POWER   0x00000280

Definition at line 666 of file reg.h.

AR_CFG_LED_POWER_S

#define AR_CFG_LED_POWER_S   7

Definition at line 667 of file reg.h.

AR_CFG_LED_NETWORK

#define AR_CFG_LED_NETWORK   0x00000300

Definition at line 668 of file reg.h.

AR_CFG_LED_NETWORK_S

#define AR_CFG_LED_NETWORK_S   7

Definition at line 669 of file reg.h.

AR_CFG_LED_MODE_PROP

#define AR_CFG_LED_MODE_PROP   0x0

Definition at line 670 of file reg.h.

AR_CFG_LED_MODE_RPROP

#define AR_CFG_LED_MODE_RPROP   0x1

Definition at line 671 of file reg.h.

AR_CFG_LED_MODE_SPLIT

#define AR_CFG_LED_MODE_SPLIT   0x2

Definition at line 672 of file reg.h.

AR_CFG_LED_MODE_RAND

#define AR_CFG_LED_MODE_RAND   0x3

Definition at line 673 of file reg.h.

AR_CFG_LED_MODE_POWER_OFF

#define AR_CFG_LED_MODE_POWER_OFF   0x4

Definition at line 674 of file reg.h.

AR_CFG_LED_MODE_POWER_ON

#define AR_CFG_LED_MODE_POWER_ON   0x5

Definition at line 675 of file reg.h.

AR_CFG_LED_MODE_NETWORK_OFF

#define AR_CFG_LED_MODE_NETWORK_OFF   0x4

Definition at line 676 of file reg.h.

AR_CFG_LED_MODE_NETWORK_ON

#define AR_CFG_LED_MODE_NETWORK_ON   0x6

Definition at line 677 of file reg.h.

AR_CFG_LED_ASSOC_CTL

#define AR_CFG_LED_ASSOC_CTL   0x00000c00

Definition at line 678 of file reg.h.

Referenced by ath9k_hw_reset().

AR_CFG_LED_ASSOC_CTL_S

#define AR_CFG_LED_ASSOC_CTL_S   10

Definition at line 679 of file reg.h.

AR_CFG_LED_ASSOC_NONE

#define AR_CFG_LED_ASSOC_NONE   0x0

Definition at line 680 of file reg.h.

AR_CFG_LED_ASSOC_ACTIVE

#define AR_CFG_LED_ASSOC_ACTIVE   0x1

Definition at line 681 of file reg.h.

AR_CFG_LED_ASSOC_PENDING

#define AR_CFG_LED_ASSOC_PENDING   0x2

Definition at line 682 of file reg.h.

AR_CFG_LED_BLINK_SLOW [2/2]

#define AR_CFG_LED_BLINK_SLOW   0x00000008

Definition at line 662 of file reg.h.

AR_CFG_LED_BLINK_SLOW_S

#define AR_CFG_LED_BLINK_SLOW_S   3

Definition at line 685 of file reg.h.

AR_CFG_LED_BLINK_THRESH_SEL [2/2]

#define AR_CFG_LED_BLINK_THRESH_SEL   0x00000070

Definition at line 663 of file reg.h.

AR_CFG_LED_BLINK_THRESH_SEL_S

#define AR_CFG_LED_BLINK_THRESH_SEL_S   4

Definition at line 688 of file reg.h.

AR_MAC_SLEEP

#define AR_MAC_SLEEP   0x1f00

Definition at line 690 of file reg.h.

AR_MAC_SLEEP_MAC_AWAKE

#define AR_MAC_SLEEP_MAC_AWAKE   0x00000000

Definition at line 691 of file reg.h.

AR_MAC_SLEEP_MAC_ASLEEP

#define AR_MAC_SLEEP_MAC_ASLEEP   0x00000001

Definition at line 692 of file reg.h.

AR_RC

#define AR_RC   0x4000

Definition at line 694 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), and ath9k_set_power_sleep().

AR_RC_AHB

#define AR_RC_AHB   0x00000001

Definition at line 695 of file reg.h.

Referenced by ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), and ath9k_set_power_sleep().

AR_RC_APB

#define AR_RC_APB   0x00000002

Definition at line 696 of file reg.h.

AR_RC_HOSTIF

#define AR_RC_HOSTIF   0x00000100

Definition at line 697 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_set_reset(), and ath9k_set_power_sleep().

AR_WA

#define AR_WA   (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)

Definition at line 699 of file reg.h.

Referenced by __ath9k_hw_init(), ar9002_hw_configpcipowersave(), ar9003_hw_configpcipowersave(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_set_reset_reg(), and ath9k_set_power_sleep().

AR_WA_BIT6

#define AR_WA_BIT6   (1 << 6)

Definition at line 700 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR_WA_BIT7

#define AR_WA_BIT7   (1 << 7)

Definition at line 701 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR_WA_BIT23

#define AR_WA_BIT23   (1 << 23)

Definition at line 702 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR_WA_D3_L1_DISABLE

#define AR_WA_D3_L1_DISABLE   (1 << 14)

Definition at line 703 of file reg.h.

Referenced by __ath9k_hw_init(), ar9002_hw_configpcipowersave(), and ath9k_set_power_sleep().

AR_WA_D3_TO_L1_DISABLE_REAL

#define AR_WA_D3_TO_L1_DISABLE_REAL   (1 << 16)

Definition at line 704 of file reg.h.

AR_WA_ASPM_TIMER_BASED_DISABLE

#define AR_WA_ASPM_TIMER_BASED_DISABLE   (1 << 17)

Definition at line 705 of file reg.h.

Referenced by __ath9k_hw_init().

AR_WA_RESET_EN

#define AR_WA_RESET_EN   (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */

Definition at line 706 of file reg.h.

AR_WA_ANALOG_SHIFT

#define AR_WA_ANALOG_SHIFT   (1 << 20)

Definition at line 707 of file reg.h.

AR_WA_POR_SHORT

#define AR_WA_POR_SHORT   (1 << 21) /* PCI-E Phy reset control */

Definition at line 708 of file reg.h.

AR_WA_BIT22

#define AR_WA_BIT22   (1 << 22)

Definition at line 709 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR9285_WA_DEFAULT

#define AR9285_WA_DEFAULT   0x004a050b

Definition at line 710 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR9280_WA_DEFAULT

#define AR9280_WA_DEFAULT   0x0040073b

Definition at line 711 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR_WA_DEFAULT

#define AR_WA_DEFAULT   0x0000073f

Definition at line 712 of file reg.h.

Referenced by ar9002_hw_configpcipowersave().

AR_PM_STATE

#define AR_PM_STATE   0x4008

Definition at line 715 of file reg.h.

AR_PM_STATE_PME_D3COLD_VAUX

#define AR_PM_STATE_PME_D3COLD_VAUX   0x00100000

Definition at line 716 of file reg.h.

AR_HOST_TIMEOUT

#define AR_HOST_TIMEOUT   (AR_SREV_9340(ah) ? 0x4008 : 0x4018)

Definition at line 718 of file reg.h.

AR_HOST_TIMEOUT_APB_CNTR

#define AR_HOST_TIMEOUT_APB_CNTR   0x0000FFFF

Definition at line 719 of file reg.h.

AR_HOST_TIMEOUT_APB_CNTR_S

#define AR_HOST_TIMEOUT_APB_CNTR_S   0

Definition at line 720 of file reg.h.

AR_HOST_TIMEOUT_LCL_CNTR

#define AR_HOST_TIMEOUT_LCL_CNTR   0xFFFF0000

Definition at line 721 of file reg.h.

AR_HOST_TIMEOUT_LCL_CNTR_S

#define AR_HOST_TIMEOUT_LCL_CNTR_S   16

Definition at line 722 of file reg.h.

AR_EEPROM

#define AR_EEPROM   0x401c

Definition at line 724 of file reg.h.

AR_EEPROM_ABSENT

#define AR_EEPROM_ABSENT   0x00000100

Definition at line 725 of file reg.h.

AR_EEPROM_CORRUPT

#define AR_EEPROM_CORRUPT   0x00000200

Definition at line 726 of file reg.h.

AR_EEPROM_PROT_MASK

#define AR_EEPROM_PROT_MASK   0x03FFFC00

Definition at line 727 of file reg.h.

AR_EEPROM_PROT_MASK_S

#define AR_EEPROM_PROT_MASK_S   10

Definition at line 728 of file reg.h.

EEPROM_PROTECT_RP_0_31

#define EEPROM_PROTECT_RP_0_31   0x0001

Definition at line 730 of file reg.h.

EEPROM_PROTECT_WP_0_31

#define EEPROM_PROTECT_WP_0_31   0x0002

Definition at line 731 of file reg.h.

EEPROM_PROTECT_RP_32_63

#define EEPROM_PROTECT_RP_32_63   0x0004

Definition at line 732 of file reg.h.

EEPROM_PROTECT_WP_32_63

#define EEPROM_PROTECT_WP_32_63   0x0008

Definition at line 733 of file reg.h.

EEPROM_PROTECT_RP_64_127

#define EEPROM_PROTECT_RP_64_127   0x0010

Definition at line 734 of file reg.h.

EEPROM_PROTECT_WP_64_127

#define EEPROM_PROTECT_WP_64_127   0x0020

Definition at line 735 of file reg.h.

EEPROM_PROTECT_RP_128_191

#define EEPROM_PROTECT_RP_128_191   0x0040

Definition at line 736 of file reg.h.

EEPROM_PROTECT_WP_128_191

#define EEPROM_PROTECT_WP_128_191   0x0080

Definition at line 737 of file reg.h.

EEPROM_PROTECT_RP_192_255

#define EEPROM_PROTECT_RP_192_255   0x0100

Definition at line 738 of file reg.h.

EEPROM_PROTECT_WP_192_255

#define EEPROM_PROTECT_WP_192_255   0x0200

Definition at line 739 of file reg.h.

EEPROM_PROTECT_RP_256_511

#define EEPROM_PROTECT_RP_256_511   0x0400

Definition at line 740 of file reg.h.

EEPROM_PROTECT_WP_256_511

#define EEPROM_PROTECT_WP_256_511   0x0800

Definition at line 741 of file reg.h.

EEPROM_PROTECT_RP_512_1023

#define EEPROM_PROTECT_RP_512_1023   0x1000

Definition at line 742 of file reg.h.

EEPROM_PROTECT_WP_512_1023

#define EEPROM_PROTECT_WP_512_1023   0x2000

Definition at line 743 of file reg.h.

EEPROM_PROTECT_RP_1024_2047

#define EEPROM_PROTECT_RP_1024_2047   0x4000

Definition at line 744 of file reg.h.

EEPROM_PROTECT_WP_1024_2047

#define EEPROM_PROTECT_WP_1024_2047   0x8000

Definition at line 745 of file reg.h.

AR_SREV

#define AR_SREV

Value:

        ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
                                        ? 0x400c : 0x4020))

Definition at line 747 of file reg.h.

#define AR_SREV \
        ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
                                        ? 0x400c : 0x4020))

Referenced by ath9k_hw_read_revisions().

AR_SREV_ID

#define AR_SREV_ID    ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)

Definition at line 751 of file reg.h.

#define AR_SREV_ID \
        ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)

Referenced by ath9k_hw_read_revisions().

AR_SREV_VERSION

#define AR_SREV_VERSION   0x000000F0

Definition at line 753 of file reg.h.

Referenced by ath9k_hw_read_revisions().

AR_SREV_VERSION_S

#define AR_SREV_VERSION_S   4

Definition at line 754 of file reg.h.

AR_SREV_REVISION

#define AR_SREV_REVISION   0x00000007

Definition at line 755 of file reg.h.

Referenced by ath9k_hw_read_revisions().

AR_SREV_ID2

#define AR_SREV_ID2   0xFFFFFFFF

Definition at line 757 of file reg.h.

AR_SREV_VERSION2

#define AR_SREV_VERSION2   0xFFFC0000

Definition at line 758 of file reg.h.

Referenced by ath9k_hw_read_revisions().

AR_SREV_VERSION2_S

#define AR_SREV_VERSION2_S   18

Definition at line 759 of file reg.h.

AR_SREV_TYPE2

#define AR_SREV_TYPE2   0x0003F000

Definition at line 760 of file reg.h.

AR_SREV_TYPE2_S

#define AR_SREV_TYPE2_S   12

Definition at line 761 of file reg.h.

Referenced by ath9k_hw_read_revisions().

AR_SREV_TYPE2_CHAIN

#define AR_SREV_TYPE2_CHAIN   0x00001000

Definition at line 762 of file reg.h.

AR_SREV_TYPE2_HOST_MODE

#define AR_SREV_TYPE2_HOST_MODE   0x00002000

Definition at line 763 of file reg.h.

Referenced by ath9k_hw_read_revisions().

AR_SREV_REVISION2

#define AR_SREV_REVISION2   0x00000F00

Definition at line 764 of file reg.h.

Referenced by ath9k_hw_read_revisions().

AR_SREV_REVISION2_S

#define AR_SREV_REVISION2_S   8

Definition at line 765 of file reg.h.

AR_SREV_VERSION_5416_PCI

#define AR_SREV_VERSION_5416_PCI   0xD

Definition at line 767 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_VERSION_5416_PCIE

#define AR_SREV_VERSION_5416_PCIE   0xC

Definition at line 768 of file reg.h.

Referenced by __ath9k_hw_init(), and ath9k_hw_read_revisions().

AR_SREV_REVISION_5416_10

#define AR_SREV_REVISION_5416_10   0

Definition at line 769 of file reg.h.

Referenced by ar5008_hw_init_chain_masks().

AR_SREV_REVISION_5416_20

#define AR_SREV_REVISION_5416_20   1

Definition at line 770 of file reg.h.

AR_SREV_REVISION_5416_22

#define AR_SREV_REVISION_5416_22   2

Definition at line 771 of file reg.h.

AR_SREV_VERSION_9100

#define AR_SREV_VERSION_9100   0x14

Definition at line 772 of file reg.h.

Referenced by __ath9k_hw_init(), and ath9k_hw_read_revisions().

AR_SREV_VERSION_9160

#define AR_SREV_VERSION_9160   0x40

Definition at line 773 of file reg.h.

Referenced by __ath9k_hw_init(), ath9k_hw_4k_set_addac(), and ath9k_hw_def_set_addac().

AR_SREV_REVISION_9160_10

#define AR_SREV_REVISION_9160_10   0

Definition at line 774 of file reg.h.

AR_SREV_REVISION_9160_11

#define AR_SREV_REVISION_9160_11   1

Definition at line 775 of file reg.h.

AR_SREV_VERSION_9280

#define AR_SREV_VERSION_9280   0x80

Definition at line 776 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_REVISION_9280_10

#define AR_SREV_REVISION_9280_10   0

Definition at line 777 of file reg.h.

AR_SREV_REVISION_9280_20

#define AR_SREV_REVISION_9280_20   1

Definition at line 778 of file reg.h.

AR_SREV_REVISION_9280_21

#define AR_SREV_REVISION_9280_21   2

Definition at line 779 of file reg.h.

AR_SREV_VERSION_9285

#define AR_SREV_VERSION_9285   0xC0

Definition at line 780 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_REVISION_9285_10

#define AR_SREV_REVISION_9285_10   0

Definition at line 781 of file reg.h.

AR_SREV_REVISION_9285_11

#define AR_SREV_REVISION_9285_11   1

Definition at line 782 of file reg.h.

AR_SREV_REVISION_9285_12

#define AR_SREV_REVISION_9285_12   2

Definition at line 783 of file reg.h.

AR_SREV_VERSION_9287

#define AR_SREV_VERSION_9287   0x180

Definition at line 784 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_REVISION_9287_10

#define AR_SREV_REVISION_9287_10   0

Definition at line 785 of file reg.h.

AR_SREV_REVISION_9287_11

#define AR_SREV_REVISION_9287_11   1

Definition at line 786 of file reg.h.

AR_SREV_REVISION_9287_12

#define AR_SREV_REVISION_9287_12   2

Definition at line 787 of file reg.h.

AR_SREV_REVISION_9287_13

#define AR_SREV_REVISION_9287_13   3

Definition at line 788 of file reg.h.

AR_SREV_VERSION_9271

#define AR_SREV_VERSION_9271   0x140

Definition at line 789 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_REVISION_9271_10

#define AR_SREV_REVISION_9271_10   0

Definition at line 790 of file reg.h.

AR_SREV_REVISION_9271_11

#define AR_SREV_REVISION_9271_11   1

Definition at line 791 of file reg.h.

AR_SREV_VERSION_9300

#define AR_SREV_VERSION_9300   0x1c0

Definition at line 792 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_REVISION_9300_20

#define AR_SREV_REVISION_9300_20   2 /* 2.0 and 2.1 */

Definition at line 793 of file reg.h.

AR_SREV_VERSION_9485

#define AR_SREV_VERSION_9485   0x240

Definition at line 794 of file reg.h.

Referenced by __ath9k_hw_init().

AR_SREV_REVISION_9485_10

#define AR_SREV_REVISION_9485_10   0

Definition at line 795 of file reg.h.

AR_SREV_REVISION_9485_11

#define AR_SREV_REVISION_9485_11   1

Definition at line 796 of file reg.h.

AR_SREV_VERSION_9340

#define AR_SREV_VERSION_9340   0x300

Definition at line 797 of file reg.h.

Referenced by __ath9k_hw_init(), and ath9k_hw_read_revisions().

AR_SREV_5416

#define AR_SREV_5416

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
         ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))

Definition at line 799 of file reg.h.

#define AR_SREV_5416(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
         ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))

Referenced by ar5008_hw_force_bias(), ath9k_hw_disablepcie(), and ath9k_set_power_sleep().

AR_SREV_5416_20_OR_LATER

#define AR_SREV_5416_20_OR_LATER

(

_ah

)

Value:

        (((AR_SREV_5416(_ah)) && \
         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \
         ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

Definition at line 802 of file reg.h.

#define AR_SREV_5416_20_OR_LATER(_ah) \
        (((AR_SREV_5416(_ah)) && \
         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \
         ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

Referenced by ar5008_hw_override_ini(), ath9k_hw_def_set_board_values(), ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_set_4k_power_cal_table(), and ath9k_hw_set_def_power_cal_table().

AR_SREV_5416_22_OR_LATER

#define AR_SREV_5416_22_OR_LATER

(

_ah

)

Value:

        (((AR_SREV_5416(_ah)) && \
         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
         ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

Definition at line 806 of file reg.h.

#define AR_SREV_5416_22_OR_LATER(_ah) \
        (((AR_SREV_5416(_ah)) && \
         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
         ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

Referenced by ar5008_hw_process_ini().

AR_SREV_9100

#define AR_SREV_9100

(

ah

)

Value:

        ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)

Definition at line 811 of file reg.h.

#define AR_SREV_9100(ah) \
        ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)

Referenced by __ath9k_hw_init(), ar5008_hw_attach_phy_ops(), ar5008_hw_init_chain_masks(), ar5008_hw_override_ini(), ar5008_hw_set_channel(), ar9002_hw_get_isr(), ar9002_hw_init_cal(), ar9002_hw_init_cal_settings(), ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ath9k_hw_fill_cap_info(), ath9k_hw_init_defaults(), ath9k_hw_init_interrupt_masks(), ath9k_hw_intrpend(), ath9k_hw_post_init(), ath9k_hw_read_revisions(), ath9k_hw_reset(), ath9k_hw_reset_calvalid(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), and ath9k_set_power_sleep().

AR_SREV_9100_OR_LATER

#define AR_SREV_9100_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

Definition at line 813 of file reg.h.

#define AR_SREV_9100_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))

Referenced by ar9002_hw_init_mode_regs().

AR_SREV_9160

#define AR_SREV_9160

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))

Definition at line 816 of file reg.h.

#define AR_SREV_9160(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))

Referenced by __ath9k_hw_init(), and ar5008_hw_override_ini().

AR_SREV_9160_10_OR_LATER

#define AR_SREV_9160_10_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))

Definition at line 818 of file reg.h.

#define AR_SREV_9160_10_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))

Referenced by ar5008_hw_attach_phy_ops(), ar5008_hw_set_channel(), ar9002_hw_init_cal(), ar9002_hw_init_cal_settings(), ar9002_hw_init_mode_regs(), ath9k_hw_fill_cap_info(), ath9k_hw_reset(), and ath9k_hw_reset_calvalid().

AR_SREV_9160_11

#define AR_SREV_9160_11

(

_ah

)

Value:

        (AR_SREV_9160(_ah) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))

Definition at line 820 of file reg.h.

#define AR_SREV_9160_11(_ah) \
        (AR_SREV_9160(_ah) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))

Referenced by ar9002_hw_init_mode_regs().

AR_SREV_9280

#define AR_SREV_9280

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))

Definition at line 823 of file reg.h.

#define AR_SREV_9280(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))

Referenced by __ath9k_hw_init(), ar5008_hw_process_ini(), ar9002_hw_configpcipowersave(), ath9k_hw_chip_reset(), ath9k_hw_def_check_eeprom(), ath9k_hw_def_set_board_values(), ath9k_hw_fill_cap_info(), and ath9k_hw_reset().

AR_SREV_9280_20_OR_LATER

#define AR_SREV_9280_20_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))

Definition at line 825 of file reg.h.

#define AR_SREV_9280_20_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))

Referenced by __ath9k_hw_init(), ar5008_hw_override_ini(), ar5008_hw_set_rf_regs(), ar5008_hw_set_rfmode(), ar9002_hw_attach_ops(), ar9002_hw_configpcipowersave(), ar9002_hw_init_cal(), ar9002_hw_init_cal_settings(), ar9002_hw_init_mode_regs(), ath9k_adjust_pdadc_values(), ath9k_change_gain_boundary_setting(), ath9k_hw_4k_set_txpower(), ath9k_hw_ar9287_set_txpower(), ath9k_hw_def_set_board_values(), ath9k_hw_def_set_gain(), ath9k_hw_def_set_txpower(), ath9k_hw_fill_cap_info(), ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_gpio_cfg_output_mux(), ath9k_hw_gpio_get(), ath9k_hw_name(), and ath9k_hw_reset().

AR_SREV_9280_20

#define AR_SREV_9280_20

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))

Definition at line 827 of file reg.h.

#define AR_SREV_9280_20(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))

Referenced by ar9002_hw_compute_pll_control(), ar9002_hw_init_mode_gain_regs(), ath9k_hw_def_set_board_values(), and ath9k_hw_fill_cap_info().

AR_SREV_9285

#define AR_SREV_9285

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))

Definition at line 830 of file reg.h.

#define AR_SREV_9285(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))

Referenced by __ath9k_hw_init(), ar9002_hw_configpcipowersave(), ar9002_hw_do_getnf(), ar9002_hw_init_cal(), ar9002_hw_set11n_txdesc(), ar9002_hw_set_nf_limits(), ath9k_hw_4k_set_board_values(), ath9k_hw_eeprom_init(), ath9k_hw_fill_cap_info(), ath9k_hw_get_gain_boundaries_pdadcs(), and ath9k_hw_set_dma().

AR_SREV_9285_12_OR_LATER

#define AR_SREV_9285_12_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))

Definition at line 832 of file reg.h.

#define AR_SREV_9285_12_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))

Referenced by ar5008_hw_process_ini(), ar5008_hw_set_channel_regs(), ar9002_hw_init_cal(), ar9002_hw_init_mode_gain_regs(), ar9002_hw_init_mode_regs(), ar9002_hw_pa_cal(), ath9k_hw_check_alive(), ath9k_hw_fill_cap_info(), and ath9k_hw_gpio_get().

AR_SREV_9287

#define AR_SREV_9287

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))

Definition at line 835 of file reg.h.

#define AR_SREV_9287(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))

Referenced by ar9002_hw_configpcipowersave(), ar9002_hw_init_cal(), ar9002_hw_init_cal_settings(), ar9002_hw_set_nf_limits(), ath9k_hw_eeprom_init(), and ath9k_hw_get_gain_boundaries_pdadcs().

AR_SREV_9287_11_OR_LATER

#define AR_SREV_9287_11_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))

Definition at line 837 of file reg.h.

#define AR_SREV_9287_11_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))

Referenced by ar5008_hw_override_ini(), ar5008_hw_process_ini(), ar9002_hw_cck_chan14_spread(), ar9002_hw_init_cal(), ar9002_hw_init_mode_gain_regs(), ar9002_hw_init_mode_regs(), ar9002_hw_set_channel(), ath9k_hw_fill_cap_info(), and ath9k_hw_gpio_get().

AR_SREV_9287_11

#define AR_SREV_9287_11

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))

Definition at line 839 of file reg.h.

#define AR_SREV_9287_11(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))

AR_SREV_9287_12

#define AR_SREV_9287_12

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))

Definition at line 842 of file reg.h.

#define AR_SREV_9287_12(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))

AR_SREV_9287_12_OR_LATER

#define AR_SREV_9287_12_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))

Definition at line 845 of file reg.h.

#define AR_SREV_9287_12_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))

AR_SREV_9287_13_OR_LATER

#define AR_SREV_9287_13_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))

Definition at line 849 of file reg.h.

#define AR_SREV_9287_13_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
          ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))

Referenced by ar9002_hw_enable_async_fifo(), ar9002_hw_enable_wep_aggregation(), and ar9002_hw_update_async_fifo().

AR_SREV_9271

#define AR_SREV_9271

(

_ah

)

Value:

    (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)

Definition at line 854 of file reg.h.

#define AR_SREV_9271(_ah) \
    (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)

Referenced by __ath9k_hw_init(), ar5008_hw_override_ini(), ar5008_hw_process_ini(), ar9002_hw_configpcipowersave(), ar9002_hw_do_getnf(), ar9002_hw_init_cal(), ar9002_hw_init_mode_regs(), ar9002_hw_pa_cal(), ar9002_hw_set11n_txdesc(), ar9002_hw_set_nf_limits(), ath9k_hw_4k_set_board_values(), ath9k_hw_eeprom_init(), ath9k_hw_fill_cap_info(), ath9k_hw_get_gain_boundaries_pdadcs(), ath9k_hw_gpio_get(), ath9k_hw_init_pll(), ath9k_hw_reset(), ath9k_hw_set_dma(), ath9k_hw_set_gpio(), and ath9k_set_power_sleep().

AR_SREV_9271_10

#define AR_SREV_9271_10

(

_ah

)

Value:

    (AR_SREV_9271(_ah) && \
     ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))

Definition at line 856 of file reg.h.

#define AR_SREV_9271_10(_ah) \
    (AR_SREV_9271(_ah) && \
     ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))

Referenced by ar5008_hw_process_ini(), and ath9k_hw_4k_set_board_values().

AR_SREV_9271_11

#define AR_SREV_9271_11

(

_ah

)

Value:

    (AR_SREV_9271(_ah) && \
     ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))

Definition at line 859 of file reg.h.

#define AR_SREV_9271_11(_ah) \
    (AR_SREV_9271(_ah) && \
     ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))

AR_SREV_9300

#define AR_SREV_9300

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))

Definition at line 863 of file reg.h.

#define AR_SREV_9300(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))

AR_SREV_9300_20_OR_LATER

#define AR_SREV_9300_20_OR_LATER

(

_ah

)

Value:

        ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)

Definition at line 865 of file reg.h.

#define AR_SREV_9300_20_OR_LATER(_ah) \
        ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)

Referenced by __ath9k_hw_init(), ath9k_hw_ani_init(), ath9k_hw_attach_ops(), ath9k_hw_chip_test(), ath9k_hw_eeprom_init(), ath9k_hw_fill_cap_info(), ath9k_hw_gpio_get(), ath9k_hw_init_interrupt_masks(), ath9k_hw_post_init(), ath9k_hw_reset(), ath9k_hw_resettxqueue(), ath9k_hw_set_cck_nil(), ath9k_hw_set_dma(), ath9k_hw_set_interrupts(), ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_set_reset_reg(), ath9k_hw_stopdmarecv(), ath9k_set_power_sleep(), and use_new_ani().

AR_SREV_9485

#define AR_SREV_9485

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))

Definition at line 868 of file reg.h.

#define AR_SREV_9485(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))

Referenced by ar9003_hw_ant_ctrl_apply(), ar9003_hw_internal_regulator_apply(), ar9003_hw_set_channel(), ar9003_hw_spur_mitigate_mrc_cck(), ar9003_hw_tx_iqcal_load_avg_2_passes(), ar9003_hw_xpa_bias_level_apply(), ar9300_eeprom_restore_internal(), ath9k_hw_ar9300_set_board_values(), ath9k_hw_fill_cap_info(), ath9k_hw_init_pll(), ath9k_hw_set_cck_nil(), and ath_hw_pll_work().

AR_SREV_9485_10

#define AR_SREV_9485_10

(

_ah

)

Value:

        (AR_SREV_9485(_ah) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))

Definition at line 870 of file reg.h.

#define AR_SREV_9485_10(_ah) \
        (AR_SREV_9485(_ah) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))

Referenced by ath9k_hw_fill_cap_info().

AR_SREV_9485_11

#define AR_SREV_9485_11

(

_ah

)

Value:

        (AR_SREV_9485(_ah) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))

Definition at line 873 of file reg.h.

#define AR_SREV_9485_11(_ah) \
        (AR_SREV_9485(_ah) && \
         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))

Referenced by ar9003_hw_init_mode_regs(), ar9003_rx_gain_table_apply(), and ar9003_tx_gain_table_apply().

AR_SREV_9485_OR_LATER

#define AR_SREV_9485_OR_LATER

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))

Definition at line 876 of file reg.h.

#define AR_SREV_9485_OR_LATER(_ah) \
        (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))

Referenced by ar9003_hw_init_cal().

AR_SREV_9340

#define AR_SREV_9340

(

_ah

)

Value:

        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))

Definition at line 879 of file reg.h.

#define AR_SREV_9340(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))

Referenced by __ath9k_hw_init(), ar9003_hw_init_mode_regs(), ar9003_hw_process_ini(), ar9003_hw_set_channel(), ar9003_hw_spur_mitigate_mrc_cck(), ar9003_hw_xpa_bias_level_apply(), ar9003_rx_gain_table_apply(), ar9003_tx_gain_table_apply(), ath9k_hw_ar9300_set_board_values(), ath9k_hw_enable_interrupts(), ath9k_hw_init_interrupt_masks(), ath9k_hw_init_pll(), ath9k_hw_post_init(), ath9k_hw_reset(), and ath9k_hw_resettxqueue().

AR_SREV_9285E_20

#define AR_SREV_9285E_20

(

_ah

)

Value:

    (AR_SREV_9285_12_OR_LATER(_ah) && \
     ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))

Definition at line 882 of file reg.h.

#define AR_SREV_9285E_20(_ah) \
    (AR_SREV_9285_12_OR_LATER(_ah) && \
     ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))

Referenced by ar9002_hw_configpcipowersave(), ar9002_hw_init_mode_gain_regs(), and ar9285_hw_clc().

AR_DEVID_7010

#define AR_DEVID_7010

(

_ah

)

Value:

        (((_ah)->hw_version.usbdev == AR9280_USB) || \
         ((_ah)->hw_version.usbdev == AR9287_USB))

Definition at line 892 of file reg.h.

#define AR_DEVID_7010(_ah) \
        (((_ah)->hw_version.usbdev == AR9280_USB) || \
         ((_ah)->hw_version.usbdev == AR9287_USB))

Referenced by ath9k_hw_cfg_gpio_input(), ath9k_hw_cfg_output(), ath9k_hw_fill_cap_info(), ath9k_hw_gpio_get(), ath9k_hw_reset(), and ath9k_hw_set_gpio().

AR_RADIO_SREV_MAJOR

#define AR_RADIO_SREV_MAJOR   0xf0

Definition at line 896 of file reg.h.

Referenced by ar9002_hw_rf_claim(), and ath9k_hw_name().

AR_RAD5133_SREV_MAJOR

#define AR_RAD5133_SREV_MAJOR   0xc0

Definition at line 897 of file reg.h.

Referenced by ar9002_hw_rf_claim().

AR_RAD2133_SREV_MAJOR

#define AR_RAD2133_SREV_MAJOR   0xd0

Definition at line 898 of file reg.h.

Referenced by ar9002_hw_rf_claim().

AR_RAD5122_SREV_MAJOR

#define AR_RAD5122_SREV_MAJOR   0xe0

Definition at line 899 of file reg.h.

Referenced by ar9002_hw_rf_claim().

AR_RAD2122_SREV_MAJOR

#define AR_RAD2122_SREV_MAJOR   0xf0

Definition at line 900 of file reg.h.

Referenced by ar9002_hw_rf_claim().

AR_AHB_MODE

#define AR_AHB_MODE   0x4024

Definition at line 902 of file reg.h.

Referenced by ar9002_hw_update_async_fifo(), and ath9k_hw_set_dma().

AR_AHB_EXACT_WR_EN

#define AR_AHB_EXACT_WR_EN   0x00000000

Definition at line 903 of file reg.h.

AR_AHB_BUF_WR_EN

#define AR_AHB_BUF_WR_EN   0x00000001

Definition at line 904 of file reg.h.

AR_AHB_EXACT_RD_EN

#define AR_AHB_EXACT_RD_EN   0x00000000

Definition at line 905 of file reg.h.

AR_AHB_CACHELINE_RD_EN

#define AR_AHB_CACHELINE_RD_EN   0x00000002

Definition at line 906 of file reg.h.

AR_AHB_PREFETCH_RD_EN

#define AR_AHB_PREFETCH_RD_EN   0x00000004

Definition at line 907 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_AHB_PAGE_SIZE_1K

#define AR_AHB_PAGE_SIZE_1K   0x00000000

Definition at line 908 of file reg.h.

AR_AHB_PAGE_SIZE_2K

#define AR_AHB_PAGE_SIZE_2K   0x00000008

Definition at line 909 of file reg.h.

AR_AHB_PAGE_SIZE_4K

#define AR_AHB_PAGE_SIZE_4K   0x00000010

Definition at line 910 of file reg.h.

AR_AHB_CUSTOM_BURST_EN

#define AR_AHB_CUSTOM_BURST_EN   0x000000C0

Definition at line 911 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_AHB_CUSTOM_BURST_EN_S

#define AR_AHB_CUSTOM_BURST_EN_S   6

Definition at line 912 of file reg.h.

AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL

#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL   3

Definition at line 913 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_INTR_RTC_IRQ

#define AR_INTR_RTC_IRQ   0x00000001

Definition at line 915 of file reg.h.

AR_INTR_MAC_IRQ

#define AR_INTR_MAC_IRQ   0x00000002

Definition at line 916 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_enable_interrupts(), and ath9k_hw_intrpend().

AR_INTR_EEP_PROT_ACCESS

#define AR_INTR_EEP_PROT_ACCESS   0x00000004

Definition at line 917 of file reg.h.

AR_INTR_MAC_AWAKE

#define AR_INTR_MAC_AWAKE   0x00020000

Definition at line 918 of file reg.h.

AR_INTR_MAC_ASLEEP

#define AR_INTR_MAC_ASLEEP   0x00040000

Definition at line 919 of file reg.h.

AR_INTR_SPURIOUS

#define AR_INTR_SPURIOUS   0xFFFFFFFF

Definition at line 920 of file reg.h.

Referenced by ath9k_hw_intrpend().

AR_INTR_SYNC_CAUSE

#define AR_INTR_SYNC_CAUSE   (AR_SREV_9340(ah) ? 0x4010 : 0x4028)

Definition at line 923 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_init_interrupt_masks(), ath9k_hw_intrpend(), and ath9k_hw_set_reset().

AR_INTR_SYNC_CAUSE_CLR

#define AR_INTR_SYNC_CAUSE_CLR   (AR_SREV_9340(ah) ? 0x4010 : 0x4028)

Definition at line 924 of file reg.h.

Referenced by ar9002_hw_get_isr(), and ar9003_hw_get_isr().

AR_INTR_SYNC_ENABLE

#define AR_INTR_SYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4014 : 0x402c)

Definition at line 927 of file reg.h.

Referenced by ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ath9k_hw_init_interrupt_masks(), and ath9k_hw_set_reset().

AR_INTR_SYNC_ENABLE_GPIO

#define AR_INTR_SYNC_ENABLE_GPIO   0xFFFC0000

Definition at line 928 of file reg.h.

AR_INTR_SYNC_ENABLE_GPIO_S

#define AR_INTR_SYNC_ENABLE_GPIO_S   18

Definition at line 929 of file reg.h.

AR_INTR_ASYNC_MASK

#define AR_INTR_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x4018 : 0x4030)

Definition at line 967 of file reg.h.

Referenced by ath9k_hw_enable_interrupts().

AR_INTR_ASYNC_MASK_GPIO

#define AR_INTR_ASYNC_MASK_GPIO   0xFFFC0000

Definition at line 968 of file reg.h.

AR_INTR_ASYNC_MASK_GPIO_S

#define AR_INTR_ASYNC_MASK_GPIO_S   18

Definition at line 969 of file reg.h.

AR_INTR_SYNC_MASK

#define AR_INTR_SYNC_MASK   (AR_SREV_9340(ah) ? 0x401c : 0x4034)

Definition at line 971 of file reg.h.

Referenced by ath9k_hw_enable_interrupts(), and ath9k_hw_init_interrupt_masks().

AR_INTR_SYNC_MASK_GPIO

#define AR_INTR_SYNC_MASK_GPIO   0xFFFC0000

Definition at line 972 of file reg.h.

AR_INTR_SYNC_MASK_GPIO_S

#define AR_INTR_SYNC_MASK_GPIO_S   18

Definition at line 973 of file reg.h.

AR_INTR_ASYNC_CAUSE_CLR

#define AR_INTR_ASYNC_CAUSE_CLR   (AR_SREV_9340(ah) ? 0x4020 : 0x4038)

Definition at line 975 of file reg.h.

AR_INTR_ASYNC_CAUSE

#define AR_INTR_ASYNC_CAUSE   (AR_SREV_9340(ah) ? 0x4020 : 0x4038)

Definition at line 976 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), and ath9k_hw_intrpend().

AR_INTR_ASYNC_ENABLE

#define AR_INTR_ASYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4024 : 0x403c)

Definition at line 978 of file reg.h.

Referenced by ath9k_hw_disable_interrupts(), and ath9k_hw_enable_interrupts().

AR_INTR_ASYNC_ENABLE_GPIO

#define AR_INTR_ASYNC_ENABLE_GPIO   0xFFFC0000

Definition at line 979 of file reg.h.

AR_INTR_ASYNC_ENABLE_GPIO_S

#define AR_INTR_ASYNC_ENABLE_GPIO_S   18

Definition at line 980 of file reg.h.

AR_PCIE_SERDES

#define AR_PCIE_SERDES   0x4040

Definition at line 982 of file reg.h.

Referenced by ar9002_hw_configpcipowersave(), and ath9k_hw_disablepcie().

AR_PCIE_SERDES2

#define AR_PCIE_SERDES2   0x4044

Definition at line 983 of file reg.h.

Referenced by ar9002_hw_configpcipowersave(), and ath9k_hw_disablepcie().

AR_PCIE_PM_CTRL

#define AR_PCIE_PM_CTRL   (AR_SREV_9340(ah) ? 0x4004 : 0x4014)

Definition at line 984 of file reg.h.

Referenced by ar9002_hw_configpcipowersave(), and ar9003_hw_configpcipowersave().

AR_PCIE_PM_CTRL_ENA

#define AR_PCIE_PM_CTRL_ENA   0x00080000

Definition at line 985 of file reg.h.

Referenced by ar9002_hw_configpcipowersave(), and ar9003_hw_configpcipowersave().

AR_NUM_GPIO

#define AR_NUM_GPIO   14

Definition at line 987 of file reg.h.

Referenced by ath9k_hw_fill_cap_info().

AR928X_NUM_GPIO

#define AR928X_NUM_GPIO   10

Definition at line 988 of file reg.h.

Referenced by ath9k_hw_fill_cap_info().

AR9285_NUM_GPIO

#define AR9285_NUM_GPIO   12

Definition at line 989 of file reg.h.

Referenced by ath9k_hw_fill_cap_info().

AR9287_NUM_GPIO

#define AR9287_NUM_GPIO   11

Definition at line 990 of file reg.h.

AR9271_NUM_GPIO

#define AR9271_NUM_GPIO   16

Definition at line 991 of file reg.h.

Referenced by ath9k_hw_fill_cap_info().

AR9300_NUM_GPIO

#define AR9300_NUM_GPIO   17

Definition at line 992 of file reg.h.

AR7010_NUM_GPIO

#define AR7010_NUM_GPIO   16

Definition at line 993 of file reg.h.

Referenced by ath9k_hw_fill_cap_info().

AR_GPIO_IN_OUT

#define AR_GPIO_IN_OUT   (AR_SREV_9340(ah) ? 0x4028 : 0x4048)

Definition at line 995 of file reg.h.

Referenced by ath9k_hw_set_gpio().

AR_GPIO_IN_VAL

#define AR_GPIO_IN_VAL   0x0FFFC000

Definition at line 996 of file reg.h.

AR_GPIO_IN_VAL_S

#define AR_GPIO_IN_VAL_S   14

Definition at line 997 of file reg.h.

AR928X_GPIO_IN_VAL

#define AR928X_GPIO_IN_VAL   0x000FFC00

Definition at line 998 of file reg.h.

AR928X_GPIO_IN_VAL_S

#define AR928X_GPIO_IN_VAL_S   10

Definition at line 999 of file reg.h.

AR9285_GPIO_IN_VAL

#define AR9285_GPIO_IN_VAL   0x00FFF000

Definition at line 1000 of file reg.h.

AR9285_GPIO_IN_VAL_S

#define AR9285_GPIO_IN_VAL_S   12

Definition at line 1001 of file reg.h.

AR9287_GPIO_IN_VAL

#define AR9287_GPIO_IN_VAL   0x003FF800

Definition at line 1002 of file reg.h.

AR9287_GPIO_IN_VAL_S

#define AR9287_GPIO_IN_VAL_S   11

Definition at line 1003 of file reg.h.

AR9271_GPIO_IN_VAL

#define AR9271_GPIO_IN_VAL   0xFFFF0000

Definition at line 1004 of file reg.h.

AR9271_GPIO_IN_VAL_S

#define AR9271_GPIO_IN_VAL_S   16

Definition at line 1005 of file reg.h.

AR7010_GPIO_IN_VAL

#define AR7010_GPIO_IN_VAL   0x0000FFFF

Definition at line 1006 of file reg.h.

Referenced by ath9k_hw_gpio_get().

AR7010_GPIO_IN_VAL_S

#define AR7010_GPIO_IN_VAL_S   0

Definition at line 1007 of file reg.h.

AR_GPIO_IN

#define AR_GPIO_IN   (AR_SREV_9340(ah) ? 0x402c : 0x404c)

Definition at line 1009 of file reg.h.

Referenced by ath9k_hw_gpio_get().

AR9300_GPIO_IN_VAL

#define AR9300_GPIO_IN_VAL   0x0001FFFF

Definition at line 1010 of file reg.h.

Referenced by ath9k_hw_gpio_get().

AR9300_GPIO_IN_VAL_S

#define AR9300_GPIO_IN_VAL_S   0

Definition at line 1011 of file reg.h.

AR_GPIO_OE_OUT

#define AR_GPIO_OE_OUT

Value:

                                                  (AR_SREV_9340(ah) ? 0x4030 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))

Definition at line 1013 of file reg.h.

#define AR_GPIO_OE_OUT                           (AR_SREV_9340(ah) ? 0x4030 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))

Referenced by ath9k_hw_cfg_gpio_input(), and ath9k_hw_cfg_output().

AR_GPIO_OE_OUT_DRV

#define AR_GPIO_OE_OUT_DRV   0x3

Definition at line 1015 of file reg.h.

Referenced by ath9k_hw_cfg_gpio_input(), and ath9k_hw_cfg_output().

AR_GPIO_OE_OUT_DRV_NO

#define AR_GPIO_OE_OUT_DRV_NO   0x0

Definition at line 1016 of file reg.h.

Referenced by ath9k_hw_cfg_gpio_input().

AR_GPIO_OE_OUT_DRV_LOW

#define AR_GPIO_OE_OUT_DRV_LOW   0x1

Definition at line 1017 of file reg.h.

AR_GPIO_OE_OUT_DRV_HI

#define AR_GPIO_OE_OUT_DRV_HI   0x2

Definition at line 1018 of file reg.h.

AR_GPIO_OE_OUT_DRV_ALL

#define AR_GPIO_OE_OUT_DRV_ALL   0x3

Definition at line 1019 of file reg.h.

Referenced by ath9k_hw_cfg_output().

AR7010_GPIO_OE

#define AR7010_GPIO_OE   0x52000

Definition at line 1021 of file reg.h.

Referenced by ath9k_hw_cfg_gpio_input(), and ath9k_hw_cfg_output().

AR7010_GPIO_OE_MASK

#define AR7010_GPIO_OE_MASK   0x1

Definition at line 1022 of file reg.h.

Referenced by ath9k_hw_cfg_gpio_input(), and ath9k_hw_cfg_output().

AR7010_GPIO_OE_AS_OUTPUT

#define AR7010_GPIO_OE_AS_OUTPUT   0x0

Definition at line 1023 of file reg.h.

Referenced by ath9k_hw_cfg_output().

AR7010_GPIO_OE_AS_INPUT

#define AR7010_GPIO_OE_AS_INPUT   0x1

Definition at line 1024 of file reg.h.

Referenced by ath9k_hw_cfg_gpio_input().

AR7010_GPIO_IN

#define AR7010_GPIO_IN   0x52004

Definition at line 1025 of file reg.h.

Referenced by ath9k_hw_gpio_get().

AR7010_GPIO_OUT

#define AR7010_GPIO_OUT   0x52008

Definition at line 1026 of file reg.h.

Referenced by ath9k_hw_set_gpio().

AR7010_GPIO_SET

#define AR7010_GPIO_SET   0x5200C

Definition at line 1027 of file reg.h.

AR7010_GPIO_CLEAR

#define AR7010_GPIO_CLEAR   0x52010

Definition at line 1028 of file reg.h.

AR7010_GPIO_INT

#define AR7010_GPIO_INT   0x52014

Definition at line 1029 of file reg.h.

AR7010_GPIO_INT_TYPE

#define AR7010_GPIO_INT_TYPE   0x52018

Definition at line 1030 of file reg.h.

AR7010_GPIO_INT_POLARITY

#define AR7010_GPIO_INT_POLARITY   0x5201C

Definition at line 1031 of file reg.h.

AR7010_GPIO_PENDING

#define AR7010_GPIO_PENDING   0x52020

Definition at line 1032 of file reg.h.

AR7010_GPIO_INT_MASK

#define AR7010_GPIO_INT_MASK   0x52024

Definition at line 1033 of file reg.h.

AR7010_GPIO_FUNCTION

#define AR7010_GPIO_FUNCTION   0x52028

Definition at line 1034 of file reg.h.

AR_GPIO_INTR_POL

#define AR_GPIO_INTR_POL

Value:

                                                  (AR_SREV_9340(ah) ? 0x4038 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))

Definition at line 1036 of file reg.h.

#define AR_GPIO_INTR_POL                         (AR_SREV_9340(ah) ? 0x4038 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))

AR_GPIO_INTR_POL_VAL

#define AR_GPIO_INTR_POL_VAL   0x0001FFFF

Definition at line 1038 of file reg.h.

AR_GPIO_INTR_POL_VAL_S

#define AR_GPIO_INTR_POL_VAL_S   0

Definition at line 1039 of file reg.h.

AR_GPIO_INPUT_EN_VAL

#define AR_GPIO_INPUT_EN_VAL

Value:

                                                  (AR_SREV_9340(ah) ? 0x403c : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))

Definition at line 1041 of file reg.h.

#define AR_GPIO_INPUT_EN_VAL                     (AR_SREV_9340(ah) ? 0x403c : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))

Referenced by ath9k_hw_reset().

AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF

#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF   0x00000004

Definition at line 1043 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S

#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S   2

Definition at line 1044 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF

#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF   0x00000008

Definition at line 1045 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S

#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S   3

Definition at line 1046 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF

#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF   0x00000010

Definition at line 1047 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S

#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S   4

Definition at line 1048 of file reg.h.

AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF

#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF   0x00000080

Definition at line 1049 of file reg.h.

AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S

#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S   7

Definition at line 1050 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB

#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB   0x00000400

Definition at line 1051 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S

#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S   10

Definition at line 1052 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB

#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB   0x00001000

Definition at line 1053 of file reg.h.

AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S

#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S   12

Definition at line 1054 of file reg.h.

AR_GPIO_INPUT_EN_VAL_RFSILENT_BB

#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB   0x00008000

Definition at line 1055 of file reg.h.

AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S

#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S   15

Definition at line 1056 of file reg.h.

AR_GPIO_RTC_RESET_OVERRIDE_ENABLE

#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE   0x00010000

Definition at line 1057 of file reg.h.

AR_GPIO_JTAG_DISABLE

#define AR_GPIO_JTAG_DISABLE   0x00020000

Definition at line 1058 of file reg.h.

Referenced by ath9k_hw_reset().

AR_GPIO_INPUT_MUX1

#define AR_GPIO_INPUT_MUX1

Value:

                                                  (AR_SREV_9340(ah) ? 0x4040 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))

Definition at line 1060 of file reg.h.

#define AR_GPIO_INPUT_MUX1                       (AR_SREV_9340(ah) ? 0x4040 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))

AR_GPIO_INPUT_MUX1_BT_ACTIVE

#define AR_GPIO_INPUT_MUX1_BT_ACTIVE   0x000f0000

Definition at line 1062 of file reg.h.

AR_GPIO_INPUT_MUX1_BT_ACTIVE_S

#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S   16

Definition at line 1063 of file reg.h.

AR_GPIO_INPUT_MUX1_BT_PRIORITY

#define AR_GPIO_INPUT_MUX1_BT_PRIORITY   0x00000f00

Definition at line 1064 of file reg.h.

AR_GPIO_INPUT_MUX1_BT_PRIORITY_S

#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S   8

Definition at line 1065 of file reg.h.

AR_GPIO_INPUT_MUX2

#define AR_GPIO_INPUT_MUX2

Value:

                                                  (AR_SREV_9340(ah) ? 0x4044 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))

Definition at line 1067 of file reg.h.

#define AR_GPIO_INPUT_MUX2                       (AR_SREV_9340(ah) ? 0x4044 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))

AR_GPIO_INPUT_MUX2_CLK25

#define AR_GPIO_INPUT_MUX2_CLK25   0x0000000f

Definition at line 1069 of file reg.h.

AR_GPIO_INPUT_MUX2_CLK25_S

#define AR_GPIO_INPUT_MUX2_CLK25_S   0

Definition at line 1070 of file reg.h.

AR_GPIO_INPUT_MUX2_RFSILENT

#define AR_GPIO_INPUT_MUX2_RFSILENT   0x000000f0

Definition at line 1071 of file reg.h.

AR_GPIO_INPUT_MUX2_RFSILENT_S

#define AR_GPIO_INPUT_MUX2_RFSILENT_S   4

Definition at line 1072 of file reg.h.

AR_GPIO_INPUT_MUX2_RTC_RESET

#define AR_GPIO_INPUT_MUX2_RTC_RESET   0x00000f00

Definition at line 1073 of file reg.h.

AR_GPIO_INPUT_MUX2_RTC_RESET_S

#define AR_GPIO_INPUT_MUX2_RTC_RESET_S   8

Definition at line 1074 of file reg.h.

AR_GPIO_OUTPUT_MUX1

#define AR_GPIO_OUTPUT_MUX1

Value:

                                                  (AR_SREV_9340(ah) ? 0x4048 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))

Definition at line 1076 of file reg.h.

#define AR_GPIO_OUTPUT_MUX1                      (AR_SREV_9340(ah) ? 0x4048 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))

Referenced by ath9k_hw_gpio_cfg_output_mux().

AR_GPIO_OUTPUT_MUX2

#define AR_GPIO_OUTPUT_MUX2

Value:

                                                  (AR_SREV_9340(ah) ? 0x404c : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))

Definition at line 1078 of file reg.h.

#define AR_GPIO_OUTPUT_MUX2                      (AR_SREV_9340(ah) ? 0x404c : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))

Referenced by ath9k_hw_gpio_cfg_output_mux().

AR_GPIO_OUTPUT_MUX3

#define AR_GPIO_OUTPUT_MUX3

Value:

                                                  (AR_SREV_9340(ah) ? 0x4050 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))

Definition at line 1080 of file reg.h.

#define AR_GPIO_OUTPUT_MUX3                      (AR_SREV_9340(ah) ? 0x4050 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))

Referenced by ath9k_hw_gpio_cfg_output_mux().

AR_INPUT_STATE

#define AR_INPUT_STATE

Value:

                                                  (AR_SREV_9340(ah) ? 0x4054 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))

Definition at line 1083 of file reg.h.

#define AR_INPUT_STATE                           (AR_SREV_9340(ah) ? 0x4054 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))

AR_EEPROM_STATUS_DATA

#define AR_EEPROM_STATUS_DATA

Value:

                                                  (AR_SREV_9340(ah) ? 0x40c8 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))

Definition at line 1086 of file reg.h.

#define AR_EEPROM_STATUS_DATA                    (AR_SREV_9340(ah) ? 0x40c8 : \
                                                  (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))

Referenced by ath_pci_eeprom_read().

AR_EEPROM_STATUS_DATA_VAL

#define AR_EEPROM_STATUS_DATA_VAL   0x0000ffff

Definition at line 1088 of file reg.h.

Referenced by ath_pci_eeprom_read().

AR_EEPROM_STATUS_DATA_VAL_S

#define AR_EEPROM_STATUS_DATA_VAL_S   0

Definition at line 1089 of file reg.h.

AR_EEPROM_STATUS_DATA_BUSY

#define AR_EEPROM_STATUS_DATA_BUSY   0x00010000

Definition at line 1090 of file reg.h.

Referenced by ath_pci_eeprom_read().

AR_EEPROM_STATUS_DATA_BUSY_ACCESS

#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS   0x00020000

Definition at line 1091 of file reg.h.

AR_EEPROM_STATUS_DATA_PROT_ACCESS

#define AR_EEPROM_STATUS_DATA_PROT_ACCESS   0x00040000

Definition at line 1092 of file reg.h.

Referenced by ath_pci_eeprom_read().

AR_EEPROM_STATUS_DATA_ABSENT_ACCESS

#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS   0x00080000

Definition at line 1093 of file reg.h.

AR_OBS

#define AR_OBS

Value:

                                 (AR_SREV_9340(ah) ? 0x405c : \
                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))

Definition at line 1095 of file reg.h.

#define AR_OBS                  (AR_SREV_9340(ah) ? 0x405c : \
                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))

Referenced by ath9k_hw_reset().

AR_GPIO_PDPU

#define AR_GPIO_PDPU   (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)

Definition at line 1098 of file reg.h.

AR_PCIE_MSI

#define AR_PCIE_MSI

Value:

                                                 (AR_SREV_9340(ah) ? 0x40d8 : \
                                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))

Definition at line 1100 of file reg.h.

#define AR_PCIE_MSI                             (AR_SREV_9340(ah) ? 0x40d8 : \
                                                 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))

AR_PCIE_MSI_ENABLE

#define AR_PCIE_MSI_ENABLE   0x00000001

Definition at line 1102 of file reg.h.

AR_INTR_PRIO_SYNC_ENABLE

#define AR_INTR_PRIO_SYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)

Definition at line 1104 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks().

AR_INTR_PRIO_ASYNC_MASK

#define AR_INTR_PRIO_ASYNC_MASK   (AR_SREV_9340(ah) ? 0x408c : 0x40c8)

Definition at line 1105 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks().

AR_INTR_PRIO_SYNC_MASK

#define AR_INTR_PRIO_SYNC_MASK   (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)

Definition at line 1106 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks().

AR_INTR_PRIO_ASYNC_ENABLE

#define AR_INTR_PRIO_ASYNC_ENABLE   (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)

Definition at line 1107 of file reg.h.

Referenced by ath9k_hw_init_interrupt_masks().

AR_ENT_OTP

#define AR_ENT_OTP   0x40d8

Definition at line 1108 of file reg.h.

Referenced by ar9003_hw_init_cal(), and ath9k_hw_fill_cap_info().

AR_ENT_OTP_CHAIN2_DISABLE

#define AR_ENT_OTP_CHAIN2_DISABLE   0x00020000

Definition at line 1109 of file reg.h.

Referenced by ar9003_hw_init_cal().

AR_ENT_OTP_MPSD

#define AR_ENT_OTP_MPSD   0x00800000

Definition at line 1110 of file reg.h.

Referenced by ar9003_hw_set11n_aggr_first().

AR_CH0_BB_DPLL1

#define AR_CH0_BB_DPLL1   0x16180

Definition at line 1112 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL1_REFDIV

#define AR_CH0_BB_DPLL1_REFDIV   0xF8000000

Definition at line 1113 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL1_REFDIV_S

#define AR_CH0_BB_DPLL1_REFDIV_S   27

Definition at line 1114 of file reg.h.

AR_CH0_BB_DPLL1_NINI

#define AR_CH0_BB_DPLL1_NINI   0x07FC0000

Definition at line 1115 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL1_NINI_S

#define AR_CH0_BB_DPLL1_NINI_S   18

Definition at line 1116 of file reg.h.

AR_CH0_BB_DPLL1_NFRAC

#define AR_CH0_BB_DPLL1_NFRAC   0x0003FFFF

Definition at line 1117 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL1_NFRAC_S

#define AR_CH0_BB_DPLL1_NFRAC_S   0

Definition at line 1118 of file reg.h.

AR_CH0_BB_DPLL2

#define AR_CH0_BB_DPLL2   0x16184

Definition at line 1120 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL2_LOCAL_PLL

#define AR_CH0_BB_DPLL2_LOCAL_PLL   0x40000000

Definition at line 1121 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL2_LOCAL_PLL_S

#define AR_CH0_BB_DPLL2_LOCAL_PLL_S   30

Definition at line 1122 of file reg.h.

AR_CH0_DPLL2_KI

#define AR_CH0_DPLL2_KI   0x3C000000

Definition at line 1123 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_DPLL2_KI_S

#define AR_CH0_DPLL2_KI_S   26

Definition at line 1124 of file reg.h.

AR_CH0_DPLL2_KD

#define AR_CH0_DPLL2_KD   0x03F80000

Definition at line 1125 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_DPLL2_KD_S

#define AR_CH0_DPLL2_KD_S   19

Definition at line 1126 of file reg.h.

AR_CH0_BB_DPLL2_EN_NEGTRIG

#define AR_CH0_BB_DPLL2_EN_NEGTRIG   0x00040000

Definition at line 1127 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL2_EN_NEGTRIG_S

#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S   18

Definition at line 1128 of file reg.h.

AR_CH0_BB_DPLL2_PLL_PWD

#define AR_CH0_BB_DPLL2_PLL_PWD   0x00010000

Definition at line 1129 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL2_PLL_PWD_S

#define AR_CH0_BB_DPLL2_PLL_PWD_S   16

Definition at line 1130 of file reg.h.

AR_CH0_BB_DPLL2_OUTDIV

#define AR_CH0_BB_DPLL2_OUTDIV   0x0000E000

Definition at line 1131 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL2_OUTDIV_S

#define AR_CH0_BB_DPLL2_OUTDIV_S   13

Definition at line 1132 of file reg.h.

AR_CH0_BB_DPLL3

#define AR_CH0_BB_DPLL3   0x16188

Definition at line 1134 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL3_PHASE_SHIFT

#define AR_CH0_BB_DPLL3_PHASE_SHIFT   0x3F800000

Definition at line 1135 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_CH0_BB_DPLL3_PHASE_SHIFT_S

#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S   23

Definition at line 1136 of file reg.h.

AR_CH0_DDR_DPLL2

#define AR_CH0_DDR_DPLL2   0x16244

Definition at line 1138 of file reg.h.

AR_CH0_DDR_DPLL3

#define AR_CH0_DDR_DPLL3   0x16248

Definition at line 1139 of file reg.h.

AR_CH0_DPLL3_PHASE_SHIFT

#define AR_CH0_DPLL3_PHASE_SHIFT   0x3F800000

Definition at line 1140 of file reg.h.

AR_CH0_DPLL3_PHASE_SHIFT_S

#define AR_CH0_DPLL3_PHASE_SHIFT_S   23

Definition at line 1141 of file reg.h.

AR_PHY_CCA_NOM_VAL_2GHZ

#define AR_PHY_CCA_NOM_VAL_2GHZ   -118

Definition at line 1142 of file reg.h.

AR_RTC_9300_PLL_DIV

#define AR_RTC_9300_PLL_DIV   0x000003ff

Definition at line 1144 of file reg.h.

Referenced by ar9003_hw_compute_pll_control().

AR_RTC_9300_PLL_DIV_S

#define AR_RTC_9300_PLL_DIV_S   0

Definition at line 1145 of file reg.h.

AR_RTC_9300_PLL_REFDIV

#define AR_RTC_9300_PLL_REFDIV   0x00003C00

Definition at line 1146 of file reg.h.

Referenced by ar9003_hw_compute_pll_control().

AR_RTC_9300_PLL_REFDIV_S

#define AR_RTC_9300_PLL_REFDIV_S   10

Definition at line 1147 of file reg.h.

AR_RTC_9300_PLL_CLKSEL

#define AR_RTC_9300_PLL_CLKSEL   0x0000C000

Definition at line 1148 of file reg.h.

Referenced by ar9003_hw_compute_pll_control().

AR_RTC_9300_PLL_CLKSEL_S

#define AR_RTC_9300_PLL_CLKSEL_S   14

Definition at line 1149 of file reg.h.

AR_RTC_9160_PLL_DIV

#define AR_RTC_9160_PLL_DIV   0x000003ff

Definition at line 1151 of file reg.h.

Referenced by ar9002_hw_compute_pll_control(), and ar9160_hw_compute_pll_control().

AR_RTC_9160_PLL_DIV_S

#define AR_RTC_9160_PLL_DIV_S   0

Definition at line 1152 of file reg.h.

AR_RTC_9160_PLL_REFDIV

#define AR_RTC_9160_PLL_REFDIV   0x00003C00

Definition at line 1153 of file reg.h.

Referenced by ar9002_hw_compute_pll_control(), and ar9160_hw_compute_pll_control().

AR_RTC_9160_PLL_REFDIV_S

#define AR_RTC_9160_PLL_REFDIV_S   10

Definition at line 1154 of file reg.h.

AR_RTC_9160_PLL_CLKSEL

#define AR_RTC_9160_PLL_CLKSEL   0x0000C000

Definition at line 1155 of file reg.h.

Referenced by ar9002_hw_compute_pll_control(), and ar9160_hw_compute_pll_control().

AR_RTC_9160_PLL_CLKSEL_S

#define AR_RTC_9160_PLL_CLKSEL_S   14

Definition at line 1156 of file reg.h.

AR_RTC_BASE

#define AR_RTC_BASE   0x00020000

Definition at line 1158 of file reg.h.

AR_RTC_RC

#define AR_RTC_RC    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)

Definition at line 1159 of file reg.h.

#define AR_RTC_RC \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)

Referenced by ath9k_hw_set_reset().

AR_RTC_RC_M

#define AR_RTC_RC_M   0x00000003

Definition at line 1161 of file reg.h.

Referenced by ath9k_hw_set_reset().

AR_RTC_RC_MAC_WARM

#define AR_RTC_RC_MAC_WARM   0x00000001

Definition at line 1162 of file reg.h.

Referenced by ath9k_hw_set_reset().

AR_RTC_RC_MAC_COLD

#define AR_RTC_RC_MAC_COLD   0x00000002

Definition at line 1163 of file reg.h.

Referenced by ath9k_hw_set_reset().

AR_RTC_RC_COLD_RESET

#define AR_RTC_RC_COLD_RESET   0x00000004

Definition at line 1164 of file reg.h.

Referenced by ath9k_hw_set_reset().

AR_RTC_RC_WARM_RESET

#define AR_RTC_RC_WARM_RESET   0x00000008

Definition at line 1165 of file reg.h.

Referenced by ath9k_hw_set_reset().

AR_RTC_XTAL_CONTROL

#define AR_RTC_XTAL_CONTROL   0x7004

Definition at line 1168 of file reg.h.

AR_RTC_REG_CONTROL0

#define AR_RTC_REG_CONTROL0   0x7008

Definition at line 1171 of file reg.h.

Referenced by ar9003_hw_internal_regulator_apply().

AR_RTC_REG_CONTROL1

#define AR_RTC_REG_CONTROL1   0x700c

Definition at line 1174 of file reg.h.

Referenced by ar9003_hw_internal_regulator_apply().

AR_RTC_REG_CONTROL1_SWREG_PROGRAM

#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM   0x00000001

Definition at line 1175 of file reg.h.

Referenced by ar9003_hw_internal_regulator_apply().

AR_RTC_PLL_CONTROL

#define AR_RTC_PLL_CONTROL    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)

Definition at line 1177 of file reg.h.

#define AR_RTC_PLL_CONTROL \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)

Referenced by ath9k_hw_init_pll().

AR_RTC_PLL_CONTROL2

#define AR_RTC_PLL_CONTROL2   0x703c

Definition at line 1180 of file reg.h.

AR_RTC_PLL_DIV

#define AR_RTC_PLL_DIV   0x0000001f

Definition at line 1182 of file reg.h.

Referenced by ar5008_hw_compute_pll_control().

AR_RTC_PLL_DIV_S

#define AR_RTC_PLL_DIV_S   0

Definition at line 1183 of file reg.h.

AR_RTC_PLL_DIV2

#define AR_RTC_PLL_DIV2   0x00000020

Definition at line 1184 of file reg.h.

Referenced by ar5008_hw_compute_pll_control().

AR_RTC_PLL_REFDIV_5

#define AR_RTC_PLL_REFDIV_5   0x000000c0

Definition at line 1185 of file reg.h.

Referenced by ar5008_hw_compute_pll_control().

AR_RTC_PLL_CLKSEL

#define AR_RTC_PLL_CLKSEL   0x00000300

Definition at line 1186 of file reg.h.

Referenced by ar5008_hw_compute_pll_control().

AR_RTC_PLL_CLKSEL_S

#define AR_RTC_PLL_CLKSEL_S   8

Definition at line 1187 of file reg.h.

AR_RTC_PLL_BYPASS

#define AR_RTC_PLL_BYPASS   0x00010000

Definition at line 1188 of file reg.h.

PLL3

#define PLL3   0x16188

Definition at line 1190 of file reg.h.

Referenced by ar9003_get_pll_sqsum_dvc().

PLL3_DO_MEAS_MASK

#define PLL3_DO_MEAS_MASK   0x40000000

Definition at line 1191 of file reg.h.

Referenced by ar9003_get_pll_sqsum_dvc().

PLL4

#define PLL4   0x1618c

Definition at line 1192 of file reg.h.

Referenced by ar9003_get_pll_sqsum_dvc().

PLL4_MEAS_DONE

#define PLL4_MEAS_DONE   0x8

Definition at line 1193 of file reg.h.

Referenced by ar9003_get_pll_sqsum_dvc().

SQSUM_DVC_MASK

#define SQSUM_DVC_MASK   0x007ffff8

Definition at line 1194 of file reg.h.

Referenced by ar9003_get_pll_sqsum_dvc().

AR_RTC_RESET

#define AR_RTC_RESET    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)

Definition at line 1196 of file reg.h.

#define AR_RTC_RESET \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)

Referenced by ath9k_hw_set_power_awake(), ath9k_hw_set_reset_power_on(), and ath9k_set_power_sleep().

AR_RTC_RESET_EN

#define AR_RTC_RESET_EN   (0x00000001)

Definition at line 1198 of file reg.h.

Referenced by ath9k_hw_set_power_awake(), and ath9k_set_power_sleep().

AR_RTC_STATUS

#define AR_RTC_STATUS    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)

Definition at line 1200 of file reg.h.

#define AR_RTC_STATUS \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_set_power_awake(), and ath9k_hw_set_reset_power_on().

AR_RTC_STATUS_M

#define AR_RTC_STATUS_M    ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)

Definition at line 1203 of file reg.h.

#define AR_RTC_STATUS_M \
        ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_set_power_awake(), and ath9k_hw_set_reset_power_on().

AR_RTC_PM_STATUS_M

#define AR_RTC_PM_STATUS_M   0x0000000f

Definition at line 1206 of file reg.h.

AR_RTC_STATUS_SHUTDOWN

#define AR_RTC_STATUS_SHUTDOWN   0x00000001

Definition at line 1208 of file reg.h.

Referenced by ath9k_hw_set_power_awake().

AR_RTC_STATUS_ON

#define AR_RTC_STATUS_ON   0x00000002

Definition at line 1209 of file reg.h.

Referenced by ar9002_hw_get_isr(), ar9003_hw_get_isr(), ath9k_hw_set_power_awake(), and ath9k_hw_set_reset_power_on().

AR_RTC_STATUS_SLEEP

#define AR_RTC_STATUS_SLEEP   0x00000004

Definition at line 1210 of file reg.h.

AR_RTC_STATUS_WAKEUP

#define AR_RTC_STATUS_WAKEUP   0x00000008

Definition at line 1211 of file reg.h.

AR_RTC_SLEEP_CLK

#define AR_RTC_SLEEP_CLK    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)

Definition at line 1213 of file reg.h.

#define AR_RTC_SLEEP_CLK \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)

Referenced by ar9003_hw_internal_regulator_apply(), and ath9k_hw_init_pll().

AR_RTC_FORCE_DERIVED_CLK

#define AR_RTC_FORCE_DERIVED_CLK   0x2

Definition at line 1215 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_RTC_FORCE_SWREG_PRD

#define AR_RTC_FORCE_SWREG_PRD   0x00000004

Definition at line 1216 of file reg.h.

Referenced by ar9003_hw_internal_regulator_apply().

AR_RTC_FORCE_WAKE

#define AR_RTC_FORCE_WAKE    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)

Definition at line 1218 of file reg.h.

#define AR_RTC_FORCE_WAKE \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)

Referenced by ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_set_reset_reg(), and ath9k_set_power_sleep().

AR_RTC_FORCE_WAKE_EN

#define AR_RTC_FORCE_WAKE_EN   0x00000001

Definition at line 1220 of file reg.h.

Referenced by ath9k_hw_set_power_awake(), ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), ath9k_hw_set_reset_reg(), and ath9k_set_power_sleep().

AR_RTC_FORCE_WAKE_ON_INT

#define AR_RTC_FORCE_WAKE_ON_INT   0x00000002

Definition at line 1221 of file reg.h.

Referenced by ath9k_hw_set_reset(), ath9k_hw_set_reset_power_on(), and ath9k_hw_set_reset_reg().

AR_RTC_INTR_CAUSE

#define AR_RTC_INTR_CAUSE    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)

Definition at line 1224 of file reg.h.

#define AR_RTC_INTR_CAUSE \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)

AR_RTC_INTR_ENABLE

#define AR_RTC_INTR_ENABLE    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)

Definition at line 1227 of file reg.h.

#define AR_RTC_INTR_ENABLE \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)

AR_RTC_INTR_MASK

#define AR_RTC_INTR_MASK    ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)

Definition at line 1230 of file reg.h.

#define AR_RTC_INTR_MASK \
        ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)

AR_RTC_DERIVED_CLK

#define AR_RTC_DERIVED_CLK    (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)

Definition at line 1235 of file reg.h.

#define AR_RTC_DERIVED_CLK \
        (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)

Referenced by ath9k_hw_init_pll(), and ath9k_hw_set_reset().

AR_RTC_DERIVED_CLK_PERIOD

#define AR_RTC_DERIVED_CLK_PERIOD   0x0000fffe

Definition at line 1237 of file reg.h.

Referenced by ath9k_hw_set_reset().

AR_RTC_DERIVED_CLK_PERIOD_S

#define AR_RTC_DERIVED_CLK_PERIOD_S   1

Definition at line 1238 of file reg.h.

AR_SEQ_MASK

#define AR_SEQ_MASK   0x8060

Definition at line 1240 of file reg.h.

AR_AN_RF2G1_CH0

#define AR_AN_RF2G1_CH0   0x7810

Definition at line 1242 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH0_OB

#define AR_AN_RF2G1_CH0_OB   0x03800000

Definition at line 1243 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH0_OB_S

#define AR_AN_RF2G1_CH0_OB_S   23

Definition at line 1244 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH0_DB

#define AR_AN_RF2G1_CH0_DB   0x1C000000

Definition at line 1245 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH0_DB_S

#define AR_AN_RF2G1_CH0_DB_S   26

Definition at line 1246 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH0

#define AR_AN_RF5G1_CH0   0x7818

Definition at line 1248 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH0_OB5

#define AR_AN_RF5G1_CH0_OB5   0x00070000

Definition at line 1249 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH0_OB5_S

#define AR_AN_RF5G1_CH0_OB5_S   16

Definition at line 1250 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH0_DB5

#define AR_AN_RF5G1_CH0_DB5   0x00380000

Definition at line 1251 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH0_DB5_S

#define AR_AN_RF5G1_CH0_DB5_S   19

Definition at line 1252 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH1

#define AR_AN_RF2G1_CH1   0x7834

Definition at line 1254 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH1_OB

#define AR_AN_RF2G1_CH1_OB   0x03800000

Definition at line 1255 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH1_OB_S

#define AR_AN_RF2G1_CH1_OB_S   23

Definition at line 1256 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH1_DB

#define AR_AN_RF2G1_CH1_DB   0x1C000000

Definition at line 1257 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF2G1_CH1_DB_S

#define AR_AN_RF2G1_CH1_DB_S   26

Definition at line 1258 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH1

#define AR_AN_RF5G1_CH1   0x783C

Definition at line 1260 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH1_OB5

#define AR_AN_RF5G1_CH1_OB5   0x00070000

Definition at line 1261 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH1_OB5_S

#define AR_AN_RF5G1_CH1_OB5_S   16

Definition at line 1262 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH1_DB5

#define AR_AN_RF5G1_CH1_DB5   0x00380000

Definition at line 1263 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_RF5G1_CH1_DB5_S

#define AR_AN_RF5G1_CH1_DB5_S   19

Definition at line 1264 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP1

#define AR_AN_TOP1   0x7890

Definition at line 1266 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP1_DACIPMODE

#define AR_AN_TOP1_DACIPMODE   0x00040000

Definition at line 1267 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP1_DACIPMODE_S

#define AR_AN_TOP1_DACIPMODE_S   18

Definition at line 1268 of file reg.h.

AR_AN_TOP2

#define AR_AN_TOP2   0x7894

Definition at line 1270 of file reg.h.

Referenced by ar5008_hw_process_ini(), and ath9k_hw_def_set_board_values().

AR_AN_TOP2_XPABIAS_LVL

#define AR_AN_TOP2_XPABIAS_LVL   0xC0000000

Definition at line 1271 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP2_XPABIAS_LVL_S

#define AR_AN_TOP2_XPABIAS_LVL_S   30

Definition at line 1272 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP2_LOCALBIAS

#define AR_AN_TOP2_LOCALBIAS   0x00200000

Definition at line 1273 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP2_LOCALBIAS_S

#define AR_AN_TOP2_LOCALBIAS_S   21

Definition at line 1274 of file reg.h.

Referenced by ath9k_hw_def_set_board_values().

AR_AN_TOP2_PWDCLKIND

#define AR_AN_TOP2_PWDCLKIND   0x00400000

Definition at line 1275 of file reg.h.

Referenced by ar5008_hw_process_ini().

AR_AN_TOP2_PWDCLKIND_S

#define AR_AN_TOP2_PWDCLKIND_S   22

Definition at line 1276 of file reg.h.

AR_AN_SYNTH9

#define AR_AN_SYNTH9   0x7868

Definition at line 1278 of file reg.h.

Referenced by ar9002_hw_set_channel().

AR_AN_SYNTH9_REFDIVA

#define AR_AN_SYNTH9_REFDIVA   0xf8000000

Definition at line 1279 of file reg.h.

Referenced by ar9002_hw_set_channel().

AR_AN_SYNTH9_REFDIVA_S

#define AR_AN_SYNTH9_REFDIVA_S   27

Definition at line 1280 of file reg.h.

AR9285_AN_RF2G1

#define AR9285_AN_RF2G1   0x7820

Definition at line 1282 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G1_ENPACAL

#define AR9285_AN_RF2G1_ENPACAL   0x00000800

Definition at line 1283 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G1_ENPACAL_S

#define AR9285_AN_RF2G1_ENPACAL_S   11

Definition at line 1284 of file reg.h.

AR9285_AN_RF2G1_PDPADRV1

#define AR9285_AN_RF2G1_PDPADRV1   0x02000000

Definition at line 1285 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G1_PDPADRV1_S

#define AR9285_AN_RF2G1_PDPADRV1_S   25

Definition at line 1286 of file reg.h.

AR9285_AN_RF2G1_PDPADRV2

#define AR9285_AN_RF2G1_PDPADRV2   0x01000000

Definition at line 1287 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G1_PDPADRV2_S

#define AR9285_AN_RF2G1_PDPADRV2_S   24

Definition at line 1288 of file reg.h.

AR9285_AN_RF2G1_PDPAOUT

#define AR9285_AN_RF2G1_PDPAOUT   0x00800000

Definition at line 1289 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G1_PDPAOUT_S

#define AR9285_AN_RF2G1_PDPAOUT_S   23

Definition at line 1290 of file reg.h.

AR9285_AN_RF2G2

#define AR9285_AN_RF2G2   0x7824

Definition at line 1293 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G2_OFFCAL

#define AR9285_AN_RF2G2_OFFCAL   0x00001000

Definition at line 1294 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G2_OFFCAL_S

#define AR9285_AN_RF2G2_OFFCAL_S   12

Definition at line 1295 of file reg.h.

AR9285_AN_RF2G3

#define AR9285_AN_RF2G3   0x7828

Definition at line 1297 of file reg.h.

Referenced by ar9271_hw_pa_cal(), ar9285_hw_pa_cal(), and ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_PDVCCOMP

#define AR9285_AN_RF2G3_PDVCCOMP   0x02000000

Definition at line 1298 of file reg.h.

Referenced by ar9285_hw_pa_cal().

AR9285_AN_RF2G3_PDVCCOMP_S

#define AR9285_AN_RF2G3_PDVCCOMP_S   25

Definition at line 1299 of file reg.h.

AR9285_AN_RF2G3_OB_0

#define AR9285_AN_RF2G3_OB_0   0x00E00000

Definition at line 1300 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_0_S

#define AR9285_AN_RF2G3_OB_0_S   21

Definition at line 1301 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_1

#define AR9285_AN_RF2G3_OB_1   0x001C0000

Definition at line 1302 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_1_S

#define AR9285_AN_RF2G3_OB_1_S   18

Definition at line 1303 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_2

#define AR9285_AN_RF2G3_OB_2   0x00038000

Definition at line 1304 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_2_S

#define AR9285_AN_RF2G3_OB_2_S   15

Definition at line 1305 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_3

#define AR9285_AN_RF2G3_OB_3   0x00007000

Definition at line 1306 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_3_S

#define AR9285_AN_RF2G3_OB_3_S   12

Definition at line 1307 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_4

#define AR9285_AN_RF2G3_OB_4   0x00000E00

Definition at line 1308 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_OB_4_S

#define AR9285_AN_RF2G3_OB_4_S   9

Definition at line 1309 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_DB1_0

#define AR9285_AN_RF2G3_DB1_0   0x000001C0

Definition at line 1311 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_DB1_0_S

#define AR9285_AN_RF2G3_DB1_0_S   6

Definition at line 1312 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_DB1_1

#define AR9285_AN_RF2G3_DB1_1   0x00000038

Definition at line 1313 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_DB1_1_S

#define AR9285_AN_RF2G3_DB1_1_S   3

Definition at line 1314 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_DB1_2

#define AR9285_AN_RF2G3_DB1_2   0x00000007

Definition at line 1315 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G3_DB1_2_S

#define AR9285_AN_RF2G3_DB1_2_S   0

Definition at line 1316 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4

#define AR9285_AN_RF2G4   0x782C

Definition at line 1317 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB1_3

#define AR9285_AN_RF2G4_DB1_3   0xE0000000

Definition at line 1318 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB1_3_S

#define AR9285_AN_RF2G4_DB1_3_S   29

Definition at line 1319 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB1_4

#define AR9285_AN_RF2G4_DB1_4   0x1C000000

Definition at line 1320 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB1_4_S

#define AR9285_AN_RF2G4_DB1_4_S   26

Definition at line 1321 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_0

#define AR9285_AN_RF2G4_DB2_0   0x03800000

Definition at line 1323 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_0_S

#define AR9285_AN_RF2G4_DB2_0_S   23

Definition at line 1324 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_1

#define AR9285_AN_RF2G4_DB2_1   0x00700000

Definition at line 1325 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_1_S

#define AR9285_AN_RF2G4_DB2_1_S   20

Definition at line 1326 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_2

#define AR9285_AN_RF2G4_DB2_2   0x000E0000

Definition at line 1327 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_2_S

#define AR9285_AN_RF2G4_DB2_2_S   17

Definition at line 1328 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_3

#define AR9285_AN_RF2G4_DB2_3   0x0001C000

Definition at line 1329 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_3_S

#define AR9285_AN_RF2G4_DB2_3_S   14

Definition at line 1330 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_4

#define AR9285_AN_RF2G4_DB2_4   0x00003800

Definition at line 1331 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G4_DB2_4_S

#define AR9285_AN_RF2G4_DB2_4_S   11

Definition at line 1332 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_RF2G5

#define AR9285_RF2G5   0x7830

Definition at line 1334 of file reg.h.

Referenced by ar9285_hw_clc().

AR9285_RF2G5_IC50TX

#define AR9285_RF2G5_IC50TX   0xfffff8ff

Definition at line 1335 of file reg.h.

Referenced by ar9285_hw_clc().

AR9285_RF2G5_IC50TX_SET

#define AR9285_RF2G5_IC50TX_SET   0x00000400

Definition at line 1336 of file reg.h.

Referenced by ar9285_hw_clc().

AR9285_RF2G5_IC50TX_XE_SET

#define AR9285_RF2G5_IC50TX_XE_SET   0x00000500

Definition at line 1337 of file reg.h.

Referenced by ar9285_hw_clc().

AR9285_RF2G5_IC50TX_CLEAR

#define AR9285_RF2G5_IC50TX_CLEAR   0x00000700

Definition at line 1338 of file reg.h.

AR9285_RF2G5_IC50TX_CLEAR_S

#define AR9285_RF2G5_IC50TX_CLEAR_S   8

Definition at line 1339 of file reg.h.

AR9271_AN_RF2G3_OB_cck

#define AR9271_AN_RF2G3_OB_cck   0x001C0000

Definition at line 1342 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_OB_cck_S

#define AR9271_AN_RF2G3_OB_cck_S   18

Definition at line 1343 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_OB_psk

#define AR9271_AN_RF2G3_OB_psk   0x00038000

Definition at line 1344 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_OB_psk_S

#define AR9271_AN_RF2G3_OB_psk_S   15

Definition at line 1345 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_OB_qam

#define AR9271_AN_RF2G3_OB_qam   0x00007000

Definition at line 1346 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_OB_qam_S

#define AR9271_AN_RF2G3_OB_qam_S   12

Definition at line 1347 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_DB_1

#define AR9271_AN_RF2G3_DB_1   0x00E00000

Definition at line 1349 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_DB_1_S

#define AR9271_AN_RF2G3_DB_1_S   21

Definition at line 1350 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G3_CCOMP

#define AR9271_AN_RF2G3_CCOMP   0xFFF

Definition at line 1352 of file reg.h.

Referenced by ar9271_hw_pa_cal().

AR9271_AN_RF2G3_CCOMP_S

#define AR9271_AN_RF2G3_CCOMP_S   0

Definition at line 1353 of file reg.h.

AR9271_AN_RF2G4_DB_2

#define AR9271_AN_RF2G4_DB_2   0xE0000000

Definition at line 1355 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9271_AN_RF2G4_DB_2_S

#define AR9271_AN_RF2G4_DB_2_S   29

Definition at line 1356 of file reg.h.

Referenced by ath9k_hw_4k_set_board_values().

AR9285_AN_RF2G6

#define AR9285_AN_RF2G6   0x7834

Definition at line 1358 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G6_CCOMP

#define AR9285_AN_RF2G6_CCOMP   0x00007800

Definition at line 1359 of file reg.h.

Referenced by ar9285_hw_pa_cal().

AR9285_AN_RF2G6_CCOMP_S

#define AR9285_AN_RF2G6_CCOMP_S   11

Definition at line 1360 of file reg.h.

AR9285_AN_RF2G6_OFFS

#define AR9285_AN_RF2G6_OFFS   0x03f00000

Definition at line 1361 of file reg.h.

Referenced by ar9285_hw_pa_cal().

AR9285_AN_RF2G6_OFFS_S

#define AR9285_AN_RF2G6_OFFS_S   20

Definition at line 1362 of file reg.h.

AR9271_AN_RF2G6_OFFS

#define AR9271_AN_RF2G6_OFFS   0x07f00000

Definition at line 1364 of file reg.h.

Referenced by ar9271_hw_pa_cal().

AR9271_AN_RF2G6_OFFS_S

#define AR9271_AN_RF2G6_OFFS_S   20

Definition at line 1365 of file reg.h.

AR9285_AN_RF2G7

#define AR9285_AN_RF2G7   0x7838

Definition at line 1367 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G7_PWDDB

#define AR9285_AN_RF2G7_PWDDB   0x00000002

Definition at line 1368 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G7_PWDDB_S

#define AR9285_AN_RF2G7_PWDDB_S   1

Definition at line 1369 of file reg.h.

AR9285_AN_RF2G7_PADRVGN2TAB0

#define AR9285_AN_RF2G7_PADRVGN2TAB0   0xE0000000

Definition at line 1370 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G7_PADRVGN2TAB0_S

#define AR9285_AN_RF2G7_PADRVGN2TAB0_S   29

Definition at line 1371 of file reg.h.

AR9285_AN_RF2G8

#define AR9285_AN_RF2G8   0x783C

Definition at line 1373 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G8_PADRVGN2TAB0

#define AR9285_AN_RF2G8_PADRVGN2TAB0   0x0001C000

Definition at line 1374 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RF2G8_PADRVGN2TAB0_S

#define AR9285_AN_RF2G8_PADRVGN2TAB0_S   14

Definition at line 1375 of file reg.h.

AR9285_AN_RF2G9

#define AR9285_AN_RF2G9   0x7840

Definition at line 1378 of file reg.h.

Referenced by ar9285_hw_pa_cal().

AR9285_AN_RXTXBB1

#define AR9285_AN_RXTXBB1   0x7854

Definition at line 1379 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RXTXBB1_PDRXTXBB1

#define AR9285_AN_RXTXBB1_PDRXTXBB1   0x00000020

Definition at line 1380 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RXTXBB1_PDRXTXBB1_S

#define AR9285_AN_RXTXBB1_PDRXTXBB1_S   5

Definition at line 1381 of file reg.h.

AR9285_AN_RXTXBB1_PDV2I

#define AR9285_AN_RXTXBB1_PDV2I   0x00000080

Definition at line 1382 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RXTXBB1_PDV2I_S

#define AR9285_AN_RXTXBB1_PDV2I_S   7

Definition at line 1383 of file reg.h.

AR9285_AN_RXTXBB1_PDDACIF

#define AR9285_AN_RXTXBB1_PDDACIF   0x00000100

Definition at line 1384 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RXTXBB1_PDDACIF_S

#define AR9285_AN_RXTXBB1_PDDACIF_S   8

Definition at line 1385 of file reg.h.

AR9285_AN_RXTXBB1_SPARE9

#define AR9285_AN_RXTXBB1_SPARE9   0x00000001

Definition at line 1386 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_RXTXBB1_SPARE9_S

#define AR9285_AN_RXTXBB1_SPARE9_S   0

Definition at line 1387 of file reg.h.

AR9285_AN_TOP2

#define AR9285_AN_TOP2   0x7868

Definition at line 1389 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_TOP3

#define AR9285_AN_TOP3   0x786c

Definition at line 1391 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_TOP3_XPABIAS_LVL

#define AR9285_AN_TOP3_XPABIAS_LVL   0x0000000C

Definition at line 1392 of file reg.h.

AR9285_AN_TOP3_XPABIAS_LVL_S

#define AR9285_AN_TOP3_XPABIAS_LVL_S   2

Definition at line 1393 of file reg.h.

AR9285_AN_TOP3_PWDDAC

#define AR9285_AN_TOP3_PWDDAC   0x00800000

Definition at line 1394 of file reg.h.

Referenced by ar9271_hw_pa_cal(), and ar9285_hw_pa_cal().

AR9285_AN_TOP3_PWDDAC_S

#define AR9285_AN_TOP3_PWDDAC_S   23

Definition at line 1395 of file reg.h.

AR9285_AN_TOP4

#define AR9285_AN_TOP4   0x7870

Definition at line 1397 of file reg.h.

AR9285_AN_TOP4_DEFAULT

#define AR9285_AN_TOP4_DEFAULT   0x10142c00

Definition at line 1398 of file reg.h.

AR9287_AN_RF2G3_CH0

#define AR9287_AN_RF2G3_CH0   0x7808

Definition at line 1400 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_CH1

#define AR9287_AN_RF2G3_CH1   0x785c

Definition at line 1401 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_DB1

#define AR9287_AN_RF2G3_DB1   0xE0000000

Definition at line 1402 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_DB1_S

#define AR9287_AN_RF2G3_DB1_S   29

Definition at line 1403 of file reg.h.

AR9287_AN_RF2G3_DB2

#define AR9287_AN_RF2G3_DB2   0x1C000000

Definition at line 1404 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_DB2_S

#define AR9287_AN_RF2G3_DB2_S   26

Definition at line 1405 of file reg.h.

AR9287_AN_RF2G3_OB_CCK

#define AR9287_AN_RF2G3_OB_CCK   0x03800000

Definition at line 1406 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_OB_CCK_S

#define AR9287_AN_RF2G3_OB_CCK_S   23

Definition at line 1407 of file reg.h.

AR9287_AN_RF2G3_OB_PSK

#define AR9287_AN_RF2G3_OB_PSK   0x00700000

Definition at line 1408 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_OB_PSK_S

#define AR9287_AN_RF2G3_OB_PSK_S   20

Definition at line 1409 of file reg.h.

AR9287_AN_RF2G3_OB_QAM

#define AR9287_AN_RF2G3_OB_QAM   0x000E0000

Definition at line 1410 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_OB_QAM_S

#define AR9287_AN_RF2G3_OB_QAM_S   17

Definition at line 1411 of file reg.h.

AR9287_AN_RF2G3_OB_PAL_OFF

#define AR9287_AN_RF2G3_OB_PAL_OFF   0x0001C000

Definition at line 1412 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_RF2G3_OB_PAL_OFF_S

#define AR9287_AN_RF2G3_OB_PAL_OFF_S   14

Definition at line 1413 of file reg.h.

AR9287_AN_TXPC0

#define AR9287_AN_TXPC0   0x7898

Definition at line 1415 of file reg.h.

Referenced by ar9002_olc_init().

AR9287_AN_TXPC0_TXPCMODE

#define AR9287_AN_TXPC0_TXPCMODE   0x0000C000

Definition at line 1416 of file reg.h.

Referenced by ar9002_olc_init().

AR9287_AN_TXPC0_TXPCMODE_S

#define AR9287_AN_TXPC0_TXPCMODE_S   14

Definition at line 1417 of file reg.h.

Referenced by ar9002_olc_init().

AR9287_AN_TXPC0_TXPCMODE_NORMAL

#define AR9287_AN_TXPC0_TXPCMODE_NORMAL   0

Definition at line 1418 of file reg.h.

AR9287_AN_TXPC0_TXPCMODE_TEST

#define AR9287_AN_TXPC0_TXPCMODE_TEST   1

Definition at line 1419 of file reg.h.

AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE

#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE   2

Definition at line 1420 of file reg.h.

Referenced by ar9002_olc_init().

AR9287_AN_TXPC0_TXPCMODE_ATBTEST

#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST   3

Definition at line 1421 of file reg.h.

AR9287_AN_TOP2

#define AR9287_AN_TOP2   0x78b4

Definition at line 1423 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_TOP2_XPABIAS_LVL

#define AR9287_AN_TOP2_XPABIAS_LVL   0xC0000000

Definition at line 1424 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9287_AN_TOP2_XPABIAS_LVL_S

#define AR9287_AN_TOP2_XPABIAS_LVL_S   30

Definition at line 1425 of file reg.h.

Referenced by ath9k_hw_ar9287_set_board_values().

AR9271_RESET_POWER_DOWN_CONTROL

#define AR9271_RESET_POWER_DOWN_CONTROL   0x50044

Definition at line 1428 of file reg.h.

Referenced by ath9k_hw_reset().

AR9271_RADIO_RF_RST

#define AR9271_RADIO_RF_RST   0x20

Definition at line 1429 of file reg.h.

Referenced by ath9k_hw_reset().

AR9271_GATE_MAC_CTL

#define AR9271_GATE_MAC_CTL   0x4000

Definition at line 1430 of file reg.h.

Referenced by ath9k_hw_reset().

AR_STA_ID0

#define AR_STA_ID0   0x8000

Definition at line 1432 of file reg.h.

Referenced by ath9k_hw_chip_test(), and ath9k_hw_reset().

AR_STA_ID1

#define AR_STA_ID1   0x8004

Definition at line 1433 of file reg.h.

Referenced by ath9k_hw_reset(), ath9k_hw_set_operating_mode(), ath9k_hw_set_power_awake(), and ath9k_set_power_sleep().

AR_STA_ID1_SADH_MASK

#define AR_STA_ID1_SADH_MASK   0x0000FFFF

Definition at line 1434 of file reg.h.

AR_STA_ID1_STA_AP

#define AR_STA_ID1_STA_AP   0x00010000

Definition at line 1435 of file reg.h.

Referenced by ath9k_hw_set_operating_mode().

AR_STA_ID1_ADHOC

#define AR_STA_ID1_ADHOC   0x00020000

Definition at line 1436 of file reg.h.

Referenced by ath9k_hw_set_operating_mode().

AR_STA_ID1_PWR_SAV

#define AR_STA_ID1_PWR_SAV   0x00040000

Definition at line 1437 of file reg.h.

Referenced by ath9k_hw_set_power_awake(), and ath9k_set_power_sleep().

AR_STA_ID1_KSRCHDIS

#define AR_STA_ID1_KSRCHDIS   0x00080000

Definition at line 1438 of file reg.h.

AR_STA_ID1_PCF

#define AR_STA_ID1_PCF   0x00100000

Definition at line 1439 of file reg.h.

AR_STA_ID1_USE_DEFANT

#define AR_STA_ID1_USE_DEFANT   0x00200000

Definition at line 1440 of file reg.h.

AR_STA_ID1_DEFANT_UPDATE

#define AR_STA_ID1_DEFANT_UPDATE   0x00400000

Definition at line 1441 of file reg.h.

AR_STA_ID1_AR9100_BA_FIX

#define AR_STA_ID1_AR9100_BA_FIX   0x00400000

Definition at line 1442 of file reg.h.

Referenced by ath9k_hw_init_defaults().

AR_STA_ID1_RTS_USE_DEF

#define AR_STA_ID1_RTS_USE_DEF   0x00800000

Definition at line 1443 of file reg.h.

Referenced by ath9k_hw_reset().

AR_STA_ID1_ACKCTS_6MB

#define AR_STA_ID1_ACKCTS_6MB   0x01000000

Definition at line 1444 of file reg.h.

Referenced by ath9k_hw_reset().

AR_STA_ID1_BASE_RATE_11B

#define AR_STA_ID1_BASE_RATE_11B   0x02000000

Definition at line 1445 of file reg.h.

Referenced by ath9k_hw_reset().

AR_STA_ID1_SECTOR_SELF_GEN

#define AR_STA_ID1_SECTOR_SELF_GEN   0x04000000

Definition at line 1446 of file reg.h.

AR_STA_ID1_CRPT_MIC_ENABLE

#define AR_STA_ID1_CRPT_MIC_ENABLE   0x08000000

Definition at line 1447 of file reg.h.

Referenced by ath9k_hw_init_defaults().

AR_STA_ID1_KSRCH_MODE

#define AR_STA_ID1_KSRCH_MODE   0x10000000

Definition at line 1448 of file reg.h.

Referenced by ath9k_hw_set_operating_mode().

AR_STA_ID1_PRESERVE_SEQNUM

#define AR_STA_ID1_PRESERVE_SEQNUM   0x20000000

Definition at line 1449 of file reg.h.

Referenced by ath9k_hw_reset().

AR_STA_ID1_CBCIV_ENDIAN

#define AR_STA_ID1_CBCIV_ENDIAN   0x40000000

Definition at line 1450 of file reg.h.

AR_STA_ID1_MCAST_KSRCH

#define AR_STA_ID1_MCAST_KSRCH   0x80000000

Definition at line 1451 of file reg.h.

Referenced by ath9k_hw_init_defaults().

AR_BSS_ID0

#define AR_BSS_ID0   0x8008

Definition at line 1453 of file reg.h.

Referenced by ath9k_hw_write_associd().

AR_BSS_ID1

#define AR_BSS_ID1   0x800C

Definition at line 1454 of file reg.h.

Referenced by ath9k_hw_write_associd().

AR_BSS_ID1_U16

#define AR_BSS_ID1_U16   0x0000FFFF

Definition at line 1455 of file reg.h.

AR_BSS_ID1_AID

#define AR_BSS_ID1_AID   0x07FF0000

Definition at line 1456 of file reg.h.

AR_BSS_ID1_AID_S

#define AR_BSS_ID1_AID_S   16

Definition at line 1457 of file reg.h.

Referenced by ath9k_hw_write_associd().

AR_BCN_RSSI_AVE

#define AR_BCN_RSSI_AVE   0x8010

Definition at line 1459 of file reg.h.

AR_BCN_RSSI_AVE_MASK

#define AR_BCN_RSSI_AVE_MASK   0x00000FFF

Definition at line 1460 of file reg.h.

AR_TIME_OUT

#define AR_TIME_OUT   0x8014

Definition at line 1462 of file reg.h.

Referenced by ar9002_hw_update_async_fifo(), ath9k_hw_set_ack_timeout(), and ath9k_hw_set_cts_timeout().

AR_TIME_OUT_ACK

#define AR_TIME_OUT_ACK   0x00003FFF

Definition at line 1463 of file reg.h.

Referenced by ath9k_hw_set_ack_timeout().

AR_TIME_OUT_ACK_S

#define AR_TIME_OUT_ACK_S   0

Definition at line 1464 of file reg.h.

AR_TIME_OUT_CTS

#define AR_TIME_OUT_CTS   0x3FFF0000

Definition at line 1465 of file reg.h.

Referenced by ath9k_hw_set_cts_timeout().

AR_TIME_OUT_CTS_S

#define AR_TIME_OUT_CTS_S   16

Definition at line 1466 of file reg.h.

AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR

#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR   0x16001D56

Definition at line 1467 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_RSSI_THR

#define AR_RSSI_THR   0x8018

Definition at line 1469 of file reg.h.

Referenced by ath9k_hw_reset().

AR_RSSI_THR_MASK

#define AR_RSSI_THR_MASK   0x000000FF

Definition at line 1470 of file reg.h.

AR_RSSI_THR_BM_THR

#define AR_RSSI_THR_BM_THR   0x0000FF00

Definition at line 1471 of file reg.h.

AR_RSSI_THR_BM_THR_S

#define AR_RSSI_THR_BM_THR_S   8

Definition at line 1472 of file reg.h.

AR_RSSI_BCN_WEIGHT

#define AR_RSSI_BCN_WEIGHT   0x1F000000

Definition at line 1473 of file reg.h.

AR_RSSI_BCN_WEIGHT_S

#define AR_RSSI_BCN_WEIGHT_S   24

Definition at line 1474 of file reg.h.

AR_RSSI_BCN_RSSI_RST

#define AR_RSSI_BCN_RSSI_RST   0x20000000

Definition at line 1475 of file reg.h.

AR_USEC

#define AR_USEC   0x801c

Definition at line 1477 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_USEC_USEC

#define AR_USEC_USEC   0x0000007F

Definition at line 1478 of file reg.h.

AR_USEC_TX_LAT

#define AR_USEC_TX_LAT   0x007FC000

Definition at line 1479 of file reg.h.

AR_USEC_TX_LAT_S

#define AR_USEC_TX_LAT_S   14

Definition at line 1480 of file reg.h.

AR_USEC_RX_LAT

#define AR_USEC_RX_LAT   0x1F800000

Definition at line 1481 of file reg.h.

AR_USEC_RX_LAT_S

#define AR_USEC_RX_LAT_S   23

Definition at line 1482 of file reg.h.

AR_USEC_ASYNC_FIFO_DUR

#define AR_USEC_ASYNC_FIFO_DUR   0x12e00074

Definition at line 1483 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_RESET_TSF

#define AR_RESET_TSF   0x8020

Definition at line 1485 of file reg.h.

AR_RESET_TSF_ONCE

#define AR_RESET_TSF_ONCE   0x01000000

Definition at line 1486 of file reg.h.

AR_MAX_CFP_DUR

#define AR_MAX_CFP_DUR   0x8038

Definition at line 1488 of file reg.h.

AR_CFP_VAL

#define AR_CFP_VAL   0x0000FFFF

Definition at line 1489 of file reg.h.

AR_RX_FILTER

#define AR_RX_FILTER   0x803C

Definition at line 1491 of file reg.h.

Referenced by ath9k_hw_getrxfilter(), and ath9k_hw_setrxfilter().

AR_MCAST_FIL0

#define AR_MCAST_FIL0   0x8040

Definition at line 1493 of file reg.h.

Referenced by ath9k_hw_setmcastfilter().

AR_MCAST_FIL1

#define AR_MCAST_FIL1   0x8044

Definition at line 1494 of file reg.h.

Referenced by ath9k_hw_setmcastfilter().

AR_DIAG_SW

#define AR_DIAG_SW   0x8048

Definition at line 1505 of file reg.h.

Referenced by ar5008_hw_override_ini(), ar9003_hw_override_ini(), ath9k_hw_abort_tx_dma(), ath9k_hw_abortpcurecv(), ath9k_hw_setrxabort(), ath9k_hw_startpcureceive(), and ath9k_hw_stopdmarecv().

AR_DIAG_CACHE_ACK

#define AR_DIAG_CACHE_ACK   0x00000001

Definition at line 1506 of file reg.h.

AR_DIAG_ACK_DIS

#define AR_DIAG_ACK_DIS   0x00000002

Definition at line 1507 of file reg.h.

AR_DIAG_CTS_DIS

#define AR_DIAG_CTS_DIS   0x00000004

Definition at line 1508 of file reg.h.

AR_DIAG_ENCRYPT_DIS

#define AR_DIAG_ENCRYPT_DIS   0x00000008

Definition at line 1509 of file reg.h.

AR_DIAG_DECRYPT_DIS

#define AR_DIAG_DECRYPT_DIS   0x00000010

Definition at line 1510 of file reg.h.

AR_DIAG_RX_DIS

#define AR_DIAG_RX_DIS   0x00000020 /* RX block */

Definition at line 1511 of file reg.h.

Referenced by ar5008_hw_override_ini(), ar9003_hw_override_ini(), ath9k_hw_abortpcurecv(), ath9k_hw_setrxabort(), and ath9k_hw_startpcureceive().

AR_DIAG_LOOP_BACK

#define AR_DIAG_LOOP_BACK   0x00000040

Definition at line 1512 of file reg.h.

AR_DIAG_CORR_FCS

#define AR_DIAG_CORR_FCS   0x00000080

Definition at line 1513 of file reg.h.

AR_DIAG_CHAN_INFO

#define AR_DIAG_CHAN_INFO   0x00000100

Definition at line 1514 of file reg.h.

AR_DIAG_SCRAM_SEED

#define AR_DIAG_SCRAM_SEED   0x0001FE00

Definition at line 1515 of file reg.h.

AR_DIAG_SCRAM_SEED_S

#define AR_DIAG_SCRAM_SEED_S   8

Definition at line 1516 of file reg.h.

AR_DIAG_FRAME_NV0

#define AR_DIAG_FRAME_NV0   0x00020000

Definition at line 1517 of file reg.h.

AR_DIAG_OBS_PT_SEL1

#define AR_DIAG_OBS_PT_SEL1   0x000C0000

Definition at line 1518 of file reg.h.

AR_DIAG_OBS_PT_SEL1_S

#define AR_DIAG_OBS_PT_SEL1_S   18

Definition at line 1519 of file reg.h.

AR_DIAG_FORCE_RX_CLEAR

#define AR_DIAG_FORCE_RX_CLEAR   0x00100000 /* force rx_clear high */

Definition at line 1520 of file reg.h.

AR_DIAG_IGNORE_VIRT_CS

#define AR_DIAG_IGNORE_VIRT_CS   0x00200000

Definition at line 1521 of file reg.h.

AR_DIAG_FORCE_CH_IDLE_HIGH

#define AR_DIAG_FORCE_CH_IDLE_HIGH   0x00400000

Definition at line 1522 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_DIAG_EIFS_CTRL_ENA

#define AR_DIAG_EIFS_CTRL_ENA   0x00800000

Definition at line 1523 of file reg.h.

AR_DIAG_DUAL_CHAIN_INFO

#define AR_DIAG_DUAL_CHAIN_INFO   0x01000000

Definition at line 1524 of file reg.h.

AR_DIAG_RX_ABORT

#define AR_DIAG_RX_ABORT   0x02000000 /* Force RX abort */

Definition at line 1525 of file reg.h.

Referenced by ar5008_hw_override_ini(), ar9003_hw_override_ini(), ath9k_hw_abortpcurecv(), ath9k_hw_setrxabort(), and ath9k_hw_startpcureceive().

AR_DIAG_SATURATE_CYCLE_CNT

#define AR_DIAG_SATURATE_CYCLE_CNT   0x04000000

Definition at line 1526 of file reg.h.

AR_DIAG_OBS_PT_SEL2

#define AR_DIAG_OBS_PT_SEL2   0x08000000

Definition at line 1527 of file reg.h.

AR_DIAG_RX_CLEAR_CTL_LOW

#define AR_DIAG_RX_CLEAR_CTL_LOW   0x10000000

Definition at line 1528 of file reg.h.

AR_DIAG_RX_CLEAR_EXT_LOW

#define AR_DIAG_RX_CLEAR_EXT_LOW   0x20000000

Definition at line 1529 of file reg.h.

AR_TSF_L32

#define AR_TSF_L32   0x804c

Definition at line 1531 of file reg.h.

AR_TSF_U32

#define AR_TSF_U32   0x8050

Definition at line 1532 of file reg.h.

AR_TST_ADDAC

#define AR_TST_ADDAC   0x8054

Definition at line 1534 of file reg.h.

AR_DEF_ANTENNA

#define AR_DEF_ANTENNA   0x8058

Definition at line 1535 of file reg.h.

Referenced by ath9k_hw_getdefantenna(), ath9k_hw_reset(), and ath9k_hw_setantenna().

AR_AES_MUTE_MASK0 [1/2]

#define AR_AES_MUTE_MASK0   0x805c

Definition at line 1537 of file reg.h.

AR_AES_MUTE_MASK0_FC [1/2]

#define AR_AES_MUTE_MASK0_FC   0x0000FFFF

Definition at line 1538 of file reg.h.

AR_AES_MUTE_MASK0_QOS [1/2]

#define AR_AES_MUTE_MASK0_QOS   0xFFFF0000

Definition at line 1539 of file reg.h.

AR_AES_MUTE_MASK0_QOS_S [1/2]

#define AR_AES_MUTE_MASK0_QOS_S   16

Definition at line 1540 of file reg.h.

AR_AES_MUTE_MASK1 [1/2]

#define AR_AES_MUTE_MASK1   0x8060

Definition at line 1542 of file reg.h.

Referenced by ath9k_hw_reset().

AR_AES_MUTE_MASK1_SEQ [1/2]

#define AR_AES_MUTE_MASK1_SEQ   0x0000FFFF

Definition at line 1543 of file reg.h.

AR_AES_MUTE_MASK1_FC_MGMT [1/2]

#define AR_AES_MUTE_MASK1_FC_MGMT   0xFFFF0000

Definition at line 1544 of file reg.h.

Referenced by ath9k_hw_reset().

AR_AES_MUTE_MASK1_FC_MGMT_S [1/2]

#define AR_AES_MUTE_MASK1_FC_MGMT_S   16

Definition at line 1545 of file reg.h.

AR_GATED_CLKS

#define AR_GATED_CLKS   0x8064

Definition at line 1547 of file reg.h.

AR_GATED_CLKS_TX

#define AR_GATED_CLKS_TX   0x00000002

Definition at line 1548 of file reg.h.

AR_GATED_CLKS_RX

#define AR_GATED_CLKS_RX   0x00000004

Definition at line 1549 of file reg.h.

AR_GATED_CLKS_REG

#define AR_GATED_CLKS_REG   0x00000008

Definition at line 1550 of file reg.h.

AR_OBS_BUS_CTRL

#define AR_OBS_BUS_CTRL   0x8068

Definition at line 1552 of file reg.h.

AR_OBS_BUS_SEL_1

#define AR_OBS_BUS_SEL_1   0x00040000

Definition at line 1553 of file reg.h.

AR_OBS_BUS_SEL_2

#define AR_OBS_BUS_SEL_2   0x00080000

Definition at line 1554 of file reg.h.

AR_OBS_BUS_SEL_3

#define AR_OBS_BUS_SEL_3   0x000C0000

Definition at line 1555 of file reg.h.

AR_OBS_BUS_SEL_4

#define AR_OBS_BUS_SEL_4   0x08040000

Definition at line 1556 of file reg.h.

AR_OBS_BUS_SEL_5

#define AR_OBS_BUS_SEL_5   0x08080000

Definition at line 1557 of file reg.h.

AR_OBS_BUS_1

#define AR_OBS_BUS_1   0x806c

Definition at line 1559 of file reg.h.

Referenced by ath9k_hw_check_alive(), and ath9k_hw_setrxabort().

AR_OBS_BUS_1_PCU

#define AR_OBS_BUS_1_PCU   0x00000001

Definition at line 1560 of file reg.h.

AR_OBS_BUS_1_RX_END

#define AR_OBS_BUS_1_RX_END   0x00000002

Definition at line 1561 of file reg.h.

AR_OBS_BUS_1_RX_WEP

#define AR_OBS_BUS_1_RX_WEP   0x00000004

Definition at line 1562 of file reg.h.

AR_OBS_BUS_1_RX_BEACON

#define AR_OBS_BUS_1_RX_BEACON   0x00000008

Definition at line 1563 of file reg.h.

AR_OBS_BUS_1_RX_FILTER

#define AR_OBS_BUS_1_RX_FILTER   0x00000010

Definition at line 1564 of file reg.h.

AR_OBS_BUS_1_TX_HCF

#define AR_OBS_BUS_1_TX_HCF   0x00000020

Definition at line 1565 of file reg.h.

AR_OBS_BUS_1_QUIET_TIME

#define AR_OBS_BUS_1_QUIET_TIME   0x00000040

Definition at line 1566 of file reg.h.

AR_OBS_BUS_1_CHAN_IDLE

#define AR_OBS_BUS_1_CHAN_IDLE   0x00000080

Definition at line 1567 of file reg.h.

AR_OBS_BUS_1_TX_HOLD

#define AR_OBS_BUS_1_TX_HOLD   0x00000100

Definition at line 1568 of file reg.h.

AR_OBS_BUS_1_TX_FRAME

#define AR_OBS_BUS_1_TX_FRAME   0x00000200

Definition at line 1569 of file reg.h.

AR_OBS_BUS_1_RX_FRAME

#define AR_OBS_BUS_1_RX_FRAME   0x00000400

Definition at line 1570 of file reg.h.

AR_OBS_BUS_1_RX_CLEAR

#define AR_OBS_BUS_1_RX_CLEAR   0x00000800

Definition at line 1571 of file reg.h.

AR_OBS_BUS_1_WEP_STATE

#define AR_OBS_BUS_1_WEP_STATE   0x0003F000

Definition at line 1572 of file reg.h.

AR_OBS_BUS_1_WEP_STATE_S

#define AR_OBS_BUS_1_WEP_STATE_S   12

Definition at line 1573 of file reg.h.

AR_OBS_BUS_1_RX_STATE

#define AR_OBS_BUS_1_RX_STATE   0x01F00000

Definition at line 1574 of file reg.h.

Referenced by ath9k_hw_setrxabort().

AR_OBS_BUS_1_RX_STATE_S

#define AR_OBS_BUS_1_RX_STATE_S   20

Definition at line 1575 of file reg.h.

AR_OBS_BUS_1_TX_STATE

#define AR_OBS_BUS_1_TX_STATE   0x7E000000

Definition at line 1576 of file reg.h.

AR_OBS_BUS_1_TX_STATE_S

#define AR_OBS_BUS_1_TX_STATE_S   25

Definition at line 1577 of file reg.h.

AR_LAST_TSTP

#define AR_LAST_TSTP   0x8080

Definition at line 1579 of file reg.h.

AR_NAV

#define AR_NAV   0x8084

Definition at line 1580 of file reg.h.

AR_RTS_OK

#define AR_RTS_OK   0x8088

Definition at line 1581 of file reg.h.

Referenced by ath9k_hw_update_mibstats().

AR_RTS_FAIL

#define AR_RTS_FAIL   0x808c

Definition at line 1582 of file reg.h.

Referenced by ath9k_hw_update_mibstats().

AR_ACK_FAIL

#define AR_ACK_FAIL   0x8090

Definition at line 1583 of file reg.h.

Referenced by ath9k_hw_update_mibstats().

AR_FCS_FAIL

#define AR_FCS_FAIL   0x8094

Definition at line 1584 of file reg.h.

Referenced by ath9k_hw_update_mibstats().

AR_BEACON_CNT

#define AR_BEACON_CNT   0x8098

Definition at line 1585 of file reg.h.

Referenced by ath9k_hw_update_mibstats().

AR_SLEEP1

#define AR_SLEEP1   0x80d4

Definition at line 1587 of file reg.h.

AR_SLEEP1_ASSUME_DTIM

#define AR_SLEEP1_ASSUME_DTIM   0x00080000

Definition at line 1588 of file reg.h.

AR_SLEEP1_CAB_TIMEOUT

#define AR_SLEEP1_CAB_TIMEOUT   0xFFE00000

Definition at line 1589 of file reg.h.

AR_SLEEP1_CAB_TIMEOUT_S

#define AR_SLEEP1_CAB_TIMEOUT_S   21

Definition at line 1590 of file reg.h.

AR_SLEEP2

#define AR_SLEEP2   0x80d8

Definition at line 1592 of file reg.h.

AR_SLEEP2_BEACON_TIMEOUT

#define AR_SLEEP2_BEACON_TIMEOUT   0xFFE00000

Definition at line 1593 of file reg.h.

AR_SLEEP2_BEACON_TIMEOUT_S

#define AR_SLEEP2_BEACON_TIMEOUT_S   21

Definition at line 1594 of file reg.h.

AR_TPC

#define AR_TPC   0x80e8

Definition at line 1596 of file reg.h.

AR_TPC_ACK

#define AR_TPC_ACK   0x0000003f

Definition at line 1597 of file reg.h.

AR_TPC_ACK_S

#define AR_TPC_ACK_S   0x00

Definition at line 1598 of file reg.h.

AR_TPC_CTS

#define AR_TPC_CTS   0x00003f00

Definition at line 1599 of file reg.h.

AR_TPC_CTS_S

#define AR_TPC_CTS_S   0x08

Definition at line 1600 of file reg.h.

AR_TPC_CHIRP

#define AR_TPC_CHIRP   0x003f0000

Definition at line 1601 of file reg.h.

AR_TPC_CHIRP_S

#define AR_TPC_CHIRP_S   0x16

Definition at line 1602 of file reg.h.

AR_QUIET1

#define AR_QUIET1   0x80fc

Definition at line 1604 of file reg.h.

AR_QUIET1_NEXT_QUIET_S

#define AR_QUIET1_NEXT_QUIET_S   0

Definition at line 1605 of file reg.h.

AR_QUIET1_NEXT_QUIET_M

#define AR_QUIET1_NEXT_QUIET_M   0x0000ffff

Definition at line 1606 of file reg.h.

AR_QUIET1_QUIET_ENABLE

#define AR_QUIET1_QUIET_ENABLE   0x00010000

Definition at line 1607 of file reg.h.

AR_QUIET1_QUIET_ACK_CTS_ENABLE

#define AR_QUIET1_QUIET_ACK_CTS_ENABLE   0x00020000

Definition at line 1608 of file reg.h.

AR_QUIET1_QUIET_ACK_CTS_ENABLE_S

#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S   17

Definition at line 1609 of file reg.h.

AR_QUIET2

#define AR_QUIET2   0x8100

Definition at line 1610 of file reg.h.

AR_QUIET2_QUIET_PERIOD_S

#define AR_QUIET2_QUIET_PERIOD_S   0

Definition at line 1611 of file reg.h.

AR_QUIET2_QUIET_PERIOD_M

#define AR_QUIET2_QUIET_PERIOD_M   0x0000ffff

Definition at line 1612 of file reg.h.

AR_QUIET2_QUIET_DUR_S

#define AR_QUIET2_QUIET_DUR_S   16

Definition at line 1613 of file reg.h.

AR_QUIET2_QUIET_DUR

#define AR_QUIET2_QUIET_DUR   0xffff0000

Definition at line 1614 of file reg.h.

AR_TSF_PARM

#define AR_TSF_PARM   0x8104

Definition at line 1616 of file reg.h.

AR_TSF_INCREMENT_M

#define AR_TSF_INCREMENT_M   0x000000ff

Definition at line 1617 of file reg.h.

AR_TSF_INCREMENT_S

#define AR_TSF_INCREMENT_S   0x00

Definition at line 1618 of file reg.h.

AR_QOS_NO_ACK

#define AR_QOS_NO_ACK   0x8108

Definition at line 1620 of file reg.h.

AR_QOS_NO_ACK_TWO_BIT

#define AR_QOS_NO_ACK_TWO_BIT   0x0000000f

Definition at line 1621 of file reg.h.

AR_QOS_NO_ACK_TWO_BIT_S

#define AR_QOS_NO_ACK_TWO_BIT_S   0

Definition at line 1622 of file reg.h.

AR_QOS_NO_ACK_BIT_OFF

#define AR_QOS_NO_ACK_BIT_OFF   0x00000070

Definition at line 1623 of file reg.h.

AR_QOS_NO_ACK_BIT_OFF_S

#define AR_QOS_NO_ACK_BIT_OFF_S   4

Definition at line 1624 of file reg.h.

AR_QOS_NO_ACK_BYTE_OFF

#define AR_QOS_NO_ACK_BYTE_OFF   0x00000180

Definition at line 1625 of file reg.h.

AR_QOS_NO_ACK_BYTE_OFF_S

#define AR_QOS_NO_ACK_BYTE_OFF_S   7

Definition at line 1626 of file reg.h.

AR_PHY_ERR

#define AR_PHY_ERR   0x810c

Definition at line 1628 of file reg.h.

Referenced by ath9k_hw_getrxfilter(), and ath9k_hw_setrxfilter().

AR_PHY_ERR_DCHIRP

#define AR_PHY_ERR_DCHIRP   0x00000008

Definition at line 1630 of file reg.h.

AR_PHY_ERR_RADAR

#define AR_PHY_ERR_RADAR   0x00000020

Definition at line 1631 of file reg.h.

Referenced by ath9k_hw_getrxfilter(), and ath9k_hw_setrxfilter().

AR_PHY_ERR_OFDM_TIMING

#define AR_PHY_ERR_OFDM_TIMING   0x00020000

Definition at line 1632 of file reg.h.

Referenced by ath9k_ani_reset(), ath9k_ani_reset_old(), ath9k_ani_restart(), ath9k_hw_ani_read_counters(), ath9k_hw_getrxfilter(), and ath9k_hw_setrxfilter().

AR_PHY_ERR_CCK_TIMING

#define AR_PHY_ERR_CCK_TIMING   0x02000000

Definition at line 1633 of file reg.h.

Referenced by ath9k_ani_reset(), ath9k_ani_reset_old(), ath9k_ani_restart(), ath9k_hw_ani_read_counters(), ath9k_hw_getrxfilter(), and ath9k_hw_setrxfilter().

AR_RXFIFO_CFG

#define AR_RXFIFO_CFG   0x8114

Definition at line 1635 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_MIC_QOS_CONTROL

#define AR_MIC_QOS_CONTROL   0x8118

Definition at line 1638 of file reg.h.

AR_MIC_QOS_SELECT

#define AR_MIC_QOS_SELECT   0x811c

Definition at line 1639 of file reg.h.

AR_PCU_MISC

#define AR_PCU_MISC   0x8120

Definition at line 1641 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma(), and ath9k_hw_init_global_settings().

AR_PCU_FORCE_BSSID_MATCH

#define AR_PCU_FORCE_BSSID_MATCH   0x00000001

Definition at line 1642 of file reg.h.

AR_PCU_MIC_NEW_LOC_ENA

#define AR_PCU_MIC_NEW_LOC_ENA   0x00000004

Definition at line 1643 of file reg.h.

Referenced by ath9k_hw_fill_cap_info(), and ath9k_init_crypto().

AR_PCU_TX_ADD_TSF

#define AR_PCU_TX_ADD_TSF   0x00000008

Definition at line 1644 of file reg.h.

AR_PCU_CCK_SIFS_MODE

#define AR_PCU_CCK_SIFS_MODE   0x00000010

Definition at line 1645 of file reg.h.

AR_PCU_RX_ANT_UPDT

#define AR_PCU_RX_ANT_UPDT   0x00000800

Definition at line 1646 of file reg.h.

AR_PCU_TXOP_TBTT_LIMIT_ENA

#define AR_PCU_TXOP_TBTT_LIMIT_ENA   0x00001000

Definition at line 1647 of file reg.h.

AR_PCU_MISS_BCN_IN_SLEEP

#define AR_PCU_MISS_BCN_IN_SLEEP   0x00004000

Definition at line 1648 of file reg.h.

AR_PCU_BUG_12306_FIX_ENA

#define AR_PCU_BUG_12306_FIX_ENA   0x00020000

Definition at line 1649 of file reg.h.

AR_PCU_FORCE_QUIET_COLL

#define AR_PCU_FORCE_QUIET_COLL   0x00040000

Definition at line 1650 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_PCU_TBTT_PROTECT

#define AR_PCU_TBTT_PROTECT   0x00200000

Definition at line 1651 of file reg.h.

AR_PCU_CLEAR_VMF

#define AR_PCU_CLEAR_VMF   0x01000000

Definition at line 1652 of file reg.h.

Referenced by ath9k_hw_abort_tx_dma().

AR_PCU_CLEAR_BA_VALID

#define AR_PCU_CLEAR_BA_VALID   0x04000000

Definition at line 1653 of file reg.h.

AR_PCU_ALWAYS_PERFORM_KEYSEARCH

#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH   0x10000000

Definition at line 1654 of file reg.h.

Referenced by ath9k_hw_fill_cap_info().

AR_PCU_BT_ANT_PREVENT_RX

#define AR_PCU_BT_ANT_PREVENT_RX   0x00100000

Definition at line 1656 of file reg.h.

AR_PCU_BT_ANT_PREVENT_RX_S

#define AR_PCU_BT_ANT_PREVENT_RX_S   20

Definition at line 1657 of file reg.h.

AR_FILT_OFDM

#define AR_FILT_OFDM   0x8124

Definition at line 1659 of file reg.h.

AR_FILT_OFDM_COUNT

#define AR_FILT_OFDM_COUNT   0x00FFFFFF

Definition at line 1660 of file reg.h.

AR_FILT_CCK

#define AR_FILT_CCK   0x8128

Definition at line 1662 of file reg.h.

AR_FILT_CCK_COUNT

#define AR_FILT_CCK_COUNT   0x00FFFFFF

Definition at line 1663 of file reg.h.

AR_PHY_ERR_1

#define AR_PHY_ERR_1   0x812c

Definition at line 1665 of file reg.h.

Referenced by ath9k_ani_restart(), and ath9k_hw_ani_read_counters().

AR_PHY_ERR_1_COUNT

#define AR_PHY_ERR_1_COUNT   0x00FFFFFF

Definition at line 1666 of file reg.h.

AR_PHY_ERR_MASK_1

#define AR_PHY_ERR_MASK_1   0x8130

Definition at line 1667 of file reg.h.

Referenced by ath9k_ani_reset(), ath9k_ani_reset_old(), ath9k_ani_restart(), and ath9k_hw_ani_read_counters().

AR_PHY_ERR_2

#define AR_PHY_ERR_2   0x8134

Definition at line 1669 of file reg.h.

Referenced by ath9k_ani_restart(), and ath9k_hw_ani_read_counters().

AR_PHY_ERR_2_COUNT

#define AR_PHY_ERR_2_COUNT   0x00FFFFFF

Definition at line 1670 of file reg.h.

AR_PHY_ERR_MASK_2

#define AR_PHY_ERR_MASK_2   0x8138

Definition at line 1671 of file reg.h.

Referenced by ath9k_ani_reset(), ath9k_ani_reset_old(), ath9k_ani_restart(), and ath9k_hw_ani_read_counters().

AR_PHY_COUNTMAX

#define AR_PHY_COUNTMAX   (3 << 22)

Definition at line 1673 of file reg.h.

Referenced by ath9k_ani_restart(), and ath9k_hw_ani_read_counters().

AR_MIBCNT_INTRMASK

#define AR_MIBCNT_INTRMASK   (3 << 22)

Definition at line 1674 of file reg.h.

AR_TSFOOR_THRESHOLD

#define AR_TSFOOR_THRESHOLD   0x813c

Definition at line 1676 of file reg.h.

AR_TSFOOR_THRESHOLD_VAL

#define AR_TSFOOR_THRESHOLD_VAL   0x0000FFFF

Definition at line 1677 of file reg.h.

AR_PHY_ERR_EIFS_MASK

#define AR_PHY_ERR_EIFS_MASK   0x8144

Definition at line 1679 of file reg.h.

AR_PHY_ERR_3

#define AR_PHY_ERR_3   0x8168

Definition at line 1681 of file reg.h.

AR_PHY_ERR_3_COUNT

#define AR_PHY_ERR_3_COUNT   0x00FFFFFF

Definition at line 1682 of file reg.h.

AR_PHY_ERR_MASK_3

#define AR_PHY_ERR_MASK_3   0x816c

Definition at line 1683 of file reg.h.

AR_BT_COEX_MODE

#define AR_BT_COEX_MODE   0x8170

Definition at line 1685 of file reg.h.

AR_BT_TIME_EXTEND

#define AR_BT_TIME_EXTEND   0x000000ff

Definition at line 1686 of file reg.h.

AR_BT_TIME_EXTEND_S

#define AR_BT_TIME_EXTEND_S   0

Definition at line 1687 of file reg.h.

AR_BT_TXSTATE_EXTEND

#define AR_BT_TXSTATE_EXTEND   0x00000100

Definition at line 1688 of file reg.h.

AR_BT_TXSTATE_EXTEND_S

#define AR_BT_TXSTATE_EXTEND_S   8

Definition at line 1689 of file reg.h.

AR_BT_TX_FRAME_EXTEND

#define AR_BT_TX_FRAME_EXTEND   0x00000200

Definition at line 1690 of file reg.h.

AR_BT_TX_FRAME_EXTEND_S

#define AR_BT_TX_FRAME_EXTEND_S   9

Definition at line 1691 of file reg.h.

AR_BT_MODE

#define AR_BT_MODE   0x00000c00

Definition at line 1692 of file reg.h.

AR_BT_MODE_S

#define AR_BT_MODE_S   10

Definition at line 1693 of file reg.h.

AR_BT_QUIET

#define AR_BT_QUIET   0x00001000

Definition at line 1694 of file reg.h.

AR_BT_QUIET_S

#define AR_BT_QUIET_S   12

Definition at line 1695 of file reg.h.

AR_BT_QCU_THRESH

#define AR_BT_QCU_THRESH   0x0001e000

Definition at line 1696 of file reg.h.

AR_BT_QCU_THRESH_S

#define AR_BT_QCU_THRESH_S   13

Definition at line 1697 of file reg.h.

AR_BT_RX_CLEAR_POLARITY

#define AR_BT_RX_CLEAR_POLARITY   0x00020000

Definition at line 1698 of file reg.h.

AR_BT_RX_CLEAR_POLARITY_S

#define AR_BT_RX_CLEAR_POLARITY_S   17

Definition at line 1699 of file reg.h.

AR_BT_PRIORITY_TIME

#define AR_BT_PRIORITY_TIME   0x00fc0000

Definition at line 1700 of file reg.h.

AR_BT_PRIORITY_TIME_S

#define AR_BT_PRIORITY_TIME_S   18

Definition at line 1701 of file reg.h.

AR_BT_FIRST_SLOT_TIME

#define AR_BT_FIRST_SLOT_TIME   0xff000000

Definition at line 1702 of file reg.h.

AR_BT_FIRST_SLOT_TIME_S

#define AR_BT_FIRST_SLOT_TIME_S   24

Definition at line 1703 of file reg.h.

AR_BT_COEX_WEIGHT

#define AR_BT_COEX_WEIGHT   0x8174

Definition at line 1705 of file reg.h.

AR_BT_COEX_WGHT

#define AR_BT_COEX_WGHT   0xff55

Definition at line 1706 of file reg.h.

AR_STOMP_ALL_WLAN_WGHT

#define AR_STOMP_ALL_WLAN_WGHT   0xfcfc

Definition at line 1707 of file reg.h.

AR_STOMP_LOW_WLAN_WGHT

#define AR_STOMP_LOW_WLAN_WGHT   0xa8a8

Definition at line 1708 of file reg.h.

AR_STOMP_NONE_WLAN_WGHT

#define AR_STOMP_NONE_WLAN_WGHT   0x0000

Definition at line 1709 of file reg.h.

AR_BTCOEX_BT_WGHT

#define AR_BTCOEX_BT_WGHT   0x0000ffff

Definition at line 1710 of file reg.h.

AR_BTCOEX_BT_WGHT_S

#define AR_BTCOEX_BT_WGHT_S   0

Definition at line 1711 of file reg.h.

AR_BTCOEX_WL_WGHT

#define AR_BTCOEX_WL_WGHT   0xffff0000

Definition at line 1712 of file reg.h.

AR_BTCOEX_WL_WGHT_S

#define AR_BTCOEX_WL_WGHT_S   16

Definition at line 1713 of file reg.h.

AR_BT_COEX_WL_WEIGHTS0

#define AR_BT_COEX_WL_WEIGHTS0   0x8174

Definition at line 1715 of file reg.h.

AR_BT_COEX_WL_WEIGHTS1

#define AR_BT_COEX_WL_WEIGHTS1   0x81c4

Definition at line 1716 of file reg.h.

AR_BT_COEX_BT_WEIGHTS0

#define AR_BT_COEX_BT_WEIGHTS0   0x83ac

Definition at line 1718 of file reg.h.

AR_BT_COEX_BT_WEIGHTS1

#define AR_BT_COEX_BT_WEIGHTS1   0x83b0

Definition at line 1719 of file reg.h.

AR_BT_COEX_BT_WEIGHTS2

#define AR_BT_COEX_BT_WEIGHTS2   0x83b4

Definition at line 1720 of file reg.h.

AR_BT_COEX_BT_WEIGHTS3

#define AR_BT_COEX_BT_WEIGHTS3   0x83b8

Definition at line 1721 of file reg.h.

AR9300_BT_WGHT

#define AR9300_BT_WGHT   0xcccc4444

Definition at line 1723 of file reg.h.

AR9300_STOMP_ALL_WLAN_WGHT0

#define AR9300_STOMP_ALL_WLAN_WGHT0   0xfffffff0

Definition at line 1724 of file reg.h.

AR9300_STOMP_ALL_WLAN_WGHT1

#define AR9300_STOMP_ALL_WLAN_WGHT1   0xfffffff0

Definition at line 1725 of file reg.h.

AR9300_STOMP_LOW_WLAN_WGHT0

#define AR9300_STOMP_LOW_WLAN_WGHT0   0x88888880

Definition at line 1726 of file reg.h.

AR9300_STOMP_LOW_WLAN_WGHT1

#define AR9300_STOMP_LOW_WLAN_WGHT1   0x88888880

Definition at line 1727 of file reg.h.

AR9300_STOMP_NONE_WLAN_WGHT0

#define AR9300_STOMP_NONE_WLAN_WGHT0   0x00000000

Definition at line 1728 of file reg.h.

AR9300_STOMP_NONE_WLAN_WGHT1

#define AR9300_STOMP_NONE_WLAN_WGHT1   0x00000000

Definition at line 1729 of file reg.h.

AR_BT_COEX_MODE2

#define AR_BT_COEX_MODE2   0x817c

Definition at line 1731 of file reg.h.

AR_BT_BCN_MISS_THRESH

#define AR_BT_BCN_MISS_THRESH   0x000000ff

Definition at line 1732 of file reg.h.

AR_BT_BCN_MISS_THRESH_S

#define AR_BT_BCN_MISS_THRESH_S   0

Definition at line 1733 of file reg.h.

AR_BT_BCN_MISS_CNT

#define AR_BT_BCN_MISS_CNT   0x0000ff00

Definition at line 1734 of file reg.h.

AR_BT_BCN_MISS_CNT_S

#define AR_BT_BCN_MISS_CNT_S   8

Definition at line 1735 of file reg.h.

AR_BT_HOLD_RX_CLEAR

#define AR_BT_HOLD_RX_CLEAR   0x00010000

Definition at line 1736 of file reg.h.

AR_BT_HOLD_RX_CLEAR_S

#define AR_BT_HOLD_RX_CLEAR_S   16

Definition at line 1737 of file reg.h.

AR_BT_DISABLE_BT_ANT

#define AR_BT_DISABLE_BT_ANT   0x00100000

Definition at line 1738 of file reg.h.

AR_BT_DISABLE_BT_ANT_S

#define AR_BT_DISABLE_BT_ANT_S   20

Definition at line 1739 of file reg.h.

AR_TXSIFS

#define AR_TXSIFS   0x81d0

Definition at line 1741 of file reg.h.

AR_TXSIFS_TIME

#define AR_TXSIFS_TIME   0x000000FF

Definition at line 1742 of file reg.h.

AR_TXSIFS_TX_LATENCY

#define AR_TXSIFS_TX_LATENCY   0x00000F00

Definition at line 1743 of file reg.h.

AR_TXSIFS_TX_LATENCY_S

#define AR_TXSIFS_TX_LATENCY_S   8

Definition at line 1744 of file reg.h.

AR_TXSIFS_ACK_SHIFT

#define AR_TXSIFS_ACK_SHIFT   0x00007000

Definition at line 1745 of file reg.h.

AR_TXSIFS_ACK_SHIFT_S

#define AR_TXSIFS_ACK_SHIFT_S   12

Definition at line 1746 of file reg.h.

AR_TXOP_X

#define AR_TXOP_X   0x81ec

Definition at line 1748 of file reg.h.

AR_TXOP_X_VAL

#define AR_TXOP_X_VAL   0x000000FF

Definition at line 1749 of file reg.h.

AR_TXOP_0_3

#define AR_TXOP_0_3   0x81f0

Definition at line 1752 of file reg.h.

AR_TXOP_4_7

#define AR_TXOP_4_7   0x81f4

Definition at line 1753 of file reg.h.

AR_TXOP_8_11

#define AR_TXOP_8_11   0x81f8

Definition at line 1754 of file reg.h.

AR_TXOP_12_15

#define AR_TXOP_12_15   0x81fc

Definition at line 1755 of file reg.h.

AR_NEXT_NDP2_TIMER

#define AR_NEXT_NDP2_TIMER   0x8180

Definition at line 1757 of file reg.h.

AR_FIRST_NDP_TIMER

#define AR_FIRST_NDP_TIMER   7

Definition at line 1758 of file reg.h.

AR_NDP2_PERIOD

#define AR_NDP2_PERIOD   0x81a0

Definition at line 1759 of file reg.h.

AR_NDP2_TIMER_MODE

#define AR_NDP2_TIMER_MODE   0x81c0

Definition at line 1760 of file reg.h.

AR_GEN_TIMERS

#define AR_GEN_TIMERS

(

_i

)

Value:

(0x8200 + ((_i) << 2))

Definition at line 1762 of file reg.h.

AR_NEXT_TBTT_TIMER

#define AR_NEXT_TBTT_TIMER   AR_GEN_TIMERS(0)

Definition at line 1763 of file reg.h.

AR_NEXT_DMA_BEACON_ALERT

#define AR_NEXT_DMA_BEACON_ALERT   AR_GEN_TIMERS(1)

Definition at line 1764 of file reg.h.

AR_NEXT_SWBA

#define AR_NEXT_SWBA   AR_GEN_TIMERS(2)

Definition at line 1765 of file reg.h.

AR_NEXT_CFP

#define AR_NEXT_CFP   AR_GEN_TIMERS(2)

Definition at line 1766 of file reg.h.

AR_NEXT_HCF

#define AR_NEXT_HCF   AR_GEN_TIMERS(3)

Definition at line 1767 of file reg.h.

AR_NEXT_TIM

#define AR_NEXT_TIM   AR_GEN_TIMERS(4)

Definition at line 1768 of file reg.h.

AR_NEXT_DTIM

#define AR_NEXT_DTIM   AR_GEN_TIMERS(5)

Definition at line 1769 of file reg.h.

AR_NEXT_QUIET_TIMER

#define AR_NEXT_QUIET_TIMER   AR_GEN_TIMERS(6)

Definition at line 1770 of file reg.h.

AR_NEXT_NDP_TIMER

#define AR_NEXT_NDP_TIMER   AR_GEN_TIMERS(7)

Definition at line 1771 of file reg.h.

AR_BEACON_PERIOD

#define AR_BEACON_PERIOD   AR_GEN_TIMERS(8)

Definition at line 1773 of file reg.h.

AR_DMA_BEACON_PERIOD

#define AR_DMA_BEACON_PERIOD   AR_GEN_TIMERS(9)

Definition at line 1774 of file reg.h.

AR_SWBA_PERIOD

#define AR_SWBA_PERIOD   AR_GEN_TIMERS(10)

Definition at line 1775 of file reg.h.

AR_HCF_PERIOD

#define AR_HCF_PERIOD   AR_GEN_TIMERS(11)

Definition at line 1776 of file reg.h.

AR_TIM_PERIOD

#define AR_TIM_PERIOD   AR_GEN_TIMERS(12)

Definition at line 1777 of file reg.h.

AR_DTIM_PERIOD

#define AR_DTIM_PERIOD   AR_GEN_TIMERS(13)

Definition at line 1778 of file reg.h.

AR_QUIET_PERIOD

#define AR_QUIET_PERIOD   AR_GEN_TIMERS(14)

Definition at line 1779 of file reg.h.

AR_NDP_PERIOD

#define AR_NDP_PERIOD   AR_GEN_TIMERS(15)

Definition at line 1780 of file reg.h.

AR_TIMER_MODE

#define AR_TIMER_MODE   0x8240

Definition at line 1782 of file reg.h.

AR_TBTT_TIMER_EN

#define AR_TBTT_TIMER_EN   0x00000001

Definition at line 1783 of file reg.h.

AR_DBA_TIMER_EN

#define AR_DBA_TIMER_EN   0x00000002

Definition at line 1784 of file reg.h.

AR_SWBA_TIMER_EN

#define AR_SWBA_TIMER_EN   0x00000004

Definition at line 1785 of file reg.h.

AR_HCF_TIMER_EN

#define AR_HCF_TIMER_EN   0x00000008

Definition at line 1786 of file reg.h.

AR_TIM_TIMER_EN

#define AR_TIM_TIMER_EN   0x00000010

Definition at line 1787 of file reg.h.

AR_DTIM_TIMER_EN

#define AR_DTIM_TIMER_EN   0x00000020

Definition at line 1788 of file reg.h.

AR_QUIET_TIMER_EN

#define AR_QUIET_TIMER_EN   0x00000040

Definition at line 1789 of file reg.h.

AR_NDP_TIMER_EN

#define AR_NDP_TIMER_EN   0x00000080

Definition at line 1790 of file reg.h.

AR_TIMER_OVERFLOW_INDEX

#define AR_TIMER_OVERFLOW_INDEX   0x00000700

Definition at line 1791 of file reg.h.

AR_TIMER_OVERFLOW_INDEX_S

#define AR_TIMER_OVERFLOW_INDEX_S   8

Definition at line 1792 of file reg.h.

AR_TIMER_THRESH

#define AR_TIMER_THRESH   0xFFFFF000

Definition at line 1793 of file reg.h.

AR_TIMER_THRESH_S

#define AR_TIMER_THRESH_S   12

Definition at line 1794 of file reg.h.

AR_SLP32_MODE

#define AR_SLP32_MODE   0x8244

Definition at line 1796 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_SLP32_HALF_CLK_LATENCY

#define AR_SLP32_HALF_CLK_LATENCY   0x000FFFFF

Definition at line 1797 of file reg.h.

AR_SLP32_ENA

#define AR_SLP32_ENA   0x00100000

Definition at line 1798 of file reg.h.

AR_SLP32_TSF_WRITE_STATUS

#define AR_SLP32_TSF_WRITE_STATUS   0x00200000

Definition at line 1799 of file reg.h.

AR_SLP32_WAKE

#define AR_SLP32_WAKE   0x8248

Definition at line 1801 of file reg.h.

AR_SLP32_WAKE_XTL_TIME

#define AR_SLP32_WAKE_XTL_TIME   0x0000FFFF

Definition at line 1802 of file reg.h.

AR_SLP32_INC

#define AR_SLP32_INC   0x824c

Definition at line 1804 of file reg.h.

Referenced by ath9k_hw_init_pll().

AR_SLP32_TST_INC

#define AR_SLP32_TST_INC   0x000FFFFF

Definition at line 1805 of file reg.h.

AR_SLP_CNT

#define AR_SLP_CNT   0x8250

Definition at line 1807 of file reg.h.

AR_SLP_CYCLE_CNT

#define AR_SLP_CYCLE_CNT   0x8254

Definition at line 1808 of file reg.h.

AR_SLP_MIB_CTRL

#define AR_SLP_MIB_CTRL   0x8258

Definition at line 1810 of file reg.h.

AR_SLP_MIB_CLEAR

#define AR_SLP_MIB_CLEAR   0x00000001

Definition at line 1811 of file reg.h.

AR_SLP_MIB_PENDING

#define AR_SLP_MIB_PENDING   0x00000002

Definition at line 1812 of file reg.h.

AR_MAC_PCU_LOGIC_ANALYZER

#define AR_MAC_PCU_LOGIC_ANALYZER   0x8264

Definition at line 1814 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768

#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768   0x20000000

Definition at line 1815 of file reg.h.

Referenced by ar9002_hw_update_async_fifo().

AR_2040_MODE

#define AR_2040_MODE   0x8318

Definition at line 1818 of file reg.h.

Referenced by ath9k_hw_set11nmac2040().

AR_2040_JOINED_RX_CLEAR

#define AR_2040_JOINED_RX_CLEAR   0x00000001

Definition at line 1819 of file reg.h.

AR_EXTRCCNT

#define AR_EXTRCCNT   0x8328

Definition at line 1822 of file reg.h.

AR_SELFGEN_MASK

#define AR_SELFGEN_MASK   0x832c

Definition at line 1824 of file reg.h.

Referenced by ar5008_hw_init_chain_masks(), and ar9003_hw_set_chain_masks().

AR_PCU_TXBUF_CTRL

#define AR_PCU_TXBUF_CTRL   0x8340

Definition at line 1826 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_PCU_TXBUF_CTRL_SIZE_MASK

#define AR_PCU_TXBUF_CTRL_SIZE_MASK   0x7FF

Definition at line 1827 of file reg.h.

AR_PCU_TXBUF_CTRL_USABLE_SIZE

#define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700

Definition at line 1828 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE

#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380

Definition at line 1829 of file reg.h.

Referenced by ath9k_hw_set_dma().

AR_PCU_MISC_MODE2

#define AR_PCU_MISC_MODE2   0x8344

Definition at line 1831 of file reg.h.

Referenced by ar5008_hw_override_ini(), ar9002_hw_enable_wep_aggregation(), ar9003_hw_override_ini(), and ath9k_hw_reset().

AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE

#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE   0x00000002

Definition at line 1832 of file reg.h.

Referenced by ath9k_hw_reset().

AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT

#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT   0x00000004

Definition at line 1833 of file reg.h.

Referenced by ath9k_hw_reset().

AR_PCU_MISC_MODE2_RESERVED

#define AR_PCU_MISC_MODE2_RESERVED   0x00000038

Definition at line 1835 of file reg.h.

AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE

#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE   0x00000040

Definition at line 1836 of file reg.h.

AR_PCU_MISC_MODE2_CFP_IGNORE

#define AR_PCU_MISC_MODE2_CFP_IGNORE   0x00000080

Definition at line 1837 of file reg.h.

AR_PCU_MISC_MODE2_MGMT_QOS

#define AR_PCU_MISC_MODE2_MGMT_QOS   0x0000FF00

Definition at line 1838 of file reg.h.

AR_PCU_MISC_MODE2_MGMT_QOS_S

#define AR_PCU_MISC_MODE2_MGMT_QOS_S   8

Definition at line 1839 of file reg.h.

AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION

#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION   0x00010000

Definition at line 1840 of file reg.h.

AR_PCU_MISC_MODE2_ENABLE_AGGWEP

#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP   0x00020000

Definition at line 1841 of file reg.h.

Referenced by ar9002_hw_enable_wep_aggregation().

AR_PCU_MISC_MODE2_HWWAR1

#define AR_PCU_MISC_MODE2_HWWAR1   0x00100000

Definition at line 1842 of file reg.h.

Referenced by ar5008_hw_override_ini().

AR_PCU_MISC_MODE2_HWWAR2

#define AR_PCU_MISC_MODE2_HWWAR2   0x02000000

Definition at line 1843 of file reg.h.

Referenced by ar5008_hw_override_ini().

AR_PCU_MISC_MODE2_RESERVED2

#define AR_PCU_MISC_MODE2_RESERVED2   0xFFFE0000

Definition at line 1844 of file reg.h.

AR_MAC_PCU_ASYNC_FIFO_REG3

#define AR_MAC_PCU_ASYNC_FIFO_REG3   0x8358

Definition at line 1846 of file reg.h.

Referenced by ar9002_hw_enable_async_fifo().

AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL

#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL   0x00000400

Definition at line 1847 of file reg.h.

Referenced by ar9002_hw_enable_async_fifo().

AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET

#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET   0x80000000

Definition at line 1848 of file reg.h.

Referenced by ar9002_hw_enable_async_fifo().

AR_AES_MUTE_MASK0 [2/2]

#define AR_AES_MUTE_MASK0   0x805c

Definition at line 1537 of file reg.h.

AR_AES_MUTE_MASK0_FC [2/2]

#define AR_AES_MUTE_MASK0_FC   0x0000FFFF

Definition at line 1538 of file reg.h.

AR_AES_MUTE_MASK0_QOS [2/2]

#define AR_AES_MUTE_MASK0_QOS   0xFFFF0000

Definition at line 1539 of file reg.h.

AR_AES_MUTE_MASK0_QOS_S [2/2]

#define AR_AES_MUTE_MASK0_QOS_S   16

Definition at line 1540 of file reg.h.

AR_AES_MUTE_MASK1 [2/2]

#define AR_AES_MUTE_MASK1   0x8060

Definition at line 1542 of file reg.h.

AR_AES_MUTE_MASK1_SEQ [2/2]

#define AR_AES_MUTE_MASK1_SEQ   0x0000FFFF

Definition at line 1543 of file reg.h.

AR_AES_MUTE_MASK1_SEQ_S

#define AR_AES_MUTE_MASK1_SEQ_S   0

Definition at line 1858 of file reg.h.

AR_AES_MUTE_MASK1_FC_MGMT [2/2]

#define AR_AES_MUTE_MASK1_FC_MGMT   0xFFFF0000

Definition at line 1544 of file reg.h.

AR_AES_MUTE_MASK1_FC_MGMT_S [2/2]

#define AR_AES_MUTE_MASK1_FC_MGMT_S   16

Definition at line 1545 of file reg.h.

AR_RATE_DURATION_0

#define AR_RATE_DURATION_0   0x8700

Definition at line 1862 of file reg.h.

AR_RATE_DURATION_31

#define AR_RATE_DURATION_31   0x87CC

Definition at line 1863 of file reg.h.

AR_RATE_DURATION_32

#define AR_RATE_DURATION_32   0x8780

Definition at line 1864 of file reg.h.

AR_RATE_DURATION

#define AR_RATE_DURATION

(

_n

)

Value:

(AR_RATE_DURATION_0 + ((_n)<<2))

Definition at line 1865 of file reg.h.

AR_KEYTABLE_0

#define AR_KEYTABLE_0   0x8800

Definition at line 1868 of file reg.h.

AR_KEYTABLE

#define AR_KEYTABLE

(

_n

)

Value:

(AR_KEYTABLE_0 + ((_n)*32))

Definition at line 1869 of file reg.h.

AR_KEY_CACHE_SIZE

#define AR_KEY_CACHE_SIZE   128

Definition at line 1870 of file reg.h.

AR_RSVD_KEYTABLE_ENTRIES

#define AR_RSVD_KEYTABLE_ENTRIES   4

Definition at line 1871 of file reg.h.

AR_KEY_TYPE

#define AR_KEY_TYPE   0x00000007

Definition at line 1872 of file reg.h.

AR_KEYTABLE_TYPE_40

#define AR_KEYTABLE_TYPE_40   0x00000000

Definition at line 1873 of file reg.h.

AR_KEYTABLE_TYPE_104

#define AR_KEYTABLE_TYPE_104   0x00000001

Definition at line 1874 of file reg.h.

AR_KEYTABLE_TYPE_128

#define AR_KEYTABLE_TYPE_128   0x00000003

Definition at line 1875 of file reg.h.

AR_KEYTABLE_TYPE_TKIP

#define AR_KEYTABLE_TYPE_TKIP   0x00000004

Definition at line 1876 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_TYPE_AES

#define AR_KEYTABLE_TYPE_AES   0x00000005

Definition at line 1877 of file reg.h.

AR_KEYTABLE_TYPE_CCM

#define AR_KEYTABLE_TYPE_CCM   0x00000006

Definition at line 1878 of file reg.h.

AR_KEYTABLE_TYPE_CLR

#define AR_KEYTABLE_TYPE_CLR   0x00000007

Definition at line 1879 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_ANT

#define AR_KEYTABLE_ANT   0x00000008

Definition at line 1880 of file reg.h.

AR_KEYTABLE_VALID

#define AR_KEYTABLE_VALID   0x00008000

Definition at line 1881 of file reg.h.

AR_KEYTABLE_KEY0

#define AR_KEYTABLE_KEY0

(

_n

)

Value:

(AR_KEYTABLE(_n) + 0)

Definition at line 1882 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_KEY1

#define AR_KEYTABLE_KEY1

(

_n

)

Value:

(AR_KEYTABLE(_n) + 4)

Definition at line 1883 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_KEY2

#define AR_KEYTABLE_KEY2

(

_n

)

Value:

(AR_KEYTABLE(_n) + 8)

Definition at line 1884 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_KEY3

#define AR_KEYTABLE_KEY3

(

_n

)

Value:

(AR_KEYTABLE(_n) + 12)

Definition at line 1885 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_KEY4

#define AR_KEYTABLE_KEY4

(

_n

)

Value:

(AR_KEYTABLE(_n) + 16)

Definition at line 1886 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_TYPE

#define AR_KEYTABLE_TYPE

(

_n

)

Value:

(AR_KEYTABLE(_n) + 20)

Definition at line 1887 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_MAC0

#define AR_KEYTABLE_MAC0

(

_n

)

Value:

(AR_KEYTABLE(_n) + 24)

Definition at line 1888 of file reg.h.

Referenced by ath_hw_keyreset().

AR_KEYTABLE_MAC1

#define AR_KEYTABLE_MAC1

(

_n

)

Value:

(AR_KEYTABLE(_n) + 28)

Definition at line 1889 of file reg.h.

Referenced by ath_hw_keyreset().

AR9271_CORE_CLOCK

#define AR9271_CORE_CLOCK   117 /* clock to 117Mhz */

Definition at line 1891 of file reg.h.

AR9271_TARGET_BAUD_RATE

#define AR9271_TARGET_BAUD_RATE   19200 /* 115200 */

Definition at line 1892 of file reg.h.

AR_AGG_WEP_ENABLE_FIX

#define AR_AGG_WEP_ENABLE_FIX   0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */

Definition at line 1894 of file reg.h.

Referenced by ar9003_hw_override_ini().

AR_ADHOC_MCAST_KEYID_ENABLE

#define AR_ADHOC_MCAST_KEYID_ENABLE

Value:

                                                     0x00000040  /* This bit enables the Multicast search
                                                     * based on both MAC Address and Key ID.
                                                     * If bit is 0, then Multicast search is
                                                     * based on MAC address only.
                                                     * For Merlin and above only.
                                                     */

Definition at line 1895 of file reg.h.

Referenced by ar9003_hw_override_ini().

AR_AGG_WEP_ENABLE

#define AR_AGG_WEP_ENABLE

Value:

                                                     0x00020000  /* This field enables AGG_WEP feature,
                                                     * when it is enable, AGG_WEP would takes
                                                     * charge of the encryption interface of
                                                     * pcu_txsm.
                                                     */

Definition at line 1896 of file reg.h.

Referenced by ar9003_hw_override_ini().

AR9300_SM_BASE

#define AR9300_SM_BASE   0xa200

Definition at line 1898 of file reg.h.

AR9002_PHY_AGC_CONTROL

#define AR9002_PHY_AGC_CONTROL   0x9860

Definition at line 1899 of file reg.h.

AR9003_PHY_AGC_CONTROL

#define AR9003_PHY_AGC_CONTROL   AR9300_SM_BASE + 0xc4

Definition at line 1900 of file reg.h.

AR_PHY_AGC_CONTROL

#define AR_PHY_AGC_CONTROL   (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)

Definition at line 1901 of file reg.h.

Referenced by ar9002_hw_calibrate(), ar9002_hw_init_cal(), ar9003_hw_init_cal(), ar9003_hw_spur_mitigate_mrc_cck(), ar9285_hw_cl_cal(), ath9k_hw_getnf(), ath9k_hw_loadnf(), and ath9k_hw_start_nfcal().

AR_PHY_AGC_CONTROL_CAL

#define AR_PHY_AGC_CONTROL_CAL   0x00000001 /* do internal calibration */

Definition at line 1902 of file reg.h.

Referenced by ar9002_hw_init_cal(), ar9003_hw_init_cal(), and ar9285_hw_cl_cal().

AR_PHY_AGC_CONTROL_NF

#define AR_PHY_AGC_CONTROL_NF   0x00000002 /* do noise-floor calibration */

Definition at line 1903 of file reg.h.

Referenced by ar9002_hw_calibrate(), ath9k_hw_getnf(), ath9k_hw_loadnf(), and ath9k_hw_start_nfcal().

AR_PHY_AGC_CONTROL_OFFSET_CAL

#define AR_PHY_AGC_CONTROL_OFFSET_CAL   0x00000800 /* allow offset calibration */

Definition at line 1904 of file reg.h.

AR_PHY_AGC_CONTROL_ENABLE_NF

#define AR_PHY_AGC_CONTROL_ENABLE_NF   0x00008000 /* enable noise floor calibration to happen */

Definition at line 1905 of file reg.h.

Referenced by ath9k_hw_loadnf(), and ath9k_hw_start_nfcal().

AR_PHY_AGC_CONTROL_FLTR_CAL

#define AR_PHY_AGC_CONTROL_FLTR_CAL   0x00010000 /* allow tx filter calibration */

Definition at line 1906 of file reg.h.

Referenced by ar9002_hw_init_cal(), and ar9285_hw_cl_cal().

AR_PHY_AGC_CONTROL_NO_UPDATE_NF

#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF   0x00020000 /* don't update noise floor automatically */

Definition at line 1907 of file reg.h.

Referenced by ath9k_hw_loadnf(), and ath9k_hw_start_nfcal().

AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS

#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS   0x00040000 /* extend noise floor power measurement */

Definition at line 1908 of file reg.h.

AR_PHY_AGC_CONTROL_CLC_SUCCESS

#define AR_PHY_AGC_CONTROL_CLC_SUCCESS   0x00080000 /* carrier leak calibration done */

Definition at line 1909 of file reg.h.

AR_PHY_AGC_CONTROL_YCOK_MAX

#define AR_PHY_AGC_CONTROL_YCOK_MAX   0x000003c0

Definition at line 1910 of file reg.h.

Referenced by ar9003_hw_spur_mitigate_mrc_cck().

AR_PHY_AGC_CONTROL_YCOK_MAX_S

#define AR_PHY_AGC_CONTROL_YCOK_MAX_S   6

Definition at line 1911 of file reg.h.

Enumeration Type Documentation

ath_usb_dev

enum ath_usb_dev

Enumerator
AR9280_USB
AR9287_USB
STORAGE_DEVICE

Definition at line 886 of file reg.h.

                 {
        AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
        AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
        STORAGE_DEVICE = 3,
};

anonymous enum

anonymous enum

Enumerator
AR_INTR_SYNC_RTC_IRQ
AR_INTR_SYNC_MAC_IRQ
AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS
AR_INTR_SYNC_APB_TIMEOUT
AR_INTR_SYNC_PCI_MODE_CONFLICT
AR_INTR_SYNC_HOST1_FATAL
AR_INTR_SYNC_HOST1_PERR
AR_INTR_SYNC_TRCV_FIFO_PERR
AR_INTR_SYNC_RADM_CPL_EP
AR_INTR_SYNC_RADM_CPL_DLLP_ABORT
AR_INTR_SYNC_RADM_CPL_TLP_ABORT
AR_INTR_SYNC_RADM_CPL_ECRC_ERR
AR_INTR_SYNC_RADM_CPL_TIMEOUT
AR_INTR_SYNC_LOCAL_TIMEOUT
AR_INTR_SYNC_PM_ACCESS
AR_INTR_SYNC_MAC_AWAKE
AR_INTR_SYNC_MAC_ASLEEP
AR_INTR_SYNC_MAC_SLEEP_ACCESS
AR_INTR_SYNC_ALL
AR_INTR_SYNC_DEFAULT
AR_INTR_SYNC_SPURIOUS

Definition at line 931 of file reg.h.

     {
        AR_INTR_SYNC_RTC_IRQ = 0x00000001,
        AR_INTR_SYNC_MAC_IRQ = 0x00000002,
        AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
        AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,
        AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
        AR_INTR_SYNC_HOST1_FATAL = 0x00000020,
        AR_INTR_SYNC_HOST1_PERR = 0x00000040,
        AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
        AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,
        AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
        AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400,
        AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
        AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
        AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
        AR_INTR_SYNC_PM_ACCESS = 0x00004000,
        AR_INTR_SYNC_MAC_AWAKE = 0x00008000,
        AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,
        AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
        AR_INTR_SYNC_ALL = 0x0003FFFF,
 
 
        AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL |
                                AR_INTR_SYNC_HOST1_PERR |
                                AR_INTR_SYNC_RADM_CPL_EP |
                                AR_INTR_SYNC_RADM_CPL_DLLP_ABORT |
                                AR_INTR_SYNC_RADM_CPL_TLP_ABORT |
                                AR_INTR_SYNC_RADM_CPL_ECRC_ERR |
                                AR_INTR_SYNC_RADM_CPL_TIMEOUT |
                                AR_INTR_SYNC_LOCAL_TIMEOUT |
                                AR_INTR_SYNC_MAC_SLEEP_ACCESS),
 
        AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
 
};

Function Documentation

FILE_LICENCE()

FILE_LICENCE

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BSD2

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FILE_SECBOOT

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