iPXE
ath9k_ar9003_eeprom.c
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 FILE_SECBOOT ( FORBIDDEN );
21 
22 #include <ipxe/io.h>
23 #include <ipxe/malloc.h>
24 
25 #include "hw.h"
26 #include "ar9003_phy.h"
27 #include "ar9003_eeprom.h"
28 
29 #define COMP_HDR_LEN 4
30 #define COMP_CKSUM_LEN 2
31 
32 #define AR_CH0_TOP (0x00016288)
33 #define AR_CH0_TOP_XPABIASLVL (0x300)
34 #define AR_CH0_TOP_XPABIASLVL_S (8)
35 
36 #define AR_CH0_THERM (0x00016290)
37 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
38 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
39 #define AR_CH0_THERM_XPASHORT2GND 0x4
40 #define AR_CH0_THERM_XPASHORT2GND_S 2
41 
42 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
43 #define AR_SWITCH_TABLE_COM_ALL_S (0)
44 
45 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
46 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
47 
48 #define AR_SWITCH_TABLE_ALL (0xfff)
49 #define AR_SWITCH_TABLE_ALL_S (0)
50 
51 #define LE16(x) (uint16_t)(x)
52 #define LE32(x) (uint32_t)(x)
53 
54 /* Local defines to distinguish between extension and control CTL's */
55 #define EXT_ADDITIVE (0x8000)
56 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
57 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
58 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
59 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
60 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
61 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
62 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
63 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
64 
65 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
66 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
67 
68 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
69 
70 #define EEPROM_DATA_LEN_9485 1088
71 
72 static int ar9003_hw_power_interpolate(int32_t x,
73  int32_t *px, int32_t *py, uint16_t np);
74 
75 
76 static const struct ar9300_eeprom ar9300_default = {
77  .eepromVersion = 2,
78  .templateVersion = 2,
79  .macAddr = {1, 2, 3, 4, 5, 6},
80  .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81  0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
82  .baseEepHeader = {
83  .regDmn = { LE16(0), LE16(0x1f) },
84  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
85  .opCapFlags = {
86  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
87  .eepMisc = 0,
88  },
89  .rfSilent = 0,
90  .blueToothOptions = 0,
91  .deviceCap = 0,
92  .deviceType = 5, /* takes lower byte in eeprom location */
93  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
94  .params_for_tuning_caps = {0, 0},
95  .featureEnable = 0x0c,
96  /*
97  * bit0 - enable tx temp comp - disabled
98  * bit1 - enable tx volt comp - disabled
99  * bit2 - enable fastClock - enabled
100  * bit3 - enable doubling - enabled
101  * bit4 - enable internal regulator - disabled
102  * bit5 - enable pa predistortion - disabled
103  */
104  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
105  .eepromWriteEnableGpio = 3,
106  .wlanDisableGpio = 0,
107  .wlanLedGpio = 8,
108  .rxBandSelectGpio = 0xff,
109  .txrxgain = 0,
110  .swreg = 0,
111  },
112  .modalHeader2G = {
113  /* ar9300_modal_eep_header 2g */
114  /* 4 idle,t1,t2,b(4 bits per setting) */
115  .antCtrlCommon = LE32(0x110),
116  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
117  .antCtrlCommon2 = LE32(0x22222),
118 
119  /*
120  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
121  * rx1, rx12, b (2 bits each)
122  */
123  .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
124 
125  /*
126  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
127  * for ar9280 (0xa20c/b20c 5:0)
128  */
129  .xatten1DB = {0, 0, 0},
130 
131  /*
132  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
133  * for ar9280 (0xa20c/b20c 16:12
134  */
135  .xatten1Margin = {0, 0, 0},
136  .tempSlope = 36,
137  .voltSlope = 0,
138 
139  /*
140  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
141  * channels in usual fbin coding format
142  */
143  .spurChans = {0, 0, 0, 0, 0},
144 
145  /*
146  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
147  * if the register is per chain
148  */
149  .noiseFloorThreshCh = {-1, 0, 0},
150  .ob = {1, 1, 1},/* 3 chain */
151  .db_stage2 = {1, 1, 1}, /* 3 chain */
152  .db_stage3 = {0, 0, 0},
153  .db_stage4 = {0, 0, 0},
154  .xpaBiasLvl = 0,
155  .txFrameToDataStart = 0x0e,
156  .txFrameToPaOn = 0x0e,
157  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
158  .antennaGain = 0,
159  .switchSettling = 0x2c,
160  .adcDesiredSize = -30,
161  .txEndToXpaOff = 0,
162  .txEndToRxOn = 0x2,
163  .txFrameToXpaOn = 0xe,
164  .thresh62 = 28,
165  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
166  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
167  .futureModal = {
168  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
169  },
170  },
171  .base_ext1 = {
172  .ant_div_control = 0,
173  .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
174  },
175  .calFreqPier2G = {
176  FREQ2FBIN(2412, 1),
177  FREQ2FBIN(2437, 1),
178  FREQ2FBIN(2472, 1),
179  },
180  /* ar9300_cal_data_per_freq_op_loop 2g */
181  .calPierData2G = {
182  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
183  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
184  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
185  },
186  .calTarget_freqbin_Cck = {
187  FREQ2FBIN(2412, 1),
188  FREQ2FBIN(2484, 1),
189  },
190  .calTarget_freqbin_2G = {
191  FREQ2FBIN(2412, 1),
192  FREQ2FBIN(2437, 1),
193  FREQ2FBIN(2472, 1)
194  },
195  .calTarget_freqbin_2GHT20 = {
196  FREQ2FBIN(2412, 1),
197  FREQ2FBIN(2437, 1),
198  FREQ2FBIN(2472, 1)
199  },
200  .calTarget_freqbin_2GHT40 = {
201  FREQ2FBIN(2412, 1),
202  FREQ2FBIN(2437, 1),
203  FREQ2FBIN(2472, 1)
204  },
205  .calTargetPowerCck = {
206  /* 1L-5L,5S,11L,11S */
207  { {36, 36, 36, 36} },
208  { {36, 36, 36, 36} },
209  },
210  .calTargetPower2G = {
211  /* 6-24,36,48,54 */
212  { {32, 32, 28, 24} },
213  { {32, 32, 28, 24} },
214  { {32, 32, 28, 24} },
215  },
216  .calTargetPower2GHT20 = {
217  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
218  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
219  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
220  },
221  .calTargetPower2GHT40 = {
222  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
223  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
224  { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
225  },
226  .ctlIndex_2G = {
227  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
228  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
229  },
230  .ctl_freqbin_2G = {
231  {
232  FREQ2FBIN(2412, 1),
233  FREQ2FBIN(2417, 1),
234  FREQ2FBIN(2457, 1),
235  FREQ2FBIN(2462, 1)
236  },
237  {
238  FREQ2FBIN(2412, 1),
239  FREQ2FBIN(2417, 1),
240  FREQ2FBIN(2462, 1),
241  0xFF,
242  },
243 
244  {
245  FREQ2FBIN(2412, 1),
246  FREQ2FBIN(2417, 1),
247  FREQ2FBIN(2462, 1),
248  0xFF,
249  },
250  {
251  FREQ2FBIN(2422, 1),
252  FREQ2FBIN(2427, 1),
253  FREQ2FBIN(2447, 1),
254  FREQ2FBIN(2452, 1)
255  },
256 
257  {
258  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
259  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
260  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
261  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
262  },
263 
264  {
265  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
266  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
267  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
268  0,
269  },
270 
271  {
272  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
273  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
274  FREQ2FBIN(2472, 1),
275  0,
276  },
277 
278  {
279  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
280  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
281  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
282  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
283  },
284 
285  {
286  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
287  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
288  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
289  },
290 
291  {
292  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
293  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
294  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
295  0
296  },
297 
298  {
299  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
300  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
301  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
302  0
303  },
304 
305  {
306  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
307  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
308  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
309  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
310  }
311  },
312  .ctlPowerData_2G = {
313  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
314  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
315  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
316 
317  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
318  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
319  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
320 
321  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
322  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
323  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
324 
325  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
326  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
327  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
328  },
329  .modalHeader5G = {
330  /* 4 idle,t1,t2,b (4 bits per setting) */
331  .antCtrlCommon = LE32(0x110),
332  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
333  .antCtrlCommon2 = LE32(0x22222),
334  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
335  .antCtrlChain = {
336  LE16(0x000), LE16(0x000), LE16(0x000),
337  },
338  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
339  .xatten1DB = {0, 0, 0},
340 
341  /*
342  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
343  * for merlin (0xa20c/b20c 16:12
344  */
345  .xatten1Margin = {0, 0, 0},
346  .tempSlope = 68,
347  .voltSlope = 0,
348  /* spurChans spur channels in usual fbin coding format */
349  .spurChans = {0, 0, 0, 0, 0},
350  /* noiseFloorThreshCh Check if the register is per chain */
351  .noiseFloorThreshCh = {-1, 0, 0},
352  .ob = {3, 3, 3}, /* 3 chain */
353  .db_stage2 = {3, 3, 3}, /* 3 chain */
354  .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
355  .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
356  .xpaBiasLvl = 0,
357  .txFrameToDataStart = 0x0e,
358  .txFrameToPaOn = 0x0e,
359  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
360  .antennaGain = 0,
361  .switchSettling = 0x2d,
362  .adcDesiredSize = -30,
363  .txEndToXpaOff = 0,
364  .txEndToRxOn = 0x2,
365  .txFrameToXpaOn = 0xe,
366  .thresh62 = 28,
367  .papdRateMaskHt20 = LE32(0x0c80c080),
368  .papdRateMaskHt40 = LE32(0x0080c080),
369  .futureModal = {
370  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
371  },
372  },
373  .base_ext2 = {
374  .tempSlopeLow = 0,
375  .tempSlopeHigh = 0,
376  .xatten1DBLow = {0, 0, 0},
377  .xatten1MarginLow = {0, 0, 0},
378  .xatten1DBHigh = {0, 0, 0},
379  .xatten1MarginHigh = {0, 0, 0}
380  },
381  .calFreqPier5G = {
382  FREQ2FBIN(5180, 0),
383  FREQ2FBIN(5220, 0),
384  FREQ2FBIN(5320, 0),
385  FREQ2FBIN(5400, 0),
386  FREQ2FBIN(5500, 0),
387  FREQ2FBIN(5600, 0),
388  FREQ2FBIN(5725, 0),
389  FREQ2FBIN(5825, 0)
390  },
391  .calPierData5G = {
392  {
393  {0, 0, 0, 0, 0, 0},
394  {0, 0, 0, 0, 0, 0},
395  {0, 0, 0, 0, 0, 0},
396  {0, 0, 0, 0, 0, 0},
397  {0, 0, 0, 0, 0, 0},
398  {0, 0, 0, 0, 0, 0},
399  {0, 0, 0, 0, 0, 0},
400  {0, 0, 0, 0, 0, 0},
401  },
402  {
403  {0, 0, 0, 0, 0, 0},
404  {0, 0, 0, 0, 0, 0},
405  {0, 0, 0, 0, 0, 0},
406  {0, 0, 0, 0, 0, 0},
407  {0, 0, 0, 0, 0, 0},
408  {0, 0, 0, 0, 0, 0},
409  {0, 0, 0, 0, 0, 0},
410  {0, 0, 0, 0, 0, 0},
411  },
412  {
413  {0, 0, 0, 0, 0, 0},
414  {0, 0, 0, 0, 0, 0},
415  {0, 0, 0, 0, 0, 0},
416  {0, 0, 0, 0, 0, 0},
417  {0, 0, 0, 0, 0, 0},
418  {0, 0, 0, 0, 0, 0},
419  {0, 0, 0, 0, 0, 0},
420  {0, 0, 0, 0, 0, 0},
421  },
422 
423  },
424  .calTarget_freqbin_5G = {
425  FREQ2FBIN(5180, 0),
426  FREQ2FBIN(5220, 0),
427  FREQ2FBIN(5320, 0),
428  FREQ2FBIN(5400, 0),
429  FREQ2FBIN(5500, 0),
430  FREQ2FBIN(5600, 0),
431  FREQ2FBIN(5725, 0),
432  FREQ2FBIN(5825, 0)
433  },
434  .calTarget_freqbin_5GHT20 = {
435  FREQ2FBIN(5180, 0),
436  FREQ2FBIN(5240, 0),
437  FREQ2FBIN(5320, 0),
438  FREQ2FBIN(5500, 0),
439  FREQ2FBIN(5700, 0),
440  FREQ2FBIN(5745, 0),
441  FREQ2FBIN(5725, 0),
442  FREQ2FBIN(5825, 0)
443  },
444  .calTarget_freqbin_5GHT40 = {
445  FREQ2FBIN(5180, 0),
446  FREQ2FBIN(5240, 0),
447  FREQ2FBIN(5320, 0),
448  FREQ2FBIN(5500, 0),
449  FREQ2FBIN(5700, 0),
450  FREQ2FBIN(5745, 0),
451  FREQ2FBIN(5725, 0),
452  FREQ2FBIN(5825, 0)
453  },
454  .calTargetPower5G = {
455  /* 6-24,36,48,54 */
456  { {20, 20, 20, 10} },
457  { {20, 20, 20, 10} },
458  { {20, 20, 20, 10} },
459  { {20, 20, 20, 10} },
460  { {20, 20, 20, 10} },
461  { {20, 20, 20, 10} },
462  { {20, 20, 20, 10} },
463  { {20, 20, 20, 10} },
464  },
465  .calTargetPower5GHT20 = {
466  /*
467  * 0_8_16,1-3_9-11_17-19,
468  * 4,5,6,7,12,13,14,15,20,21,22,23
469  */
470  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
478  },
479  .calTargetPower5GHT40 = {
480  /*
481  * 0_8_16,1-3_9-11_17-19,
482  * 4,5,6,7,12,13,14,15,20,21,22,23
483  */
484  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
485  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
486  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
487  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
488  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
489  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
490  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
491  { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
492  },
493  .ctlIndex_5G = {
494  0x10, 0x16, 0x18, 0x40, 0x46,
495  0x48, 0x30, 0x36, 0x38
496  },
497  .ctl_freqbin_5G = {
498  {
499  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
500  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
501  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
502  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
503  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
504  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
505  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
506  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
507  },
508  {
509  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
510  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
511  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
512  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
513  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
514  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
515  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
516  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
517  },
518 
519  {
520  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
521  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
522  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
523  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
524  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
525  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
526  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
527  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
528  },
529 
530  {
531  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
532  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
533  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
534  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
535  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
536  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
537  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
538  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
539  },
540 
541  {
542  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
543  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
544  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
545  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
546  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
547  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
548  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
549  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
550  },
551 
552  {
553  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
554  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
555  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
556  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
557  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
558  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
559  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
560  /* Data[5].ctlEdges[7].bChannel */ 0xFF
561  },
562 
563  {
564  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
565  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
566  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
567  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
568  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
569  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
570  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
571  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
572  },
573 
574  {
575  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
576  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
577  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
578  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
579  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
580  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
581  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
582  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
583  },
584 
585  {
586  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
587  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
588  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
589  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
590  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
591  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
592  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
593  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
594  }
595  },
596  .ctlPowerData_5G = {
597  {
598  {
599  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
600  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
601  }
602  },
603  {
604  {
605  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
606  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
607  }
608  },
609  {
610  {
611  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
612  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
613  }
614  },
615  {
616  {
617  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
618  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
619  }
620  },
621  {
622  {
623  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
624  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
625  }
626  },
627  {
628  {
629  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
630  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
631  }
632  },
633  {
634  {
635  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
636  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
637  }
638  },
639  {
640  {
641  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
642  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
643  }
644  },
645  {
646  {
647  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
648  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
649  }
650  },
651  }
652 };
653 
654 static const struct ar9300_eeprom ar9300_x113 = {
655  .eepromVersion = 2,
656  .templateVersion = 6,
657  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
658  .custData = {"x113-023-f0000"},
659  .baseEepHeader = {
660  .regDmn = { LE16(0), LE16(0x1f) },
661  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
662  .opCapFlags = {
663  .opFlags = AR5416_OPFLAGS_11A,
664  .eepMisc = 0,
665  },
666  .rfSilent = 0,
667  .blueToothOptions = 0,
668  .deviceCap = 0,
669  .deviceType = 5, /* takes lower byte in eeprom location */
670  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
671  .params_for_tuning_caps = {0, 0},
672  .featureEnable = 0x0d,
673  /*
674  * bit0 - enable tx temp comp - disabled
675  * bit1 - enable tx volt comp - disabled
676  * bit2 - enable fastClock - enabled
677  * bit3 - enable doubling - enabled
678  * bit4 - enable internal regulator - disabled
679  * bit5 - enable pa predistortion - disabled
680  */
681  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
682  .eepromWriteEnableGpio = 6,
683  .wlanDisableGpio = 0,
684  .wlanLedGpio = 8,
685  .rxBandSelectGpio = 0xff,
686  .txrxgain = 0x21,
687  .swreg = 0,
688  },
689  .modalHeader2G = {
690  /* ar9300_modal_eep_header 2g */
691  /* 4 idle,t1,t2,b(4 bits per setting) */
692  .antCtrlCommon = LE32(0x110),
693  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
694  .antCtrlCommon2 = LE32(0x44444),
695 
696  /*
697  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
698  * rx1, rx12, b (2 bits each)
699  */
700  .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
701 
702  /*
703  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
704  * for ar9280 (0xa20c/b20c 5:0)
705  */
706  .xatten1DB = {0, 0, 0},
707 
708  /*
709  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
710  * for ar9280 (0xa20c/b20c 16:12
711  */
712  .xatten1Margin = {0, 0, 0},
713  .tempSlope = 25,
714  .voltSlope = 0,
715 
716  /*
717  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
718  * channels in usual fbin coding format
719  */
720  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
721 
722  /*
723  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
724  * if the register is per chain
725  */
726  .noiseFloorThreshCh = {-1, 0, 0},
727  .ob = {1, 1, 1},/* 3 chain */
728  .db_stage2 = {1, 1, 1}, /* 3 chain */
729  .db_stage3 = {0, 0, 0},
730  .db_stage4 = {0, 0, 0},
731  .xpaBiasLvl = 0,
732  .txFrameToDataStart = 0x0e,
733  .txFrameToPaOn = 0x0e,
734  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
735  .antennaGain = 0,
736  .switchSettling = 0x2c,
737  .adcDesiredSize = -30,
738  .txEndToXpaOff = 0,
739  .txEndToRxOn = 0x2,
740  .txFrameToXpaOn = 0xe,
741  .thresh62 = 28,
742  .papdRateMaskHt20 = LE32(0x0c80c080),
743  .papdRateMaskHt40 = LE32(0x0080c080),
744  .futureModal = {
745  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
746  },
747  },
748  .base_ext1 = {
749  .ant_div_control = 0,
750  .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
751  },
752  .calFreqPier2G = {
753  FREQ2FBIN(2412, 1),
754  FREQ2FBIN(2437, 1),
755  FREQ2FBIN(2472, 1),
756  },
757  /* ar9300_cal_data_per_freq_op_loop 2g */
758  .calPierData2G = {
759  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
760  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
761  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
762  },
763  .calTarget_freqbin_Cck = {
764  FREQ2FBIN(2412, 1),
765  FREQ2FBIN(2472, 1),
766  },
767  .calTarget_freqbin_2G = {
768  FREQ2FBIN(2412, 1),
769  FREQ2FBIN(2437, 1),
770  FREQ2FBIN(2472, 1)
771  },
772  .calTarget_freqbin_2GHT20 = {
773  FREQ2FBIN(2412, 1),
774  FREQ2FBIN(2437, 1),
775  FREQ2FBIN(2472, 1)
776  },
777  .calTarget_freqbin_2GHT40 = {
778  FREQ2FBIN(2412, 1),
779  FREQ2FBIN(2437, 1),
780  FREQ2FBIN(2472, 1)
781  },
782  .calTargetPowerCck = {
783  /* 1L-5L,5S,11L,11S */
784  { {34, 34, 34, 34} },
785  { {34, 34, 34, 34} },
786  },
787  .calTargetPower2G = {
788  /* 6-24,36,48,54 */
789  { {34, 34, 32, 32} },
790  { {34, 34, 32, 32} },
791  { {34, 34, 32, 32} },
792  },
793  .calTargetPower2GHT20 = {
794  { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
795  { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
796  { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
797  },
798  .calTargetPower2GHT40 = {
799  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
800  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
801  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
802  },
803  .ctlIndex_2G = {
804  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
805  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
806  },
807  .ctl_freqbin_2G = {
808  {
809  FREQ2FBIN(2412, 1),
810  FREQ2FBIN(2417, 1),
811  FREQ2FBIN(2457, 1),
812  FREQ2FBIN(2462, 1)
813  },
814  {
815  FREQ2FBIN(2412, 1),
816  FREQ2FBIN(2417, 1),
817  FREQ2FBIN(2462, 1),
818  0xFF,
819  },
820 
821  {
822  FREQ2FBIN(2412, 1),
823  FREQ2FBIN(2417, 1),
824  FREQ2FBIN(2462, 1),
825  0xFF,
826  },
827  {
828  FREQ2FBIN(2422, 1),
829  FREQ2FBIN(2427, 1),
830  FREQ2FBIN(2447, 1),
831  FREQ2FBIN(2452, 1)
832  },
833 
834  {
835  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
836  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
837  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
838  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
839  },
840 
841  {
842  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
843  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
844  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
845  0,
846  },
847 
848  {
849  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
850  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
851  FREQ2FBIN(2472, 1),
852  0,
853  },
854 
855  {
856  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
857  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
858  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
859  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
860  },
861 
862  {
863  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
864  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
865  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
866  },
867 
868  {
869  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
870  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
871  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
872  0
873  },
874 
875  {
876  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
877  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
878  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
879  0
880  },
881 
882  {
883  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
884  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
885  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
886  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
887  }
888  },
889  .ctlPowerData_2G = {
890  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
891  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
892  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
893 
894  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
895  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
896  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
897 
898  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
899  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
900  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
901 
902  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
903  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
904  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
905  },
906  .modalHeader5G = {
907  /* 4 idle,t1,t2,b (4 bits per setting) */
908  .antCtrlCommon = LE32(0x220),
909  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
910  .antCtrlCommon2 = LE32(0x11111),
911  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
912  .antCtrlChain = {
913  LE16(0x150), LE16(0x150), LE16(0x150),
914  },
915  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
916  .xatten1DB = {0, 0, 0},
917 
918  /*
919  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
920  * for merlin (0xa20c/b20c 16:12
921  */
922  .xatten1Margin = {0, 0, 0},
923  .tempSlope = 68,
924  .voltSlope = 0,
925  /* spurChans spur channels in usual fbin coding format */
926  .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
927  /* noiseFloorThreshCh Check if the register is per chain */
928  .noiseFloorThreshCh = {-1, 0, 0},
929  .ob = {3, 3, 3}, /* 3 chain */
930  .db_stage2 = {3, 3, 3}, /* 3 chain */
931  .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
932  .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
933  .xpaBiasLvl = 0xf,
934  .txFrameToDataStart = 0x0e,
935  .txFrameToPaOn = 0x0e,
936  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
937  .antennaGain = 0,
938  .switchSettling = 0x2d,
939  .adcDesiredSize = -30,
940  .txEndToXpaOff = 0,
941  .txEndToRxOn = 0x2,
942  .txFrameToXpaOn = 0xe,
943  .thresh62 = 28,
944  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
945  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
946  .futureModal = {
947  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
948  },
949  },
950  .base_ext2 = {
951  .tempSlopeLow = 72,
952  .tempSlopeHigh = 105,
953  .xatten1DBLow = {0, 0, 0},
954  .xatten1MarginLow = {0, 0, 0},
955  .xatten1DBHigh = {0, 0, 0},
956  .xatten1MarginHigh = {0, 0, 0}
957  },
958  .calFreqPier5G = {
959  FREQ2FBIN(5180, 0),
960  FREQ2FBIN(5240, 0),
961  FREQ2FBIN(5320, 0),
962  FREQ2FBIN(5400, 0),
963  FREQ2FBIN(5500, 0),
964  FREQ2FBIN(5600, 0),
965  FREQ2FBIN(5745, 0),
966  FREQ2FBIN(5785, 0)
967  },
968  .calPierData5G = {
969  {
970  {0, 0, 0, 0, 0, 0},
971  {0, 0, 0, 0, 0, 0},
972  {0, 0, 0, 0, 0, 0},
973  {0, 0, 0, 0, 0, 0},
974  {0, 0, 0, 0, 0, 0},
975  {0, 0, 0, 0, 0, 0},
976  {0, 0, 0, 0, 0, 0},
977  {0, 0, 0, 0, 0, 0},
978  },
979  {
980  {0, 0, 0, 0, 0, 0},
981  {0, 0, 0, 0, 0, 0},
982  {0, 0, 0, 0, 0, 0},
983  {0, 0, 0, 0, 0, 0},
984  {0, 0, 0, 0, 0, 0},
985  {0, 0, 0, 0, 0, 0},
986  {0, 0, 0, 0, 0, 0},
987  {0, 0, 0, 0, 0, 0},
988  },
989  {
990  {0, 0, 0, 0, 0, 0},
991  {0, 0, 0, 0, 0, 0},
992  {0, 0, 0, 0, 0, 0},
993  {0, 0, 0, 0, 0, 0},
994  {0, 0, 0, 0, 0, 0},
995  {0, 0, 0, 0, 0, 0},
996  {0, 0, 0, 0, 0, 0},
997  {0, 0, 0, 0, 0, 0},
998  },
999 
1000  },
1001  .calTarget_freqbin_5G = {
1002  FREQ2FBIN(5180, 0),
1003  FREQ2FBIN(5220, 0),
1004  FREQ2FBIN(5320, 0),
1005  FREQ2FBIN(5400, 0),
1006  FREQ2FBIN(5500, 0),
1007  FREQ2FBIN(5600, 0),
1008  FREQ2FBIN(5745, 0),
1009  FREQ2FBIN(5785, 0)
1010  },
1011  .calTarget_freqbin_5GHT20 = {
1012  FREQ2FBIN(5180, 0),
1013  FREQ2FBIN(5240, 0),
1014  FREQ2FBIN(5320, 0),
1015  FREQ2FBIN(5400, 0),
1016  FREQ2FBIN(5500, 0),
1017  FREQ2FBIN(5700, 0),
1018  FREQ2FBIN(5745, 0),
1019  FREQ2FBIN(5825, 0)
1020  },
1021  .calTarget_freqbin_5GHT40 = {
1022  FREQ2FBIN(5190, 0),
1023  FREQ2FBIN(5230, 0),
1024  FREQ2FBIN(5320, 0),
1025  FREQ2FBIN(5410, 0),
1026  FREQ2FBIN(5510, 0),
1027  FREQ2FBIN(5670, 0),
1028  FREQ2FBIN(5755, 0),
1029  FREQ2FBIN(5825, 0)
1030  },
1031  .calTargetPower5G = {
1032  /* 6-24,36,48,54 */
1033  { {42, 40, 40, 34} },
1034  { {42, 40, 40, 34} },
1035  { {42, 40, 40, 34} },
1036  { {42, 40, 40, 34} },
1037  { {42, 40, 40, 34} },
1038  { {42, 40, 40, 34} },
1039  { {42, 40, 40, 34} },
1040  { {42, 40, 40, 34} },
1041  },
1042  .calTargetPower5GHT20 = {
1043  /*
1044  * 0_8_16,1-3_9-11_17-19,
1045  * 4,5,6,7,12,13,14,15,20,21,22,23
1046  */
1047  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1048  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1049  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1050  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1051  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1052  { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1053  { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1054  { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1055  },
1056  .calTargetPower5GHT40 = {
1057  /*
1058  * 0_8_16,1-3_9-11_17-19,
1059  * 4,5,6,7,12,13,14,15,20,21,22,23
1060  */
1061  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1062  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1063  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1064  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1065  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1066  { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1067  { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1068  { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1069  },
1070  .ctlIndex_5G = {
1071  0x10, 0x16, 0x18, 0x40, 0x46,
1072  0x48, 0x30, 0x36, 0x38
1073  },
1074  .ctl_freqbin_5G = {
1075  {
1076  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1077  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1078  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1079  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1080  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1081  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1082  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1083  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1084  },
1085  {
1086  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1087  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1088  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1089  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1090  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1091  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1092  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1093  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1094  },
1095 
1096  {
1097  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1098  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1099  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1100  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1101  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1102  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1103  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1104  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1105  },
1106 
1107  {
1108  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1109  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1110  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1111  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1112  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1113  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1114  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1115  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1116  },
1117 
1118  {
1119  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1120  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1121  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1122  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1123  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1124  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1125  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1126  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1127  },
1128 
1129  {
1130  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1131  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1132  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1133  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1134  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1135  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1136  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1137  /* Data[5].ctlEdges[7].bChannel */ 0xFF
1138  },
1139 
1140  {
1141  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1142  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1143  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1144  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1145  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1146  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1147  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1148  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1149  },
1150 
1151  {
1152  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1153  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1154  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1155  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1156  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1157  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1158  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1159  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1160  },
1161 
1162  {
1163  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1164  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1165  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1166  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1167  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1168  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1169  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1170  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1171  }
1172  },
1173  .ctlPowerData_5G = {
1174  {
1175  {
1176  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1177  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1178  }
1179  },
1180  {
1181  {
1182  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1183  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1184  }
1185  },
1186  {
1187  {
1188  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1189  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1190  }
1191  },
1192  {
1193  {
1194  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1195  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1196  }
1197  },
1198  {
1199  {
1200  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1201  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1202  }
1203  },
1204  {
1205  {
1206  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1207  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1208  }
1209  },
1210  {
1211  {
1212  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1213  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1214  }
1215  },
1216  {
1217  {
1218  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1219  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1220  }
1221  },
1222  {
1223  {
1224  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1225  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1226  }
1227  },
1228  }
1229 };
1230 
1231 
1232 static const struct ar9300_eeprom ar9300_h112 = {
1233  .eepromVersion = 2,
1234  .templateVersion = 3,
1235  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1236  .custData = {"h112-241-f0000"},
1237  .baseEepHeader = {
1238  .regDmn = { LE16(0), LE16(0x1f) },
1239  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1240  .opCapFlags = {
1241  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1242  .eepMisc = 0,
1243  },
1244  .rfSilent = 0,
1245  .blueToothOptions = 0,
1246  .deviceCap = 0,
1247  .deviceType = 5, /* takes lower byte in eeprom location */
1248  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1249  .params_for_tuning_caps = {0, 0},
1250  .featureEnable = 0x0d,
1251  /*
1252  * bit0 - enable tx temp comp - disabled
1253  * bit1 - enable tx volt comp - disabled
1254  * bit2 - enable fastClock - enabled
1255  * bit3 - enable doubling - enabled
1256  * bit4 - enable internal regulator - disabled
1257  * bit5 - enable pa predistortion - disabled
1258  */
1259  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1260  .eepromWriteEnableGpio = 6,
1261  .wlanDisableGpio = 0,
1262  .wlanLedGpio = 8,
1263  .rxBandSelectGpio = 0xff,
1264  .txrxgain = 0x10,
1265  .swreg = 0,
1266  },
1267  .modalHeader2G = {
1268  /* ar9300_modal_eep_header 2g */
1269  /* 4 idle,t1,t2,b(4 bits per setting) */
1270  .antCtrlCommon = LE32(0x110),
1271  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1272  .antCtrlCommon2 = LE32(0x44444),
1273 
1274  /*
1275  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1276  * rx1, rx12, b (2 bits each)
1277  */
1278  .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1279 
1280  /*
1281  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1282  * for ar9280 (0xa20c/b20c 5:0)
1283  */
1284  .xatten1DB = {0, 0, 0},
1285 
1286  /*
1287  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1288  * for ar9280 (0xa20c/b20c 16:12
1289  */
1290  .xatten1Margin = {0, 0, 0},
1291  .tempSlope = 25,
1292  .voltSlope = 0,
1293 
1294  /*
1295  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1296  * channels in usual fbin coding format
1297  */
1298  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1299 
1300  /*
1301  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1302  * if the register is per chain
1303  */
1304  .noiseFloorThreshCh = {-1, 0, 0},
1305  .ob = {1, 1, 1},/* 3 chain */
1306  .db_stage2 = {1, 1, 1}, /* 3 chain */
1307  .db_stage3 = {0, 0, 0},
1308  .db_stage4 = {0, 0, 0},
1309  .xpaBiasLvl = 0,
1310  .txFrameToDataStart = 0x0e,
1311  .txFrameToPaOn = 0x0e,
1312  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1313  .antennaGain = 0,
1314  .switchSettling = 0x2c,
1315  .adcDesiredSize = -30,
1316  .txEndToXpaOff = 0,
1317  .txEndToRxOn = 0x2,
1318  .txFrameToXpaOn = 0xe,
1319  .thresh62 = 28,
1320  .papdRateMaskHt20 = LE32(0x80c080),
1321  .papdRateMaskHt40 = LE32(0x80c080),
1322  .futureModal = {
1323  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1324  },
1325  },
1326  .base_ext1 = {
1327  .ant_div_control = 0,
1328  .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1329  },
1330  .calFreqPier2G = {
1331  FREQ2FBIN(2412, 1),
1332  FREQ2FBIN(2437, 1),
1333  FREQ2FBIN(2472, 1),
1334  },
1335  /* ar9300_cal_data_per_freq_op_loop 2g */
1336  .calPierData2G = {
1337  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1338  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1339  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1340  },
1341  .calTarget_freqbin_Cck = {
1342  FREQ2FBIN(2412, 1),
1343  FREQ2FBIN(2484, 1),
1344  },
1345  .calTarget_freqbin_2G = {
1346  FREQ2FBIN(2412, 1),
1347  FREQ2FBIN(2437, 1),
1348  FREQ2FBIN(2472, 1)
1349  },
1350  .calTarget_freqbin_2GHT20 = {
1351  FREQ2FBIN(2412, 1),
1352  FREQ2FBIN(2437, 1),
1353  FREQ2FBIN(2472, 1)
1354  },
1355  .calTarget_freqbin_2GHT40 = {
1356  FREQ2FBIN(2412, 1),
1357  FREQ2FBIN(2437, 1),
1358  FREQ2FBIN(2472, 1)
1359  },
1360  .calTargetPowerCck = {
1361  /* 1L-5L,5S,11L,11S */
1362  { {34, 34, 34, 34} },
1363  { {34, 34, 34, 34} },
1364  },
1365  .calTargetPower2G = {
1366  /* 6-24,36,48,54 */
1367  { {34, 34, 32, 32} },
1368  { {34, 34, 32, 32} },
1369  { {34, 34, 32, 32} },
1370  },
1371  .calTargetPower2GHT20 = {
1372  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1373  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1374  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1375  },
1376  .calTargetPower2GHT40 = {
1377  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1378  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1379  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1380  },
1381  .ctlIndex_2G = {
1382  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1383  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1384  },
1385  .ctl_freqbin_2G = {
1386  {
1387  FREQ2FBIN(2412, 1),
1388  FREQ2FBIN(2417, 1),
1389  FREQ2FBIN(2457, 1),
1390  FREQ2FBIN(2462, 1)
1391  },
1392  {
1393  FREQ2FBIN(2412, 1),
1394  FREQ2FBIN(2417, 1),
1395  FREQ2FBIN(2462, 1),
1396  0xFF,
1397  },
1398 
1399  {
1400  FREQ2FBIN(2412, 1),
1401  FREQ2FBIN(2417, 1),
1402  FREQ2FBIN(2462, 1),
1403  0xFF,
1404  },
1405  {
1406  FREQ2FBIN(2422, 1),
1407  FREQ2FBIN(2427, 1),
1408  FREQ2FBIN(2447, 1),
1409  FREQ2FBIN(2452, 1)
1410  },
1411 
1412  {
1413  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1417  },
1418 
1419  {
1420  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1421  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1422  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1423  0,
1424  },
1425 
1426  {
1427  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429  FREQ2FBIN(2472, 1),
1430  0,
1431  },
1432 
1433  {
1434  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1435  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1436  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1437  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1438  },
1439 
1440  {
1441  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1442  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1443  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1444  },
1445 
1446  {
1447  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1448  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1449  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1450  0
1451  },
1452 
1453  {
1454  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1455  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1456  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1457  0
1458  },
1459 
1460  {
1461  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1462  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1463  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1464  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1465  }
1466  },
1467  .ctlPowerData_2G = {
1468  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1469  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1470  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1471 
1472  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
1473  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1474  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1475 
1476  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1477  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1478  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1479 
1480  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1481  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1482  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1483  },
1484  .modalHeader5G = {
1485  /* 4 idle,t1,t2,b (4 bits per setting) */
1486  .antCtrlCommon = LE32(0x220),
1487  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1488  .antCtrlCommon2 = LE32(0x44444),
1489  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1490  .antCtrlChain = {
1491  LE16(0x150), LE16(0x150), LE16(0x150),
1492  },
1493  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1494  .xatten1DB = {0, 0, 0},
1495 
1496  /*
1497  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1498  * for merlin (0xa20c/b20c 16:12
1499  */
1500  .xatten1Margin = {0, 0, 0},
1501  .tempSlope = 45,
1502  .voltSlope = 0,
1503  /* spurChans spur channels in usual fbin coding format */
1504  .spurChans = {0, 0, 0, 0, 0},
1505  /* noiseFloorThreshCh Check if the register is per chain */
1506  .noiseFloorThreshCh = {-1, 0, 0},
1507  .ob = {3, 3, 3}, /* 3 chain */
1508  .db_stage2 = {3, 3, 3}, /* 3 chain */
1509  .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1510  .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1511  .xpaBiasLvl = 0,
1512  .txFrameToDataStart = 0x0e,
1513  .txFrameToPaOn = 0x0e,
1514  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1515  .antennaGain = 0,
1516  .switchSettling = 0x2d,
1517  .adcDesiredSize = -30,
1518  .txEndToXpaOff = 0,
1519  .txEndToRxOn = 0x2,
1520  .txFrameToXpaOn = 0xe,
1521  .thresh62 = 28,
1522  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1523  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1524  .futureModal = {
1525  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1526  },
1527  },
1528  .base_ext2 = {
1529  .tempSlopeLow = 40,
1530  .tempSlopeHigh = 50,
1531  .xatten1DBLow = {0, 0, 0},
1532  .xatten1MarginLow = {0, 0, 0},
1533  .xatten1DBHigh = {0, 0, 0},
1534  .xatten1MarginHigh = {0, 0, 0}
1535  },
1536  .calFreqPier5G = {
1537  FREQ2FBIN(5180, 0),
1538  FREQ2FBIN(5220, 0),
1539  FREQ2FBIN(5320, 0),
1540  FREQ2FBIN(5400, 0),
1541  FREQ2FBIN(5500, 0),
1542  FREQ2FBIN(5600, 0),
1543  FREQ2FBIN(5700, 0),
1544  FREQ2FBIN(5825, 0)
1545  },
1546  .calPierData5G = {
1547  {
1548  {0, 0, 0, 0, 0, 0},
1549  {0, 0, 0, 0, 0, 0},
1550  {0, 0, 0, 0, 0, 0},
1551  {0, 0, 0, 0, 0, 0},
1552  {0, 0, 0, 0, 0, 0},
1553  {0, 0, 0, 0, 0, 0},
1554  {0, 0, 0, 0, 0, 0},
1555  {0, 0, 0, 0, 0, 0},
1556  },
1557  {
1558  {0, 0, 0, 0, 0, 0},
1559  {0, 0, 0, 0, 0, 0},
1560  {0, 0, 0, 0, 0, 0},
1561  {0, 0, 0, 0, 0, 0},
1562  {0, 0, 0, 0, 0, 0},
1563  {0, 0, 0, 0, 0, 0},
1564  {0, 0, 0, 0, 0, 0},
1565  {0, 0, 0, 0, 0, 0},
1566  },
1567  {
1568  {0, 0, 0, 0, 0, 0},
1569  {0, 0, 0, 0, 0, 0},
1570  {0, 0, 0, 0, 0, 0},
1571  {0, 0, 0, 0, 0, 0},
1572  {0, 0, 0, 0, 0, 0},
1573  {0, 0, 0, 0, 0, 0},
1574  {0, 0, 0, 0, 0, 0},
1575  {0, 0, 0, 0, 0, 0},
1576  },
1577 
1578  },
1579  .calTarget_freqbin_5G = {
1580  FREQ2FBIN(5180, 0),
1581  FREQ2FBIN(5240, 0),
1582  FREQ2FBIN(5320, 0),
1583  FREQ2FBIN(5400, 0),
1584  FREQ2FBIN(5500, 0),
1585  FREQ2FBIN(5600, 0),
1586  FREQ2FBIN(5700, 0),
1587  FREQ2FBIN(5825, 0)
1588  },
1589  .calTarget_freqbin_5GHT20 = {
1590  FREQ2FBIN(5180, 0),
1591  FREQ2FBIN(5240, 0),
1592  FREQ2FBIN(5320, 0),
1593  FREQ2FBIN(5400, 0),
1594  FREQ2FBIN(5500, 0),
1595  FREQ2FBIN(5700, 0),
1596  FREQ2FBIN(5745, 0),
1597  FREQ2FBIN(5825, 0)
1598  },
1599  .calTarget_freqbin_5GHT40 = {
1600  FREQ2FBIN(5180, 0),
1601  FREQ2FBIN(5240, 0),
1602  FREQ2FBIN(5320, 0),
1603  FREQ2FBIN(5400, 0),
1604  FREQ2FBIN(5500, 0),
1605  FREQ2FBIN(5700, 0),
1606  FREQ2FBIN(5745, 0),
1607  FREQ2FBIN(5825, 0)
1608  },
1609  .calTargetPower5G = {
1610  /* 6-24,36,48,54 */
1611  { {30, 30, 28, 24} },
1612  { {30, 30, 28, 24} },
1613  { {30, 30, 28, 24} },
1614  { {30, 30, 28, 24} },
1615  { {30, 30, 28, 24} },
1616  { {30, 30, 28, 24} },
1617  { {30, 30, 28, 24} },
1618  { {30, 30, 28, 24} },
1619  },
1620  .calTargetPower5GHT20 = {
1621  /*
1622  * 0_8_16,1-3_9-11_17-19,
1623  * 4,5,6,7,12,13,14,15,20,21,22,23
1624  */
1625  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1626  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1627  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1628  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1629  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1630  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1631  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1632  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1633  },
1634  .calTargetPower5GHT40 = {
1635  /*
1636  * 0_8_16,1-3_9-11_17-19,
1637  * 4,5,6,7,12,13,14,15,20,21,22,23
1638  */
1639  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1640  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1641  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1642  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1643  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1644  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1645  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1646  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1647  },
1648  .ctlIndex_5G = {
1649  0x10, 0x16, 0x18, 0x40, 0x46,
1650  0x48, 0x30, 0x36, 0x38
1651  },
1652  .ctl_freqbin_5G = {
1653  {
1654  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1657  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1658  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1659  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1660  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1661  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1662  },
1663  {
1664  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1665  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1666  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1667  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1668  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1669  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1670  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1671  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1672  },
1673 
1674  {
1675  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1676  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1677  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1678  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1679  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1680  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1681  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1682  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1683  },
1684 
1685  {
1686  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1687  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1688  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1689  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1690  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1691  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1692  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1693  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1694  },
1695 
1696  {
1697  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1698  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1699  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1700  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1701  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1702  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1703  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1704  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1705  },
1706 
1707  {
1708  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1709  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1710  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1711  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1712  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1713  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1714  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1715  /* Data[5].ctlEdges[7].bChannel */ 0xFF
1716  },
1717 
1718  {
1719  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1720  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1721  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1722  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1723  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1724  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1725  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1726  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1727  },
1728 
1729  {
1730  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1731  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1732  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1733  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1734  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1735  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1736  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1737  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1738  },
1739 
1740  {
1741  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1742  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1743  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1744  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1745  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1746  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1747  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1748  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1749  }
1750  },
1751  .ctlPowerData_5G = {
1752  {
1753  {
1754  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1755  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1756  }
1757  },
1758  {
1759  {
1760  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1761  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1762  }
1763  },
1764  {
1765  {
1766  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1767  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1768  }
1769  },
1770  {
1771  {
1772  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1773  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1774  }
1775  },
1776  {
1777  {
1778  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1779  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1780  }
1781  },
1782  {
1783  {
1784  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1785  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1786  }
1787  },
1788  {
1789  {
1790  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1791  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1792  }
1793  },
1794  {
1795  {
1796  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1797  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1798  }
1799  },
1800  {
1801  {
1802  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1803  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1804  }
1805  },
1806  }
1807 };
1808 
1809 
1810 static const struct ar9300_eeprom ar9300_x112 = {
1811  .eepromVersion = 2,
1812  .templateVersion = 5,
1813  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1814  .custData = {"x112-041-f0000"},
1815  .baseEepHeader = {
1816  .regDmn = { LE16(0), LE16(0x1f) },
1817  .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1818  .opCapFlags = {
1819  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1820  .eepMisc = 0,
1821  },
1822  .rfSilent = 0,
1823  .blueToothOptions = 0,
1824  .deviceCap = 0,
1825  .deviceType = 5, /* takes lower byte in eeprom location */
1826  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1827  .params_for_tuning_caps = {0, 0},
1828  .featureEnable = 0x0d,
1829  /*
1830  * bit0 - enable tx temp comp - disabled
1831  * bit1 - enable tx volt comp - disabled
1832  * bit2 - enable fastclock - enabled
1833  * bit3 - enable doubling - enabled
1834  * bit4 - enable internal regulator - disabled
1835  * bit5 - enable pa predistortion - disabled
1836  */
1837  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1838  .eepromWriteEnableGpio = 6,
1839  .wlanDisableGpio = 0,
1840  .wlanLedGpio = 8,
1841  .rxBandSelectGpio = 0xff,
1842  .txrxgain = 0x0,
1843  .swreg = 0,
1844  },
1845  .modalHeader2G = {
1846  /* ar9300_modal_eep_header 2g */
1847  /* 4 idle,t1,t2,b(4 bits per setting) */
1848  .antCtrlCommon = LE32(0x110),
1849  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1850  .antCtrlCommon2 = LE32(0x22222),
1851 
1852  /*
1853  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1854  * rx1, rx12, b (2 bits each)
1855  */
1856  .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1857 
1858  /*
1859  * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1860  * for ar9280 (0xa20c/b20c 5:0)
1861  */
1862  .xatten1DB = {0x1b, 0x1b, 0x1b},
1863 
1864  /*
1865  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1866  * for ar9280 (0xa20c/b20c 16:12
1867  */
1868  .xatten1Margin = {0x15, 0x15, 0x15},
1869  .tempSlope = 50,
1870  .voltSlope = 0,
1871 
1872  /*
1873  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1874  * channels in usual fbin coding format
1875  */
1876  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1877 
1878  /*
1879  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1880  * if the register is per chain
1881  */
1882  .noiseFloorThreshCh = {-1, 0, 0},
1883  .ob = {1, 1, 1},/* 3 chain */
1884  .db_stage2 = {1, 1, 1}, /* 3 chain */
1885  .db_stage3 = {0, 0, 0},
1886  .db_stage4 = {0, 0, 0},
1887  .xpaBiasLvl = 0,
1888  .txFrameToDataStart = 0x0e,
1889  .txFrameToPaOn = 0x0e,
1890  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1891  .antennaGain = 0,
1892  .switchSettling = 0x2c,
1893  .adcDesiredSize = -30,
1894  .txEndToXpaOff = 0,
1895  .txEndToRxOn = 0x2,
1896  .txFrameToXpaOn = 0xe,
1897  .thresh62 = 28,
1898  .papdRateMaskHt20 = LE32(0x0c80c080),
1899  .papdRateMaskHt40 = LE32(0x0080c080),
1900  .futureModal = {
1901  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1902  },
1903  },
1904  .base_ext1 = {
1905  .ant_div_control = 0,
1906  .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1907  },
1908  .calFreqPier2G = {
1909  FREQ2FBIN(2412, 1),
1910  FREQ2FBIN(2437, 1),
1911  FREQ2FBIN(2472, 1),
1912  },
1913  /* ar9300_cal_data_per_freq_op_loop 2g */
1914  .calPierData2G = {
1915  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1916  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1917  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1918  },
1919  .calTarget_freqbin_Cck = {
1920  FREQ2FBIN(2412, 1),
1921  FREQ2FBIN(2472, 1),
1922  },
1923  .calTarget_freqbin_2G = {
1924  FREQ2FBIN(2412, 1),
1925  FREQ2FBIN(2437, 1),
1926  FREQ2FBIN(2472, 1)
1927  },
1928  .calTarget_freqbin_2GHT20 = {
1929  FREQ2FBIN(2412, 1),
1930  FREQ2FBIN(2437, 1),
1931  FREQ2FBIN(2472, 1)
1932  },
1933  .calTarget_freqbin_2GHT40 = {
1934  FREQ2FBIN(2412, 1),
1935  FREQ2FBIN(2437, 1),
1936  FREQ2FBIN(2472, 1)
1937  },
1938  .calTargetPowerCck = {
1939  /* 1L-5L,5S,11L,11s */
1940  { {38, 38, 38, 38} },
1941  { {38, 38, 38, 38} },
1942  },
1943  .calTargetPower2G = {
1944  /* 6-24,36,48,54 */
1945  { {38, 38, 36, 34} },
1946  { {38, 38, 36, 34} },
1947  { {38, 38, 34, 32} },
1948  },
1949  .calTargetPower2GHT20 = {
1950  { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1951  { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1952  { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1953  },
1954  .calTargetPower2GHT40 = {
1955  { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1956  { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1957  { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1958  },
1959  .ctlIndex_2G = {
1960  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1961  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1962  },
1963  .ctl_freqbin_2G = {
1964  {
1965  FREQ2FBIN(2412, 1),
1966  FREQ2FBIN(2417, 1),
1967  FREQ2FBIN(2457, 1),
1968  FREQ2FBIN(2462, 1)
1969  },
1970  {
1971  FREQ2FBIN(2412, 1),
1972  FREQ2FBIN(2417, 1),
1973  FREQ2FBIN(2462, 1),
1974  0xFF,
1975  },
1976 
1977  {
1978  FREQ2FBIN(2412, 1),
1979  FREQ2FBIN(2417, 1),
1980  FREQ2FBIN(2462, 1),
1981  0xFF,
1982  },
1983  {
1984  FREQ2FBIN(2422, 1),
1985  FREQ2FBIN(2427, 1),
1986  FREQ2FBIN(2447, 1),
1987  FREQ2FBIN(2452, 1)
1988  },
1989 
1990  {
1991  /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992  /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993  /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994  /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1995  },
1996 
1997  {
1998  /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999  /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000  /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2001  0,
2002  },
2003 
2004  {
2005  /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006  /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007  FREQ2FBIN(2472, 1),
2008  0,
2009  },
2010 
2011  {
2012  /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2013  /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2014  /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2015  /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2016  },
2017 
2018  {
2019  /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2020  /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2021  /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2022  },
2023 
2024  {
2025  /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2026  /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2027  /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2028  0
2029  },
2030 
2031  {
2032  /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2033  /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2034  /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2035  0
2036  },
2037 
2038  {
2039  /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2040  /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2041  /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2042  /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2043  }
2044  },
2045  .ctlPowerData_2G = {
2046  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2047  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2048  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2049 
2050  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2051  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2052  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2053 
2054  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2055  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2056  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2057 
2058  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2059  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2060  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2061  },
2062  .modalHeader5G = {
2063  /* 4 idle,t1,t2,b (4 bits per setting) */
2064  .antCtrlCommon = LE32(0x110),
2065  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2066  .antCtrlCommon2 = LE32(0x22222),
2067  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2068  .antCtrlChain = {
2069  LE16(0x0), LE16(0x0), LE16(0x0),
2070  },
2071  /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2072  .xatten1DB = {0x13, 0x19, 0x17},
2073 
2074  /*
2075  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2076  * for merlin (0xa20c/b20c 16:12
2077  */
2078  .xatten1Margin = {0x19, 0x19, 0x19},
2079  .tempSlope = 70,
2080  .voltSlope = 15,
2081  /* spurChans spur channels in usual fbin coding format */
2082  .spurChans = {0, 0, 0, 0, 0},
2083  /* noiseFloorThreshch check if the register is per chain */
2084  .noiseFloorThreshCh = {-1, 0, 0},
2085  .ob = {3, 3, 3}, /* 3 chain */
2086  .db_stage2 = {3, 3, 3}, /* 3 chain */
2087  .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2088  .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2089  .xpaBiasLvl = 0,
2090  .txFrameToDataStart = 0x0e,
2091  .txFrameToPaOn = 0x0e,
2092  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2093  .antennaGain = 0,
2094  .switchSettling = 0x2d,
2095  .adcDesiredSize = -30,
2096  .txEndToXpaOff = 0,
2097  .txEndToRxOn = 0x2,
2098  .txFrameToXpaOn = 0xe,
2099  .thresh62 = 28,
2100  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2101  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2102  .futureModal = {
2103  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2104  },
2105  },
2106  .base_ext2 = {
2107  .tempSlopeLow = 72,
2108  .tempSlopeHigh = 105,
2109  .xatten1DBLow = {0x10, 0x14, 0x10},
2110  .xatten1MarginLow = {0x19, 0x19 , 0x19},
2111  .xatten1DBHigh = {0x1d, 0x20, 0x24},
2112  .xatten1MarginHigh = {0x10, 0x10, 0x10}
2113  },
2114  .calFreqPier5G = {
2115  FREQ2FBIN(5180, 0),
2116  FREQ2FBIN(5220, 0),
2117  FREQ2FBIN(5320, 0),
2118  FREQ2FBIN(5400, 0),
2119  FREQ2FBIN(5500, 0),
2120  FREQ2FBIN(5600, 0),
2121  FREQ2FBIN(5700, 0),
2122  FREQ2FBIN(5785, 0)
2123  },
2124  .calPierData5G = {
2125  {
2126  {0, 0, 0, 0, 0, 0},
2127  {0, 0, 0, 0, 0, 0},
2128  {0, 0, 0, 0, 0, 0},
2129  {0, 0, 0, 0, 0, 0},
2130  {0, 0, 0, 0, 0, 0},
2131  {0, 0, 0, 0, 0, 0},
2132  {0, 0, 0, 0, 0, 0},
2133  {0, 0, 0, 0, 0, 0},
2134  },
2135  {
2136  {0, 0, 0, 0, 0, 0},
2137  {0, 0, 0, 0, 0, 0},
2138  {0, 0, 0, 0, 0, 0},
2139  {0, 0, 0, 0, 0, 0},
2140  {0, 0, 0, 0, 0, 0},
2141  {0, 0, 0, 0, 0, 0},
2142  {0, 0, 0, 0, 0, 0},
2143  {0, 0, 0, 0, 0, 0},
2144  },
2145  {
2146  {0, 0, 0, 0, 0, 0},
2147  {0, 0, 0, 0, 0, 0},
2148  {0, 0, 0, 0, 0, 0},
2149  {0, 0, 0, 0, 0, 0},
2150  {0, 0, 0, 0, 0, 0},
2151  {0, 0, 0, 0, 0, 0},
2152  {0, 0, 0, 0, 0, 0},
2153  {0, 0, 0, 0, 0, 0},
2154  },
2155 
2156  },
2157  .calTarget_freqbin_5G = {
2158  FREQ2FBIN(5180, 0),
2159  FREQ2FBIN(5220, 0),
2160  FREQ2FBIN(5320, 0),
2161  FREQ2FBIN(5400, 0),
2162  FREQ2FBIN(5500, 0),
2163  FREQ2FBIN(5600, 0),
2164  FREQ2FBIN(5725, 0),
2165  FREQ2FBIN(5825, 0)
2166  },
2167  .calTarget_freqbin_5GHT20 = {
2168  FREQ2FBIN(5180, 0),
2169  FREQ2FBIN(5220, 0),
2170  FREQ2FBIN(5320, 0),
2171  FREQ2FBIN(5400, 0),
2172  FREQ2FBIN(5500, 0),
2173  FREQ2FBIN(5600, 0),
2174  FREQ2FBIN(5725, 0),
2175  FREQ2FBIN(5825, 0)
2176  },
2177  .calTarget_freqbin_5GHT40 = {
2178  FREQ2FBIN(5180, 0),
2179  FREQ2FBIN(5220, 0),
2180  FREQ2FBIN(5320, 0),
2181  FREQ2FBIN(5400, 0),
2182  FREQ2FBIN(5500, 0),
2183  FREQ2FBIN(5600, 0),
2184  FREQ2FBIN(5725, 0),
2185  FREQ2FBIN(5825, 0)
2186  },
2187  .calTargetPower5G = {
2188  /* 6-24,36,48,54 */
2189  { {32, 32, 28, 26} },
2190  { {32, 32, 28, 26} },
2191  { {32, 32, 28, 26} },
2192  { {32, 32, 26, 24} },
2193  { {32, 32, 26, 24} },
2194  { {32, 32, 24, 22} },
2195  { {30, 30, 24, 22} },
2196  { {30, 30, 24, 22} },
2197  },
2198  .calTargetPower5GHT20 = {
2199  /*
2200  * 0_8_16,1-3_9-11_17-19,
2201  * 4,5,6,7,12,13,14,15,20,21,22,23
2202  */
2203  { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2204  { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2205  { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2206  { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2207  { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2208  { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2209  { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2210  { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2211  },
2212  .calTargetPower5GHT40 = {
2213  /*
2214  * 0_8_16,1-3_9-11_17-19,
2215  * 4,5,6,7,12,13,14,15,20,21,22,23
2216  */
2217  { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2218  { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2219  { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2220  { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2221  { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2222  { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2223  { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2224  { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2225  },
2226  .ctlIndex_5G = {
2227  0x10, 0x16, 0x18, 0x40, 0x46,
2228  0x48, 0x30, 0x36, 0x38
2229  },
2230  .ctl_freqbin_5G = {
2231  {
2232  /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2233  /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2234  /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2235  /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2236  /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2237  /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2238  /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2239  /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2240  },
2241  {
2242  /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2243  /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2244  /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2245  /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2246  /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2247  /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2248  /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2249  /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2250  },
2251 
2252  {
2253  /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2254  /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2255  /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2256  /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2257  /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2258  /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2259  /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2260  /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2261  },
2262 
2263  {
2264  /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2265  /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2266  /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2267  /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2268  /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2269  /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2270  /* Data[3].ctledges[6].bchannel */ 0xFF,
2271  /* Data[3].ctledges[7].bchannel */ 0xFF,
2272  },
2273 
2274  {
2275  /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2276  /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2277  /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2278  /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2279  /* Data[4].ctledges[4].bchannel */ 0xFF,
2280  /* Data[4].ctledges[5].bchannel */ 0xFF,
2281  /* Data[4].ctledges[6].bchannel */ 0xFF,
2282  /* Data[4].ctledges[7].bchannel */ 0xFF,
2283  },
2284 
2285  {
2286  /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2287  /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2288  /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2289  /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2290  /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2291  /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2292  /* Data[5].ctledges[6].bchannel */ 0xFF,
2293  /* Data[5].ctledges[7].bchannel */ 0xFF
2294  },
2295 
2296  {
2297  /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2298  /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2299  /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2300  /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2301  /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2302  /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2303  /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2304  /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2305  },
2306 
2307  {
2308  /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2309  /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2310  /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2311  /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2312  /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2313  /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2314  /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2315  /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2316  },
2317 
2318  {
2319  /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2320  /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2321  /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2322  /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2323  /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2324  /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2325  /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2326  /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2327  }
2328  },
2329  .ctlPowerData_5G = {
2330  {
2331  {
2332  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2333  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2334  }
2335  },
2336  {
2337  {
2338  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2339  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2340  }
2341  },
2342  {
2343  {
2344  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2345  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2346  }
2347  },
2348  {
2349  {
2350  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2351  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2352  }
2353  },
2354  {
2355  {
2356  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2357  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2358  }
2359  },
2360  {
2361  {
2362  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2363  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2364  }
2365  },
2366  {
2367  {
2368  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2369  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2370  }
2371  },
2372  {
2373  {
2374  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2375  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2376  }
2377  },
2378  {
2379  {
2380  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2381  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2382  }
2383  },
2384  }
2385 };
2386 
2387 static const struct ar9300_eeprom ar9300_h116 = {
2388  .eepromVersion = 2,
2389  .templateVersion = 4,
2390  .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2391  .custData = {"h116-041-f0000"},
2392  .baseEepHeader = {
2393  .regDmn = { LE16(0), LE16(0x1f) },
2394  .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2395  .opCapFlags = {
2396  .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2397  .eepMisc = 0,
2398  },
2399  .rfSilent = 0,
2400  .blueToothOptions = 0,
2401  .deviceCap = 0,
2402  .deviceType = 5, /* takes lower byte in eeprom location */
2403  .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2404  .params_for_tuning_caps = {0, 0},
2405  .featureEnable = 0x0d,
2406  /*
2407  * bit0 - enable tx temp comp - disabled
2408  * bit1 - enable tx volt comp - disabled
2409  * bit2 - enable fastClock - enabled
2410  * bit3 - enable doubling - enabled
2411  * bit4 - enable internal regulator - disabled
2412  * bit5 - enable pa predistortion - disabled
2413  */
2414  .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2415  .eepromWriteEnableGpio = 6,
2416  .wlanDisableGpio = 0,
2417  .wlanLedGpio = 8,
2418  .rxBandSelectGpio = 0xff,
2419  .txrxgain = 0x10,
2420  .swreg = 0,
2421  },
2422  .modalHeader2G = {
2423  /* ar9300_modal_eep_header 2g */
2424  /* 4 idle,t1,t2,b(4 bits per setting) */
2425  .antCtrlCommon = LE32(0x110),
2426  /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2427  .antCtrlCommon2 = LE32(0x44444),
2428 
2429  /*
2430  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2431  * rx1, rx12, b (2 bits each)
2432  */
2433  .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2434 
2435  /*
2436  * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2437  * for ar9280 (0xa20c/b20c 5:0)
2438  */
2439  .xatten1DB = {0x1f, 0x1f, 0x1f},
2440 
2441  /*
2442  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2443  * for ar9280 (0xa20c/b20c 16:12
2444  */
2445  .xatten1Margin = {0x12, 0x12, 0x12},
2446  .tempSlope = 25,
2447  .voltSlope = 0,
2448 
2449  /*
2450  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2451  * channels in usual fbin coding format
2452  */
2453  .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2454 
2455  /*
2456  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2457  * if the register is per chain
2458  */
2459  .noiseFloorThreshCh = {-1, 0, 0},
2460  .ob = {1, 1, 1},/* 3 chain */
2461  .db_stage2 = {1, 1, 1}, /* 3 chain */
2462  .db_stage3 = {0, 0, 0},
2463  .db_stage4 = {0, 0, 0},
2464  .xpaBiasLvl = 0,
2465  .txFrameToDataStart = 0x0e,
2466  .txFrameToPaOn = 0x0e,
2467  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2468  .antennaGain = 0,
2469  .switchSettling = 0x2c,
2470  .adcDesiredSize = -30,
2471  .txEndToXpaOff = 0,
2472  .txEndToRxOn = 0x2,
2473  .txFrameToXpaOn = 0xe,
2474  .thresh62 = 28,
2475  .papdRateMaskHt20 = LE32(0x0c80C080),
2476  .papdRateMaskHt40 = LE32(0x0080C080),
2477  .futureModal = {
2478  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2479  },
2480  },
2481  .base_ext1 = {
2482  .ant_div_control = 0,
2483  .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2484  },
2485  .calFreqPier2G = {
2486  FREQ2FBIN(2412, 1),
2487  FREQ2FBIN(2437, 1),
2488  FREQ2FBIN(2472, 1),
2489  },
2490  /* ar9300_cal_data_per_freq_op_loop 2g */
2491  .calPierData2G = {
2492  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2493  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2494  { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2495  },
2496  .calTarget_freqbin_Cck = {
2497  FREQ2FBIN(2412, 1),
2498  FREQ2FBIN(2472, 1),
2499  },
2500  .calTarget_freqbin_2G = {
2501  FREQ2FBIN(2412, 1),
2502  FREQ2FBIN(2437, 1),
2503  FREQ2FBIN(2472, 1)
2504  },
2505  .calTarget_freqbin_2GHT20 = {
2506  FREQ2FBIN(2412, 1),
2507  FREQ2FBIN(2437, 1),
2508  FREQ2FBIN(2472, 1)
2509  },
2510  .calTarget_freqbin_2GHT40 = {
2511  FREQ2FBIN(2412, 1),
2512  FREQ2FBIN(2437, 1),
2513  FREQ2FBIN(2472, 1)
2514  },
2515  .calTargetPowerCck = {
2516  /* 1L-5L,5S,11L,11S */
2517  { {34, 34, 34, 34} },
2518  { {34, 34, 34, 34} },
2519  },
2520  .calTargetPower2G = {
2521  /* 6-24,36,48,54 */
2522  { {34, 34, 32, 32} },
2523  { {34, 34, 32, 32} },
2524  { {34, 34, 32, 32} },
2525  },
2526  .calTargetPower2GHT20 = {
2527  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2528  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2529  { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2530  },
2531  .calTargetPower2GHT40 = {
2532  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2533  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2534  { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2535  },
2536  .ctlIndex_2G = {
2537  0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2538  0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2539  },
2540  .ctl_freqbin_2G = {
2541  {
2542  FREQ2FBIN(2412, 1),
2543  FREQ2FBIN(2417, 1),
2544  FREQ2FBIN(2457, 1),
2545  FREQ2FBIN(2462, 1)
2546  },
2547  {
2548  FREQ2FBIN(2412, 1),
2549  FREQ2FBIN(2417, 1),
2550  FREQ2FBIN(2462, 1),
2551  0xFF,
2552  },
2553 
2554  {
2555  FREQ2FBIN(2412, 1),
2556  FREQ2FBIN(2417, 1),
2557  FREQ2FBIN(2462, 1),
2558  0xFF,
2559  },
2560  {
2561  FREQ2FBIN(2422, 1),
2562  FREQ2FBIN(2427, 1),
2563  FREQ2FBIN(2447, 1),
2564  FREQ2FBIN(2452, 1)
2565  },
2566 
2567  {
2568  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2571  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2572  },
2573 
2574  {
2575  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2576  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2577  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2578  0,
2579  },
2580 
2581  {
2582  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584  FREQ2FBIN(2472, 1),
2585  0,
2586  },
2587 
2588  {
2589  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2590  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2591  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2592  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2593  },
2594 
2595  {
2596  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2597  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2598  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2599  },
2600 
2601  {
2602  /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2603  /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2604  /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2605  0
2606  },
2607 
2608  {
2609  /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2610  /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2611  /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2612  0
2613  },
2614 
2615  {
2616  /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2617  /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2618  /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2619  /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2620  }
2621  },
2622  .ctlPowerData_2G = {
2623  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2624  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2625  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2626 
2627  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2628  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2629  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2630 
2631  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2632  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2633  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2634 
2635  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2636  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2637  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2638  },
2639  .modalHeader5G = {
2640  /* 4 idle,t1,t2,b (4 bits per setting) */
2641  .antCtrlCommon = LE32(0x220),
2642  /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2643  .antCtrlCommon2 = LE32(0x44444),
2644  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2645  .antCtrlChain = {
2646  LE16(0x150), LE16(0x150), LE16(0x150),
2647  },
2648  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2649  .xatten1DB = {0x19, 0x19, 0x19},
2650 
2651  /*
2652  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2653  * for merlin (0xa20c/b20c 16:12
2654  */
2655  .xatten1Margin = {0x14, 0x14, 0x14},
2656  .tempSlope = 70,
2657  .voltSlope = 0,
2658  /* spurChans spur channels in usual fbin coding format */
2659  .spurChans = {0, 0, 0, 0, 0},
2660  /* noiseFloorThreshCh Check if the register is per chain */
2661  .noiseFloorThreshCh = {-1, 0, 0},
2662  .ob = {3, 3, 3}, /* 3 chain */
2663  .db_stage2 = {3, 3, 3}, /* 3 chain */
2664  .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2665  .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2666  .xpaBiasLvl = 0,
2667  .txFrameToDataStart = 0x0e,
2668  .txFrameToPaOn = 0x0e,
2669  .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2670  .antennaGain = 0,
2671  .switchSettling = 0x2d,
2672  .adcDesiredSize = -30,
2673  .txEndToXpaOff = 0,
2674  .txEndToRxOn = 0x2,
2675  .txFrameToXpaOn = 0xe,
2676  .thresh62 = 28,
2677  .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2678  .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2679  .futureModal = {
2680  0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2681  },
2682  },
2683  .base_ext2 = {
2684  .tempSlopeLow = 35,
2685  .tempSlopeHigh = 50,
2686  .xatten1DBLow = {0, 0, 0},
2687  .xatten1MarginLow = {0, 0, 0},
2688  .xatten1DBHigh = {0, 0, 0},
2689  .xatten1MarginHigh = {0, 0, 0}
2690  },
2691  .calFreqPier5G = {
2692  FREQ2FBIN(5180, 0),
2693  FREQ2FBIN(5220, 0),
2694  FREQ2FBIN(5320, 0),
2695  FREQ2FBIN(5400, 0),
2696  FREQ2FBIN(5500, 0),
2697  FREQ2FBIN(5600, 0),
2698  FREQ2FBIN(5700, 0),
2699  FREQ2FBIN(5785, 0)
2700  },
2701  .calPierData5G = {
2702  {
2703  {0, 0, 0, 0, 0, 0},
2704  {0, 0, 0, 0, 0, 0},
2705  {0, 0, 0, 0, 0, 0},
2706  {0, 0, 0, 0, 0, 0},
2707  {0, 0, 0, 0, 0, 0},
2708  {0, 0, 0, 0, 0, 0},
2709  {0, 0, 0, 0, 0, 0},
2710  {0, 0, 0, 0, 0, 0},
2711  },
2712  {
2713  {0, 0, 0, 0, 0, 0},
2714  {0, 0, 0, 0, 0, 0},
2715  {0, 0, 0, 0, 0, 0},
2716  {0, 0, 0, 0, 0, 0},
2717  {0, 0, 0, 0, 0, 0},
2718  {0, 0, 0, 0, 0, 0},
2719  {0, 0, 0, 0, 0, 0},
2720  {0, 0, 0, 0, 0, 0},
2721  },
2722  {
2723  {0, 0, 0, 0, 0, 0},
2724  {0, 0, 0, 0, 0, 0},
2725  {0, 0, 0, 0, 0, 0},
2726  {0, 0, 0, 0, 0, 0},
2727  {0, 0, 0, 0, 0, 0},
2728  {0, 0, 0, 0, 0, 0},
2729  {0, 0, 0, 0, 0, 0},
2730  {0, 0, 0, 0, 0, 0},
2731  },
2732 
2733  },
2734  .calTarget_freqbin_5G = {
2735  FREQ2FBIN(5180, 0),
2736  FREQ2FBIN(5240, 0),
2737  FREQ2FBIN(5320, 0),
2738  FREQ2FBIN(5400, 0),
2739  FREQ2FBIN(5500, 0),
2740  FREQ2FBIN(5600, 0),
2741  FREQ2FBIN(5700, 0),
2742  FREQ2FBIN(5825, 0)
2743  },
2744  .calTarget_freqbin_5GHT20 = {
2745  FREQ2FBIN(5180, 0),
2746  FREQ2FBIN(5240, 0),
2747  FREQ2FBIN(5320, 0),
2748  FREQ2FBIN(5400, 0),
2749  FREQ2FBIN(5500, 0),
2750  FREQ2FBIN(5700, 0),
2751  FREQ2FBIN(5745, 0),
2752  FREQ2FBIN(5825, 0)
2753  },
2754  .calTarget_freqbin_5GHT40 = {
2755  FREQ2FBIN(5180, 0),
2756  FREQ2FBIN(5240, 0),
2757  FREQ2FBIN(5320, 0),
2758  FREQ2FBIN(5400, 0),
2759  FREQ2FBIN(5500, 0),
2760  FREQ2FBIN(5700, 0),
2761  FREQ2FBIN(5745, 0),
2762  FREQ2FBIN(5825, 0)
2763  },
2764  .calTargetPower5G = {
2765  /* 6-24,36,48,54 */
2766  { {30, 30, 28, 24} },
2767  { {30, 30, 28, 24} },
2768  { {30, 30, 28, 24} },
2769  { {30, 30, 28, 24} },
2770  { {30, 30, 28, 24} },
2771  { {30, 30, 28, 24} },
2772  { {30, 30, 28, 24} },
2773  { {30, 30, 28, 24} },
2774  },
2775  .calTargetPower5GHT20 = {
2776  /*
2777  * 0_8_16,1-3_9-11_17-19,
2778  * 4,5,6,7,12,13,14,15,20,21,22,23
2779  */
2780  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2781  { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2782  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2783  { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2784  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2785  { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2786  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2787  { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2788  },
2789  .calTargetPower5GHT40 = {
2790  /*
2791  * 0_8_16,1-3_9-11_17-19,
2792  * 4,5,6,7,12,13,14,15,20,21,22,23
2793  */
2794  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2795  { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2796  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2797  { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2798  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2799  { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2800  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2801  { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2802  },
2803  .ctlIndex_5G = {
2804  0x10, 0x16, 0x18, 0x40, 0x46,
2805  0x48, 0x30, 0x36, 0x38
2806  },
2807  .ctl_freqbin_5G = {
2808  {
2809  /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2810  /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2811  /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2812  /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2813  /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2814  /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2815  /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2816  /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2817  },
2818  {
2819  /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2820  /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2821  /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2822  /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2823  /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2824  /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2825  /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2826  /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2827  },
2828 
2829  {
2830  /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2831  /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2832  /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2833  /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2834  /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2835  /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2836  /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2837  /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2838  },
2839 
2840  {
2841  /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2842  /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2843  /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2844  /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2845  /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2846  /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2847  /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2848  /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2849  },
2850 
2851  {
2852  /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2853  /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2854  /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2855  /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2856  /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2857  /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2858  /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2859  /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2860  },
2861 
2862  {
2863  /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2864  /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2865  /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2866  /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2867  /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2868  /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2869  /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2870  /* Data[5].ctlEdges[7].bChannel */ 0xFF
2871  },
2872 
2873  {
2874  /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2875  /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2876  /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2877  /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2878  /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2879  /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2880  /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2881  /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2882  },
2883 
2884  {
2885  /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2886  /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2887  /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2888  /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2889  /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2890  /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2891  /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2892  /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2893  },
2894 
2895  {
2896  /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2897  /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2898  /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2899  /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2900  /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2901  /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2902  /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2903  /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2904  }
2905  },
2906  .ctlPowerData_5G = {
2907  {
2908  {
2909  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2910  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2911  }
2912  },
2913  {
2914  {
2915  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2916  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2917  }
2918  },
2919  {
2920  {
2921  CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2922  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2923  }
2924  },
2925  {
2926  {
2927  CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2928  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2929  }
2930  },
2931  {
2932  {
2933  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2934  CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2935  }
2936  },
2937  {
2938  {
2939  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2940  CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2941  }
2942  },
2943  {
2944  {
2945  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2946  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2947  }
2948  },
2949  {
2950  {
2951  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2952  CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2953  }
2954  },
2955  {
2956  {
2957  CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2958  CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2959  }
2960  },
2961  }
2962 };
2963 
2964 
2965 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2966  &ar9300_default,
2967  &ar9300_x112,
2968  &ar9300_h116,
2969  &ar9300_h112,
2970  &ar9300_x113,
2971 };
2972 
2973 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2974 {
2975 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2976  unsigned int it;
2977 
2978  for (it = 0; it < N_LOOP; it++)
2979  if (ar9300_eep_templates[it]->templateVersion == id)
2980  return ar9300_eep_templates[it];
2981  return NULL;
2982 #undef N_LOOP
2983 }
2984 
2985 
2986 static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
2987 {
2988  if (fbin == AR5416_BCHAN_UNUSED)
2989  return fbin;
2990 
2991  return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2992 }
2993 
2994 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah __unused)
2995 {
2996  return 0;
2997 }
2998 
2999 static int interpolate(int x, int xa, int xb, int ya, int yb)
3000 {
3001  int bf, factor, plus;
3002 
3003  bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
3004  factor = bf / 2;
3005  plus = bf % 2;
3006  return ya + factor + plus;
3007 }
3008 
3009 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3010  enum eeprom_param param)
3011 {
3012  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3013  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3014 
3015  switch (param) {
3016  case EEP_MAC_LSW:
3017  return eep->macAddr[0] << 8 | eep->macAddr[1];
3018  case EEP_MAC_MID:
3019  return eep->macAddr[2] << 8 | eep->macAddr[3];
3020  case EEP_MAC_MSW:
3021  return eep->macAddr[4] << 8 | eep->macAddr[5];
3022  case EEP_REG_0:
3023  return (uint16_t)(pBase->regDmn[0]);
3024  case EEP_REG_1:
3025  return (uint16_t)(pBase->regDmn[1]);
3026  case EEP_OP_CAP:
3027  return pBase->deviceCap;
3028  case EEP_OP_MODE:
3029  return pBase->opCapFlags.opFlags;
3030  case EEP_RF_SILENT:
3031  return pBase->rfSilent;
3032  case EEP_TX_MASK:
3033  return (pBase->txrxMask >> 4) & 0xf;
3034  case EEP_RX_MASK:
3035  return pBase->txrxMask & 0xf;
3036  case EEP_DRIVE_STRENGTH:
3037 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3038  return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3039  case EEP_INTERNAL_REGULATOR:
3040  /* Bit 4 is internal regulator flag */
3041  return (pBase->featureEnable & 0x10) >> 4;
3042  case EEP_SWREG:
3043  return (uint32_t)(pBase->swreg);
3044  case EEP_PAPRD:
3045  return !!(pBase->featureEnable & BIT(5));
3046  case EEP_CHAIN_MASK_REDUCE:
3047  return (pBase->miscConfiguration >> 0x3) & 0x1;
3048  case EEP_ANT_DIV_CTL1:
3049  return (uint32_t)(eep->base_ext1.ant_div_control);
3050  default:
3051  return 0;
3052  }
3053 }
3054 
3055 static int ar9300_eeprom_read_byte(struct ath_common *common, int address,
3056  u8 *buffer)
3057 {
3058  u16 val;
3059 
3060  if (!ath9k_hw_nvram_read(common, address / 2, &val))
3061  return 0;
3062 
3063  *buffer = (val >> (8 * (address % 2))) & 0xff;
3064  return 1;
3065 }
3066 
3067 static int ar9300_eeprom_read_word(struct ath_common *common, int address,
3068  u8 *buffer)
3069 {
3070  u16 val;
3071 
3072  if (!ath9k_hw_nvram_read(common, address / 2, &val))
3073  return 0;
3074 
3075  buffer[0] = val >> 8;
3076  buffer[1] = val & 0xff;
3077 
3078  return 1;
3079 }
3080 
3081 static int ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3082  int count)
3083 {
3084  struct ath_common *common = ath9k_hw_common(ah);
3085  int i;
3086 
3087  if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3088  DBG("ath9k: "
3089  "eeprom address not in range\n");
3090  return 0;
3091  }
3092 
3093  /*
3094  * Since we're reading the bytes in reverse order from a little-endian
3095  * word stream, an even address means we only use the lower half of
3096  * the 16-bit word at that address
3097  */
3098  if (address % 2 == 0) {
3099  if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3100  goto error;
3101 
3102  count--;
3103  }
3104 
3105  for (i = 0; i < count / 2; i++) {
3106  if (!ar9300_eeprom_read_word(common, address, buffer))
3107  goto error;
3108 
3109  address -= 2;
3110  buffer += 2;
3111  }
3112 
3113  if (count % 2)
3114  if (!ar9300_eeprom_read_byte(common, address, buffer))
3115  goto error;
3116 
3117  return 1;
3118 
3119 error:
3120  DBG("ath9k: "
3121  "unable to read eeprom region at offset %d\n", address);
3122  return 0;
3123 }
3124 
3125 static int ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3126 {
3127  REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3128 
3129  if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3130  AR9300_OTP_STATUS_VALID, 1000))
3131  return 0;
3132 
3133  *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3134  return 1;
3135 }
3136 
3137 static int ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3138  int count)
3139 {
3140  u32 data;
3141  int i;
3142 
3143  for (i = 0; i < count; i++) {
3144  int offset = 8 * ((address - i) % 4);
3145  if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3146  return 0;
3147 
3148  buffer[i] = (data >> offset) & 0xff;
3149  }
3150 
3151  return 1;
3152 }
3153 
3154 
3155 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3156  int *length, int *major, int *minor)
3157 {
3158  unsigned long value[4];
3159 
3160  value[0] = best[0];
3161  value[1] = best[1];
3162  value[2] = best[2];
3163  value[3] = best[3];
3164  *code = ((value[0] >> 5) & 0x0007);
3165  *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3166  *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3167  *major = (value[2] & 0x000f);
3168  *minor = (value[3] & 0x00ff);
3169 }
3170 
3171 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3172 {
3173  int it, checksum = 0;
3174 
3175  for (it = 0; it < dsize; it++) {
3176  checksum += data[it];
3177  checksum &= 0xffff;
3178  }
3179 
3180  return checksum;
3181 }
3182 
3183 static int ar9300_uncompress_block(struct ath_hw *ah __unused,
3184  u8 *mptr,
3185  int mdataSize,
3186  u8 *block,
3187  int size)
3188 {
3189  int it;
3190  int spot;
3191  int offset;
3192  int length;
3193 
3194  spot = 0;
3195 
3196  for (it = 0; it < size; it += (length+2)) {
3197  offset = block[it];
3198  offset &= 0xff;
3199  spot += offset;
3200  length = block[it+1];
3201  length &= 0xff;
3202 
3203  if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3204  DBG2("ath9k: "
3205  "Restore at %d: spot=%d offset=%d length=%d\n",
3206  it, spot, offset, length);
3207  memcpy(&mptr[spot], &block[it+2], length);
3208  spot += length;
3209  } else if (length > 0) {
3210  DBG("ath9k: "
3211  "Bad restore at %d: spot=%d offset=%d length=%d\n",
3212  it, spot, offset, length);
3213  return 0;
3214  }
3215  }
3216  return 1;
3217 }
3218 
3219 static int ar9300_compress_decision(struct ath_hw *ah,
3220  int it,
3221  int code,
3222  int reference,
3223  u8 *mptr,
3224  u8 *word, int length, int mdata_size)
3225 {
3226  const struct ar9300_eeprom *eep = NULL;
3227 
3228  switch (code) {
3229  case _CompressNone:
3230  if (length != mdata_size) {
3231  DBG("ath9k: "
3232  "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3233  mdata_size, length);
3234  return -1;
3235  }
3236  memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3237  DBG2("ath9k: "
3238  "restored eeprom %d: uncompressed, length %d\n",
3239  it, length);
3240  break;
3241  case _CompressBlock:
3242  if (reference == 0) {
3243  } else {
3244  eep = ar9003_eeprom_struct_find_by_id(reference);
3245  if (eep == NULL) {
3246  DBG("ath9k: "
3247  "can't find reference eeprom struct %d\n",
3248  reference);
3249  return -1;
3250  }
3251  memcpy(mptr, eep, mdata_size);
3252  }
3253  DBG2("ath9k: "
3254  "restore eeprom %d: block, reference %d, length %d\n",
3255  it, reference, length);
3256  ar9300_uncompress_block(ah, mptr, mdata_size,
3257  (u8 *) (word + COMP_HDR_LEN), length);
3258  break;
3259  default:
3260  DBG("ath9k: "
3261  "unknown compression code %d\n", code);
3262  return -1;
3263  }
3264  return 0;
3265 }
3266 
3267 typedef int (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3268  int count);
3269 
3270 static int ar9300_check_header(void *data)
3271 {
3272  u32 *word = data;
3273  return !(*word == 0 || *word == (unsigned int)~0);
3274 }
3275 
3276 static int ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3277  int base_addr)
3278 {
3279  u8 header[4];
3280 
3281  if (!read(ah, base_addr, header, 4))
3282  return 0;
3283 
3284  return ar9300_check_header(header);
3285 }
3286 
3287 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3288  int mdata_size)
3289 {
3290  struct ath_common *common = ath9k_hw_common(ah);
3291  u16 *data = (u16 *) mptr;
3292  int i;
3293 
3294  for (i = 0; i < mdata_size / 2; i++, data++)
3295  ath9k_hw_nvram_read(common, i, data);
3296 
3297  return 0;
3298 }
3299 /*
3300  * Read the configuration data from the eeprom.
3301  * The data can be put in any specified memory buffer.
3302  *
3303  * Returns -1 on error.
3304  * Returns address of next memory location on success.
3305  */
3306 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3307  u8 *mptr, int mdata_size)
3308 {
3309 #define MDEFAULT 15
3310 #define MSTATE 100
3311  int cptr;
3312  u8 *word;
3313  int code;
3314  int reference, length, major, minor;
3315  int osize;
3316  int it;
3317  u16 checksum, mchecksum;
3318  eeprom_read_op read;
3319 
3320  if (ath9k_hw_use_flash(ah))
3321  return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3322 
3323  word = zalloc(2048);
3324  if (!word)
3325  return -1;
3326 
3327  memcpy(mptr, &ar9300_default, mdata_size);
3328 
3329  read = ar9300_read_eeprom;
3330  if (AR_SREV_9485(ah))
3331  cptr = AR9300_BASE_ADDR_4K;
3332  else
3333  cptr = AR9300_BASE_ADDR;
3334  DBG2("ath9k: "
3335  "Trying EEPROM access at Address 0x%04x\n", cptr);
3336  if (ar9300_check_eeprom_header(ah, read, cptr))
3337  goto found;
3338 
3339  cptr = AR9300_BASE_ADDR_512;
3340  DBG2("ath9k: "
3341  "Trying EEPROM access at Address 0x%04x\n", cptr);
3342  if (ar9300_check_eeprom_header(ah, read, cptr))
3343  goto found;
3344 
3345  read = ar9300_read_otp;
3346  cptr = AR9300_BASE_ADDR;
3347  DBG2("ath9k: "
3348  "Trying OTP access at Address 0x%04x\n", cptr);
3349  if (ar9300_check_eeprom_header(ah, read, cptr))
3350  goto found;
3351 
3352  cptr = AR9300_BASE_ADDR_512;
3353  DBG2("ath9k: "
3354  "Trying OTP access at Address 0x%04x\n", cptr);
3355  if (ar9300_check_eeprom_header(ah, read, cptr))
3356  goto found;
3357 
3358  goto fail;
3359 
3360 found:
3361  DBG2("ath9k: Found valid EEPROM data\n");
3362 
3363  for (it = 0; it < MSTATE; it++) {
3364  if (!read(ah, cptr, word, COMP_HDR_LEN))
3365  goto fail;
3366 
3367  if (!ar9300_check_header(word))
3368  break;
3369 
3370  ar9300_comp_hdr_unpack(word, &code, &reference,
3371  &length, &major, &minor);
3372  DBG2("ath9k: "
3373  "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3374  cptr, code, reference, length, major, minor);
3375  if ((!AR_SREV_9485(ah) && length >= 1024) ||
3376  (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3377  DBG2("ath9k: "
3378  "Skipping bad header\n");
3379  cptr -= COMP_HDR_LEN;
3380  continue;
3381  }
3382 
3383  osize = length;
3384  read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3385  checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3386  mchecksum = word[COMP_HDR_LEN + osize] |
3387  (word[COMP_HDR_LEN + osize + 1] << 8);
3388  DBG2("ath9k: "
3389  "checksum %x %x\n", checksum, mchecksum);
3390  if (checksum == mchecksum) {
3391  ar9300_compress_decision(ah, it, code, reference, mptr,
3392  word, length, mdata_size);
3393  } else {
3394  DBG2("ath9k: "
3395  "skipping block with bad checksum\n");
3396  }
3397  cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3398  }
3399 
3400  free(word);
3401  return cptr;
3402 
3403 fail:
3404  free(word);
3405  return -1;
3406 }
3407 
3408 /*
3409  * Restore the configuration structure by reading the eeprom.
3410  * This function destroys any existing in-memory structure
3411  * content.
3412  */
3413 static int ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3414 {
3415  u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3416 
3417  if (ar9300_eeprom_restore_internal(ah, mptr,
3418  sizeof(struct ar9300_eeprom)) < 0)
3419  return 0;
3420 
3421  return 1;
3422 }
3423 
3424 /* XXX: review hardware docs */
3425 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3426 {
3427  return ah->eeprom.ar9300_eep.eepromVersion;
3428 }
3429 
3430 /* XXX: could be read from the eepromVersion, not sure yet */
3431 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah __unused)
3432 {
3433  return 0;
3434 }
3435 
3436 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, int is2ghz)
3437 {
3438  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3439 
3440  if (is2ghz)
3441  return eep->modalHeader2G.xpaBiasLvl;
3442  else
3443  return eep->modalHeader5G.xpaBiasLvl;
3444 }
3445 
3446 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, int is2ghz)
3447 {
3448  int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3449 
3450  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3451  REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3452  else {
3453  REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3454  REG_RMW_FIELD(ah, AR_CH0_THERM,
3455  AR_CH0_THERM_XPABIASLVL_MSB,
3456  bias >> 2);
3457  REG_RMW_FIELD(ah, AR_CH0_THERM,
3458  AR_CH0_THERM_XPASHORT2GND, 1);
3459  }
3460 }
3461 
3462 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, int is2ghz)
3463 {
3464  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3465  uint32_t val;
3466 
3467  if (is2ghz)
3468  val = eep->modalHeader2G.antCtrlCommon;
3469  else
3470  val = eep->modalHeader5G.antCtrlCommon;
3471  return (uint32_t)(val);
3472 }
3473 
3474 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, int is2ghz)
3475 {
3476  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3477  uint32_t val;
3478 
3479  if (is2ghz)
3480  val = eep->modalHeader2G.antCtrlCommon2;
3481  else
3482  val = eep->modalHeader5G.antCtrlCommon2;
3483  return (uint32_t)(val);
3484 }
3485 
3486 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3487  int chain,
3488  int is2ghz)
3489 {
3490  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3491  uint16_t val = 0;
3492 
3493  if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3494  if (is2ghz)
3495  val = eep->modalHeader2G.antCtrlChain[chain];
3496  else
3497  val = eep->modalHeader5G.antCtrlChain[chain];
3498  }
3499 
3500  return (uint16_t)(val);
3501 }
3502 
3503 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, int is2ghz)
3504 {
3505  int chain;
3506  u32 regval;
3507  u32 ant_div_ctl1;
3508  static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3509  AR_PHY_SWITCH_CHAIN_0,
3510  AR_PHY_SWITCH_CHAIN_1,
3511  AR_PHY_SWITCH_CHAIN_2,
3512  };
3513 
3514  u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3515 
3516  REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3517 
3518  value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3519  REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3520 
3521  for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3522  if ((ah->rxchainmask & BIT(chain)) ||
3523  (ah->txchainmask & BIT(chain))) {
3524  value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3525  is2ghz);
3526  REG_RMW_FIELD(ah, switch_chain_reg[chain],
3527  AR_SWITCH_TABLE_ALL, value);
3528  }
3529  }
3530 
3531  if (AR_SREV_9485(ah)) {
3532  value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3533  /*
3534  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3535  * are the fields present
3536  */
3537  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3538  regval &= (~AR_ANT_DIV_CTRL_ALL);
3539  regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3540  /* enable_lnadiv */
3541  regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3542  regval |= ((value >> 6) & 0x1) <<
3543  AR_PHY_9485_ANT_DIV_LNADIV_S;
3544  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3545 
3546  /*enable fast_div */
3547  regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3548  regval &= (~AR_FAST_DIV_ENABLE);
3549  regval |= ((value >> 7) & 0x1) <<
3550  AR_FAST_DIV_ENABLE_S;
3551  REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3552  ant_div_ctl1 =
3553  ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3554  /* check whether antenna diversity is enabled */
3555  if ((ant_div_ctl1 >> 0x6) == 0x3) {
3556  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3557  /*
3558  * clear bits 25-30 main_lnaconf, alt_lnaconf,
3559  * main_tb, alt_tb
3560  */
3561  regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3562  AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3563  AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3564  AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3565  /* by default use LNA1 for the main antenna */
3566  regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3567  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3568  regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3569  AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3570  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3571  }
3572 
3573 
3574  }
3575 
3576 }
3577 
3578 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3579 {
3580  int drive_strength;
3581  unsigned long reg;
3582 
3583  drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3584 
3585  if (!drive_strength)
3586  return;
3587 
3588  reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3589  reg &= ~0x00ffffc0;
3590  reg |= 0x5 << 21;
3591  reg |= 0x5 << 18;
3592  reg |= 0x5 << 15;
3593  reg |= 0x5 << 12;
3594  reg |= 0x5 << 9;
3595  reg |= 0x5 << 6;
3596  REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3597 
3598  reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3599  reg &= ~0xffffffe0;
3600  reg |= 0x5 << 29;
3601  reg |= 0x5 << 26;
3602  reg |= 0x5 << 23;
3603  reg |= 0x5 << 20;
3604  reg |= 0x5 << 17;
3605  reg |= 0x5 << 14;
3606  reg |= 0x5 << 11;
3607  reg |= 0x5 << 8;
3608  reg |= 0x5 << 5;
3609  REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3610 
3611  reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3612  reg &= ~0xff800000;
3613  reg |= 0x5 << 29;
3614  reg |= 0x5 << 26;
3615  reg |= 0x5 << 23;
3616  REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3617 }
3618 
3619 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3620  struct ath9k_channel *chan)
3621 {
3622  int f[3], t[3];
3623  u16 value;
3624  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3625 
3626  if (chain >= 0 && chain < 3) {
3627  if (IS_CHAN_2GHZ(chan))
3628  return eep->modalHeader2G.xatten1DB[chain];
3629  else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3630  t[0] = eep->base_ext2.xatten1DBLow[chain];
3631  f[0] = 5180;
3632  t[1] = eep->modalHeader5G.xatten1DB[chain];
3633  f[1] = 5500;
3634  t[2] = eep->base_ext2.xatten1DBHigh[chain];
3635  f[2] = 5785;
3636  value = ar9003_hw_power_interpolate((s32) chan->channel,
3637  f, t, 3);
3638  return value;
3639  } else
3640  return eep->modalHeader5G.xatten1DB[chain];
3641  }
3642 
3643  return 0;
3644 }
3645 
3646 
3647 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3648  struct ath9k_channel *chan)
3649 {
3650  int f[3], t[3];
3651  u16 value;
3652  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3653 
3654  if (chain >= 0 && chain < 3) {
3655  if (IS_CHAN_2GHZ(chan))
3656  return eep->modalHeader2G.xatten1Margin[chain];
3657  else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3658  t[0] = eep->base_ext2.xatten1MarginLow[chain];
3659  f[0] = 5180;
3660  t[1] = eep->modalHeader5G.xatten1Margin[chain];
3661  f[1] = 5500;
3662  t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3663  f[2] = 5785;
3664  value = ar9003_hw_power_interpolate((s32) chan->channel,
3665  f, t, 3);
3666  return value;
3667  } else
3668  return eep->modalHeader5G.xatten1Margin[chain];
3669  }
3670 
3671  return 0;
3672 }
3673 
3674 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3675 {
3676  int i;
3677  u16 value;
3678  unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3679  AR_PHY_EXT_ATTEN_CTL_1,
3680  AR_PHY_EXT_ATTEN_CTL_2,
3681  };
3682 
3683  /* Test value. if 0 then attenuation is unused. Don't load anything. */
3684  for (i = 0; i < 3; i++) {
3685  if (ah->txchainmask & BIT(i)) {
3686  value = ar9003_hw_atten_chain_get(ah, i, chan);
3687  REG_RMW_FIELD(ah, ext_atten_reg[i],
3688  AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3689 
3690  value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3691  REG_RMW_FIELD(ah, ext_atten_reg[i],
3692  AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3693  value);
3694  }
3695  }
3696 }
3697 
3698 static int is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3699 {
3700  int timeout = 100;
3701 
3702  while ((unsigned int)pmu_set != REG_READ(ah, pmu_reg)) {
3703  if (timeout-- == 0)
3704  return 0;
3705  REG_WRITE(ah, pmu_reg, pmu_set);
3706  udelay(10);
3707  }
3708 
3709  return 1;
3710 }
3711 
3712 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3713 {
3714  int internal_regulator =
3715  ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3716 
3717  if (internal_regulator) {
3718  if (AR_SREV_9485(ah)) {
3719  int reg_pmu_set;
3720 
3721  reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3722  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3723  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3724  return;
3725 
3726  reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3727  (2 << 14) | (6 << 17) | (1 << 20) |
3728  (3 << 24) | (1 << 28);
3729 
3730  REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3731  if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3732  return;
3733 
3734  reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3735  | (4 << 26);
3736  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3737  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3738  return;
3739 
3740  reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3741  | (1 << 21);
3742  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3743  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3744  return;
3745  } else {
3746  /* Internal regulator is ON. Write swreg register. */
3747  int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3748  REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3749  REG_READ(ah, AR_RTC_REG_CONTROL1) &
3750  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3751  REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3752  /* Set REG_CONTROL1.SWREG_PROGRAM */
3753  REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3754  REG_READ(ah,
3755  AR_RTC_REG_CONTROL1) |
3756  AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3757  }
3758  } else {
3759  if (AR_SREV_9485(ah)) {
3760  REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3761  while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3762  AR_PHY_PMU2_PGM))
3763  udelay(10);
3764 
3765  REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3766  while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3767  AR_PHY_PMU1_PWD))
3768  udelay(10);
3769  REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3770  while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3771  AR_PHY_PMU2_PGM))
3772  udelay(10);
3773  } else
3774  REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3775  (REG_READ(ah,
3776  AR_RTC_SLEEP_CLK) |
3777  AR_RTC_FORCE_SWREG_PRD));
3778  }
3779 
3780 }
3781 
3782 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3783 {
3784  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3785  u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3786 
3787  if (eep->baseEepHeader.featureEnable & 0x40) {
3788  tuning_caps_param &= 0x7f;
3789  REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3790  tuning_caps_param);
3791  REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3792  tuning_caps_param);
3793  }
3794 }
3795 
3796 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3797  struct ath9k_channel *chan)
3798 {
3799  ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3800  ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3801  ar9003_hw_drive_strength_apply(ah);
3802  ar9003_hw_atten_apply(ah, chan);
3803  if (!AR_SREV_9340(ah))
3804  ar9003_hw_internal_regulator_apply(ah);
3805  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3806  ar9003_hw_apply_tuning_caps(ah);
3807 }
3808 
3809 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah __unused,
3810  struct ath9k_channel *chan __unused)
3811 {
3812 }
3813 
3814 /*
3815  * Returns the interpolated y value corresponding to the specified x value
3816  * from the np ordered pairs of data (px,py).
3817  * The pairs do not have to be in any order.
3818  * If the specified x value is less than any of the px,
3819  * the returned y value is equal to the py for the lowest px.
3820  * If the specified x value is greater than any of the px,
3821  * the returned y value is equal to the py for the highest px.
3822  */
3823 static int ar9003_hw_power_interpolate(int32_t x,
3824  int32_t *px, int32_t *py, uint16_t np)
3825 {
3826  int ip = 0;
3827  int lx = 0, ly = 0, lhave = 0;
3828  int hx = 0, hy = 0, hhave = 0;
3829  int dx = 0;
3830  int y = 0;
3831 
3832  lhave = 0;
3833  hhave = 0;
3834 
3835  /* identify best lower and higher x calibration measurement */
3836  for (ip = 0; ip < np; ip++) {
3837  dx = x - px[ip];
3838 
3839  /* this measurement is higher than our desired x */
3840  if (dx <= 0) {
3841  if (!hhave || dx > (x - hx)) {
3842  /* new best higher x measurement */
3843  hx = px[ip];
3844  hy = py[ip];
3845  hhave = 1;
3846  }
3847  }
3848  /* this measurement is lower than our desired x */
3849  if (dx >= 0) {
3850  if (!lhave || dx < (x - lx)) {
3851  /* new best lower x measurement */
3852  lx = px[ip];
3853  ly = py[ip];
3854  lhave = 1;
3855  }
3856  }
3857  }
3858 
3859  /* the low x is good */
3860  if (lhave) {
3861  /* so is the high x */
3862  if (hhave) {
3863  /* they're the same, so just pick one */
3864  if (hx == lx)
3865  y = ly;
3866  else /* interpolate */
3867  y = interpolate(x, lx, hx, ly, hy);
3868  } else /* only low is good, use it */
3869  y = ly;
3870  } else if (hhave) /* only high is good, use it */
3871  y = hy;
3872  else /* nothing is good,this should never happen unless np=0, ???? */
3873  y = -(1 << 30);
3874  return y;
3875 }
3876 
3877 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3878  u16 rateIndex, u16 freq, int is2GHz)
3879 {
3880  u16 numPiers, i;
3881  s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3882  s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3883  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3884  struct cal_tgt_pow_legacy *pEepromTargetPwr;
3885  u8 *pFreqBin;
3886 
3887  if (is2GHz) {
3888  numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3889  pEepromTargetPwr = eep->calTargetPower2G;
3890  pFreqBin = eep->calTarget_freqbin_2G;
3891  } else {
3892  numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3893  pEepromTargetPwr = eep->calTargetPower5G;
3894  pFreqBin = eep->calTarget_freqbin_5G;
3895  }
3896 
3897  /*
3898  * create array of channels and targetpower from
3899  * targetpower piers stored on eeprom
3900  */
3901  for (i = 0; i < numPiers; i++) {
3902  freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3903  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3904  }
3905 
3906  /* interpolate to get target power for given frequency */
3907  return (u8) ar9003_hw_power_interpolate((s32) freq,
3908  freqArray,
3909  targetPowerArray, numPiers);
3910 }
3911 
3912 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3913  u16 rateIndex,
3914  u16 freq, int is2GHz)
3915 {
3916  u16 numPiers, i;
3917  s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3918  s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3919  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3920  struct cal_tgt_pow_ht *pEepromTargetPwr;
3921  u8 *pFreqBin;
3922 
3923  if (is2GHz) {
3924  numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3925  pEepromTargetPwr = eep->calTargetPower2GHT20;
3926  pFreqBin = eep->calTarget_freqbin_2GHT20;
3927  } else {
3928  numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3929  pEepromTargetPwr = eep->calTargetPower5GHT20;
3930  pFreqBin = eep->calTarget_freqbin_5GHT20;
3931  }
3932 
3933  /*
3934  * create array of channels and targetpower
3935  * from targetpower piers stored on eeprom
3936  */
3937  for (i = 0; i < numPiers; i++) {
3938  freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3939  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3940  }
3941 
3942  /* interpolate to get target power for given frequency */
3943  return (u8) ar9003_hw_power_interpolate((s32) freq,
3944  freqArray,
3945  targetPowerArray, numPiers);
3946 }
3947 
3948 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3949  u16 rateIndex,
3950  u16 freq, int is2GHz)
3951 {
3952  u16 numPiers, i;
3953  s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3954  s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3955  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3956  struct cal_tgt_pow_ht *pEepromTargetPwr;
3957  u8 *pFreqBin;
3958 
3959  if (is2GHz) {
3960  numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3961  pEepromTargetPwr = eep->calTargetPower2GHT40;
3962  pFreqBin = eep->calTarget_freqbin_2GHT40;
3963  } else {
3964  numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3965  pEepromTargetPwr = eep->calTargetPower5GHT40;
3966  pFreqBin = eep->calTarget_freqbin_5GHT40;
3967  }
3968 
3969  /*
3970  * create array of channels and targetpower from
3971  * targetpower piers stored on eeprom
3972  */
3973  for (i = 0; i < numPiers; i++) {
3974  freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3975  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3976  }
3977 
3978  /* interpolate to get target power for given frequency */
3979  return (u8) ar9003_hw_power_interpolate((s32) freq,
3980  freqArray,
3981  targetPowerArray, numPiers);
3982 }
3983 
3984 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3985  u16 rateIndex, u16 freq)
3986 {
3987  u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3988  s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3989  s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3990  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3991  struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3992  u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3993 
3994  /*
3995  * create array of channels and targetpower from
3996  * targetpower piers stored on eeprom
3997  */
3998  for (i = 0; i < numPiers; i++) {
3999  freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4000  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4001  }
4002 
4003  /* interpolate to get target power for given frequency */
4004  return (u8) ar9003_hw_power_interpolate((s32) freq,
4005  freqArray,
4006  targetPowerArray, numPiers);
4007 }
4008 
4009 /* Set tx power registers to array of values passed in */
4010 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4011 {
4012 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4013  /* make sure forced gain is not set */
4014  REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4015 
4016  /* Write the OFDM power per rate set */
4017 
4018  /* 6 (LSB), 9, 12, 18 (MSB) */
4019  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4020  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4021  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4022  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4023  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4024 
4025  /* 24 (LSB), 36, 48, 54 (MSB) */
4026  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4027  POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4028  POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4029  POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4030  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4031 
4032  /* Write the CCK power per rate set */
4033 
4034  /* 1L (LSB), reserved, 2L, 2S (MSB) */
4035  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4036  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4037  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4038  /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4039  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4040 
4041  /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4042  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4043  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4044  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4045  POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4046  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4047  );
4048 
4049  /* Write the power for duplicated frames - HT40 */
4050 
4051  /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4052  REG_WRITE(ah, 0xa3e0,
4053  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4054  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4055  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4056  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4057  );
4058 
4059  /* Write the HT20 power per rate set */
4060 
4061  /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4062  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4063  POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4064  POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4065  POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4066  POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4067  );
4068 
4069  /* 6 (LSB), 7, 12, 13 (MSB) */
4070  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4071  POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4072  POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4073  POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4074  POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4075  );
4076 
4077  /* 14 (LSB), 15, 20, 21 */
4078  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4079  POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4080  POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4081  POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4082  POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4083  );
4084 
4085  /* Mixed HT20 and HT40 rates */
4086 
4087  /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4088  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4089  POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4090  POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4091  POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4092  POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4093  );
4094 
4095  /*
4096  * Write the HT40 power per rate set
4097  * correct PAR difference between HT40 and HT20/LEGACY
4098  * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4099  */
4100  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4101  POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4102  POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4103  POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4104  POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4105  );
4106 
4107  /* 6 (LSB), 7, 12, 13 (MSB) */
4108  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4109  POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4110  POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4111  POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4112  POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4113  );
4114 
4115  /* 14 (LSB), 15, 20, 21 */
4116  REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4117  POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4118  POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4119  POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4120  POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4121  );
4122 
4123  return 0;
4124 #undef POW_SM
4125 }
4126 
4127 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4128  u8 *targetPowerValT2)
4129 {
4130  /* XXX: hard code for now, need to get from eeprom struct */
4131  u8 ht40PowerIncForPdadc = 0;
4132  int is2GHz = 0;
4133  unsigned int i = 0;
4134 
4135  if (freq < 4000)
4136  is2GHz = 1;
4137 
4138  targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4139  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4140  is2GHz);
4141  targetPowerValT2[ALL_TARGET_LEGACY_36] =
4142  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4143  is2GHz);
4144  targetPowerValT2[ALL_TARGET_LEGACY_48] =
4145  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4146  is2GHz);
4147  targetPowerValT2[ALL_TARGET_LEGACY_54] =
4148  ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4149  is2GHz);
4150  targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4151  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4152  freq);
4153  targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4154  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4155  targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4156  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4157  targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4158  ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4159  targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4160  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4161  is2GHz);
4162  targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4163  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4164  freq, is2GHz);
4165  targetPowerValT2[ALL_TARGET_HT20_4] =
4166  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4167  is2GHz);
4168  targetPowerValT2[ALL_TARGET_HT20_5] =
4169  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4170  is2GHz);
4171  targetPowerValT2[ALL_TARGET_HT20_6] =
4172  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4173  is2GHz);
4174  targetPowerValT2[ALL_TARGET_HT20_7] =
4175  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4176  is2GHz);
4177  targetPowerValT2[ALL_TARGET_HT20_12] =
4178  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4179  is2GHz);
4180  targetPowerValT2[ALL_TARGET_HT20_13] =
4181  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4182  is2GHz);
4183  targetPowerValT2[ALL_TARGET_HT20_14] =
4184  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4185  is2GHz);
4186  targetPowerValT2[ALL_TARGET_HT20_15] =
4187  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4188  is2GHz);
4189  targetPowerValT2[ALL_TARGET_HT20_20] =
4190  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4191  is2GHz);
4192  targetPowerValT2[ALL_TARGET_HT20_21] =
4193  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4194  is2GHz);
4195  targetPowerValT2[ALL_TARGET_HT20_22] =
4196  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4197  is2GHz);
4198  targetPowerValT2[ALL_TARGET_HT20_23] =
4199  ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4200  is2GHz);
4201  targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4202  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4203  is2GHz) + ht40PowerIncForPdadc;
4204  targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4205  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4206  freq,
4207  is2GHz) + ht40PowerIncForPdadc;
4208  targetPowerValT2[ALL_TARGET_HT40_4] =
4209  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4210  is2GHz) + ht40PowerIncForPdadc;
4211  targetPowerValT2[ALL_TARGET_HT40_5] =
4212  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4213  is2GHz) + ht40PowerIncForPdadc;
4214  targetPowerValT2[ALL_TARGET_HT40_6] =
4215  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4216  is2GHz) + ht40PowerIncForPdadc;
4217  targetPowerValT2[ALL_TARGET_HT40_7] =
4218  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4219  is2GHz) + ht40PowerIncForPdadc;
4220  targetPowerValT2[ALL_TARGET_HT40_12] =
4221  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4222  is2GHz) + ht40PowerIncForPdadc;
4223  targetPowerValT2[ALL_TARGET_HT40_13] =
4224  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4225  is2GHz) + ht40PowerIncForPdadc;
4226  targetPowerValT2[ALL_TARGET_HT40_14] =
4227  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4228  is2GHz) + ht40PowerIncForPdadc;
4229  targetPowerValT2[ALL_TARGET_HT40_15] =
4230  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4231  is2GHz) + ht40PowerIncForPdadc;
4232  targetPowerValT2[ALL_TARGET_HT40_20] =
4233  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4234  is2GHz) + ht40PowerIncForPdadc;
4235  targetPowerValT2[ALL_TARGET_HT40_21] =
4236  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4237  is2GHz) + ht40PowerIncForPdadc;
4238  targetPowerValT2[ALL_TARGET_HT40_22] =
4239  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4240  is2GHz) + ht40PowerIncForPdadc;
4241  targetPowerValT2[ALL_TARGET_HT40_23] =
4242  ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4243  is2GHz) + ht40PowerIncForPdadc;
4244 
4245  for (i = 0; i < ar9300RateSize; i++) {
4246  DBG2("ath9k: "
4247  "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4248  }
4249 }
4250 
4251 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4252  int mode,
4253  int ipier,
4254  int ichain,
4255  int *pfrequency,
4256  int *pcorrection,
4257  int *ptemperature, int *pvoltage)
4258 {
4259  u8 *pCalPier;
4260  struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4261  int is2GHz;
4262  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4263 
4264  if (ichain >= AR9300_MAX_CHAINS) {
4265  DBG("ath9k: "
4266  "Invalid chain index, must be less than %d\n",
4267  AR9300_MAX_CHAINS);
4268  return -1;
4269  }
4270 
4271  if (mode) { /* 5GHz */
4272  if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4273  DBG("ath9k: "
4274  "Invalid 5GHz cal pier index, must be less than %d\n",
4275  AR9300_NUM_5G_CAL_PIERS);
4276  return -1;
4277  }
4278  pCalPier = &(eep->calFreqPier5G[ipier]);
4279  pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4280  is2GHz = 0;
4281  } else {
4282  if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4283  DBG("ath9k: "
4284  "Invalid 2GHz cal pier index, must be less than %d\n",
4285  AR9300_NUM_2G_CAL_PIERS);
4286  return -1;
4287  }
4288 
4289  pCalPier = &(eep->calFreqPier2G[ipier]);
4290  pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4291  is2GHz = 1;
4292  }
4293 
4294  *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4295  *pcorrection = pCalPierStruct->refPower;
4296  *ptemperature = pCalPierStruct->tempMeas;
4297  *pvoltage = pCalPierStruct->voltMeas;
4298 
4299  return 0;
4300 }
4301 
4302 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4303  int frequency,
4304  int *correction,
4305  int *voltage __unused, int *temperature)
4306 {
4307  int tempSlope = 0;
4308  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4309  int f[3], t[3];
4310 
4311  REG_RMW(ah, AR_PHY_TPC_11_B0,
4312  (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4313  AR_PHY_TPC_OLPC_GAIN_DELTA);
4314  if (ah->caps.tx_chainmask & BIT(1))
4315  REG_RMW(ah, AR_PHY_TPC_11_B1,
4316  (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4317  AR_PHY_TPC_OLPC_GAIN_DELTA);
4318  if (ah->caps.tx_chainmask & BIT(2))
4319  REG_RMW(ah, AR_PHY_TPC_11_B2,
4320  (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4321  AR_PHY_TPC_OLPC_GAIN_DELTA);
4322 
4323  /* enable open loop power control on chip */
4324  REG_RMW(ah, AR_PHY_TPC_6_B0,
4325  (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4326  AR_PHY_TPC_6_ERROR_EST_MODE);
4327  if (ah->caps.tx_chainmask & BIT(1))
4328  REG_RMW(ah, AR_PHY_TPC_6_B1,
4329  (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4330  AR_PHY_TPC_6_ERROR_EST_MODE);
4331  if (ah->caps.tx_chainmask & BIT(2))
4332  REG_RMW(ah, AR_PHY_TPC_6_B2,
4333  (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4334  AR_PHY_TPC_6_ERROR_EST_MODE);
4335 
4336  /*
4337  * enable temperature compensation
4338  * Need to use register names
4339  */
4340  if (frequency < 4000)
4341  tempSlope = eep->modalHeader2G.tempSlope;
4342  else if (eep->base_ext2.tempSlopeLow != 0) {
4343  t[0] = eep->base_ext2.tempSlopeLow;
4344  f[0] = 5180;
4345  t[1] = eep->modalHeader5G.tempSlope;
4346  f[1] = 5500;
4347  t[2] = eep->base_ext2.tempSlopeHigh;
4348  f[2] = 5785;
4349  tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4350  f, t, 3);
4351  } else
4352  tempSlope = eep->modalHeader5G.tempSlope;
4353 
4354  REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4355  REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4356  temperature[0]);
4357 
4358  return 0;
4359 }
4360 
4361 /* Apply the recorded correction values. */
4362 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4363 {
4364  int ichain, ipier, npier;
4365  int mode;
4366  int lfrequency[AR9300_MAX_CHAINS],
4367  lcorrection[AR9300_MAX_CHAINS],
4368  ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4369  int hfrequency[AR9300_MAX_CHAINS],
4370  hcorrection[AR9300_MAX_CHAINS],
4371  htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4372  int fdiff;
4373  int correction[AR9300_MAX_CHAINS],
4374  voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4375  int pfrequency, pcorrection, ptemperature, pvoltage;
4376 
4377  mode = (frequency >= 4000);
4378  if (mode)
4379  npier = AR9300_NUM_5G_CAL_PIERS;
4380  else
4381  npier = AR9300_NUM_2G_CAL_PIERS;
4382 
4383  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4384  lfrequency[ichain] = 0;
4385  hfrequency[ichain] = 100000;
4386  }
4387  /* identify best lower and higher frequency calibration measurement */
4388  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4389  for (ipier = 0; ipier < npier; ipier++) {
4390  if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4391  &pfrequency, &pcorrection,
4392  &ptemperature, &pvoltage)) {
4393  fdiff = frequency - pfrequency;
4394 
4395  /*
4396  * this measurement is higher than
4397  * our desired frequency
4398  */
4399  if (fdiff <= 0) {
4400  if (hfrequency[ichain] <= 0 ||
4401  hfrequency[ichain] >= 100000 ||
4402  fdiff >
4403  (frequency - hfrequency[ichain])) {
4404  /*
4405  * new best higher
4406  * frequency measurement
4407  */
4408  hfrequency[ichain] = pfrequency;
4409  hcorrection[ichain] =
4410  pcorrection;
4411  htemperature[ichain] =
4412  ptemperature;
4413  hvoltage[ichain] = pvoltage;
4414  }
4415  }
4416  if (fdiff >= 0) {
4417  if (lfrequency[ichain] <= 0
4418  || fdiff <
4419  (frequency - lfrequency[ichain])) {
4420  /*
4421  * new best lower
4422  * frequency measurement
4423  */
4424  lfrequency[ichain] = pfrequency;
4425  lcorrection[ichain] =
4426  pcorrection;
4427  ltemperature[ichain] =
4428  ptemperature;
4429  lvoltage[ichain] = pvoltage;
4430  }
4431  }
4432  }
4433  }
4434  }
4435 
4436  /* interpolate */
4437  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4438  DBG2("ath9k: "
4439  "ch=%d f=%d low=%d %d h=%d %d\n",
4440  ichain, frequency, lfrequency[ichain],
4441  lcorrection[ichain], hfrequency[ichain],
4442  hcorrection[ichain]);
4443  /* they're the same, so just pick one */
4444  if (hfrequency[ichain] == lfrequency[ichain]) {
4445  correction[ichain] = lcorrection[ichain];
4446  voltage[ichain] = lvoltage[ichain];
4447  temperature[ichain] = ltemperature[ichain];
4448  }
4449  /* the low frequency is good */
4450  else if (frequency - lfrequency[ichain] < 1000) {
4451  /* so is the high frequency, interpolate */
4452  if (hfrequency[ichain] - frequency < 1000) {
4453 
4454  correction[ichain] = interpolate(frequency,
4455  lfrequency[ichain],
4456  hfrequency[ichain],
4457  lcorrection[ichain],
4458  hcorrection[ichain]);
4459 
4460  temperature[ichain] = interpolate(frequency,
4461  lfrequency[ichain],
4462  hfrequency[ichain],
4463  ltemperature[ichain],
4464  htemperature[ichain]);
4465 
4466  voltage[ichain] = interpolate(frequency,
4467  lfrequency[ichain],
4468  hfrequency[ichain],
4469  lvoltage[ichain],
4470  hvoltage[ichain]);
4471  }
4472  /* only low is good, use it */
4473  else {
4474  correction[ichain] = lcorrection[ichain];
4475  temperature[ichain] = ltemperature[ichain];
4476  voltage[ichain] = lvoltage[ichain];
4477  }
4478  }
4479  /* only high is good, use it */
4480  else if (hfrequency[ichain] - frequency < 1000) {
4481  correction[ichain] = hcorrection[ichain];
4482  temperature[ichain] = htemperature[ichain];
4483  voltage[ichain] = hvoltage[ichain];
4484  } else { /* nothing is good, presume 0???? */
4485  correction[ichain] = 0;
4486  temperature[ichain] = 0;
4487  voltage[ichain] = 0;
4488  }
4489  }
4490 
4491  ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4492  temperature);
4493 
4494  DBG2("ath9k: "
4495  "for frequency=%d, calibration correction = %d %d %d\n",
4496  frequency, correction[0], correction[1], correction[2]);
4497 
4498  return 0;
4499 }
4500 
4501 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4502  int idx,
4503  int edge,
4504  int is2GHz)
4505 {
4506  struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4507  struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4508 
4509  if (is2GHz)
4510  return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4511  else
4512  return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4513 }
4514 
4515 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4516  int idx,
4517  unsigned int edge,
4518  u16 freq,
4519  int is2GHz)
4520 {
4521  struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4522  struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4523 
4524  u8 *ctl_freqbin = is2GHz ?
4525  &eep->ctl_freqbin_2G[idx][0] :
4526  &eep->ctl_freqbin_5G[idx][0];
4527 
4528  if (is2GHz) {
4529  if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4530  CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4531  return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4532  } else {
4533  if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4534  CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4535  return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4536  }
4537 
4538  return MAX_RATE_POWER;
4539 }
4540 
4541 /*
4542  * Find the maximum conformance test limit for the given channel and CTL info
4543  */
4544 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4545  u16 freq, int idx, int is2GHz)
4546 {
4547  u16 twiceMaxEdgePower = MAX_RATE_POWER;
4548  u8 *ctl_freqbin = is2GHz ?
4549  &eep->ctl_freqbin_2G[idx][0] :
4550  &eep->ctl_freqbin_5G[idx][0];
4551  u16 num_edges = is2GHz ?
4552  AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4553  unsigned int edge;
4554 
4555  /* Get the edge power */
4556  for (edge = 0;
4557  (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4558  edge++) {
4559  /*
4560  * If there's an exact channel match or an inband flag set
4561  * on the lower channel use the given rdEdgePower
4562  */
4563  if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4564  twiceMaxEdgePower =
4565  ar9003_hw_get_direct_edge_power(eep, idx,
4566  edge, is2GHz);
4567  break;
4568  } else if ((edge > 0) &&
4569  (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4570  is2GHz))) {
4571  twiceMaxEdgePower =
4572  ar9003_hw_get_indirect_edge_power(eep, idx,
4573  edge, freq,
4574  is2GHz);
4575  /*
4576  * Leave loop - no more affecting edges possible in
4577  * this monotonic increasing list
4578  */
4579  break;
4580  }
4581  }
4582  return twiceMaxEdgePower;
4583 }
4584 
4585 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4586  struct ath9k_channel *chan,
4587  u8 *pPwrArray, u16 cfgCtl,
4588  u8 twiceAntennaReduction,
4589  u8 twiceMaxRegulatoryPower,
4590  u16 powerLimit)
4591 {
4592  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4593  struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4594  u16 twiceMaxEdgePower = MAX_RATE_POWER;
4595  static const u16 tpScaleReductionTable[5] = {
4596  0, 3, 6, 9, MAX_RATE_POWER
4597  };
4598  int i;
4599  int16_t twiceLargestAntenna;
4600  u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4601  static const u16 ctlModesFor11a[] = {
4602  CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4603  };
4604  static const u16 ctlModesFor11g[] = {
4605  CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4606  CTL_11G_EXT, CTL_2GHT40
4607  };
4608  u16 numCtlModes;
4609  const u16 *pCtlMode;
4610  u16 ctlMode, freq;
4611  struct chan_centers centers;
4612  u8 *ctlIndex;
4613  u8 ctlNum;
4614  u16 twiceMinEdgePower;
4615  int is2ghz = IS_CHAN_2GHZ(chan);
4616 
4617  ath9k_hw_get_channel_centers(ah, chan, &centers);
4618 
4619  /* Compute TxPower reduction due to Antenna Gain */
4620  if (is2ghz)
4621  twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4622  else
4623  twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4624 
4625  twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4626  twiceLargestAntenna, 0);
4627 
4628  /*
4629  * scaledPower is the minimum of the user input power level
4630  * and the regulatory allowed power level
4631  */
4632  maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4633 
4634  if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4635  maxRegAllowedPower -=
4636  (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4637  }
4638 
4639  scaledPower = min(powerLimit, maxRegAllowedPower);
4640 
4641  /*
4642  * Reduce scaled Power by number of chains active to get
4643  * to per chain tx power level
4644  */
4645  switch (ar5416_get_ntxchains(ah->txchainmask)) {
4646  case 1:
4647  break;
4648  case 2:
4649  if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4650  scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4651  else
4652  scaledPower = 0;
4653  break;
4654  case 3:
4655  if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4656  scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4657  else
4658  scaledPower = 0;
4659  break;
4660  }
4661 
4662  scaledPower = max((u16)0, scaledPower);
4663 
4664  /*
4665  * Get target powers from EEPROM - our baseline for TX Power
4666  */
4667  if (is2ghz) {
4668  /* Setup for CTL modes */
4669  /* CTL_11B, CTL_11G, CTL_2GHT20 */
4670  numCtlModes =
4671  ARRAY_SIZE(ctlModesFor11g) -
4672  SUB_NUM_CTL_MODES_AT_2G_40;
4673  pCtlMode = ctlModesFor11g;
4674  if (IS_CHAN_HT40(chan))
4675  /* All 2G CTL's */
4676  numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4677  } else {
4678  /* Setup for CTL modes */
4679  /* CTL_11A, CTL_5GHT20 */
4680  numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4681  SUB_NUM_CTL_MODES_AT_5G_40;
4682  pCtlMode = ctlModesFor11a;
4683  if (IS_CHAN_HT40(chan))
4684  /* All 5G CTL's */
4685  numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4686  }
4687 
4688  /*
4689  * For MIMO, need to apply regulatory caps individually across
4690  * dynamically running modes: CCK, OFDM, HT20, HT40
4691  *
4692  * The outer loop walks through each possible applicable runtime mode.
4693  * The inner loop walks through each ctlIndex entry in EEPROM.
4694  * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4695  */
4696  for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4697  int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4698  (pCtlMode[ctlMode] == CTL_2GHT40);
4699  if (isHt40CtlMode)
4700  freq = centers.synth_center;
4701  else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4702  freq = centers.ext_center;
4703  else
4704  freq = centers.ctl_center;
4705 
4706  DBG2("ath9k: "
4707  "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4708  ctlMode, numCtlModes, isHt40CtlMode,
4709  (pCtlMode[ctlMode] & EXT_ADDITIVE));
4710 
4711  /* walk through each CTL index stored in EEPROM */
4712  if (is2ghz) {
4713  ctlIndex = pEepData->ctlIndex_2G;
4714  ctlNum = AR9300_NUM_CTLS_2G;
4715  } else {
4716  ctlIndex = pEepData->ctlIndex_5G;
4717  ctlNum = AR9300_NUM_CTLS_5G;
4718  }
4719 
4720  for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4721  DBG2("ath9k: "
4722  "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4723  i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4724  chan->channel);
4725 
4726  /*
4727  * compare test group from regulatory
4728  * channel list with test mode from pCtlMode
4729  * list
4730  */
4731  if ((((cfgCtl & ~CTL_MODE_M) |
4732  (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4733  ctlIndex[i]) ||
4734  (((cfgCtl & ~CTL_MODE_M) |
4735  (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4736  ((ctlIndex[i] & CTL_MODE_M) |
4737  SD_NO_CTL))) {
4738  twiceMinEdgePower =
4739  ar9003_hw_get_max_edge_power(pEepData,
4740  freq, i,
4741  is2ghz);
4742 
4743  if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4744  /*
4745  * Find the minimum of all CTL
4746  * edge powers that apply to
4747  * this channel
4748  */
4749  twiceMaxEdgePower =
4750  min(twiceMaxEdgePower,
4751  twiceMinEdgePower);
4752  else {
4753  /* specific */
4754  twiceMaxEdgePower =
4755  twiceMinEdgePower;
4756  break;
4757  }
4758  }
4759  }
4760 
4761  minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4762 
4763  DBG2("ath9k: "
4764  "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4765  ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4766  scaledPower, minCtlPower);
4767 
4768  /* Apply ctl mode to correct target power set */
4769  switch (pCtlMode[ctlMode]) {
4770  case CTL_11B:
4771  for (i = ALL_TARGET_LEGACY_1L_5L;
4772  i <= ALL_TARGET_LEGACY_11S; i++)
4773  pPwrArray[i] =
4774  (u8)min((u16)pPwrArray[i],
4775  minCtlPower);
4776  break;
4777  case CTL_11A:
4778  case CTL_11G:
4779  for (i = ALL_TARGET_LEGACY_6_24;
4780  i <= ALL_TARGET_LEGACY_54; i++)
4781  pPwrArray[i] =
4782  (u8)min((u16)pPwrArray[i],
4783  minCtlPower);
4784  break;
4785  case CTL_5GHT20:
4786  case CTL_2GHT20:
4787  for (i = ALL_TARGET_HT20_0_8_16;
4788  i <= ALL_TARGET_HT20_21; i++)
4789  pPwrArray[i] =
4790  (u8)min((u16)pPwrArray[i],
4791  minCtlPower);
4792  pPwrArray[ALL_TARGET_HT20_22] =
4793  (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4794  minCtlPower);
4795  pPwrArray[ALL_TARGET_HT20_23] =
4796  (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4797  minCtlPower);
4798  break;
4799  case CTL_5GHT40:
4800  case CTL_2GHT40:
4801  for (i = ALL_TARGET_HT40_0_8_16;
4802  i <= ALL_TARGET_HT40_23; i++)
4803  pPwrArray[i] =
4804  (u8)min((u16)pPwrArray[i],
4805  minCtlPower);
4806  break;
4807  default:
4808  break;
4809  }
4810  } /* end ctl mode checking */
4811 }
4812 
4813 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4814 {
4815  u8 mod_idx = mcs_idx % 8;
4816 
4817  if (mod_idx <= 3)
4818  return mod_idx ? (base_pwridx + 1) : base_pwridx;
4819  else
4820  return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4821 }
4822 
4823 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4824  struct ath9k_channel *chan, u16 cfgCtl,
4825  u8 twiceAntennaReduction,
4826  u8 twiceMaxRegulatoryPower,
4827  u8 powerLimit, int test)
4828 {
4829  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4830  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4831  struct ar9300_modal_eep_header *modal_hdr;
4832  u8 targetPowerValT2[ar9300RateSize];
4833  u8 target_power_val_t2_eep[ar9300RateSize];
4834  unsigned int i = 0, paprd_scale_factor = 0;
4835  u8 pwr_idx, min_pwridx = 0;
4836 
4837  ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4838 
4839  if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4840  if (IS_CHAN_2GHZ(chan))
4841  modal_hdr = &eep->modalHeader2G;
4842  else
4843  modal_hdr = &eep->modalHeader5G;
4844 
4845  ah->paprd_ratemask =
4846  (uint32_t)(modal_hdr->papdRateMaskHt20) &
4847  AR9300_PAPRD_RATE_MASK;
4848 
4849  ah->paprd_ratemask_ht40 =
4850  (uint32_t)(modal_hdr->papdRateMaskHt40) &
4851  AR9300_PAPRD_RATE_MASK;
4852 
4853  paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4854  min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4855  ALL_TARGET_HT20_0_8_16;
4856 
4857  if (!ah->paprd_table_write_done) {
4858  memcpy(target_power_val_t2_eep, targetPowerValT2,
4859  sizeof(targetPowerValT2));
4860  for (i = 0; i < 24; i++) {
4861  pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4862  if (ah->paprd_ratemask & (1 << i)) {
4863  if (targetPowerValT2[pwr_idx] &&
4864  targetPowerValT2[pwr_idx] ==
4865  target_power_val_t2_eep[pwr_idx])
4866  targetPowerValT2[pwr_idx] -=
4867  paprd_scale_factor;
4868  }
4869  }
4870  }
4871  memcpy(target_power_val_t2_eep, targetPowerValT2,
4872  sizeof(targetPowerValT2));
4873  }
4874 
4875  ar9003_hw_set_power_per_rate_table(ah, chan,
4876  targetPowerValT2, cfgCtl,
4877  twiceAntennaReduction,
4878  twiceMaxRegulatoryPower,
4879  powerLimit);
4880 
4881  if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4882  for (i = 0; i < ar9300RateSize; i++) {
4883  if ((ah->paprd_ratemask & (1 << i)) &&
4884  ((unsigned int)abs(targetPowerValT2[i] -
4885  target_power_val_t2_eep[i]) >
4886  paprd_scale_factor)) {
4887  ah->paprd_ratemask &= ~(1 << i);
4888  DBG2("ath9k: "
4889  "paprd disabled for mcs %d\n", i);
4890  }
4891  }
4892  }
4893 
4894  regulatory->max_power_level = 0;
4895  for (i = 0; i < ar9300RateSize; i++) {
4896  if (targetPowerValT2[i] > regulatory->max_power_level)
4897  regulatory->max_power_level = targetPowerValT2[i];
4898  }
4899 
4900  if (test)
4901  return;
4902 
4903  for (i = 0; i < ar9300RateSize; i++) {
4904  DBG2("ath9k: "
4905  "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4906  }
4907 
4908  /*
4909  * This is the TX power we send back to driver core,
4910  * and it can use to pass to userspace to display our
4911  * currently configured TX power setting.
4912  *
4913  * Since power is rate dependent, use one of the indices
4914  * from the AR9300_Rates enum to select an entry from
4915  * targetPowerValT2[] to report. Currently returns the
4916  * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4917  * as CCK power is less interesting (?).
4918  */
4919  i = ALL_TARGET_LEGACY_6_24; /* legacy */
4920  if (IS_CHAN_HT40(chan))
4921  i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4922  else if (IS_CHAN_HT20(chan))
4923  i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4924 
4925  ah->txpower_limit = targetPowerValT2[i];
4926  regulatory->max_power_level = targetPowerValT2[i];
4927 
4928  /* Write target power array to registers */
4929  ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4930  ar9003_hw_calibration_apply(ah, chan->channel);
4931 
4932  if (IS_CHAN_2GHZ(chan)) {
4933  if (IS_CHAN_HT40(chan))
4934  i = ALL_TARGET_HT40_0_8_16;
4935  else
4936  i = ALL_TARGET_HT20_0_8_16;
4937  } else {
4938  if (IS_CHAN_HT40(chan))
4939  i = ALL_TARGET_HT40_7;
4940  else
4941  i = ALL_TARGET_HT20_7;
4942  }
4943  ah->paprd_target_power = targetPowerValT2[i];
4944 }
4945 
4946 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah __unused,
4947  u16 i __unused, int is2GHz __unused)
4948 {
4949  return AR_NO_SPUR;
4950 }
4951 
4952 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4953 {
4954  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4955 
4956  return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4957 }
4958 
4959 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4960 {
4961  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4962 
4963  return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4964 }
4965 
4966 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
4967 {
4968  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4969 
4970  if (is_2ghz)
4971  return eep->modalHeader2G.spurChans;
4972  else
4973  return eep->modalHeader5G.spurChans;
4974 }
4975 
4976 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
4977  struct ath9k_channel *chan)
4978 {
4979  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4980 
4981  if (IS_CHAN_2GHZ(chan))
4982  return MS((uint32_t)(eep->modalHeader2G.papdRateMaskHt20),
4983  AR9300_PAPRD_SCALE_1);
4984  else {
4985  if (chan->channel >= 5700)
4986  return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt20),
4987  AR9300_PAPRD_SCALE_1);
4988  else if (chan->channel >= 5400)
4989  return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
4990  AR9300_PAPRD_SCALE_2);
4991  else
4992  return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
4993  AR9300_PAPRD_SCALE_1);
4994  }
4995 }
4996 
4997 const struct eeprom_ops eep_ar9300_ops = {
4998  .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4999  .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5000  .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5001  .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5002  .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5003  .set_board_values = ath9k_hw_ar9300_set_board_values,
5004  .set_addac = ath9k_hw_ar9300_set_addac,
5005  .set_txpower = ath9k_hw_ar9300_set_txpower,
5006  .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5007 };
AR9300_MAX_CHAINS
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:50
u16
uint16_t u16
Definition: stdint.h:22
ar9300_eeprom::ctlIndex_2G
u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]
Definition: ar9003_eeprom.h:312
ar9300_modal_eep_header::spurChans
u8 spurChans[AR_EEPROM_MODAL_SPURS]
Definition: ar9003_eeprom.h:220
ar9003_hw_set_target_power_eeprom
static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2)
Definition: ath9k_ar9003_eeprom.c:4127
AR9300_NUM_5G_CAL_PIERS
#define AR9300_NUM_5G_CAL_PIERS
Definition: ar9003_eeprom.h:33
length
u16 length
Definition: sky2.h:9
ar9300_eeprom::calTarget_freqbin_2GHT20
u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:302
read
struct option_descriptor read[1]
Definition: nvo_cmd.c:116
ar9003_phy.h
ALL_TARGET_HT20_12
Definition: ar9003_eeprom.h:130
LEGACY_TARGET_RATE_36
Definition: ar9003_eeprom.h:103
ath9k_channel::channel
u16 channel
Definition: hw.h:350
REDUCE_SCALED_POWER_BY_THREE_CHAIN
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN
Definition: ath9k_ar9003_eeprom.c:60
io.h
iPXE I/O API
AR9300_BASE_ADDR
#define AR9300_BASE_ADDR
Definition: ar9003_eeprom.h:73
ALL_TARGET_LEGACY_5S
Definition: ar9003_eeprom.h:121
uint16_t
unsigned short uint16_t
Definition: stdint.h:11
AR_PHY_9485_ANT_DIV_MAIN_LNACONF
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF
Definition: ar9003_phy.h:282
ar9300_eeprom::calTarget_freqbin_2GHT40
u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]
Definition: ar9003_eeprom.h:303
ath_hw
Definition: hw.h:657
chan_centers::synth_center
u16 synth_center
Definition: hw.h:423
cal_tgt_pow_ht
Definition: ar9003_eeprom.h:261
checksum
uint8_t checksum
Checksum.
Definition: pnpbios.c:37
ar9300_default
static const struct ar9300_eeprom ar9300_default
Definition: ath9k_ar9003_eeprom.c:76
AR_CH0_THERM_XPASHORT2GND
#define AR_CH0_THERM_XPASHORT2GND
Definition: ath9k_ar9003_eeprom.c:39
ALL_TARGET_HT40_4
Definition: ar9003_eeprom.h:140
ar9300_eeprom::eepromVersion
u8 eepromVersion
Definition: ar9003_eeprom.h:288
AR_SWITCH_TABLE_COM2_ALL
#define AR_SWITCH_TABLE_COM2_ALL
Definition: ath9k_ar9003_eeprom.c:45
AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
Definition: ar9003_phy.h:283
max
#define max(x, y)
Definition: ath.h:41
ar9300_eeprom::calFreqPier2G
u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]
Definition: ar9003_eeprom.h:297
reg
static unsigned int unsigned int reg
Definition: myson.h:162
ar5416_get_ntxchains
#define ar5416_get_ntxchains(_txchainmask)
Definition: eeprom.h:707
CTL_2GHT40
#define CTL_2GHT40
Definition: eeprom.h:76
AR_PHY_PMU2
#define AR_PHY_PMU2
Definition: ar9003_phy.h:642
ar9300_h116
static const struct ar9300_eeprom ar9300_h116
Definition: ath9k_ar9003_eeprom.c:2387
AR_PHY_POWER_TX_RATE
#define AR_PHY_POWER_TX_RATE(_d)
Definition: ar9003_phy.h:513
ar9300_eeprom::calTarget_freqbin_2G
u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:301
AR_PHY_TPC_6_B1
#define AR_PHY_TPC_6_B1
Definition: ar9003_phy.h:849
val
void __asmcall int val
Definition: setjmp.h:12
interpolate
static int interpolate(int x, int xa, int xb, int ya, int yb)
Definition: ath9k_ar9003_eeprom.c:2999
AR9300_EEPROM_SIZE
#define AR9300_EEPROM_SIZE
Definition: ar9003_eeprom.h:70
ALL_TARGET_HT40_23
Definition: ar9003_eeprom.h:151
ath9k_hw_ar9300_get_spur_channel
static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah __unused, u16 i __unused, int is2GHz __unused)
Definition: ath9k_ar9003_eeprom.c:4946
s32
int32_t s32
Definition: stdint.h:23
ath9k_hw_ar9300_fill_eeprom
static int ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:3413
AR_PHY_TPC_OLPC_GAIN_DELTA
#define AR_PHY_TPC_OLPC_GAIN_DELTA
Definition: ar9003_phy.h:416
ar9003_eeprom_struct_find_by_id
static const struct ar9300_eeprom * ar9003_eeprom_struct_find_by_id(int id)
Definition: ath9k_ar9003_eeprom.c:2973
AR_RTC_REG_CONTROL1
#define AR_RTC_REG_CONTROL1
Definition: reg.h:1174
AR_PHY_65NM_CH0_BIAS2
#define AR_PHY_65NM_CH0_BIAS2
Definition: ar9003_phy.h:609
ar9003_hw_get_rx_gain_idx
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:4959
EXT_ADDITIVE
#define EXT_ADDITIVE
Definition: ath9k_ar9003_eeprom.c:55
ar9300_h112
static const struct ar9300_eeprom ar9300_h112
Definition: ath9k_ar9003_eeprom.c:1232
AR_CH0_TOP_XPABIASLVL
#define AR_CH0_TOP_XPABIASLVL
Definition: ath9k_ar9003_eeprom.c:33
AR9300_NUM_2G_CCK_TARGET_POWERS
#define AR9300_NUM_2G_CCK_TARGET_POWERS
Definition: ar9003_eeprom.h:37
IS_CHAN_2GHZ
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:362
ath9k_hw_ar9300_set_addac
static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah __unused, struct ath9k_channel *chan __unused)
Definition: ath9k_ar9003_eeprom.c:3809
ar9300_x113
static const struct ar9300_eeprom ar9300_x113
Definition: ath9k_ar9003_eeprom.c:654
CTL_EDGE_FLAGS
#define CTL_EDGE_FLAGS(_ctl)
Definition: eeprom.h:215
MS
#define MS(_v, _f)
Definition: hw.h:103
ALL_TARGET_HT40_0_8_16
Definition: ar9003_eeprom.h:138
mode
uint16_t mode
Acceleration mode.
Definition: ena.h:26
ar9003_hw_cal_pier_get
static int ar9003_hw_cal_pier_get(struct ath_hw *ah, int mode, int ipier, int ichain, int *pfrequency, int *pcorrection, int *ptemperature, int *pvoltage)
Definition: ath9k_ar9003_eeprom.c:4251
address
uint64_t address
Base address.
Definition: ena.h:24
ar9003_hw_internal_regulator_apply
static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:3712
ar9003_hw_power_control_override
static int ar9003_hw_power_control_override(struct ath_hw *ah, int frequency, int *correction, int *voltage __unused, int *temperature)
Definition: ath9k_ar9003_eeprom.c:4302
error
struct arbelprm_completion_with_error error
Definition: arbel.h:12
ALL_TARGET_HT20_20
Definition: ar9003_eeprom.h:134
chan_centers::ext_center
u16 ext_center
Definition: hw.h:425
cal_tgt_pow_ht::tPow2x
u8 tPow2x[14]
Definition: ar9003_eeprom.h:262
size
uint16_t size
Buffer size.
Definition: dwmac.h:14
AR9300_PWR_TABLE_OFFSET
#define AR9300_PWR_TABLE_OFFSET
Definition: ar9003_eeprom.h:67
ar9300_base_eep_hdr::miscConfiguration
u8 miscConfiguration
Definition: ar9003_eeprom.h:196
SUB_NUM_CTL_MODES_AT_5G_40
#define SUB_NUM_CTL_MODES_AT_5G_40
Definition: ath9k_ar9003_eeprom.c:65
ALL_TARGET_LEGACY_6_24
Definition: ar9003_eeprom.h:116
tempSlope
int8_t tempSlope
Definition: ar9003_eeprom.h:35
ar9003_hw_calibration_apply
static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
Definition: ath9k_ar9003_eeprom.c:4362
ALL_TARGET_HT40_22
Definition: ar9003_eeprom.h:150
HT_TARGET_RATE_4
Definition: ar9003_eeprom.h:87
min
#define min(x, y)
Definition: ath.h:36
ar9300_BaseExtension_2::xatten1DBLow
u8 xatten1DBLow[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:281
ar9003_hw_eeprom_get_cck_tgt_pwr
static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq)
Definition: ath9k_ar9003_eeprom.c:3984
REG_RMW
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:87
AR9300_NUM_5G_20_TARGET_POWERS
#define AR9300_NUM_5G_20_TARGET_POWERS
Definition: ar9003_eeprom.h:35
CTL
#define CTL(_tpower, _flag)
Definition: ath9k_ar9003_eeprom.c:68
x
static unsigned int x
Definition: pixbuf.h:63
ALL_TARGET_HT40_12
Definition: ar9003_eeprom.h:144
ar9300_BaseExtension_2::xatten1MarginLow
u8 xatten1MarginLow[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:282
AR_PHY_TPC_11_B0
#define AR_PHY_TPC_11_B0
Definition: ar9003_phy.h:528
AR_SREV_9485
#define AR_SREV_9485(_ah)
Definition: reg.h:868
AR_SWITCH_TABLE_ALL
#define AR_SWITCH_TABLE_ALL
Definition: ath9k_ar9003_eeprom.c:48
HT_TARGET_RATE_6
Definition: ar9003_eeprom.h:89
ar9300_base_eep_hdr::opCapFlags
struct eepFlags opCapFlags
Definition: ar9003_eeprom.h:176
AR_PHY_SWITCH_CHAIN_1
#define AR_PHY_SWITCH_CHAIN_1
Definition: ar9003_phy.h:842
ar9300_compress_decision
static int ar9300_compress_decision(struct ath_hw *ah, int it, int code, int reference, u8 *mptr, u8 *word, int length, int mdata_size)
Definition: ath9k_ar9003_eeprom.c:3219
ar9300_eeprom_restore_internal
static int ar9300_eeprom_restore_internal(struct ath_hw *ah, u8 *mptr, int mdata_size)
Definition: ath9k_ar9003_eeprom.c:3306
ar9300_eeprom::calTargetPowerCck
struct cal_tgt_pow_legacy calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]
Definition: ar9003_eeprom.h:304
AR_PHY_TX_FORCED_GAIN
#define AR_PHY_TX_FORCED_GAIN
Definition: ar9003_phy.h:550
ar9003_get_paprd_scale_factor
unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_eeprom.c:4976
buffer
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
AR_PHY_TPC_6_ERROR_EST_MODE
#define AR_PHY_TPC_6_ERROR_EST_MODE
Definition: ar9003_phy.h:419
LEGACY_TARGET_RATE_11S
Definition: ar9003_eeprom.h:112
AR_RTC_REG_CONTROL0
#define AR_RTC_REG_CONTROL0
Definition: reg.h:1171
ar9003_eeprom.h
AR9300_OTP_STATUS_VALID
#define AR9300_OTP_STATUS_VALID
Definition: ar9003_eeprom.h:79
ar9300_eeprom_read_byte
static int ar9300_eeprom_read_byte(struct ath_common *common, int address, u8 *buffer)
Definition: ath9k_ar9003_eeprom.c:3055
ar9300_cal_data_per_freq_op_loop::voltMeas
u8 voltMeas
Definition: ar9003_eeprom.h:246
ar9300_eeprom::ctlIndex_5G
u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]
Definition: ar9003_eeprom.h:329
AR9300_NUM_BAND_EDGES_5G
#define AR9300_NUM_BAND_EDGES_5G
Definition: ar9003_eeprom.h:43
ALL_TARGET_HT40_6
Definition: ar9003_eeprom.h:142
AR_PHY_TPC_11_B1
#define AR_PHY_TPC_11_B1
Definition: ar9003_phy.h:850
ar9003_hw_tx_power_regwrite
static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 *pPwrArray)
Definition: ath9k_ar9003_eeprom.c:4010
ALL_TARGET_LEGACY_54
Definition: ar9003_eeprom.h:119
AR9300_PAPRD_SCALE_1
#define AR9300_PAPRD_SCALE_1
Definition: ar9003_eeprom.h:55
HT_TARGET_RATE_1_3_9_11_17_19
Definition: ar9003_eeprom.h:86
ar9003_hw_eeprom_get_ht40_tgt_pwr
static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:3948
ar9300RateSize
Definition: ar9003_eeprom.h:152
N_LOOP
#define N_LOOP
ar9300_modal_eep_header::papdRateMaskHt40
uint32_t papdRateMaskHt40
Definition: ar9003_eeprom.h:239
ar9300_x112
static const struct ar9300_eeprom ar9300_x112
Definition: ath9k_ar9003_eeprom.c:1810
AR_CH0_XTAL
#define AR_CH0_XTAL
Definition: ar9003_phy.h:632
code
static unsigned int code
Response code.
Definition: hyperv.h:26
LEGACY_TARGET_RATE_5S
Definition: ar9003_eeprom.h:110
ar9300_eeprom::ctl_freqbin_2G
u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]
Definition: ar9003_eeprom.h:313
LEGACY_TARGET_RATE_6_24
Definition: ar9003_eeprom.h:102
ar9300_eeprom::calTargetPower5GHT20
struct cal_tgt_pow_ht calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:325
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
AR9300_OTP_STATUS_TYPE
#define AR9300_OTP_STATUS_TYPE
Definition: ar9003_eeprom.h:78
FREQ2FBIN
#define FREQ2FBIN(x, y)
Definition: eeprom.h:103
ar9300_cal_data_per_freq_op_loop
Definition: ar9003_eeprom.h:243
ath_regulatory
Definition: ath.h:138
HT_TARGET_RATE_7
Definition: ar9003_eeprom.h:90
malloc.h
Dynamic memory allocation.
abs
#define abs(x)
Definition: ath.h:46
HT_TARGET_RATE_0_8_16
Definition: ar9003_eeprom.h:85
ar9003_hw_get_max_edge_power
static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, u16 freq, int idx, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:4544
AR_RTC_REG_CONTROL1_SWREG_PROGRAM
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM
Definition: reg.h:1175
ar9300_base_eep_hdr::txrxgain
u8 txrxgain
Definition: ar9003_eeprom.h:201
AR_CH0_TOP2
#define AR_CH0_TOP2
Definition: ar9003_phy.h:628
AR_PHY_PMU1_PWD
#define AR_PHY_PMU1_PWD
Definition: ar9003_phy.h:639
ar9003_hw_ant_ctrl_apply
static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, int is2ghz)
Definition: ath9k_ar9003_eeprom.c:3503
ar9003_hw_eeprom_get_ht20_tgt_pwr
static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:3912
AR_PHY_SWITCH_COM
#define AR_PHY_SWITCH_COM
Definition: ar9002_phy.h:253
AR_PHY_EXT_ATTEN_CTL_2
#define AR_PHY_EXT_ATTEN_CTL_2
Definition: ar9003_phy.h:879
ar9300_BaseExtension_2::xatten1MarginHigh
u8 xatten1MarginHigh[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:284
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
ar9300_BaseExtension_2::tempSlopeHigh
int8_t tempSlopeHigh
Definition: ar9003_eeprom.h:280
major
uint32_t major
Major version.
Definition: netvsc.h:14
minor
uint32_t minor
Minor version.
Definition: netvsc.h:16
ar9300_base_eep_hdr::deviceCap
u8 deviceCap
Definition: ar9003_eeprom.h:179
ar9300_eeprom
Definition: ar9003_eeprom.h:287
AR9300_OTP_STATUS
#define AR9300_OTP_STATUS
Definition: ar9003_eeprom.h:77
LEGACY_TARGET_RATE_54
Definition: ar9003_eeprom.h:105
HT_TARGET_RATE_12
Definition: ar9003_eeprom.h:91
AR_RTC_SLEEP_CLK
#define AR_RTC_SLEEP_CLK
Definition: reg.h:1213
AR9300_NUM_CTLS_5G
#define AR9300_NUM_CTLS_5G
Definition: ar9003_eeprom.h:41
AR_PHY_SWITCH_COM_2
#define AR_PHY_SWITCH_COM_2
Definition: ar9003_phy.h:448
REDUCE_SCALED_POWER_BY_TWO_CHAIN
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN
Definition: ath9k_ar9003_eeprom.c:59
dx
uint16_t dx
Definition: registers.h:43
ar9300_base_eep_hdr::featureEnable
u8 featureEnable
Definition: ar9003_eeprom.h:194
AR_PHY_9485_ANT_DIV_LNA2
#define AR_PHY_9485_ANT_DIV_LNA2
Definition: ar9003_phy.h:290
cal_ctl_data_2g
Definition: ar9003_eeprom.h:265
AR9300_EEP_BASE_DRIV_STRENGTH
#define AR9300_EEP_BASE_DRIV_STRENGTH
AR9300_OTP_READ_DATA
#define AR9300_OTP_READ_DATA
Definition: ar9003_eeprom.h:82
AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN
Definition: ar9003_phy.h:348
value
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
HT_TARGET_RATE_23
Definition: ar9003_eeprom.h:98
ALL_TARGET_HT40_21
Definition: ar9003_eeprom.h:149
AR5416_OPFLAGS_11A
#define AR5416_OPFLAGS_11A
Definition: eeprom.h:124
__unused
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
AR9300_BASE_ADDR_4K
#define AR9300_BASE_ADDR_4K
Definition: ar9003_eeprom.h:72
ath9k_hw_regulatory
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:875
ar9003_hw_power_interpolate
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
Definition: ath9k_ar9003_eeprom.c:3823
eep_ar9300_ops
const struct eeprom_ops eep_ar9300_ops
Definition: ath9k_ar9003_eeprom.c:4997
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:61
AR_PHY_TPC_19
#define AR_PHY_TPC_19
Definition: ar9003_phy.h:544
ath9k_hw_ar9300_check_eeprom
static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah __unused)
Definition: ath9k_ar9003_eeprom.c:2994
FILE_SECBOOT
FILE_SECBOOT(FORBIDDEN)
ar9300_cal_data_per_freq_op_loop::tempMeas
u8 tempMeas
Definition: ar9003_eeprom.h:248
u8
#define u8
Definition: igbvf_osdep.h:40
AR_RTC_FORCE_SWREG_PRD
#define AR_RTC_FORCE_SWREG_PRD
Definition: reg.h:1216
count
static unsigned int count
Number of entries.
Definition: dwmac.h:225
LE16
#define LE16(x)
Definition: ath9k_ar9003_eeprom.c:51
ALL_TARGET_HT20_4
Definition: ar9003_eeprom.h:126
ar9003_hw_atten_chain_get
static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, struct ath9k_channel *chan)
Definition: ath9k_ar9003_eeprom.c:3619
cal_tgt_pow_legacy::tPow2x
u8 tPow2x[4]
Definition: ar9003_eeprom.h:258
ALL_TARGET_LEGACY_36
Definition: ar9003_eeprom.h:117
ar9300_eeprom::calTarget_freqbin_5GHT20
u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:321
AR_PHY_EXT_ATTEN_CTL_0
#define AR_PHY_EXT_ATTEN_CTL_0
Definition: ar9003_phy.h:261
AR_SREV_9340
#define AR_SREV_9340(_ah)
Definition: reg.h:879
ar9300_check_eeprom_header
static int ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, int base_addr)
Definition: ath9k_ar9003_eeprom.c:3276
ar9300_eeprom::calTargetPower2GHT20
struct cal_tgt_pow_ht calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:308
ALL_TARGET_HT20_14
Definition: ar9003_eeprom.h:132
templateVersion
u8 templateVersion
Definition: ar9003_eeprom.h:26
ar9300_modal_eep_header::antCtrlCommon
uint32_t antCtrlCommon
Definition: ar9003_eeprom.h:208
EEPROM_DATA_LEN_9485
#define EEPROM_DATA_LEN_9485
Definition: ath9k_ar9003_eeprom.c:70
AR_CH0_XTAL_CAPOUTDAC
#define AR_CH0_XTAL_CAPOUTDAC
Definition: ar9003_phy.h:635
HT_TARGET_RATE_20
Definition: ar9003_eeprom.h:95
ar9003_hw_apply_tuning_caps
static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:3782
ath9k_hw_use_flash
#define ath9k_hw_use_flash(_ah)
Definition: eeprom.h:104
AR_PHY_9485_ANT_DIV_LNA1
#define AR_PHY_9485_ANT_DIV_LNA1
Definition: ar9003_phy.h:291
FBIN2FREQ
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:49
ALL_TARGET_HT20_0_8_16
Definition: ar9003_eeprom.h:124
ALL_TARGET_HT40_7
Definition: ar9003_eeprom.h:143
AR_PHY_9485_ANT_DIV_ALT_GAINTB
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB
Definition: ar9003_phy.h:284
HT_TARGET_RATE_21
Definition: ar9003_eeprom.h:96
free
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:55
ar9300_modal_eep_header::papdRateMaskHt20
uint32_t papdRateMaskHt20
Definition: ar9003_eeprom.h:238
AR_CH0_TOP
#define AR_CH0_TOP
Definition: ath9k_ar9003_eeprom.c:32
ALL_TARGET_LEGACY_11S
Definition: ar9003_eeprom.h:123
ar9003_hw_xpa_bias_level_get
static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, int is2ghz)
Definition: ath9k_ar9003_eeprom.c:3436
AR_PHY_TPC_19_ALPHA_THERM
#define AR_PHY_TPC_19_ALPHA_THERM
Definition: ar9003_phy.h:547
ath9k_hw_nvram_read
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:131
ar9003_hw_get_indirect_edge_power
static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, int idx, unsigned int edge, u16 freq, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:4515
zalloc
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:662
CTL_11G_EXT
#define CTL_11G_EXT
Definition: ath9k_ar9003_eeprom.c:57
is_pmu_set
static int is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
Definition: ath9k_ar9003_eeprom.c:3698
AR5416_BCHAN_UNUSED
#define AR5416_BCHAN_UNUSED
Definition: eeprom.h:158
ath9k_hw_ar9300_get_eeprom
static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
Definition: ath9k_ar9003_eeprom.c:3009
AR_CH0_THERM_XPABIASLVL_MSB
#define AR_CH0_THERM_XPABIASLVL_MSB
Definition: ath9k_ar9003_eeprom.c:37
AR_CH0_TOP2_XPABIASLVL
#define AR_CH0_TOP2_XPABIASLVL
Definition: ar9003_phy.h:629
HT_TARGET_RATE_13
Definition: ar9003_eeprom.h:92
ar9003_hw_drive_strength_apply
static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:3578
AR_PHY_EXT_ATTEN_CTL_1
#define AR_PHY_EXT_ATTEN_CTL_1
Definition: ar9003_phy.h:824
AR9300_OTP_BASE
#define AR9300_OTP_BASE
Definition: ar9003_eeprom.h:76
ar9300_base_eep_hdr::regDmn
uint16_t regDmn[2]
Definition: ar9003_eeprom.h:173
param
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
ar9300_check_header
static int ar9300_check_header(void *data)
Definition: ath9k_ar9003_eeprom.c:3270
POW_SM
#define POW_SM(_r, _s)
AR_FAST_DIV_ENABLE
#define AR_FAST_DIV_ENABLE
Definition: ar9003_phy.h:306
addr
uint32_t addr
Buffer address.
Definition: dwmac.h:20
ar9300_base_eep_hdr
Definition: ar9003_eeprom.h:172
ALL_TARGET_LEGACY_48
Definition: ar9003_eeprom.h:118
ALL_TARGET_HT20_7
Definition: ar9003_eeprom.h:129
LE32
#define LE32(x)
Definition: ath9k_ar9003_eeprom.c:52
AR_PHY_PMU1
#define AR_PHY_PMU1
Definition: ar9003_phy.h:638
ar9300_BaseExtension_2::xatten1DBHigh
u8 xatten1DBHigh[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:283
ar9300_read_otp
static int ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, int count)
Definition: ath9k_ar9003_eeprom.c:3137
ar9300_read_eeprom
static int ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, int count)
Definition: ath9k_ar9003_eeprom.c:3081
ctlEdges
u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]
Definition: ar9003_eeprom.h:25
ath9k_hw_common
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:870
ip
IP4_t ip
Destination IP address.
Definition: pxe_api.h:58
base_addr
uint64_t base_addr
Definition: multiboot.h:13
AR_PHY_TPC_11_B2
#define AR_PHY_TPC_11_B2
Definition: ar9003_phy.h:903
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
ar9300_eeprom::calTarget_freqbin_5GHT40
u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]
Definition: ar9003_eeprom.h:322
ALL_TARGET_HT40_5
Definition: ar9003_eeprom.h:141
CTL_11A
#define CTL_11A
Definition: eeprom.h:71
ar9300_eeprom::modalHeader2G
struct ar9300_modal_eep_header modalHeader2G
Definition: ar9003_eeprom.h:295
ar9300_eeprom::base_ext1
struct ar9300_BaseExtension_1 base_ext1
Definition: ar9003_eeprom.h:296
ath9k_hw_ar9300_get_eeprom_ver
static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:3425
ar9300_eeprom::modalHeader5G
struct ar9300_modal_eep_header modalHeader5G
Definition: ar9003_eeprom.h:315
AR_PHY_CCK_DETECT
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:414
AR_PHY_TPC_6_B2
#define AR_PHY_TPC_6_B2
Definition: ar9003_phy.h:902
ath_common
Definition: ath.h:196
AR9300_PAPRD_SCALE_2
#define AR9300_PAPRD_SCALE_2
Definition: ar9003_eeprom.h:57
CTL_11G
#define CTL_11G
Definition: eeprom.h:73
ar9003_hw_eeprom_get_tgt_pwr
static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:3877
AR_NO_SPUR
#define AR_NO_SPUR
Definition: hw.h:241
ar9003_hw_xpa_bias_level_apply
static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, int is2ghz)
Definition: ath9k_ar9003_eeprom.c:3446
AR9300_NUM_2G_20_TARGET_POWERS
#define AR9300_NUM_2G_20_TARGET_POWERS
Definition: ar9003_eeprom.h:38
ar9300_base_eep_hdr::swreg
uint32_t swreg
Definition: ar9003_eeprom.h:203
ar9003_hw_atten_chain_get_margin
static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, struct ath9k_channel *chan)
Definition: ath9k_ar9003_eeprom.c:3647
ar9300_eeprom::calTarget_freqbin_Cck
u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]
Definition: ar9003_eeprom.h:300
ar9300_modal_eep_header::antennaGain
int8_t antennaGain
Definition: ar9003_eeprom.h:231
ar9300_BaseExtension_2::tempSlopeLow
int8_t tempSlopeLow
Definition: ar9003_eeprom.h:279
eeprom_ops
Definition: eeprom.h:653
ALL_TARGET_LEGACY_11L
Definition: ar9003_eeprom.h:122
ath9k_hw_ar9300_set_board_values
static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_eeprom.c:3796
uint32_t
unsigned int uint32_t
Definition: stdint.h:12
ar9300_eeprom::base_ext2
struct ar9300_BaseExtension_2 base_ext2
Definition: ar9003_eeprom.h:316
ar9300_base_eep_hdr::txrxMask
u8 txrxMask
Definition: ar9003_eeprom.h:175
common
struct ib_cm_common common
Definition: ib_mad.h:12
AR_PHY_TPC_OLPC_GAIN_DELTA_S
#define AR_PHY_TPC_OLPC_GAIN_DELTA_S
Definition: ar9003_phy.h:417
eeprom_ops::check_eeprom
int(* check_eeprom)(struct ath_hw *hw)
Definition: eeprom.h:654
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
ALL_TARGET_HT40_14
Definition: ar9003_eeprom.h:146
ar9300_base_eep_hdr::rfSilent
u8 rfSilent
Definition: ar9003_eeprom.h:177
HT_TARGET_RATE_15
Definition: ar9003_eeprom.h:94
ar9300_modal_eep_header::xatten1Margin
u8 xatten1Margin[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:216
ar9300_eeprom::calTargetPower5GHT40
struct cal_tgt_pow_ht calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]
Definition: ar9003_eeprom.h:327
ar9300_modal_eep_header
Definition: ar9003_eeprom.h:206
ar9300_modal_eep_header::xpaBiasLvl
u8 xpaBiasLvl
Definition: ar9003_eeprom.h:227
AR9300_NUM_BAND_EDGES_2G
#define AR9300_NUM_BAND_EDGES_2G
Definition: ar9003_eeprom.h:44
ar9300_eeprom::ctlPowerData_2G
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]
Definition: ar9003_eeprom.h:314
ar9300_eep_templates
static const struct ar9300_eeprom * ar9300_eep_templates[]
Definition: ath9k_ar9003_eeprom.c:2965
ALL_TARGET_HT20_13
Definition: ar9003_eeprom.h:131
ALL_TARGET_HT40_20
Definition: ar9003_eeprom.h:148
ar9300_eeprom::calTargetPower2G
struct cal_tgt_pow_legacy calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:306
chan_centers
Definition: hw.h:422
ar9300_eeprom::calTarget_freqbin_5G
u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:320
AR5416_OPFLAGS_11G
#define AR5416_OPFLAGS_11G
Definition: eeprom.h:125
ar9300_BaseExtension_1::ant_div_control
u8 ant_div_control
Definition: ar9003_eeprom.h:274
ar9003_hw_ant_ctrl_chain_get
static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, int is2ghz)
Definition: ath9k_ar9003_eeprom.c:3486
ar9300_comp_cksum
static u16 ar9300_comp_cksum(u8 *data, int dsize)
Definition: ath9k_ar9003_eeprom.c:3171
AR_PHY_TPC_18_THERM_CAL_VALUE
#define AR_PHY_TPC_18_THERM_CAL_VALUE
Definition: ar9003_phy.h:539
ath9k_hw_ar9300_get_eeprom_rev
static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah __unused)
Definition: ath9k_ar9003_eeprom.c:3431
SUB_NUM_CTL_MODES_AT_2G_40
#define SUB_NUM_CTL_MODES_AT_2G_40
Definition: ath9k_ar9003_eeprom.c:66
ALL_TARGET_HT20_15
Definition: ar9003_eeprom.h:133
SD_NO_CTL
#define SD_NO_CTL
Definition: eeprom.h:68
ar9300_base_eep_hdr::params_for_tuning_caps
u8 params_for_tuning_caps[2]
Definition: ar9003_eeprom.h:186
LEGACY_TARGET_RATE_11L
Definition: ar9003_eeprom.h:111
ar9300_otp_read_word
static int ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
Definition: ath9k_ar9003_eeprom.c:3125
LEGACY_TARGET_RATE_48
Definition: ar9003_eeprom.h:104
COMP_CKSUM_LEN
#define COMP_CKSUM_LEN
Definition: ath9k_ar9003_eeprom.c:30
ath9k_channel
Definition: hw.h:347
AR_ANT_DIV_CTRL_ALL
#define AR_ANT_DIV_CTRL_ALL
Definition: ar9003_phy.h:270
ar9003_hw_ant_ctrl_common_get
static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, int is2ghz)
Definition: ath9k_ar9003_eeprom.c:3462
ar9300_eeprom::calTargetPower5G
struct cal_tgt_pow_legacy calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]
Definition: ar9003_eeprom.h:323
BIT
#define BIT(nr)
Definition: ath.h:34
ar9300_cal_data_per_freq_op_loop::refPower
int8_t refPower
Definition: ar9003_eeprom.h:244
ar9003_hw_get_tx_gain_idx
s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
Definition: ath9k_ar9003_eeprom.c:4952
AR_PHY_9485_ANT_DIV_LNADIV
#define AR_PHY_9485_ANT_DIV_LNADIV
Definition: ar9003_phy.h:278
AR9300_BASE_ADDR_512
#define AR9300_BASE_ADDR_512
Definition: ar9003_eeprom.h:74
int32_t
signed int int32_t
Definition: stdint.h:17
ALL_TARGET_HT20_21
Definition: ar9003_eeprom.h:135
ALL_TARGET_HT40_1_3_9_11_17_19
Definition: ar9003_eeprom.h:139
CTL_11A_EXT
#define CTL_11A_EXT
Definition: ath9k_ar9003_eeprom.c:56
eeprom_param
eeprom_param
Definition: eeprom.h:226
ath9k_hw_ar9300_set_txpower
static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
Definition: ath9k_ar9003_eeprom.c:4823
HT_TARGET_RATE_22
Definition: ar9003_eeprom.h:97
block
uint8_t block[3][8]
DES-encrypted blocks.
Definition: mschapv2.h:12
eeprom_read_op
int(* eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, int count)
Definition: ath9k_ar9003_eeprom.c:3267
AR_PHY_SWITCH_CHAIN_2
#define AR_PHY_SWITCH_CHAIN_2
Definition: ar9003_phy.h:895
ath9k_hw_wait
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:95
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ALL_TARGET_HT20_22
Definition: ar9003_eeprom.h:136
AR9300_NUM_2G_CAL_PIERS
#define AR9300_NUM_2G_CAL_PIERS
Definition: ar9003_eeprom.h:34
ar9003_hw_get_direct_edge_power
static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, int idx, int edge, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:4501
CTL_2GHT20
#define CTL_2GHT20
Definition: eeprom.h:74
y
static unsigned int unsigned int y
Definition: pixbuf.h:63
header
struct ena_llq_option header
Header locations.
Definition: ena.h:16
CTL_11B
#define CTL_11B
Definition: eeprom.h:72
ALL_TARGET_HT20_6
Definition: ar9003_eeprom.h:128
REG_READ_FIELD
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:106
ar9300_eeprom::calPierData2G
struct ar9300_cal_data_per_freq_op_loop calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]
Definition: ar9003_eeprom.h:298
ar9003_hw_atten_apply
static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_eeprom.c:3674
word
unsigned short word
Definition: smc9000.h:39
ar9300_modal_eep_header::antCtrlCommon2
uint32_t antCtrlCommon2
Definition: ar9003_eeprom.h:210
ar9300_eeprom::ctlPowerData_5G
struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]
Definition: ar9003_eeprom.h:331
data
uint8_t data[48]
Additional event data.
Definition: ena.h:22
ar9003_get_spur_chan_ptr
u8 * ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
Definition: ath9k_ar9003_eeprom.c:4966
ar9300_modal_eep_header::xatten1DB
u8 xatten1DB[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:214
HT_TARGET_RATE_14
Definition: ar9003_eeprom.h:93
AR_PHY_65NM_CH0_BIAS1
#define AR_PHY_65NM_CH0_BIAS1
Definition: ar9003_phy.h:608
CTL_MODE_M
#define CTL_MODE_M
Definition: eeprom.h:70
ALL_TARGET_HT20_1_3_9_11_17_19
Definition: ar9003_eeprom.h:125
CTL_11B_EXT
#define CTL_11B_EXT
Definition: ath9k_ar9003_eeprom.c:58
_CompressBlock
Definition: ar9003_eeprom.h:165
ar9300_eeprom::calFreqPier5G
u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]
Definition: ar9003_eeprom.h:317
ath9k_hw_get_channel_centers
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:191
ar9300_eeprom::baseEepHeader
struct ar9300_base_eep_hdr baseEepHeader
Definition: ar9003_eeprom.h:293
AR9300_NUM_CTLS_2G
#define AR9300_NUM_CTLS_2G
Definition: ar9003_eeprom.h:42
ALL_TARGET_HT20_5
Definition: ar9003_eeprom.h:127
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_PMU2_PGM
#define AR_PHY_PMU2_PGM
Definition: ar9003_phy.h:643
ath9k_hw_fbin2freq
static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
Definition: ath9k_ar9003_eeprom.c:2986
timeout
void timeout(int)
COMP_HDR_LEN
#define COMP_HDR_LEN
Definition: ath9k_ar9003_eeprom.c:29
AR_PHY_TPC_18
#define AR_PHY_TPC_18
Definition: ar9003_phy.h:538
AR_PHY_SWITCH_CHAIN_0
#define AR_PHY_SWITCH_CHAIN_0
Definition: ar9002_phy.h:252
AR9300_NUM_5G_40_TARGET_POWERS
#define AR9300_NUM_5G_40_TARGET_POWERS
Definition: ar9003_eeprom.h:36
ar9003_hw_set_power_per_rate_table
static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, u8 *pPwrArray, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u16 powerLimit)
Definition: ath9k_ar9003_eeprom.c:4585
swreg
uint32_t swreg
Definition: ar9003_eeprom.h:55
ar9300_eeprom::calPierData5G
struct ar9300_cal_data_per_freq_op_loop calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]
Definition: ar9003_eeprom.h:318
mcsidx_to_tgtpwridx
static u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
Definition: ath9k_ar9003_eeprom.c:4813
AR_PHY_MC_GAIN_CTRL
#define AR_PHY_MC_GAIN_CTRL
Definition: ar9003_phy.h:269
AR9300_PAPRD_RATE_MASK
#define AR9300_PAPRD_RATE_MASK
Definition: ar9003_eeprom.h:54
int16_t
signed short int16_t
Definition: stdint.h:16
ALL_TARGET_HT20_23
Definition: ar9003_eeprom.h:137
IS_CHAN_HT20
#define IS_CHAN_HT20(_c)
Definition: hw.h:371
offset
uint16_t offset
Offset to command line.
Definition: bzimage.h:8
ar9300_eeprom_restore_flash
static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, int mdata_size)
Definition: ath9k_ar9003_eeprom.c:3287
AR9300_NUM_2G_40_TARGET_POWERS
#define AR9300_NUM_2G_40_TARGET_POWERS
Definition: ar9003_eeprom.h:39
AR_PHY_9485_ANT_DIV_LNADIV_S
#define AR_PHY_9485_ANT_DIV_LNADIV_S
Definition: ar9003_phy.h:279
ar9300_eeprom::calTargetPower2GHT40
struct cal_tgt_pow_ht calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]
Definition: ar9003_eeprom.h:310
DBG
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
IS_CHAN_HT40
#define IS_CHAN_HT40(_c)
Definition: hw.h:373
ar9300_comp_hdr_unpack
static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, int *length, int *major, int *minor)
Definition: ath9k_ar9003_eeprom.c:3155
AR_ANT_DIV_CTRL_ALL_S
#define AR_ANT_DIV_CTRL_ALL_S
Definition: ar9003_phy.h:271
AR_SWITCH_TABLE_COM_ALL
#define AR_SWITCH_TABLE_COM_ALL
Definition: ath9k_ar9003_eeprom.c:42
CTL_EDGE_TPOWER
#define CTL_EDGE_TPOWER(_ctl)
Definition: eeprom.h:214
CTL_5GHT40
#define CTL_5GHT40
Definition: eeprom.h:77
MSTATE
#define MSTATE
ar9300_eeprom::macAddr
u8 macAddr[6]
Definition: ar9003_eeprom.h:290
AR_PHY_9485_ANT_DIV_ALT_LNACONF
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF
Definition: ar9003_phy.h:280
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
AR_PHY_65NM_CH0_BIAS4
#define AR_PHY_65NM_CH0_BIAS4
Definition: ar9003_phy.h:610
AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
Definition: ar9003_phy.h:281
ALL_TARGET_HT40_13
Definition: ar9003_eeprom.h:145
CTL_5GHT20
#define CTL_5GHT20
Definition: eeprom.h:75
AR_CH0_THERM
#define AR_CH0_THERM
Definition: ath9k_ar9003_eeprom.c:36
AR_FAST_DIV_ENABLE_S
#define AR_FAST_DIV_ENABLE_S
Definition: ar9003_phy.h:307
u8
uint8_t u8
Definition: stdint.h:20
AR_CH0_XTAL_CAPINDAC
#define AR_CH0_XTAL_CAPINDAC
Definition: ar9003_phy.h:633
test
static int test
Definition: epic100.c:73
ath_regulatory::max_power_level
u16 max_power_level
Definition: ath.h:141
MAX_RATE_POWER
#define MAX_RATE_POWER
Definition: hw.h:145
ar9300_eeprom_read_word
static int ar9300_eeprom_read_word(struct ath_common *common, int address, u8 *buffer)
Definition: ath9k_ar9003_eeprom.c:3067
u32
uint32_t u32
Definition: stdint.h:24
ar9300_uncompress_block
static int ar9300_uncompress_block(struct ath_hw *ah __unused, u8 *mptr, int mdataSize, u8 *block, int size)
Definition: ath9k_ar9003_eeprom.c:3183
HT_TARGET_RATE_5
Definition: ar9003_eeprom.h:88
AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB
Definition: ar9003_phy.h:352
LEGACY_TARGET_RATE_1L_5L
Definition: ar9003_eeprom.h:109
ar9300_modal_eep_header::antCtrlChain
uint16_t antCtrlChain[AR9300_MAX_CHAINS]
Definition: ar9003_eeprom.h:212
cal_tgt_pow_legacy
Definition: ar9003_eeprom.h:257
cal_ctl_data_5g
Definition: ar9003_eeprom.h:269
ar9003_hw_ant_ctrl_common_2_get
static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, int is2ghz)
Definition: ath9k_ar9003_eeprom.c:3474
DBG2
#define DBG2(...)
Definition: compiler.h:515
ar9300_eeprom::ctl_freqbin_5G
u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]
Definition: ar9003_eeprom.h:330
_CompressNone
Definition: ar9003_eeprom.h:162
if
if(natsemi->flags &NATSEMI_64BIT) return 1
AR_PHY_TPC_6_ERROR_EST_MODE_S
#define AR_PHY_TPC_6_ERROR_EST_MODE_S
Definition: ar9003_phy.h:420
ALL_TARGET_LEGACY_1L_5L
Definition: ar9003_eeprom.h:120
ath_regulatory::tp_scale
u32 tp_scale
Definition: ath.h:142
ALL_TARGET_HT40_15
Definition: ar9003_eeprom.h:147
ar9300_modal_eep_header::tempSlope
int8_t tempSlope
Definition: ar9003_eeprom.h:217
AR_PHY_9485_ANT_DIV_MAIN_GAINTB
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB
Definition: ar9003_phy.h:286
AR_PHY_TPC_6_B0
#define AR_PHY_TPC_6_B0
Definition: ar9003_phy.h:526
chan_centers::ctl_center
u16 ctl_center
Definition: hw.h:424
Generated by   doxygen 1.8.15