27 #define COMP_HDR_LEN 4 28 #define COMP_CKSUM_LEN 2 30 #define AR_CH0_TOP (0x00016288) 31 #define AR_CH0_TOP_XPABIASLVL (0x300) 32 #define AR_CH0_TOP_XPABIASLVL_S (8) 34 #define AR_CH0_THERM (0x00016290) 35 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3 36 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0 37 #define AR_CH0_THERM_XPASHORT2GND 0x4 38 #define AR_CH0_THERM_XPASHORT2GND_S 2 40 #define AR_SWITCH_TABLE_COM_ALL (0xffff) 41 #define AR_SWITCH_TABLE_COM_ALL_S (0) 43 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff) 44 #define AR_SWITCH_TABLE_COM2_ALL_S (0) 46 #define AR_SWITCH_TABLE_ALL (0xfff) 47 #define AR_SWITCH_TABLE_ALL_S (0) 49 #define LE16(x) (uint16_t)(x) 50 #define LE32(x) (uint32_t)(x) 53 #define EXT_ADDITIVE (0x8000) 54 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 55 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 56 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 57 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 58 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 59 #define PWRINCR_3_TO_1_CHAIN 9 60 #define PWRINCR_3_TO_2_CHAIN 3 61 #define PWRINCR_2_TO_1_CHAIN 6 63 #define SUB_NUM_CTL_MODES_AT_5G_40 2 64 #define SUB_NUM_CTL_MODES_AT_2G_40 3 66 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) 68 #define EEPROM_DATA_LEN_9485 1088 77 .macAddr = {1, 2, 3, 4, 5, 6},
78 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
88 .blueToothOptions = 0,
92 .params_for_tuning_caps = {0, 0},
93 .featureEnable = 0x0c,
102 .miscConfiguration = 0,
103 .eepromWriteEnableGpio = 3,
104 .wlanDisableGpio = 0,
106 .rxBandSelectGpio = 0xff,
113 .antCtrlCommon =
LE32(0x110),
115 .antCtrlCommon2 =
LE32(0x22222),
121 .antCtrlChain = {
LE16(0x150),
LE16(0x150),
LE16(0x150) },
127 .xatten1DB = {0, 0, 0},
133 .xatten1Margin = {0, 0, 0},
141 .spurChans = {0, 0, 0, 0, 0},
147 .noiseFloorThreshCh = {-1, 0, 0},
149 .db_stage2 = {1, 1, 1},
150 .db_stage3 = {0, 0, 0},
151 .db_stage4 = {0, 0, 0},
153 .txFrameToDataStart = 0x0e,
154 .txFrameToPaOn = 0x0e,
157 .switchSettling = 0x2c,
158 .adcDesiredSize = -30,
161 .txFrameToXpaOn = 0xe,
163 .papdRateMaskHt20 =
LE32(0x0cf0e0e0),
164 .papdRateMaskHt40 =
LE32(0x6cf0e0e0),
166 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
170 .ant_div_control = 0,
171 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
180 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
181 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
182 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
184 .calTarget_freqbin_Cck = {
188 .calTarget_freqbin_2G = {
193 .calTarget_freqbin_2GHT20 = {
198 .calTarget_freqbin_2GHT40 = {
203 .calTargetPowerCck = {
205 { {36, 36, 36, 36} },
206 { {36, 36, 36, 36} },
208 .calTargetPower2G = {
210 { {32, 32, 28, 24} },
211 { {32, 32, 28, 24} },
212 { {32, 32, 28, 24} },
214 .calTargetPower2GHT20 = {
215 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
216 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
217 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
219 .calTargetPower2GHT40 = {
220 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
221 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
222 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
225 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
226 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
329 .antCtrlCommon =
LE32(0x110),
331 .antCtrlCommon2 =
LE32(0x22222),
337 .xatten1DB = {0, 0, 0},
343 .xatten1Margin = {0, 0, 0},
347 .spurChans = {0, 0, 0, 0, 0},
349 .noiseFloorThreshCh = {-1, 0, 0},
351 .db_stage2 = {3, 3, 3},
352 .db_stage3 = {3, 3, 3},
353 .db_stage4 = {3, 3, 3},
355 .txFrameToDataStart = 0x0e,
356 .txFrameToPaOn = 0x0e,
359 .switchSettling = 0x2d,
360 .adcDesiredSize = -30,
363 .txFrameToXpaOn = 0xe,
365 .papdRateMaskHt20 =
LE32(0x0c80c080),
366 .papdRateMaskHt40 =
LE32(0x0080c080),
368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
374 .xatten1DBLow = {0, 0, 0},
375 .xatten1MarginLow = {0, 0, 0},
376 .xatten1DBHigh = {0, 0, 0},
377 .xatten1MarginHigh = {0, 0, 0}
422 .calTarget_freqbin_5G = {
432 .calTarget_freqbin_5GHT20 = {
442 .calTarget_freqbin_5GHT40 = {
452 .calTargetPower5G = {
454 { {20, 20, 20, 10} },
455 { {20, 20, 20, 10} },
456 { {20, 20, 20, 10} },
457 { {20, 20, 20, 10} },
458 { {20, 20, 20, 10} },
459 { {20, 20, 20, 10} },
460 { {20, 20, 20, 10} },
461 { {20, 20, 20, 10} },
463 .calTargetPower5GHT20 = {
468 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
469 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
477 .calTargetPower5GHT40 = {
482 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
483 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
484 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
485 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
486 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
487 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
488 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
489 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
492 0x10, 0x16, 0x18, 0x40, 0x46,
493 0x48, 0x30, 0x36, 0x38
654 .templateVersion = 6,
655 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
656 .custData = {
"x113-023-f0000"},
665 .blueToothOptions = 0,
669 .params_for_tuning_caps = {0, 0},
670 .featureEnable = 0x0d,
679 .miscConfiguration = 0,
680 .eepromWriteEnableGpio = 6,
681 .wlanDisableGpio = 0,
683 .rxBandSelectGpio = 0xff,
690 .antCtrlCommon =
LE32(0x110),
692 .antCtrlCommon2 =
LE32(0x44444),
698 .antCtrlChain = {
LE16(0x150),
LE16(0x150),
LE16(0x150) },
704 .xatten1DB = {0, 0, 0},
710 .xatten1Margin = {0, 0, 0},
718 .spurChans = {
FREQ2FBIN(2464, 1), 0, 0, 0, 0},
724 .noiseFloorThreshCh = {-1, 0, 0},
726 .db_stage2 = {1, 1, 1},
727 .db_stage3 = {0, 0, 0},
728 .db_stage4 = {0, 0, 0},
730 .txFrameToDataStart = 0x0e,
731 .txFrameToPaOn = 0x0e,
734 .switchSettling = 0x2c,
735 .adcDesiredSize = -30,
738 .txFrameToXpaOn = 0xe,
740 .papdRateMaskHt20 =
LE32(0x0c80c080),
741 .papdRateMaskHt40 =
LE32(0x0080c080),
743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
747 .ant_div_control = 0,
748 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
757 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
758 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
759 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
761 .calTarget_freqbin_Cck = {
765 .calTarget_freqbin_2G = {
770 .calTarget_freqbin_2GHT20 = {
775 .calTarget_freqbin_2GHT40 = {
780 .calTargetPowerCck = {
782 { {34, 34, 34, 34} },
783 { {34, 34, 34, 34} },
785 .calTargetPower2G = {
787 { {34, 34, 32, 32} },
788 { {34, 34, 32, 32} },
789 { {34, 34, 32, 32} },
791 .calTargetPower2GHT20 = {
792 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
793 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
794 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
796 .calTargetPower2GHT40 = {
797 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
798 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
799 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
802 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
803 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
906 .antCtrlCommon =
LE32(0x220),
908 .antCtrlCommon2 =
LE32(0x11111),
914 .xatten1DB = {0, 0, 0},
920 .xatten1Margin = {0, 0, 0},
924 .spurChans = {
FREQ2FBIN(5500, 0), 0, 0, 0, 0},
926 .noiseFloorThreshCh = {-1, 0, 0},
928 .db_stage2 = {3, 3, 3},
929 .db_stage3 = {3, 3, 3},
930 .db_stage4 = {3, 3, 3},
932 .txFrameToDataStart = 0x0e,
933 .txFrameToPaOn = 0x0e,
936 .switchSettling = 0x2d,
937 .adcDesiredSize = -30,
940 .txFrameToXpaOn = 0xe,
942 .papdRateMaskHt20 =
LE32(0x0cf0e0e0),
943 .papdRateMaskHt40 =
LE32(0x6cf0e0e0),
945 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
950 .tempSlopeHigh = 105,
951 .xatten1DBLow = {0, 0, 0},
952 .xatten1MarginLow = {0, 0, 0},
953 .xatten1DBHigh = {0, 0, 0},
954 .xatten1MarginHigh = {0, 0, 0}
999 .calTarget_freqbin_5G = {
1009 .calTarget_freqbin_5GHT20 = {
1019 .calTarget_freqbin_5GHT40 = {
1029 .calTargetPower5G = {
1031 { {42, 40, 40, 34} },
1032 { {42, 40, 40, 34} },
1033 { {42, 40, 40, 34} },
1034 { {42, 40, 40, 34} },
1035 { {42, 40, 40, 34} },
1036 { {42, 40, 40, 34} },
1037 { {42, 40, 40, 34} },
1038 { {42, 40, 40, 34} },
1040 .calTargetPower5GHT20 = {
1045 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1046 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1047 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1048 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1049 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1050 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1051 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1052 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1054 .calTargetPower5GHT40 = {
1059 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1060 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1061 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1062 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1063 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1064 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1065 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1066 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1069 0x10, 0x16, 0x18, 0x40, 0x46,
1070 0x48, 0x30, 0x36, 0x38
1171 .ctlPowerData_5G = {
1232 .templateVersion = 3,
1233 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1234 .custData = {
"h112-241-f0000"},
1243 .blueToothOptions = 0,
1247 .params_for_tuning_caps = {0, 0},
1248 .featureEnable = 0x0d,
1257 .miscConfiguration = 0,
1258 .eepromWriteEnableGpio = 6,
1259 .wlanDisableGpio = 0,
1261 .rxBandSelectGpio = 0xff,
1268 .antCtrlCommon =
LE32(0x110),
1270 .antCtrlCommon2 =
LE32(0x44444),
1276 .antCtrlChain = {
LE16(0x150),
LE16(0x150),
LE16(0x150) },
1282 .xatten1DB = {0, 0, 0},
1288 .xatten1Margin = {0, 0, 0},
1296 .spurChans = {
FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1302 .noiseFloorThreshCh = {-1, 0, 0},
1304 .db_stage2 = {1, 1, 1},
1305 .db_stage3 = {0, 0, 0},
1306 .db_stage4 = {0, 0, 0},
1308 .txFrameToDataStart = 0x0e,
1309 .txFrameToPaOn = 0x0e,
1312 .switchSettling = 0x2c,
1313 .adcDesiredSize = -30,
1316 .txFrameToXpaOn = 0xe,
1318 .papdRateMaskHt20 =
LE32(0x80c080),
1319 .papdRateMaskHt40 =
LE32(0x80c080),
1321 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1325 .ant_div_control = 0,
1326 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1335 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1336 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1337 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1339 .calTarget_freqbin_Cck = {
1343 .calTarget_freqbin_2G = {
1348 .calTarget_freqbin_2GHT20 = {
1353 .calTarget_freqbin_2GHT40 = {
1358 .calTargetPowerCck = {
1360 { {34, 34, 34, 34} },
1361 { {34, 34, 34, 34} },
1363 .calTargetPower2G = {
1365 { {34, 34, 32, 32} },
1366 { {34, 34, 32, 32} },
1367 { {34, 34, 32, 32} },
1369 .calTargetPower2GHT20 = {
1370 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1371 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1372 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1374 .calTargetPower2GHT40 = {
1375 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1376 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1377 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1380 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1381 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1465 .ctlPowerData_2G = {
1466 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1467 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1468 { {
CTL(60, 1),
CTL(60, 0),
CTL(60, 0),
CTL(60, 1) } },
1471 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1472 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1474 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 0) } },
1475 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1476 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1478 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
1479 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 1) } },
1480 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 1) } },
1484 .antCtrlCommon =
LE32(0x220),
1486 .antCtrlCommon2 =
LE32(0x44444),
1492 .xatten1DB = {0, 0, 0},
1498 .xatten1Margin = {0, 0, 0},
1502 .spurChans = {0, 0, 0, 0, 0},
1504 .noiseFloorThreshCh = {-1, 0, 0},
1506 .db_stage2 = {3, 3, 3},
1507 .db_stage3 = {3, 3, 3},
1508 .db_stage4 = {3, 3, 3},
1510 .txFrameToDataStart = 0x0e,
1511 .txFrameToPaOn = 0x0e,
1514 .switchSettling = 0x2d,
1515 .adcDesiredSize = -30,
1518 .txFrameToXpaOn = 0xe,
1520 .papdRateMaskHt20 =
LE32(0x0cf0e0e0),
1521 .papdRateMaskHt40 =
LE32(0x6cf0e0e0),
1523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1528 .tempSlopeHigh = 50,
1529 .xatten1DBLow = {0, 0, 0},
1530 .xatten1MarginLow = {0, 0, 0},
1531 .xatten1DBHigh = {0, 0, 0},
1532 .xatten1MarginHigh = {0, 0, 0}
1577 .calTarget_freqbin_5G = {
1587 .calTarget_freqbin_5GHT20 = {
1597 .calTarget_freqbin_5GHT40 = {
1607 .calTargetPower5G = {
1609 { {30, 30, 28, 24} },
1610 { {30, 30, 28, 24} },
1611 { {30, 30, 28, 24} },
1612 { {30, 30, 28, 24} },
1613 { {30, 30, 28, 24} },
1614 { {30, 30, 28, 24} },
1615 { {30, 30, 28, 24} },
1616 { {30, 30, 28, 24} },
1618 .calTargetPower5GHT20 = {
1623 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1624 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1625 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1626 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1627 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1628 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1629 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1630 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1632 .calTargetPower5GHT40 = {
1637 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1638 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1639 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1640 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1641 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1642 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1643 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1644 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1647 0x10, 0x16, 0x18, 0x40, 0x46,
1648 0x48, 0x30, 0x36, 0x38
1749 .ctlPowerData_5G = {
1810 .templateVersion = 5,
1811 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1812 .custData = {
"x112-041-f0000"},
1821 .blueToothOptions = 0,
1825 .params_for_tuning_caps = {0, 0},
1826 .featureEnable = 0x0d,
1835 .miscConfiguration = 0,
1836 .eepromWriteEnableGpio = 6,
1837 .wlanDisableGpio = 0,
1839 .rxBandSelectGpio = 0xff,
1846 .antCtrlCommon =
LE32(0x110),
1848 .antCtrlCommon2 =
LE32(0x22222),
1854 .antCtrlChain = {
LE16(0x10),
LE16(0x10),
LE16(0x10) },
1860 .xatten1DB = {0x1b, 0x1b, 0x1b},
1866 .xatten1Margin = {0x15, 0x15, 0x15},
1874 .spurChans = {
FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1880 .noiseFloorThreshCh = {-1, 0, 0},
1882 .db_stage2 = {1, 1, 1},
1883 .db_stage3 = {0, 0, 0},
1884 .db_stage4 = {0, 0, 0},
1886 .txFrameToDataStart = 0x0e,
1887 .txFrameToPaOn = 0x0e,
1890 .switchSettling = 0x2c,
1891 .adcDesiredSize = -30,
1894 .txFrameToXpaOn = 0xe,
1896 .papdRateMaskHt20 =
LE32(0x0c80c080),
1897 .papdRateMaskHt40 =
LE32(0x0080c080),
1899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1903 .ant_div_control = 0,
1904 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1913 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1914 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1915 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1917 .calTarget_freqbin_Cck = {
1921 .calTarget_freqbin_2G = {
1926 .calTarget_freqbin_2GHT20 = {
1931 .calTarget_freqbin_2GHT40 = {
1936 .calTargetPowerCck = {
1938 { {38, 38, 38, 38} },
1939 { {38, 38, 38, 38} },
1941 .calTargetPower2G = {
1943 { {38, 38, 36, 34} },
1944 { {38, 38, 36, 34} },
1945 { {38, 38, 34, 32} },
1947 .calTargetPower2GHT20 = {
1948 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1949 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1950 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1952 .calTargetPower2GHT40 = {
1953 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1954 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1955 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1958 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1959 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2043 .ctlPowerData_2G = {
2044 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2045 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2046 { {
CTL(60, 1),
CTL(60, 0),
CTL(60, 0),
CTL(60, 1) } },
2049 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2050 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2052 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 0) } },
2053 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2054 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2056 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2057 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 1) } },
2058 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 1) } },
2062 .antCtrlCommon =
LE32(0x110),
2064 .antCtrlCommon2 =
LE32(0x22222),
2070 .xatten1DB = {0x13, 0x19, 0x17},
2076 .xatten1Margin = {0x19, 0x19, 0x19},
2080 .spurChans = {0, 0, 0, 0, 0},
2082 .noiseFloorThreshCh = {-1, 0, 0},
2084 .db_stage2 = {3, 3, 3},
2085 .db_stage3 = {3, 3, 3},
2086 .db_stage4 = {3, 3, 3},
2088 .txFrameToDataStart = 0x0e,
2089 .txFrameToPaOn = 0x0e,
2092 .switchSettling = 0x2d,
2093 .adcDesiredSize = -30,
2096 .txFrameToXpaOn = 0xe,
2098 .papdRateMaskHt20 =
LE32(0x0cf0e0e0),
2099 .papdRateMaskHt40 =
LE32(0x6cf0e0e0),
2101 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2106 .tempSlopeHigh = 105,
2107 .xatten1DBLow = {0x10, 0x14, 0x10},
2108 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2109 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2110 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2155 .calTarget_freqbin_5G = {
2165 .calTarget_freqbin_5GHT20 = {
2175 .calTarget_freqbin_5GHT40 = {
2185 .calTargetPower5G = {
2187 { {32, 32, 28, 26} },
2188 { {32, 32, 28, 26} },
2189 { {32, 32, 28, 26} },
2190 { {32, 32, 26, 24} },
2191 { {32, 32, 26, 24} },
2192 { {32, 32, 24, 22} },
2193 { {30, 30, 24, 22} },
2194 { {30, 30, 24, 22} },
2196 .calTargetPower5GHT20 = {
2201 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2202 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2203 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2204 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2205 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2206 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2207 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2208 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2210 .calTargetPower5GHT40 = {
2215 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2216 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2217 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2218 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2219 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2220 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2221 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2222 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2225 0x10, 0x16, 0x18, 0x40, 0x46,
2226 0x48, 0x30, 0x36, 0x38
2327 .ctlPowerData_5G = {
2387 .templateVersion = 4,
2388 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2389 .custData = {
"h116-041-f0000"},
2398 .blueToothOptions = 0,
2402 .params_for_tuning_caps = {0, 0},
2403 .featureEnable = 0x0d,
2412 .miscConfiguration = 0,
2413 .eepromWriteEnableGpio = 6,
2414 .wlanDisableGpio = 0,
2416 .rxBandSelectGpio = 0xff,
2423 .antCtrlCommon =
LE32(0x110),
2425 .antCtrlCommon2 =
LE32(0x44444),
2431 .antCtrlChain = {
LE16(0x10),
LE16(0x10),
LE16(0x10) },
2437 .xatten1DB = {0x1f, 0x1f, 0x1f},
2443 .xatten1Margin = {0x12, 0x12, 0x12},
2451 .spurChans = {
FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2457 .noiseFloorThreshCh = {-1, 0, 0},
2459 .db_stage2 = {1, 1, 1},
2460 .db_stage3 = {0, 0, 0},
2461 .db_stage4 = {0, 0, 0},
2463 .txFrameToDataStart = 0x0e,
2464 .txFrameToPaOn = 0x0e,
2467 .switchSettling = 0x2c,
2468 .adcDesiredSize = -30,
2471 .txFrameToXpaOn = 0xe,
2473 .papdRateMaskHt20 =
LE32(0x0c80C080),
2474 .papdRateMaskHt40 =
LE32(0x0080C080),
2476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2480 .ant_div_control = 0,
2481 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2490 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2491 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2492 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2494 .calTarget_freqbin_Cck = {
2498 .calTarget_freqbin_2G = {
2503 .calTarget_freqbin_2GHT20 = {
2508 .calTarget_freqbin_2GHT40 = {
2513 .calTargetPowerCck = {
2515 { {34, 34, 34, 34} },
2516 { {34, 34, 34, 34} },
2518 .calTargetPower2G = {
2520 { {34, 34, 32, 32} },
2521 { {34, 34, 32, 32} },
2522 { {34, 34, 32, 32} },
2524 .calTargetPower2GHT20 = {
2525 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2526 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2527 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2529 .calTargetPower2GHT40 = {
2530 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2531 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2532 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2535 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2536 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2620 .ctlPowerData_2G = {
2621 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2622 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2623 { {
CTL(60, 1),
CTL(60, 0),
CTL(60, 0),
CTL(60, 1) } },
2626 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2627 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2629 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 0) } },
2630 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2631 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2633 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 0),
CTL(60, 0) } },
2634 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 1) } },
2635 { {
CTL(60, 0),
CTL(60, 1),
CTL(60, 1),
CTL(60, 1) } },
2639 .antCtrlCommon =
LE32(0x220),
2641 .antCtrlCommon2 =
LE32(0x44444),
2647 .xatten1DB = {0x19, 0x19, 0x19},
2653 .xatten1Margin = {0x14, 0x14, 0x14},
2657 .spurChans = {0, 0, 0, 0, 0},
2659 .noiseFloorThreshCh = {-1, 0, 0},
2661 .db_stage2 = {3, 3, 3},
2662 .db_stage3 = {3, 3, 3},
2663 .db_stage4 = {3, 3, 3},
2665 .txFrameToDataStart = 0x0e,
2666 .txFrameToPaOn = 0x0e,
2669 .switchSettling = 0x2d,
2670 .adcDesiredSize = -30,
2673 .txFrameToXpaOn = 0xe,
2675 .papdRateMaskHt20 =
LE32(0x0cf0e0e0),
2676 .papdRateMaskHt40 =
LE32(0x6cf0e0e0),
2678 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2683 .tempSlopeHigh = 50,
2684 .xatten1DBLow = {0, 0, 0},
2685 .xatten1MarginLow = {0, 0, 0},
2686 .xatten1DBHigh = {0, 0, 0},
2687 .xatten1MarginHigh = {0, 0, 0}
2732 .calTarget_freqbin_5G = {
2742 .calTarget_freqbin_5GHT20 = {
2752 .calTarget_freqbin_5GHT40 = {
2762 .calTargetPower5G = {
2764 { {30, 30, 28, 24} },
2765 { {30, 30, 28, 24} },
2766 { {30, 30, 28, 24} },
2767 { {30, 30, 28, 24} },
2768 { {30, 30, 28, 24} },
2769 { {30, 30, 28, 24} },
2770 { {30, 30, 28, 24} },
2771 { {30, 30, 28, 24} },
2773 .calTargetPower5GHT20 = {
2778 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2779 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2780 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2781 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2782 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2783 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2784 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2785 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2787 .calTargetPower5GHT40 = {
2792 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2793 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2794 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2795 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2796 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2797 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2798 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2799 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2802 0x10, 0x16, 0x18, 0x40, 0x46,
2803 0x48, 0x30, 0x36, 0x38
2904 .ctlPowerData_5G = {
2973 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0])) 2976 for (it = 0; it <
N_LOOP; it++)
2989 return (
u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2999 int bf, factor, plus;
3001 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
3004 return ya + factor + plus;
3031 return (pBase->
txrxMask >> 4) & 0xf;
3035 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1 3087 "eeprom address not in range\n");
3103 for (i = 0; i <
count / 2; i++) {
3119 "unable to read eeprom region at offset %d\n",
address);
3141 for (i = 0; i <
count; i++) {
3156 unsigned long value[4];
3163 *reference = (
value[0] & 0x001f) | ((
value[1] >> 2) & 0x0020);
3173 for (it = 0; it < dsize; it++) {
3201 if (
length > 0 && spot >= 0 && spot+
length <= mdataSize) {
3203 "Restore at %d: spot=%d offset=%d length=%d\n",
3209 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3228 if (
length != mdata_size) {
3230 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3236 "restored eeprom %d: uncompressed, length %d\n",
3240 if (reference == 0) {
3245 "can't find reference eeprom struct %d\n",
3249 memcpy(mptr, eep, mdata_size);
3252 "restore eeprom %d: block, reference %d, length %d\n",
3259 "unknown compression code %d\n",
code);
3271 return !(*
word == 0 || *
word == (
unsigned int)~0);
3292 for (i = 0; i < mdata_size / 2; i++,
data++)
3305 u8 *mptr,
int mdata_size)
3333 "Trying EEPROM access at Address 0x%04x\n", cptr);
3339 "Trying EEPROM access at Address 0x%04x\n", cptr);
3346 "Trying OTP access at Address 0x%04x\n", cptr);
3352 "Trying OTP access at Address 0x%04x\n", cptr);
3359 DBG2(
"ath9k: Found valid EEPROM data\n");
3361 for (it = 0; it <
MSTATE; it++) {
3371 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3376 "Skipping bad header\n");
3387 "checksum %x %x\n",
checksum, mchecksum);
3393 "skipping block with bad checksum\n");
3413 u8 *mptr = (
u8 *) &
ah->eeprom.ar9300_eep;
3425 return ah->eeprom.ar9300_eep.eepromVersion;
3520 if ((
ah->rxchainmask &
BIT(chain)) ||
3521 (
ah->txchainmask &
BIT(chain))) {
3540 regval |= ((
value >> 6) & 0x1) <<
3547 regval |= ((
value >> 7) & 0x1) <<
3553 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3583 if (!drive_strength)
3624 if (chain >= 0 && chain < 3) {
3652 if (chain >= 0 && chain < 3) {
3682 for (i = 0; i < 3; i++) {
3683 if (
ah->txchainmask &
BIT(i)) {
3700 while ((
unsigned int)pmu_set !=
REG_READ(
ah, pmu_reg)) {
3712 int internal_regulator =
3715 if (internal_regulator) {
3724 reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3725 (2 << 14) | (6 << 17) | (1 << 20) |
3726 (3 << 24) | (1 << 28);
3786 tuning_caps_param &= 0x7f;
3825 int lx = 0, ly = 0, lhave = 0;
3826 int hx = 0, hy = 0, hhave = 0;
3834 for (
ip = 0;
ip < np;
ip++) {
3839 if (!hhave ||
dx > (x - hx)) {
3848 if (!lhave ||
dx < (x - lx)) {
3876 u16 rateIndex,
u16 freq,
int is2GHz)
3899 for (i = 0; i < numPiers; i++) {
3900 freqArray[i] =
FBIN2FREQ(pFreqBin[i], is2GHz);
3901 targetPowerArray[i] = pEepromTargetPwr[i].
tPow2x[rateIndex];
3907 targetPowerArray, numPiers);
3912 u16 freq,
int is2GHz)
3935 for (i = 0; i < numPiers; i++) {
3936 freqArray[i] =
FBIN2FREQ(pFreqBin[i], is2GHz);
3937 targetPowerArray[i] = pEepromTargetPwr[i].
tPow2x[rateIndex];
3943 targetPowerArray, numPiers);
3948 u16 freq,
int is2GHz)
3971 for (i = 0; i < numPiers; i++) {
3972 freqArray[i] =
FBIN2FREQ(pFreqBin[i], is2GHz);
3973 targetPowerArray[i] = pEepromTargetPwr[i].
tPow2x[rateIndex];
3979 targetPowerArray, numPiers);
3996 for (i = 0; i < numPiers; i++) {
3997 freqArray[i] =
FBIN2FREQ(pFreqBin[i], 1);
3998 targetPowerArray[i] = pEepromTargetPwr[i].
tPow2x[rateIndex];
4004 targetPowerArray, numPiers);
4010 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 4126 u8 *targetPowerValT2)
4129 u8 ht40PowerIncForPdadc = 0;
4201 is2GHz) + ht40PowerIncForPdadc;
4205 is2GHz) + ht40PowerIncForPdadc;
4208 is2GHz) + ht40PowerIncForPdadc;
4211 is2GHz) + ht40PowerIncForPdadc;
4214 is2GHz) + ht40PowerIncForPdadc;
4217 is2GHz) + ht40PowerIncForPdadc;
4220 is2GHz) + ht40PowerIncForPdadc;
4223 is2GHz) + ht40PowerIncForPdadc;
4226 is2GHz) + ht40PowerIncForPdadc;
4229 is2GHz) + ht40PowerIncForPdadc;
4232 is2GHz) + ht40PowerIncForPdadc;
4235 is2GHz) + ht40PowerIncForPdadc;
4238 is2GHz) + ht40PowerIncForPdadc;
4241 is2GHz) + ht40PowerIncForPdadc;
4245 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4255 int *ptemperature,
int *pvoltage)
4264 "Invalid chain index, must be less than %d\n",
4272 "Invalid 5GHz cal pier index, must be less than %d\n",
4282 "Invalid 2GHz cal pier index, must be less than %d\n",
4292 *pfrequency =
FBIN2FREQ(*pCalPier, is2GHz);
4293 *pcorrection = pCalPierStruct->
refPower;
4294 *ptemperature = pCalPierStruct->
tempMeas;
4295 *pvoltage = pCalPierStruct->
voltMeas;
4303 int *voltage
__unused,
int *temperature)
4312 if (
ah->caps.tx_chainmask &
BIT(1))
4316 if (
ah->caps.tx_chainmask &
BIT(2))
4325 if (
ah->caps.tx_chainmask &
BIT(1))
4329 if (
ah->caps.tx_chainmask &
BIT(2))
4338 if (frequency < 4000)
4362 int ichain, ipier, npier;
4373 int pfrequency, pcorrection, ptemperature, pvoltage;
4375 mode = (frequency >= 4000);
4382 lfrequency[ichain] = 0;
4383 hfrequency[ichain] = 100000;
4387 for (ipier = 0; ipier < npier; ipier++) {
4389 &pfrequency, &pcorrection,
4390 &ptemperature, &pvoltage)) {
4391 fdiff = frequency - pfrequency;
4398 if (hfrequency[ichain] <= 0 ||
4399 hfrequency[ichain] >= 100000 ||
4401 (frequency - hfrequency[ichain])) {
4406 hfrequency[ichain] = pfrequency;
4407 hcorrection[ichain] =
4409 htemperature[ichain] =
4411 hvoltage[ichain] = pvoltage;
4415 if (lfrequency[ichain] <= 0
4417 (frequency - lfrequency[ichain])) {
4422 lfrequency[ichain] = pfrequency;
4423 lcorrection[ichain] =
4425 ltemperature[ichain] =
4427 lvoltage[ichain] = pvoltage;
4437 "ch=%d f=%d low=%d %d h=%d %d\n",
4438 ichain, frequency, lfrequency[ichain],
4439 lcorrection[ichain], hfrequency[ichain],
4440 hcorrection[ichain]);
4442 if (hfrequency[ichain] == lfrequency[ichain]) {
4443 correction[ichain] = lcorrection[ichain];
4444 voltage[ichain] = lvoltage[ichain];
4445 temperature[ichain] = ltemperature[ichain];
4448 else if (frequency - lfrequency[ichain] < 1000) {
4450 if (hfrequency[ichain] - frequency < 1000) {
4455 lcorrection[ichain],
4456 hcorrection[ichain]);
4461 ltemperature[ichain],
4462 htemperature[ichain]);
4472 correction[ichain] = lcorrection[ichain];
4473 temperature[ichain] = ltemperature[ichain];
4474 voltage[ichain] = lvoltage[ichain];
4478 else if (hfrequency[ichain] - frequency < 1000) {
4479 correction[ichain] = hcorrection[ichain];
4480 temperature[ichain] = htemperature[ichain];
4481 voltage[ichain] = hvoltage[ichain];
4483 correction[ichain] = 0;
4484 temperature[ichain] = 0;
4485 voltage[ichain] = 0;
4493 "for frequency=%d, calibration correction = %d %d %d\n",
4494 frequency, correction[0], correction[1], correction[2]);
4522 u8 *ctl_freqbin = is2GHz ?
4543 u16 freq,
int idx,
int is2GHz)
4546 u8 *ctl_freqbin = is2GHz ?
4549 u16 num_edges = is2GHz ?
4566 }
else if ((edge > 0) &&
4580 return twiceMaxEdgePower;
4585 u8 *pPwrArray,
u16 cfgCtl,
4586 u8 twiceAntennaReduction,
4587 u8 twiceMaxRegulatoryPower,
4593 static const u16 tpScaleReductionTable[5] = {
4598 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4599 static const u16 ctlModesFor11a[] = {
4602 static const u16 ctlModesFor11g[] = {
4607 const u16 *pCtlMode;
4612 u16 twiceMinEdgePower;
4623 twiceLargestAntenna = (
int16_t)
min((twiceAntennaReduction) -
4624 twiceLargestAntenna, 0);
4630 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4633 maxRegAllowedPower -=
4634 (tpScaleReductionTable[(regulatory->
tp_scale)] * 2);
4637 scaledPower =
min(powerLimit, maxRegAllowedPower);
4660 scaledPower =
max((
u16)0, scaledPower);
4671 pCtlMode = ctlModesFor11g;
4680 pCtlMode = ctlModesFor11a;
4694 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4695 int isHt40CtlMode = (pCtlMode[ctlMode] ==
CTL_5GHT40) ||
4705 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4706 ctlMode, numCtlModes, isHt40CtlMode,
4718 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4720 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4721 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4748 min(twiceMaxEdgePower,
4759 minCtlPower = (
u8)
min(twiceMaxEdgePower, scaledPower);
4762 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4763 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4764 scaledPower, minCtlPower);
4767 switch (pCtlMode[ctlMode]) {
4813 u8 mod_idx = mcs_idx % 8;
4816 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4818 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4823 u8 twiceAntennaReduction,
4824 u8 twiceMaxRegulatoryPower,
4832 unsigned int i = 0, paprd_scale_factor = 0;
4833 u8 pwr_idx, min_pwridx = 0;
4843 ah->paprd_ratemask =
4847 ah->paprd_ratemask_ht40 =
4855 if (!
ah->paprd_table_write_done) {
4856 memcpy(target_power_val_t2_eep, targetPowerValT2,
4857 sizeof(targetPowerValT2));
4858 for (i = 0; i < 24; i++) {
4860 if (
ah->paprd_ratemask & (1 << i)) {
4861 if (targetPowerValT2[pwr_idx] &&
4862 targetPowerValT2[pwr_idx] ==
4863 target_power_val_t2_eep[pwr_idx])
4864 targetPowerValT2[pwr_idx] -=
4869 memcpy(target_power_val_t2_eep, targetPowerValT2,
4870 sizeof(targetPowerValT2));
4874 targetPowerValT2, cfgCtl,
4875 twiceAntennaReduction,
4876 twiceMaxRegulatoryPower,
4881 if ((
ah->paprd_ratemask & (1 << i)) &&
4882 ((
unsigned int)
abs(targetPowerValT2[i] -
4883 target_power_val_t2_eep[i]) >
4884 paprd_scale_factor)) {
4885 ah->paprd_ratemask &= ~(1 << i);
4887 "paprd disabled for mcs %d\n", i);
4903 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4923 ah->txpower_limit = targetPowerValT2[i];
4941 ah->paprd_target_power = targetPowerValT2[i];
4986 else if (chan->
channel >= 5400)
#define AR9300_MAX_CHAINS
u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]
static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2)
#define AR9300_NUM_5G_CAL_PIERS
u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]
struct option_descriptor read[1]
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF
u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]
uint8_t checksum
Checksum.
static const struct ar9300_eeprom ar9300_default
#define AR_CH0_THERM_XPASHORT2GND
#define AR_SWITCH_TABLE_COM2_ALL
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]
static unsigned int unsigned int reg
#define ar5416_get_ntxchains(_txchainmask)
static const struct ar9300_eeprom ar9300_h116
#define AR_PHY_POWER_TX_RATE(_d)
u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]
static int interpolate(int x, int xa, int xb, int ya, int yb)
#define AR9300_EEPROM_SIZE
static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah __unused, u16 i __unused, int is2GHz __unused)
static int ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
#define AR_PHY_TPC_OLPC_GAIN_DELTA
static const struct ar9300_eeprom * ar9003_eeprom_struct_find_by_id(int id)
#define AR_RTC_REG_CONTROL1
#define AR_PHY_65NM_CH0_BIAS2
s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
static const struct ar9300_eeprom ar9300_h112
#define AR_CH0_TOP_XPABIASLVL
#define AR9300_NUM_2G_CCK_TARGET_POWERS
static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah __unused, struct ath9k_channel *chan __unused)
static const struct ar9300_eeprom ar9300_x113
#define CTL_EDGE_FLAGS(_ctl)
static int ar9003_hw_cal_pier_get(struct ath_hw *ah, int mode, int ipier, int ichain, int *pfrequency, int *pcorrection, int *ptemperature, int *pvoltage)
uint64_t address
Base address.
static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
static int ar9003_hw_power_control_override(struct ath_hw *ah, int frequency, int *correction, int *voltage __unused, int *temperature)
struct arbelprm_completion_with_error error
uint8_t size
Entry size (in 32-bit words)
#define AR9300_PWR_TABLE_OFFSET
#define SUB_NUM_CTL_MODES_AT_5G_40
static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
u8 xatten1DBLow[AR9300_MAX_CHAINS]
static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq)
#define REG_RMW(_ah, _reg, _set, _clr)
#define AR9300_NUM_5G_20_TARGET_POWERS
#define CTL(_tpower, _flag)
u8 xatten1MarginLow[AR9300_MAX_CHAINS]
#define AR_SREV_9485(_ah)
#define AR_SWITCH_TABLE_ALL
struct eepFlags opCapFlags
#define AR_PHY_SWITCH_CHAIN_1
static int ar9300_compress_decision(struct ath_hw *ah, int it, int code, int reference, u8 *mptr, u8 *word, int length, int mdata_size)
static int ar9300_eeprom_restore_internal(struct ath_hw *ah, u8 *mptr, int mdata_size)
struct cal_tgt_pow_legacy calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]
#define AR_PHY_TX_FORCED_GAIN
unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, struct ath9k_channel *chan)
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
#define AR_PHY_TPC_6_ERROR_EST_MODE
#define AR_RTC_REG_CONTROL0
#define AR9300_OTP_STATUS_VALID
static int ar9300_eeprom_read_byte(struct ath_common *common, int address, u8 *buffer)
u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]
#define AR9300_NUM_BAND_EDGES_5G
static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 *pPwrArray)
#define AR9300_PAPRD_SCALE_1
static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static const struct ar9300_eeprom ar9300_x112
static unsigned int code
Response code.
u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]
struct cal_tgt_pow_ht calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]
#define REG_RMW_FIELD(_a, _r, _f, _v)
#define AR9300_OTP_STATUS_TYPE
Dynamic memory allocation.
static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, u16 freq, int idx, int is2GHz)
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM
static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, int is2ghz)
static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
#define AR_PHY_SWITCH_COM
#define AR_PHY_EXT_ATTEN_CTL_2
u8 xatten1MarginHigh[AR9300_MAX_CHAINS]
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint32_t major
Major version.
uint32_t minor
Minor version.
#define AR9300_OTP_STATUS
#define AR9300_NUM_CTLS_5G
#define AR_PHY_SWITCH_COM_2
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN
#define AR_PHY_9485_ANT_DIV_LNA2
#define AR9300_EEP_BASE_DRIV_STRENGTH
#define AR9300_OTP_READ_DATA
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN
pseudo_bit_t value[0x00020]
#define AR5416_OPFLAGS_11A
#define __unused
Declare a variable or data structure as unused.
#define AR9300_BASE_ADDR_4K
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
const struct eeprom_ops eep_ar9300_ops
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah __unused)
#define AR_RTC_FORCE_SWREG_PRD
uint16_t count
Number of entries.
static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, struct ath9k_channel *chan)
u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]
#define AR_PHY_EXT_ATTEN_CTL_0
#define AR_SREV_9340(_ah)
static int ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, int base_addr)
struct cal_tgt_pow_ht calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]
#define EEPROM_DATA_LEN_9485
#define AR_CH0_XTAL_CAPOUTDAC
static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
#define ath9k_hw_use_flash(_ah)
#define AR_PHY_9485_ANT_DIV_LNA1
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB
static void(* free)(struct refcnt *refcnt))
static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, int is2ghz)
#define AR_PHY_TPC_19_ALPHA_THERM
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, int idx, unsigned int edge, u16 freq, int is2GHz)
void * zalloc(size_t size)
Allocate cleared memory.
static int is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
#define AR5416_BCHAN_UNUSED
static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
#define AR_CH0_THERM_XPABIASLVL_MSB
#define AR_CH0_TOP2_XPABIASLVL
static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
#define AR_PHY_EXT_ATTEN_CTL_1
struct hv_monitor_parameter param[4][32]
Parameters.
static int ar9300_check_header(void *data)
#define AR_FAST_DIV_ENABLE
u8 xatten1DBHigh[AR9300_MAX_CHAINS]
static int ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, int count)
static int ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, int count)
u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
IP4_t ip
Destination IP address.
u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_BaseExtension_1 base_ext1
static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
struct ar9300_modal_eep_header modalHeader5G
#define AR_PHY_CCK_DETECT
#define AR9300_PAPRD_SCALE_2
static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, int is2ghz)
#define AR9300_NUM_2G_20_TARGET_POWERS
static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, struct ath9k_channel *chan)
u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]
static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan)
struct ar9300_BaseExtension_2 base_ext2
struct ib_cm_common common
#define AR_PHY_TPC_OLPC_GAIN_DELTA_S
int(* check_eeprom)(struct ath_hw *hw)
#define REG_READ(_ah, _reg)
struct cal_tgt_pow_ht calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]
#define AR9300_NUM_BAND_EDGES_2G
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]
static const struct ar9300_eeprom * ar9300_eep_templates[]
struct cal_tgt_pow_legacy calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]
u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]
#define AR5416_OPFLAGS_11G
static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, int is2ghz)
static u16 ar9300_comp_cksum(u8 *data, int dsize)
#define AR_PHY_TPC_18_THERM_CAL_VALUE
static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah __unused)
#define SUB_NUM_CTL_MODES_AT_2G_40
u8 params_for_tuning_caps[2]
static int ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
#define AR_ANT_DIV_CTRL_ALL
static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, int is2ghz)
struct cal_tgt_pow_legacy calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]
s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
#define AR_PHY_9485_ANT_DIV_LNADIV
#define AR9300_BASE_ADDR_512
static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
uint8_t block[3][8]
DES-encrypted blocks.
int(* eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, int count)
#define AR_PHY_SWITCH_CHAIN_2
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
#define REG_WRITE(_ah, _reg, _val)
#define AR9300_NUM_2G_CAL_PIERS
static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, int idx, int edge, int is2GHz)
struct ena_aq_header header
Header.
#define REG_READ_FIELD(_a, _r, _f)
struct ar9300_cal_data_per_freq_op_loop calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]
static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]
uint8_t data[48]
Additional event data.
u8 * ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
#define AR_PHY_65NM_CH0_BIAS1
u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
struct ar9300_base_eep_hdr baseEepHeader
#define AR9300_NUM_CTLS_2G
uint16_t offset
Offset to command line.
static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
#define AR_PHY_SWITCH_CHAIN_0
#define AR9300_NUM_5G_40_TARGET_POWERS
static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, u8 *pPwrArray, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u16 powerLimit)
struct ar9300_cal_data_per_freq_op_loop calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]
static u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
#define AR_PHY_MC_GAIN_CTRL
#define AR9300_PAPRD_RATE_MASK
static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, int mdata_size)
#define AR9300_NUM_2G_40_TARGET_POWERS
#define AR_PHY_9485_ANT_DIV_LNADIV_S
struct cal_tgt_pow_ht calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]
#define DBG(...)
Print a debugging message.
static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, int *length, int *major, int *minor)
#define AR_ANT_DIV_CTRL_ALL_S
#define AR_SWITCH_TABLE_COM_ALL
#define CTL_EDGE_TPOWER(_ctl)
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF
#define NULL
NULL pointer (VOID *)
#define AR_PHY_65NM_CH0_BIAS4
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
#define AR_FAST_DIV_ENABLE_S
#define AR_CH0_XTAL_CAPINDAC
static int ar9300_eeprom_read_word(struct ath_common *common, int address, u8 *buffer)
static int ar9300_uncompress_block(struct ath_hw *ah __unused, u8 *mptr, int mdataSize, u8 *block, int size)
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB
static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, int is2ghz)
u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]
if(natsemi->flags &NATSEMI_64BIT) return 1
#define AR_PHY_TPC_6_ERROR_EST_MODE_S
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB