iPXE
Macros | Functions | Variables
ath9k_ar9003_phy.c File Reference
#include <ipxe/io.h>
#include "hw.h"
#include "ar9003_phy.h"

Go to the source code of this file.

Macros

#define AR_PHY_CH_MINCCA_PWR   0x1FF00000
 
#define AR_PHY_CH_MINCCA_PWR_S   20
 
#define AR_PHY_CH_EXT_MINCCA_PWR   0x01FF0000
 
#define AR_PHY_CH_EXT_MINCCA_PWR_S   16
 

Functions

 FILE_SECBOOT (FORBIDDEN)
 
static int ar9003_hw_set_channel (struct ath_hw *ah, struct ath9k_channel *chan)
 ar9003_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan: More...
 
static void ar9003_hw_spur_mitigate_mrc_cck (struct ath_hw *ah, struct ath9k_channel *chan)
 ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency @ah: atheros hardware structure @chan: More...
 
static void ar9003_hw_spur_ofdm_clear (struct ath_hw *ah)
 
static void ar9003_hw_spur_ofdm (struct ath_hw *ah, int freq_offset, int spur_freq_sd, int spur_delta_phase, int spur_subchannel_sd)
 
static void ar9003_hw_spur_ofdm_work (struct ath_hw *ah, struct ath9k_channel *chan, int freq_offset)
 
static void ar9003_hw_spur_mitigate_ofdm (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ar9003_hw_spur_mitigate (struct ath_hw *ah, struct ath9k_channel *chan)
 
static u32 ar9003_hw_compute_pll_control (struct ath_hw *ah __unused, struct ath9k_channel *chan)
 
static void ar9003_hw_set_channel_regs (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ar9003_hw_init_bb (struct ath_hw *ah, struct ath9k_channel *chan)
 
void ar9003_hw_set_chain_masks (struct ath_hw *ah, u8 rx, u8 tx)
 
static void ar9003_hw_override_ini (struct ath_hw *ah)
 
static void ar9003_hw_prog_ini (struct ath_hw *ah, struct ar5416IniArray *iniArr, int column)
 
static int ar9003_hw_process_ini (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ar9003_hw_set_rfmode (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ar9003_hw_mark_phy_inactive (struct ath_hw *ah)
 
static void ar9003_hw_set_delta_slope (struct ath_hw *ah, struct ath9k_channel *chan)
 
static int ar9003_hw_rfbus_req (struct ath_hw *ah)
 
static void ar9003_hw_rfbus_done (struct ath_hw *ah)
 
static void ar9003_hw_set_diversity (struct ath_hw *ah, int value)
 
static int ar9003_hw_ani_control (struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
 
static void ar9003_hw_do_getnf (struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
 
static void ar9003_hw_set_nf_limits (struct ath_hw *ah)
 
static void ar9003_hw_ani_cache_ini_regs (struct ath_hw *ah)
 
static void ar9003_hw_set_radar_params (struct ath_hw *ah, struct ath_hw_radar_conf *conf)
 
static void ar9003_hw_set_radar_conf (struct ath_hw *ah)
 
static void ar9003_hw_antdiv_comb_conf_get (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
 
static void ar9003_hw_antdiv_comb_conf_set (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
 
void ar9003_hw_attach_phy_ops (struct ath_hw *ah)
 
void ar9003_hw_disable_phy_restart (struct ath_hw *ah)
 

Variables

static const int firstep_table []
 
static const int cycpwrThr1_table []
 
static const int m1ThreshLow_off = 127
 
static const int m2ThreshLow_off = 127
 
static const int m1Thresh_off = 127
 
static const int m2Thresh_off = 127
 
static const int m2CountThr_off = 31
 
static const int m2CountThrLow_off = 63
 
static const int m1ThreshLowExt_off = 127
 
static const int m2ThreshLowExt_off = 127
 
static const int m1ThreshExt_off = 127
 
static const int m2ThreshExt_off = 127
 

Macro Definition Documentation

◆ AR_PHY_CH_MINCCA_PWR

#define AR_PHY_CH_MINCCA_PWR   0x1FF00000

◆ AR_PHY_CH_MINCCA_PWR_S

#define AR_PHY_CH_MINCCA_PWR_S   20

◆ AR_PHY_CH_EXT_MINCCA_PWR

#define AR_PHY_CH_EXT_MINCCA_PWR   0x01FF0000

◆ AR_PHY_CH_EXT_MINCCA_PWR_S

#define AR_PHY_CH_EXT_MINCCA_PWR_S   16

Function Documentation

◆ FILE_SECBOOT()

FILE_SECBOOT ( FORBIDDEN  )

◆ ar9003_hw_set_channel()

static int ar9003_hw_set_channel ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

ar9003_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan:

This is the function to change channel on single-chip devices, that is all devices after ar9280.

This function takes the channel value in MHz and sets hardware channel value. Assumes writes have been enabled to analog bus.

Actual Expression,

For 2GHz channel, Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) (freq_ref = 40MHz)

For 5GHz channel, Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) (freq_ref = 40MHz/(24>>amodeRefSel))

For 5GHz channels which are 5MHz spaced, Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) (freq_ref = 40MHz)

Definition at line 74 of file ath9k_ar9003_phy.c.

75 {
76  u16 bMode, fracMode = 0, aModeRefSel = 0;
77  u32 freq, channelSel = 0, reg32 = 0;
78  struct chan_centers centers;
79  int loadSynthChannel;
80 
81  ath9k_hw_get_channel_centers(ah, chan, &centers);
82  freq = centers.synth_center;
83 
84  if (freq < 4800) { /* 2 GHz, fractional mode */
85  if (AR_SREV_9485(ah)) {
86  u32 chan_frac;
87 
88  /*
89  * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
90  * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
91  * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
92  */
93  channelSel = (freq * 4) / 120;
94  chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
95  channelSel = (channelSel << 17) | chan_frac;
96  } else if (AR_SREV_9340(ah)) {
97  if (ah->is_clk_25mhz) {
98  u32 chan_frac;
99 
100  channelSel = (freq * 2) / 75;
101  chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102  channelSel = (channelSel << 17) | chan_frac;
103  } else
104  channelSel = CHANSEL_2G(freq) >> 1;
105  } else
106  channelSel = CHANSEL_2G(freq);
107  /* Set to 2G mode */
108  bMode = 1;
109  } else {
110  if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
111  u32 chan_frac;
112 
113  channelSel = (freq * 2) / 75;
114  chan_frac = ((freq % 75) * 0x20000) / 75;
115  channelSel = (channelSel << 17) | chan_frac;
116  } else {
117  channelSel = CHANSEL_5G(freq);
118  /* Doubler is ON, so, divide channelSel by 2. */
119  channelSel >>= 1;
120  }
121  /* Set to 5G mode */
122  bMode = 0;
123  }
124 
125  /* Enable fractional mode for all channels */
126  fracMode = 1;
127  aModeRefSel = 0;
128  loadSynthChannel = 0;
129 
130  reg32 = (bMode << 29);
131  REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
132 
133  /* Enable Long shift Select for Synthesizer */
134  REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
135  AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
136 
137  /* Program Synth. setting */
138  reg32 = (channelSel << 2) | (fracMode << 30) |
139  (aModeRefSel << 28) | (loadSynthChannel << 31);
140  REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
141 
142  /* Toggle Load Synth channel bit */
143  loadSynthChannel = 1;
144  reg32 = (channelSel << 2) | (fracMode << 30) |
145  (aModeRefSel << 28) | (loadSynthChannel << 31);
146  REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
147 
148  ah->curchan = chan;
149  ah->curchan_rad_index = -1;
150 
151  return 0;
152 }
u16
uint16_t u16
Definition: stdint.h:22
CHANSEL_5G
#define CHANSEL_5G(_freq)
Definition: phy.h:25
AR_SREV_9485
#define AR_SREV_9485(_ah)
Definition: reg.h:868
CHANSEL_2G
#define CHANSEL_2G(_freq)
Definition: phy.h:24
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
AR_PHY_SYNTH4_LONG_SHIFT_SELECT
#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT
Definition: ar9003_phy.h:605
AR_PHY_65NM_CH0_SYNTH7
#define AR_PHY_65NM_CH0_SYNTH7
Definition: ar9003_phy.h:607
AR_PHY_65NM_CH0_SYNTH4
#define AR_PHY_65NM_CH0_SYNTH4
Definition: ar9003_phy.h:604
AR_SREV_9340
#define AR_SREV_9340(_ah)
Definition: reg.h:879
chan_centers
Definition: hw.h:422
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ath9k_hw_get_channel_centers
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:191
ah
uint8_t ah
Definition: registers.h:85
u32
uint32_t u32
Definition: stdint.h:24
AR_PHY_SYNTH_CONTROL
#define AR_PHY_SYNTH_CONTROL
Definition: ar9002_phy.h:159

References ah, AR_PHY_65NM_CH0_SYNTH4, AR_PHY_65NM_CH0_SYNTH7, AR_PHY_SYNTH4_LONG_SHIFT_SELECT, AR_PHY_SYNTH_CONTROL, AR_SREV_9340, AR_SREV_9485, ath9k_hw_get_channel_centers(), CHANSEL_2G, CHANSEL_5G, REG_RMW_FIELD, REG_WRITE, and chan_centers::synth_center.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_spur_mitigate_mrc_cck()

static void ar9003_hw_spur_mitigate_mrc_cck ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency @ah: atheros hardware structure @chan:

For single-chip solutions. Converts to baseband spur frequency given the input channel frequency and compute register settings below.

Spur mitigation for MRC CCK

Definition at line 164 of file ath9k_ar9003_phy.c.

166 {
167  static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
168  int cur_bb_spur, negative = 0, cck_spur_freq;
169  int i;
170  int range, max_spur_cnts, synth_freq;
171  u8 *spur_fbin_ptr = NULL;
172 
173  /*
174  * Need to verify range +/- 10 MHz in control channel, otherwise spur
175  * is out-of-band and can be ignored.
176  */
177 
178  if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
179  spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
180  IS_CHAN_2GHZ(chan));
181  if (spur_fbin_ptr[0] == 0) /* No spur */
182  return;
183  max_spur_cnts = 5;
184  if (IS_CHAN_HT40(chan)) {
185  range = 19;
186  if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
187  AR_PHY_GC_DYN2040_PRI_CH) == 0)
188  synth_freq = chan->channel + 10;
189  else
190  synth_freq = chan->channel - 10;
191  } else {
192  range = 10;
193  synth_freq = chan->channel;
194  }
195  } else {
196  range = 10;
197  max_spur_cnts = 4;
198  synth_freq = chan->channel;
199  }
200 
201  for (i = 0; i < max_spur_cnts; i++) {
202  negative = 0;
203  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
204  cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
205  IS_CHAN_2GHZ(chan)) - synth_freq;
206  else
207  cur_bb_spur = spur_freq[i] - synth_freq;
208 
209  if (cur_bb_spur < 0) {
210  negative = 1;
211  cur_bb_spur = -cur_bb_spur;
212  }
213  if (cur_bb_spur < range) {
214  cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
215 
216  if (negative == 1)
217  cck_spur_freq = -cck_spur_freq;
218 
219  cck_spur_freq = cck_spur_freq & 0xfffff;
220 
221  REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
222  AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
223  REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
224  AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
225  REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
226  AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
227  0x2);
228  REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
229  AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
230  0x1);
231  REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
232  AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
233  cck_spur_freq);
234 
235  return;
236  }
237  }
238 
239  REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
240  AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
241  REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242  AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
243  REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
244  AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
245 }
ath9k_channel::channel
u16 channel
Definition: hw.h:350
AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE
#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE
Definition: ar9003_phy.h:315
range
struct pci_range range
PCI bus:dev.fn address range.
Definition: pcicloud.c:40
AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT
#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT
Definition: ar9003_phy.h:317
AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR
#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR
Definition: ar9003_phy.h:313
AR_PHY_GEN_CTRL
#define AR_PHY_GEN_CTRL
Definition: ar9003_phy.h:428
IS_CHAN_2GHZ
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:362
AR_SREV_9485
#define AR_SREV_9485(_ah)
Definition: reg.h:868
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
AR_PHY_AGC_CONTROL
#define AR_PHY_AGC_CONTROL
Definition: reg.h:1910
AR_SREV_9340
#define AR_SREV_9340(_ah)
Definition: reg.h:879
ar9003_get_spur_chan_ptr
u8 * ar9003_get_spur_chan_ptr(struct ath_hw *ah, int is_2ghz)
Definition: ath9k_ar9003_eeprom.c:4966
FBIN2FREQ
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:49
AR_PHY_GC_DYN2040_PRI_CH
#define AR_PHY_GC_DYN2040_PRI_CH
Definition: ar9003_phy.h:680
AR_PHY_CCK_SPUR_MIT
#define AR_PHY_CCK_SPUR_MIT
Definition: ar9003_phy.h:312
AR_PHY_AGC_CONTROL_YCOK_MAX
#define AR_PHY_AGC_CONTROL_YCOK_MAX
Definition: reg.h:1919
REG_READ_FIELD
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:106
AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ
#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ
Definition: ar9003_phy.h:319
ah
uint8_t ah
Definition: registers.h:85
IS_CHAN_HT40
#define IS_CHAN_HT40(_c)
Definition: hw.h:373
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
u8
uint8_t u8
Definition: stdint.h:20
u32
uint32_t u32
Definition: stdint.h:24

References ah, ar9003_get_spur_chan_ptr(), AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_YCOK_MAX, AR_PHY_CCK_SPUR_MIT, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GEN_CTRL, AR_SREV_9340, AR_SREV_9485, ath9k_channel::channel, FBIN2FREQ, IS_CHAN_2GHZ, IS_CHAN_HT40, NULL, range, REG_READ_FIELD, and REG_RMW_FIELD.

Referenced by ar9003_hw_spur_mitigate().

◆ ar9003_hw_spur_ofdm_clear()

static void ar9003_hw_spur_ofdm_clear ( struct ath_hw *  ah)
static

Definition at line 248 of file ath9k_ar9003_phy.c.

249 {
250  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
251  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
252  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
253  AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
254  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
255  AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
256  REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
257  AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
258  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
259  AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
260  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
261  AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
262  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
263  AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
264  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
265  AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
266  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
267  AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
268 
269  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
270  AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
271  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
272  AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
273  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
274  AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
275  REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
276  AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
277  REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
278  AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
279  REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
280  AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
281  REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
282  AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
283  REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
284  AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
285  REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
286  AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
287  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
288  AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
289 }
AR_PHY_TIMING4_ENABLE_CHAN_MASK
#define AR_PHY_TIMING4_ENABLE_CHAN_MASK
Definition: ar9003_phy.h:116
AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A
Definition: ar9003_phy.h:464
AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A
Definition: ar9003_phy.h:466
AR_PHY_TIMING11_SPUR_FREQ_SD
#define AR_PHY_TIMING11_SPUR_FREQ_SD
Definition: ar9003_phy.h:38
AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A
Definition: ar9003_phy.h:230
AR_PHY_SPUR_REG_ENABLE_MASK_PPM
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM
Definition: ar9002_phy.h:523
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
AR_PHY_TIMING4_ENABLE_SPUR_RSSI
#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI
Definition: ar9003_phy.h:121
AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR
Definition: ar9003_phy.h:47
AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD
#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD
Definition: ar9003_phy.h:147
AR_PHY_PILOT_SPUR_MASK
#define AR_PHY_PILOT_SPUR_MASK
Definition: ar9003_phy.h:221
AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A
Definition: ar9003_phy.h:235
AR_PHY_SPUR_REG_MASK_RATE_CNTL
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL
Definition: ar9002_phy.h:520
AR_PHY_TIMING11
#define AR_PHY_TIMING11
Definition: ar9002_phy.h:296
AR_PHY_TIMING11_SPUR_DELTA_PHASE
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE
Definition: ar9002_phy.h:297
AR_PHY_CHAN_SPUR_MASK
#define AR_PHY_CHAN_SPUR_MASK
Definition: ar9003_phy.h:222
AR_PHY_SPUR_REG
#define AR_PHY_SPUR_REG
Definition: ar9002_phy.h:518
AR_PHY_TIMING4_ENABLE_PILOT_MASK
#define AR_PHY_TIMING4_ENABLE_PILOT_MASK
Definition: ar9003_phy.h:114
AR_PHY_TIMING4_ENABLE_SPUR_FILTER
#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER
Definition: ar9003_phy.h:119
AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A
Definition: ar9003_phy.h:233
AR_PHY_SFCORR_EXT
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:345
AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI
#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI
Definition: ar9003_phy.h:57
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT
#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT
Definition: ar9003_phy.h:50
AR_PHY_TIMING4
#define AR_PHY_TIMING4
Definition: ar9003_phy.h:30
AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC
Definition: ar9003_phy.h:44
AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A
Definition: ar9003_phy.h:228
AR_PHY_SPUR_MASK_A
#define AR_PHY_SPUR_MASK_A
Definition: ar9003_phy.h:431

References ah, AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, AR_PHY_SPUR_REG_MASK_RATE_CNTL, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, AR_PHY_TIMING11_SPUR_FREQ_SD, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, AR_PHY_TIMING4_ENABLE_PILOT_MASK, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, and REG_RMW_FIELD.

Referenced by ar9003_hw_spur_mitigate_ofdm().

◆ ar9003_hw_spur_ofdm()

static void ar9003_hw_spur_ofdm ( struct ath_hw *  ah,
int  freq_offset,
int  spur_freq_sd,
int  spur_delta_phase,
int  spur_subchannel_sd 
)
static

Definition at line 291 of file ath9k_ar9003_phy.c.

296 {
297  int mask_index = 0;
298 
299  /* OFDM Spur mitigation */
300  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
301  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
302  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
303  AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
304  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
305  AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
306  REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
307  AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
308  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
309  AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
310  REG_RMW_FIELD(ah, AR_PHY_TIMING11,
311  AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
312  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
313  AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
314  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
315  AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
316  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
317  AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
318 
319  if (REG_READ_FIELD(ah, AR_PHY_MODE,
320  AR_PHY_MODE_DYNAMIC) == 0x1)
321  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
322  AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
323 
324  mask_index = (freq_offset << 4) / 5;
325  if (mask_index < 0)
326  mask_index = mask_index - 1;
327 
328  mask_index = mask_index & 0x7f;
329 
330  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
331  AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
332  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
333  AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
334  REG_RMW_FIELD(ah, AR_PHY_TIMING4,
335  AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
336  REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
337  AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
338  REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
339  AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
340  REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
341  AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
342  REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
343  AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
344  REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
345  AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
346  REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
347  AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
348  REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
349  AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
350 }
AR_PHY_TIMING4_ENABLE_CHAN_MASK
#define AR_PHY_TIMING4_ENABLE_CHAN_MASK
Definition: ar9003_phy.h:116
AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A
Definition: ar9003_phy.h:464
AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A
#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A
Definition: ar9003_phy.h:466
AR_PHY_TIMING11_SPUR_FREQ_SD
#define AR_PHY_TIMING11_SPUR_FREQ_SD
Definition: ar9003_phy.h:38
AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A
Definition: ar9003_phy.h:230
AR_PHY_SPUR_REG_ENABLE_MASK_PPM
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM
Definition: ar9002_phy.h:523
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
AR_PHY_TIMING4_ENABLE_SPUR_RSSI
#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI
Definition: ar9003_phy.h:121
AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR
Definition: ar9003_phy.h:47
AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD
#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD
Definition: ar9003_phy.h:147
AR_PHY_PILOT_SPUR_MASK
#define AR_PHY_PILOT_SPUR_MASK
Definition: ar9003_phy.h:221
AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A
Definition: ar9003_phy.h:235
AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
Definition: ar9002_phy.h:527
AR_PHY_SPUR_REG_MASK_RATE_CNTL
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL
Definition: ar9002_phy.h:520
AR_PHY_TIMING11
#define AR_PHY_TIMING11
Definition: ar9002_phy.h:296
AR_PHY_TIMING11_SPUR_DELTA_PHASE
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE
Definition: ar9002_phy.h:297
AR_PHY_CHAN_SPUR_MASK
#define AR_PHY_CHAN_SPUR_MASK
Definition: ar9003_phy.h:222
AR_PHY_SPUR_REG
#define AR_PHY_SPUR_REG
Definition: ar9002_phy.h:518
AR_PHY_TIMING4_ENABLE_PILOT_MASK
#define AR_PHY_TIMING4_ENABLE_PILOT_MASK
Definition: ar9003_phy.h:114
AR_PHY_TIMING4_ENABLE_SPUR_FILTER
#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER
Definition: ar9003_phy.h:119
AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A
#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A
Definition: ar9003_phy.h:233
AR_PHY_SFCORR_EXT
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:345
AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI
#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI
Definition: ar9003_phy.h:57
REG_READ_FIELD
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:106
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT
#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT
Definition: ar9003_phy.h:50
AR_PHY_TIMING4
#define AR_PHY_TIMING4
Definition: ar9003_phy.h:30
AR_PHY_MODE
#define AR_PHY_MODE
Definition: ar9002_phy.h:397
AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC
#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC
Definition: ar9003_phy.h:44
AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A
#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A
Definition: ar9003_phy.h:228
AR_PHY_MODE_DYNAMIC
#define AR_PHY_MODE_DYNAMIC
Definition: ar9002_phy.h:402
AR_PHY_SPUR_MASK_A
#define AR_PHY_SPUR_MASK_A
Definition: ar9003_phy.h:431

References ah, AR_PHY_CHAN_SPUR_MASK, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC, AR_PHY_PILOT_SPUR_MASK, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, AR_PHY_SPUR_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, AR_PHY_SPUR_REG_MASK_RATE_CNTL, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, AR_PHY_TIMING11_SPUR_FREQ_SD, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, AR_PHY_TIMING4_ENABLE_PILOT_MASK, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, REG_READ_FIELD, and REG_RMW_FIELD.

Referenced by ar9003_hw_spur_ofdm_work().

◆ ar9003_hw_spur_ofdm_work()

static void ar9003_hw_spur_ofdm_work ( struct ath_hw *  ah,
struct ath9k_channel *  chan,
int  freq_offset 
)
static

Definition at line 352 of file ath9k_ar9003_phy.c.

355 {
356  int spur_freq_sd = 0;
357  int spur_subchannel_sd = 0;
358  int spur_delta_phase = 0;
359 
360  if (IS_CHAN_HT40(chan)) {
361  if (freq_offset < 0) {
362  if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
363  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
364  spur_subchannel_sd = 1;
365  else
366  spur_subchannel_sd = 0;
367 
368  spur_freq_sd = ((freq_offset + 10) << 9) / 11;
369 
370  } else {
371  if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
372  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
373  spur_subchannel_sd = 0;
374  else
375  spur_subchannel_sd = 1;
376 
377  spur_freq_sd = ((freq_offset - 10) << 9) / 11;
378 
379  }
380 
381  spur_delta_phase = (freq_offset << 17) / 5;
382 
383  } else {
384  spur_subchannel_sd = 0;
385  spur_freq_sd = (freq_offset << 9) /11;
386  spur_delta_phase = (freq_offset << 18) / 5;
387  }
388 
389  spur_freq_sd = spur_freq_sd & 0x3ff;
390  spur_delta_phase = spur_delta_phase & 0xfffff;
391 
392  ar9003_hw_spur_ofdm(ah,
393  freq_offset,
394  spur_freq_sd,
395  spur_delta_phase,
396  spur_subchannel_sd);
397 }
AR_PHY_GEN_CTRL
#define AR_PHY_GEN_CTRL
Definition: ar9003_phy.h:428
ar9003_hw_spur_ofdm
static void ar9003_hw_spur_ofdm(struct ath_hw *ah, int freq_offset, int spur_freq_sd, int spur_delta_phase, int spur_subchannel_sd)
Definition: ath9k_ar9003_phy.c:291
AR_PHY_GC_DYN2040_PRI_CH
#define AR_PHY_GC_DYN2040_PRI_CH
Definition: ar9003_phy.h:680
REG_READ_FIELD
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:106
ah
uint8_t ah
Definition: registers.h:85
IS_CHAN_HT40
#define IS_CHAN_HT40(_c)
Definition: hw.h:373

References ah, ar9003_hw_spur_ofdm(), AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GEN_CTRL, IS_CHAN_HT40, and REG_READ_FIELD.

Referenced by ar9003_hw_spur_mitigate_ofdm().

◆ ar9003_hw_spur_mitigate_ofdm()

static void ar9003_hw_spur_mitigate_ofdm ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 400 of file ath9k_ar9003_phy.c.

402 {
403  int synth_freq;
404  int range = 10;
405  int freq_offset = 0;
406  int mode;
407  u8* spurChansPtr;
408  unsigned int i;
409  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
410 
411  if (IS_CHAN_5GHZ(chan)) {
412  spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
413  mode = 0;
414  }
415  else {
416  spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
417  mode = 1;
418  }
419 
420  if (spurChansPtr[0] == 0)
421  return; /* No spur in the mode */
422 
423  if (IS_CHAN_HT40(chan)) {
424  range = 19;
425  if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427  synth_freq = chan->channel - 10;
428  else
429  synth_freq = chan->channel + 10;
430  } else {
431  range = 10;
432  synth_freq = chan->channel;
433  }
434 
435  ar9003_hw_spur_ofdm_clear(ah);
436 
437  for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
438  freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
439  if (abs(freq_offset) < range) {
440  ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
441  break;
442  }
443  }
444 }
ar9300_modal_eep_header::spurChans
u8 spurChans[AR_EEPROM_MODAL_SPURS]
Definition: ar9003_eeprom.h:220
ath9k_channel::channel
u16 channel
Definition: hw.h:350
range
struct pci_range range
PCI bus:dev.fn address range.
Definition: pcicloud.c:40
AR_PHY_GEN_CTRL
#define AR_PHY_GEN_CTRL
Definition: ar9003_phy.h:428
AR_EEPROM_MODAL_SPURS
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:26
mode
uint16_t mode
Acceleration mode.
Definition: ena.h:26
ar9003_hw_spur_ofdm_work
static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, struct ath9k_channel *chan, int freq_offset)
Definition: ath9k_ar9003_phy.c:352
abs
#define abs(x)
Definition: ath.h:46
ar9300_eeprom
Definition: ar9003_eeprom.h:287
FBIN2FREQ
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:49
ar9300_eeprom::modalHeader2G
struct ar9300_modal_eep_header modalHeader2G
Definition: ar9003_eeprom.h:295
ar9300_eeprom::modalHeader5G
struct ar9300_modal_eep_header modalHeader5G
Definition: ar9003_eeprom.h:315
AR_PHY_GC_DYN2040_PRI_CH
#define AR_PHY_GC_DYN2040_PRI_CH
Definition: ar9003_phy.h:680
IS_CHAN_5GHZ
#define IS_CHAN_5GHZ(_c)
Definition: hw.h:361
ar9003_hw_spur_ofdm_clear
static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:248
REG_READ_FIELD
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:106
ah
uint8_t ah
Definition: registers.h:85
IS_CHAN_HT40
#define IS_CHAN_HT40(_c)
Definition: hw.h:373
u8
uint8_t u8
Definition: stdint.h:20

References abs, ah, ar9003_hw_spur_ofdm_clear(), ar9003_hw_spur_ofdm_work(), AR_EEPROM_MODAL_SPURS, AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GEN_CTRL, ath9k_channel::channel, FBIN2FREQ, IS_CHAN_5GHZ, IS_CHAN_HT40, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, mode, range, REG_READ_FIELD, and ar9300_modal_eep_header::spurChans.

Referenced by ar9003_hw_spur_mitigate().

◆ ar9003_hw_spur_mitigate()

static void ar9003_hw_spur_mitigate ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 446 of file ath9k_ar9003_phy.c.

448 {
449  ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
450  ar9003_hw_spur_mitigate_ofdm(ah, chan);
451 }
ar9003_hw_spur_mitigate_mrc_cck
static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, struct ath9k_channel *chan)
ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency @ah: atheros hardware structure @ch...
Definition: ath9k_ar9003_phy.c:164
ar9003_hw_spur_mitigate_ofdm
static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:400
ah
uint8_t ah
Definition: registers.h:85

References ah, ar9003_hw_spur_mitigate_mrc_cck(), and ar9003_hw_spur_mitigate_ofdm().

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_compute_pll_control()

static u32 ar9003_hw_compute_pll_control ( struct ath_hw *ah  __unused,
struct ath9k_channel *  chan 
)
static

Definition at line 453 of file ath9k_ar9003_phy.c.

455 {
456  u32 pll;
457 
458  pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
459 
460  if (chan && IS_CHAN_HALF_RATE(chan))
461  pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
462  else if (chan && IS_CHAN_QUARTER_RATE(chan))
463  pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
464 
465  pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
466 
467  return pll;
468 }
AR_RTC_9300_PLL_REFDIV
#define AR_RTC_9300_PLL_REFDIV
Definition: reg.h:1146
IS_CHAN_HALF_RATE
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:363
AR_RTC_9300_PLL_CLKSEL
#define AR_RTC_9300_PLL_CLKSEL
Definition: reg.h:1148
IS_CHAN_QUARTER_RATE
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:364
SM
#define SM(_v, _f)
Definition: hw.h:102
AR_RTC_9300_PLL_DIV
#define AR_RTC_9300_PLL_DIV
Definition: reg.h:1144
u32
uint32_t u32
Definition: stdint.h:24

References AR_RTC_9300_PLL_CLKSEL, AR_RTC_9300_PLL_DIV, AR_RTC_9300_PLL_REFDIV, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, and SM.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_channel_regs()

static void ar9003_hw_set_channel_regs ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 470 of file ath9k_ar9003_phy.c.

472 {
473  u32 phymode;
474  u32 enableDacFifo = 0;
475 
476  enableDacFifo =
477  (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
478 
479  /* Enable 11n HT, 20 MHz */
480  phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
481  AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
482 
483  /* Configure baseband for dynamic 20/40 operation */
484  if (IS_CHAN_HT40(chan)) {
485  phymode |= AR_PHY_GC_DYN2040_EN;
486  /* Configure control (primary) channel at +-10MHz */
487  if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
488  (chan->chanmode == CHANNEL_G_HT40PLUS))
489  phymode |= AR_PHY_GC_DYN2040_PRI_CH;
490 
491  }
492 
493  /* make sure we preserve INI settings */
494  phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
495  /* turn off Green Field detection for STA for now */
496  phymode &= ~AR_PHY_GC_GF_DETECT_EN;
497 
498  REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
499 
500  /* Configure MAC for 20/40 operation */
501  ath9k_hw_set11nmac2040(ah);
502 
503  /* global transmit timeout (25 TUs default)*/
504  REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
505  /* carrier sense timeout */
506  REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
507 }
AR_PHY_GC_SHORT_GI_40
#define AR_PHY_GC_SHORT_GI_40
Definition: ar9003_phy.h:684
ath9k_channel::chanmode
u32 chanmode
Definition: hw.h:352
AR_GTXTO_TIMEOUT_LIMIT_S
#define AR_GTXTO_TIMEOUT_LIMIT_S
Definition: reg.h:156
AR_PHY_GC_ENABLE_DAC_FIFO
#define AR_PHY_GC_ENABLE_DAC_FIFO
Definition: ar9003_phy.h:688
AR_PHY_GEN_CTRL
#define AR_PHY_GEN_CTRL
Definition: ar9003_phy.h:428
AR_PHY_GC_DYN2040_EN
#define AR_PHY_GC_DYN2040_EN
Definition: ar9003_phy.h:678
AR_CST
#define AR_CST
Definition: reg.h:164
AR_PHY_GC_SINGLE_HT_LTF1
#define AR_PHY_GC_SINGLE_HT_LTF1
Definition: ar9003_phy.h:686
AR_PHY_GC_WALSH
#define AR_PHY_GC_WALSH
Definition: ar9003_phy.h:685
AR_PHY_GC_DYN2040_PRI_CH
#define AR_PHY_GC_DYN2040_PRI_CH
Definition: ar9003_phy.h:680
AR_PHY_GC_HT_EN
#define AR_PHY_GC_HT_EN
Definition: ar9003_phy.h:683
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
AR_CST_TIMEOUT_LIMIT_S
#define AR_CST_TIMEOUT_LIMIT_S
Definition: reg.h:167
AR_GTXTO
#define AR_GTXTO
Definition: reg.h:153
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ath9k_hw_set11nmac2040
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Definition: ath9k_hw.c:1975
CHANNEL_A_HT40PLUS
#define CHANNEL_A_HT40PLUS
Definition: hw.h:322
ah
uint8_t ah
Definition: registers.h:85
IS_CHAN_HT40
#define IS_CHAN_HT40(_c)
Definition: hw.h:373
CHANNEL_G_HT40PLUS
#define CHANNEL_G_HT40PLUS
Definition: hw.h:320
u32
uint32_t u32
Definition: stdint.h:24
AR_PHY_GC_GF_DETECT_EN
#define AR_PHY_GC_GF_DETECT_EN
Definition: ar9003_phy.h:687

References ah, AR_CST, AR_CST_TIMEOUT_LIMIT_S, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT_S, AR_PHY_GC_DYN2040_EN, AR_PHY_GC_DYN2040_PRI_CH, AR_PHY_GC_ENABLE_DAC_FIFO, AR_PHY_GC_GF_DETECT_EN, AR_PHY_GC_HT_EN, AR_PHY_GC_SHORT_GI_40, AR_PHY_GC_SINGLE_HT_LTF1, AR_PHY_GC_WALSH, AR_PHY_GEN_CTRL, ath9k_hw_set11nmac2040(), ath9k_channel::chanmode, CHANNEL_A_HT40PLUS, CHANNEL_G_HT40PLUS, IS_CHAN_HT40, REG_READ, and REG_WRITE.

Referenced by ar9003_hw_attach_phy_ops(), and ar9003_hw_process_ini().

◆ ar9003_hw_init_bb()

static void ar9003_hw_init_bb ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 509 of file ath9k_ar9003_phy.c.

511 {
512  u32 synthDelay;
513 
514  /*
515  * Wait for the frequency synth to settle (synth goes on
516  * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
517  * Value is in 100ns increments.
518  */
519  synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
520  if (IS_CHAN_B(chan))
521  synthDelay = (4 * synthDelay) / 22;
522  else
523  synthDelay /= 10;
524 
525  /* Activate the PHY (includes baseband activate + synthesizer on) */
526  REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
527 
528  /*
529  * There is an issue if the AP starts the calibration before
530  * the base band timeout completes. This could result in the
531  * rx_clear false triggering. As a workaround we add delay an
532  * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
533  * does not happen.
534  */
535  udelay(synthDelay + BASE_ACTIVATE_DELAY);
536 }
BASE_ACTIVATE_DELAY
#define BASE_ACTIVATE_DELAY
Definition: hw.h:134
IS_CHAN_B
#define IS_CHAN_B(_c)
Definition: ath5k.h:660
AR_PHY_ACTIVE_EN
#define AR_PHY_ACTIVE_EN
Definition: ar9002_phy.h:54
AR_PHY_ACTIVE
#define AR_PHY_ACTIVE
Definition: ar9002_phy.h:53
AR_PHY_RX_DELAY_DELAY
#define AR_PHY_RX_DELAY_DELAY
Definition: ar9002_phy.h:186
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:61
AR_PHY_RX_DELAY
#define AR_PHY_RX_DELAY
Definition: ar9002_phy.h:184
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ah
uint8_t ah
Definition: registers.h:85
u32
uint32_t u32
Definition: stdint.h:24

References ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY, BASE_ACTIVATE_DELAY, IS_CHAN_B, REG_READ, REG_WRITE, and udelay().

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_chain_masks()

void ar9003_hw_set_chain_masks ( struct ath_hw *  ah,
u8  rx,
u8  tx 
)

Definition at line 538 of file ath9k_ar9003_phy.c.

539 {
540  switch (rx) {
541  case 0x5:
542  REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
543  AR_PHY_SWAP_ALT_CHAIN);
544  /* Fall through */
545  case 0x3:
546  case 0x1:
547  case 0x2:
548  case 0x7:
549  REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
550  REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
551  break;
552  default:
553  break;
554  }
555 
556  if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
557  REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
558  else
559  REG_WRITE(ah, AR_SELFGEN_MASK, tx);
560 
561  if (tx == 0x5) {
562  REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
563  AR_PHY_SWAP_ALT_CHAIN);
564  }
565 }
AR_SELFGEN_MASK
#define AR_SELFGEN_MASK
Definition: reg.h:1824
AR_PHY_ANALOG_SWAP
#define AR_PHY_ANALOG_SWAP
Definition: ar9002_phy.h:536
AR_PHY_RX_CHAINMASK
#define AR_PHY_RX_CHAINMASK
Definition: ar9002_phy.h:302
AR_PHY_CAL_CHAINMASK
#define AR_PHY_CAL_CHAINMASK
Definition: ar9002_phy.h:559
AR_PHY_SWAP_ALT_CHAIN
#define AR_PHY_SWAP_ALT_CHAIN
Definition: ar9002_phy.h:537
REG_SET_BIT
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:108
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
rx
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
ah
uint8_t ah
Definition: registers.h:85
tx
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition: wpa.h:237

References ah, AR_PHY_ANALOG_SWAP, AR_PHY_CAL_CHAINMASK, AR_PHY_RX_CHAINMASK, AR_PHY_SWAP_ALT_CHAIN, AR_SELFGEN_MASK, ATH9K_HW_CAP_APM, REG_SET_BIT, REG_WRITE, rx, and tx.

Referenced by ar9003_hw_init_cal(), and ar9003_hw_process_ini().

◆ ar9003_hw_override_ini()

static void ar9003_hw_override_ini ( struct ath_hw *  ah)
static

Definition at line 570 of file ath9k_ar9003_phy.c.

571 {
572  u32 val;
573 
574  /*
575  * Set the RX_ABORT and RX_DIS and clear it only after
576  * RXE is set for MAC. This prevents frames with
577  * corrupted descriptor status.
578  */
579  REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
580 
581  /*
582  * For AR9280 and above, there is a new feature that allows
583  * Multicast search based on both MAC Address and Key ID. By default,
584  * this feature is enabled. But since the driver is not using this
585  * feature, we switch it off; otherwise multicast search based on
586  * MAC addr only will fail.
587  */
588  val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
589  REG_WRITE(ah, AR_PCU_MISC_MODE2,
590  val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
591 }
AR_DIAG_RX_ABORT
#define AR_DIAG_RX_ABORT
Definition: reg.h:1525
val
void __asmcall int val
Definition: setjmp.h:12
AR_PCU_MISC_MODE2
#define AR_PCU_MISC_MODE2
Definition: reg.h:1831
AR_DIAG_RX_DIS
#define AR_DIAG_RX_DIS
Definition: reg.h:1511
AR_AGG_WEP_ENABLE
#define AR_AGG_WEP_ENABLE
Definition: reg.h:1901
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
REG_SET_BIT
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:108
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ah
uint8_t ah
Definition: registers.h:85
AR_DIAG_SW
#define AR_DIAG_SW
Definition: reg.h:1505
u32
uint32_t u32
Definition: stdint.h:24
AR_AGG_WEP_ENABLE_FIX
#define AR_AGG_WEP_ENABLE_FIX
Definition: reg.h:1894
AR_ADHOC_MCAST_KEYID_ENABLE
#define AR_ADHOC_MCAST_KEYID_ENABLE
Definition: reg.h:1895

References ah, AR_ADHOC_MCAST_KEYID_ENABLE, AR_AGG_WEP_ENABLE, AR_AGG_WEP_ENABLE_FIX, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, AR_PCU_MISC_MODE2, REG_READ, REG_SET_BIT, REG_WRITE, and val.

Referenced by ar9003_hw_process_ini().

◆ ar9003_hw_prog_ini()

static void ar9003_hw_prog_ini ( struct ath_hw *  ah,
struct ar5416IniArray *  iniArr,
int  column 
)
static

Definition at line 593 of file ath9k_ar9003_phy.c.

596 {
597  unsigned int i, regWrites = 0;
598 
599  /* New INI format: Array may be undefined (pre, core, post arrays) */
600  if (!iniArr->ia_array)
601  return;
602 
603  /*
604  * New INI format: Pre, core, and post arrays for a given subsystem
605  * may be modal (> 2 columns) or non-modal (2 columns). Determine if
606  * the array is non-modal and force the column to 1.
607  */
608  if ((unsigned int)column >= iniArr->ia_columns)
609  column = 1;
610 
611  for (i = 0; i < iniArr->ia_rows; i++) {
612  u32 reg = INI_RA(iniArr, i, 0);
613  u32 val = INI_RA(iniArr, i, column);
614 
615  REG_WRITE(ah, reg, val);
616 
617  DO_DELAY(regWrites);
618  }
619 }
reg
static unsigned int unsigned int reg
Definition: myson.h:162
val
void __asmcall int val
Definition: setjmp.h:12
DO_DELAY
#define DO_DELAY(x)
Definition: hw.h:113
INI_RA
#define INI_RA(iniarray, row, column)
Definition: calib.h:46
ar5416IniArray::ia_rows
u32 ia_rows
Definition: calib.h:36
ar5416IniArray::ia_columns
u32 ia_columns
Definition: calib.h:37
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ah
uint8_t ah
Definition: registers.h:85
ar5416IniArray::ia_array
u32 * ia_array
Definition: calib.h:35
u32
uint32_t u32
Definition: stdint.h:24

References ah, DO_DELAY, ar5416IniArray::ia_array, ar5416IniArray::ia_columns, ar5416IniArray::ia_rows, INI_RA, reg, REG_WRITE, and val.

Referenced by ar9003_hw_process_ini().

◆ ar9003_hw_process_ini()

static int ar9003_hw_process_ini ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 621 of file ath9k_ar9003_phy.c.

623 {
624  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
625  unsigned int regWrites = 0, i;
626  struct net80211_channel *channel = chan->chan;
627  u32 modesIndex;
628 
629  switch (chan->chanmode) {
630  case CHANNEL_A:
631  case CHANNEL_A_HT20:
632  modesIndex = 1;
633  break;
634  case CHANNEL_A_HT40PLUS:
635  case CHANNEL_A_HT40MINUS:
636  modesIndex = 2;
637  break;
638  case CHANNEL_G:
639  case CHANNEL_G_HT20:
640  case CHANNEL_B:
641  modesIndex = 4;
642  break;
643  case CHANNEL_G_HT40PLUS:
644  case CHANNEL_G_HT40MINUS:
645  modesIndex = 3;
646  break;
647 
648  default:
649  return -EINVAL;
650  }
651 
652  for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
653  ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
654  ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
655  ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
656  ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
657  }
658 
659  REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
660  REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
661 
662  /*
663  * For 5GHz channels requiring Fast Clock, apply
664  * different modal values.
665  */
666  if (IS_CHAN_A_FAST_CLOCK(ah, chan))
667  REG_WRITE_ARRAY(&ah->iniModesAdditional,
668  modesIndex, regWrites);
669 
670  if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
671  REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
672 
673  ar9003_hw_override_ini(ah);
674  ar9003_hw_set_channel_regs(ah, chan);
675  ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
676 
677  /* Set TX power */
678  ah->eep_ops->set_txpower(ah, chan,
679  ath9k_regd_get_ctl(regulatory, chan),
680  0,
681  channel->maxpower * 2,
682  min((u32) MAX_RATE_POWER,
683  (u32) regulatory->power_limit), 0);
684 
685  return 0;
686 }
EINVAL
#define EINVAL
Invalid argument.
Definition: errno.h:429
ar9003_hw_prog_ini
static void ar9003_hw_prog_ini(struct ath_hw *ah, struct ar5416IniArray *iniArr, int column)
Definition: ath9k_ar9003_phy.c:593
ath9k_channel::chanmode
u32 chanmode
Definition: hw.h:352
ar9003_hw_override_ini
static void ar9003_hw_override_ini(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:570
min
#define min(x, y)
Definition: ath.h:36
CHANNEL_A_HT40MINUS
#define CHANNEL_A_HT40MINUS
Definition: hw.h:323
ar9003_hw_set_channel_regs
static void ar9003_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:470
ath9k_channel::chan
struct net80211_channel * chan
Definition: hw.h:348
CHANNEL_A
#define CHANNEL_A
Definition: ath5k.h:640
ath_regulatory
Definition: ath.h:138
ath9k_regd_get_ctl
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Definition: ath9k_hw.c:869
CHANNEL_G
#define CHANNEL_G
Definition: ath5k.h:642
ath9k_hw_regulatory
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:875
ath_regulatory::power_limit
int16_t power_limit
Definition: ath.h:145
channel
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
AR_SREV_9340
#define AR_SREV_9340(_ah)
Definition: reg.h:879
CHANNEL_A_HT20
#define CHANNEL_A_HT20
Definition: hw.h:319
net80211_channel
An 802.11 RF channel.
Definition: net80211.h:385
REG_WRITE_ARRAY
#define REG_WRITE_ARRAY(iniarray, column, regWr)
Definition: hw.h:120
ar9003_hw_set_chain_masks
void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
Definition: ath9k_ar9003_phy.c:538
CHANNEL_A_HT40PLUS
#define CHANNEL_A_HT40PLUS
Definition: hw.h:322
ah
uint8_t ah
Definition: registers.h:85
CHANNEL_G_HT20
#define CHANNEL_G_HT20
Definition: hw.h:318
CHANNEL_B
#define CHANNEL_B
Definition: ath5k.h:641
CHANNEL_G_HT40PLUS
#define CHANNEL_G_HT40PLUS
Definition: hw.h:320
IS_CHAN_A_FAST_CLOCK
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
Definition: hw.h:365
CHANNEL_G_HT40MINUS
#define CHANNEL_G_HT40MINUS
Definition: hw.h:321
MAX_RATE_POWER
#define MAX_RATE_POWER
Definition: hw.h:145
u32
uint32_t u32
Definition: stdint.h:24

References ah, ar9003_hw_override_ini(), ar9003_hw_prog_ini(), ar9003_hw_set_chain_masks(), ar9003_hw_set_channel_regs(), AR_SREV_9340, ath9k_hw_regulatory(), ath9k_regd_get_ctl(), ATH_INI_NUM_SPLIT, ath9k_channel::chan, ath9k_channel::chanmode, channel, CHANNEL_A, CHANNEL_A_HT20, CHANNEL_A_HT40MINUS, CHANNEL_A_HT40PLUS, CHANNEL_B, CHANNEL_G, CHANNEL_G_HT20, CHANNEL_G_HT40MINUS, CHANNEL_G_HT40PLUS, EINVAL, IS_CHAN_A_FAST_CLOCK, MAX_RATE_POWER, min, ath_regulatory::power_limit, and REG_WRITE_ARRAY.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_rfmode()

static void ar9003_hw_set_rfmode ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 688 of file ath9k_ar9003_phy.c.

690 {
691  u32 rfMode = 0;
692 
693  if (chan == NULL)
694  return;
695 
696  rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
697  ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
698 
699  if (IS_CHAN_A_FAST_CLOCK(ah, chan))
700  rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
701 
702  REG_WRITE(ah, AR_PHY_MODE, rfMode);
703 }
IS_CHAN_B
#define IS_CHAN_B(_c)
Definition: ath5k.h:660
IS_CHAN_G
#define IS_CHAN_G(_c)
Definition: hw.h:356
AR_PHY_MODE_DYN_CCK_DISABLE
#define AR_PHY_MODE_DYN_CCK_DISABLE
Definition: ar9002_phy.h:407
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
AR_PHY_MODE_OFDM
#define AR_PHY_MODE_OFDM
Definition: ar9002_phy.h:406
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_MODE
#define AR_PHY_MODE
Definition: ar9002_phy.h:397
IS_CHAN_A_FAST_CLOCK
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
Definition: hw.h:365
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
u32
uint32_t u32
Definition: stdint.h:24
AR_PHY_MODE_DYNAMIC
#define AR_PHY_MODE_DYNAMIC
Definition: ar9002_phy.h:402

References ah, AR_PHY_MODE, AR_PHY_MODE_DYN_CCK_DISABLE, AR_PHY_MODE_DYNAMIC, AR_PHY_MODE_OFDM, IS_CHAN_A_FAST_CLOCK, IS_CHAN_B, IS_CHAN_G, NULL, and REG_WRITE.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_mark_phy_inactive()

static void ar9003_hw_mark_phy_inactive ( struct ath_hw *  ah)
static

Definition at line 705 of file ath9k_ar9003_phy.c.

706 {
707  REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
708 }
AR_PHY_ACTIVE
#define AR_PHY_ACTIVE
Definition: ar9002_phy.h:53
AR_PHY_ACTIVE_DIS
#define AR_PHY_ACTIVE_DIS
Definition: ar9002_phy.h:55
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ah
uint8_t ah
Definition: registers.h:85

References ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS, and REG_WRITE.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_delta_slope()

static void ar9003_hw_set_delta_slope ( struct ath_hw *  ah,
struct ath9k_channel *  chan 
)
static

Definition at line 710 of file ath9k_ar9003_phy.c.

712 {
713  u32 coef_scaled, ds_coef_exp, ds_coef_man;
714  u32 clockMhzScaled = 0x64000000;
715  struct chan_centers centers;
716 
717  /*
718  * half and quarter rate can divide the scaled clock by 2 or 4
719  * scale for selected channel bandwidth
720  */
721  if (IS_CHAN_HALF_RATE(chan))
722  clockMhzScaled = clockMhzScaled >> 1;
723  else if (IS_CHAN_QUARTER_RATE(chan))
724  clockMhzScaled = clockMhzScaled >> 2;
725 
726  /*
727  * ALGO -> coef = 1e8/fcarrier*fclock/40;
728  * scaled coef to provide precision for this floating calculation
729  */
730  ath9k_hw_get_channel_centers(ah, chan, &centers);
731  coef_scaled = clockMhzScaled / centers.synth_center;
732 
733  ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
734  &ds_coef_exp);
735 
736  REG_RMW_FIELD(ah, AR_PHY_TIMING3,
737  AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
738  REG_RMW_FIELD(ah, AR_PHY_TIMING3,
739  AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
740 
741  /*
742  * For Short GI,
743  * scaled coeff is 9/10 that of normal coeff
744  */
745  coef_scaled = (9 * coef_scaled) / 10;
746 
747  ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
748  &ds_coef_exp);
749 
750  /* for short gi */
751  REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
752  AR_PHY_SGI_DSC_MAN, ds_coef_man);
753  REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
754  AR_PHY_SGI_DSC_EXP, ds_coef_exp);
755 }
AR_PHY_SGI_DELTA
#define AR_PHY_SGI_DELTA
Definition: ar9003_phy.h:223
ath9k_hw_get_delta_slope_vals
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah __unused, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent)
Definition: ath9k_hw.c:966
IS_CHAN_HALF_RATE
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:363
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
IS_CHAN_QUARTER_RATE
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:364
AR_PHY_SGI_DSC_MAN
#define AR_PHY_SGI_DSC_MAN
Definition: ar9003_phy.h:241
AR_PHY_TIMING3_DSC_EXP
#define AR_PHY_TIMING3_DSC_EXP
Definition: ar9002_phy.h:46
AR_PHY_TIMING3_DSC_MAN
#define AR_PHY_TIMING3_DSC_MAN
Definition: ar9002_phy.h:44
AR_PHY_SGI_DSC_EXP
#define AR_PHY_SGI_DSC_EXP
Definition: ar9003_phy.h:243
chan_centers
Definition: hw.h:422
AR_PHY_TIMING3
#define AR_PHY_TIMING3
Definition: ar9002_phy.h:43
ath9k_hw_get_channel_centers
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:191
ah
uint8_t ah
Definition: registers.h:85
u32
uint32_t u32
Definition: stdint.h:24

References ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_EXP, AR_PHY_SGI_DSC_MAN, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_EXP, AR_PHY_TIMING3_DSC_MAN, ath9k_hw_get_channel_centers(), ath9k_hw_get_delta_slope_vals(), IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, REG_RMW_FIELD, and chan_centers::synth_center.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_rfbus_req()

static int ar9003_hw_rfbus_req ( struct ath_hw *  ah)
static

Definition at line 757 of file ath9k_ar9003_phy.c.

758 {
759  REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
760  return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
761  AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
762 }
AR_PHY_RFBUS_REQ_EN
#define AR_PHY_RFBUS_REQ_EN
Definition: ar9002_phy.h:270
AR_PHY_RFBUS_GRANT_EN
#define AR_PHY_RFBUS_GRANT_EN
Definition: ar9002_phy.h:390
ath9k_hw_wait
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:95
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
AR_PHY_RFBUS_REQ
#define AR_PHY_RFBUS_REQ
Definition: ar9002_phy.h:269
AH_WAIT_TIMEOUT
#define AH_WAIT_TIMEOUT
Definition: hw.h:146
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_RFBUS_GRANT
#define AR_PHY_RFBUS_GRANT
Definition: ar9002_phy.h:389

References ah, AH_WAIT_TIMEOUT, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN, ath9k_hw_wait(), and REG_WRITE.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_rfbus_done()

static void ar9003_hw_rfbus_done ( struct ath_hw *  ah)
static

Definition at line 768 of file ath9k_ar9003_phy.c.

769 {
770  u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
771  if (IS_CHAN_B(ah->curchan))
772  synthDelay = (4 * synthDelay) / 22;
773  else
774  synthDelay /= 10;
775 
776  udelay(synthDelay + BASE_ACTIVATE_DELAY);
777 
778  REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
779 }
BASE_ACTIVATE_DELAY
#define BASE_ACTIVATE_DELAY
Definition: hw.h:134
IS_CHAN_B
#define IS_CHAN_B(_c)
Definition: ath5k.h:660
AR_PHY_RX_DELAY_DELAY
#define AR_PHY_RX_DELAY_DELAY
Definition: ar9002_phy.h:186
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:61
AR_PHY_RX_DELAY
#define AR_PHY_RX_DELAY
Definition: ar9002_phy.h:184
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
AR_PHY_RFBUS_REQ
#define AR_PHY_RFBUS_REQ
Definition: ar9002_phy.h:269
ah
uint8_t ah
Definition: registers.h:85
u32
uint32_t u32
Definition: stdint.h:24

References ah, AR_PHY_RFBUS_REQ, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY, BASE_ACTIVATE_DELAY, IS_CHAN_B, REG_READ, REG_WRITE, and udelay().

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_diversity()

static void ar9003_hw_set_diversity ( struct ath_hw *  ah,
int  value 
)
static

Definition at line 781 of file ath9k_ar9003_phy.c.

782 {
783  u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
784  if (value)
785  v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
786  else
787  v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
788  REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
789 }
AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
Definition: ar9002_phy.h:420
value
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
AR_PHY_CCK_DETECT
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:414
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ah
uint8_t ah
Definition: registers.h:85
u32
uint32_t u32
Definition: stdint.h:24

References ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV, REG_READ, REG_WRITE, and value.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_ani_control()

static int ar9003_hw_ani_control ( struct ath_hw *  ah,
enum ath9k_ani_cmd  cmd,
int  param 
)
static

Definition at line 791 of file ath9k_ar9003_phy.c.

793 {
794  struct ath9k_channel *chan = ah->curchan;
795  struct ar5416AniState *aniState = &chan->ani;
796  s32 value, value2;
797 
798  switch (cmd & ah->ani_function) {
799  case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
800  /*
801  * on == 1 means ofdm weak signal detection is ON
802  * on == 1 is the default, for less noise immunity
803  *
804  * on == 0 means ofdm weak signal detection is OFF
805  * on == 0 means more noise imm
806  */
807  u32 on = param ? 1 : 0;
808  /*
809  * make register setting for default
810  * (weak sig detect ON) come from INI file
811  */
812  int m1ThreshLow = on ?
813  aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
814  int m2ThreshLow = on ?
815  aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
816  int m1Thresh = on ?
817  aniState->iniDef.m1Thresh : m1Thresh_off;
818  int m2Thresh = on ?
819  aniState->iniDef.m2Thresh : m2Thresh_off;
820  int m2CountThr = on ?
821  aniState->iniDef.m2CountThr : m2CountThr_off;
822  int m2CountThrLow = on ?
823  aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
824  int m1ThreshLowExt = on ?
825  aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
826  int m2ThreshLowExt = on ?
827  aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
828  int m1ThreshExt = on ?
829  aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
830  int m2ThreshExt = on ?
831  aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
832 
833  REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
834  AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
835  m1ThreshLow);
836  REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
837  AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
838  m2ThreshLow);
839  REG_RMW_FIELD(ah, AR_PHY_SFCORR,
840  AR_PHY_SFCORR_M1_THRESH, m1Thresh);
841  REG_RMW_FIELD(ah, AR_PHY_SFCORR,
842  AR_PHY_SFCORR_M2_THRESH, m2Thresh);
843  REG_RMW_FIELD(ah, AR_PHY_SFCORR,
844  AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
845  REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
846  AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
847  m2CountThrLow);
848 
849  REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
850  AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
851  REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
852  AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
853  REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
854  AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
855  REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
856  AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
857 
858  if (on)
859  REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
860  AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
861  else
862  REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
863  AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
864 
865  if (on != aniState->ofdmWeakSigDetect) {
866  DBG2("ath9k: "
867  "** ch %d: ofdm weak signal: %s=>%s\n",
868  chan->channel,
869  aniState->ofdmWeakSigDetect ?
870  "on" : "off",
871  on ? "on" : "off");
872  if (on)
873  ah->stats.ast_ani_ofdmon++;
874  else
875  ah->stats.ast_ani_ofdmoff++;
876  aniState->ofdmWeakSigDetect = on;
877  }
878  break;
879  }
880  case ATH9K_ANI_FIRSTEP_LEVEL:{
881  u32 level = param;
882 
883  if (level >= ARRAY_SIZE(firstep_table)) {
884  DBG("ath9k: "
885  "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
886  level, ARRAY_SIZE(firstep_table));
887  return 0;
888  }
889 
890  /*
891  * make register setting relative to default
892  * from INI file & cap value
893  */
894  value = firstep_table[level] -
895  firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
896  aniState->iniDef.firstep;
897  if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
898  value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
899  if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
900  value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
901  REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
902  AR_PHY_FIND_SIG_FIRSTEP,
903  value);
904  /*
905  * we need to set first step low register too
906  * make register setting relative to default
907  * from INI file & cap value
908  */
909  value2 = firstep_table[level] -
910  firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
911  aniState->iniDef.firstepLow;
912  if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
913  value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
914  if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
915  value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
916 
917  REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
918  AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
919 
920  if (level != aniState->firstepLevel) {
921  DBG2("ath9k: "
922  "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
923  chan->channel,
924  aniState->firstepLevel,
925  level,
926  ATH9K_ANI_FIRSTEP_LVL_NEW,
927  value,
928  aniState->iniDef.firstep);
929  DBG2("ath9k: "
930  "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
931  chan->channel,
932  aniState->firstepLevel,
933  level,
934  ATH9K_ANI_FIRSTEP_LVL_NEW,
935  value2,
936  aniState->iniDef.firstepLow);
937  if (level > aniState->firstepLevel)
938  ah->stats.ast_ani_stepup++;
939  else if (level < aniState->firstepLevel)
940  ah->stats.ast_ani_stepdown++;
941  aniState->firstepLevel = level;
942  }
943  break;
944  }
945  case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
946  u32 level = param;
947 
948  if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
949  DBG("ath9k: "
950  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
951  level, ARRAY_SIZE(cycpwrThr1_table));
952  return 0;
953  }
954  /*
955  * make register setting relative to default
956  * from INI file & cap value
957  */
958  value = cycpwrThr1_table[level] -
959  cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
960  aniState->iniDef.cycpwrThr1;
961  if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
962  value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
963  if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
964  value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
965  REG_RMW_FIELD(ah, AR_PHY_TIMING5,
966  AR_PHY_TIMING5_CYCPWR_THR1,
967  value);
968 
969  /*
970  * set AR_PHY_EXT_CCA for extension channel
971  * make register setting relative to default
972  * from INI file & cap value
973  */
974  value2 = cycpwrThr1_table[level] -
975  cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
976  aniState->iniDef.cycpwrThr1Ext;
977  if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
978  value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
979  if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
980  value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
981  REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
982  AR_PHY_EXT_CYCPWR_THR1, value2);
983 
984  if (level != aniState->spurImmunityLevel) {
985  DBG2("ath9k: "
986  "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
987  chan->channel,
988  aniState->spurImmunityLevel,
989  level,
990  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
991  value,
992  aniState->iniDef.cycpwrThr1);
993  DBG2("ath9k: "
994  "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
995  chan->channel,
996  aniState->spurImmunityLevel,
997  level,
998  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
999  value2,
1000  aniState->iniDef.cycpwrThr1Ext);
1001  if (level > aniState->spurImmunityLevel)
1002  ah->stats.ast_ani_spurup++;
1003  else if (level < aniState->spurImmunityLevel)
1004  ah->stats.ast_ani_spurdown++;
1005  aniState->spurImmunityLevel = level;
1006  }
1007  break;
1008  }
1009  case ATH9K_ANI_MRC_CCK:{
1010  /*
1011  * is_on == 1 means MRC CCK ON (default, less noise imm)
1012  * is_on == 0 means MRC CCK is OFF (more noise imm)
1013  */
1014  int is_on = param ? 1 : 0;
1015  REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1016  AR_PHY_MRC_CCK_ENABLE, is_on);
1017  REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1018  AR_PHY_MRC_CCK_MUX_REG, is_on);
1019  if (!(is_on != aniState->mrcCCKOff)) {
1020  DBG2("ath9k: "
1021  "** ch %d: MRC CCK: %s=>%s\n",
1022  chan->channel,
1023  !aniState->mrcCCKOff ? "on" : "off",
1024  is_on ? "on" : "off");
1025  if (is_on)
1026  ah->stats.ast_ani_ccklow++;
1027  else
1028  ah->stats.ast_ani_cckhigh++;
1029  aniState->mrcCCKOff = !is_on;
1030  }
1031  break;
1032  }
1033  case ATH9K_ANI_PRESENT:
1034  break;
1035  default:
1036  DBG2("ath9k: invalid cmd %d\n", cmd);
1037  return 0;
1038  }
1039 
1040  DBG2("ath9k: "
1041  "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1042  aniState->spurImmunityLevel,
1043  aniState->ofdmWeakSigDetect ? "on" : "off",
1044  aniState->firstepLevel,
1045  !aniState->mrcCCKOff ? "on" : "off",
1046  aniState->listenTime,
1047  aniState->ofdmPhyErrCount,
1048  aniState->cckPhyErrCount);
1049  return 1;
1050 }
AR_PHY_SFCORR_LOW
#define AR_PHY_SFCORR_LOW
Definition: ar9002_phy.h:140
AR_PHY_SFCORR_LOW_M2_THRESH_LOW
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW
Definition: ar9002_phy.h:146
m2CountThrLow_off
static const int m2CountThrLow_off
Definition: ath9k_ar9003_phy.c:43
ath9k_channel::channel
u16 channel
Definition: hw.h:350
ar5416AniState::listenTime
u32 listenTime
Definition: ani.h:131
ath9k_ani_default::m1ThreshLow
u16 m1ThreshLow
Definition: ani.h:104
AR_PHY_MRC_CCK_CTRL
#define AR_PHY_MRC_CCK_CTRL
Definition: ar9003_phy.h:322
firstep_table
static const int firstep_table[]
Definition: ath9k_ar9003_phy.c:27
AR_PHY_SFCORR_LOW_M1_THRESH_LOW
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW
Definition: ar9002_phy.h:144
ar5416AniState::spurImmunityLevel
u8 spurImmunityLevel
Definition: ani.h:127
ar5416AniState::mrcCCKOff
u8 mrcCCKOff
Definition: ani.h:126
s32
int32_t s32
Definition: stdint.h:23
ath9k_ani_default::m2CountThrLow
u16 m2CountThrLow
Definition: ani.h:109
ath9k_ani_default::m2CountThr
u16 m2CountThr
Definition: ani.h:108
REG_CLR_BIT
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:110
ATH9K_SIG_FIRSTEP_SETTING_MAX
#define ATH9K_SIG_FIRSTEP_SETTING_MAX
Definition: ani.h:73
AR_PHY_MRC_CCK_MUX_REG
#define AR_PHY_MRC_CCK_MUX_REG
Definition: ar9003_phy.h:325
AR_PHY_FIND_SIG_LOW
#define AR_PHY_FIND_SIG_LOW
Definition: ar9002_phy.h:120
AR_PHY_SFCORR_EXT_M1_THRESH_LOW
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW
Definition: ar9002_phy.h:350
ath9k_ani_default::m1ThreshExt
u16 m1ThreshExt
Definition: ani.h:112
m2ThreshLow_off
static const int m2ThreshLow_off
Definition: ath9k_ar9003_phy.c:39
AR_PHY_SFCORR_EXT_M2_THRESH_LOW
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW
Definition: ar9002_phy.h:352
ath9k_ani_default::cycpwrThr1Ext
u16 cycpwrThr1Ext
Definition: ani.h:117
ath9k_channel::chan
struct net80211_channel * chan
Definition: hw.h:348
ath9k_ani_default::m2Thresh
u16 m2Thresh
Definition: ani.h:107
REG_RMW_FIELD
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:104
m1ThreshLowExt_off
static const int m1ThreshLowExt_off
Definition: ath9k_ar9003_phy.c:44
AR_PHY_EXT_CCA
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:332
AR_PHY_SFCORR_EXT_M2_THRESH
#define AR_PHY_SFCORR_EXT_M2_THRESH
Definition: ar9002_phy.h:348
AR_PHY_TIMING5
#define AR_PHY_TIMING5
Definition: ar9002_phy.h:203
ath9k_ani_default::firstepLow
u16 firstepLow
Definition: ani.h:115
AR_PHY_SFCORR_M1_THRESH
#define AR_PHY_SFCORR_M1_THRESH
Definition: ar9002_phy.h:152
ath9k_ani_default::m1Thresh
u16 m1Thresh
Definition: ani.h:106
ar5416AniState::ofdmWeakSigDetect
u8 ofdmWeakSigDetect
Definition: ani.h:129
value
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
Definition: ar9002_phy.h:142
m2ThreshLowExt_off
static const int m2ThreshLowExt_off
Definition: ath9k_ar9003_phy.c:45
ar5416AniState::firstepLevel
u8 firstepLevel
Definition: ani.h:128
ATH9K_ANI_FIRSTEP_LVL_NEW
#define ATH9K_ANI_FIRSTEP_LVL_NEW
Definition: ani.h:56
AR_PHY_TIMING5_CYCPWR_THR1
#define AR_PHY_TIMING5_CYCPWR_THR1
Definition: ar9002_phy.h:204
ath9k_ani_default::cycpwrThr1
u16 cycpwrThr1
Definition: ani.h:116
ATH9K_SIG_SPUR_IMM_SETTING_MIN
#define ATH9K_SIG_SPUR_IMM_SETTING_MIN
Definition: ani.h:74
AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW
#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW
Definition: ar9003_phy.h:193
param
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW
Definition: ar9002_phy.h:141
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
ATH9K_SIG_SPUR_IMM_SETTING_MAX
#define ATH9K_SIG_SPUR_IMM_SETTING_MAX
Definition: ani.h:75
m1Thresh_off
static const int m1Thresh_off
Definition: ath9k_ar9003_phy.c:40
AR_PHY_SFCORR_M2COUNT_THR
#define AR_PHY_SFCORR_M2COUNT_THR
Definition: ar9002_phy.h:150
ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
Definition: ani.h:53
ath9k_ani_default::firstep
u16 firstep
Definition: ani.h:114
cycpwrThr1_table
static const int cycpwrThr1_table[]
Definition: ath9k_ar9003_phy.c:31
AR_PHY_FIND_SIG_FIRSTEP
#define AR_PHY_FIND_SIG_FIRSTEP
Definition: ar9002_phy.h:115
AR_PHY_SFCORR
#define AR_PHY_SFCORR
Definition: ar9002_phy.h:149
REG_SET_BIT
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:108
ath9k_ani_default::m2ThreshLowExt
u16 m2ThreshLowExt
Definition: ani.h:111
ath9k_channel
Definition: hw.h:347
AR_PHY_SFCORR_M2_THRESH
#define AR_PHY_SFCORR_M2_THRESH
Definition: ar9002_phy.h:154
m2Thresh_off
static const int m2Thresh_off
Definition: ath9k_ar9003_phy.c:41
AR_PHY_SFCORR_EXT
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:345
AR_PHY_EXT_CYCPWR_THR1
#define AR_PHY_EXT_CYCPWR_THR1
Definition: ar9003_phy.h:154
ath9k_channel::ani
struct ar5416AniState ani
Definition: hw.h:349
m2CountThr_off
static const int m2CountThr_off
Definition: ath9k_ar9003_phy.c:42
ath9k_ani_default::m1ThreshLowExt
u16 m1ThreshLowExt
Definition: ani.h:110
ATH9K_SIG_FIRSTEP_SETTING_MIN
#define ATH9K_SIG_FIRSTEP_SETTING_MIN
Definition: ani.h:72
AR_PHY_SFCORR_EXT_M1_THRESH
#define AR_PHY_SFCORR_EXT_M1_THRESH
Definition: ar9002_phy.h:346
AR_PHY_FIND_SIG
#define AR_PHY_FIND_SIG
Definition: ar9002_phy.h:114
ar5416AniState::ofdmPhyErrCount
u32 ofdmPhyErrCount
Definition: ani.h:135
ath9k_ani_default::m2ThreshLow
u16 m2ThreshLow
Definition: ani.h:105
ah
uint8_t ah
Definition: registers.h:85
m2ThreshExt_off
static const int m2ThreshExt_off
Definition: ath9k_ar9003_phy.c:47
m1ThreshLow_off
static const int m1ThreshLow_off
Definition: ath9k_ar9003_phy.c:38
DBG
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
ar5416AniState::cckPhyErrCount
u32 cckPhyErrCount
Definition: ani.h:136
ar5416AniState::iniDef
struct ath9k_ani_default iniDef
Definition: ani.h:140
ath9k_ani_default::m2ThreshExt
u16 m2ThreshExt
Definition: ani.h:113
cmd
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
AR_PHY_MRC_CCK_ENABLE
#define AR_PHY_MRC_CCK_ENABLE
Definition: ar9003_phy.h:323
m1ThreshExt_off
static const int m1ThreshExt_off
Definition: ath9k_ar9003_phy.c:46
u32
uint32_t u32
Definition: stdint.h:24
DBG2
#define DBG2(...)
Definition: compiler.h:515

References ah, ath9k_channel::ani, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, AR_PHY_MRC_CCK_CTRL, AR_PHY_MRC_CCK_ENABLE, AR_PHY_MRC_CCK_MUX_REG, AR_PHY_SFCORR, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, AR_PHY_SFCORR_EXT_M2_THRESH, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW, AR_PHY_SFCORR_M1_THRESH, AR_PHY_SFCORR_M2_THRESH, AR_PHY_SFCORR_M2COUNT_THR, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, ARRAY_SIZE, ATH9K_ANI_FIRSTEP_LEVEL, ATH9K_ANI_FIRSTEP_LVL_NEW, ATH9K_ANI_MRC_CCK, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, ATH9K_ANI_PRESENT, ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, ATH9K_SIG_FIRSTEP_SETTING_MAX, ATH9K_SIG_FIRSTEP_SETTING_MIN, ATH9K_SIG_SPUR_IMM_SETTING_MAX, ATH9K_SIG_SPUR_IMM_SETTING_MIN, ar5416AniState::cckPhyErrCount, ath9k_channel::chan, ath9k_channel::channel, cmd, ath9k_ani_default::cycpwrThr1, cycpwrThr1_table, ath9k_ani_default::cycpwrThr1Ext, DBG, DBG2, ath9k_ani_default::firstep, firstep_table, ar5416AniState::firstepLevel, ath9k_ani_default::firstepLow, ar5416AniState::iniDef, ar5416AniState::listenTime, ath9k_ani_default::m1Thresh, m1Thresh_off, ath9k_ani_default::m1ThreshExt, m1ThreshExt_off, ath9k_ani_default::m1ThreshLow, m1ThreshLow_off, ath9k_ani_default::m1ThreshLowExt, m1ThreshLowExt_off, ath9k_ani_default::m2CountThr, m2CountThr_off, ath9k_ani_default::m2CountThrLow, m2CountThrLow_off, ath9k_ani_default::m2Thresh, m2Thresh_off, ath9k_ani_default::m2ThreshExt, m2ThreshExt_off, ath9k_ani_default::m2ThreshLow, m2ThreshLow_off, ath9k_ani_default::m2ThreshLowExt, m2ThreshLowExt_off, ar5416AniState::mrcCCKOff, ar5416AniState::ofdmPhyErrCount, ar5416AniState::ofdmWeakSigDetect, param, REG_CLR_BIT, REG_RMW_FIELD, REG_SET_BIT, ar5416AniState::spurImmunityLevel, and value.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_do_getnf()

static void ar9003_hw_do_getnf ( struct ath_hw *  ah,
int16_t  nfarray[NUM_NF_READINGS] 
)
static

Definition at line 1052 of file ath9k_ar9003_phy.c.

1054 {
1055 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1056 #define AR_PHY_CH_MINCCA_PWR_S 20
1057 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1058 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1059 
1060  int16_t nf;
1061  int i;
1062 
1063  for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1064  if (ah->rxchainmask & BIT(i)) {
1065  nf = MS(REG_READ(ah, ah->nf_regs[i]),
1066  AR_PHY_CH_MINCCA_PWR);
1067  nfarray[i] = sign_extend32(nf, 8);
1068 
1069  if (IS_CHAN_HT40(ah->curchan)) {
1070  u8 ext_idx = AR9300_MAX_CHAINS + i;
1071 
1072  nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1073  AR_PHY_CH_EXT_MINCCA_PWR);
1074  nfarray[ext_idx] = sign_extend32(nf, 8);
1075  }
1076  }
1077  }
1078 }
AR9300_MAX_CHAINS
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:50
MS
#define MS(_v, _f)
Definition: hw.h:103
sign_extend32
static int32_t sign_extend32(uint32_t value, int index)
Definition: ath.h:71
AR_PHY_CH_EXT_MINCCA_PWR
#define AR_PHY_CH_EXT_MINCCA_PWR
AR_PHY_CH_MINCCA_PWR
#define AR_PHY_CH_MINCCA_PWR
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
BIT
#define BIT(nr)
Definition: ath.h:34
ah
uint8_t ah
Definition: registers.h:85
int16_t
signed short int16_t
Definition: stdint.h:16
IS_CHAN_HT40
#define IS_CHAN_HT40(_c)
Definition: hw.h:373
u8
uint8_t u8
Definition: stdint.h:20

References ah, AR9300_MAX_CHAINS, AR_PHY_CH_EXT_MINCCA_PWR, AR_PHY_CH_MINCCA_PWR, BIT, IS_CHAN_HT40, MS, REG_READ, and sign_extend32().

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_nf_limits()

static void ar9003_hw_set_nf_limits ( struct ath_hw *  ah)
static

Definition at line 1080 of file ath9k_ar9003_phy.c.

1081 {
1082  ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1083  ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1084  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1085  ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1086  ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1087  ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1088 }
AR_PHY_CCA_NOM_VAL_9300_5GHZ
#define AR_PHY_CCA_NOM_VAL_9300_5GHZ
Definition: ar9003_phy.h:331
AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ
Definition: ar9003_phy.h:335
AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ
Definition: ar9003_phy.h:332
AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ
#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ
Definition: ar9003_phy.h:334
AR_PHY_CCA_NOM_VAL_9300_2GHZ
#define AR_PHY_CCA_NOM_VAL_9300_2GHZ
Definition: ar9003_phy.h:330
AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ
#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ
Definition: ar9003_phy.h:333
ah
uint8_t ah
Definition: registers.h:85

References ah, AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ, AR_PHY_CCA_NOM_VAL_9300_2GHZ, and AR_PHY_CCA_NOM_VAL_9300_5GHZ.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_ani_cache_ini_regs()

static void ar9003_hw_ani_cache_ini_regs ( struct ath_hw *  ah)
static

Definition at line 1095 of file ath9k_ar9003_phy.c.

1096 {
1097  struct ar5416AniState *aniState;
1098  struct ath9k_channel *chan = ah->curchan;
1099  struct ath9k_ani_default *iniDef;
1100  u32 val;
1101 
1102  aniState = &ah->curchan->ani;
1103  iniDef = &aniState->iniDef;
1104 
1105  DBG2("ath9k: "
1106  "ver %d.%d chan %d Mhz/0x%x\n",
1107  ah->hw_version.macVersion,
1108  ah->hw_version.macRev,
1109  chan->channel,
1110  chan->channelFlags);
1111 
1112  val = REG_READ(ah, AR_PHY_SFCORR);
1113  iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1114  iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1115  iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1116 
1117  val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1118  iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1119  iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1120  iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1121 
1122  val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1123  iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1124  iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1125  iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1126  iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1127  iniDef->firstep = REG_READ_FIELD(ah,
1128  AR_PHY_FIND_SIG,
1129  AR_PHY_FIND_SIG_FIRSTEP);
1130  iniDef->firstepLow = REG_READ_FIELD(ah,
1131  AR_PHY_FIND_SIG_LOW,
1132  AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1133  iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1134  AR_PHY_TIMING5,
1135  AR_PHY_TIMING5_CYCPWR_THR1);
1136  iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1137  AR_PHY_EXT_CCA,
1138  AR_PHY_EXT_CYCPWR_THR1);
1139 
1140  /* these levels just got reset to defaults by the INI */
1141  aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1142  aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1143  aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1144  aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1145 }
AR_PHY_SFCORR_LOW
#define AR_PHY_SFCORR_LOW
Definition: ar9002_phy.h:140
AR_PHY_SFCORR_LOW_M2_THRESH_LOW
#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW
Definition: ar9002_phy.h:146
ath9k_channel::channel
u16 channel
Definition: hw.h:350
ath9k_ani_default::m1ThreshLow
u16 m1ThreshLow
Definition: ani.h:104
AR_PHY_SFCORR_LOW_M1_THRESH_LOW
#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW
Definition: ar9002_phy.h:144
val
void __asmcall int val
Definition: setjmp.h:12
ar5416AniState::spurImmunityLevel
u8 spurImmunityLevel
Definition: ani.h:127
ar5416AniState::mrcCCKOff
u8 mrcCCKOff
Definition: ani.h:126
ath9k_ani_default::m2CountThrLow
u16 m2CountThrLow
Definition: ani.h:109
ath9k_ani_default::m2CountThr
u16 m2CountThr
Definition: ani.h:108
MS
#define MS(_v, _f)
Definition: hw.h:103
AR_PHY_FIND_SIG_LOW
#define AR_PHY_FIND_SIG_LOW
Definition: ar9002_phy.h:120
AR_PHY_SFCORR_EXT_M1_THRESH_LOW
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW
Definition: ar9002_phy.h:350
ath9k_ani_default::m1ThreshExt
u16 m1ThreshExt
Definition: ani.h:112
AR_PHY_SFCORR_EXT_M2_THRESH_LOW
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW
Definition: ar9002_phy.h:352
ath9k_ani_default::cycpwrThr1Ext
u16 cycpwrThr1Ext
Definition: ani.h:117
ath9k_channel::chan
struct net80211_channel * chan
Definition: hw.h:348
ath9k_channel::channelFlags
u32 channelFlags
Definition: hw.h:351
ath9k_ani_default::m2Thresh
u16 m2Thresh
Definition: ani.h:107
AR_PHY_EXT_CCA
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:332
AR_PHY_SFCORR_EXT_M2_THRESH
#define AR_PHY_SFCORR_EXT_M2_THRESH
Definition: ar9002_phy.h:348
AR_PHY_TIMING5
#define AR_PHY_TIMING5
Definition: ar9002_phy.h:203
ath9k_ani_default::firstepLow
u16 firstepLow
Definition: ani.h:115
AR_PHY_SFCORR_M1_THRESH
#define AR_PHY_SFCORR_M1_THRESH
Definition: ar9002_phy.h:152
ath9k_ani_default::m1Thresh
u16 m1Thresh
Definition: ani.h:106
ar5416AniState::ofdmWeakSigDetect
u8 ofdmWeakSigDetect
Definition: ani.h:129
AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW
Definition: ar9002_phy.h:142
ar5416AniState::firstepLevel
u8 firstepLevel
Definition: ani.h:128
ATH9K_ANI_FIRSTEP_LVL_NEW
#define ATH9K_ANI_FIRSTEP_LVL_NEW
Definition: ani.h:56
AR_PHY_TIMING5_CYCPWR_THR1
#define AR_PHY_TIMING5_CYCPWR_THR1
Definition: ar9002_phy.h:204
ath9k_ani_default::cycpwrThr1
u16 cycpwrThr1
Definition: ani.h:116
AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW
#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW
Definition: ar9003_phy.h:193
AR_PHY_SFCORR_M2COUNT_THR
#define AR_PHY_SFCORR_M2COUNT_THR
Definition: ar9002_phy.h:150
ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW
Definition: ani.h:53
ath9k_ani_default::firstep
u16 firstep
Definition: ani.h:114
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
AR_PHY_FIND_SIG_FIRSTEP
#define AR_PHY_FIND_SIG_FIRSTEP
Definition: ar9002_phy.h:115
AR_PHY_SFCORR
#define AR_PHY_SFCORR
Definition: ar9002_phy.h:149
ath9k_ani_default::m2ThreshLowExt
u16 m2ThreshLowExt
Definition: ani.h:111
ath9k_channel
Definition: hw.h:347
AR_PHY_SFCORR_M2_THRESH
#define AR_PHY_SFCORR_M2_THRESH
Definition: ar9002_phy.h:154
AR_PHY_SFCORR_EXT
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:345
AR_PHY_EXT_CYCPWR_THR1
#define AR_PHY_EXT_CYCPWR_THR1
Definition: ar9003_phy.h:154
ath9k_ani_default::m1ThreshLowExt
u16 m1ThreshLowExt
Definition: ani.h:110
REG_READ_FIELD
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:106
AR_PHY_SFCORR_EXT_M1_THRESH
#define AR_PHY_SFCORR_EXT_M1_THRESH
Definition: ar9002_phy.h:346
AR_PHY_FIND_SIG
#define AR_PHY_FIND_SIG
Definition: ar9002_phy.h:114
ATH9K_ANI_USE_OFDM_WEAK_SIG
#define ATH9K_ANI_USE_OFDM_WEAK_SIG
Definition: ani.h:49
ath9k_ani_default::m2ThreshLow
u16 m2ThreshLow
Definition: ani.h:105
ah
uint8_t ah
Definition: registers.h:85
ATH9K_ANI_ENABLE_MRC_CCK
#define ATH9K_ANI_ENABLE_MRC_CCK
Definition: ani.h:77
ar5416AniState::iniDef
struct ath9k_ani_default iniDef
Definition: ani.h:140
ath9k_ani_default::m2ThreshExt
u16 m2ThreshExt
Definition: ani.h:113
ath9k_ani_default
Definition: ani.h:103
u32
uint32_t u32
Definition: stdint.h:24
DBG2
#define DBG2(...)
Definition: compiler.h:515

References ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, AR_PHY_SFCORR, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, AR_PHY_SFCORR_EXT_M2_THRESH, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, AR_PHY_SFCORR_LOW, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, AR_PHY_SFCORR_M1_THRESH, AR_PHY_SFCORR_M2_THRESH, AR_PHY_SFCORR_M2COUNT_THR, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, ATH9K_ANI_ENABLE_MRC_CCK, ATH9K_ANI_FIRSTEP_LVL_NEW, ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, ATH9K_ANI_USE_OFDM_WEAK_SIG, ath9k_channel::chan, ath9k_channel::channel, ath9k_channel::channelFlags, ath9k_ani_default::cycpwrThr1, ath9k_ani_default::cycpwrThr1Ext, DBG2, ath9k_ani_default::firstep, ar5416AniState::firstepLevel, ath9k_ani_default::firstepLow, ar5416AniState::iniDef, ath9k_ani_default::m1Thresh, ath9k_ani_default::m1ThreshExt, ath9k_ani_default::m1ThreshLow, ath9k_ani_default::m1ThreshLowExt, ath9k_ani_default::m2CountThr, ath9k_ani_default::m2CountThrLow, ath9k_ani_default::m2Thresh, ath9k_ani_default::m2ThreshExt, ath9k_ani_default::m2ThreshLow, ath9k_ani_default::m2ThreshLowExt, ar5416AniState::mrcCCKOff, MS, ar5416AniState::ofdmWeakSigDetect, REG_READ, REG_READ_FIELD, ar5416AniState::spurImmunityLevel, and val.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_radar_params()

static void ar9003_hw_set_radar_params ( struct ath_hw *  ah,
struct ath_hw_radar_conf *  conf 
)
static

Definition at line 1147 of file ath9k_ar9003_phy.c.

1149 {
1150  u32 radar_0 = 0, radar_1 = 0;
1151 
1152  if (!conf) {
1153  REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1154  return;
1155  }
1156 
1157  radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1158  radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1159  radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1160  radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1161  radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1162  radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1163 
1164  radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1165  radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1166  radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1167  radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1168  radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1169 
1170  REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1171  REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1172  if (conf->ext_channel)
1173  REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1174  else
1175  REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1176 }
AR_PHY_RADAR_0_FFT_ENA
#define AR_PHY_RADAR_0_FFT_ENA
Definition: ar9002_phy.h:227
REG_CLR_BIT
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:110
AR_PHY_RADAR_EXT
#define AR_PHY_RADAR_EXT
Definition: ar9002_phy.h:222
AR_PHY_RADAR_1_MAX_RRSSI
#define AR_PHY_RADAR_1_MAX_RRSSI
Definition: ar9002_phy.h:245
AR_PHY_RADAR_1
#define AR_PHY_RADAR_1
Definition: ar9002_phy.h:239
ath_hw_radar_conf::pulse_maxlen
unsigned int pulse_maxlen
Definition: hw.h:517
ath_hw_radar_conf::ext_channel
int ext_channel
Definition: hw.h:523
SM
#define SM(_v, _f)
Definition: hw.h:102
AR_PHY_RADAR_0_HEIGHT
#define AR_PHY_RADAR_0_HEIGHT
Definition: ar9002_phy.h:232
ath_hw_radar_conf::pulse_inband_step
unsigned int pulse_inband_step
Definition: hw.h:514
ath_hw_radar_conf::pulse_height
unsigned int pulse_height
Definition: hw.h:515
ath_hw_radar_conf::radar_rssi
unsigned int radar_rssi
Definition: hw.h:519
AR_PHY_RADAR_1_RELSTEP_THRESH
#define AR_PHY_RADAR_1_RELSTEP_THRESH
Definition: ar9002_phy.h:247
AR_PHY_RADAR_0_RRSSI
#define AR_PHY_RADAR_0_RRSSI
Definition: ar9002_phy.h:234
ath_hw_radar_conf::fir_power
int fir_power
Definition: hw.h:521
AR_PHY_RADAR_0_INBAND
#define AR_PHY_RADAR_0_INBAND
Definition: ar9002_phy.h:228
AR_PHY_RADAR_0_PRSSI
#define AR_PHY_RADAR_0_PRSSI
Definition: ar9002_phy.h:230
AR_PHY_RADAR_1_MAXLEN
#define AR_PHY_RADAR_1_MAXLEN
Definition: ar9002_phy.h:249
ath_hw_radar_conf::radar_inband
unsigned int radar_inband
Definition: hw.h:520
ath_hw_radar_conf::pulse_rssi
unsigned int pulse_rssi
Definition: hw.h:516
AR_PHY_RADAR_0_ENA
#define AR_PHY_RADAR_0_ENA
Definition: ar9002_phy.h:226
AR_PHY_RADAR_0_FIRPWR
#define AR_PHY_RADAR_0_FIRPWR
Definition: ar9002_phy.h:236
REG_SET_BIT
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:108
AR_PHY_RADAR_1_BLOCK_CHECK
#define AR_PHY_RADAR_1_BLOCK_CHECK
Definition: ar9002_phy.h:244
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
AR_PHY_RADAR_0
#define AR_PHY_RADAR_0
Definition: ar9002_phy.h:225
ath_hw_radar_conf::pulse_inband
unsigned int pulse_inband
Definition: hw.h:513
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_RADAR_EXT_ENA
#define AR_PHY_RADAR_EXT_ENA
Definition: ar9002_phy.h:223
u32
uint32_t u32
Definition: stdint.h:24
AR_PHY_RADAR_1_RELPWR_THRESH
#define AR_PHY_RADAR_1_RELPWR_THRESH
Definition: ar9002_phy.h:242

References ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA, AR_PHY_RADAR_0_FFT_ENA, AR_PHY_RADAR_0_FIRPWR, AR_PHY_RADAR_0_HEIGHT, AR_PHY_RADAR_0_INBAND, AR_PHY_RADAR_0_PRSSI, AR_PHY_RADAR_0_RRSSI, AR_PHY_RADAR_1, AR_PHY_RADAR_1_BLOCK_CHECK, AR_PHY_RADAR_1_MAX_RRSSI, AR_PHY_RADAR_1_MAXLEN, AR_PHY_RADAR_1_RELPWR_THRESH, AR_PHY_RADAR_1_RELSTEP_THRESH, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA, ath_hw_radar_conf::ext_channel, ath_hw_radar_conf::fir_power, ath_hw_radar_conf::pulse_height, ath_hw_radar_conf::pulse_inband, ath_hw_radar_conf::pulse_inband_step, ath_hw_radar_conf::pulse_maxlen, ath_hw_radar_conf::pulse_rssi, ath_hw_radar_conf::radar_inband, ath_hw_radar_conf::radar_rssi, REG_CLR_BIT, REG_SET_BIT, REG_WRITE, and SM.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_set_radar_conf()

static void ar9003_hw_set_radar_conf ( struct ath_hw *  ah)
static

Definition at line 1178 of file ath9k_ar9003_phy.c.

1179 {
1180  struct ath_hw_radar_conf *conf = &ah->radar_conf;
1181 
1182  conf->fir_power = -28;
1183  conf->radar_rssi = 0;
1184  conf->pulse_height = 10;
1185  conf->pulse_rssi = 24;
1186  conf->pulse_inband = 8;
1187  conf->pulse_maxlen = 255;
1188  conf->pulse_inband_step = 12;
1189  conf->radar_inband = 8;
1190 }
ath_hw_radar_conf::pulse_maxlen
unsigned int pulse_maxlen
Definition: hw.h:517
ath_hw_radar_conf::pulse_inband_step
unsigned int pulse_inband_step
Definition: hw.h:514
ath_hw_radar_conf::pulse_height
unsigned int pulse_height
Definition: hw.h:515
ath_hw_radar_conf::radar_rssi
unsigned int radar_rssi
Definition: hw.h:519
ath_hw_radar_conf::fir_power
int fir_power
Definition: hw.h:521
ath_hw_radar_conf
struct ath_hw_radar_conf - radar detection initialization parameters
Definition: hw.h:512
ath_hw_radar_conf::radar_inband
unsigned int radar_inband
Definition: hw.h:520
ath_hw_radar_conf::pulse_rssi
unsigned int pulse_rssi
Definition: hw.h:516
ath_hw_radar_conf::pulse_inband
unsigned int pulse_inband
Definition: hw.h:513
ah
uint8_t ah
Definition: registers.h:85

References ah, ath_hw_radar_conf::fir_power, ath_hw_radar_conf::pulse_height, ath_hw_radar_conf::pulse_inband, ath_hw_radar_conf::pulse_inband_step, ath_hw_radar_conf::pulse_maxlen, ath_hw_radar_conf::pulse_rssi, ath_hw_radar_conf::radar_inband, and ath_hw_radar_conf::radar_rssi.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_antdiv_comb_conf_get()

static void ar9003_hw_antdiv_comb_conf_get ( struct ath_hw *  ah,
struct ath_hw_antcomb_conf *  antconf 
)
static

Definition at line 1192 of file ath9k_ar9003_phy.c.

1194 {
1195  u32 regval;
1196 
1197  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1198  antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1199  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1200  antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1201  AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1202  antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1203  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1204  antconf->lna1_lna2_delta = -9;
1205  antconf->div_group = 2;
1206 }
ath_hw_antcomb_conf::fast_div_bias
u8 fast_div_bias
Definition: hw.h:485
AR_PHY_9485_ANT_DIV_MAIN_LNACONF
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF
Definition: ar9003_phy.h:282
AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
Definition: ar9003_phy.h:283
AR_PHY_9485_ANT_FAST_DIV_BIAS
#define AR_PHY_9485_ANT_FAST_DIV_BIAS
Definition: ar9003_phy.h:276
ath_hw_antcomb_conf::div_group
u8 div_group
Definition: hw.h:489
ath_hw_antcomb_conf::alt_lna_conf
u8 alt_lna_conf
Definition: hw.h:484
AR_PHY_9485_ANT_FAST_DIV_BIAS_S
#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S
Definition: ar9003_phy.h:277
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
ath_hw_antcomb_conf::lna1_lna2_delta
int lna1_lna2_delta
Definition: hw.h:488
ath_hw_antcomb_conf::main_lna_conf
u8 main_lna_conf
Definition: hw.h:483
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_MC_GAIN_CTRL
#define AR_PHY_MC_GAIN_CTRL
Definition: ar9003_phy.h:269
AR_PHY_9485_ANT_DIV_ALT_LNACONF
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF
Definition: ar9003_phy.h:280
AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
Definition: ar9003_phy.h:281
u32
uint32_t u32
Definition: stdint.h:24

References ah, ath_hw_antcomb_conf::alt_lna_conf, AR_PHY_9485_ANT_DIV_ALT_LNACONF, AR_PHY_9485_ANT_DIV_ALT_LNACONF_S, AR_PHY_9485_ANT_DIV_MAIN_LNACONF, AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S, AR_PHY_9485_ANT_FAST_DIV_BIAS, AR_PHY_9485_ANT_FAST_DIV_BIAS_S, AR_PHY_MC_GAIN_CTRL, ath_hw_antcomb_conf::div_group, ath_hw_antcomb_conf::fast_div_bias, ath_hw_antcomb_conf::lna1_lna2_delta, ath_hw_antcomb_conf::main_lna_conf, and REG_READ.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_antdiv_comb_conf_set()

static void ar9003_hw_antdiv_comb_conf_set ( struct ath_hw *  ah,
struct ath_hw_antcomb_conf *  antconf 
)
static

Definition at line 1208 of file ath9k_ar9003_phy.c.

1210 {
1211  u32 regval;
1212 
1213  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1214  regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1215  AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1216  AR_PHY_9485_ANT_FAST_DIV_BIAS |
1217  AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1218  AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1219  regval |= ((antconf->main_lna_conf <<
1220  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1221  & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1222  regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1223  & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1224  regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1225  & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1226  regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1227  & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1228  regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1229  & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1230 
1231  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1232 }
ath_hw_antcomb_conf::fast_div_bias
u8 fast_div_bias
Definition: hw.h:485
AR_PHY_9485_ANT_DIV_MAIN_LNACONF
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF
Definition: ar9003_phy.h:282
ath_hw_antcomb_conf::alt_gaintb
u8 alt_gaintb
Definition: hw.h:487
AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
Definition: ar9003_phy.h:283
AR_PHY_9485_ANT_FAST_DIV_BIAS
#define AR_PHY_9485_ANT_FAST_DIV_BIAS
Definition: ar9003_phy.h:276
AR_PHY_9485_ANT_DIV_ALT_GAINTB_S
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S
Definition: ar9003_phy.h:285
AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S
Definition: ar9003_phy.h:287
AR_PHY_9485_ANT_DIV_ALT_GAINTB
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB
Definition: ar9003_phy.h:284
ath_hw_antcomb_conf::main_gaintb
u8 main_gaintb
Definition: hw.h:486
ath_hw_antcomb_conf::alt_lna_conf
u8 alt_lna_conf
Definition: hw.h:484
AR_PHY_9485_ANT_FAST_DIV_BIAS_S
#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S
Definition: ar9003_phy.h:277
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ath_hw_antcomb_conf::main_lna_conf
u8 main_lna_conf
Definition: hw.h:483
ah
uint8_t ah
Definition: registers.h:85
AR_PHY_MC_GAIN_CTRL
#define AR_PHY_MC_GAIN_CTRL
Definition: ar9003_phy.h:269
AR_PHY_9485_ANT_DIV_ALT_LNACONF
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF
Definition: ar9003_phy.h:280
AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
Definition: ar9003_phy.h:281
u32
uint32_t u32
Definition: stdint.h:24
AR_PHY_9485_ANT_DIV_MAIN_GAINTB
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB
Definition: ar9003_phy.h:286

References ah, ath_hw_antcomb_conf::alt_gaintb, ath_hw_antcomb_conf::alt_lna_conf, AR_PHY_9485_ANT_DIV_ALT_GAINTB, AR_PHY_9485_ANT_DIV_ALT_GAINTB_S, AR_PHY_9485_ANT_DIV_ALT_LNACONF, AR_PHY_9485_ANT_DIV_ALT_LNACONF_S, AR_PHY_9485_ANT_DIV_MAIN_GAINTB, AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S, AR_PHY_9485_ANT_DIV_MAIN_LNACONF, AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S, AR_PHY_9485_ANT_FAST_DIV_BIAS, AR_PHY_9485_ANT_FAST_DIV_BIAS_S, AR_PHY_MC_GAIN_CTRL, ath_hw_antcomb_conf::fast_div_bias, ath_hw_antcomb_conf::main_gaintb, ath_hw_antcomb_conf::main_lna_conf, REG_READ, and REG_WRITE.

Referenced by ar9003_hw_attach_phy_ops().

◆ ar9003_hw_attach_phy_ops()

void ar9003_hw_attach_phy_ops ( struct ath_hw *  ah)

Definition at line 1234 of file ath9k_ar9003_phy.c.

1235 {
1236  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1237  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1238  static const u32 ar9300_cca_regs[6] = {
1239  AR_PHY_CCA_0,
1240  AR_PHY_CCA_1,
1241  AR_PHY_CCA_2,
1242  AR_PHY_EXT_CCA,
1243  AR_PHY_EXT_CCA_1,
1244  AR_PHY_EXT_CCA_2,
1245  };
1246 
1247  priv_ops->rf_set_freq = ar9003_hw_set_channel;
1248  priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1249  priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1250  priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1251  priv_ops->init_bb = ar9003_hw_init_bb;
1252  priv_ops->process_ini = ar9003_hw_process_ini;
1253  priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1254  priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1255  priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1256  priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1257  priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1258  priv_ops->set_diversity = ar9003_hw_set_diversity;
1259  priv_ops->ani_control = ar9003_hw_ani_control;
1260  priv_ops->do_getnf = ar9003_hw_do_getnf;
1261  priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1262  priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1263 
1264  ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1265  ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1266 
1267  ar9003_hw_set_nf_limits(ah);
1268  ar9003_hw_set_radar_conf(ah);
1269  memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1270 }
ath_hw_private_ops::set_delta_slope
void(* set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:578
ar9003_hw_compute_pll_control
static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah __unused, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:453
ath_hw_private_ops::init_bb
void(* init_bb)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:572
ar9003_hw_set_radar_conf
static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:1178
ar9003_hw_do_getnf
static void ar9003_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: ath9k_ar9003_phy.c:1052
ar9003_hw_set_delta_slope
static void ar9003_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:710
ath_hw_private_ops::spur_mitigate_freq
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:564
ar9003_hw_mark_phy_inactive
static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:705
ath_hw_private_ops::rfbus_done
void(* rfbus_done)(struct ath_hw *ah)
Definition: hw.h:580
ar9003_hw_set_channel_regs
static void ar9003_hw_set_channel_regs(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:470
AR_PHY_EXT_CCA_1
#define AR_PHY_EXT_CCA_1
Definition: ar9003_phy.h:804
ath_hw_private_ops
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:551
ar9003_hw_set_nf_limits
static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:1080
ar9003_hw_set_rfmode
static void ar9003_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:688
ath_hw_ops::antdiv_comb_conf_set
void(* antdiv_comb_conf_set)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:642
ath_hw_private_ops::mark_phy_inactive
void(* mark_phy_inactive)(struct ath_hw *ah)
Definition: hw.h:577
ar9003_hw_ani_cache_ini_regs
static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:1095
AR_PHY_EXT_CCA
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:332
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
ath_hw_private_ops::process_ini
int(* process_ini)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:574
ar9003_hw_antdiv_comb_conf_get
static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: ath9k_ar9003_phy.c:1192
ath_hw_private_ops::ani_cache_ini_regs
void(* ani_cache_ini_regs)(struct ath_hw *ah)
Definition: hw.h:592
ar9003_hw_init_bb
static void ar9003_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:509
ar9003_hw_spur_mitigate
static void ar9003_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:446
ath_hw_ops
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:604
ar9003_hw_rfbus_done
static void ar9003_hw_rfbus_done(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:768
ar9003_hw_process_ini
static int ar9003_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: ath9k_ar9003_phy.c:621
ar9003_hw_set_diversity
static void ar9003_hw_set_diversity(struct ath_hw *ah, int value)
Definition: ath9k_ar9003_phy.c:781
AR_PHY_CCA_1
#define AR_PHY_CCA_1
Definition: ar9003_phy.h:825
ar9003_hw_rfbus_req
static int ar9003_hw_rfbus_req(struct ath_hw *ah)
Definition: ath9k_ar9003_phy.c:757
ar9003_hw_ani_control
static int ar9003_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: ath9k_ar9003_phy.c:791
ath_hw_private_ops::set_rfmode
void(* set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:576
ath_hw_private_ops::set_diversity
void(* set_diversity)(struct ath_hw *ah, int value)
Definition: hw.h:582
ath9k_hw_ops
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:885
ath_hw_private_ops::rfbus_req
int(* rfbus_req)(struct ath_hw *ah)
Definition: hw.h:579
ath_hw_private_ops::ani_control
int(* ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param)
Definition: hw.h:585
ath_hw_ops::antdiv_comb_conf_get
void(* antdiv_comb_conf_get)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:640
ath_hw_private_ops::rf_set_freq
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:562
ath_hw_private_ops::set_channel_regs
void(* set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:571
ah
uint8_t ah
Definition: registers.h:85
ath_hw_private_ops::compute_pll_control
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:583
ath_hw_private_ops::set_radar_params
void(* set_radar_params)(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: hw.h:588
ath9k_hw_private_ops
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:880
ath_hw_private_ops::do_getnf
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:587
ar9003_hw_antdiv_comb_conf_set
static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: ath9k_ar9003_phy.c:1208
ar9003_hw_set_radar_params
static void ar9003_hw_set_radar_params(struct ath_hw *ah, struct ath_hw_radar_conf *conf)
Definition: ath9k_ar9003_phy.c:1147
AR_PHY_EXT_CCA_2
#define AR_PHY_EXT_CCA_2
Definition: ar9003_phy.h:860
u32
uint32_t u32
Definition: stdint.h:24
AR_PHY_CCA_2
#define AR_PHY_CCA_2
Definition: ar9003_phy.h:880
AR_PHY_CCA_0
#define AR_PHY_CCA_0
Definition: ar9003_phy.h:262
ar9003_hw_set_channel
static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
ar9003_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan:
Definition: ath9k_ar9003_phy.c:74

References ah, ath_hw_private_ops::ani_cache_ini_regs, ath_hw_private_ops::ani_control, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9003_hw_ani_cache_ini_regs(), ar9003_hw_ani_control(), ar9003_hw_antdiv_comb_conf_get(), ar9003_hw_antdiv_comb_conf_set(), ar9003_hw_compute_pll_control(), ar9003_hw_do_getnf(), ar9003_hw_init_bb(), ar9003_hw_mark_phy_inactive(), ar9003_hw_process_ini(), ar9003_hw_rfbus_done(), ar9003_hw_rfbus_req(), ar9003_hw_set_channel(), ar9003_hw_set_channel_regs(), ar9003_hw_set_delta_slope(), ar9003_hw_set_diversity(), ar9003_hw_set_nf_limits(), ar9003_hw_set_radar_conf(), ar9003_hw_set_radar_params(), ar9003_hw_set_rfmode(), ar9003_hw_spur_mitigate(), AR_PHY_CCA_0, AR_PHY_CCA_1, AR_PHY_CCA_2, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_1, AR_PHY_EXT_CCA_2, ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, ath_hw_private_ops::init_bb, ath_hw_private_ops::mark_phy_inactive, memcpy(), ath_hw_private_ops::process_ini, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::rfbus_done, ath_hw_private_ops::rfbus_req, ath_hw_private_ops::set_channel_regs, ath_hw_private_ops::set_delta_slope, ath_hw_private_ops::set_diversity, ath_hw_private_ops::set_radar_params, ath_hw_private_ops::set_rfmode, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9003_hw_attach_ops().

◆ ar9003_hw_disable_phy_restart()

void ar9003_hw_disable_phy_restart ( struct ath_hw *  ah)

Definition at line 1272 of file ath9k_ar9003_phy.c.

1273 {
1274  u32 val;
1275 
1276  val = REG_READ(ah, AR_PHY_RESTART);
1277  val &= ~AR_PHY_RESTART_ENA;
1278 
1279  REG_WRITE(ah, AR_PHY_RESTART, val);
1280 }
val
void __asmcall int val
Definition: setjmp.h:12
AR_PHY_RESTART
#define AR_PHY_RESTART
Definition: ar9002_phy.h:265
AR_PHY_RESTART_ENA
#define AR_PHY_RESTART_ENA
Definition: ar9003_phy.h:411
REG_READ
#define REG_READ(_ah, _reg)
Definition: hw.h:81
REG_WRITE
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:78
ah
uint8_t ah
Definition: registers.h:85
u32
uint32_t u32
Definition: stdint.h:24

References ah, AR_PHY_RESTART, AR_PHY_RESTART_ENA, REG_READ, REG_WRITE, and val.

Referenced by ath9k_hw_reset().

Variable Documentation

◆ firstep_table

const int firstep_table[]
static
Initial value:
=
{ -4, -2, 0, 2, 4, 6, 8, 10, 12 }

Definition at line 27 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ cycpwrThr1_table

const int cycpwrThr1_table[]
static
Initial value:
=
{ -6, -4, -2, 0, 2, 4, 6, 8 }

Definition at line 31 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m1ThreshLow_off

const int m1ThreshLow_off = 127
static

Definition at line 38 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m2ThreshLow_off

const int m2ThreshLow_off = 127
static

Definition at line 39 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m1Thresh_off

const int m1Thresh_off = 127
static

Definition at line 40 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m2Thresh_off

const int m2Thresh_off = 127
static

Definition at line 41 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m2CountThr_off

const int m2CountThr_off = 31
static

Definition at line 42 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m2CountThrLow_off

const int m2CountThrLow_off = 63
static

Definition at line 43 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m1ThreshLowExt_off

const int m1ThreshLowExt_off = 127
static

Definition at line 44 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m2ThreshLowExt_off

const int m2ThreshLowExt_off = 127
static

Definition at line 45 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m1ThreshExt_off

const int m1ThreshExt_off = 127
static

Definition at line 46 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

◆ m2ThreshExt_off

const int m2ThreshExt_off = 127
static

Definition at line 47 of file ath9k_ar9003_phy.c.

Referenced by ar9003_hw_ani_control().

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