iPXE
dmfe.c
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1 /**************************************************************************
2 *
3 * dmfe.c -- Etherboot device driver for the Davicom
4 * DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast ethernet card
5 *
6 * Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * 02110-1301, USA.
22 *
23 * Portions of this code based on:
24 *
25 * dmfe.c: A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802
26 * NIC fast ethernet driver for Linux.
27 * Copyright (C) 1997 Sten Wang
28 * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
29 *
30 *
31 * REVISION HISTORY:
32 * ================
33 * v1.0 10-02-2004 timlegge Boots ltsp needs cleanup
34 *
35 * Indent Options: indent -kr -i8
36 *
37 *
38 ***************************************************************************/
39 
40 FILE_LICENCE ( GPL2_OR_LATER );
41 
42 /* to get some global routines like printf */
43 #include "etherboot.h"
44 /* to get the interface to the body of the program */
45 #include "nic.h"
46 /* to get the PCI support functions, if this is a PCI NIC */
47 #include <ipxe/pci.h>
48 #include <ipxe/ethernet.h>
49 
50 /* #define EDEBUG 1 */
51 #ifdef EDEBUG
52 #define dprintf(x) printf x
53 #else
54 #define dprintf(x)
55 #endif
56 
57 /* Condensed operations for readability. */
58 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
59 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
60 
61 /* Board/System/Debug information/definition ---------------- */
62 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
63 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
64 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
65 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
66 
67 #define DM9102_IO_SIZE 0x80
68 #define DM9102A_IO_SIZE 0x100
69 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
70 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
71 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
72 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
73 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
74 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
75 #define TX_BUF_ALLOC 0x600
76 #define RX_ALLOC_SIZE 0x620
77 #define DM910X_RESET 1
78 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
79 #define CR6_DEFAULT 0x00080000 /* HD */
80 #define CR7_DEFAULT 0x180c1
81 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
82 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
83 #define MAX_PACKET_SIZE 1514
84 #define DMFE_MAX_MULTICAST 14
85 #define RX_COPY_SIZE 100
86 #define MAX_CHECK_PACKET 0x8000
87 #define DM9801_NOISE_FLOOR 8
88 #define DM9802_NOISE_FLOOR 5
89 
90 #define DMFE_10MHF 0
91 #define DMFE_100MHF 1
92 #define DMFE_10MFD 4
93 #define DMFE_100MFD 5
94 #define DMFE_AUTO 8
95 #define DMFE_1M_HPNA 0x10
96 
97 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
98 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
99 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
100 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
101 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
102 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
103 
104 #define DMFE_TIMER_WUT (jiffies + HZ * 1) /* timer wakeup time : 1 second */
105 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
106 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
107 
108 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
109 
110 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
111 
112 
113 /* CR9 definition: SROM/MII */
114 #define CR9_SROM_READ 0x4800
115 #define CR9_SRCS 0x1
116 #define CR9_SRCLK 0x2
117 #define CR9_CRDOUT 0x8
118 #define SROM_DATA_0 0x0
119 #define SROM_DATA_1 0x4
120 #define PHY_DATA_1 0x20000
121 #define PHY_DATA_0 0x00000
122 #define MDCLKH 0x10000
123 
124 #define PHY_POWER_DOWN 0x800
125 
126 #define SROM_V41_CODE 0x14
127 
128 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
129 
130 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
131 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
132 
133 /* Sten Check */
134 #define DEVICE net_device
135 
136 /* Structure/enum declaration ------------------------------- */
137 struct tx_desc {
138  u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
139  void * tx_buf_ptr; /* Data for us */
141 } __attribute__ ((aligned(32)));
142 
143 struct rx_desc {
144  u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
145  void * rx_skb_ptr; /* Data for us */
147 } __attribute__ ((aligned(32)));
148 
149 static struct dmfe_private {
150  u32 chip_id; /* Chip vendor/Device ID */
151  u32 chip_revision; /* Chip revision */
153 // u32 cr5_data;
157 
158  u16 HPNA_command; /* For HPNA register 16 */
159  u16 HPNA_timer; /* For HPNA remote device check */
160  u16 NIC_capability; /* NIC media capability */
161  u16 PHY_reg4; /* Saved Phyxcer register 4 value */
162 
163  u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
164  u8 chip_type; /* Keep DM9102A chip type */
165  u8 media_mode; /* user specify media mode */
166  u8 op_mode; /* real work media mode */
168  u8 dm910x_chk_mode; /* Operating mode check */
169 
170  /* NIC SROM data */
171  unsigned char srom[128];
172  /* Etherboot Only */
175 } dfx;
176 
177 static struct dmfe_private *db;
178 
180  DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
181  DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
182  DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 =
183  0x70,
184  DCR15 = 0x78
185 };
186 
188  CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
189  CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
190  CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
191 };
192 
193 /* Global variable declaration ----------------------------- */
195 
196 static unsigned char dmfe_media_mode = DMFE_AUTO;
198 
199 /* For module input parameter */
200 static u8 chkmode = 1;
201 static u8 HPNA_mode; /* Default: Low Power/High Speed */
202 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
203 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
204 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
205 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
206  4: TX pause packet */
207 
208 
209 /**********************************************
210 * Descriptor Ring and Buffer defination
211 ***********************************************/
212 struct {
213  struct tx_desc txd[TX_DESC_CNT] __attribute__ ((aligned(32)));
214  unsigned char txb[TX_BUF_ALLOC * TX_DESC_CNT]
215  __attribute__ ((aligned(32)));
216  struct rx_desc rxd[RX_DESC_CNT] __attribute__ ((aligned(32)));
217  unsigned char rxb[RX_ALLOC_SIZE * RX_DESC_CNT]
218  __attribute__ ((aligned(32)));
219 } dmfe_bufs __shared;
220 #define txd dmfe_bufs.txd
221 #define txb dmfe_bufs.txb
222 #define rxd dmfe_bufs.rxd
223 #define rxb dmfe_bufs.rxb
224 
225 /* NIC specific static variables go here */
226 static long int BASE;
227 
228 static u16 read_srom_word(long ioaddr, int offset);
229 static void dmfe_init_dm910x(struct nic *nic);
230 static void dmfe_descriptor_init(struct nic *, unsigned long ioaddr);
231 static void update_cr6(u32, unsigned long);
232 static void send_filter_frame(struct nic *nic);
233 static void dm9132_id_table(struct nic *nic);
234 
235 static u16 phy_read(unsigned long, u8, u8, u32);
236 static void phy_write(unsigned long, u8, u8, u16, u32);
237 static void phy_write_1bit(unsigned long, u32);
238 static u16 phy_read_1bit(unsigned long);
239 static void dmfe_set_phyxcer(struct nic *nic);
240 
241 static void dmfe_parse_srom(struct nic *nic);
242 static void dmfe_program_DM9801(struct nic *nic, int);
243 static void dmfe_program_DM9802(struct nic *nic);
244 
245 static void dmfe_reset(struct nic *nic)
246 {
247  /* system variable init */
249 
250  db->NIC_capability = 0xf; /* All capability */
251  db->PHY_reg4 = 0x1e0;
252 
253  /* CR6 operation mode decision */
254  if (!chkmode || (db->chip_id == PCI_DM9132_ID) ||
255  (db->chip_revision >= 0x02000030)) {
258  db->dm910x_chk_mode = 4; /* Enter the normal mode */
259  } else {
260  db->cr6_data |= CR6_SFT; /* Store & Forward mode */
261  db->cr0_data = 0;
262  db->dm910x_chk_mode = 1; /* Enter the check mode */
263  }
264  /* Initialize DM910X board */
266 
267  return;
268 }
269 
270 /* Initialize DM910X board
271  * Reset DM910X board
272  * Initialize TX/Rx descriptor chain structure
273  * Send the set-up frame
274  * Enable Tx/Rx machine
275  */
276 
277 static void dmfe_init_dm910x(struct nic *nic)
278 {
279  unsigned long ioaddr = BASE;
280 
281  /* Reset DM910x MAC controller */
282  outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
283  udelay(100);
284  outl(db->cr0_data, ioaddr + DCR0);
285  udelay(5);
286 
287  /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
288  db->phy_addr = 1;
289 
290  /* Parser SROM and media mode */
293 
294  /* RESET Phyxcer Chip by GPR port bit 7 */
295  outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
296  if (db->chip_id == PCI_DM9009_ID) {
297  outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
298  mdelay(300); /* Delay 300 ms */
299  }
300  outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
301 
302  /* Process Phyxcer Media Mode */
303  if (!(db->media_mode & 0x10)) /* Force 1M mode */
305 
306  /* Media Mode Process */
307  if (!(db->media_mode & DMFE_AUTO))
308  db->op_mode = db->media_mode; /* Force Mode */
309 
310  /* Initiliaze Transmit/Receive descriptor and CR3/4 */
312 
313  /* tx descriptor start pointer */
314  outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
315 
316  /* rx descriptor start pointer */
317  outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
318 
319  /* Init CR6 to program DM910x operation */
321 
322  /* Send setup frame */
323  if (db->chip_id == PCI_DM9132_ID) {
324  dm9132_id_table(nic); /* DM9132 */
325  } else {
326  send_filter_frame(nic); /* DM9102/DM9102A */
327  }
328 
329  /* Init CR7, interrupt active bit */
331  outl(db->cr7_data, ioaddr + DCR7);
332  /* Init CR15, Tx jabber and Rx watchdog timer */
334  /* Enable DM910X Tx/Rx function */
335  db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
337 }
338 #ifdef EDEBUG
339 void hex_dump(const char *data, const unsigned int len);
340 #endif
341 /**************************************************************************
342 POLL - Wait for a frame
343 ***************************************************************************/
344 static int dmfe_poll(struct nic *nic, int retrieve)
345 {
346  u32 rdes0;
347  int entry = db->cur_rx % RX_DESC_CNT;
348  int rxlen;
350  if (rdes0 & 0x80000000)
351  return 0;
352 
353  if (!retrieve)
354  return 1;
355 
356  if ((rdes0 & 0x300) != 0x300) {
357  /* A packet without First/Last flag */
358  printf("strange Packet\n");
359  rxd[entry].rdes0 = cpu_to_le32(0x80000000);
360  return 0;
361  } else {
362  /* A packet with First/Last flag */
363  rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
364  /* error summary bit check */
365  if (rdes0 & 0x8000) {
366  printf("Error\n");
367  return 0;
368  }
369  if (!(rdes0 & 0x8000) ||
370  ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
371  if (db->dm910x_chk_mode & 1)
372  printf("Silly check mode\n");
373 
374  nic->packetlen = rxlen;
376  nic->packetlen);
377  }
378  }
379  rxd[entry].rdes0 = cpu_to_le32(0x80000000);
380  db->cur_rx++;
381  return 1;
382 }
383 
384 static void dmfe_irq(struct nic *nic __unused, irq_action_t action __unused)
385 {
386  switch ( action ) {
387  case DISABLE :
388  break;
389  case ENABLE :
390  break;
391  case FORCE :
392  break;
393  }
394 }
395 
396 /**************************************************************************
397 TRANSMIT - Transmit a frame
398 ***************************************************************************/
399 static void dmfe_transmit(struct nic *nic,
400  const char *dest, /* Destination */
401  unsigned int type, /* Type */
402  unsigned int size, /* size */
403  const char *packet) /* Packet */
404 {
405  u16 nstype;
406  u8 *ptxb;
407 
408  ptxb = &txb[db->cur_tx];
409 
410  /* Stop Tx */
411  outl(0, BASE + DCR7);
412  memcpy(ptxb, dest, ETH_ALEN);
413  memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
414  nstype = htons((u16) type);
415  memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
416  memcpy(ptxb + ETH_HLEN, packet, size);
417 
418  size += ETH_HLEN;
419  while (size < ETH_ZLEN)
420  ptxb[size++] = '\0';
421 
422  /* setup the transmit descriptor */
423  txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size);
424  txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000); /* give ownership to device */
425 
426  /* immediate transmit demand */
427  outl(0x1, BASE + DCR1);
428  outl(db->cr7_data, BASE + DCR7);
429 
430  /* Point to next TX descriptor */
431  db->cur_tx++;
432  db->cur_tx = db->cur_tx % TX_DESC_CNT;
433 }
434 
435 /**************************************************************************
436 DISABLE - Turn off ethernet interface
437 ***************************************************************************/
438 static void dmfe_disable ( struct nic *nic __unused ) {
439  /* Reset & stop DM910X board */
441  udelay(5);
442  phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
443 
444 }
445 
446 /**************************************************************************
447 PROBE - Look for an adapter, this routine's visible to the outside
448 ***************************************************************************/
449 
450 #define board_found 1
451 #define valid_link 0
452 static int dmfe_probe ( struct nic *nic, struct pci_device *pci ) {
453 
454  uint32_t dev_rev, pci_pmr;
455  int i;
456 
457  if (pci->ioaddr == 0)
458  return 0;
459 
460  BASE = pci->ioaddr;
461  printf("dmfe.c: Found %s Vendor=0x%hX Device=0x%hX\n",
462  pci->id->name, pci->vendor, pci->device);
463 
464  /* Read Chip revision */
465  pci_read_config_dword(pci, PCI_REVISION, &dev_rev);
466  dprintf(("Revision %lX\n", dev_rev));
467 
468  /* point to private storage */
469  db = &dfx;
470 
471  db->chip_id = ((u32) pci->device << 16) | pci->vendor;
473  db->chip_revision = dev_rev;
474 
475  pci_read_config_dword(pci, 0x50, &pci_pmr);
476  pci_pmr &= 0x70000;
477  if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031))
478  db->chip_type = 1; /* DM9102A E3 */
479  else
480  db->chip_type = 0;
481 
482  dprintf(("Chip type : %d\n", db->chip_type));
483 
484  /* read 64 word srom data */
485  for (i = 0; i < 64; i++)
486  ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i));
487 
488  /* Set Node address */
489  for (i = 0; i < 6; i++)
490  nic->node_addr[i] = db->srom[20 + i];
491 
492  /* Print out some hardware info */
493  DBG ( "%s: %s at ioaddr %4.4lx\n",
494  pci->id->name, eth_ntoa ( nic->node_addr ), BASE );
495 
496  /* Set the card as PCI Bus Master */
497  adjust_pci_device(pci);
498 
499  dmfe_reset(nic);
500 
501  nic->irqno = 0;
502  nic->ioaddr = pci->ioaddr;
503 
504  /* point to NIC specific routines */
506 
507  return 1;
508 }
509 
510 /*
511  * Initialize transmit/Receive descriptor
512  * Using Chain structure, and allocate Tx/Rx buffer
513  */
514 
515 static void dmfe_descriptor_init(struct nic *nic __unused, unsigned long ioaddr)
516 {
517  int i;
518  db->cur_tx = 0;
519  db->cur_rx = 0;
520 
521  /* tx descriptor start pointer */
522  outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
523 
524  /* rx descriptor start pointer */
525  outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
526 
527  /* Init Transmit chain */
528  for (i = 0; i < TX_DESC_CNT; i++) {
529  txd[i].tx_buf_ptr = &txb[i];
530  txd[i].tdes0 = cpu_to_le32(0);
531  txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
532  txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
533  txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
534  txd[i].next_tx_desc = &txd[i + 1];
535  }
536  /* Mark the last entry as wrapping the ring */
537  txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
538  txd[i - 1].next_tx_desc = &txd[0];
539 
540  /* receive descriptor chain */
541  for (i = 0; i < RX_DESC_CNT; i++) {
542  rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
543  rxd[i].rdes0 = cpu_to_le32(0x80000000);
544  rxd[i].rdes1 = cpu_to_le32(0x01000600);
545  rxd[i].rdes2 =
547  rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
548  rxd[i].next_rx_desc = &rxd[i + 1];
549  }
550  /* Mark the last entry as wrapping the ring */
551  rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
552  rxd[i - 1].next_rx_desc = &rxd[0];
553 
554 }
555 
556 /*
557  * Update CR6 value
558  * Firstly stop DM910X , then written value and start
559  */
560 
561 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
562 {
563  u32 cr6_tmp;
564 
565  cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
566  outl(cr6_tmp, ioaddr + DCR6);
567  udelay(5);
568  outl(cr6_data, ioaddr + DCR6);
569  udelay(5);
570 }
571 
572 
573 /*
574  * Send a setup frame for DM9132
575  * This setup frame initialize DM910X address filter mode
576 */
577 
578 static void dm9132_id_table(struct nic *nic __unused)
579 {
580 #ifdef LINUX
581  u16 *addrptr;
582  u8 dmi_addr[8];
583  unsigned long ioaddr = BASE + 0xc0; /* ID Table */
584  u32 hash_val;
585  u16 i, hash_table[4];
586 #endif
587  dprintf(("dm9132_id_table\n"));
588 
589  printf("FIXME: This function is broken. If you have this card contact "
590  "Timothy Legge at the etherboot-user list\n");
591 
592 #ifdef LINUX
593  //DMFE_DBUG(0, "dm9132_id_table()", 0);
594 
595  /* Node address */
596  addrptr = (u16 *) nic->node_addr;
597  outw(addrptr[0], ioaddr);
598  ioaddr += 4;
599  outw(addrptr[1], ioaddr);
600  ioaddr += 4;
601  outw(addrptr[2], ioaddr);
602  ioaddr += 4;
603 
604  /* Clear Hash Table */
605  for (i = 0; i < 4; i++)
606  hash_table[i] = 0x0;
607 
608  /* broadcast address */
609  hash_table[3] = 0x8000;
610 
611  /* the multicast address in Hash Table : 64 bits */
612  for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
613  hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
614  hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
615  }
616 
617  /* Write the hash table to MAC MD table */
618  for (i = 0; i < 4; i++, ioaddr += 4)
619  outw(hash_table[i], ioaddr);
620 #endif
621 }
622 
623 
624 /*
625  * Send a setup frame for DM9102/DM9102A
626  * This setup frame initialize DM910X address filter mode
627  */
628 
629 static void send_filter_frame(struct nic *nic)
630 {
631 
632  u8 *ptxb;
633  int i;
634 
635  dprintf(("send_filter_frame\n"));
636  /* point to the current txb incase multiple tx_rings are used */
637  ptxb = &txb[db->cur_tx];
638 
639  /* construct perfect filter frame with mac address as first match
640  and broadcast address for all others */
641  for (i = 0; i < 192; i++)
642  ptxb[i] = 0xFF;
643  ptxb[0] = nic->node_addr[0];
644  ptxb[1] = nic->node_addr[1];
645  ptxb[4] = nic->node_addr[2];
646  ptxb[5] = nic->node_addr[3];
647  ptxb[8] = nic->node_addr[4];
648  ptxb[9] = nic->node_addr[5];
649 
650  /* prepare the setup frame */
651  txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0);
652  txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);
653  update_cr6(db->cr6_data | 0x2000, BASE);
654  outl(0x1, BASE + DCR1); /* Issue Tx polling */
656  db->cur_tx++;
657 }
658 
659 /*
660  * Read one word data from the serial ROM
661  */
662 
663 static u16 read_srom_word(long ioaddr, int offset)
664 {
665  int i;
666  u16 srom_data = 0;
667  long cr9_ioaddr = ioaddr + DCR9;
668 
669  outl(CR9_SROM_READ, cr9_ioaddr);
670  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
671 
672  /* Send the Read Command 110b */
673  SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
674  SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
675  SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
676 
677  /* Send the offset */
678  for (i = 5; i >= 0; i--) {
679  srom_data =
680  (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
681  SROM_CLK_WRITE(srom_data, cr9_ioaddr);
682  }
683 
684  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
685 
686  for (i = 16; i > 0; i--) {
687  outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
688  udelay(5);
689  srom_data =
690  (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1
691  : 0);
692  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
693  udelay(5);
694  }
695 
696  outl(CR9_SROM_READ, cr9_ioaddr);
697  return srom_data;
698 }
699 
700 
701 /*
702  * Auto sense the media mode
703  */
704 
705 #if 0 /* not used */
706 static u8 dmfe_sense_speed(struct nic *nic __unused)
707 {
708  u8 ErrFlag = 0;
709  u16 phy_mode;
710 
711  /* CR6 bit18=0, select 10/100M */
712  update_cr6((db->cr6_data & ~0x40000), BASE);
713 
714  phy_mode = phy_read(BASE, db->phy_addr, 1, db->chip_id);
715  phy_mode = phy_read(BASE, db->phy_addr, 1, db->chip_id);
716 
717  if ((phy_mode & 0x24) == 0x24) {
718  if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
719  phy_mode =
720  phy_read(BASE, db->phy_addr, 7,
721  db->chip_id) & 0xf000;
722  else /* DM9102/DM9102A */
723  phy_mode =
724  phy_read(BASE, db->phy_addr, 17,
725  db->chip_id) & 0xf000;
726  /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
727  switch (phy_mode) {
728  case 0x1000:
729  db->op_mode = DMFE_10MHF;
730  break;
731  case 0x2000:
732  db->op_mode = DMFE_10MFD;
733  break;
734  case 0x4000:
736  break;
737  case 0x8000:
739  break;
740  default:
741  db->op_mode = DMFE_10MHF;
742  ErrFlag = 1;
743  break;
744  }
745  } else {
746  db->op_mode = DMFE_10MHF;
747  //DMFE_DBUG(0, "Link Failed :", phy_mode);
748  ErrFlag = 1;
749  }
750 
751  return ErrFlag;
752 }
753 #endif
754 
755 /*
756  * Set 10/100 phyxcer capability
757  * AUTO mode : phyxcer register4 is NIC capability
758  * Force mode: phyxcer register4 is the force media
759  */
760 
761 static void dmfe_set_phyxcer(struct nic *nic __unused)
762 {
763  u16 phy_reg;
764 
765  /* Select 10/100M phyxcer */
766  db->cr6_data &= ~0x40000;
768 
769  /* DM9009 Chip: Phyxcer reg18 bit12=0 */
770  if (db->chip_id == PCI_DM9009_ID) {
771  phy_reg =
772  phy_read(BASE, db->phy_addr, 18,
773  db->chip_id) & ~0x1000;
774  phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id);
775  }
776 
777  /* Phyxcer capability setting */
778  phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0;
779 
780  if (db->media_mode & DMFE_AUTO) {
781  /* AUTO Mode */
782  phy_reg |= db->PHY_reg4;
783  } else {
784  /* Force Mode */
785  switch (db->media_mode) {
786  case DMFE_10MHF:
787  phy_reg |= 0x20;
788  break;
789  case DMFE_10MFD:
790  phy_reg |= 0x40;
791  break;
792  case DMFE_100MHF:
793  phy_reg |= 0x80;
794  break;
795  case DMFE_100MFD:
796  phy_reg |= 0x100;
797  break;
798  }
799  if (db->chip_id == PCI_DM9009_ID)
800  phy_reg &= 0x61;
801  }
802 
803  /* Write new capability to Phyxcer Reg4 */
804  if (!(phy_reg & 0x01e0)) {
805  phy_reg |= db->PHY_reg4;
806  db->media_mode |= DMFE_AUTO;
807  }
808  phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id);
809 
810  /* Restart Auto-Negotiation */
811  if (db->chip_type && (db->chip_id == PCI_DM9102_ID))
812  phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id);
813  if (!db->chip_type)
814  phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id);
815 }
816 
817 
818 /*
819  * Process op-mode
820  * AUTO mode : PHY controller in Auto-negotiation Mode
821  * Force mode: PHY controller in force mode with HUB
822  * N-way force capability with SWITCH
823  */
824 
825 #if 0 /* not used */
826 static void dmfe_process_mode(struct nic *nic __unused)
827 {
828  u16 phy_reg;
829 
830  /* Full Duplex Mode Check */
831  if (db->op_mode & 0x4)
832  db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
833  else
834  db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
835 
836  /* Transciver Selection */
837  if (db->op_mode & 0x10) /* 1M HomePNA */
838  db->cr6_data |= 0x40000; /* External MII select */
839  else
840  db->cr6_data &= ~0x40000; /* Internal 10/100 transciver */
841 
843 
844  /* 10/100M phyxcer force mode need */
845  if (!(db->media_mode & 0x18)) {
846  /* Forece Mode */
847  phy_reg = phy_read(BASE, db->phy_addr, 6, db->chip_id);
848  if (!(phy_reg & 0x1)) {
849  /* parter without N-Way capability */
850  phy_reg = 0x0;
851  switch (db->op_mode) {
852  case DMFE_10MHF:
853  phy_reg = 0x0;
854  break;
855  case DMFE_10MFD:
856  phy_reg = 0x100;
857  break;
858  case DMFE_100MHF:
859  phy_reg = 0x2000;
860  break;
861  case DMFE_100MFD:
862  phy_reg = 0x2100;
863  break;
864  }
865  phy_write(BASE, db->phy_addr, 0, phy_reg,
866  db->chip_id);
867  if (db->chip_type
868  && (db->chip_id == PCI_DM9102_ID))
869  mdelay(20);
870  phy_write(BASE, db->phy_addr, 0, phy_reg,
871  db->chip_id);
872  }
873  }
874 }
875 #endif
876 
877 /*
878  * Write a word to Phy register
879  */
880 
881 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
882  u16 phy_data, u32 chip_id)
883 {
884  u16 i;
885  unsigned long ioaddr;
886 
887  if (chip_id == PCI_DM9132_ID) {
888  ioaddr = iobase + 0x80 + offset * 4;
889  outw(phy_data, ioaddr);
890  } else {
891  /* DM9102/DM9102A Chip */
892  ioaddr = iobase + DCR9;
893 
894  /* Send 33 synchronization clock to Phy controller */
895  for (i = 0; i < 35; i++)
897 
898  /* Send start command(01) to Phy */
901 
902  /* Send write command(01) to Phy */
905 
906  /* Send Phy address */
907  for (i = 0x10; i > 0; i = i >> 1)
909  phy_addr & i ? PHY_DATA_1 :
910  PHY_DATA_0);
911 
912  /* Send register address */
913  for (i = 0x10; i > 0; i = i >> 1)
915  offset & i ? PHY_DATA_1 :
916  PHY_DATA_0);
917 
918  /* written trasnition */
921 
922  /* Write a word data to PHY controller */
923  for (i = 0x8000; i > 0; i >>= 1)
925  phy_data & i ? PHY_DATA_1 :
926  PHY_DATA_0);
927  }
928 }
929 
930 
931 /*
932  * Read a word data from phy register
933  */
934 
935 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
936  u32 chip_id)
937 {
938  int i;
939  u16 phy_data;
940  unsigned long ioaddr;
941 
942  if (chip_id == PCI_DM9132_ID) {
943  /* DM9132 Chip */
944  ioaddr = iobase + 0x80 + offset * 4;
945  phy_data = inw(ioaddr);
946  } else {
947  /* DM9102/DM9102A Chip */
948  ioaddr = iobase + DCR9;
949 
950  /* Send 33 synchronization clock to Phy controller */
951  for (i = 0; i < 35; i++)
953 
954  /* Send start command(01) to Phy */
957 
958  /* Send read command(10) to Phy */
961 
962  /* Send Phy address */
963  for (i = 0x10; i > 0; i = i >> 1)
965  phy_addr & i ? PHY_DATA_1 :
966  PHY_DATA_0);
967 
968  /* Send register address */
969  for (i = 0x10; i > 0; i = i >> 1)
971  offset & i ? PHY_DATA_1 :
972  PHY_DATA_0);
973 
974  /* Skip transition state */
976 
977  /* read 16bit data */
978  for (phy_data = 0, i = 0; i < 16; i++) {
979  phy_data <<= 1;
980  phy_data |= phy_read_1bit(ioaddr);
981  }
982  }
983 
984  return phy_data;
985 }
986 
987 
988 /*
989  * Write one bit data to Phy Controller
990  */
991 
992 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
993 {
994  outl(phy_data, ioaddr); /* MII Clock Low */
995  udelay(1);
996  outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
997  udelay(1);
998  outl(phy_data, ioaddr); /* MII Clock Low */
999  udelay(1);
1000 }
1001 
1002 
1003 /*
1004  * Read one bit phy data from PHY controller
1005  */
1006 
1007 static u16 phy_read_1bit(unsigned long ioaddr)
1008 {
1009  u16 phy_data;
1010 
1011  outl(0x50000, ioaddr);
1012  udelay(1);
1013  phy_data = (inl(ioaddr) >> 19) & 0x1;
1014  outl(0x40000, ioaddr);
1015  udelay(1);
1016 
1017  return phy_data;
1018 }
1019 
1020 
1021 /*
1022  * Parser SROM and media mode
1023  */
1024 
1025 static void dmfe_parse_srom(struct nic *nic)
1026 {
1027  unsigned char *srom = db->srom;
1028  int dmfe_mode, tmp_reg;
1029 
1030  /* Init CR15 */
1032 
1033  /* Check SROM Version */
1034  if (((int) srom[18] & 0xff) == SROM_V41_CODE) {
1035  /* SROM V4.01 */
1036  /* Get NIC support media mode */
1037  db->NIC_capability = *(u16 *) (srom + 34);
1038  db->PHY_reg4 = 0;
1039  for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1040  switch (db->NIC_capability & tmp_reg) {
1041  case 0x1:
1042  db->PHY_reg4 |= 0x0020;
1043  break;
1044  case 0x2:
1045  db->PHY_reg4 |= 0x0040;
1046  break;
1047  case 0x4:
1048  db->PHY_reg4 |= 0x0080;
1049  break;
1050  case 0x8:
1051  db->PHY_reg4 |= 0x0100;
1052  break;
1053  }
1054  }
1055 
1056  /* Media Mode Force or not check */
1057  dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36);
1058  switch (dmfe_mode) {
1059  case 0x4:
1061  break; /* 100MHF */
1062  case 0x2:
1064  break; /* 10MFD */
1065  case 0x8:
1067  break; /* 100MFD */
1068  case 0x100:
1069  case 0x200:
1071  break; /* HomePNA */
1072  }
1073 
1074  /* Special Function setting */
1075  /* VLAN function */
1076  if ((SF_mode & 0x1) || (srom[43] & 0x80))
1077  db->cr15_data |= 0x40;
1078 
1079  /* Flow Control */
1080  if ((SF_mode & 0x2) || (srom[40] & 0x1))
1081  db->cr15_data |= 0x400;
1082 
1083  /* TX pause packet */
1084  if ((SF_mode & 0x4) || (srom[40] & 0xe))
1085  db->cr15_data |= 0x9800;
1086  }
1087 
1088  /* Parse HPNA parameter */
1089  db->HPNA_command = 1;
1090 
1091  /* Accept remote command or not */
1092  if (HPNA_rx_cmd == 0)
1093  db->HPNA_command |= 0x8000;
1094 
1095  /* Issue remote command & operation mode */
1096  if (HPNA_tx_cmd == 1)
1097  switch (HPNA_mode) { /* Issue Remote Command */
1098  case 0:
1099  db->HPNA_command |= 0x0904;
1100  break;
1101  case 1:
1102  db->HPNA_command |= 0x0a00;
1103  break;
1104  case 2:
1105  db->HPNA_command |= 0x0506;
1106  break;
1107  case 3:
1108  db->HPNA_command |= 0x0602;
1109  break;
1110  } else
1111  switch (HPNA_mode) { /* Don't Issue */
1112  case 0:
1113  db->HPNA_command |= 0x0004;
1114  break;
1115  case 1:
1116  db->HPNA_command |= 0x0000;
1117  break;
1118  case 2:
1119  db->HPNA_command |= 0x0006;
1120  break;
1121  case 3:
1122  db->HPNA_command |= 0x0002;
1123  break;
1124  }
1125 
1126  /* Check DM9801 or DM9802 present or not */
1127  db->HPNA_present = 0;
1128  update_cr6(db->cr6_data | 0x40000, BASE);
1129  tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id);
1130  if ((tmp_reg & 0xfff0) == 0xb900) {
1131  /* DM9801 or DM9802 present */
1132  db->HPNA_timer = 8;
1133  if (phy_read(BASE, db->phy_addr, 31, db->chip_id) ==
1134  0x4404) {
1135  /* DM9801 HomeRun */
1136  db->HPNA_present = 1;
1137  dmfe_program_DM9801(nic, tmp_reg);
1138  } else {
1139  /* DM9802 LongRun */
1140  db->HPNA_present = 2;
1142  }
1143  }
1144 
1145 }
1146 
1147 /*
1148  * Init HomeRun DM9801
1149  */
1150 
1151 static void dmfe_program_DM9801(struct nic *nic __unused, int HPNA_rev)
1152 {
1153  u32 reg17, reg25;
1154 
1155  if (!HPNA_NoiseFloor)
1157  switch (HPNA_rev) {
1158  case 0xb900: /* DM9801 E3 */
1159  db->HPNA_command |= 0x1000;
1160  reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id);
1161  reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1162  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1163  break;
1164  case 0xb901: /* DM9801 E4 */
1165  reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1166  reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1167  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1168  reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1169  break;
1170  case 0xb902: /* DM9801 E5 */
1171  case 0xb903: /* DM9801 E6 */
1172  default:
1173  db->HPNA_command |= 0x1000;
1174  reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1175  reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1176  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1177  reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1178  break;
1179  }
1181  phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id);
1182  phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id);
1183 }
1184 
1185 
1186 /*
1187  * Init HomeRun DM9802
1188  */
1189 
1190 static void dmfe_program_DM9802(struct nic *nic __unused)
1191 {
1192  u32 phy_reg;
1193 
1194  if (!HPNA_NoiseFloor)
1197  phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1198  phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor;
1199  phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id);
1200 }
1201 
1202 static struct nic_operations dmfe_operations = {
1204  .poll = dmfe_poll,
1205  .transmit = dmfe_transmit,
1206  .irq = dmfe_irq,
1207 
1208 };
1209 
1210 static struct pci_device_id dmfe_nics[] = {
1211  PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
1212  PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
1213  PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
1214  PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0), /* Needs probably some fixing */
1215 };
1216 
1217 PCI_DRIVER ( dmfe_driver, dmfe_nics, PCI_NO_CLASS );
1218 
1219 DRIVER ( "DMFE/PCI", nic_driver, pci_driver, dmfe_driver,
1221 
1222 /*
1223  * Local variables:
1224  * c-basic-offset: 8
1225  * c-indent-level: 8
1226  * tab-width: 8
1227  * End:
1228  */
unsigned char irqno
Definition: nic.h:56
#define u16
Definition: vga.h:20
static void phy_write_1bit(unsigned long, u32)
Definition: dmfe.c:992
uint16_t u16
Definition: stdint.h:21
#define DMFE_1M_HPNA
Definition: dmfe.c:95
#define __attribute__(x)
Definition: compiler.h:10
Definition: nic.h:35
u8 op_mode
Definition: dmfe.c:166
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
A PCI driver.
Definition: pci.h:224
Definition: sis900.h:35
struct @37 __shared
#define CR9_SRCLK
Definition: dmfe.c:116
#define TX_BUF_ALLOC
Definition: dmfe.c:75
FILE_LICENCE(GPL2_OR_LATER)
#define le32_to_cpu(value)
Definition: byteswap.h:113
static unsigned char dmfe_media_mode
Definition: dmfe.c:196
#define virt_to_le32desc(addr)
Definition: dmfe.c:58
u32 cr6_data
Definition: dmfe.c:154
u8 cur_rx
Definition: dmfe.c:174
#define outw(data, io_addr)
Definition: io.h:319
#define DMFE_100MFD
Definition: dmfe.c:93
unsigned long ioaddr
I/O address.
Definition: pci.h:200
static u8 HPNA_rx_cmd
Definition: dmfe.c:202
Definition: dmfe.c:188
Definition: dmfe.c:189
Definition: dmfe.c:180
Definition: dmfe.c:182
u8 cur_tx
Definition: dmfe.c:173
#define TX_DESC_CNT
Definition: dmfe.c:70
Definition: dmfe.c:189
#define rxb
Definition: dmfe.c:223
Definition: dmfe.c:181
uint8_t type
Type.
Definition: ena.h:16
static int dmfe_probe(struct nic *nic, struct pci_device *pci)
Definition: dmfe.c:452
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:881
u8 HPNA_present
Definition: dmfe.c:163
Definition: dmfe.c:180
#define PCI_BASE_ADDRESS_0
Definition: pci.h:61
static void dmfe_parse_srom(struct nic *nic)
Definition: dmfe.c:1025
u32 chip_id
Definition: dmfe.c:150
unsigned char srom[128]
Definition: dmfe.c:171
#define rxd
Definition: dmfe.c:222
#define DM9802_NOISE_FLOOR
Definition: dmfe.c:88
u32 rdes3
Definition: dmfe.c:144
#define PHY_DATA_0
Definition: dmfe.c:121
Definition: dmfe.c:181
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
Definition: dmfe.c:180
#define RX_ALLOC_SIZE
Definition: dmfe.c:76
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
u16 NIC_capability
Definition: dmfe.c:160
static void dm9132_id_table(struct nic *nic)
u32 tdes3
Definition: dmfe.c:138
#define SROM_CLK_WRITE(data, ioaddr)
Definition: dmfe.c:128
static u8 HPNA_tx_cmd
Definition: dmfe.c:203
void * rx_skb_ptr
Definition: dmfe.c:145
PCI_DRIVER(dmfe_driver, dmfe_nics, PCI_NO_CLASS)
u32 cr15_data
Definition: dmfe.c:156
#define PHY_DATA_1
Definition: dmfe.c:120
static unsigned long ioaddr
Definition: davicom.c:129
void * memcpy(void *dest, const void *src, size_t len) __nonnull
unsigned int ioaddr
Definition: nic.h:55
static u8 HPNA_mode
Definition: dmfe.c:201
u32 tdes2
Definition: dmfe.c:138
u32 chip_revision
Definition: dmfe.c:151
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define SROM_V41_CODE
Definition: dmfe.c:126
uint16_t device
Device ID.
Definition: pci.h:204
#define ETH_HLEN
Definition: if_ether.h:9
DRIVER("DMFE/PCI", nic_driver, pci_driver, dmfe_driver, dmfe_probe, dmfe_disable)
Ethernet protocol.
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
Definition: dmfe.c:182
Definition: dmfe.c:184
static u8 chkmode
Definition: dmfe.c:200
Definition: dmfe.c:188
#define u32
Definition: vga.h:21
#define DMFE_TXTH_256
Definition: dmfe.c:100
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
A 16-bit general register.
Definition: registers.h:24
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
u8 dm910x_chk_mode
Definition: dmfe.c:168
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
irq_action_t
Definition: nic.h:34
#define txd
Definition: dmfe.c:220
static void send_filter_frame(struct nic *nic)
Definition: dmfe.c:629
#define SROM_DATA_1
Definition: dmfe.c:119
Definition: dmfe.c:180
static struct pci_device_id dmfe_nics[]
Definition: dmfe.c:1210
#define DM910X_RESET
Definition: dmfe.c:77
static void * dest
Definition: strings.h:176
#define cpu_to_le32(value)
Definition: byteswap.h:107
u32 rdes2
Definition: dmfe.c:144
unsigned int packetlen
Definition: nic.h:54
#define DMFE_10MFD
Definition: dmfe.c:92
static void dmfe_transmit(struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *packet)
Definition: dmfe.c:399
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
Definition: dmfe.c:190
#define RX_DESC_CNT
Definition: dmfe.c:71
u32 tdes0
Definition: dmfe.c:138
struct tx_desc * next_tx_desc
Definition: dmfe.c:140
#define outl(data, io_addr)
Definition: io.h:329
PCI bus.
#define CR9_CRDOUT
Definition: dmfe.c:117
A PCI device.
Definition: pci.h:187
static struct dmfe_private dfx
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
Definition: dmfe.c:181
#define DM9801_NOISE_FLOOR
Definition: dmfe.c:87
#define CR7_DEFAULT
Definition: dmfe.c:80
#define CR6_DEFAULT
Definition: dmfe.c:79
#define dprintf(x)
Definition: dmfe.c:54
static u32 dmfe_cr6_user_set
Definition: dmfe.c:197
Definition: dmfe.c:188
#define DMFE_AUTO
Definition: dmfe.c:94
void * tx_buf_ptr
Definition: dmfe.c:139
struct rx_desc * next_rx_desc
Definition: dmfe.c:146
#define CR9_SRCS
Definition: dmfe.c:115
#define DMFE_10MHF
Definition: dmfe.c:90
#define PCI_DM9102_ID
Definition: dmfe.c:63
#define ETH_ALEN
Definition: if_ether.h:8
#define CR9_SROM_READ
Definition: dmfe.c:114
#define ETH_ZLEN
Definition: if_ether.h:10
A PCI device ID list entry.
Definition: pci.h:151
#define MDCLKH
Definition: dmfe.c:122
u8 media_mode
Definition: dmfe.c:165
Definition: nic.h:37
Definition: nic.h:49
unsigned int uint32_t
Definition: stdint.h:12
Definition: dmfe.c:181
#define PCI_DM9009_ID
Definition: dmfe.c:65
Definition: dmfe.c:182
const char * name
Name.
Definition: pci.h:153
uint16_t vendor
Vendor ID.
Definition: pci.h:202
Definition: dmfe.c:190
Definition: dmfe.c:137
u32 tdes1
Definition: dmfe.c:138
static void dmfe_reset(struct nic *nic)
Definition: dmfe.c:245
static int dmfe_poll(struct nic *nic, int retrieve)
Definition: dmfe.c:344
dmfe_offsets
Definition: dmfe.c:179
#define CR0_DEFAULT
Definition: dmfe.c:78
u8 chip_type
Definition: dmfe.c:164
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
static struct dmfe_private * db
Definition: dmfe.c:177
Definition: nic.h:36
unsigned char * packet
Definition: nic.h:53
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
u32 rdes1
Definition: dmfe.c:144
unsigned char * node_addr
Definition: nic.h:52
static void dmfe_init_dm910x(struct nic *nic)
Definition: dmfe.c:277
static u16 phy_read_1bit(unsigned long)
Definition: dmfe.c:1007
static u8 SF_mode
Definition: dmfe.c:205
Definition: dmfe.c:182
uint32_t len
Length.
Definition: ena.h:14
Definition: dmfe.c:189
u32 cr0_data
Definition: dmfe.c:152
static void dmfe_disable(struct nic *nic __unused)
Definition: dmfe.c:438
static u8 HPNA_NoiseFloor
Definition: dmfe.c:204
Definition: dmfe.c:143
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:561
Definition: dmfe.c:188
static struct nic_operations dmfe_operations
Definition: dmfe.c:194
u32 rdes0
Definition: dmfe.c:144
u16 HPNA_timer
Definition: dmfe.c:159
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
struct pci_device_id * id
Driver device ID.
Definition: pci.h:220
Definition: dmfe.c:182
#define cpu_to_le16(value)
Definition: byteswap.h:106
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
#define PCI_REVISION
PCI revision.
Definition: pci.h:43
static void dmfe_program_DM9802(struct nic *nic)
u32 cr7_data
Definition: dmfe.c:155
#define DMFE_100MHF
Definition: dmfe.c:91
#define CR15_DEFAULT
Definition: dmfe.c:81
static void dmfe_irq(struct nic *nic __unused, irq_action_t action __unused)
Definition: dmfe.c:384
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
Definition: dmfe.c:180
#define SROM_DATA_0
Definition: dmfe.c:118
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
Definition: dmfe.c:181
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:935
u16 HPNA_command
Definition: dmfe.c:158
int(* connect)(struct nic *)
Definition: nic.h:63
#define txb
Definition: dmfe.c:221
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define htons(value)
Definition: byteswap.h:135
static void dmfe_descriptor_init(struct nic *, unsigned long ioaddr)
uint8_t u8
Definition: stdint.h:19
static long int BASE
Definition: dmfe.c:226
uint32_t u32
Definition: stdint.h:23
u8 phy_addr
Definition: dmfe.c:167
#define PCI_DM9132_ID
Definition: dmfe.c:62
static void dmfe_program_DM9801(struct nic *nic, int)
static void dmfe_set_phyxcer(struct nic *nic)
u16 PHY_reg4
Definition: dmfe.c:161
dmfe_CR6_bits
Definition: dmfe.c:187
static u16 read_srom_word(long ioaddr, int offset)
Definition: dmfe.c:663