iPXE
Data Structures | Macros | Enumerations | Functions | Variables
dmfe.c File Reference
#include "etherboot.h"
#include "nic.h"
#include <ipxe/pci.h>
#include <ipxe/ethernet.h>

Go to the source code of this file.

Data Structures

struct  tx_desc
 
struct  rx_desc
 
struct  dmfe_private
 
struct  dmfe_bss
 

Macros

#define dprintf(x)
 
#define virt_to_le32desc(addr)   cpu_to_le32(virt_to_bus(addr))
 
#define le32desc_to_virt(addr)   bus_to_virt(le32_to_cpu(addr))
 
#define PCI_DM9132_ID   0x91321282 /* Davicom DM9132 ID */
 
#define PCI_DM9102_ID   0x91021282 /* Davicom DM9102 ID */
 
#define PCI_DM9100_ID   0x91001282 /* Davicom DM9100 ID */
 
#define PCI_DM9009_ID   0x90091282 /* Davicom DM9009 ID */
 
#define DM9102_IO_SIZE   0x80
 
#define DM9102A_IO_SIZE   0x100
 
#define TX_MAX_SEND_CNT   0x1 /* Maximum tx packet per time */
 
#define TX_DESC_CNT   0x10 /* Allocated Tx descriptors */
 
#define RX_DESC_CNT   0x20 /* Allocated Rx descriptors */
 
#define TX_FREE_DESC_CNT   (TX_DESC_CNT - 2) /* Max TX packet count */
 
#define TX_WAKE_DESC_CNT   (TX_DESC_CNT - 3) /* TX wakeup count */
 
#define DESC_ALL_CNT   (TX_DESC_CNT + RX_DESC_CNT)
 
#define TX_BUF_ALLOC   0x600
 
#define RX_ALLOC_SIZE   0x620
 
#define DM910X_RESET   1
 
#define CR0_DEFAULT   0x00E00000 /* TX & RX burst mode */
 
#define CR6_DEFAULT   0x00080000 /* HD */
 
#define CR7_DEFAULT   0x180c1
 
#define CR15_DEFAULT   0x06 /* TxJabber RxWatchdog */
 
#define TDES0_ERR_MASK   0x4302 /* TXJT, LC, EC, FUE */
 
#define MAX_PACKET_SIZE   1514
 
#define DMFE_MAX_MULTICAST   14
 
#define RX_COPY_SIZE   100
 
#define MAX_CHECK_PACKET   0x8000
 
#define DM9801_NOISE_FLOOR   8
 
#define DM9802_NOISE_FLOOR   5
 
#define DMFE_10MHF   0
 
#define DMFE_100MHF   1
 
#define DMFE_10MFD   4
 
#define DMFE_100MFD   5
 
#define DMFE_AUTO   8
 
#define DMFE_1M_HPNA   0x10
 
#define DMFE_TXTH_72   0x400000 /* TX TH 72 byte */
 
#define DMFE_TXTH_96   0x404000 /* TX TH 96 byte */
 
#define DMFE_TXTH_128   0x0000 /* TX TH 128 byte */
 
#define DMFE_TXTH_256   0x4000 /* TX TH 256 byte */
 
#define DMFE_TXTH_512   0x8000 /* TX TH 512 byte */
 
#define DMFE_TXTH_1K   0xC000 /* TX TH 1K byte */
 
#define DMFE_TIMER_WUT   (jiffies + HZ * 1) /* timer wakeup time : 1 second */
 
#define DMFE_TX_TIMEOUT   ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
 
#define DMFE_TX_KICK   (HZ/2) /* tx packet Kick-out time 0.5 s" */
 
#define DMFE_DBUG(dbug_now, msg, value)   if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
 
#define SHOW_MEDIA_TYPE(mode)   printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
 
#define CR9_SROM_READ   0x4800
 
#define CR9_SRCS   0x1
 
#define CR9_SRCLK   0x2
 
#define CR9_CRDOUT   0x8
 
#define SROM_DATA_0   0x0
 
#define SROM_DATA_1   0x4
 
#define PHY_DATA_1   0x20000
 
#define PHY_DATA_0   0x00000
 
#define MDCLKH   0x10000
 
#define PHY_POWER_DOWN   0x800
 
#define SROM_V41_CODE   0x14
 
#define SROM_CLK_WRITE(data, ioaddr)   outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
 
#define __CHK_IO_SIZE(pci_id, dev_rev)   ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
 
#define CHK_IO_SIZE(pci_dev, dev_rev)   __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
 
#define DEVICE   net_device
 
#define dmfe_bufs   NIC_FAKE_BSS ( struct dmfe_bss )
 
#define txd   dmfe_bufs.txd
 
#define txb   dmfe_bufs.txb
 
#define rxd   dmfe_bufs.rxd
 
#define rxb   dmfe_bufs.rxb
 
#define board_found   1
 
#define valid_link   0
 

Enumerations

enum  dmfe_offsets {
  DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18,
  DCR4 = 0x20, DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38,
  DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58,
  DCR12 = 0x60, DCR13 = 0x68, DCR14, DCR15 = 0x78
}
 
enum  dmfe_CR6_bits {
  CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
  CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000,
  CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
}
 

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
static u16 read_srom_word (long ioaddr, int offset)
 
static void dmfe_init_dm910x (struct nic *nic)
 
static void dmfe_descriptor_init (struct nic *, unsigned long ioaddr)
 
static void update_cr6 (u32, unsigned long)
 
static void send_filter_frame (struct nic *nic)
 
static void dm9132_id_table (struct nic *nic)
 
static u16 phy_read (unsigned long, u8, u8, u32)
 
static void phy_write (unsigned long, u8, u8, u16, u32)
 
static void phy_write_1bit (unsigned long, u32)
 
static u16 phy_read_1bit (unsigned long)
 
static void dmfe_set_phyxcer (struct nic *nic)
 
static void dmfe_parse_srom (struct nic *nic)
 
static void dmfe_program_DM9801 (struct nic *nic, int)
 
static void dmfe_program_DM9802 (struct nic *nic)
 
static void dmfe_reset (struct nic *nic)
 
static int dmfe_poll (struct nic *nic, int retrieve)
 
static void dmfe_irq (struct nic *nic __unused, irq_action_t action __unused)
 
static void dmfe_transmit (struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *packet)
 
static void dmfe_disable (struct nic *nic __unused, void *hwdev __unused)
 
static int dmfe_probe (struct nic *nic, struct pci_device *pci)
 
static void dmfe_descriptor_init (struct nic *nic __unused, unsigned long ioaddr)
 
static void dm9132_id_table (struct nic *nic __unused)
 
static void dmfe_set_phyxcer (struct nic *nic __unused)
 
static void dmfe_program_DM9801 (struct nic *nic __unused, int HPNA_rev)
 
static void dmfe_program_DM9802 (struct nic *nic __unused)
 
 PCI_DRIVER (dmfe_driver, dmfe_nics, PCI_NO_CLASS)
 
 DRIVER ("DMFE/PCI", nic_driver, pci_driver, dmfe_driver, dmfe_probe, dmfe_disable, dmfe_bufs)
 

Variables

static struct dmfe_private dfx
 
static struct dmfe_private * db
 
static struct nic_operations dmfe_operations
 
static unsigned char dmfe_media_mode = DMFE_AUTO
 
static u32 dmfe_cr6_user_set
 
static u8 chkmode = 1
 
static u8 HPNA_mode
 
static u8 HPNA_rx_cmd
 
static u8 HPNA_tx_cmd
 
static u8 HPNA_NoiseFloor
 
static u8 SF_mode
 
static long int BASE
 
static struct pci_device_id dmfe_nics []
 

Macro Definition Documentation

◆ dprintf

#define dprintf (   x)

Definition at line 54 of file dmfe.c.

◆ virt_to_le32desc

#define virt_to_le32desc (   addr)    cpu_to_le32(virt_to_bus(addr))

Definition at line 58 of file dmfe.c.

◆ le32desc_to_virt

#define le32desc_to_virt (   addr)    bus_to_virt(le32_to_cpu(addr))

Definition at line 59 of file dmfe.c.

◆ PCI_DM9132_ID

#define PCI_DM9132_ID   0x91321282 /* Davicom DM9132 ID */

Definition at line 62 of file dmfe.c.

◆ PCI_DM9102_ID

#define PCI_DM9102_ID   0x91021282 /* Davicom DM9102 ID */

Definition at line 63 of file dmfe.c.

◆ PCI_DM9100_ID

#define PCI_DM9100_ID   0x91001282 /* Davicom DM9100 ID */

Definition at line 64 of file dmfe.c.

◆ PCI_DM9009_ID

#define PCI_DM9009_ID   0x90091282 /* Davicom DM9009 ID */

Definition at line 65 of file dmfe.c.

◆ DM9102_IO_SIZE

#define DM9102_IO_SIZE   0x80

Definition at line 67 of file dmfe.c.

◆ DM9102A_IO_SIZE

#define DM9102A_IO_SIZE   0x100

Definition at line 68 of file dmfe.c.

◆ TX_MAX_SEND_CNT

#define TX_MAX_SEND_CNT   0x1 /* Maximum tx packet per time */

Definition at line 69 of file dmfe.c.

◆ TX_DESC_CNT

#define TX_DESC_CNT   0x10 /* Allocated Tx descriptors */

Definition at line 70 of file dmfe.c.

◆ RX_DESC_CNT

#define RX_DESC_CNT   0x20 /* Allocated Rx descriptors */

Definition at line 71 of file dmfe.c.

◆ TX_FREE_DESC_CNT

#define TX_FREE_DESC_CNT   (TX_DESC_CNT - 2) /* Max TX packet count */

Definition at line 72 of file dmfe.c.

◆ TX_WAKE_DESC_CNT

#define TX_WAKE_DESC_CNT   (TX_DESC_CNT - 3) /* TX wakeup count */

Definition at line 73 of file dmfe.c.

◆ DESC_ALL_CNT

#define DESC_ALL_CNT   (TX_DESC_CNT + RX_DESC_CNT)

Definition at line 74 of file dmfe.c.

◆ TX_BUF_ALLOC

#define TX_BUF_ALLOC   0x600

Definition at line 75 of file dmfe.c.

◆ RX_ALLOC_SIZE

#define RX_ALLOC_SIZE   0x620

Definition at line 76 of file dmfe.c.

◆ DM910X_RESET

#define DM910X_RESET   1

Definition at line 77 of file dmfe.c.

◆ CR0_DEFAULT

#define CR0_DEFAULT   0x00E00000 /* TX & RX burst mode */

Definition at line 78 of file dmfe.c.

◆ CR6_DEFAULT

#define CR6_DEFAULT   0x00080000 /* HD */

Definition at line 79 of file dmfe.c.

◆ CR7_DEFAULT

#define CR7_DEFAULT   0x180c1

Definition at line 80 of file dmfe.c.

◆ CR15_DEFAULT

#define CR15_DEFAULT   0x06 /* TxJabber RxWatchdog */

Definition at line 81 of file dmfe.c.

◆ TDES0_ERR_MASK

#define TDES0_ERR_MASK   0x4302 /* TXJT, LC, EC, FUE */

Definition at line 82 of file dmfe.c.

◆ MAX_PACKET_SIZE

#define MAX_PACKET_SIZE   1514

Definition at line 83 of file dmfe.c.

◆ DMFE_MAX_MULTICAST

#define DMFE_MAX_MULTICAST   14

Definition at line 84 of file dmfe.c.

◆ RX_COPY_SIZE

#define RX_COPY_SIZE   100

Definition at line 85 of file dmfe.c.

◆ MAX_CHECK_PACKET

#define MAX_CHECK_PACKET   0x8000

Definition at line 86 of file dmfe.c.

◆ DM9801_NOISE_FLOOR

#define DM9801_NOISE_FLOOR   8

Definition at line 87 of file dmfe.c.

◆ DM9802_NOISE_FLOOR

#define DM9802_NOISE_FLOOR   5

Definition at line 88 of file dmfe.c.

◆ DMFE_10MHF

#define DMFE_10MHF   0

Definition at line 90 of file dmfe.c.

◆ DMFE_100MHF

#define DMFE_100MHF   1

Definition at line 91 of file dmfe.c.

◆ DMFE_10MFD

#define DMFE_10MFD   4

Definition at line 92 of file dmfe.c.

◆ DMFE_100MFD

#define DMFE_100MFD   5

Definition at line 93 of file dmfe.c.

◆ DMFE_AUTO

#define DMFE_AUTO   8

Definition at line 94 of file dmfe.c.

◆ DMFE_1M_HPNA

#define DMFE_1M_HPNA   0x10

Definition at line 95 of file dmfe.c.

◆ DMFE_TXTH_72

#define DMFE_TXTH_72   0x400000 /* TX TH 72 byte */

Definition at line 97 of file dmfe.c.

◆ DMFE_TXTH_96

#define DMFE_TXTH_96   0x404000 /* TX TH 96 byte */

Definition at line 98 of file dmfe.c.

◆ DMFE_TXTH_128

#define DMFE_TXTH_128   0x0000 /* TX TH 128 byte */

Definition at line 99 of file dmfe.c.

◆ DMFE_TXTH_256

#define DMFE_TXTH_256   0x4000 /* TX TH 256 byte */

Definition at line 100 of file dmfe.c.

◆ DMFE_TXTH_512

#define DMFE_TXTH_512   0x8000 /* TX TH 512 byte */

Definition at line 101 of file dmfe.c.

◆ DMFE_TXTH_1K

#define DMFE_TXTH_1K   0xC000 /* TX TH 1K byte */

Definition at line 102 of file dmfe.c.

◆ DMFE_TIMER_WUT

#define DMFE_TIMER_WUT   (jiffies + HZ * 1) /* timer wakeup time : 1 second */

Definition at line 104 of file dmfe.c.

◆ DMFE_TX_TIMEOUT

#define DMFE_TX_TIMEOUT   ((3*HZ)/2) /* tx packet time-out time 1.5 s" */

Definition at line 105 of file dmfe.c.

◆ DMFE_TX_KICK

#define DMFE_TX_KICK   (HZ/2) /* tx packet Kick-out time 0.5 s" */

Definition at line 106 of file dmfe.c.

◆ DMFE_DBUG

#define DMFE_DBUG (   dbug_now,
  msg,
  value 
)    if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))

Definition at line 108 of file dmfe.c.

◆ SHOW_MEDIA_TYPE

#define SHOW_MEDIA_TYPE (   mode)    printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");

Definition at line 110 of file dmfe.c.

◆ CR9_SROM_READ

#define CR9_SROM_READ   0x4800

Definition at line 114 of file dmfe.c.

◆ CR9_SRCS

#define CR9_SRCS   0x1

Definition at line 115 of file dmfe.c.

◆ CR9_SRCLK

#define CR9_SRCLK   0x2

Definition at line 116 of file dmfe.c.

◆ CR9_CRDOUT

#define CR9_CRDOUT   0x8

Definition at line 117 of file dmfe.c.

◆ SROM_DATA_0

#define SROM_DATA_0   0x0

Definition at line 118 of file dmfe.c.

◆ SROM_DATA_1

#define SROM_DATA_1   0x4

Definition at line 119 of file dmfe.c.

◆ PHY_DATA_1

#define PHY_DATA_1   0x20000

Definition at line 120 of file dmfe.c.

◆ PHY_DATA_0

#define PHY_DATA_0   0x00000

Definition at line 121 of file dmfe.c.

◆ MDCLKH

#define MDCLKH   0x10000

Definition at line 122 of file dmfe.c.

◆ PHY_POWER_DOWN

#define PHY_POWER_DOWN   0x800

Definition at line 124 of file dmfe.c.

◆ SROM_V41_CODE

#define SROM_V41_CODE   0x14

Definition at line 126 of file dmfe.c.

◆ SROM_CLK_WRITE

#define SROM_CLK_WRITE (   data,
  ioaddr 
)    outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);

Definition at line 128 of file dmfe.c.

◆ __CHK_IO_SIZE

#define __CHK_IO_SIZE (   pci_id,
  dev_rev 
)    ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE

Definition at line 130 of file dmfe.c.

◆ CHK_IO_SIZE

#define CHK_IO_SIZE (   pci_dev,
  dev_rev 
)    __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)

Definition at line 131 of file dmfe.c.

◆ DEVICE

#define DEVICE   net_device

Definition at line 134 of file dmfe.c.

◆ dmfe_bufs

#define dmfe_bufs   NIC_FAKE_BSS ( struct dmfe_bss )

Definition at line 220 of file dmfe.c.

◆ txd

#define txd   dmfe_bufs.txd

Definition at line 221 of file dmfe.c.

◆ txb

#define txb   dmfe_bufs.txb

Definition at line 222 of file dmfe.c.

◆ rxd

#define rxd   dmfe_bufs.rxd

Definition at line 223 of file dmfe.c.

◆ rxb

#define rxb   dmfe_bufs.rxb

Definition at line 224 of file dmfe.c.

◆ board_found

#define board_found   1

Definition at line 451 of file dmfe.c.

◆ valid_link

#define valid_link   0

Definition at line 452 of file dmfe.c.

Enumeration Type Documentation

◆ dmfe_offsets

enum dmfe_offsets
Enumerator
DCR0 
DCR1 
DCR2 
DCR3 
DCR4 
DCR5 
DCR6 
DCR7 
DCR8 
DCR9 
DCR10 
DCR11 
DCR12 
DCR13 
DCR14 
DCR15 

Definition at line 179 of file dmfe.c.

179  {
180  DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
181  DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
182  DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 =
183  0x70,
184  DCR15 = 0x78
185 };
DCR2
Definition: dmfe.c:180
DCR11
Definition: dmfe.c:182
DCR9
Definition: dmfe.c:181
DCR4
Definition: dmfe.c:180
DCR7
Definition: dmfe.c:181
DCR1
Definition: dmfe.c:180
DCR13
Definition: dmfe.c:182
DCR15
Definition: dmfe.c:184
DCR3
Definition: dmfe.c:180
DCR8
Definition: dmfe.c:181
DCR6
Definition: dmfe.c:181
DCR10
Definition: dmfe.c:182
DCR12
Definition: dmfe.c:182
DCR14
Definition: dmfe.c:182
DCR0
Definition: dmfe.c:180
DCR5
Definition: dmfe.c:181

◆ dmfe_CR6_bits

enum dmfe_CR6_bits
Enumerator
CR6_RXSC 
CR6_PBF 
CR6_PM 
CR6_PAM 
CR6_FDM 
CR6_TXSC 
CR6_STI 
CR6_SFT 
CR6_RXA 
CR6_NO_PURGE 

Definition at line 187 of file dmfe.c.

187  {
188  CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
189  CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
190  CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
191 };
CR6_RXSC
Definition: dmfe.c:188
CR6_TXSC
Definition: dmfe.c:189
CR6_STI
Definition: dmfe.c:189
CR6_PBF
Definition: dmfe.c:188
CR6_RXA
Definition: dmfe.c:190
CR6_PAM
Definition: dmfe.c:188
CR6_SFT
Definition: dmfe.c:190
CR6_FDM
Definition: dmfe.c:189
CR6_PM
Definition: dmfe.c:188

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ read_srom_word()

static u16 read_srom_word ( long  ioaddr,
int  offset 
)
static

Definition at line 664 of file dmfe.c.

665 {
666  int i;
667  u16 srom_data = 0;
668  long cr9_ioaddr = ioaddr + DCR9;
669 
670  outl(CR9_SROM_READ, cr9_ioaddr);
671  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
672 
673  /* Send the Read Command 110b */
674  SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
675  SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
676  SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
677 
678  /* Send the offset */
679  for (i = 5; i >= 0; i--) {
680  srom_data =
681  (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
682  SROM_CLK_WRITE(srom_data, cr9_ioaddr);
683  }
684 
685  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
686 
687  for (i = 16; i > 0; i--) {
688  outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
689  udelay(5);
690  srom_data =
691  (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1
692  : 0);
693  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
694  udelay(5);
695  }
696 
697  outl(CR9_SROM_READ, cr9_ioaddr);
698  return srom_data;
699 }
u16
uint16_t u16
Definition: stdint.h:21
CR9_SRCLK
#define CR9_SRCLK
Definition: dmfe.c:116
DCR9
Definition: dmfe.c:181
SROM_CLK_WRITE
#define SROM_CLK_WRITE(data, ioaddr)
Definition: dmfe.c:128
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
SROM_DATA_1
#define SROM_DATA_1
Definition: dmfe.c:119
outl
#define outl(data, io_addr)
Definition: io.h:329
CR9_CRDOUT
#define CR9_CRDOUT
Definition: dmfe.c:117
CR9_SRCS
#define CR9_SRCS
Definition: dmfe.c:115
CR9_SROM_READ
#define CR9_SROM_READ
Definition: dmfe.c:114
inl
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
offset
uint16_t offset
Offset to command line.
Definition: bzimage.h:8
SROM_DATA_0
#define SROM_DATA_0
Definition: dmfe.c:118

References CR9_CRDOUT, CR9_SRCLK, CR9_SRCS, CR9_SROM_READ, DCR9, inl(), ioaddr, offset, outl, SROM_CLK_WRITE, SROM_DATA_0, SROM_DATA_1, and udelay().

Referenced by dmfe_probe().

◆ dmfe_init_dm910x()

static void dmfe_init_dm910x ( struct nic *  nic)
static

Definition at line 278 of file dmfe.c.

279 {
280  unsigned long ioaddr = BASE;
281 
282  /* Reset DM910x MAC controller */
283  outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
284  udelay(100);
285  outl(db->cr0_data, ioaddr + DCR0);
286  udelay(5);
287 
288  /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
289  db->phy_addr = 1;
290 
291  /* Parser SROM and media mode */
292  dmfe_parse_srom(nic);
293  db->media_mode = dmfe_media_mode;
294 
295  /* RESET Phyxcer Chip by GPR port bit 7 */
296  outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
297  if (db->chip_id == PCI_DM9009_ID) {
298  outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
299  mdelay(300); /* Delay 300 ms */
300  }
301  outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
302 
303  /* Process Phyxcer Media Mode */
304  if (!(db->media_mode & 0x10)) /* Force 1M mode */
305  dmfe_set_phyxcer(nic);
306 
307  /* Media Mode Process */
308  if (!(db->media_mode & DMFE_AUTO))
309  db->op_mode = db->media_mode; /* Force Mode */
310 
311  /* Initiliaze Transmit/Receive descriptor and CR3/4 */
312  dmfe_descriptor_init(nic, ioaddr);
313 
314  /* tx descriptor start pointer */
315  outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
316 
317  /* rx descriptor start pointer */
318  outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
319 
320  /* Init CR6 to program DM910x operation */
321  update_cr6(db->cr6_data, ioaddr);
322 
323  /* Send setup frame */
324  if (db->chip_id == PCI_DM9132_ID) {
325  dm9132_id_table(nic); /* DM9132 */
326  } else {
327  send_filter_frame(nic); /* DM9102/DM9102A */
328  }
329 
330  /* Init CR7, interrupt active bit */
331  db->cr7_data = CR7_DEFAULT;
332  outl(db->cr7_data, ioaddr + DCR7);
333  /* Init CR15, Tx jabber and Rx watchdog timer */
334  outl(db->cr15_data, ioaddr + DCR15);
335  /* Enable DM910X Tx/Rx function */
336  db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
337  update_cr6(db->cr6_data, ioaddr);
338 }
dmfe_private::op_mode
u8 op_mode
Definition: dmfe.c:166
dmfe_media_mode
static unsigned char dmfe_media_mode
Definition: dmfe.c:196
virt_to_le32desc
#define virt_to_le32desc(addr)
Definition: dmfe.c:58
dmfe_private::cr6_data
u32 cr6_data
Definition: dmfe.c:154
CR6_RXSC
Definition: dmfe.c:188
CR6_TXSC
Definition: dmfe.c:189
DCR4
Definition: dmfe.c:180
dmfe_parse_srom
static void dmfe_parse_srom(struct nic *nic)
Definition: dmfe.c:1026
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
rxd
#define rxd
Definition: dmfe.c:223
DCR7
Definition: dmfe.c:181
dm9132_id_table
static void dm9132_id_table(struct nic *nic)
dmfe_private::cr15_data
u32 cr15_data
Definition: dmfe.c:156
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
DCR15
Definition: dmfe.c:184
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
txd
#define txd
Definition: dmfe.c:221
send_filter_frame
static void send_filter_frame(struct nic *nic)
Definition: dmfe.c:630
DCR3
Definition: dmfe.c:180
DM910X_RESET
#define DM910X_RESET
Definition: dmfe.c:77
outl
#define outl(data, io_addr)
Definition: io.h:329
CR7_DEFAULT
#define CR7_DEFAULT
Definition: dmfe.c:80
DMFE_AUTO
#define DMFE_AUTO
Definition: dmfe.c:94
dmfe_private::media_mode
u8 media_mode
Definition: dmfe.c:165
nic
Definition: nic.h:49
PCI_DM9009_ID
#define PCI_DM9009_ID
Definition: dmfe.c:65
db
static struct dmfe_private * db
Definition: dmfe.c:177
mdelay
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
DCR12
Definition: dmfe.c:182
dmfe_private::cr0_data
u32 cr0_data
Definition: dmfe.c:152
update_cr6
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:562
dmfe_private::cr7_data
u32 cr7_data
Definition: dmfe.c:155
DCR0
Definition: dmfe.c:180
dmfe_descriptor_init
static void dmfe_descriptor_init(struct nic *, unsigned long ioaddr)
BASE
static long int BASE
Definition: dmfe.c:227
dmfe_private::phy_addr
u8 phy_addr
Definition: dmfe.c:167
PCI_DM9132_ID
#define PCI_DM9132_ID
Definition: dmfe.c:62
dmfe_set_phyxcer
static void dmfe_set_phyxcer(struct nic *nic)

References BASE, dmfe_private::chip_id, dmfe_private::cr0_data, dmfe_private::cr15_data, dmfe_private::cr6_data, CR6_RXSC, CR6_TXSC, dmfe_private::cr7_data, CR7_DEFAULT, db, DCR0, DCR12, DCR15, DCR3, DCR4, DCR7, DM910X_RESET, dm9132_id_table(), DMFE_AUTO, dmfe_descriptor_init(), dmfe_media_mode, dmfe_parse_srom(), dmfe_set_phyxcer(), ioaddr, mdelay(), dmfe_private::media_mode, dmfe_private::op_mode, outl, PCI_DM9009_ID, PCI_DM9132_ID, dmfe_private::phy_addr, rxd, send_filter_frame(), txd, udelay(), update_cr6(), and virt_to_le32desc.

Referenced by dmfe_reset().

◆ dmfe_descriptor_init() [1/2]

static void dmfe_descriptor_init ( struct nic *  ,
unsigned long  ioaddr 
)
static

Referenced by dmfe_init_dm910x().

◆ update_cr6()

static void update_cr6 ( u32  cr6_data,
unsigned long  ioaddr 
)
static

Definition at line 562 of file dmfe.c.

563 {
564  u32 cr6_tmp;
565 
566  cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
567  outl(cr6_tmp, ioaddr + DCR6);
568  udelay(5);
569  outl(cr6_data, ioaddr + DCR6);
570  udelay(5);
571 }
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
outl
#define outl(data, io_addr)
Definition: io.h:329
DCR6
Definition: dmfe.c:181
u32
uint32_t u32
Definition: stdint.h:23

References DCR6, ioaddr, outl, and udelay().

Referenced by dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_set_phyxcer(), and send_filter_frame().

◆ send_filter_frame()

static void send_filter_frame ( struct nic *  nic)
static

Definition at line 630 of file dmfe.c.

631 {
632 
633  u8 *ptxb;
634  int i;
635 
636  dprintf(("send_filter_frame\n"));
637  /* point to the current txb incase multiple tx_rings are used */
638  ptxb = &txb[db->cur_tx];
639 
640  /* construct perfect filter frame with mac address as first match
641  and broadcast address for all others */
642  for (i = 0; i < 192; i++)
643  ptxb[i] = 0xFF;
644  ptxb[0] = nic->node_addr[0];
645  ptxb[1] = nic->node_addr[1];
646  ptxb[4] = nic->node_addr[2];
647  ptxb[5] = nic->node_addr[3];
648  ptxb[8] = nic->node_addr[4];
649  ptxb[9] = nic->node_addr[5];
650 
651  /* prepare the setup frame */
652  txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0);
653  txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);
654  update_cr6(db->cr6_data | 0x2000, BASE);
655  outl(0x1, BASE + DCR1); /* Issue Tx polling */
656  update_cr6(db->cr6_data, BASE);
657  db->cur_tx++;
658 }
dmfe_private::cr6_data
u32 cr6_data
Definition: dmfe.c:154
dmfe_private::cur_tx
u8 cur_tx
Definition: dmfe.c:173
DCR1
Definition: dmfe.c:180
txd
#define txd
Definition: dmfe.c:221
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:107
outl
#define outl(data, io_addr)
Definition: io.h:329
dprintf
#define dprintf(x)
Definition: dmfe.c:54
nic
Definition: nic.h:49
db
static struct dmfe_private * db
Definition: dmfe.c:177
nic::node_addr
unsigned char * node_addr
Definition: nic.h:52
update_cr6
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:562
txb
#define txb
Definition: dmfe.c:222
u8
uint8_t u8
Definition: stdint.h:19
BASE
static long int BASE
Definition: dmfe.c:227

References BASE, cpu_to_le32, dmfe_private::cr6_data, dmfe_private::cur_tx, db, DCR1, dprintf, nic::node_addr, outl, txb, txd, and update_cr6().

Referenced by dmfe_init_dm910x().

◆ dm9132_id_table() [1/2]

static void dm9132_id_table ( struct nic *  nic)
static

Referenced by dmfe_init_dm910x().

◆ phy_read()

static u16 phy_read ( unsigned long  iobase,
u8  phy_addr,
u8  offset,
u32  chip_id 
)
static

Definition at line 936 of file dmfe.c.

938 {
939  int i;
940  u16 phy_data;
941  unsigned long ioaddr;
942 
943  if (chip_id == PCI_DM9132_ID) {
944  /* DM9132 Chip */
945  ioaddr = iobase + 0x80 + offset * 4;
946  phy_data = inw(ioaddr);
947  } else {
948  /* DM9102/DM9102A Chip */
949  ioaddr = iobase + DCR9;
950 
951  /* Send 33 synchronization clock to Phy controller */
952  for (i = 0; i < 35; i++)
953  phy_write_1bit(ioaddr, PHY_DATA_1);
954 
955  /* Send start command(01) to Phy */
956  phy_write_1bit(ioaddr, PHY_DATA_0);
957  phy_write_1bit(ioaddr, PHY_DATA_1);
958 
959  /* Send read command(10) to Phy */
960  phy_write_1bit(ioaddr, PHY_DATA_1);
961  phy_write_1bit(ioaddr, PHY_DATA_0);
962 
963  /* Send Phy address */
964  for (i = 0x10; i > 0; i = i >> 1)
965  phy_write_1bit(ioaddr,
966  phy_addr & i ? PHY_DATA_1 :
967  PHY_DATA_0);
968 
969  /* Send register address */
970  for (i = 0x10; i > 0; i = i >> 1)
971  phy_write_1bit(ioaddr,
972  offset & i ? PHY_DATA_1 :
973  PHY_DATA_0);
974 
975  /* Skip transition state */
976  phy_read_1bit(ioaddr);
977 
978  /* read 16bit data */
979  for (phy_data = 0, i = 0; i < 16; i++) {
980  phy_data <<= 1;
981  phy_data |= phy_read_1bit(ioaddr);
982  }
983  }
984 
985  return phy_data;
986 }
phy_write_1bit
static void phy_write_1bit(unsigned long, u32)
Definition: dmfe.c:993
u16
uint16_t u16
Definition: stdint.h:21
inw
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
DCR9
Definition: dmfe.c:181
PHY_DATA_0
#define PHY_DATA_0
Definition: dmfe.c:121
PHY_DATA_1
#define PHY_DATA_1
Definition: dmfe.c:120
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
phy_read_1bit
static u16 phy_read_1bit(unsigned long)
Definition: dmfe.c:1008
offset
uint16_t offset
Offset to command line.
Definition: bzimage.h:8
PCI_DM9132_ID
#define PCI_DM9132_ID
Definition: dmfe.c:62

References DCR9, inw(), ioaddr, offset, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, phy_read_1bit(), and phy_write_1bit().

Referenced by dmfe_parse_srom(), dmfe_program_DM9801(), dmfe_program_DM9802(), and dmfe_set_phyxcer().

◆ phy_write()

static void phy_write ( unsigned long  iobase,
u8  phy_addr,
u8  offset,
u16  phy_data,
u32  chip_id 
)
static

Definition at line 882 of file dmfe.c.

884 {
885  u16 i;
886  unsigned long ioaddr;
887 
888  if (chip_id == PCI_DM9132_ID) {
889  ioaddr = iobase + 0x80 + offset * 4;
890  outw(phy_data, ioaddr);
891  } else {
892  /* DM9102/DM9102A Chip */
893  ioaddr = iobase + DCR9;
894 
895  /* Send 33 synchronization clock to Phy controller */
896  for (i = 0; i < 35; i++)
897  phy_write_1bit(ioaddr, PHY_DATA_1);
898 
899  /* Send start command(01) to Phy */
900  phy_write_1bit(ioaddr, PHY_DATA_0);
901  phy_write_1bit(ioaddr, PHY_DATA_1);
902 
903  /* Send write command(01) to Phy */
904  phy_write_1bit(ioaddr, PHY_DATA_0);
905  phy_write_1bit(ioaddr, PHY_DATA_1);
906 
907  /* Send Phy address */
908  for (i = 0x10; i > 0; i = i >> 1)
909  phy_write_1bit(ioaddr,
910  phy_addr & i ? PHY_DATA_1 :
911  PHY_DATA_0);
912 
913  /* Send register address */
914  for (i = 0x10; i > 0; i = i >> 1)
915  phy_write_1bit(ioaddr,
916  offset & i ? PHY_DATA_1 :
917  PHY_DATA_0);
918 
919  /* written trasnition */
920  phy_write_1bit(ioaddr, PHY_DATA_1);
921  phy_write_1bit(ioaddr, PHY_DATA_0);
922 
923  /* Write a word data to PHY controller */
924  for (i = 0x8000; i > 0; i >>= 1)
925  phy_write_1bit(ioaddr,
926  phy_data & i ? PHY_DATA_1 :
927  PHY_DATA_0);
928  }
929 }
phy_write_1bit
static void phy_write_1bit(unsigned long, u32)
Definition: dmfe.c:993
u16
uint16_t u16
Definition: stdint.h:21
outw
#define outw(data, io_addr)
Definition: io.h:319
DCR9
Definition: dmfe.c:181
PHY_DATA_0
#define PHY_DATA_0
Definition: dmfe.c:121
PHY_DATA_1
#define PHY_DATA_1
Definition: dmfe.c:120
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
offset
uint16_t offset
Offset to command line.
Definition: bzimage.h:8
PCI_DM9132_ID
#define PCI_DM9132_ID
Definition: dmfe.c:62

References DCR9, ioaddr, offset, outw, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, and phy_write_1bit().

Referenced by dmfe_disable(), dmfe_program_DM9801(), dmfe_program_DM9802(), and dmfe_set_phyxcer().

◆ phy_write_1bit()

static void phy_write_1bit ( unsigned long  ioaddr,
u32  phy_data 
)
static

Definition at line 993 of file dmfe.c.

994 {
995  outl(phy_data, ioaddr); /* MII Clock Low */
996  udelay(1);
997  outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
998  udelay(1);
999  outl(phy_data, ioaddr); /* MII Clock Low */
1000  udelay(1);
1001 }
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
outl
#define outl(data, io_addr)
Definition: io.h:329
MDCLKH
#define MDCLKH
Definition: dmfe.c:122

References ioaddr, MDCLKH, outl, and udelay().

Referenced by phy_read(), and phy_write().

◆ phy_read_1bit()

static u16 phy_read_1bit ( unsigned long  ioaddr)
static

Definition at line 1008 of file dmfe.c.

1009 {
1010  u16 phy_data;
1011 
1012  outl(0x50000, ioaddr);
1013  udelay(1);
1014  phy_data = (inl(ioaddr) >> 19) & 0x1;
1015  outl(0x40000, ioaddr);
1016  udelay(1);
1017 
1018  return phy_data;
1019 }
u16
uint16_t u16
Definition: stdint.h:21
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
outl
#define outl(data, io_addr)
Definition: io.h:329
inl
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.

References inl(), ioaddr, outl, and udelay().

Referenced by phy_read().

◆ dmfe_set_phyxcer() [1/2]

static void dmfe_set_phyxcer ( struct nic *  nic)
static

Referenced by dmfe_init_dm910x().

◆ dmfe_parse_srom()

static void dmfe_parse_srom ( struct nic *  nic)
static

Definition at line 1026 of file dmfe.c.

1027 {
1028  unsigned char *srom = db->srom;
1029  int dmfe_mode, tmp_reg;
1030 
1031  /* Init CR15 */
1032  db->cr15_data = CR15_DEFAULT;
1033 
1034  /* Check SROM Version */
1035  if (((int) srom[18] & 0xff) == SROM_V41_CODE) {
1036  /* SROM V4.01 */
1037  /* Get NIC support media mode */
1038  db->NIC_capability = *(u16 *) (srom + 34);
1039  db->PHY_reg4 = 0;
1040  for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1041  switch (db->NIC_capability & tmp_reg) {
1042  case 0x1:
1043  db->PHY_reg4 |= 0x0020;
1044  break;
1045  case 0x2:
1046  db->PHY_reg4 |= 0x0040;
1047  break;
1048  case 0x4:
1049  db->PHY_reg4 |= 0x0080;
1050  break;
1051  case 0x8:
1052  db->PHY_reg4 |= 0x0100;
1053  break;
1054  }
1055  }
1056 
1057  /* Media Mode Force or not check */
1058  dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36);
1059  switch (dmfe_mode) {
1060  case 0x4:
1061  dmfe_media_mode = DMFE_100MHF;
1062  break; /* 100MHF */
1063  case 0x2:
1064  dmfe_media_mode = DMFE_10MFD;
1065  break; /* 10MFD */
1066  case 0x8:
1067  dmfe_media_mode = DMFE_100MFD;
1068  break; /* 100MFD */
1069  case 0x100:
1070  case 0x200:
1071  dmfe_media_mode = DMFE_1M_HPNA;
1072  break; /* HomePNA */
1073  }
1074 
1075  /* Special Function setting */
1076  /* VLAN function */
1077  if ((SF_mode & 0x1) || (srom[43] & 0x80))
1078  db->cr15_data |= 0x40;
1079 
1080  /* Flow Control */
1081  if ((SF_mode & 0x2) || (srom[40] & 0x1))
1082  db->cr15_data |= 0x400;
1083 
1084  /* TX pause packet */
1085  if ((SF_mode & 0x4) || (srom[40] & 0xe))
1086  db->cr15_data |= 0x9800;
1087  }
1088 
1089  /* Parse HPNA parameter */
1090  db->HPNA_command = 1;
1091 
1092  /* Accept remote command or not */
1093  if (HPNA_rx_cmd == 0)
1094  db->HPNA_command |= 0x8000;
1095 
1096  /* Issue remote command & operation mode */
1097  if (HPNA_tx_cmd == 1)
1098  switch (HPNA_mode) { /* Issue Remote Command */
1099  case 0:
1100  db->HPNA_command |= 0x0904;
1101  break;
1102  case 1:
1103  db->HPNA_command |= 0x0a00;
1104  break;
1105  case 2:
1106  db->HPNA_command |= 0x0506;
1107  break;
1108  case 3:
1109  db->HPNA_command |= 0x0602;
1110  break;
1111  } else
1112  switch (HPNA_mode) { /* Don't Issue */
1113  case 0:
1114  db->HPNA_command |= 0x0004;
1115  break;
1116  case 1:
1117  db->HPNA_command |= 0x0000;
1118  break;
1119  case 2:
1120  db->HPNA_command |= 0x0006;
1121  break;
1122  case 3:
1123  db->HPNA_command |= 0x0002;
1124  break;
1125  }
1126 
1127  /* Check DM9801 or DM9802 present or not */
1128  db->HPNA_present = 0;
1129  update_cr6(db->cr6_data | 0x40000, BASE);
1130  tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id);
1131  if ((tmp_reg & 0xfff0) == 0xb900) {
1132  /* DM9801 or DM9802 present */
1133  db->HPNA_timer = 8;
1134  if (phy_read(BASE, db->phy_addr, 31, db->chip_id) ==
1135  0x4404) {
1136  /* DM9801 HomeRun */
1137  db->HPNA_present = 1;
1138  dmfe_program_DM9801(nic, tmp_reg);
1139  } else {
1140  /* DM9802 LongRun */
1141  db->HPNA_present = 2;
1142  dmfe_program_DM9802(nic);
1143  }
1144  }
1145 
1146 }
u16
uint16_t u16
Definition: stdint.h:21
DMFE_1M_HPNA
#define DMFE_1M_HPNA
Definition: dmfe.c:95
dmfe_media_mode
static unsigned char dmfe_media_mode
Definition: dmfe.c:196
dmfe_private::cr6_data
u32 cr6_data
Definition: dmfe.c:154
DMFE_100MFD
#define DMFE_100MFD
Definition: dmfe.c:93
HPNA_rx_cmd
static u8 HPNA_rx_cmd
Definition: dmfe.c:202
dmfe_private::HPNA_present
u8 HPNA_present
Definition: dmfe.c:163
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
dmfe_private::srom
unsigned char srom[128]
Definition: dmfe.c:171
dmfe_private::NIC_capability
u16 NIC_capability
Definition: dmfe.c:160
HPNA_tx_cmd
static u8 HPNA_tx_cmd
Definition: dmfe.c:203
dmfe_private::cr15_data
u32 cr15_data
Definition: dmfe.c:156
HPNA_mode
static u8 HPNA_mode
Definition: dmfe.c:201
SROM_V41_CODE
#define SROM_V41_CODE
Definition: dmfe.c:126
DMFE_10MFD
#define DMFE_10MFD
Definition: dmfe.c:92
nic
Definition: nic.h:49
db
static struct dmfe_private * db
Definition: dmfe.c:177
SF_mode
static u8 SF_mode
Definition: dmfe.c:205
update_cr6
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:562
dmfe_private::HPNA_timer
u16 HPNA_timer
Definition: dmfe.c:159
dmfe_program_DM9802
static void dmfe_program_DM9802(struct nic *nic)
DMFE_100MHF
#define DMFE_100MHF
Definition: dmfe.c:91
CR15_DEFAULT
#define CR15_DEFAULT
Definition: dmfe.c:81
phy_read
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:936
dmfe_private::HPNA_command
u16 HPNA_command
Definition: dmfe.c:158
BASE
static long int BASE
Definition: dmfe.c:227
dmfe_private::phy_addr
u8 phy_addr
Definition: dmfe.c:167
dmfe_program_DM9801
static void dmfe_program_DM9801(struct nic *nic, int)
dmfe_private::PHY_reg4
u16 PHY_reg4
Definition: dmfe.c:161

References BASE, dmfe_private::chip_id, dmfe_private::cr15_data, CR15_DEFAULT, dmfe_private::cr6_data, db, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_1M_HPNA, dmfe_media_mode, dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_private::HPNA_command, HPNA_mode, dmfe_private::HPNA_present, HPNA_rx_cmd, dmfe_private::HPNA_timer, HPNA_tx_cmd, dmfe_private::NIC_capability, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, SF_mode, dmfe_private::srom, SROM_V41_CODE, and update_cr6().

Referenced by dmfe_init_dm910x().

◆ dmfe_program_DM9801() [1/2]

static void dmfe_program_DM9801 ( struct nic *  nic,
int   
)
static

Referenced by dmfe_parse_srom().

◆ dmfe_program_DM9802() [1/2]

static void dmfe_program_DM9802 ( struct nic *  nic)
static

Referenced by dmfe_parse_srom().

◆ dmfe_reset()

static void dmfe_reset ( struct nic *  nic)
static

Definition at line 246 of file dmfe.c.

247 {
248  /* system variable init */
249  db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
250 
251  db->NIC_capability = 0xf; /* All capability */
252  db->PHY_reg4 = 0x1e0;
253 
254  /* CR6 operation mode decision */
255  if (!chkmode || (db->chip_id == PCI_DM9132_ID) ||
256  (db->chip_revision >= 0x02000030)) {
257  db->cr6_data |= DMFE_TXTH_256;
258  db->cr0_data = CR0_DEFAULT;
259  db->dm910x_chk_mode = 4; /* Enter the normal mode */
260  } else {
261  db->cr6_data |= CR6_SFT; /* Store & Forward mode */
262  db->cr0_data = 0;
263  db->dm910x_chk_mode = 1; /* Enter the check mode */
264  }
265  /* Initialize DM910X board */
266  dmfe_init_dm910x(nic);
267 
268  return;
269 }
dmfe_private::cr6_data
u32 cr6_data
Definition: dmfe.c:154
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
dmfe_private::NIC_capability
u16 NIC_capability
Definition: dmfe.c:160
dmfe_private::chip_revision
u32 chip_revision
Definition: dmfe.c:151
chkmode
static u8 chkmode
Definition: dmfe.c:200
DMFE_TXTH_256
#define DMFE_TXTH_256
Definition: dmfe.c:100
dmfe_private::dm910x_chk_mode
u8 dm910x_chk_mode
Definition: dmfe.c:168
CR6_DEFAULT
#define CR6_DEFAULT
Definition: dmfe.c:79
dmfe_cr6_user_set
static u32 dmfe_cr6_user_set
Definition: dmfe.c:197
nic
Definition: nic.h:49
CR6_SFT
Definition: dmfe.c:190
CR0_DEFAULT
#define CR0_DEFAULT
Definition: dmfe.c:78
db
static struct dmfe_private * db
Definition: dmfe.c:177
dmfe_init_dm910x
static void dmfe_init_dm910x(struct nic *nic)
Definition: dmfe.c:278
dmfe_private::cr0_data
u32 cr0_data
Definition: dmfe.c:152
PCI_DM9132_ID
#define PCI_DM9132_ID
Definition: dmfe.c:62
dmfe_private::PHY_reg4
u16 PHY_reg4
Definition: dmfe.c:161

References dmfe_private::chip_id, dmfe_private::chip_revision, chkmode, dmfe_private::cr0_data, CR0_DEFAULT, dmfe_private::cr6_data, CR6_DEFAULT, CR6_SFT, db, dmfe_private::dm910x_chk_mode, dmfe_cr6_user_set, dmfe_init_dm910x(), DMFE_TXTH_256, dmfe_private::NIC_capability, PCI_DM9132_ID, and dmfe_private::PHY_reg4.

Referenced by dmfe_probe().

◆ dmfe_poll()

static int dmfe_poll ( struct nic *  nic,
int  retrieve 
)
static

Definition at line 345 of file dmfe.c.

346 {
347  u32 rdes0;
348  int entry = db->cur_rx % RX_DESC_CNT;
349  int rxlen;
350  rdes0 = le32_to_cpu(rxd[entry].rdes0);
351  if (rdes0 & 0x80000000)
352  return 0;
353 
354  if (!retrieve)
355  return 1;
356 
357  if ((rdes0 & 0x300) != 0x300) {
358  /* A packet without First/Last flag */
359  printf("strange Packet\n");
360  rxd[entry].rdes0 = cpu_to_le32(0x80000000);
361  return 0;
362  } else {
363  /* A packet with First/Last flag */
364  rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
365  /* error summary bit check */
366  if (rdes0 & 0x8000) {
367  printf("Error\n");
368  return 0;
369  }
370  if (!(rdes0 & 0x8000) ||
371  ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
372  if (db->dm910x_chk_mode & 1)
373  printf("Silly check mode\n");
374 
375  nic->packetlen = rxlen;
376  memcpy(nic->packet, rxb + (entry * RX_ALLOC_SIZE),
377  nic->packetlen);
378  }
379  }
380  rxd[entry].rdes0 = cpu_to_le32(0x80000000);
381  db->cur_rx++;
382  return 1;
383 }
printf
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
rxlen
Definition: sis900.h:35
le32_to_cpu
#define le32_to_cpu(value)
Definition: byteswap.h:113
dmfe_private::cr6_data
u32 cr6_data
Definition: dmfe.c:154
dmfe_private::cur_rx
u8 cur_rx
Definition: dmfe.c:174
rxb
#define rxb
Definition: dmfe.c:224
rxd
#define rxd
Definition: dmfe.c:223
RX_ALLOC_SIZE
#define RX_ALLOC_SIZE
Definition: dmfe.c:76
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
dmfe_private::dm910x_chk_mode
u8 dm910x_chk_mode
Definition: dmfe.c:168
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:107
nic::packetlen
unsigned int packetlen
Definition: nic.h:54
RX_DESC_CNT
#define RX_DESC_CNT
Definition: dmfe.c:71
nic
Definition: nic.h:49
db
static struct dmfe_private * db
Definition: dmfe.c:177
nic::packet
unsigned char * packet
Definition: nic.h:53
CR6_PM
Definition: dmfe.c:188
u32
uint32_t u32
Definition: stdint.h:23

References cpu_to_le32, dmfe_private::cr6_data, CR6_PM, dmfe_private::cur_rx, db, dmfe_private::dm910x_chk_mode, le32_to_cpu, memcpy(), nic::packet, nic::packetlen, printf(), rx_desc::rdes0, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, and rxlen.

◆ dmfe_irq()

static void dmfe_irq ( struct nic *nic  __unused,
irq_action_t action  __unused 
)
static

Definition at line 385 of file dmfe.c.

386 {
387  switch ( action ) {
388  case DISABLE :
389  break;
390  case ENABLE :
391  break;
392  case FORCE :
393  break;
394  }
395 }
DISABLE
Definition: nic.h:35
FORCE
Definition: nic.h:37
ENABLE
Definition: nic.h:36

References DISABLE, ENABLE, and FORCE.

◆ dmfe_transmit()

static void dmfe_transmit ( struct nic *  nic,
const char *  dest,
unsigned int  type,
unsigned int  size,
const char *  packet 
)
static

Definition at line 400 of file dmfe.c.

405 {
406  u16 nstype;
407  u8 *ptxb;
408 
409  ptxb = &txb[db->cur_tx];
410 
411  /* Stop Tx */
412  outl(0, BASE + DCR7);
413  memcpy(ptxb, dest, ETH_ALEN);
414  memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
415  nstype = htons((u16) type);
416  memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
417  memcpy(ptxb + ETH_HLEN, packet, size);
418 
419  size += ETH_HLEN;
420  while (size < ETH_ZLEN)
421  ptxb[size++] = '\0';
422 
423  /* setup the transmit descriptor */
424  txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size);
425  txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000); /* give ownership to device */
426 
427  /* immediate transmit demand */
428  outl(0x1, BASE + DCR1);
429  outl(db->cr7_data, BASE + DCR7);
430 
431  /* Point to next TX descriptor */
432  db->cur_tx++;
433  db->cur_tx = db->cur_tx % TX_DESC_CNT;
434 }
u16
uint16_t u16
Definition: stdint.h:21
dmfe_private::cur_tx
u8 cur_tx
Definition: dmfe.c:173
TX_DESC_CNT
#define TX_DESC_CNT
Definition: dmfe.c:70
type
uint32_t type
Operating system type.
Definition: ena.h:12
size
uint16_t size
Buffer size.
Definition: dwmac.h:14
DCR7
Definition: dmfe.c:181
DCR1
Definition: dmfe.c:180
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
ETH_HLEN
#define ETH_HLEN
Definition: if_ether.h:9
txd
#define txd
Definition: dmfe.c:221
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:107
outl
#define outl(data, io_addr)
Definition: io.h:329
ETH_ALEN
#define ETH_ALEN
Definition: if_ether.h:8
ETH_ZLEN
#define ETH_ZLEN
Definition: if_ether.h:10
nic
Definition: nic.h:49
db
static struct dmfe_private * db
Definition: dmfe.c:177
nic::node_addr
unsigned char * node_addr
Definition: nic.h:52
dest
if(len >=6 *4) __asm__ __volatile__("movsl" if(len >=5 *4) __asm__ __volatile__("movsl" if(len >=4 *4) __asm__ __volatile__("movsl" if(len >=3 *4) __asm__ __volatile__("movsl" if(len >=2 *4) __asm__ __volatile__("movsl" if(len >=1 *4) __asm__ __volatile__("movsl" if((len % 4) >=2) __asm__ __volatile__("movsw" if((len % 2) >=1) __asm__ __volatile__("movsb" return dest
Definition: string.h:150
dmfe_private::cr7_data
u32 cr7_data
Definition: dmfe.c:155
txb
#define txb
Definition: dmfe.c:222
htons
#define htons(value)
Definition: byteswap.h:135
u8
uint8_t u8
Definition: stdint.h:19
BASE
static long int BASE
Definition: dmfe.c:227

References BASE, cpu_to_le32, dmfe_private::cr7_data, dmfe_private::cur_tx, db, DCR1, DCR7, dest, ETH_ALEN, ETH_HLEN, ETH_ZLEN, htons, memcpy(), nic::node_addr, outl, size, TX_DESC_CNT, txb, txd, and type.

◆ dmfe_disable()

static void dmfe_disable ( struct nic *nic  __unused,
void *hwdev  __unused 
)
static

Definition at line 439 of file dmfe.c.

439  {
440  /* Reset & stop DM910X board */
441  outl(DM910X_RESET, BASE + DCR0);
442  udelay(5);
443  phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
444 
445 }
phy_write
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:882
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
DM910X_RESET
#define DM910X_RESET
Definition: dmfe.c:77
outl
#define outl(data, io_addr)
Definition: io.h:329
db
static struct dmfe_private * db
Definition: dmfe.c:177
DCR0
Definition: dmfe.c:180
BASE
static long int BASE
Definition: dmfe.c:227
dmfe_private::phy_addr
u8 phy_addr
Definition: dmfe.c:167

References BASE, dmfe_private::chip_id, db, DCR0, DM910X_RESET, outl, dmfe_private::phy_addr, phy_write(), and udelay().

◆ dmfe_probe()

static int dmfe_probe ( struct nic *  nic,
struct pci_device *  pci 
)
static

Definition at line 453 of file dmfe.c.

453  {
454 
455  uint32_t dev_rev, pci_pmr;
456  int i;
457 
458  if (pci->ioaddr == 0)
459  return 0;
460 
461  BASE = pci->ioaddr;
462  printf("dmfe.c: Found %s Vendor=0x%hX Device=0x%hX\n",
463  pci->id->name, pci->vendor, pci->device);
464 
465  /* Read Chip revision */
466  pci_read_config_dword(pci, PCI_REVISION, &dev_rev);
467  dprintf(("Revision %lX\n", dev_rev));
468 
469  /* point to private storage */
470  db = &dfx;
471 
472  db->chip_id = ((u32) pci->device << 16) | pci->vendor;
473  BASE = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
474  db->chip_revision = dev_rev;
475 
476  pci_read_config_dword(pci, 0x50, &pci_pmr);
477  pci_pmr &= 0x70000;
478  if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031))
479  db->chip_type = 1; /* DM9102A E3 */
480  else
481  db->chip_type = 0;
482 
483  dprintf(("Chip type : %d\n", db->chip_type));
484 
485  /* read 64 word srom data */
486  for (i = 0; i < 64; i++)
487  ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i));
488 
489  /* Set Node address */
490  for (i = 0; i < 6; i++)
491  nic->node_addr[i] = db->srom[20 + i];
492 
493  /* Print out some hardware info */
494  DBG ( "%s: %s at ioaddr %4.4lx\n",
495  pci->id->name, eth_ntoa ( nic->node_addr ), BASE );
496 
497  /* Set the card as PCI Bus Master */
498  adjust_pci_device(pci);
499 
500  dmfe_reset(nic);
501 
502  nic->irqno = 0;
503  nic->ioaddr = pci->ioaddr;
504 
505  /* point to NIC specific routines */
506  nic->nic_op = &dmfe_operations;
507 
508  return 1;
509 }
nic::irqno
unsigned char irqno
Definition: nic.h:56
u16
uint16_t u16
Definition: stdint.h:21
printf
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
pci_device::ioaddr
unsigned long ioaddr
I/O address.
Definition: pci.h:225
PCI_BASE_ADDRESS_0
#define PCI_BASE_ADDRESS_0
Definition: pci.h:62
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
dmfe_private::srom
unsigned char srom[128]
Definition: dmfe.c:171
adjust_pci_device
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:240
nic::ioaddr
unsigned int ioaddr
Definition: nic.h:55
dmfe_private::chip_revision
u32 chip_revision
Definition: dmfe.c:151
pci_device::device
uint16_t device
Device ID.
Definition: pci.h:229
pci_read_config_dword
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
u32
#define u32
Definition: vga.h:21
pci_bar_start
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
dfx
static struct dmfe_private dfx
eth_ntoa
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
dprintf
#define dprintf(x)
Definition: dmfe.c:54
nic
Definition: nic.h:49
uint32_t
unsigned int uint32_t
Definition: stdint.h:12
pci_device_id::name
const char * name
Name.
Definition: pci.h:176
pci_device::vendor
uint16_t vendor
Vendor ID.
Definition: pci.h:227
dmfe_reset
static void dmfe_reset(struct nic *nic)
Definition: dmfe.c:246
dmfe_private::chip_type
u8 chip_type
Definition: dmfe.c:164
db
static struct dmfe_private * db
Definition: dmfe.c:177
nic::node_addr
unsigned char * node_addr
Definition: nic.h:52
dmfe_operations
static struct nic_operations dmfe_operations
Definition: dmfe.c:194
pci_device::id
struct pci_device_id * id
Driver device ID.
Definition: pci.h:247
cpu_to_le16
#define cpu_to_le16(value)
Definition: byteswap.h:106
PCI_REVISION
#define PCI_REVISION
PCI revision.
Definition: pci.h:44
DBG
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
nic::nic_op
struct nic_operations * nic_op
Definition: nic.h:50
BASE
static long int BASE
Definition: dmfe.c:227
read_srom_word
static u16 read_srom_word(long ioaddr, int offset)
Definition: dmfe.c:664

References adjust_pci_device(), BASE, dmfe_private::chip_id, dmfe_private::chip_revision, dmfe_private::chip_type, cpu_to_le16, db, DBG, pci_device::device, dfx, dmfe_operations, dmfe_reset(), dprintf, eth_ntoa(), pci_device::id, nic::ioaddr, pci_device::ioaddr, nic::irqno, pci_device_id::name, nic::nic_op, nic::node_addr, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_read_config_dword(), PCI_REVISION, printf(), read_srom_word(), dmfe_private::srom, u32, and pci_device::vendor.

◆ dmfe_descriptor_init() [2/2]

static void dmfe_descriptor_init ( struct nic *nic  __unused,
unsigned long  ioaddr 
)
static

Definition at line 516 of file dmfe.c.

517 {
518  int i;
519  db->cur_tx = 0;
520  db->cur_rx = 0;
521 
522  /* tx descriptor start pointer */
523  outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
524 
525  /* rx descriptor start pointer */
526  outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
527 
528  /* Init Transmit chain */
529  for (i = 0; i < TX_DESC_CNT; i++) {
530  txd[i].tx_buf_ptr = &txb[i];
531  txd[i].tdes0 = cpu_to_le32(0);
532  txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
533  txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
534  txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
535  txd[i].next_tx_desc = &txd[i + 1];
536  }
537  /* Mark the last entry as wrapping the ring */
538  txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
539  txd[i - 1].next_tx_desc = &txd[0];
540 
541  /* receive descriptor chain */
542  for (i = 0; i < RX_DESC_CNT; i++) {
543  rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
544  rxd[i].rdes0 = cpu_to_le32(0x80000000);
545  rxd[i].rdes1 = cpu_to_le32(0x01000600);
546  rxd[i].rdes2 =
547  cpu_to_le32(virt_to_bus(&rxb[i * RX_ALLOC_SIZE]));
548  rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
549  rxd[i].next_rx_desc = &rxd[i + 1];
550  }
551  /* Mark the last entry as wrapping the ring */
552  rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
553  rxd[i - 1].next_rx_desc = &rxd[0];
554 
555 }
virt_to_le32desc
#define virt_to_le32desc(addr)
Definition: dmfe.c:58
dmfe_private::cur_rx
u8 cur_rx
Definition: dmfe.c:174
dmfe_private::cur_tx
u8 cur_tx
Definition: dmfe.c:173
TX_DESC_CNT
#define TX_DESC_CNT
Definition: dmfe.c:70
rxb
#define rxb
Definition: dmfe.c:224
DCR4
Definition: dmfe.c:180
rxd
#define rxd
Definition: dmfe.c:223
RX_ALLOC_SIZE
#define RX_ALLOC_SIZE
Definition: dmfe.c:76
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
virt_to_bus
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
txd
#define txd
Definition: dmfe.c:221
DCR3
Definition: dmfe.c:180
cpu_to_le32
#define cpu_to_le32(value)
Definition: byteswap.h:107
RX_DESC_CNT
#define RX_DESC_CNT
Definition: dmfe.c:71
outl
#define outl(data, io_addr)
Definition: io.h:329
db
static struct dmfe_private * db
Definition: dmfe.c:177
txb
#define txb
Definition: dmfe.c:222

References cpu_to_le32, dmfe_private::cur_rx, dmfe_private::cur_tx, db, DCR3, DCR4, ioaddr, outl, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, TX_DESC_CNT, txb, txd, virt_to_bus(), and virt_to_le32desc.

◆ dm9132_id_table() [2/2]

static void dm9132_id_table ( struct nic *nic  __unused)
static

Definition at line 579 of file dmfe.c.

580 {
581 #ifdef LINUX
582  u16 *addrptr;
583  u8 dmi_addr[8];
584  unsigned long ioaddr = BASE + 0xc0; /* ID Table */
585  u32 hash_val;
586  u16 i, hash_table[4];
587 #endif
588  dprintf(("dm9132_id_table\n"));
589 
590  printf("FIXME: This function is broken. If you have this card contact "
591  "Timothy Legge at the etherboot-user list\n");
592 
593 #ifdef LINUX
594  //DMFE_DBUG(0, "dm9132_id_table()", 0);
595 
596  /* Node address */
597  addrptr = (u16 *) nic->node_addr;
598  outw(addrptr[0], ioaddr);
599  ioaddr += 4;
600  outw(addrptr[1], ioaddr);
601  ioaddr += 4;
602  outw(addrptr[2], ioaddr);
603  ioaddr += 4;
604 
605  /* Clear Hash Table */
606  for (i = 0; i < 4; i++)
607  hash_table[i] = 0x0;
608 
609  /* broadcast address */
610  hash_table[3] = 0x8000;
611 
612  /* the multicast address in Hash Table : 64 bits */
613  for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
614  hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
615  hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
616  }
617 
618  /* Write the hash table to MAC MD table */
619  for (i = 0; i < 4; i++, ioaddr += 4)
620  outw(hash_table[i], ioaddr);
621 #endif
622 }
u16
#define u16
Definition: vga.h:20
u16
uint16_t u16
Definition: stdint.h:21
printf
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
outw
#define outw(data, io_addr)
Definition: io.h:319
ioaddr
static unsigned long ioaddr
Definition: davicom.c:129
dprintf
#define dprintf(x)
Definition: dmfe.c:54
nic
Definition: nic.h:49
nic::node_addr
unsigned char * node_addr
Definition: nic.h:52
u8
uint8_t u8
Definition: stdint.h:19
BASE
static long int BASE
Definition: dmfe.c:227
u32
uint32_t u32
Definition: stdint.h:23

References BASE, dprintf, ioaddr, nic::node_addr, outw, printf(), and u16.

◆ dmfe_set_phyxcer() [2/2]

static void dmfe_set_phyxcer ( struct nic *nic  __unused)
static

Definition at line 762 of file dmfe.c.

763 {
764  u16 phy_reg;
765 
766  /* Select 10/100M phyxcer */
767  db->cr6_data &= ~0x40000;
768  update_cr6(db->cr6_data, BASE);
769 
770  /* DM9009 Chip: Phyxcer reg18 bit12=0 */
771  if (db->chip_id == PCI_DM9009_ID) {
772  phy_reg =
773  phy_read(BASE, db->phy_addr, 18,
774  db->chip_id) & ~0x1000;
775  phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id);
776  }
777 
778  /* Phyxcer capability setting */
779  phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0;
780 
781  if (db->media_mode & DMFE_AUTO) {
782  /* AUTO Mode */
783  phy_reg |= db->PHY_reg4;
784  } else {
785  /* Force Mode */
786  switch (db->media_mode) {
787  case DMFE_10MHF:
788  phy_reg |= 0x20;
789  break;
790  case DMFE_10MFD:
791  phy_reg |= 0x40;
792  break;
793  case DMFE_100MHF:
794  phy_reg |= 0x80;
795  break;
796  case DMFE_100MFD:
797  phy_reg |= 0x100;
798  break;
799  }
800  if (db->chip_id == PCI_DM9009_ID)
801  phy_reg &= 0x61;
802  }
803 
804  /* Write new capability to Phyxcer Reg4 */
805  if (!(phy_reg & 0x01e0)) {
806  phy_reg |= db->PHY_reg4;
807  db->media_mode |= DMFE_AUTO;
808  }
809  phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id);
810 
811  /* Restart Auto-Negotiation */
812  if (db->chip_type && (db->chip_id == PCI_DM9102_ID))
813  phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id);
814  if (!db->chip_type)
815  phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id);
816 }
u16
uint16_t u16
Definition: stdint.h:21
dmfe_private::cr6_data
u32 cr6_data
Definition: dmfe.c:154
DMFE_100MFD
#define DMFE_100MFD
Definition: dmfe.c:93
phy_write
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:882
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
DMFE_10MFD
#define DMFE_10MFD
Definition: dmfe.c:92
DMFE_AUTO
#define DMFE_AUTO
Definition: dmfe.c:94
DMFE_10MHF
#define DMFE_10MHF
Definition: dmfe.c:90
PCI_DM9102_ID
#define PCI_DM9102_ID
Definition: dmfe.c:63
dmfe_private::media_mode
u8 media_mode
Definition: dmfe.c:165
PCI_DM9009_ID
#define PCI_DM9009_ID
Definition: dmfe.c:65
dmfe_private::chip_type
u8 chip_type
Definition: dmfe.c:164
db
static struct dmfe_private * db
Definition: dmfe.c:177
update_cr6
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:562
DMFE_100MHF
#define DMFE_100MHF
Definition: dmfe.c:91
phy_read
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:936
BASE
static long int BASE
Definition: dmfe.c:227
dmfe_private::phy_addr
u8 phy_addr
Definition: dmfe.c:167
dmfe_private::PHY_reg4
u16 PHY_reg4
Definition: dmfe.c:161

References BASE, dmfe_private::chip_id, dmfe_private::chip_type, dmfe_private::cr6_data, db, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_10MHF, DMFE_AUTO, dmfe_private::media_mode, PCI_DM9009_ID, PCI_DM9102_ID, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, phy_write(), and update_cr6().

◆ dmfe_program_DM9801() [2/2]

static void dmfe_program_DM9801 ( struct nic *nic  __unused,
int  HPNA_rev 
)
static

Definition at line 1152 of file dmfe.c.

1153 {
1154  u32 reg17, reg25;
1155 
1156  if (!HPNA_NoiseFloor)
1157  HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1158  switch (HPNA_rev) {
1159  case 0xb900: /* DM9801 E3 */
1160  db->HPNA_command |= 0x1000;
1161  reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id);
1162  reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1163  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1164  break;
1165  case 0xb901: /* DM9801 E4 */
1166  reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1167  reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1168  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1169  reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1170  break;
1171  case 0xb902: /* DM9801 E5 */
1172  case 0xb903: /* DM9801 E6 */
1173  default:
1174  db->HPNA_command |= 0x1000;
1175  reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1176  reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1177  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1178  reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1179  break;
1180  }
1181  phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1182  phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id);
1183  phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id);
1184 }
phy_write
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:882
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
DM9801_NOISE_FLOOR
#define DM9801_NOISE_FLOOR
Definition: dmfe.c:87
db
static struct dmfe_private * db
Definition: dmfe.c:177
HPNA_NoiseFloor
static u8 HPNA_NoiseFloor
Definition: dmfe.c:204
phy_read
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:936
dmfe_private::HPNA_command
u16 HPNA_command
Definition: dmfe.c:158
BASE
static long int BASE
Definition: dmfe.c:227
u32
uint32_t u32
Definition: stdint.h:23
dmfe_private::phy_addr
u8 phy_addr
Definition: dmfe.c:167

References BASE, dmfe_private::chip_id, db, DM9801_NOISE_FLOOR, dmfe_private::HPNA_command, HPNA_NoiseFloor, dmfe_private::phy_addr, phy_read(), and phy_write().

◆ dmfe_program_DM9802() [2/2]

static void dmfe_program_DM9802 ( struct nic *nic  __unused)
static

Definition at line 1191 of file dmfe.c.

1192 {
1193  u32 phy_reg;
1194 
1195  if (!HPNA_NoiseFloor)
1196  HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1197  phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1198  phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1199  phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor;
1200  phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id);
1201 }
phy_write
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:882
dmfe_private::chip_id
u32 chip_id
Definition: dmfe.c:150
DM9802_NOISE_FLOOR
#define DM9802_NOISE_FLOOR
Definition: dmfe.c:88
db
static struct dmfe_private * db
Definition: dmfe.c:177
HPNA_NoiseFloor
static u8 HPNA_NoiseFloor
Definition: dmfe.c:204
phy_read
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:936
dmfe_private::HPNA_command
u16 HPNA_command
Definition: dmfe.c:158
BASE
static long int BASE
Definition: dmfe.c:227
u32
uint32_t u32
Definition: stdint.h:23
dmfe_private::phy_addr
u8 phy_addr
Definition: dmfe.c:167

References BASE, dmfe_private::chip_id, db, DM9802_NOISE_FLOOR, dmfe_private::HPNA_command, HPNA_NoiseFloor, dmfe_private::phy_addr, phy_read(), and phy_write().

◆ PCI_DRIVER()

PCI_DRIVER ( dmfe_driver  ,
dmfe_nics  ,
PCI_NO_CLASS   
)

◆ DRIVER()

DRIVER ( "DMFE/PCI"  ,
nic_driver  ,
pci_driver  ,
dmfe_driver  ,
dmfe_probe  ,
dmfe_disable  ,
dmfe_bufs   
)

Variable Documentation

◆ dfx

struct dmfe_private dfx
static

Referenced by dmfe_probe().

◆ db

struct dmfe_private* db
static

Definition at line 177 of file dmfe.c.

Referenced by dmfe_descriptor_init(), dmfe_disable(), dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_poll(), dmfe_probe(), dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_reset(), dmfe_set_phyxcer(), dmfe_transmit(), efi_undi_get_init_info(), efi_undi_get_status(), efi_undi_issue(), efi_undi_receive(), efi_undi_station_address(), nii_get_init_info(), nii_get_station_address(), nii_initialise_flags(), nii_issue_cpb_db(), nii_issue_db(), nii_poll(), nii_poll_rx(), and send_filter_frame().

◆ dmfe_operations

static struct nic_operations dmfe_operations
static
Initial value:
= {
.connect = dummy_connect,
.poll = dmfe_poll,
.transmit = dmfe_transmit,
.irq = dmfe_irq,
}
dummy_connect
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:175
dmfe_transmit
static void dmfe_transmit(struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *packet)
Definition: dmfe.c:400
dmfe_poll
static int dmfe_poll(struct nic *nic, int retrieve)
Definition: dmfe.c:345
dmfe_irq
static void dmfe_irq(struct nic *nic __unused, irq_action_t action __unused)
Definition: dmfe.c:385

Definition at line 194 of file dmfe.c.

Referenced by dmfe_probe().

◆ dmfe_media_mode

unsigned char dmfe_media_mode = DMFE_AUTO
static

Definition at line 196 of file dmfe.c.

Referenced by dmfe_init_dm910x(), and dmfe_parse_srom().

◆ dmfe_cr6_user_set

u32 dmfe_cr6_user_set
static

Definition at line 197 of file dmfe.c.

Referenced by dmfe_reset().

◆ chkmode

u8 chkmode = 1
static

Definition at line 200 of file dmfe.c.

Referenced by dmfe_reset().

◆ HPNA_mode

u8 HPNA_mode
static

Definition at line 201 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_rx_cmd

u8 HPNA_rx_cmd
static

Definition at line 202 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_tx_cmd

u8 HPNA_tx_cmd
static

Definition at line 203 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_NoiseFloor

u8 HPNA_NoiseFloor
static

Definition at line 204 of file dmfe.c.

Referenced by dmfe_program_DM9801(), and dmfe_program_DM9802().

◆ SF_mode

u8 SF_mode
static

Definition at line 205 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ BASE

long int BASE
static

Definition at line 227 of file dmfe.c.

Referenced by dm9132_id_table(), dmfe_disable(), dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_probe(), dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_set_phyxcer(), dmfe_transmit(), and send_filter_frame().

◆ dmfe_nics

struct pci_device_id dmfe_nics[]
static
Initial value:
= {
PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0),
}
PCI_ROM
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:307

Definition at line 1211 of file dmfe.c.

Generated by   doxygen 1.8.15