iPXE
Data Structures | Macros | Enumerations | Functions | Variables
dmfe.c File Reference
#include "etherboot.h"
#include "nic.h"
#include <ipxe/pci.h>
#include <ipxe/ethernet.h>

Go to the source code of this file.

Data Structures

struct  tx_desc
 
struct  rx_desc
 
struct  dmfe_private
 

Macros

#define dprintf(x)
 
#define virt_to_le32desc(addr)   cpu_to_le32(virt_to_bus(addr))
 
#define le32desc_to_virt(addr)   bus_to_virt(le32_to_cpu(addr))
 
#define PCI_DM9132_ID   0x91321282 /* Davicom DM9132 ID */
 
#define PCI_DM9102_ID   0x91021282 /* Davicom DM9102 ID */
 
#define PCI_DM9100_ID   0x91001282 /* Davicom DM9100 ID */
 
#define PCI_DM9009_ID   0x90091282 /* Davicom DM9009 ID */
 
#define DM9102_IO_SIZE   0x80
 
#define DM9102A_IO_SIZE   0x100
 
#define TX_MAX_SEND_CNT   0x1 /* Maximum tx packet per time */
 
#define TX_DESC_CNT   0x10 /* Allocated Tx descriptors */
 
#define RX_DESC_CNT   0x20 /* Allocated Rx descriptors */
 
#define TX_FREE_DESC_CNT   (TX_DESC_CNT - 2) /* Max TX packet count */
 
#define TX_WAKE_DESC_CNT   (TX_DESC_CNT - 3) /* TX wakeup count */
 
#define DESC_ALL_CNT   (TX_DESC_CNT + RX_DESC_CNT)
 
#define TX_BUF_ALLOC   0x600
 
#define RX_ALLOC_SIZE   0x620
 
#define DM910X_RESET   1
 
#define CR0_DEFAULT   0x00E00000 /* TX & RX burst mode */
 
#define CR6_DEFAULT   0x00080000 /* HD */
 
#define CR7_DEFAULT   0x180c1
 
#define CR15_DEFAULT   0x06 /* TxJabber RxWatchdog */
 
#define TDES0_ERR_MASK   0x4302 /* TXJT, LC, EC, FUE */
 
#define MAX_PACKET_SIZE   1514
 
#define DMFE_MAX_MULTICAST   14
 
#define RX_COPY_SIZE   100
 
#define MAX_CHECK_PACKET   0x8000
 
#define DM9801_NOISE_FLOOR   8
 
#define DM9802_NOISE_FLOOR   5
 
#define DMFE_10MHF   0
 
#define DMFE_100MHF   1
 
#define DMFE_10MFD   4
 
#define DMFE_100MFD   5
 
#define DMFE_AUTO   8
 
#define DMFE_1M_HPNA   0x10
 
#define DMFE_TXTH_72   0x400000 /* TX TH 72 byte */
 
#define DMFE_TXTH_96   0x404000 /* TX TH 96 byte */
 
#define DMFE_TXTH_128   0x0000 /* TX TH 128 byte */
 
#define DMFE_TXTH_256   0x4000 /* TX TH 256 byte */
 
#define DMFE_TXTH_512   0x8000 /* TX TH 512 byte */
 
#define DMFE_TXTH_1K   0xC000 /* TX TH 1K byte */
 
#define DMFE_TIMER_WUT   (jiffies + HZ * 1) /* timer wakeup time : 1 second */
 
#define DMFE_TX_TIMEOUT   ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
 
#define DMFE_TX_KICK   (HZ/2) /* tx packet Kick-out time 0.5 s" */
 
#define DMFE_DBUG(dbug_now, msg, value)   if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
 
#define SHOW_MEDIA_TYPE(mode)   printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
 
#define CR9_SROM_READ   0x4800
 
#define CR9_SRCS   0x1
 
#define CR9_SRCLK   0x2
 
#define CR9_CRDOUT   0x8
 
#define SROM_DATA_0   0x0
 
#define SROM_DATA_1   0x4
 
#define PHY_DATA_1   0x20000
 
#define PHY_DATA_0   0x00000
 
#define MDCLKH   0x10000
 
#define PHY_POWER_DOWN   0x800
 
#define SROM_V41_CODE   0x14
 
#define SROM_CLK_WRITE(data, ioaddr)   outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
 
#define __CHK_IO_SIZE(pci_id, dev_rev)   ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
 
#define CHK_IO_SIZE(pci_dev, dev_rev)   __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
 
#define DEVICE   net_device
 
#define txd   dmfe_bufs.txd
 
#define txb   dmfe_bufs.txb
 
#define rxd   dmfe_bufs.rxd
 
#define rxb   dmfe_bufs.rxb
 
#define board_found   1
 
#define valid_link   0
 

Enumerations

enum  dmfe_offsets {
  DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18,
  DCR4 = 0x20, DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38,
  DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58,
  DCR12 = 0x60, DCR13 = 0x68, DCR14, DCR15 = 0x78
}
 
enum  dmfe_CR6_bits {
  CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
  CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000,
  CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
}
 

Functions

 FILE_LICENCE (GPL2_OR_LATER)
 
static u16 read_srom_word (long ioaddr, int offset)
 
static void dmfe_init_dm910x (struct nic *nic)
 
static void dmfe_descriptor_init (struct nic *, unsigned long ioaddr)
 
static void update_cr6 (u32, unsigned long)
 
static void send_filter_frame (struct nic *nic)
 
static void dm9132_id_table (struct nic *nic)
 
static u16 phy_read (unsigned long, u8, u8, u32)
 
static void phy_write (unsigned long, u8, u8, u16, u32)
 
static void phy_write_1bit (unsigned long, u32)
 
static u16 phy_read_1bit (unsigned long)
 
static void dmfe_set_phyxcer (struct nic *nic)
 
static void dmfe_parse_srom (struct nic *nic)
 
static void dmfe_program_DM9801 (struct nic *nic, int)
 
static void dmfe_program_DM9802 (struct nic *nic)
 
static void dmfe_reset (struct nic *nic)
 
static int dmfe_poll (struct nic *nic, int retrieve)
 
static void dmfe_irq (struct nic *nic __unused, irq_action_t action __unused)
 
static void dmfe_transmit (struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *packet)
 
static void dmfe_disable (struct nic *nic __unused)
 
static int dmfe_probe (struct nic *nic, struct pci_device *pci)
 
static void dmfe_descriptor_init (struct nic *nic __unused, unsigned long ioaddr)
 
static void dm9132_id_table (struct nic *nic __unused)
 
static void dmfe_set_phyxcer (struct nic *nic __unused)
 
static void dmfe_program_DM9801 (struct nic *nic __unused, int HPNA_rev)
 
static void dmfe_program_DM9802 (struct nic *nic __unused)
 
 PCI_DRIVER (dmfe_driver, dmfe_nics, PCI_NO_CLASS)
 
 DRIVER ("DMFE/PCI", nic_driver, pci_driver, dmfe_driver, dmfe_probe, dmfe_disable)
 

Variables

static struct dmfe_private dfx
 
static struct dmfe_privatedb
 
static struct nic_operations dmfe_operations
 
static unsigned char dmfe_media_mode = DMFE_AUTO
 
static u32 dmfe_cr6_user_set
 
static u8 chkmode = 1
 
static u8 HPNA_mode
 
static u8 HPNA_rx_cmd
 
static u8 HPNA_tx_cmd
 
static u8 HPNA_NoiseFloor
 
static u8 SF_mode
 
struct {
   struct tx_desc   txd [TX_DESC_CNT]
 
   unsigned char   txb [TX_BUF_ALLOC *TX_DESC_CNT]
 
   struct rx_desc   rxd [RX_DESC_CNT]
 
   unsigned char   rxb [RX_ALLOC_SIZE *RX_DESC_CNT]
 
__shared
 
static long int BASE
 
static struct pci_device_id dmfe_nics []
 

Macro Definition Documentation

◆ dprintf

#define dprintf (   x)

Definition at line 54 of file dmfe.c.

◆ virt_to_le32desc

#define virt_to_le32desc (   addr)    cpu_to_le32(virt_to_bus(addr))

Definition at line 58 of file dmfe.c.

◆ le32desc_to_virt

#define le32desc_to_virt (   addr)    bus_to_virt(le32_to_cpu(addr))

Definition at line 59 of file dmfe.c.

◆ PCI_DM9132_ID

#define PCI_DM9132_ID   0x91321282 /* Davicom DM9132 ID */

Definition at line 62 of file dmfe.c.

◆ PCI_DM9102_ID

#define PCI_DM9102_ID   0x91021282 /* Davicom DM9102 ID */

Definition at line 63 of file dmfe.c.

◆ PCI_DM9100_ID

#define PCI_DM9100_ID   0x91001282 /* Davicom DM9100 ID */

Definition at line 64 of file dmfe.c.

◆ PCI_DM9009_ID

#define PCI_DM9009_ID   0x90091282 /* Davicom DM9009 ID */

Definition at line 65 of file dmfe.c.

◆ DM9102_IO_SIZE

#define DM9102_IO_SIZE   0x80

Definition at line 67 of file dmfe.c.

◆ DM9102A_IO_SIZE

#define DM9102A_IO_SIZE   0x100

Definition at line 68 of file dmfe.c.

◆ TX_MAX_SEND_CNT

#define TX_MAX_SEND_CNT   0x1 /* Maximum tx packet per time */

Definition at line 69 of file dmfe.c.

◆ TX_DESC_CNT

#define TX_DESC_CNT   0x10 /* Allocated Tx descriptors */

Definition at line 70 of file dmfe.c.

◆ RX_DESC_CNT

#define RX_DESC_CNT   0x20 /* Allocated Rx descriptors */

Definition at line 71 of file dmfe.c.

◆ TX_FREE_DESC_CNT

#define TX_FREE_DESC_CNT   (TX_DESC_CNT - 2) /* Max TX packet count */

Definition at line 72 of file dmfe.c.

◆ TX_WAKE_DESC_CNT

#define TX_WAKE_DESC_CNT   (TX_DESC_CNT - 3) /* TX wakeup count */

Definition at line 73 of file dmfe.c.

◆ DESC_ALL_CNT

#define DESC_ALL_CNT   (TX_DESC_CNT + RX_DESC_CNT)

Definition at line 74 of file dmfe.c.

◆ TX_BUF_ALLOC

#define TX_BUF_ALLOC   0x600

Definition at line 75 of file dmfe.c.

◆ RX_ALLOC_SIZE

#define RX_ALLOC_SIZE   0x620

Definition at line 76 of file dmfe.c.

◆ DM910X_RESET

#define DM910X_RESET   1

Definition at line 77 of file dmfe.c.

◆ CR0_DEFAULT

#define CR0_DEFAULT   0x00E00000 /* TX & RX burst mode */

Definition at line 78 of file dmfe.c.

◆ CR6_DEFAULT

#define CR6_DEFAULT   0x00080000 /* HD */

Definition at line 79 of file dmfe.c.

◆ CR7_DEFAULT

#define CR7_DEFAULT   0x180c1

Definition at line 80 of file dmfe.c.

◆ CR15_DEFAULT

#define CR15_DEFAULT   0x06 /* TxJabber RxWatchdog */

Definition at line 81 of file dmfe.c.

◆ TDES0_ERR_MASK

#define TDES0_ERR_MASK   0x4302 /* TXJT, LC, EC, FUE */

Definition at line 82 of file dmfe.c.

◆ MAX_PACKET_SIZE

#define MAX_PACKET_SIZE   1514

Definition at line 83 of file dmfe.c.

◆ DMFE_MAX_MULTICAST

#define DMFE_MAX_MULTICAST   14

Definition at line 84 of file dmfe.c.

◆ RX_COPY_SIZE

#define RX_COPY_SIZE   100

Definition at line 85 of file dmfe.c.

◆ MAX_CHECK_PACKET

#define MAX_CHECK_PACKET   0x8000

Definition at line 86 of file dmfe.c.

◆ DM9801_NOISE_FLOOR

#define DM9801_NOISE_FLOOR   8

Definition at line 87 of file dmfe.c.

◆ DM9802_NOISE_FLOOR

#define DM9802_NOISE_FLOOR   5

Definition at line 88 of file dmfe.c.

◆ DMFE_10MHF

#define DMFE_10MHF   0

Definition at line 90 of file dmfe.c.

◆ DMFE_100MHF

#define DMFE_100MHF   1

Definition at line 91 of file dmfe.c.

◆ DMFE_10MFD

#define DMFE_10MFD   4

Definition at line 92 of file dmfe.c.

◆ DMFE_100MFD

#define DMFE_100MFD   5

Definition at line 93 of file dmfe.c.

◆ DMFE_AUTO

#define DMFE_AUTO   8

Definition at line 94 of file dmfe.c.

◆ DMFE_1M_HPNA

#define DMFE_1M_HPNA   0x10

Definition at line 95 of file dmfe.c.

◆ DMFE_TXTH_72

#define DMFE_TXTH_72   0x400000 /* TX TH 72 byte */

Definition at line 97 of file dmfe.c.

◆ DMFE_TXTH_96

#define DMFE_TXTH_96   0x404000 /* TX TH 96 byte */

Definition at line 98 of file dmfe.c.

◆ DMFE_TXTH_128

#define DMFE_TXTH_128   0x0000 /* TX TH 128 byte */

Definition at line 99 of file dmfe.c.

◆ DMFE_TXTH_256

#define DMFE_TXTH_256   0x4000 /* TX TH 256 byte */

Definition at line 100 of file dmfe.c.

◆ DMFE_TXTH_512

#define DMFE_TXTH_512   0x8000 /* TX TH 512 byte */

Definition at line 101 of file dmfe.c.

◆ DMFE_TXTH_1K

#define DMFE_TXTH_1K   0xC000 /* TX TH 1K byte */

Definition at line 102 of file dmfe.c.

◆ DMFE_TIMER_WUT

#define DMFE_TIMER_WUT   (jiffies + HZ * 1) /* timer wakeup time : 1 second */

Definition at line 104 of file dmfe.c.

◆ DMFE_TX_TIMEOUT

#define DMFE_TX_TIMEOUT   ((3*HZ)/2) /* tx packet time-out time 1.5 s" */

Definition at line 105 of file dmfe.c.

◆ DMFE_TX_KICK

#define DMFE_TX_KICK   (HZ/2) /* tx packet Kick-out time 0.5 s" */

Definition at line 106 of file dmfe.c.

◆ DMFE_DBUG

#define DMFE_DBUG (   dbug_now,
  msg,
  value 
)    if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))

Definition at line 108 of file dmfe.c.

◆ SHOW_MEDIA_TYPE

#define SHOW_MEDIA_TYPE (   mode)    printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");

Definition at line 110 of file dmfe.c.

◆ CR9_SROM_READ

#define CR9_SROM_READ   0x4800

Definition at line 114 of file dmfe.c.

◆ CR9_SRCS

#define CR9_SRCS   0x1

Definition at line 115 of file dmfe.c.

◆ CR9_SRCLK

#define CR9_SRCLK   0x2

Definition at line 116 of file dmfe.c.

◆ CR9_CRDOUT

#define CR9_CRDOUT   0x8

Definition at line 117 of file dmfe.c.

◆ SROM_DATA_0

#define SROM_DATA_0   0x0

Definition at line 118 of file dmfe.c.

◆ SROM_DATA_1

#define SROM_DATA_1   0x4

Definition at line 119 of file dmfe.c.

◆ PHY_DATA_1

#define PHY_DATA_1   0x20000

Definition at line 120 of file dmfe.c.

◆ PHY_DATA_0

#define PHY_DATA_0   0x00000

Definition at line 121 of file dmfe.c.

◆ MDCLKH

#define MDCLKH   0x10000

Definition at line 122 of file dmfe.c.

◆ PHY_POWER_DOWN

#define PHY_POWER_DOWN   0x800

Definition at line 124 of file dmfe.c.

◆ SROM_V41_CODE

#define SROM_V41_CODE   0x14

Definition at line 126 of file dmfe.c.

◆ SROM_CLK_WRITE

Definition at line 128 of file dmfe.c.

◆ __CHK_IO_SIZE

#define __CHK_IO_SIZE (   pci_id,
  dev_rev 
)    ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE

Definition at line 130 of file dmfe.c.

◆ CHK_IO_SIZE

#define CHK_IO_SIZE (   pci_dev,
  dev_rev 
)    __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)

Definition at line 131 of file dmfe.c.

◆ DEVICE

#define DEVICE   net_device

Definition at line 134 of file dmfe.c.

◆ txd

#define txd   dmfe_bufs.txd

Definition at line 220 of file dmfe.c.

◆ txb

#define txb   dmfe_bufs.txb

Definition at line 221 of file dmfe.c.

◆ rxd

#define rxd   dmfe_bufs.rxd

Definition at line 222 of file dmfe.c.

◆ rxb

#define rxb   dmfe_bufs.rxb

Definition at line 223 of file dmfe.c.

◆ board_found

#define board_found   1

Definition at line 450 of file dmfe.c.

◆ valid_link

#define valid_link   0

Definition at line 451 of file dmfe.c.

Enumeration Type Documentation

◆ dmfe_offsets

Enumerator
DCR0 
DCR1 
DCR2 
DCR3 
DCR4 
DCR5 
DCR6 
DCR7 
DCR8 
DCR9 
DCR10 
DCR11 
DCR12 
DCR13 
DCR14 
DCR15 

Definition at line 179 of file dmfe.c.

179  {
180  DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
181  DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
182  DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 =
183  0x70,
184  DCR15 = 0x78
185 };
Definition: dmfe.c:180
Definition: dmfe.c:182
Definition: dmfe.c:181
Definition: dmfe.c:180
Definition: dmfe.c:181
Definition: dmfe.c:180
Definition: dmfe.c:182
Definition: dmfe.c:184
Definition: dmfe.c:180
Definition: dmfe.c:181
Definition: dmfe.c:181
Definition: dmfe.c:182
Definition: dmfe.c:182
Definition: dmfe.c:182
Definition: dmfe.c:180
Definition: dmfe.c:181

◆ dmfe_CR6_bits

Enumerator
CR6_RXSC 
CR6_PBF 
CR6_PM 
CR6_PAM 
CR6_FDM 
CR6_TXSC 
CR6_STI 
CR6_SFT 
CR6_RXA 
CR6_NO_PURGE 

Definition at line 187 of file dmfe.c.

187  {
188  CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
189  CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
190  CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
191 };
Definition: dmfe.c:188
Definition: dmfe.c:189
Definition: dmfe.c:189
Definition: dmfe.c:188
Definition: dmfe.c:190
Definition: dmfe.c:188
Definition: dmfe.c:190
Definition: dmfe.c:189
Definition: dmfe.c:188

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER  )

◆ read_srom_word()

static u16 read_srom_word ( long  ioaddr,
int  offset 
)
static

Definition at line 663 of file dmfe.c.

664 {
665  int i;
666  u16 srom_data = 0;
667  long cr9_ioaddr = ioaddr + DCR9;
668 
669  outl(CR9_SROM_READ, cr9_ioaddr);
670  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
671 
672  /* Send the Read Command 110b */
673  SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
674  SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
675  SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
676 
677  /* Send the offset */
678  for (i = 5; i >= 0; i--) {
679  srom_data =
680  (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
681  SROM_CLK_WRITE(srom_data, cr9_ioaddr);
682  }
683 
684  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
685 
686  for (i = 16; i > 0; i--) {
687  outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
688  udelay(5);
689  srom_data =
690  (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1
691  : 0);
692  outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
693  udelay(5);
694  }
695 
696  outl(CR9_SROM_READ, cr9_ioaddr);
697  return srom_data;
698 }
uint16_t u16
Definition: stdint.h:21
#define CR9_SRCLK
Definition: dmfe.c:116
Definition: dmfe.c:181
#define SROM_CLK_WRITE(data, ioaddr)
Definition: dmfe.c:128
static unsigned long ioaddr
Definition: davicom.c:129
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
#define SROM_DATA_1
Definition: dmfe.c:119
#define outl(data, io_addr)
Definition: io.h:329
#define CR9_CRDOUT
Definition: dmfe.c:117
#define CR9_SRCS
Definition: dmfe.c:115
#define CR9_SROM_READ
Definition: dmfe.c:114
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
#define SROM_DATA_0
Definition: dmfe.c:118

References CR9_CRDOUT, CR9_SRCLK, CR9_SRCS, CR9_SROM_READ, DCR9, inl(), ioaddr, offset, outl, SROM_CLK_WRITE, SROM_DATA_0, SROM_DATA_1, and udelay().

Referenced by dmfe_probe().

◆ dmfe_init_dm910x()

static void dmfe_init_dm910x ( struct nic nic)
static

Definition at line 277 of file dmfe.c.

278 {
279  unsigned long ioaddr = BASE;
280 
281  /* Reset DM910x MAC controller */
282  outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
283  udelay(100);
284  outl(db->cr0_data, ioaddr + DCR0);
285  udelay(5);
286 
287  /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
288  db->phy_addr = 1;
289 
290  /* Parser SROM and media mode */
293 
294  /* RESET Phyxcer Chip by GPR port bit 7 */
295  outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
296  if (db->chip_id == PCI_DM9009_ID) {
297  outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
298  mdelay(300); /* Delay 300 ms */
299  }
300  outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
301 
302  /* Process Phyxcer Media Mode */
303  if (!(db->media_mode & 0x10)) /* Force 1M mode */
305 
306  /* Media Mode Process */
307  if (!(db->media_mode & DMFE_AUTO))
308  db->op_mode = db->media_mode; /* Force Mode */
309 
310  /* Initiliaze Transmit/Receive descriptor and CR3/4 */
312 
313  /* tx descriptor start pointer */
314  outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
315 
316  /* rx descriptor start pointer */
317  outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
318 
319  /* Init CR6 to program DM910x operation */
321 
322  /* Send setup frame */
323  if (db->chip_id == PCI_DM9132_ID) {
324  dm9132_id_table(nic); /* DM9132 */
325  } else {
326  send_filter_frame(nic); /* DM9102/DM9102A */
327  }
328 
329  /* Init CR7, interrupt active bit */
331  outl(db->cr7_data, ioaddr + DCR7);
332  /* Init CR15, Tx jabber and Rx watchdog timer */
334  /* Enable DM910X Tx/Rx function */
335  db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
337 }
u8 op_mode
Definition: dmfe.c:166
static unsigned char dmfe_media_mode
Definition: dmfe.c:196
#define virt_to_le32desc(addr)
Definition: dmfe.c:58
u32 cr6_data
Definition: dmfe.c:154
Definition: dmfe.c:188
Definition: dmfe.c:189
Definition: dmfe.c:180
static void dmfe_parse_srom(struct nic *nic)
Definition: dmfe.c:1025
u32 chip_id
Definition: dmfe.c:150
#define rxd
Definition: dmfe.c:222
Definition: dmfe.c:181
static void dm9132_id_table(struct nic *nic)
u32 cr15_data
Definition: dmfe.c:156
static unsigned long ioaddr
Definition: davicom.c:129
Definition: dmfe.c:184
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define txd
Definition: dmfe.c:220
static void send_filter_frame(struct nic *nic)
Definition: dmfe.c:629
Definition: dmfe.c:180
#define DM910X_RESET
Definition: dmfe.c:77
#define outl(data, io_addr)
Definition: io.h:329
#define CR7_DEFAULT
Definition: dmfe.c:80
#define DMFE_AUTO
Definition: dmfe.c:94
u8 media_mode
Definition: dmfe.c:165
Definition: nic.h:49
#define PCI_DM9009_ID
Definition: dmfe.c:65
static struct dmfe_private * db
Definition: dmfe.c:177
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Definition: dmfe.c:182
u32 cr0_data
Definition: dmfe.c:152
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:561
u32 cr7_data
Definition: dmfe.c:155
Definition: dmfe.c:180
static void dmfe_descriptor_init(struct nic *, unsigned long ioaddr)
static long int BASE
Definition: dmfe.c:226
u8 phy_addr
Definition: dmfe.c:167
#define PCI_DM9132_ID
Definition: dmfe.c:62
static void dmfe_set_phyxcer(struct nic *nic)

References BASE, dmfe_private::chip_id, dmfe_private::cr0_data, dmfe_private::cr15_data, dmfe_private::cr6_data, CR6_RXSC, CR6_TXSC, dmfe_private::cr7_data, CR7_DEFAULT, db, DCR0, DCR12, DCR15, DCR3, DCR4, DCR7, DM910X_RESET, dm9132_id_table(), DMFE_AUTO, dmfe_descriptor_init(), dmfe_media_mode, dmfe_parse_srom(), dmfe_set_phyxcer(), ioaddr, mdelay(), dmfe_private::media_mode, dmfe_private::op_mode, outl, PCI_DM9009_ID, PCI_DM9132_ID, dmfe_private::phy_addr, rxd, send_filter_frame(), txd, udelay(), update_cr6(), and virt_to_le32desc.

Referenced by dmfe_reset().

◆ dmfe_descriptor_init() [1/2]

static void dmfe_descriptor_init ( struct nic ,
unsigned long  ioaddr 
)
static

Referenced by dmfe_init_dm910x().

◆ update_cr6()

static void update_cr6 ( u32  cr6_data,
unsigned long  ioaddr 
)
static

Definition at line 561 of file dmfe.c.

562 {
563  u32 cr6_tmp;
564 
565  cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
566  outl(cr6_tmp, ioaddr + DCR6);
567  udelay(5);
568  outl(cr6_data, ioaddr + DCR6);
569  udelay(5);
570 }
static unsigned long ioaddr
Definition: davicom.c:129
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define outl(data, io_addr)
Definition: io.h:329
Definition: dmfe.c:181
uint32_t u32
Definition: stdint.h:23

References DCR6, ioaddr, outl, and udelay().

Referenced by dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_set_phyxcer(), and send_filter_frame().

◆ send_filter_frame()

static void send_filter_frame ( struct nic nic)
static

Definition at line 629 of file dmfe.c.

630 {
631 
632  u8 *ptxb;
633  int i;
634 
635  dprintf(("send_filter_frame\n"));
636  /* point to the current txb incase multiple tx_rings are used */
637  ptxb = &txb[db->cur_tx];
638 
639  /* construct perfect filter frame with mac address as first match
640  and broadcast address for all others */
641  for (i = 0; i < 192; i++)
642  ptxb[i] = 0xFF;
643  ptxb[0] = nic->node_addr[0];
644  ptxb[1] = nic->node_addr[1];
645  ptxb[4] = nic->node_addr[2];
646  ptxb[5] = nic->node_addr[3];
647  ptxb[8] = nic->node_addr[4];
648  ptxb[9] = nic->node_addr[5];
649 
650  /* prepare the setup frame */
651  txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0);
652  txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);
653  update_cr6(db->cr6_data | 0x2000, BASE);
654  outl(0x1, BASE + DCR1); /* Issue Tx polling */
656  db->cur_tx++;
657 }
u32 cr6_data
Definition: dmfe.c:154
u8 cur_tx
Definition: dmfe.c:173
Definition: dmfe.c:180
#define txd
Definition: dmfe.c:220
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define outl(data, io_addr)
Definition: io.h:329
#define dprintf(x)
Definition: dmfe.c:54
Definition: nic.h:49
static struct dmfe_private * db
Definition: dmfe.c:177
unsigned char * node_addr
Definition: nic.h:52
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:561
#define txb
Definition: dmfe.c:221
uint8_t u8
Definition: stdint.h:19
static long int BASE
Definition: dmfe.c:226

References BASE, cpu_to_le32, dmfe_private::cr6_data, dmfe_private::cur_tx, db, DCR1, dprintf, nic::node_addr, outl, txb, txd, and update_cr6().

Referenced by dmfe_init_dm910x().

◆ dm9132_id_table() [1/2]

static void dm9132_id_table ( struct nic nic)
static

Referenced by dmfe_init_dm910x().

◆ phy_read()

static u16 phy_read ( unsigned long  iobase,
u8  phy_addr,
u8  offset,
u32  chip_id 
)
static

Definition at line 935 of file dmfe.c.

937 {
938  int i;
939  u16 phy_data;
940  unsigned long ioaddr;
941 
942  if (chip_id == PCI_DM9132_ID) {
943  /* DM9132 Chip */
944  ioaddr = iobase + 0x80 + offset * 4;
945  phy_data = inw(ioaddr);
946  } else {
947  /* DM9102/DM9102A Chip */
948  ioaddr = iobase + DCR9;
949 
950  /* Send 33 synchronization clock to Phy controller */
951  for (i = 0; i < 35; i++)
953 
954  /* Send start command(01) to Phy */
957 
958  /* Send read command(10) to Phy */
961 
962  /* Send Phy address */
963  for (i = 0x10; i > 0; i = i >> 1)
965  phy_addr & i ? PHY_DATA_1 :
966  PHY_DATA_0);
967 
968  /* Send register address */
969  for (i = 0x10; i > 0; i = i >> 1)
971  offset & i ? PHY_DATA_1 :
972  PHY_DATA_0);
973 
974  /* Skip transition state */
976 
977  /* read 16bit data */
978  for (phy_data = 0, i = 0; i < 16; i++) {
979  phy_data <<= 1;
980  phy_data |= phy_read_1bit(ioaddr);
981  }
982  }
983 
984  return phy_data;
985 }
static void phy_write_1bit(unsigned long, u32)
Definition: dmfe.c:992
uint16_t u16
Definition: stdint.h:21
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
Definition: dmfe.c:181
#define PHY_DATA_0
Definition: dmfe.c:121
#define PHY_DATA_1
Definition: dmfe.c:120
static unsigned long ioaddr
Definition: davicom.c:129
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
static u16 phy_read_1bit(unsigned long)
Definition: dmfe.c:1007
#define PCI_DM9132_ID
Definition: dmfe.c:62

References DCR9, inw(), ioaddr, offset, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, phy_read_1bit(), and phy_write_1bit().

Referenced by dmfe_parse_srom(), dmfe_program_DM9801(), dmfe_program_DM9802(), and dmfe_set_phyxcer().

◆ phy_write()

static void phy_write ( unsigned long  iobase,
u8  phy_addr,
u8  offset,
u16  phy_data,
u32  chip_id 
)
static

Definition at line 881 of file dmfe.c.

883 {
884  u16 i;
885  unsigned long ioaddr;
886 
887  if (chip_id == PCI_DM9132_ID) {
888  ioaddr = iobase + 0x80 + offset * 4;
889  outw(phy_data, ioaddr);
890  } else {
891  /* DM9102/DM9102A Chip */
892  ioaddr = iobase + DCR9;
893 
894  /* Send 33 synchronization clock to Phy controller */
895  for (i = 0; i < 35; i++)
897 
898  /* Send start command(01) to Phy */
901 
902  /* Send write command(01) to Phy */
905 
906  /* Send Phy address */
907  for (i = 0x10; i > 0; i = i >> 1)
909  phy_addr & i ? PHY_DATA_1 :
910  PHY_DATA_0);
911 
912  /* Send register address */
913  for (i = 0x10; i > 0; i = i >> 1)
915  offset & i ? PHY_DATA_1 :
916  PHY_DATA_0);
917 
918  /* written trasnition */
921 
922  /* Write a word data to PHY controller */
923  for (i = 0x8000; i > 0; i >>= 1)
925  phy_data & i ? PHY_DATA_1 :
926  PHY_DATA_0);
927  }
928 }
static void phy_write_1bit(unsigned long, u32)
Definition: dmfe.c:992
uint16_t u16
Definition: stdint.h:21
#define outw(data, io_addr)
Definition: io.h:319
Definition: dmfe.c:181
#define PHY_DATA_0
Definition: dmfe.c:121
#define PHY_DATA_1
Definition: dmfe.c:120
static unsigned long ioaddr
Definition: davicom.c:129
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
#define PCI_DM9132_ID
Definition: dmfe.c:62

References DCR9, ioaddr, offset, outw, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, and phy_write_1bit().

Referenced by dmfe_disable(), dmfe_program_DM9801(), dmfe_program_DM9802(), and dmfe_set_phyxcer().

◆ phy_write_1bit()

static void phy_write_1bit ( unsigned long  ioaddr,
u32  phy_data 
)
static

Definition at line 992 of file dmfe.c.

993 {
994  outl(phy_data, ioaddr); /* MII Clock Low */
995  udelay(1);
996  outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
997  udelay(1);
998  outl(phy_data, ioaddr); /* MII Clock Low */
999  udelay(1);
1000 }
static unsigned long ioaddr
Definition: davicom.c:129
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define outl(data, io_addr)
Definition: io.h:329
#define MDCLKH
Definition: dmfe.c:122

References ioaddr, MDCLKH, outl, and udelay().

Referenced by phy_read(), and phy_write().

◆ phy_read_1bit()

static u16 phy_read_1bit ( unsigned long  ioaddr)
static

Definition at line 1007 of file dmfe.c.

1008 {
1009  u16 phy_data;
1010 
1011  outl(0x50000, ioaddr);
1012  udelay(1);
1013  phy_data = (inl(ioaddr) >> 19) & 0x1;
1014  outl(0x40000, ioaddr);
1015  udelay(1);
1016 
1017  return phy_data;
1018 }
uint16_t u16
Definition: stdint.h:21
static unsigned long ioaddr
Definition: davicom.c:129
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define outl(data, io_addr)
Definition: io.h:329
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.

References inl(), ioaddr, outl, and udelay().

Referenced by phy_read().

◆ dmfe_set_phyxcer() [1/2]

static void dmfe_set_phyxcer ( struct nic nic)
static

Referenced by dmfe_init_dm910x().

◆ dmfe_parse_srom()

static void dmfe_parse_srom ( struct nic nic)
static

Definition at line 1025 of file dmfe.c.

1026 {
1027  unsigned char *srom = db->srom;
1028  int dmfe_mode, tmp_reg;
1029 
1030  /* Init CR15 */
1032 
1033  /* Check SROM Version */
1034  if (((int) srom[18] & 0xff) == SROM_V41_CODE) {
1035  /* SROM V4.01 */
1036  /* Get NIC support media mode */
1037  db->NIC_capability = *(u16 *) (srom + 34);
1038  db->PHY_reg4 = 0;
1039  for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1040  switch (db->NIC_capability & tmp_reg) {
1041  case 0x1:
1042  db->PHY_reg4 |= 0x0020;
1043  break;
1044  case 0x2:
1045  db->PHY_reg4 |= 0x0040;
1046  break;
1047  case 0x4:
1048  db->PHY_reg4 |= 0x0080;
1049  break;
1050  case 0x8:
1051  db->PHY_reg4 |= 0x0100;
1052  break;
1053  }
1054  }
1055 
1056  /* Media Mode Force or not check */
1057  dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36);
1058  switch (dmfe_mode) {
1059  case 0x4:
1061  break; /* 100MHF */
1062  case 0x2:
1064  break; /* 10MFD */
1065  case 0x8:
1067  break; /* 100MFD */
1068  case 0x100:
1069  case 0x200:
1071  break; /* HomePNA */
1072  }
1073 
1074  /* Special Function setting */
1075  /* VLAN function */
1076  if ((SF_mode & 0x1) || (srom[43] & 0x80))
1077  db->cr15_data |= 0x40;
1078 
1079  /* Flow Control */
1080  if ((SF_mode & 0x2) || (srom[40] & 0x1))
1081  db->cr15_data |= 0x400;
1082 
1083  /* TX pause packet */
1084  if ((SF_mode & 0x4) || (srom[40] & 0xe))
1085  db->cr15_data |= 0x9800;
1086  }
1087 
1088  /* Parse HPNA parameter */
1089  db->HPNA_command = 1;
1090 
1091  /* Accept remote command or not */
1092  if (HPNA_rx_cmd == 0)
1093  db->HPNA_command |= 0x8000;
1094 
1095  /* Issue remote command & operation mode */
1096  if (HPNA_tx_cmd == 1)
1097  switch (HPNA_mode) { /* Issue Remote Command */
1098  case 0:
1099  db->HPNA_command |= 0x0904;
1100  break;
1101  case 1:
1102  db->HPNA_command |= 0x0a00;
1103  break;
1104  case 2:
1105  db->HPNA_command |= 0x0506;
1106  break;
1107  case 3:
1108  db->HPNA_command |= 0x0602;
1109  break;
1110  } else
1111  switch (HPNA_mode) { /* Don't Issue */
1112  case 0:
1113  db->HPNA_command |= 0x0004;
1114  break;
1115  case 1:
1116  db->HPNA_command |= 0x0000;
1117  break;
1118  case 2:
1119  db->HPNA_command |= 0x0006;
1120  break;
1121  case 3:
1122  db->HPNA_command |= 0x0002;
1123  break;
1124  }
1125 
1126  /* Check DM9801 or DM9802 present or not */
1127  db->HPNA_present = 0;
1128  update_cr6(db->cr6_data | 0x40000, BASE);
1129  tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id);
1130  if ((tmp_reg & 0xfff0) == 0xb900) {
1131  /* DM9801 or DM9802 present */
1132  db->HPNA_timer = 8;
1133  if (phy_read(BASE, db->phy_addr, 31, db->chip_id) ==
1134  0x4404) {
1135  /* DM9801 HomeRun */
1136  db->HPNA_present = 1;
1137  dmfe_program_DM9801(nic, tmp_reg);
1138  } else {
1139  /* DM9802 LongRun */
1140  db->HPNA_present = 2;
1142  }
1143  }
1144 
1145 }
uint16_t u16
Definition: stdint.h:21
#define DMFE_1M_HPNA
Definition: dmfe.c:95
static unsigned char dmfe_media_mode
Definition: dmfe.c:196
u32 cr6_data
Definition: dmfe.c:154
#define DMFE_100MFD
Definition: dmfe.c:93
static u8 HPNA_rx_cmd
Definition: dmfe.c:202
u8 HPNA_present
Definition: dmfe.c:163
u32 chip_id
Definition: dmfe.c:150
unsigned char srom[128]
Definition: dmfe.c:171
u16 NIC_capability
Definition: dmfe.c:160
static u8 HPNA_tx_cmd
Definition: dmfe.c:203
u32 cr15_data
Definition: dmfe.c:156
static u8 HPNA_mode
Definition: dmfe.c:201
#define SROM_V41_CODE
Definition: dmfe.c:126
#define DMFE_10MFD
Definition: dmfe.c:92
Definition: nic.h:49
static struct dmfe_private * db
Definition: dmfe.c:177
static u8 SF_mode
Definition: dmfe.c:205
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:561
u16 HPNA_timer
Definition: dmfe.c:159
static void dmfe_program_DM9802(struct nic *nic)
#define DMFE_100MHF
Definition: dmfe.c:91
#define CR15_DEFAULT
Definition: dmfe.c:81
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:935
u16 HPNA_command
Definition: dmfe.c:158
static long int BASE
Definition: dmfe.c:226
u8 phy_addr
Definition: dmfe.c:167
static void dmfe_program_DM9801(struct nic *nic, int)
u16 PHY_reg4
Definition: dmfe.c:161

References BASE, dmfe_private::chip_id, dmfe_private::cr15_data, CR15_DEFAULT, dmfe_private::cr6_data, db, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_1M_HPNA, dmfe_media_mode, dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_private::HPNA_command, HPNA_mode, dmfe_private::HPNA_present, HPNA_rx_cmd, dmfe_private::HPNA_timer, HPNA_tx_cmd, dmfe_private::NIC_capability, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, SF_mode, dmfe_private::srom, SROM_V41_CODE, and update_cr6().

Referenced by dmfe_init_dm910x().

◆ dmfe_program_DM9801() [1/2]

static void dmfe_program_DM9801 ( struct nic nic,
int   
)
static

Referenced by dmfe_parse_srom().

◆ dmfe_program_DM9802() [1/2]

static void dmfe_program_DM9802 ( struct nic nic)
static

Referenced by dmfe_parse_srom().

◆ dmfe_reset()

static void dmfe_reset ( struct nic nic)
static

Definition at line 245 of file dmfe.c.

246 {
247  /* system variable init */
249 
250  db->NIC_capability = 0xf; /* All capability */
251  db->PHY_reg4 = 0x1e0;
252 
253  /* CR6 operation mode decision */
254  if (!chkmode || (db->chip_id == PCI_DM9132_ID) ||
255  (db->chip_revision >= 0x02000030)) {
258  db->dm910x_chk_mode = 4; /* Enter the normal mode */
259  } else {
260  db->cr6_data |= CR6_SFT; /* Store & Forward mode */
261  db->cr0_data = 0;
262  db->dm910x_chk_mode = 1; /* Enter the check mode */
263  }
264  /* Initialize DM910X board */
266 
267  return;
268 }
u32 cr6_data
Definition: dmfe.c:154
u32 chip_id
Definition: dmfe.c:150
u16 NIC_capability
Definition: dmfe.c:160
u32 chip_revision
Definition: dmfe.c:151
static u8 chkmode
Definition: dmfe.c:200
#define DMFE_TXTH_256
Definition: dmfe.c:100
u8 dm910x_chk_mode
Definition: dmfe.c:168
#define CR6_DEFAULT
Definition: dmfe.c:79
static u32 dmfe_cr6_user_set
Definition: dmfe.c:197
Definition: nic.h:49
Definition: dmfe.c:190
#define CR0_DEFAULT
Definition: dmfe.c:78
static struct dmfe_private * db
Definition: dmfe.c:177
static void dmfe_init_dm910x(struct nic *nic)
Definition: dmfe.c:277
u32 cr0_data
Definition: dmfe.c:152
#define PCI_DM9132_ID
Definition: dmfe.c:62
u16 PHY_reg4
Definition: dmfe.c:161

References dmfe_private::chip_id, dmfe_private::chip_revision, chkmode, dmfe_private::cr0_data, CR0_DEFAULT, dmfe_private::cr6_data, CR6_DEFAULT, CR6_SFT, db, dmfe_private::dm910x_chk_mode, dmfe_cr6_user_set, dmfe_init_dm910x(), DMFE_TXTH_256, dmfe_private::NIC_capability, PCI_DM9132_ID, and dmfe_private::PHY_reg4.

Referenced by dmfe_probe().

◆ dmfe_poll()

static int dmfe_poll ( struct nic nic,
int  retrieve 
)
static

Definition at line 344 of file dmfe.c.

345 {
346  u32 rdes0;
347  int entry = db->cur_rx % RX_DESC_CNT;
348  int rxlen;
349  rdes0 = le32_to_cpu(rxd[entry].rdes0);
350  if (rdes0 & 0x80000000)
351  return 0;
352 
353  if (!retrieve)
354  return 1;
355 
356  if ((rdes0 & 0x300) != 0x300) {
357  /* A packet without First/Last flag */
358  printf("strange Packet\n");
359  rxd[entry].rdes0 = cpu_to_le32(0x80000000);
360  return 0;
361  } else {
362  /* A packet with First/Last flag */
363  rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
364  /* error summary bit check */
365  if (rdes0 & 0x8000) {
366  printf("Error\n");
367  return 0;
368  }
369  if (!(rdes0 & 0x8000) ||
370  ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
371  if (db->dm910x_chk_mode & 1)
372  printf("Silly check mode\n");
373 
374  nic->packetlen = rxlen;
376  nic->packetlen);
377  }
378  }
379  rxd[entry].rdes0 = cpu_to_le32(0x80000000);
380  db->cur_rx++;
381  return 1;
382 }
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
Definition: sis900.h:35
#define le32_to_cpu(value)
Definition: byteswap.h:113
u32 cr6_data
Definition: dmfe.c:154
u8 cur_rx
Definition: dmfe.c:174
#define rxb
Definition: dmfe.c:223
#define rxd
Definition: dmfe.c:222
#define RX_ALLOC_SIZE
Definition: dmfe.c:76
void * memcpy(void *dest, const void *src, size_t len) __nonnull
u8 dm910x_chk_mode
Definition: dmfe.c:168
#define cpu_to_le32(value)
Definition: byteswap.h:107
unsigned int packetlen
Definition: nic.h:54
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
#define RX_DESC_CNT
Definition: dmfe.c:71
Definition: nic.h:49
static struct dmfe_private * db
Definition: dmfe.c:177
unsigned char * packet
Definition: nic.h:53
Definition: dmfe.c:188
uint32_t u32
Definition: stdint.h:23

References cpu_to_le32, dmfe_private::cr6_data, CR6_PM, dmfe_private::cur_rx, db, dmfe_private::dm910x_chk_mode, entry, le32_to_cpu, memcpy(), nic::packet, nic::packetlen, printf(), rx_desc::rdes0, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, and rxlen.

◆ dmfe_irq()

static void dmfe_irq ( struct nic *nic  __unused,
irq_action_t action  __unused 
)
static

Definition at line 384 of file dmfe.c.

385 {
386  switch ( action ) {
387  case DISABLE :
388  break;
389  case ENABLE :
390  break;
391  case FORCE :
392  break;
393  }
394 }
Definition: nic.h:35
Definition: nic.h:37
Definition: nic.h:36

References DISABLE, ENABLE, and FORCE.

◆ dmfe_transmit()

static void dmfe_transmit ( struct nic nic,
const char *  dest,
unsigned int  type,
unsigned int  size,
const char *  packet 
)
static

Definition at line 399 of file dmfe.c.

404 {
405  u16 nstype;
406  u8 *ptxb;
407 
408  ptxb = &txb[db->cur_tx];
409 
410  /* Stop Tx */
411  outl(0, BASE + DCR7);
412  memcpy(ptxb, dest, ETH_ALEN);
413  memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
414  nstype = htons((u16) type);
415  memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
416  memcpy(ptxb + ETH_HLEN, packet, size);
417 
418  size += ETH_HLEN;
419  while (size < ETH_ZLEN)
420  ptxb[size++] = '\0';
421 
422  /* setup the transmit descriptor */
423  txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size);
424  txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000); /* give ownership to device */
425 
426  /* immediate transmit demand */
427  outl(0x1, BASE + DCR1);
428  outl(db->cr7_data, BASE + DCR7);
429 
430  /* Point to next TX descriptor */
431  db->cur_tx++;
432  db->cur_tx = db->cur_tx % TX_DESC_CNT;
433 }
uint16_t u16
Definition: stdint.h:21
u8 cur_tx
Definition: dmfe.c:173
#define TX_DESC_CNT
Definition: dmfe.c:70
uint8_t type
Type.
Definition: ena.h:16
Definition: dmfe.c:181
Definition: dmfe.c:180
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define ETH_HLEN
Definition: if_ether.h:9
#define txd
Definition: dmfe.c:220
static void * dest
Definition: strings.h:176
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define outl(data, io_addr)
Definition: io.h:329
#define ETH_ALEN
Definition: if_ether.h:8
#define ETH_ZLEN
Definition: if_ether.h:10
Definition: nic.h:49
static struct dmfe_private * db
Definition: dmfe.c:177
unsigned char * node_addr
Definition: nic.h:52
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
u32 cr7_data
Definition: dmfe.c:155
#define txb
Definition: dmfe.c:221
#define htons(value)
Definition: byteswap.h:135
uint8_t u8
Definition: stdint.h:19
static long int BASE
Definition: dmfe.c:226

References BASE, cpu_to_le32, dmfe_private::cr7_data, dmfe_private::cur_tx, db, DCR1, DCR7, dest, ETH_ALEN, ETH_HLEN, ETH_ZLEN, htons, memcpy(), nic::node_addr, outl, size, TX_DESC_CNT, txb, txd, and type.

◆ dmfe_disable()

static void dmfe_disable ( struct nic *nic  __unused)
static

Definition at line 438 of file dmfe.c.

438  {
439  /* Reset & stop DM910X board */
441  udelay(5);
442  phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
443 
444 }
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:881
u32 chip_id
Definition: dmfe.c:150
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define DM910X_RESET
Definition: dmfe.c:77
#define outl(data, io_addr)
Definition: io.h:329
static struct dmfe_private * db
Definition: dmfe.c:177
Definition: dmfe.c:180
static long int BASE
Definition: dmfe.c:226
u8 phy_addr
Definition: dmfe.c:167

References BASE, dmfe_private::chip_id, db, DCR0, DM910X_RESET, outl, dmfe_private::phy_addr, phy_write(), and udelay().

◆ dmfe_probe()

static int dmfe_probe ( struct nic nic,
struct pci_device pci 
)
static

Definition at line 452 of file dmfe.c.

452  {
453 
454  uint32_t dev_rev, pci_pmr;
455  int i;
456 
457  if (pci->ioaddr == 0)
458  return 0;
459 
460  BASE = pci->ioaddr;
461  printf("dmfe.c: Found %s Vendor=0x%hX Device=0x%hX\n",
462  pci->id->name, pci->vendor, pci->device);
463 
464  /* Read Chip revision */
465  pci_read_config_dword(pci, PCI_REVISION, &dev_rev);
466  dprintf(("Revision %lX\n", dev_rev));
467 
468  /* point to private storage */
469  db = &dfx;
470 
471  db->chip_id = ((u32) pci->device << 16) | pci->vendor;
473  db->chip_revision = dev_rev;
474 
475  pci_read_config_dword(pci, 0x50, &pci_pmr);
476  pci_pmr &= 0x70000;
477  if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031))
478  db->chip_type = 1; /* DM9102A E3 */
479  else
480  db->chip_type = 0;
481 
482  dprintf(("Chip type : %d\n", db->chip_type));
483 
484  /* read 64 word srom data */
485  for (i = 0; i < 64; i++)
486  ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i));
487 
488  /* Set Node address */
489  for (i = 0; i < 6; i++)
490  nic->node_addr[i] = db->srom[20 + i];
491 
492  /* Print out some hardware info */
493  DBG ( "%s: %s at ioaddr %4.4lx\n",
494  pci->id->name, eth_ntoa ( nic->node_addr ), BASE );
495 
496  /* Set the card as PCI Bus Master */
497  adjust_pci_device(pci);
498 
499  dmfe_reset(nic);
500 
501  nic->irqno = 0;
502  nic->ioaddr = pci->ioaddr;
503 
504  /* point to NIC specific routines */
506 
507  return 1;
508 }
unsigned char irqno
Definition: nic.h:56
uint16_t u16
Definition: stdint.h:21
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
unsigned long ioaddr
I/O address.
Definition: pci.h:200
#define PCI_BASE_ADDRESS_0
Definition: pci.h:61
u32 chip_id
Definition: dmfe.c:150
unsigned char srom[128]
Definition: dmfe.c:171
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
unsigned int ioaddr
Definition: nic.h:55
u32 chip_revision
Definition: dmfe.c:151
uint16_t device
Device ID.
Definition: pci.h:204
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
#define u32
Definition: vga.h:21
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
static struct dmfe_private dfx
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
#define dprintf(x)
Definition: dmfe.c:54
Definition: nic.h:49
unsigned int uint32_t
Definition: stdint.h:12
const char * name
Name.
Definition: pci.h:153
uint16_t vendor
Vendor ID.
Definition: pci.h:202
static void dmfe_reset(struct nic *nic)
Definition: dmfe.c:245
u8 chip_type
Definition: dmfe.c:164
static struct dmfe_private * db
Definition: dmfe.c:177
unsigned char * node_addr
Definition: nic.h:52
static struct nic_operations dmfe_operations
Definition: dmfe.c:194
struct pci_device_id * id
Driver device ID.
Definition: pci.h:220
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define PCI_REVISION
PCI revision.
Definition: pci.h:43
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
static long int BASE
Definition: dmfe.c:226
static u16 read_srom_word(long ioaddr, int offset)
Definition: dmfe.c:663

References adjust_pci_device(), BASE, dmfe_private::chip_id, dmfe_private::chip_revision, dmfe_private::chip_type, cpu_to_le16, db, DBG, pci_device::device, dfx, dmfe_operations, dmfe_reset(), dprintf, eth_ntoa(), pci_device::id, nic::ioaddr, pci_device::ioaddr, nic::irqno, pci_device_id::name, nic::nic_op, nic::node_addr, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_read_config_dword(), PCI_REVISION, printf(), read_srom_word(), dmfe_private::srom, u32, and pci_device::vendor.

◆ dmfe_descriptor_init() [2/2]

static void dmfe_descriptor_init ( struct nic *nic  __unused,
unsigned long  ioaddr 
)
static

Definition at line 515 of file dmfe.c.

516 {
517  int i;
518  db->cur_tx = 0;
519  db->cur_rx = 0;
520 
521  /* tx descriptor start pointer */
522  outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
523 
524  /* rx descriptor start pointer */
525  outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
526 
527  /* Init Transmit chain */
528  for (i = 0; i < TX_DESC_CNT; i++) {
529  txd[i].tx_buf_ptr = &txb[i];
530  txd[i].tdes0 = cpu_to_le32(0);
531  txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
532  txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
533  txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
534  txd[i].next_tx_desc = &txd[i + 1];
535  }
536  /* Mark the last entry as wrapping the ring */
537  txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
538  txd[i - 1].next_tx_desc = &txd[0];
539 
540  /* receive descriptor chain */
541  for (i = 0; i < RX_DESC_CNT; i++) {
542  rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
543  rxd[i].rdes0 = cpu_to_le32(0x80000000);
544  rxd[i].rdes1 = cpu_to_le32(0x01000600);
545  rxd[i].rdes2 =
547  rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
548  rxd[i].next_rx_desc = &rxd[i + 1];
549  }
550  /* Mark the last entry as wrapping the ring */
551  rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
552  rxd[i - 1].next_rx_desc = &rxd[0];
553 
554 }
#define virt_to_le32desc(addr)
Definition: dmfe.c:58
u8 cur_rx
Definition: dmfe.c:174
u8 cur_tx
Definition: dmfe.c:173
#define TX_DESC_CNT
Definition: dmfe.c:70
#define rxb
Definition: dmfe.c:223
Definition: dmfe.c:180
#define rxd
Definition: dmfe.c:222
#define RX_ALLOC_SIZE
Definition: dmfe.c:76
static unsigned long ioaddr
Definition: davicom.c:129
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define txd
Definition: dmfe.c:220
Definition: dmfe.c:180
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define RX_DESC_CNT
Definition: dmfe.c:71
#define outl(data, io_addr)
Definition: io.h:329
static struct dmfe_private * db
Definition: dmfe.c:177
#define txb
Definition: dmfe.c:221

References cpu_to_le32, dmfe_private::cur_rx, dmfe_private::cur_tx, db, DCR3, DCR4, ioaddr, outl, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, TX_DESC_CNT, txb, txd, virt_to_bus(), and virt_to_le32desc.

◆ dm9132_id_table() [2/2]

static void dm9132_id_table ( struct nic *nic  __unused)
static

Definition at line 578 of file dmfe.c.

579 {
580 #ifdef LINUX
581  u16 *addrptr;
582  u8 dmi_addr[8];
583  unsigned long ioaddr = BASE + 0xc0; /* ID Table */
584  u32 hash_val;
585  u16 i, hash_table[4];
586 #endif
587  dprintf(("dm9132_id_table\n"));
588 
589  printf("FIXME: This function is broken. If you have this card contact "
590  "Timothy Legge at the etherboot-user list\n");
591 
592 #ifdef LINUX
593  //DMFE_DBUG(0, "dm9132_id_table()", 0);
594 
595  /* Node address */
596  addrptr = (u16 *) nic->node_addr;
597  outw(addrptr[0], ioaddr);
598  ioaddr += 4;
599  outw(addrptr[1], ioaddr);
600  ioaddr += 4;
601  outw(addrptr[2], ioaddr);
602  ioaddr += 4;
603 
604  /* Clear Hash Table */
605  for (i = 0; i < 4; i++)
606  hash_table[i] = 0x0;
607 
608  /* broadcast address */
609  hash_table[3] = 0x8000;
610 
611  /* the multicast address in Hash Table : 64 bits */
612  for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
613  hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
614  hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
615  }
616 
617  /* Write the hash table to MAC MD table */
618  for (i = 0; i < 4; i++, ioaddr += 4)
619  outw(hash_table[i], ioaddr);
620 #endif
621 }
#define u16
Definition: vga.h:20
uint16_t u16
Definition: stdint.h:21
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
#define outw(data, io_addr)
Definition: io.h:319
static unsigned long ioaddr
Definition: davicom.c:129
#define dprintf(x)
Definition: dmfe.c:54
Definition: nic.h:49
unsigned char * node_addr
Definition: nic.h:52
uint8_t u8
Definition: stdint.h:19
static long int BASE
Definition: dmfe.c:226
uint32_t u32
Definition: stdint.h:23

References BASE, dprintf, ioaddr, nic::node_addr, outw, printf(), and u16.

◆ dmfe_set_phyxcer() [2/2]

static void dmfe_set_phyxcer ( struct nic *nic  __unused)
static

Definition at line 761 of file dmfe.c.

762 {
763  u16 phy_reg;
764 
765  /* Select 10/100M phyxcer */
766  db->cr6_data &= ~0x40000;
768 
769  /* DM9009 Chip: Phyxcer reg18 bit12=0 */
770  if (db->chip_id == PCI_DM9009_ID) {
771  phy_reg =
772  phy_read(BASE, db->phy_addr, 18,
773  db->chip_id) & ~0x1000;
774  phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id);
775  }
776 
777  /* Phyxcer capability setting */
778  phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0;
779 
780  if (db->media_mode & DMFE_AUTO) {
781  /* AUTO Mode */
782  phy_reg |= db->PHY_reg4;
783  } else {
784  /* Force Mode */
785  switch (db->media_mode) {
786  case DMFE_10MHF:
787  phy_reg |= 0x20;
788  break;
789  case DMFE_10MFD:
790  phy_reg |= 0x40;
791  break;
792  case DMFE_100MHF:
793  phy_reg |= 0x80;
794  break;
795  case DMFE_100MFD:
796  phy_reg |= 0x100;
797  break;
798  }
799  if (db->chip_id == PCI_DM9009_ID)
800  phy_reg &= 0x61;
801  }
802 
803  /* Write new capability to Phyxcer Reg4 */
804  if (!(phy_reg & 0x01e0)) {
805  phy_reg |= db->PHY_reg4;
806  db->media_mode |= DMFE_AUTO;
807  }
808  phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id);
809 
810  /* Restart Auto-Negotiation */
811  if (db->chip_type && (db->chip_id == PCI_DM9102_ID))
812  phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id);
813  if (!db->chip_type)
814  phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id);
815 }
uint16_t u16
Definition: stdint.h:21
u32 cr6_data
Definition: dmfe.c:154
#define DMFE_100MFD
Definition: dmfe.c:93
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:881
u32 chip_id
Definition: dmfe.c:150
#define DMFE_10MFD
Definition: dmfe.c:92
#define DMFE_AUTO
Definition: dmfe.c:94
#define DMFE_10MHF
Definition: dmfe.c:90
#define PCI_DM9102_ID
Definition: dmfe.c:63
u8 media_mode
Definition: dmfe.c:165
#define PCI_DM9009_ID
Definition: dmfe.c:65
u8 chip_type
Definition: dmfe.c:164
static struct dmfe_private * db
Definition: dmfe.c:177
static void update_cr6(u32, unsigned long)
Definition: dmfe.c:561
#define DMFE_100MHF
Definition: dmfe.c:91
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:935
static long int BASE
Definition: dmfe.c:226
u8 phy_addr
Definition: dmfe.c:167
u16 PHY_reg4
Definition: dmfe.c:161

References BASE, dmfe_private::chip_id, dmfe_private::chip_type, dmfe_private::cr6_data, db, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_10MHF, DMFE_AUTO, dmfe_private::media_mode, PCI_DM9009_ID, PCI_DM9102_ID, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, phy_write(), and update_cr6().

◆ dmfe_program_DM9801() [2/2]

static void dmfe_program_DM9801 ( struct nic *nic  __unused,
int  HPNA_rev 
)
static

Definition at line 1151 of file dmfe.c.

1152 {
1153  u32 reg17, reg25;
1154 
1155  if (!HPNA_NoiseFloor)
1157  switch (HPNA_rev) {
1158  case 0xb900: /* DM9801 E3 */
1159  db->HPNA_command |= 0x1000;
1160  reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id);
1161  reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1162  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1163  break;
1164  case 0xb901: /* DM9801 E4 */
1165  reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1166  reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1167  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1168  reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1169  break;
1170  case 0xb902: /* DM9801 E5 */
1171  case 0xb903: /* DM9801 E6 */
1172  default:
1173  db->HPNA_command |= 0x1000;
1174  reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1175  reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1176  reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
1177  reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1178  break;
1179  }
1181  phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id);
1182  phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id);
1183 }
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:881
u32 chip_id
Definition: dmfe.c:150
#define DM9801_NOISE_FLOOR
Definition: dmfe.c:87
static struct dmfe_private * db
Definition: dmfe.c:177
static u8 HPNA_NoiseFloor
Definition: dmfe.c:204
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:935
u16 HPNA_command
Definition: dmfe.c:158
static long int BASE
Definition: dmfe.c:226
uint32_t u32
Definition: stdint.h:23
u8 phy_addr
Definition: dmfe.c:167

References BASE, dmfe_private::chip_id, db, DM9801_NOISE_FLOOR, dmfe_private::HPNA_command, HPNA_NoiseFloor, dmfe_private::phy_addr, phy_read(), and phy_write().

◆ dmfe_program_DM9802() [2/2]

static void dmfe_program_DM9802 ( struct nic *nic  __unused)
static

Definition at line 1190 of file dmfe.c.

1191 {
1192  u32 phy_reg;
1193 
1194  if (!HPNA_NoiseFloor)
1197  phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id);
1198  phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor;
1199  phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id);
1200 }
static void phy_write(unsigned long, u8, u8, u16, u32)
Definition: dmfe.c:881
u32 chip_id
Definition: dmfe.c:150
#define DM9802_NOISE_FLOOR
Definition: dmfe.c:88
static struct dmfe_private * db
Definition: dmfe.c:177
static u8 HPNA_NoiseFloor
Definition: dmfe.c:204
static u16 phy_read(unsigned long, u8, u8, u32)
Definition: dmfe.c:935
u16 HPNA_command
Definition: dmfe.c:158
static long int BASE
Definition: dmfe.c:226
uint32_t u32
Definition: stdint.h:23
u8 phy_addr
Definition: dmfe.c:167

References BASE, dmfe_private::chip_id, db, DM9802_NOISE_FLOOR, dmfe_private::HPNA_command, HPNA_NoiseFloor, dmfe_private::phy_addr, phy_read(), and phy_write().

◆ PCI_DRIVER()

PCI_DRIVER ( dmfe_driver  ,
dmfe_nics  ,
PCI_NO_CLASS   
)

◆ DRIVER()

DRIVER ( "DMFE/PCI"  ,
nic_driver  ,
pci_driver  ,
dmfe_driver  ,
dmfe_probe  ,
dmfe_disable   
)

Variable Documentation

◆ dfx

struct dmfe_private dfx
static

Referenced by dmfe_probe().

◆ db

struct dmfe_private* db
static

◆ dmfe_operations

static struct nic_operations dmfe_operations
static
Initial value:
= {
.connect = dummy_connect,
.poll = dmfe_poll,
.transmit = dmfe_transmit,
.irq = dmfe_irq,
}
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
static void dmfe_transmit(struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *packet)
Definition: dmfe.c:399
static int dmfe_poll(struct nic *nic, int retrieve)
Definition: dmfe.c:344
static void dmfe_irq(struct nic *nic __unused, irq_action_t action __unused)
Definition: dmfe.c:384

Definition at line 194 of file dmfe.c.

Referenced by dmfe_probe().

◆ dmfe_media_mode

unsigned char dmfe_media_mode = DMFE_AUTO
static

Definition at line 196 of file dmfe.c.

Referenced by dmfe_init_dm910x(), and dmfe_parse_srom().

◆ dmfe_cr6_user_set

u32 dmfe_cr6_user_set
static

Definition at line 197 of file dmfe.c.

Referenced by dmfe_reset().

◆ chkmode

u8 chkmode = 1
static

Definition at line 200 of file dmfe.c.

Referenced by dmfe_reset().

◆ HPNA_mode

u8 HPNA_mode
static

Definition at line 201 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_rx_cmd

u8 HPNA_rx_cmd
static

Definition at line 202 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_tx_cmd

u8 HPNA_tx_cmd
static

Definition at line 203 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_NoiseFloor

u8 HPNA_NoiseFloor
static

Definition at line 204 of file dmfe.c.

Referenced by dmfe_program_DM9801(), and dmfe_program_DM9802().

◆ SF_mode

u8 SF_mode
static

Definition at line 205 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ txd

struct tx_desc txd[TX_DESC_CNT]

Definition at line 213 of file dmfe.c.

◆ txb

unsigned char txb[TX_BUF_ALLOC *TX_DESC_CNT]

Definition at line 215 of file dmfe.c.

◆ rxd

struct rx_desc rxd[RX_DESC_CNT]

Definition at line 216 of file dmfe.c.

◆ rxb

unsigned char rxb[RX_ALLOC_SIZE *RX_DESC_CNT]

Definition at line 218 of file dmfe.c.

◆ __shared

struct { ... } __shared

◆ BASE

long int BASE
static

◆ dmfe_nics

struct pci_device_id dmfe_nics[]
static
Initial value:
= {
PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0),
}
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283

Definition at line 1210 of file dmfe.c.