#include "etherboot.h"
#include "nic.h"
#include <ipxe/pci.h>
#include <ipxe/ethernet.h>

Data Structures
struct	tx_desc

struct	rx_desc

struct	dmfe_private

Macros
#define	dprintf(x)

#define	virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))

#define	le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))

#define	PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */

#define	PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */

#define	PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */

#define	PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */

#define	DM9102_IO_SIZE 0x80

#define	DM9102A_IO_SIZE 0x100

#define	TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */

#define	TX_DESC_CNT 0x10 /* Allocated Tx descriptors */

#define	RX_DESC_CNT 0x20 /* Allocated Rx descriptors */

#define	TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */

#define	TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */

#define	DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)

#define	TX_BUF_ALLOC 0x600

#define	RX_ALLOC_SIZE 0x620

#define	DM910X_RESET 1

#define	CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */

#define	CR6_DEFAULT 0x00080000 /* HD */

#define	CR7_DEFAULT 0x180c1

#define	CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */

#define	TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */

#define	MAX_PACKET_SIZE 1514

#define	DMFE_MAX_MULTICAST 14

#define	RX_COPY_SIZE 100

#define	MAX_CHECK_PACKET 0x8000

#define	DM9801_NOISE_FLOOR 8

#define	DM9802_NOISE_FLOOR 5

#define	DMFE_10MHF 0

#define	DMFE_100MHF 1

#define	DMFE_10MFD 4

#define	DMFE_100MFD 5

#define	DMFE_AUTO 8

#define	DMFE_1M_HPNA 0x10

#define	DMFE_TXTH_72 0x400000 /* TX TH 72 byte */

#define	DMFE_TXTH_96 0x404000 /* TX TH 96 byte */

#define	DMFE_TXTH_128 0x0000 /* TX TH 128 byte */

#define	DMFE_TXTH_256 0x4000 /* TX TH 256 byte */

#define	DMFE_TXTH_512 0x8000 /* TX TH 512 byte */

#define	DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */

#define	DMFE_TIMER_WUT (jiffies + HZ * 1) /* timer wakeup time : 1 second */

#define	DMFE_TX_TIMEOUT ((3HZ)/2) / tx packet time-out time 1.5 s" */

#define	DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */

#define	DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug \|\| (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))

#define	SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");

#define	CR9_SROM_READ 0x4800

#define	CR9_SRCS 0x1

#define	CR9_SRCLK 0x2

#define	CR9_CRDOUT 0x8

#define	SROM_DATA_0 0x0

#define	SROM_DATA_1 0x4

#define	PHY_DATA_1 0x20000

#define	PHY_DATA_0 0x00000

#define	MDCLKH 0x10000

#define	PHY_POWER_DOWN 0x800

#define	SROM_V41_CODE 0x14

#define	SROM_CLK_WRITE(data, ioaddr) outl(data\|CR9_SROM_READ\|CR9_SRCS,ioaddr);udelay(5);outl(data\|CR9_SROM_READ\|CR9_SRCS\|CR9_SRCLK,ioaddr);udelay(5);outl(data\|CR9_SROM_READ\|CR9_SRCS,ioaddr);udelay(5);

#define	__CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) \|\| ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE

#define	CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) \| (pci_dev)->vendor, dev_rev)

#define	DEVICE net_device

#define	txd dmfe_bufs.txd

#define	txb dmfe_bufs.txb

#define	rxd dmfe_bufs.rxd

#define	rxb dmfe_bufs.rxb

#define	board_found 1

#define	valid_link 0

Enumerations
enum	dmfe_offsets { DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14, DCR15 = 0x78 }

enum	dmfe_CR6_bits { CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 }

Functions
	FILE_LICENCE (GPL2_OR_LATER)

static u16	read_srom_word (long ioaddr, int offset)

static void	dmfe_init_dm910x (struct nic *nic)

static void	dmfe_descriptor_init (struct nic *, unsigned long ioaddr)

static void	update_cr6 (u32, unsigned long)

static void	send_filter_frame (struct nic *nic)

static void	dm9132_id_table (struct nic *nic)

static u16	phy_read (unsigned long, u8, u8, u32)

static void	phy_write (unsigned long, u8, u8, u16, u32)

static void	phy_write_1bit (unsigned long, u32)

static u16	phy_read_1bit (unsigned long)

static void	dmfe_set_phyxcer (struct nic *nic)

static void	dmfe_parse_srom (struct nic *nic)

static void	dmfe_program_DM9801 (struct nic *nic, int)

static void	dmfe_program_DM9802 (struct nic *nic)

static void	dmfe_reset (struct nic *nic)

static int	dmfe_poll (struct nic *nic, int retrieve)

static void	dmfe_irq (struct nic *nic __unused, irq_action_t action __unused)

static void	dmfe_transmit (struct nic nic, const char dest, unsigned int type, unsigned int size, const char *packet)

static void	dmfe_disable (struct nic *nic __unused)

static int	dmfe_probe (struct nic nic, struct pci_device pci)

static void	dmfe_descriptor_init (struct nic *nic __unused, unsigned long ioaddr)

static void	dm9132_id_table (struct nic *nic __unused)

static void	dmfe_set_phyxcer (struct nic *nic __unused)

static void	dmfe_program_DM9801 (struct nic *nic __unused, int HPNA_rev)

static void	dmfe_program_DM9802 (struct nic *nic __unused)

	PCI_DRIVER (dmfe_driver, dmfe_nics, PCI_NO_CLASS)

	DRIVER ("DMFE/PCI", nic_driver, pci_driver, dmfe_driver, dmfe_probe, dmfe_disable)

Variables
static struct dmfe_private	dfx

static struct dmfe_private *	db

static struct nic_operations	dmfe_operations

static unsigned char	dmfe_media_mode = DMFE_AUTO

static u32	dmfe_cr6_user_set

static u8	chkmode = 1

static u8	HPNA_mode

static u8	HPNA_rx_cmd

static u8	HPNA_tx_cmd

static u8	HPNA_NoiseFloor

static u8	SF_mode

struct {
struct tx_desc txd [TX_DESC_CNT]

unsigned char txb [TX_BUF_ALLOC *TX_DESC_CNT]

struct rx_desc rxd [RX_DESC_CNT]

unsigned char rxb [RX_ALLOC_SIZE *RX_DESC_CNT]

}	__shared

static long int	BASE

static struct pci_device_id	dmfe_nics []

Macro Definition Documentation

◆ dprintf

#define dprintf ( x )

Definition at line 54 of file dmfe.c.

◆ virt_to_le32desc

#define virt_to_le32desc ( addr ) cpu_to_le32(virt_to_bus(addr))

Definition at line 58 of file dmfe.c.

◆ le32desc_to_virt

#define le32desc_to_virt ( addr ) bus_to_virt(le32_to_cpu(addr))

Definition at line 59 of file dmfe.c.

◆ PCI_DM9132_ID

#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */

Definition at line 62 of file dmfe.c.

◆ PCI_DM9102_ID

#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */

Definition at line 63 of file dmfe.c.

◆ PCI_DM9100_ID

#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */

Definition at line 64 of file dmfe.c.

◆ PCI_DM9009_ID

#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */

Definition at line 65 of file dmfe.c.

◆ DM9102_IO_SIZE

#define DM9102_IO_SIZE 0x80

Definition at line 67 of file dmfe.c.

◆ DM9102A_IO_SIZE

#define DM9102A_IO_SIZE 0x100

Definition at line 68 of file dmfe.c.

◆ TX_MAX_SEND_CNT

#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */

Definition at line 69 of file dmfe.c.

◆ TX_DESC_CNT

#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */

Definition at line 70 of file dmfe.c.

◆ RX_DESC_CNT

#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */

Definition at line 71 of file dmfe.c.

◆ TX_FREE_DESC_CNT

#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */

Definition at line 72 of file dmfe.c.

◆ TX_WAKE_DESC_CNT

#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */

Definition at line 73 of file dmfe.c.

◆ DESC_ALL_CNT

#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)

Definition at line 74 of file dmfe.c.

◆ TX_BUF_ALLOC

#define TX_BUF_ALLOC 0x600

Definition at line 75 of file dmfe.c.

◆ RX_ALLOC_SIZE

#define RX_ALLOC_SIZE 0x620

Definition at line 76 of file dmfe.c.

◆ DM910X_RESET

#define DM910X_RESET 1

Definition at line 77 of file dmfe.c.

◆ CR0_DEFAULT

#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */

Definition at line 78 of file dmfe.c.

◆ CR6_DEFAULT

#define CR6_DEFAULT 0x00080000 /* HD */

Definition at line 79 of file dmfe.c.

◆ CR7_DEFAULT

#define CR7_DEFAULT 0x180c1

Definition at line 80 of file dmfe.c.

◆ CR15_DEFAULT

#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */

Definition at line 81 of file dmfe.c.

◆ TDES0_ERR_MASK

#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */

Definition at line 82 of file dmfe.c.

◆ MAX_PACKET_SIZE

#define MAX_PACKET_SIZE 1514

Definition at line 83 of file dmfe.c.

◆ DMFE_MAX_MULTICAST

#define DMFE_MAX_MULTICAST 14

Definition at line 84 of file dmfe.c.

◆ RX_COPY_SIZE

#define RX_COPY_SIZE 100

Definition at line 85 of file dmfe.c.

◆ MAX_CHECK_PACKET

#define MAX_CHECK_PACKET 0x8000

Definition at line 86 of file dmfe.c.

◆ DM9801_NOISE_FLOOR

#define DM9801_NOISE_FLOOR 8

Definition at line 87 of file dmfe.c.

◆ DM9802_NOISE_FLOOR

#define DM9802_NOISE_FLOOR 5

Definition at line 88 of file dmfe.c.

◆ DMFE_10MHF

#define DMFE_10MHF 0

Definition at line 90 of file dmfe.c.

◆ DMFE_100MHF

#define DMFE_100MHF 1

Definition at line 91 of file dmfe.c.

◆ DMFE_10MFD

#define DMFE_10MFD 4

Definition at line 92 of file dmfe.c.

◆ DMFE_100MFD

#define DMFE_100MFD 5

Definition at line 93 of file dmfe.c.

◆ DMFE_AUTO

#define DMFE_AUTO 8

Definition at line 94 of file dmfe.c.

◆ DMFE_1M_HPNA

#define DMFE_1M_HPNA 0x10

Definition at line 95 of file dmfe.c.

◆ DMFE_TXTH_72

#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */

Definition at line 97 of file dmfe.c.

◆ DMFE_TXTH_96

#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */

Definition at line 98 of file dmfe.c.

◆ DMFE_TXTH_128

#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */

Definition at line 99 of file dmfe.c.

◆ DMFE_TXTH_256

#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */

Definition at line 100 of file dmfe.c.

◆ DMFE_TXTH_512

#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */

Definition at line 101 of file dmfe.c.

◆ DMFE_TXTH_1K

#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */

Definition at line 102 of file dmfe.c.

◆ DMFE_TIMER_WUT

#define DMFE_TIMER_WUT (jiffies + HZ * 1) /* timer wakeup time : 1 second */

Definition at line 104 of file dmfe.c.

◆ DMFE_TX_TIMEOUT

#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */

Definition at line 105 of file dmfe.c.

◆ DMFE_TX_KICK

#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */

Definition at line 106 of file dmfe.c.

◆ DMFE_DBUG

#define DMFE_DBUG	(	dbug_now,
		msg,
		value
	)	if (dmfe_debug \|\| (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))

Definition at line 108 of file dmfe.c.

◆ SHOW_MEDIA_TYPE

#define SHOW_MEDIA_TYPE ( mode ) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");

Definition at line 110 of file dmfe.c.

◆ CR9_SROM_READ

#define CR9_SROM_READ 0x4800

Definition at line 114 of file dmfe.c.

◆ CR9_SRCS

#define CR9_SRCS 0x1

Definition at line 115 of file dmfe.c.

◆ CR9_SRCLK

#define CR9_SRCLK 0x2

Definition at line 116 of file dmfe.c.

◆ CR9_CRDOUT

#define CR9_CRDOUT 0x8

Definition at line 117 of file dmfe.c.

◆ SROM_DATA_0

#define SROM_DATA_0 0x0

Definition at line 118 of file dmfe.c.

◆ SROM_DATA_1

#define SROM_DATA_1 0x4

Definition at line 119 of file dmfe.c.

◆ PHY_DATA_1

#define PHY_DATA_1 0x20000

Definition at line 120 of file dmfe.c.

◆ PHY_DATA_0

#define PHY_DATA_0 0x00000

Definition at line 121 of file dmfe.c.

◆ MDCLKH

#define MDCLKH 0x10000

Definition at line 122 of file dmfe.c.

◆ PHY_POWER_DOWN

#define PHY_POWER_DOWN 0x800

Definition at line 124 of file dmfe.c.

◆ SROM_V41_CODE

#define SROM_V41_CODE 0x14

Definition at line 126 of file dmfe.c.

◆ SROM_CLK_WRITE

#define SROM_CLK_WRITE	(	data,
		ioaddr
	)	outl(data\|CR9_SROM_READ\|CR9_SRCS,ioaddr);udelay(5);outl(data\|CR9_SROM_READ\|CR9_SRCS\|CR9_SRCLK,ioaddr);udelay(5);outl(data\|CR9_SROM_READ\|CR9_SRCS,ioaddr);udelay(5);

Definition at line 128 of file dmfe.c.

◆ __CHK_IO_SIZE

#define __CHK_IO_SIZE	(	pci_id,
		dev_rev
	)	( ((pci_id)==PCI_DM9132_ID) \|\| ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE

Definition at line 130 of file dmfe.c.

◆ CHK_IO_SIZE

#define CHK_IO_SIZE	(	pci_dev,
		dev_rev
	)	__CHK_IO_SIZE(((pci_dev)->device << 16) \| (pci_dev)->vendor, dev_rev)

Definition at line 131 of file dmfe.c.

◆ DEVICE

#define DEVICE net_device

Definition at line 134 of file dmfe.c.

◆ txd

#define txd dmfe_bufs.txd

Definition at line 220 of file dmfe.c.

◆ txb

#define txb dmfe_bufs.txb

Definition at line 221 of file dmfe.c.

◆ rxd

#define rxd dmfe_bufs.rxd

Definition at line 222 of file dmfe.c.

◆ rxb

#define rxb dmfe_bufs.rxb

Definition at line 223 of file dmfe.c.

◆ board_found

#define board_found 1

Definition at line 450 of file dmfe.c.

◆ valid_link

#define valid_link 0

Definition at line 451 of file dmfe.c.

Enumeration Type Documentation

◆ dmfe_offsets

enum dmfe_offsets

Enumerator
DCR0
DCR1
DCR2
DCR3
DCR4
DCR5
DCR6
DCR7
DCR8
DCR9
DCR10
DCR11
DCR12
DCR13
DCR14
DCR15

Definition at line 179 of file dmfe.c.

                   {
         DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
         DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
         DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 =
             0x70,
         DCR15 = 0x78
 };

◆ dmfe_CR6_bits

enum dmfe_CR6_bits

Enumerator
CR6_RXSC
CR6_PBF
CR6_PM
CR6_PAM
CR6_FDM
CR6_TXSC
CR6_STI
CR6_SFT
CR6_RXA
CR6_NO_PURGE

Definition at line 187 of file dmfe.c.

                    {
         CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
         CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
         CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
 };

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER )

◆ read_srom_word()

static u16 read_srom_word	(	long	ioaddr,
		int	offset
	)

static

Definition at line 663 of file dmfe.c.

 {
         int i;
         u16 srom_data = 0;
         long cr9_ioaddr = ioaddr + DCR9;
 
         outl(CR9_SROM_READ, cr9_ioaddr);
         outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
 
         /* Send the Read Command 110b */
         SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
         SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
         SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
 
         /* Send the offset */
         for (i = 5; i >= 0; i--) {
                 srom_data =
                     (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
                 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
         }
 
         outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
 
         for (i = 16; i > 0; i--) {
                 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
                 udelay(5);
                 srom_data =
                     (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1
                                         : 0);
                 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
                 udelay(5);
         }
 
         outl(CR9_SROM_READ, cr9_ioaddr);
         return srom_data;
 }

References CR9_CRDOUT, CR9_SRCLK, CR9_SRCS, CR9_SROM_READ, DCR9, inl(), ioaddr, offset, outl, SROM_CLK_WRITE, SROM_DATA_0, SROM_DATA_1, and udelay().

Referenced by dmfe_probe().

◆ dmfe_init_dm910x()

static void dmfe_init_dm910x ( struct nic * nic )

static

Definition at line 277 of file dmfe.c.

 {
         unsigned long ioaddr = BASE;
 
         /* Reset DM910x MAC controller */
         outl(DM910X_RESET, ioaddr + DCR0);      /* RESET MAC */
         udelay(100);
         outl(db->cr0_data, ioaddr + DCR0);
         udelay(5);
 
         /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
         db->phy_addr = 1;
 
         /* Parser SROM and media mode */
         dmfe_parse_srom(nic);
         db->media_mode = dmfe_media_mode;
 
         /* RESET Phyxcer Chip by GPR port bit 7 */
         outl(0x180, ioaddr + DCR12);    /* Let bit 7 output port */
         if (db->chip_id == PCI_DM9009_ID) {
                 outl(0x80, ioaddr + DCR12);     /* Issue RESET signal */
                 mdelay(300);    /* Delay 300 ms */
         }
         outl(0x0, ioaddr + DCR12);      /* Clear RESET signal */
 
         /* Process Phyxcer Media Mode */
         if (!(db->media_mode & 0x10))   /* Force 1M mode */
                 dmfe_set_phyxcer(nic);
 
         /* Media Mode Process */
         if (!(db->media_mode & DMFE_AUTO))
                 db->op_mode = db->media_mode;   /* Force Mode */
 
         /* Initiliaze Transmit/Receive descriptor and CR3/4 */
         dmfe_descriptor_init(nic, ioaddr);
 
         /* tx descriptor start pointer */
         outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
 
         /* rx descriptor start pointer */
         outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
 
         /* Init CR6 to program DM910x operation */
         update_cr6(db->cr6_data, ioaddr);
 
         /* Send setup frame */
         if (db->chip_id == PCI_DM9132_ID) {
                 dm9132_id_table(nic);   /* DM9132 */
         } else {
                 send_filter_frame(nic); /* DM9102/DM9102A */
         }
 
         /* Init CR7, interrupt active bit */
         db->cr7_data = CR7_DEFAULT;
         outl(db->cr7_data, ioaddr + DCR7);
         /* Init CR15, Tx jabber and Rx watchdog timer */
         outl(db->cr15_data, ioaddr + DCR15);
         /* Enable DM910X Tx/Rx function */
         db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
         update_cr6(db->cr6_data, ioaddr);
 }

References BASE, dmfe_private::chip_id, dmfe_private::cr0_data, dmfe_private::cr15_data, dmfe_private::cr6_data, CR6_RXSC, CR6_TXSC, dmfe_private::cr7_data, CR7_DEFAULT, db, DCR0, DCR12, DCR15, DCR3, DCR4, DCR7, DM910X_RESET, dm9132_id_table(), DMFE_AUTO, dmfe_descriptor_init(), dmfe_media_mode, dmfe_parse_srom(), dmfe_set_phyxcer(), ioaddr, mdelay(), dmfe_private::media_mode, dmfe_private::op_mode, outl, PCI_DM9009_ID, PCI_DM9132_ID, dmfe_private::phy_addr, rxd, send_filter_frame(), txd, udelay(), update_cr6(), and virt_to_le32desc.

Referenced by dmfe_reset().

◆ dmfe_descriptor_init() [1/2]

static void dmfe_descriptor_init	(	struct nic *	,
		unsigned long	ioaddr
	)

static

Referenced by dmfe_init_dm910x().

◆ update_cr6()

static void update_cr6	(	u32	cr6_data,
		unsigned long	ioaddr
	)

static

Definition at line 561 of file dmfe.c.

 {
         u32 cr6_tmp;
 
         cr6_tmp = cr6_data & ~0x2002;   /* stop Tx/Rx */
         outl(cr6_tmp, ioaddr + DCR6);
         udelay(5);
         outl(cr6_data, ioaddr + DCR6);
         udelay(5);
 }

References DCR6, ioaddr, outl, and udelay().

Referenced by dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_set_phyxcer(), and send_filter_frame().

◆ send_filter_frame()

static void send_filter_frame ( struct nic * nic )

static

Definition at line 629 of file dmfe.c.

 {
 
         u8 *ptxb;
         int i;
 
         dprintf(("send_filter_frame\n"));
         /* point to the current txb incase multiple tx_rings are used */
         ptxb = &txb[db->cur_tx];
 
         /* construct perfect filter frame with mac address as first match
            and broadcast address for all others */
         for (i = 0; i < 192; i++)
                 ptxb[i] = 0xFF;
         ptxb[0] = nic->node_addr[0];
         ptxb[1] = nic->node_addr[1];
         ptxb[4] = nic->node_addr[2];
         ptxb[5] = nic->node_addr[3];
         ptxb[8] = nic->node_addr[4];
         ptxb[9] = nic->node_addr[5];
 
         /* prepare the setup frame */
         txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0);
         txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);
         update_cr6(db->cr6_data | 0x2000, BASE);
         outl(0x1, BASE + DCR1); /* Issue Tx polling */
         update_cr6(db->cr6_data, BASE);
         db->cur_tx++;
 }

References BASE, cpu_to_le32, dmfe_private::cr6_data, dmfe_private::cur_tx, db, DCR1, dprintf, nic::node_addr, outl, txb, txd, and update_cr6().

Referenced by dmfe_init_dm910x().

◆ dm9132_id_table() [1/2]

static void dm9132_id_table ( struct nic * nic )

static

Referenced by dmfe_init_dm910x().

◆ phy_read()

static u16 phy_read	(	unsigned long	iobase,
		u8	phy_addr,
		u8	offset,
		u32	chip_id
	)

static

Definition at line 935 of file dmfe.c.

 {
         int i;
         u16 phy_data;
         unsigned long ioaddr;
 
         if (chip_id == PCI_DM9132_ID) {
                 /* DM9132 Chip */
                 ioaddr = iobase + 0x80 + offset * 4;
                 phy_data = inw(ioaddr);
         } else {
                 /* DM9102/DM9102A Chip */
                 ioaddr = iobase + DCR9;
 
                 /* Send 33 synchronization clock to Phy controller */
                 for (i = 0; i < 35; i++)
                         phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send start command(01) to Phy */
                 phy_write_1bit(ioaddr, PHY_DATA_0);
                 phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send read command(10) to Phy */
                 phy_write_1bit(ioaddr, PHY_DATA_1);
                 phy_write_1bit(ioaddr, PHY_DATA_0);
 
                 /* Send Phy address */
                 for (i = 0x10; i > 0; i = i >> 1)
                         phy_write_1bit(ioaddr,
                                        phy_addr & i ? PHY_DATA_1 :
                                        PHY_DATA_0);
 
                 /* Send register address */
                 for (i = 0x10; i > 0; i = i >> 1)
                         phy_write_1bit(ioaddr,
                                        offset & i ? PHY_DATA_1 :
                                        PHY_DATA_0);
 
                 /* Skip transition state */
                 phy_read_1bit(ioaddr);
 
                 /* read 16bit data */
                 for (phy_data = 0, i = 0; i < 16; i++) {
                         phy_data <<= 1;
                         phy_data |= phy_read_1bit(ioaddr);
                 }
         }
 
         return phy_data;
 }

References DCR9, inw(), ioaddr, offset, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, phy_read_1bit(), and phy_write_1bit().

Referenced by dmfe_parse_srom(), dmfe_program_DM9801(), dmfe_program_DM9802(), and dmfe_set_phyxcer().

◆ phy_write()

static void phy_write	(	unsigned long	iobase,
		u8	phy_addr,
		u8	offset,
		u16	phy_data,
		u32	chip_id
	)

static

Definition at line 881 of file dmfe.c.

 {
         u16 i;
         unsigned long ioaddr;
 
         if (chip_id == PCI_DM9132_ID) {
                 ioaddr = iobase + 0x80 + offset * 4;
                 outw(phy_data, ioaddr);
         } else {
                 /* DM9102/DM9102A Chip */
                 ioaddr = iobase + DCR9;
 
                 /* Send 33 synchronization clock to Phy controller */
                 for (i = 0; i < 35; i++)
                         phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send start command(01) to Phy */
                 phy_write_1bit(ioaddr, PHY_DATA_0);
                 phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send write command(01) to Phy */
                 phy_write_1bit(ioaddr, PHY_DATA_0);
                 phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send Phy address */
                 for (i = 0x10; i > 0; i = i >> 1)
                         phy_write_1bit(ioaddr,
                                        phy_addr & i ? PHY_DATA_1 :
                                        PHY_DATA_0);
 
                 /* Send register address */
                 for (i = 0x10; i > 0; i = i >> 1)
                         phy_write_1bit(ioaddr,
                                        offset & i ? PHY_DATA_1 :
                                        PHY_DATA_0);
 
                 /* written trasnition */
                 phy_write_1bit(ioaddr, PHY_DATA_1);
                 phy_write_1bit(ioaddr, PHY_DATA_0);
 
                 /* Write a word data to PHY controller */
                 for (i = 0x8000; i > 0; i >>= 1)
                         phy_write_1bit(ioaddr,
                                        phy_data & i ? PHY_DATA_1 :
                                        PHY_DATA_0);
         }
 }

References DCR9, ioaddr, offset, outw, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, and phy_write_1bit().

Referenced by dmfe_disable(), dmfe_program_DM9801(), dmfe_program_DM9802(), and dmfe_set_phyxcer().

◆ phy_write_1bit()

static void phy_write_1bit	(	unsigned long	ioaddr,
		u32	phy_data
	)

static

Definition at line 992 of file dmfe.c.

 {
         outl(phy_data, ioaddr); /* MII Clock Low */
         udelay(1);
         outl(phy_data | MDCLKH, ioaddr);        /* MII Clock High */
         udelay(1);
         outl(phy_data, ioaddr); /* MII Clock Low */
         udelay(1);
 }

References ioaddr, MDCLKH, outl, and udelay().

Referenced by phy_read(), and phy_write().

◆ phy_read_1bit()

static u16 phy_read_1bit ( unsigned long ioaddr )

static

Definition at line 1007 of file dmfe.c.

 {
         u16 phy_data;
 
         outl(0x50000, ioaddr);
         udelay(1);
         phy_data = (inl(ioaddr) >> 19) & 0x1;
         outl(0x40000, ioaddr);
         udelay(1);
 
         return phy_data;
 }

References inl(), ioaddr, outl, and udelay().

Referenced by phy_read().

◆ dmfe_set_phyxcer() [1/2]

static void dmfe_set_phyxcer ( struct nic * nic )

static

Referenced by dmfe_init_dm910x().

◆ dmfe_parse_srom()

static void dmfe_parse_srom ( struct nic * nic )

static

Definition at line 1025 of file dmfe.c.

 {
         unsigned char *srom = db->srom;
         int dmfe_mode, tmp_reg;
 
         /* Init CR15 */
         db->cr15_data = CR15_DEFAULT;
 
         /* Check SROM Version */
         if (((int) srom[18] & 0xff) == SROM_V41_CODE) {
                 /* SROM V4.01 */
                 /* Get NIC support media mode */
                 db->NIC_capability = *(u16 *) (srom + 34);
                 db->PHY_reg4 = 0;
                 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
                         switch (db->NIC_capability & tmp_reg) {
                         case 0x1:
                                 db->PHY_reg4 |= 0x0020;
                                 break;
                         case 0x2:
                                 db->PHY_reg4 |= 0x0040;
                                 break;
                         case 0x4:
                                 db->PHY_reg4 |= 0x0080;
                                 break;
                         case 0x8:
                                 db->PHY_reg4 |= 0x0100;
                                 break;
                         }
                 }
 
                 /* Media Mode Force or not check */
                 dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36);
                 switch (dmfe_mode) {
                 case 0x4:
                         dmfe_media_mode = DMFE_100MHF;
                         break;  /* 100MHF */
                 case 0x2:
                         dmfe_media_mode = DMFE_10MFD;
                         break;  /* 10MFD */
                 case 0x8:
                         dmfe_media_mode = DMFE_100MFD;
                         break;  /* 100MFD */
                 case 0x100:
                 case 0x200:
                         dmfe_media_mode = DMFE_1M_HPNA;
                         break;  /* HomePNA */
                 }
 
                 /* Special Function setting */
                 /* VLAN function */
                 if ((SF_mode & 0x1) || (srom[43] & 0x80))
                         db->cr15_data |= 0x40;
 
                 /* Flow Control */
                 if ((SF_mode & 0x2) || (srom[40] & 0x1))
                         db->cr15_data |= 0x400;
 
                 /* TX pause packet */
                 if ((SF_mode & 0x4) || (srom[40] & 0xe))
                         db->cr15_data |= 0x9800;
         }
 
         /* Parse HPNA parameter */
         db->HPNA_command = 1;
 
         /* Accept remote command or not */
         if (HPNA_rx_cmd == 0)
                 db->HPNA_command |= 0x8000;
 
         /* Issue remote command & operation mode */
         if (HPNA_tx_cmd == 1)
                 switch (HPNA_mode) {    /* Issue Remote Command */
                 case 0:
                         db->HPNA_command |= 0x0904;
                         break;
                 case 1:
                         db->HPNA_command |= 0x0a00;
                         break;
                 case 2:
                         db->HPNA_command |= 0x0506;
                         break;
                 case 3:
                         db->HPNA_command |= 0x0602;
                         break;
         } else
                 switch (HPNA_mode) {    /* Don't Issue */
                 case 0:
                         db->HPNA_command |= 0x0004;
                         break;
                 case 1:
                         db->HPNA_command |= 0x0000;
                         break;
                 case 2:
                         db->HPNA_command |= 0x0006;
                         break;
                 case 3:
                         db->HPNA_command |= 0x0002;
                         break;
                 }
 
         /* Check DM9801 or DM9802 present or not */
         db->HPNA_present = 0;
         update_cr6(db->cr6_data | 0x40000, BASE);
         tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id);
         if ((tmp_reg & 0xfff0) == 0xb900) {
                 /* DM9801 or DM9802 present */
                 db->HPNA_timer = 8;
                 if (phy_read(BASE, db->phy_addr, 31, db->chip_id) ==
                     0x4404) {
                         /* DM9801 HomeRun */
                         db->HPNA_present = 1;
                         dmfe_program_DM9801(nic, tmp_reg);
                 } else {
                         /* DM9802 LongRun */
                         db->HPNA_present = 2;
                         dmfe_program_DM9802(nic);
                 }
         }
 
 }

References BASE, dmfe_private::chip_id, dmfe_private::cr15_data, CR15_DEFAULT, dmfe_private::cr6_data, db, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_1M_HPNA, dmfe_media_mode, dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_private::HPNA_command, HPNA_mode, dmfe_private::HPNA_present, HPNA_rx_cmd, dmfe_private::HPNA_timer, HPNA_tx_cmd, dmfe_private::NIC_capability, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, SF_mode, dmfe_private::srom, SROM_V41_CODE, and update_cr6().

Referenced by dmfe_init_dm910x().

◆ dmfe_program_DM9801() [1/2]

static void dmfe_program_DM9801	(	struct nic *	nic,
		int
	)

static

Referenced by dmfe_parse_srom().

◆ dmfe_program_DM9802() [1/2]

static void dmfe_program_DM9802 ( struct nic * nic )

static

Referenced by dmfe_parse_srom().

◆ dmfe_reset()

static void dmfe_reset ( struct nic * nic )

static

Definition at line 245 of file dmfe.c.

 {
         /* system variable init */
         db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
 
         db->NIC_capability = 0xf;       /* All capability */
         db->PHY_reg4 = 0x1e0;
 
         /* CR6 operation mode decision */
         if (!chkmode || (db->chip_id == PCI_DM9132_ID) ||
             (db->chip_revision >= 0x02000030)) {
                 db->cr6_data |= DMFE_TXTH_256;
                 db->cr0_data = CR0_DEFAULT;
                 db->dm910x_chk_mode = 4;        /* Enter the normal mode */
         } else {
                 db->cr6_data |= CR6_SFT;        /* Store & Forward mode */
                 db->cr0_data = 0;
                 db->dm910x_chk_mode = 1;        /* Enter the check mode */
         }
         /* Initialize DM910X board */
         dmfe_init_dm910x(nic);
 
         return;
 }

References dmfe_private::chip_id, dmfe_private::chip_revision, chkmode, dmfe_private::cr0_data, CR0_DEFAULT, dmfe_private::cr6_data, CR6_DEFAULT, CR6_SFT, db, dmfe_private::dm910x_chk_mode, dmfe_cr6_user_set, dmfe_init_dm910x(), DMFE_TXTH_256, dmfe_private::NIC_capability, PCI_DM9132_ID, and dmfe_private::PHY_reg4.

Referenced by dmfe_probe().

◆ dmfe_poll()

static int dmfe_poll	(	struct nic *	nic,
		int	retrieve
	)

static

Definition at line 344 of file dmfe.c.

 {
         u32 rdes0;
         int entry = db->cur_rx % RX_DESC_CNT;
         int rxlen;
         rdes0 = le32_to_cpu(rxd[entry].rdes0);
         if (rdes0 & 0x80000000)
                 return 0;
 
         if (!retrieve)
                 return 1;
 
         if ((rdes0 & 0x300) != 0x300) {
                 /* A packet without First/Last flag */
                 printf("strange Packet\n");
                 rxd[entry].rdes0 = cpu_to_le32(0x80000000);
                 return 0;
         } else {
                 /* A packet with First/Last flag */
                 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
                 /* error summary bit check */
                 if (rdes0 & 0x8000) {
                         printf("Error\n");
                         return 0;
                 }
                 if (!(rdes0 & 0x8000) ||
                     ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
                         if (db->dm910x_chk_mode & 1)
                                 printf("Silly check mode\n");
 
                         nic->packetlen = rxlen;
                         memcpy(nic->packet, rxb + (entry * RX_ALLOC_SIZE),
                                nic->packetlen);
                 }
         }
         rxd[entry].rdes0 = cpu_to_le32(0x80000000);
         db->cur_rx++;
         return 1;
 }

References cpu_to_le32, dmfe_private::cr6_data, CR6_PM, dmfe_private::cur_rx, db, dmfe_private::dm910x_chk_mode, le32_to_cpu, memcpy(), nic::packet, nic::packetlen, printf(), rx_desc::rdes0, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, and rxlen.

◆ dmfe_irq()

static void dmfe_irq	(	struct nic *nic	__unused,
		irq_action_t action	__unused
	)

static

Definition at line 384 of file dmfe.c.

 {
         switch ( action ) {
                 case DISABLE :
                         break;
                 case ENABLE :
                         break;
                 case FORCE :
                         break;
         }
 }

References DISABLE, ENABLE, and FORCE.

◆ dmfe_transmit()

static void dmfe_transmit	(	struct nic *	nic,
		const char *	dest,
		unsigned int	type,
		unsigned int	size,
		const char *	packet
	)

static

Definition at line 399 of file dmfe.c.

 {       
         u16 nstype;
         u8 *ptxb;
 
         ptxb = &txb[db->cur_tx];
 
         /* Stop Tx */
         outl(0, BASE + DCR7);
         memcpy(ptxb, dest, ETH_ALEN);
         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
         nstype = htons((u16) type);
         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
         memcpy(ptxb + ETH_HLEN, packet, size);
 
         size += ETH_HLEN;
         while (size < ETH_ZLEN)
                 ptxb[size++] = '\0';
 
         /* setup the transmit descriptor */
         txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size);
         txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);        /* give ownership to device */
 
         /* immediate transmit demand */
         outl(0x1, BASE + DCR1);
         outl(db->cr7_data, BASE + DCR7);
 
         /* Point to next TX descriptor */
         db->cur_tx++;
         db->cur_tx = db->cur_tx % TX_DESC_CNT;
 }

References BASE, cpu_to_le32, dmfe_private::cr7_data, dmfe_private::cur_tx, db, DCR1, DCR7, dest, ETH_ALEN, ETH_HLEN, ETH_ZLEN, htons, memcpy(), nic::node_addr, outl, size, TX_DESC_CNT, txb, txd, and type.

◆ dmfe_disable()

static void dmfe_disable ( struct nic *nic __unused )

static

Definition at line 438 of file dmfe.c.

                                                       {
         /* Reset & stop DM910X board */
         outl(DM910X_RESET, BASE + DCR0);
         udelay(5);
         phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
 
 }

References BASE, dmfe_private::chip_id, db, DCR0, DM910X_RESET, outl, dmfe_private::phy_addr, phy_write(), and udelay().

◆ dmfe_probe()

static int dmfe_probe	(	struct nic *	nic,
		struct pci_device *	pci
	)

static

Definition at line 452 of file dmfe.c.

                                                                   {
 
         uint32_t dev_rev, pci_pmr;
         int i;
 
         if (pci->ioaddr == 0)
                 return 0;
 
         BASE = pci->ioaddr;
         printf("dmfe.c: Found %s Vendor=0x%hX Device=0x%hX\n",
                pci->id->name, pci->vendor, pci->device);
 
         /* Read Chip revision */
         pci_read_config_dword(pci, PCI_REVISION, &dev_rev);
         dprintf(("Revision %lX\n", dev_rev));
 
         /* point to private storage */
         db = &dfx;
 
         db->chip_id = ((u32) pci->device << 16) | pci->vendor;
         BASE = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
         db->chip_revision = dev_rev;
 
         pci_read_config_dword(pci, 0x50, &pci_pmr);
         pci_pmr &= 0x70000;
         if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031))
                 db->chip_type = 1;      /* DM9102A E3 */
         else
                 db->chip_type = 0;
 
         dprintf(("Chip type : %d\n", db->chip_type));
 
         /* read 64 word srom data */
         for (i = 0; i < 64; i++)
                 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i));
 
         /* Set Node address */
         for (i = 0; i < 6; i++)
                 nic->node_addr[i] = db->srom[20 + i];
 
         /* Print out some hardware info */
         DBG ( "%s: %s at ioaddr %4.4lx\n",
               pci->id->name, eth_ntoa ( nic->node_addr ), BASE );
 
         /* Set the card as PCI Bus Master */
         adjust_pci_device(pci);
 
         dmfe_reset(nic);
 
         nic->irqno  = 0;
         nic->ioaddr = pci->ioaddr;
 
         /* point to NIC specific routines */
         nic->nic_op     = &dmfe_operations;
 
         return 1;
 }

References adjust_pci_device(), BASE, dmfe_private::chip_id, dmfe_private::chip_revision, dmfe_private::chip_type, cpu_to_le16, db, DBG, pci_device::device, dfx, dmfe_operations, dmfe_reset(), dprintf, eth_ntoa(), pci_device::id, nic::ioaddr, pci_device::ioaddr, nic::irqno, pci_device_id::name, nic::nic_op, nic::node_addr, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_read_config_dword(), PCI_REVISION, printf(), read_srom_word(), dmfe_private::srom, u32, and pci_device::vendor.

◆ dmfe_descriptor_init() [2/2]

static void dmfe_descriptor_init	(	struct nic *nic	__unused,
		unsigned long	ioaddr
	)

static

Definition at line 515 of file dmfe.c.

 {
         int i;
         db->cur_tx = 0;
         db->cur_rx = 0;
 
         /* tx descriptor start pointer */
         outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
 
         /* rx descriptor start pointer */
         outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
 
         /* Init Transmit chain */
         for (i = 0; i < TX_DESC_CNT; i++) {
                 txd[i].tx_buf_ptr = &txb[i];
                 txd[i].tdes0 = cpu_to_le32(0);
                 txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
                 txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
                 txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
                 txd[i].next_tx_desc = &txd[i + 1];
         }
         /* Mark the last entry as wrapping the ring */
         txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
         txd[i - 1].next_tx_desc = &txd[0];
 
         /* receive descriptor chain */
         for (i = 0; i < RX_DESC_CNT; i++) {
                 rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
                 rxd[i].rdes0 = cpu_to_le32(0x80000000);
                 rxd[i].rdes1 = cpu_to_le32(0x01000600);
                 rxd[i].rdes2 =
                     cpu_to_le32(virt_to_bus(&rxb[i * RX_ALLOC_SIZE]));
                 rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
                 rxd[i].next_rx_desc = &rxd[i + 1];
         }
         /* Mark the last entry as wrapping the ring */
         rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
         rxd[i - 1].next_rx_desc = &rxd[0];
 
 }

References cpu_to_le32, dmfe_private::cur_rx, dmfe_private::cur_tx, db, DCR3, DCR4, ioaddr, outl, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, TX_DESC_CNT, txb, txd, virt_to_bus(), and virt_to_le32desc.

◆ dm9132_id_table() [2/2]

static void dm9132_id_table ( struct nic *nic __unused )

static

Definition at line 578 of file dmfe.c.

 {
 #ifdef LINUX
         u16 *addrptr;
         u8 dmi_addr[8];
         unsigned long ioaddr = BASE + 0xc0;     /* ID Table */
         u32 hash_val;
         u16 i, hash_table[4];
 #endif
         dprintf(("dm9132_id_table\n"));
 
         printf("FIXME: This function is broken.  If you have this card contact "
                 "Timothy Legge at the etherboot-user list\n");
 
 #ifdef LINUX
         //DMFE_DBUG(0, "dm9132_id_table()", 0);
 
         /* Node address */
         addrptr = (u16 *) nic->node_addr;
         outw(addrptr[0], ioaddr);
         ioaddr += 4;
         outw(addrptr[1], ioaddr);
         ioaddr += 4;
         outw(addrptr[2], ioaddr);
         ioaddr += 4;
 
         /* Clear Hash Table */
         for (i = 0; i < 4; i++)
                 hash_table[i] = 0x0;
 
         /* broadcast address */
         hash_table[3] = 0x8000;
 
         /* the multicast address in Hash Table : 64 bits */
         for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
                 hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
                 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
         }
 
         /* Write the hash table to MAC MD table */
         for (i = 0; i < 4; i++, ioaddr += 4)
                 outw(hash_table[i], ioaddr);
 #endif
 }

References BASE, dprintf, ioaddr, nic::node_addr, outw, printf(), and u16.

◆ dmfe_set_phyxcer() [2/2]

static void dmfe_set_phyxcer ( struct nic *nic __unused )

static

Definition at line 761 of file dmfe.c.

 {
         u16 phy_reg;
 
         /* Select 10/100M phyxcer */
         db->cr6_data &= ~0x40000;
         update_cr6(db->cr6_data, BASE);
 
         /* DM9009 Chip: Phyxcer reg18 bit12=0 */
         if (db->chip_id == PCI_DM9009_ID) {
                 phy_reg =
                     phy_read(BASE, db->phy_addr, 18,
                              db->chip_id) & ~0x1000;
                 phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id);
         }
 
         /* Phyxcer capability setting */
         phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0;
 
         if (db->media_mode & DMFE_AUTO) {
                 /* AUTO Mode */
                 phy_reg |= db->PHY_reg4;
         } else {
                 /* Force Mode */
                 switch (db->media_mode) {
                 case DMFE_10MHF:
                         phy_reg |= 0x20;
                         break;
                 case DMFE_10MFD:
                         phy_reg |= 0x40;
                         break;
                 case DMFE_100MHF:
                         phy_reg |= 0x80;
                         break;
                 case DMFE_100MFD:
                         phy_reg |= 0x100;
                         break;
                 }
                 if (db->chip_id == PCI_DM9009_ID)
                         phy_reg &= 0x61;
         }
 
         /* Write new capability to Phyxcer Reg4 */
         if (!(phy_reg & 0x01e0)) {
                 phy_reg |= db->PHY_reg4;
                 db->media_mode |= DMFE_AUTO;
         }
         phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id);
 
         /* Restart Auto-Negotiation */
         if (db->chip_type && (db->chip_id == PCI_DM9102_ID))
                 phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id);
         if (!db->chip_type)
                 phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id);
 }

References BASE, dmfe_private::chip_id, dmfe_private::chip_type, dmfe_private::cr6_data, db, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_10MHF, DMFE_AUTO, dmfe_private::media_mode, PCI_DM9009_ID, PCI_DM9102_ID, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, phy_write(), and update_cr6().

◆ dmfe_program_DM9801() [2/2]

static void dmfe_program_DM9801	(	struct nic *nic	__unused,
		int	HPNA_rev
	)

static

Definition at line 1151 of file dmfe.c.

 {
         u32 reg17, reg25;
 
         if (!HPNA_NoiseFloor)
                 HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
         switch (HPNA_rev) {
         case 0xb900:            /* DM9801 E3 */
                 db->HPNA_command |= 0x1000;
                 reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id);
                 reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
                 break;
         case 0xb901:            /* DM9801 E4 */
                 reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
                 break;
         case 0xb902:            /* DM9801 E5 */
         case 0xb903:            /* DM9801 E6 */
         default:
                 db->HPNA_command |= 0x1000;
                 reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
                 break;
         }
         phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
         phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id);
         phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id);
 }

References BASE, dmfe_private::chip_id, db, DM9801_NOISE_FLOOR, dmfe_private::HPNA_command, HPNA_NoiseFloor, dmfe_private::phy_addr, phy_read(), and phy_write().

◆ dmfe_program_DM9802() [2/2]

static void dmfe_program_DM9802 ( struct nic *nic __unused )

static

Definition at line 1190 of file dmfe.c.

 {
         u32 phy_reg;
 
         if (!HPNA_NoiseFloor)
                 HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
         phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
         phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id);
         phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor;
         phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id);
 }

References BASE, dmfe_private::chip_id, db, DM9802_NOISE_FLOOR, dmfe_private::HPNA_command, HPNA_NoiseFloor, dmfe_private::phy_addr, phy_read(), and phy_write().

◆ PCI_DRIVER()

PCI_DRIVER	(	dmfe_driver	,
		dmfe_nics	,
		PCI_NO_CLASS
	)

◆ DRIVER()

DRIVER	(	"DMFE/PCI"	,
		nic_driver	,
		pci_driver	,
		dmfe_driver	,
		dmfe_probe	,
		dmfe_disable
	)

Variable Documentation

◆ dfx

struct dmfe_private dfx

static

Referenced by dmfe_probe().

◆ db

struct dmfe_private* db

static

◆ dmfe_operations

static struct nic_operations dmfe_operations

static

Initial value:

= {
        .connect        = dummy_connect,
        .poll           = dmfe_poll,
        .transmit       = dmfe_transmit,
        .irq            = dmfe_irq,
}

Definition at line 194 of file dmfe.c.

Referenced by dmfe_probe().

◆ dmfe_media_mode

unsigned char dmfe_media_mode = DMFE_AUTO

static

Definition at line 196 of file dmfe.c.

Referenced by dmfe_init_dm910x(), and dmfe_parse_srom().

◆ dmfe_cr6_user_set

u32 dmfe_cr6_user_set

static

Definition at line 197 of file dmfe.c.

Referenced by dmfe_reset().

◆ chkmode

u8 chkmode = 1

static

Definition at line 200 of file dmfe.c.

Referenced by dmfe_reset().

◆ HPNA_mode

u8 HPNA_mode

static

Definition at line 201 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_rx_cmd

u8 HPNA_rx_cmd

static

Definition at line 202 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_tx_cmd

u8 HPNA_tx_cmd

static

Definition at line 203 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ HPNA_NoiseFloor

u8 HPNA_NoiseFloor

static

Definition at line 204 of file dmfe.c.

Referenced by dmfe_program_DM9801(), and dmfe_program_DM9802().

◆ SF_mode

u8 SF_mode

static

Definition at line 205 of file dmfe.c.

Referenced by dmfe_parse_srom().

◆ txd

struct tx_desc txd[TX_DESC_CNT]

Definition at line 213 of file dmfe.c.

◆ txb

unsigned char txb[TX_BUF_ALLOC *TX_DESC_CNT]

Definition at line 215 of file dmfe.c.

◆ rxd

struct rx_desc rxd[RX_DESC_CNT]

Definition at line 216 of file dmfe.c.

◆ rxb

unsigned char rxb[RX_ALLOC_SIZE *RX_DESC_CNT]

Definition at line 218 of file dmfe.c.

◆ __shared

struct { ... } __shared

◆ BASE

long int BASE

static

Definition at line 226 of file dmfe.c.

Referenced by dm9132_id_table(), dmfe_disable(), dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_probe(), dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_set_phyxcer(), dmfe_transmit(), and send_filter_frame().

◆ dmfe_nics

struct pci_device_id dmfe_nics[]

static

Initial value:

= {
        PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
        PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
        PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
        PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0), 
}

Definition at line 1210 of file dmfe.c.

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ dprintf

◆ virt_to_le32desc

◆ le32desc_to_virt

◆ PCI_DM9132_ID

◆ PCI_DM9102_ID

◆ PCI_DM9100_ID

◆ PCI_DM9009_ID

◆ DM9102_IO_SIZE

◆ DM9102A_IO_SIZE

◆ TX_MAX_SEND_CNT

◆ TX_DESC_CNT

◆ RX_DESC_CNT

◆ TX_FREE_DESC_CNT

◆ TX_WAKE_DESC_CNT

◆ DESC_ALL_CNT

◆ TX_BUF_ALLOC

◆ RX_ALLOC_SIZE

◆ DM910X_RESET

◆ CR0_DEFAULT

◆ CR6_DEFAULT

◆ CR7_DEFAULT

◆ CR15_DEFAULT

◆ TDES0_ERR_MASK

◆ MAX_PACKET_SIZE

◆ DMFE_MAX_MULTICAST

◆ RX_COPY_SIZE

◆ MAX_CHECK_PACKET

◆ DM9801_NOISE_FLOOR

◆ DM9802_NOISE_FLOOR

◆ DMFE_10MHF

◆ DMFE_100MHF

◆ DMFE_10MFD

◆ DMFE_100MFD

◆ DMFE_AUTO

◆ DMFE_1M_HPNA

◆ DMFE_TXTH_72

◆ DMFE_TXTH_96

◆ DMFE_TXTH_128

◆ DMFE_TXTH_256

◆ DMFE_TXTH_512

◆ DMFE_TXTH_1K

◆ DMFE_TIMER_WUT

◆ DMFE_TX_TIMEOUT

◆ DMFE_TX_KICK

◆ DMFE_DBUG

◆ SHOW_MEDIA_TYPE

◆ CR9_SROM_READ

◆ CR9_SRCS

◆ CR9_SRCLK

◆ CR9_CRDOUT

◆ SROM_DATA_0

◆ SROM_DATA_1

◆ PHY_DATA_1

◆ PHY_DATA_0

◆ MDCLKH

◆ PHY_POWER_DOWN

◆ SROM_V41_CODE

◆ SROM_CLK_WRITE

◆ __CHK_IO_SIZE

◆ CHK_IO_SIZE

◆ DEVICE

◆ txd

◆ txb

◆ rxd

◆ rxb

◆ board_found

◆ valid_link

Enumeration Type Documentation

◆ dmfe_offsets

◆ dmfe_CR6_bits

Function Documentation

◆ FILE_LICENCE()

◆ read_srom_word()

◆ dmfe_init_dm910x()