iPXE
etherfabric.c
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1 /**************************************************************************
2  *
3  * Etherboot driver for Level 5 Etherfabric network cards
4  *
5  * Written by Michael Brown <mbrown@fensystems.co.uk>
6  *
7  * Copyright Fen Systems Ltd. 2005
8  * Copyright Level 5 Networks Inc. 2005
9  *
10  * This software may be used and distributed according to the terms of
11  * the GNU General Public License (GPL), incorporated herein by
12  * reference. Drivers based on or derived from this code fall under
13  * the GPL and must retain the authorship, copyright and license
14  * notice.
15  *
16  **************************************************************************
17  */
18 
19 FILE_LICENCE ( GPL_ANY );
20 
21 #include <stdint.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <unistd.h>
25 #include <errno.h>
26 #include <assert.h>
27 #include <byteswap.h>
28 #include <ipxe/io.h>
29 #include <ipxe/pci.h>
30 #include <ipxe/malloc.h>
31 #include <ipxe/ethernet.h>
32 #include <ipxe/iobuf.h>
33 #include <ipxe/netdevice.h>
34 #include <ipxe/timer.h>
35 #include <mii.h>
36 #include "etherfabric.h"
37 #include "etherfabric_nic.h"
38 
39 /**************************************************************************
40  *
41  * Constants and macros
42  *
43  **************************************************************************
44  */
45 
46 #define EFAB_REGDUMP(...)
47 #define EFAB_TRACE(...) DBGP(__VA_ARGS__)
48 
49 // printf() is not allowed within drivers. Use DBG() instead.
50 #define EFAB_LOG(...) DBG(__VA_ARGS__)
51 #define EFAB_ERR(...) DBG(__VA_ARGS__)
52 
53 #define FALCON_USE_IO_BAR 0
54 
55 #define HZ 100
56 #define EFAB_BYTE 1
57 
58 /**************************************************************************
59  *
60  * Hardware data structures and sizing
61  *
62  **************************************************************************
63  */
64 extern int __invalid_queue_size;
65 #define FQS(_prefix, _x) \
66  ( ( (_x) == 512 ) ? _prefix ## _SIZE_512 : \
67  ( ( (_x) == 1024 ) ? _prefix ## _SIZE_1K : \
68  ( ( (_x) == 2048 ) ? _prefix ## _SIZE_2K : \
69  ( ( (_x) == 4096) ? _prefix ## _SIZE_4K : \
70  __invalid_queue_size ) ) ) )
71 
72 
73 #define EFAB_MAX_FRAME_LEN(mtu) \
74  ( ( ( ( mtu ) + 4/* FCS */ ) + 7 ) & ~7 )
75 
76 /**************************************************************************
77  *
78  * GMII routines
79  *
80  **************************************************************************
81  */
82 
83 static void falcon_mdio_write (struct efab_nic *efab, int device,
84  int location, int value );
85 static int falcon_mdio_read ( struct efab_nic *efab, int device, int location );
86 
87 /* GMII registers */
88 #define GMII_PSSR 0x11 /* PHY-specific status register */
89 
90 /* Pseudo extensions to the link partner ability register */
91 #define LPA_EF_1000FULL 0x00020000
92 #define LPA_EF_1000HALF 0x00010000
93 #define LPA_EF_10000FULL 0x00040000
94 #define LPA_EF_10000HALF 0x00080000
95 
96 #define LPA_EF_1000 ( LPA_EF_1000FULL | LPA_EF_1000HALF )
97 #define LPA_EF_10000 ( LPA_EF_10000FULL | LPA_EF_10000HALF )
98 #define LPA_EF_DUPLEX ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \
99  LPA_EF_10000FULL )
100 
101 /* Mask of bits not associated with speed or duplexity. */
102 #define LPA_OTHER ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \
103  LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF )
104 
105 /* PHY-specific status register */
106 #define PSSR_LSTATUS 0x0400 /* Bit 10 - link status */
107 
108 /**
109  * Retrieve GMII autonegotiation advertised abilities
110  *
111  */
112 static unsigned int
114 {
115  unsigned int mii_advertise;
116  unsigned int gmii_advertise;
117 
118  /* Extended bits are in bits 8 and 9 of MII_CTRL1000 */
119  mii_advertise = falcon_mdio_read ( efab, 0, MII_ADVERTISE );
120  gmii_advertise = ( ( falcon_mdio_read ( efab, 0, MII_CTRL1000 ) >> 8 )
121  & 0x03 );
122  return ( ( gmii_advertise << 16 ) | mii_advertise );
123 }
124 
125 /**
126  * Retrieve GMII autonegotiation link partner abilities
127  *
128  */
129 static unsigned int
130 gmii_autoneg_lpa ( struct efab_nic *efab )
131 {
132  unsigned int mii_lpa;
133  unsigned int gmii_lpa;
134 
135  /* Extended bits are in bits 10 and 11 of MII_STAT1000 */
136  mii_lpa = falcon_mdio_read ( efab, 0, MII_LPA );
137  gmii_lpa = ( falcon_mdio_read ( efab, 0, MII_STAT1000 ) >> 10 ) & 0x03;
138  return ( ( gmii_lpa << 16 ) | mii_lpa );
139 }
140 
141 /**
142  * Calculate GMII autonegotiated link technology
143  *
144  */
145 static unsigned int
146 gmii_nway_result ( unsigned int negotiated )
147 {
148  unsigned int other_bits;
149 
150  /* Mask out the speed and duplexity bits */
151  other_bits = negotiated & LPA_OTHER;
152 
153  if ( negotiated & LPA_EF_1000FULL )
154  return ( other_bits | LPA_EF_1000FULL );
155  else if ( negotiated & LPA_EF_1000HALF )
156  return ( other_bits | LPA_EF_1000HALF );
157  else if ( negotiated & LPA_100FULL )
158  return ( other_bits | LPA_100FULL );
159  else if ( negotiated & LPA_100BASE4 )
160  return ( other_bits | LPA_100BASE4 );
161  else if ( negotiated & LPA_100HALF )
162  return ( other_bits | LPA_100HALF );
163  else if ( negotiated & LPA_10FULL )
164  return ( other_bits | LPA_10FULL );
165  else return ( other_bits | LPA_10HALF );
166 }
167 
168 /**
169  * Check GMII PHY link status
170  *
171  */
172 static int
173 gmii_link_ok ( struct efab_nic *efab )
174 {
175  int status;
176  int phy_status;
177 
178  /* BMSR is latching - it returns "link down" if the link has
179  * been down at any point since the last read. To get a
180  * real-time status, we therefore read the register twice and
181  * use the result of the second read.
182  */
183  (void) falcon_mdio_read ( efab, 0, MII_BMSR );
184  status = falcon_mdio_read ( efab, 0, MII_BMSR );
185 
186  /* Read the PHY-specific Status Register. This is
187  * non-latching, so we need do only a single read.
188  */
189  phy_status = falcon_mdio_read ( efab, 0, GMII_PSSR );
190 
191  return ( ( status & BMSR_LSTATUS ) && ( phy_status & PSSR_LSTATUS ) );
192 }
193 
194 /**************************************************************************
195  *
196  * MDIO routines
197  *
198  **************************************************************************
199  */
200 
201 /* Numbering of the MDIO Manageable Devices (MMDs) */
202 /* Physical Medium Attachment/ Physical Medium Dependent sublayer */
203 #define MDIO_MMD_PMAPMD (1)
204 /* WAN Interface Sublayer */
205 #define MDIO_MMD_WIS (2)
206 /* Physical Coding Sublayer */
207 #define MDIO_MMD_PCS (3)
208 /* PHY Extender Sublayer */
209 #define MDIO_MMD_PHYXS (4)
210 /* Extender Sublayer */
211 #define MDIO_MMD_DTEXS (5)
212 /* Transmission convergence */
213 #define MDIO_MMD_TC (6)
214 /* Auto negotiation */
215 #define MDIO_MMD_AN (7)
216 
217 /* Generic register locations */
218 #define MDIO_MMDREG_CTRL1 (0)
219 #define MDIO_MMDREG_STAT1 (1)
220 #define MDIO_MMDREG_DEVS0 (5)
221 #define MDIO_MMDREG_STAT2 (8)
222 
223 /* Bits in MMDREG_CTRL1 */
224 /* Reset */
225 #define MDIO_MMDREG_CTRL1_RESET_LBN (15)
226 #define MDIO_MMDREG_CTRL1_RESET_WIDTH (1)
227 
228 /* Bits in MMDREG_STAT1 */
229 #define MDIO_MMDREG_STAT1_FAULT_LBN (7)
230 #define MDIO_MMDREG_STAT1_FAULT_WIDTH (1)
231 
232 /* Link state */
233 #define MDIO_MMDREG_STAT1_LINK_LBN (2)
234 #define MDIO_MMDREG_STAT1_LINK_WIDTH (1)
235 
236 /* Bits in MMDREG_DEVS0. */
237 #define DEV_PRESENT_BIT(_b) (1 << _b)
238 
239 #define MDIO_MMDREG_DEVS0_DTEXS DEV_PRESENT_BIT(MDIO_MMD_DTEXS)
240 #define MDIO_MMDREG_DEVS0_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
241 #define MDIO_MMDREG_DEVS0_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS)
242 #define MDIO_MMDREG_DEVS0_WIS DEV_PRESENT_BIT(MDIO_MMD_WIS)
243 #define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
244 
245 #define MDIO_MMDREG_DEVS0_AN DEV_PRESENT_BIT(MDIO_MMD_AN)
246 
247 /* Bits in MMDREG_STAT2 */
248 #define MDIO_MMDREG_STAT2_PRESENT_VAL (2)
249 #define MDIO_MMDREG_STAT2_PRESENT_LBN (14)
250 #define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
251 
252 /* PHY XGXS lane state */
253 #define MDIO_PHYXS_LANE_STATE (0x18)
254 #define MDIO_PHYXS_LANE_ALIGNED_LBN (12)
255 #define MDIO_PHYXS_LANE_SYNC0_LBN (0)
256 #define MDIO_PHYXS_LANE_SYNC1_LBN (1)
257 #define MDIO_PHYXS_LANE_SYNC2_LBN (2)
258 #define MDIO_PHYXS_LANE_SYNC3_LBN (3)
259 
260 /* This ought to be ridiculous overkill. We expect it to fail rarely */
261 #define MDIO45_RESET_TRIES 100
262 #define MDIO45_RESET_SPINTIME 10
263 
264 static int
266 {
267  int tries = MDIO45_RESET_TRIES;
268  int in_reset;
269 
270  while(tries) {
271  int mask = efab->phy_op->mmds;
272  int mmd = 0;
273  in_reset = 0;
274  while(mask) {
275  if (mask & 1) {
276  int stat = falcon_mdio_read ( efab, mmd,
278  if (stat < 0) {
279  EFAB_ERR("Failed to read status of MMD %d\n",
280  mmd );
281  in_reset = 1;
282  break;
283  }
284  if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
285  in_reset |= (1 << mmd);
286  }
287  mask = mask >> 1;
288  mmd++;
289  }
290  if (!in_reset)
291  break;
292  tries--;
294  }
295  if (in_reset != 0) {
296  EFAB_ERR("Not all MMDs came out of reset in time. MMDs "
297  "still in reset: %x\n", in_reset);
298  return -ETIMEDOUT;
299  }
300  return 0;
301 }
302 
303 static int
304 mdio_clause45_reset_mmd ( struct efab_nic *efab, int mmd )
305 {
306  int tries = MDIO45_RESET_TRIES;
307  int ctrl;
308 
310  ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) );
311 
312  /* Wait for the reset bit to clear. */
313  do {
315 
316  ctrl = falcon_mdio_read ( efab, mmd, MDIO_MMDREG_CTRL1 );
317  if ( ~ctrl & ( 1 << MDIO_MMDREG_CTRL1_RESET_LBN ) )
318  return 0;
319  } while ( --tries );
320 
321  EFAB_ERR ( "Failed to reset mmd %d\n", mmd );
322 
323  return -ETIMEDOUT;
324 }
325 
326 static int
328 {
329  int status, good;
330  int ok = 1;
331  int mmd = 0;
332  int mmd_mask = efab->phy_op->mmds;
333 
334  while (mmd_mask) {
335  if (mmd_mask & 1) {
336  /* Double reads because link state is latched, and a
337  * read moves the current state into the register */
338  status = falcon_mdio_read ( efab, mmd,
340  status = falcon_mdio_read ( efab, mmd,
342 
343  good = status & (1 << MDIO_MMDREG_STAT1_LINK_LBN);
344  ok = ok && good;
345  }
346  mmd_mask = (mmd_mask >> 1);
347  mmd++;
348  }
349  return ok;
350 }
351 
352 static int
354 {
355  int mmd = 0;
356  int devices = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
358  int mmd_mask = efab->phy_op->mmds;
359 
360  /* Check all the expected MMDs are present */
361  if ( devices < 0 ) {
362  EFAB_ERR ( "Failed to read devices present\n" );
363  return -EIO;
364  }
365  if ( ( devices & mmd_mask ) != mmd_mask ) {
366  EFAB_ERR ( "required MMDs not present: got %x, wanted %x\n",
367  devices, mmd_mask );
368  return -EIO;
369  }
370 
371  /* Check all required MMDs are responding and happy. */
372  while ( mmd_mask ) {
373  if ( mmd_mask & 1 ) {
375  int status;
376  reg.opaque = falcon_mdio_read ( efab, mmd,
379  MDIO_MMDREG_STAT2_PRESENT );
381 
382 
383  return -EIO;
384  }
385  }
386  mmd_mask >>= 1;
387  mmd++;
388  }
389 
390  return 0;
391 }
392 
393 /* I/O BAR address register */
394 #define FCN_IOM_IND_ADR_REG 0x0
395 
396 /* I/O BAR data register */
397 #define FCN_IOM_IND_DAT_REG 0x4
398 
399 /* Address region register */
400 #define FCN_ADR_REGION_REG_KER 0x00
401 #define FCN_ADR_REGION0_LBN 0
402 #define FCN_ADR_REGION0_WIDTH 18
403 #define FCN_ADR_REGION1_LBN 32
404 #define FCN_ADR_REGION1_WIDTH 18
405 #define FCN_ADR_REGION2_LBN 64
406 #define FCN_ADR_REGION2_WIDTH 18
407 #define FCN_ADR_REGION3_LBN 96
408 #define FCN_ADR_REGION3_WIDTH 18
409 
410 /* Interrupt enable register */
411 #define FCN_INT_EN_REG_KER 0x0010
412 #define FCN_MEM_PERR_INT_EN_KER_LBN 5
413 #define FCN_MEM_PERR_INT_EN_KER_WIDTH 1
414 #define FCN_KER_INT_CHAR_LBN 4
415 #define FCN_KER_INT_CHAR_WIDTH 1
416 #define FCN_KER_INT_KER_LBN 3
417 #define FCN_KER_INT_KER_WIDTH 1
418 #define FCN_ILL_ADR_ERR_INT_EN_KER_LBN 2
419 #define FCN_ILL_ADR_ERR_INT_EN_KER_WIDTH 1
420 #define FCN_SRM_PERR_INT_EN_KER_LBN 1
421 #define FCN_SRM_PERR_INT_EN_KER_WIDTH 1
422 #define FCN_DRV_INT_EN_KER_LBN 0
423 #define FCN_DRV_INT_EN_KER_WIDTH 1
424 
425 /* Interrupt status register */
426 #define FCN_INT_ADR_REG_KER 0x0030
427 #define FCN_INT_ADR_KER_LBN 0
428 #define FCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 )
429 
430 /* Interrupt status register (B0 only) */
431 #define INT_ISR0_B0 0x90
432 #define INT_ISR1_B0 0xA0
433 
434 /* Interrupt acknowledge register (A0/A1 only) */
435 #define FCN_INT_ACK_KER_REG_A1 0x0050
436 #define INT_ACK_DUMMY_DATA_LBN 0
437 #define INT_ACK_DUMMY_DATA_WIDTH 32
438 
439 /* Interrupt acknowledge work-around register (A0/A1 only )*/
440 #define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070
441 
442 /* Hardware initialisation register */
443 #define FCN_HW_INIT_REG_KER 0x00c0
444 #define FCN_BCSR_TARGET_MASK_LBN 101
445 #define FCN_BCSR_TARGET_MASK_WIDTH 4
446 
447 /* SPI host command register */
448 #define FCN_EE_SPI_HCMD_REG 0x0100
449 #define FCN_EE_SPI_HCMD_CMD_EN_LBN 31
450 #define FCN_EE_SPI_HCMD_CMD_EN_WIDTH 1
451 #define FCN_EE_WR_TIMER_ACTIVE_LBN 28
452 #define FCN_EE_WR_TIMER_ACTIVE_WIDTH 1
453 #define FCN_EE_SPI_HCMD_SF_SEL_LBN 24
454 #define FCN_EE_SPI_HCMD_SF_SEL_WIDTH 1
455 #define FCN_EE_SPI_EEPROM 0
456 #define FCN_EE_SPI_FLASH 1
457 #define FCN_EE_SPI_HCMD_DABCNT_LBN 16
458 #define FCN_EE_SPI_HCMD_DABCNT_WIDTH 5
459 #define FCN_EE_SPI_HCMD_READ_LBN 15
460 #define FCN_EE_SPI_HCMD_READ_WIDTH 1
461 #define FCN_EE_SPI_READ 1
462 #define FCN_EE_SPI_WRITE 0
463 #define FCN_EE_SPI_HCMD_DUBCNT_LBN 12
464 #define FCN_EE_SPI_HCMD_DUBCNT_WIDTH 2
465 #define FCN_EE_SPI_HCMD_ADBCNT_LBN 8
466 #define FCN_EE_SPI_HCMD_ADBCNT_WIDTH 2
467 #define FCN_EE_SPI_HCMD_ENC_LBN 0
468 #define FCN_EE_SPI_HCMD_ENC_WIDTH 8
469 
470 /* SPI host address register */
471 #define FCN_EE_SPI_HADR_REG 0x0110
472 #define FCN_EE_SPI_HADR_DUBYTE_LBN 24
473 #define FCN_EE_SPI_HADR_DUBYTE_WIDTH 8
474 #define FCN_EE_SPI_HADR_ADR_LBN 0
475 #define FCN_EE_SPI_HADR_ADR_WIDTH 24
476 
477 /* SPI host data register */
478 #define FCN_EE_SPI_HDATA_REG 0x0120
479 #define FCN_EE_SPI_HDATA3_LBN 96
480 #define FCN_EE_SPI_HDATA3_WIDTH 32
481 #define FCN_EE_SPI_HDATA2_LBN 64
482 #define FCN_EE_SPI_HDATA2_WIDTH 32
483 #define FCN_EE_SPI_HDATA1_LBN 32
484 #define FCN_EE_SPI_HDATA1_WIDTH 32
485 #define FCN_EE_SPI_HDATA0_LBN 0
486 #define FCN_EE_SPI_HDATA0_WIDTH 32
487 
488 /* VPD Config 0 Register register */
489 #define FCN_EE_VPD_CFG_REG 0x0140
490 #define FCN_EE_VPD_EN_LBN 0
491 #define FCN_EE_VPD_EN_WIDTH 1
492 #define FCN_EE_VPD_EN_AD9_MODE_LBN 1
493 #define FCN_EE_VPD_EN_AD9_MODE_WIDTH 1
494 #define FCN_EE_EE_CLOCK_DIV_LBN 112
495 #define FCN_EE_EE_CLOCK_DIV_WIDTH 7
496 #define FCN_EE_SF_CLOCK_DIV_LBN 120
497 #define FCN_EE_SF_CLOCK_DIV_WIDTH 7
498 
499 
500 /* NIC status register */
501 #define FCN_NIC_STAT_REG 0x0200
502 #define FCN_ONCHIP_SRAM_LBN 16
503 #define FCN_ONCHIP_SRAM_WIDTH 1
504 #define FCN_SF_PRST_LBN 9
505 #define FCN_SF_PRST_WIDTH 1
506 #define FCN_EE_PRST_LBN 8
507 #define FCN_EE_PRST_WIDTH 1
508 #define FCN_EE_STRAP_LBN 7
509 #define FCN_EE_STRAP_WIDTH 1
510 #define FCN_PCI_PCIX_MODE_LBN 4
511 #define FCN_PCI_PCIX_MODE_WIDTH 3
512 #define FCN_PCI_PCIX_MODE_PCI33_DECODE 0
513 #define FCN_PCI_PCIX_MODE_PCI66_DECODE 1
514 #define FCN_PCI_PCIX_MODE_PCIX66_DECODE 5
515 #define FCN_PCI_PCIX_MODE_PCIX100_DECODE 6
516 #define FCN_PCI_PCIX_MODE_PCIX133_DECODE 7
517 #define FCN_STRAP_ISCSI_EN_LBN 3
518 #define FCN_STRAP_ISCSI_EN_WIDTH 1
519 #define FCN_STRAP_PINS_LBN 0
520 #define FCN_STRAP_PINS_WIDTH 3
521 #define FCN_STRAP_10G_LBN 2
522 #define FCN_STRAP_10G_WIDTH 1
523 #define FCN_STRAP_DUAL_PORT_LBN 1
524 #define FCN_STRAP_DUAL_PORT_WIDTH 1
525 #define FCN_STRAP_PCIE_LBN 0
526 #define FCN_STRAP_PCIE_WIDTH 1
527 
528 /* Falcon revisions */
529 #define FALCON_REV_A0 0
530 #define FALCON_REV_A1 1
531 #define FALCON_REV_B0 2
532 
533 /* GPIO control register */
534 #define FCN_GPIO_CTL_REG_KER 0x0210
535 #define FCN_GPIO_CTL_REG_KER 0x0210
536 
537 #define FCN_GPIO3_OEN_LBN 27
538 #define FCN_GPIO3_OEN_WIDTH 1
539 #define FCN_GPIO2_OEN_LBN 26
540 #define FCN_GPIO2_OEN_WIDTH 1
541 #define FCN_GPIO1_OEN_LBN 25
542 #define FCN_GPIO1_OEN_WIDTH 1
543 #define FCN_GPIO0_OEN_LBN 24
544 #define FCN_GPIO0_OEN_WIDTH 1
545 
546 #define FCN_GPIO3_OUT_LBN 19
547 #define FCN_GPIO3_OUT_WIDTH 1
548 #define FCN_GPIO2_OUT_LBN 18
549 #define FCN_GPIO2_OUT_WIDTH 1
550 #define FCN_GPIO1_OUT_LBN 17
551 #define FCN_GPIO1_OUT_WIDTH 1
552 #define FCN_GPIO0_OUT_LBN 16
553 #define FCN_GPIO0_OUT_WIDTH 1
554 
555 #define FCN_GPIO3_IN_LBN 11
556 #define FCN_GPIO3_IN_WIDTH 1
557 #define FCN_GPIO2_IN_LBN 10
558 #define FCN_GPIO2_IN_WIDTH 1
559 #define FCN_GPIO1_IN_LBN 9
560 #define FCN_GPIO1_IN_WIDTH 1
561 #define FCN_GPIO0_IN_LBN 8
562 #define FCN_GPIO0_IN_WIDTH 1
563 
564 #define FCN_FLASH_PRESENT_LBN 7
565 #define FCN_FLASH_PRESENT_WIDTH 1
566 #define FCN_EEPROM_PRESENT_LBN 6
567 #define FCN_EEPROM_PRESENT_WIDTH 1
568 #define FCN_BOOTED_USING_NVDEVICE_LBN 3
569 #define FCN_BOOTED_USING_NVDEVICE_WIDTH 1
570 
571 /* Defines for extra non-volatile storage */
572 #define FCN_NV_MAGIC_NUMBER 0xFA1C
573 
574 /* Global control register */
575 #define FCN_GLB_CTL_REG_KER 0x0220
576 #define FCN_EXT_PHY_RST_CTL_LBN 63
577 #define FCN_EXT_PHY_RST_CTL_WIDTH 1
578 #define FCN_PCIE_SD_RST_CTL_LBN 61
579 #define FCN_PCIE_SD_RST_CTL_WIDTH 1
580 #define FCN_PCIE_STCK_RST_CTL_LBN 59
581 #define FCN_PCIE_STCK_RST_CTL_WIDTH 1
582 #define FCN_PCIE_NSTCK_RST_CTL_LBN 58
583 #define FCN_PCIE_NSTCK_RST_CTL_WIDTH 1
584 #define FCN_PCIE_CORE_RST_CTL_LBN 57
585 #define FCN_PCIE_CORE_RST_CTL_WIDTH 1
586 #define FCN_EE_RST_CTL_LBN 49
587 #define FCN_EE_RST_CTL_WIDTH 1
588 #define FCN_RST_EXT_PHY_LBN 31
589 #define FCN_RST_EXT_PHY_WIDTH 1
590 #define FCN_EXT_PHY_RST_DUR_LBN 1
591 #define FCN_EXT_PHY_RST_DUR_WIDTH 3
592 #define FCN_SWRST_LBN 0
593 #define FCN_SWRST_WIDTH 1
594 #define INCLUDE_IN_RESET 0
595 #define EXCLUDE_FROM_RESET 1
596 
597 /* FPGA build version */
598 #define FCN_ALTERA_BUILD_REG_KER 0x0300
599 #define FCN_VER_MAJOR_LBN 24
600 #define FCN_VER_MAJOR_WIDTH 8
601 #define FCN_VER_MINOR_LBN 16
602 #define FCN_VER_MINOR_WIDTH 8
603 #define FCN_VER_BUILD_LBN 0
604 #define FCN_VER_BUILD_WIDTH 16
605 #define FCN_VER_ALL_LBN 0
606 #define FCN_VER_ALL_WIDTH 32
607 
608 /* Spare EEPROM bits register (flash 0x390) */
609 #define FCN_SPARE_REG_KER 0x310
610 #define FCN_MEM_PERR_EN_TX_DATA_LBN 72
611 #define FCN_MEM_PERR_EN_TX_DATA_WIDTH 2
612 
613 /* Timer table for kernel access */
614 #define FCN_TIMER_CMD_REG_KER 0x420
615 #define FCN_TIMER_MODE_LBN 12
616 #define FCN_TIMER_MODE_WIDTH 2
617 #define FCN_TIMER_MODE_DIS 0
618 #define FCN_TIMER_MODE_INT_HLDOFF 1
619 #define FCN_TIMER_VAL_LBN 0
620 #define FCN_TIMER_VAL_WIDTH 12
621 
622 /* Receive configuration register */
623 #define FCN_RX_CFG_REG_KER 0x800
624 #define FCN_RX_XOFF_EN_LBN 0
625 #define FCN_RX_XOFF_EN_WIDTH 1
626 
627 /* SRAM receive descriptor cache configuration register */
628 #define FCN_SRM_RX_DC_CFG_REG_KER 0x610
629 #define FCN_SRM_RX_DC_BASE_ADR_LBN 0
630 #define FCN_SRM_RX_DC_BASE_ADR_WIDTH 21
631 
632 /* SRAM transmit descriptor cache configuration register */
633 #define FCN_SRM_TX_DC_CFG_REG_KER 0x620
634 #define FCN_SRM_TX_DC_BASE_ADR_LBN 0
635 #define FCN_SRM_TX_DC_BASE_ADR_WIDTH 21
636 
637 /* SRAM configuration register */
638 #define FCN_SRM_CFG_REG_KER 0x630
639 #define FCN_SRAM_OOB_ADR_INTEN_LBN 5
640 #define FCN_SRAM_OOB_ADR_INTEN_WIDTH 1
641 #define FCN_SRAM_OOB_BUF_INTEN_LBN 4
642 #define FCN_SRAM_OOB_BUF_INTEN_WIDTH 1
643 #define FCN_SRAM_OOB_BT_INIT_EN_LBN 3
644 #define FCN_SRAM_OOB_BT_INIT_EN_WIDTH 1
645 #define FCN_SRM_NUM_BANK_LBN 2
646 #define FCN_SRM_NUM_BANK_WIDTH 1
647 #define FCN_SRM_BANK_SIZE_LBN 0
648 #define FCN_SRM_BANK_SIZE_WIDTH 2
649 #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0
650 #define FCN_SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3
651 
652 #define FCN_RX_CFG_REG_KER 0x800
653 #define FCN_RX_INGR_EN_B0_LBN 47
654 #define FCN_RX_INGR_EN_B0_WIDTH 1
655 #define FCN_RX_USR_BUF_SIZE_B0_LBN 19
656 #define FCN_RX_USR_BUF_SIZE_B0_WIDTH 9
657 #define FCN_RX_XON_MAC_TH_B0_LBN 10
658 #define FCN_RX_XON_MAC_TH_B0_WIDTH 9
659 #define FCN_RX_XOFF_MAC_TH_B0_LBN 1
660 #define FCN_RX_XOFF_MAC_TH_B0_WIDTH 9
661 #define FCN_RX_XOFF_MAC_EN_B0_LBN 0
662 #define FCN_RX_XOFF_MAC_EN_B0_WIDTH 1
663 #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
664 #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
665 #define FCN_RX_XON_MAC_TH_A1_LBN 6
666 #define FCN_RX_XON_MAC_TH_A1_WIDTH 5
667 #define FCN_RX_XOFF_MAC_TH_A1_LBN 1
668 #define FCN_RX_XOFF_MAC_TH_A1_WIDTH 5
669 #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
670 #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
671 
672 #define FCN_RX_USR_BUF_SIZE_A1_LBN 11
673 #define FCN_RX_USR_BUF_SIZE_A1_WIDTH 9
674 #define FCN_RX_XOFF_MAC_EN_A1_LBN 0
675 #define FCN_RX_XOFF_MAC_EN_A1_WIDTH 1
676 
677 /* Receive filter control register */
678 #define FCN_RX_FILTER_CTL_REG_KER 0x810
679 #define FCN_UDP_FULL_SRCH_LIMIT_LBN 32
680 #define FCN_UDP_FULL_SRCH_LIMIT_WIDTH 8
681 #define FCN_NUM_KER_LBN 24
682 #define FCN_NUM_KER_WIDTH 2
683 #define FCN_UDP_WILD_SRCH_LIMIT_LBN 16
684 #define FCN_UDP_WILD_SRCH_LIMIT_WIDTH 8
685 #define FCN_TCP_WILD_SRCH_LIMIT_LBN 8
686 #define FCN_TCP_WILD_SRCH_LIMIT_WIDTH 8
687 #define FCN_TCP_FULL_SRCH_LIMIT_LBN 0
688 #define FCN_TCP_FULL_SRCH_LIMIT_WIDTH 8
689 
690 /* RX queue flush register */
691 #define FCN_RX_FLUSH_DESCQ_REG_KER 0x0820
692 #define FCN_RX_FLUSH_DESCQ_CMD_LBN 24
693 #define FCN_RX_FLUSH_DESCQ_CMD_WIDTH 1
694 #define FCN_RX_FLUSH_DESCQ_LBN 0
695 #define FCN_RX_FLUSH_DESCQ_WIDTH 12
696 
697 /* Receive descriptor update register */
698 #define FCN_RX_DESC_UPD_REG_KER 0x0830
699 #define FCN_RX_DESC_WPTR_LBN 96
700 #define FCN_RX_DESC_WPTR_WIDTH 12
701 #define FCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 )
702 #define FCN_RX_DESC_WPTR_DWORD_LBN 0
703 #define FCN_RX_DESC_WPTR_DWORD_WIDTH 12
704 
705 /* Receive descriptor cache configuration register */
706 #define FCN_RX_DC_CFG_REG_KER 0x840
707 #define FCN_RX_DC_SIZE_LBN 0
708 #define FCN_RX_DC_SIZE_WIDTH 2
709 
710 #define FCN_RX_SELF_RST_REG_KER 0x890
711 #define FCN_RX_ISCSI_DIS_LBN 17
712 #define FCN_RX_ISCSI_DIS_WIDTH 1
713 #define FCN_RX_NODESC_WAIT_DIS_LBN 9
714 #define FCN_RX_NODESC_WAIT_DIS_WIDTH 1
715 #define FCN_RX_RECOVERY_EN_LBN 8
716 #define FCN_RX_RECOVERY_EN_WIDTH 1
717 
718 /* TX queue flush register */
719 #define FCN_TX_FLUSH_DESCQ_REG_KER 0x0a00
720 #define FCN_TX_FLUSH_DESCQ_CMD_LBN 12
721 #define FCN_TX_FLUSH_DESCQ_CMD_WIDTH 1
722 #define FCN_TX_FLUSH_DESCQ_LBN 0
723 #define FCN_TX_FLUSH_DESCQ_WIDTH 12
724 
725 /* Transmit configuration register 2 */
726 #define FCN_TX_CFG2_REG_KER 0xa80
727 #define FCN_TX_DIS_NON_IP_EV_LBN 17
728 #define FCN_TX_DIS_NON_IP_EV_WIDTH 1
729 
730 /* Transmit descriptor update register */
731 #define FCN_TX_DESC_UPD_REG_KER 0x0a10
732 #define FCN_TX_DESC_WPTR_LBN 96
733 #define FCN_TX_DESC_WPTR_WIDTH 12
734 #define FCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 )
735 #define FCN_TX_DESC_WPTR_DWORD_LBN 0
736 #define FCN_TX_DESC_WPTR_DWORD_WIDTH 12
737 
738 /* Transmit descriptor cache configuration register */
739 #define FCN_TX_DC_CFG_REG_KER 0xa20
740 #define FCN_TX_DC_SIZE_LBN 0
741 #define FCN_TX_DC_SIZE_WIDTH 2
742 
743 /* PHY management transmit data register */
744 #define FCN_MD_TXD_REG_KER 0xc00
745 #define FCN_MD_TXD_LBN 0
746 #define FCN_MD_TXD_WIDTH 16
747 
748 /* PHY management receive data register */
749 #define FCN_MD_RXD_REG_KER 0xc10
750 #define FCN_MD_RXD_LBN 0
751 #define FCN_MD_RXD_WIDTH 16
752 
753 /* PHY management configuration & status register */
754 #define FCN_MD_CS_REG_KER 0xc20
755 #define FCN_MD_GC_LBN 4
756 #define FCN_MD_GC_WIDTH 1
757 #define FCN_MD_RIC_LBN 2
758 #define FCN_MD_RIC_WIDTH 1
759 #define FCN_MD_RDC_LBN 1
760 #define FCN_MD_RDC_WIDTH 1
761 #define FCN_MD_WRC_LBN 0
762 #define FCN_MD_WRC_WIDTH 1
763 
764 /* PHY management PHY address register */
765 #define FCN_MD_PHY_ADR_REG_KER 0xc30
766 #define FCN_MD_PHY_ADR_LBN 0
767 #define FCN_MD_PHY_ADR_WIDTH 16
768 
769 /* PHY management ID register */
770 #define FCN_MD_ID_REG_KER 0xc40
771 #define FCN_MD_PRT_ADR_LBN 11
772 #define FCN_MD_PRT_ADR_WIDTH 5
773 #define FCN_MD_DEV_ADR_LBN 6
774 #define FCN_MD_DEV_ADR_WIDTH 5
775 
776 /* PHY management status & mask register */
777 #define FCN_MD_STAT_REG_KER 0xc50
778 #define FCN_MD_PINT_LBN 4
779 #define FCN_MD_PINT_WIDTH 1
780 #define FCN_MD_DONE_LBN 3
781 #define FCN_MD_DONE_WIDTH 1
782 #define FCN_MD_BSERR_LBN 2
783 #define FCN_MD_BSERR_WIDTH 1
784 #define FCN_MD_LNFL_LBN 1
785 #define FCN_MD_LNFL_WIDTH 1
786 #define FCN_MD_BSY_LBN 0
787 #define FCN_MD_BSY_WIDTH 1
788 
789 /* Port 0 and 1 MAC control registers */
790 #define FCN_MAC0_CTRL_REG_KER 0xc80
791 #define FCN_MAC1_CTRL_REG_KER 0xc90
792 #define FCN_MAC_XOFF_VAL_LBN 16
793 #define FCN_MAC_XOFF_VAL_WIDTH 16
794 #define FCN_MAC_BCAD_ACPT_LBN 4
795 #define FCN_MAC_BCAD_ACPT_WIDTH 1
796 #define FCN_MAC_UC_PROM_LBN 3
797 #define FCN_MAC_UC_PROM_WIDTH 1
798 #define FCN_MAC_LINK_STATUS_LBN 2
799 #define FCN_MAC_LINK_STATUS_WIDTH 1
800 #define FCN_MAC_SPEED_LBN 0
801 #define FCN_MAC_SPEED_WIDTH 2
802 
803 /* 10Gig Xaui XGXS Default Values */
804 #define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */
805 #define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */
806 #define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */
807 
808 /* GMAC registers */
809 #define FALCON_GMAC_REGBANK 0xe00
810 #define FALCON_GMAC_REGBANK_SIZE 0x200
811 #define FALCON_GMAC_REG_SIZE 0x10
812 
813 /* XGMAC registers */
814 #define FALCON_XMAC_REGBANK 0x1200
815 #define FALCON_XMAC_REGBANK_SIZE 0x200
816 #define FALCON_XMAC_REG_SIZE 0x10
817 
818 /* XGMAC address register low */
819 #define FCN_XM_ADR_LO_REG_MAC 0x00
820 #define FCN_XM_ADR_3_LBN 24
821 #define FCN_XM_ADR_3_WIDTH 8
822 #define FCN_XM_ADR_2_LBN 16
823 #define FCN_XM_ADR_2_WIDTH 8
824 #define FCN_XM_ADR_1_LBN 8
825 #define FCN_XM_ADR_1_WIDTH 8
826 #define FCN_XM_ADR_0_LBN 0
827 #define FCN_XM_ADR_0_WIDTH 8
828 
829 /* XGMAC address register high */
830 #define FCN_XM_ADR_HI_REG_MAC 0x01
831 #define FCN_XM_ADR_5_LBN 8
832 #define FCN_XM_ADR_5_WIDTH 8
833 #define FCN_XM_ADR_4_LBN 0
834 #define FCN_XM_ADR_4_WIDTH 8
835 
836 /* XGMAC global configuration - port 0*/
837 #define FCN_XM_GLB_CFG_REG_MAC 0x02
838 #define FCN_XM_RX_STAT_EN_LBN 11
839 #define FCN_XM_RX_STAT_EN_WIDTH 1
840 #define FCN_XM_TX_STAT_EN_LBN 10
841 #define FCN_XM_TX_STAT_EN_WIDTH 1
842 #define FCN_XM_RX_JUMBO_MODE_LBN 6
843 #define FCN_XM_RX_JUMBO_MODE_WIDTH 1
844 #define FCN_XM_CORE_RST_LBN 0
845 #define FCN_XM_CORE_RST_WIDTH 1
846 
847 /* XGMAC transmit configuration - port 0 */
848 #define FCN_XM_TX_CFG_REG_MAC 0x03
849 #define FCN_XM_IPG_LBN 16
850 #define FCN_XM_IPG_WIDTH 4
851 #define FCN_XM_FCNTL_LBN 10
852 #define FCN_XM_FCNTL_WIDTH 1
853 #define FCN_XM_TXCRC_LBN 8
854 #define FCN_XM_TXCRC_WIDTH 1
855 #define FCN_XM_AUTO_PAD_LBN 5
856 #define FCN_XM_AUTO_PAD_WIDTH 1
857 #define FCN_XM_TX_PRMBL_LBN 2
858 #define FCN_XM_TX_PRMBL_WIDTH 1
859 #define FCN_XM_TXEN_LBN 1
860 #define FCN_XM_TXEN_WIDTH 1
861 
862 /* XGMAC receive configuration - port 0 */
863 #define FCN_XM_RX_CFG_REG_MAC 0x04
864 #define FCN_XM_PASS_CRC_ERR_LBN 25
865 #define FCN_XM_PASS_CRC_ERR_WIDTH 1
866 #define FCN_XM_AUTO_DEPAD_LBN 8
867 #define FCN_XM_AUTO_DEPAD_WIDTH 1
868 #define FCN_XM_RXEN_LBN 1
869 #define FCN_XM_RXEN_WIDTH 1
870 
871 /* XGMAC management interrupt mask register */
872 #define FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5
873 #define FCN_XM_MSK_PRMBLE_ERR_LBN 2
874 #define FCN_XM_MSK_PRMBLE_ERR_WIDTH 1
875 #define FCN_XM_MSK_RMTFLT_LBN 1
876 #define FCN_XM_MSK_RMTFLT_WIDTH 1
877 #define FCN_XM_MSK_LCLFLT_LBN 0
878 #define FCN_XM_MSK_LCLFLT_WIDTH 1
879 
880 /* XGMAC flow control register */
881 #define FCN_XM_FC_REG_MAC 0x7
882 #define FCN_XM_PAUSE_TIME_LBN 16
883 #define FCN_XM_PAUSE_TIME_WIDTH 16
884 #define FCN_XM_DIS_FCNTL_LBN 0
885 #define FCN_XM_DIS_FCNTL_WIDTH 1
886 
887 /* XGMAC transmit parameter register */
888 #define FCN_XM_TX_PARAM_REG_MAC 0x0d
889 #define FCN_XM_TX_JUMBO_MODE_LBN 31
890 #define FCN_XM_TX_JUMBO_MODE_WIDTH 1
891 #define FCN_XM_MAX_TX_FRM_SIZE_LBN 16
892 #define FCN_XM_MAX_TX_FRM_SIZE_WIDTH 14
893 #define FCN_XM_ACPT_ALL_MCAST_LBN 11
894 #define FCN_XM_ACPT_ALL_MCAST_WIDTH 1
895 
896 /* XGMAC receive parameter register */
897 #define FCN_XM_RX_PARAM_REG_MAC 0x0e
898 #define FCN_XM_MAX_RX_FRM_SIZE_LBN 0
899 #define FCN_XM_MAX_RX_FRM_SIZE_WIDTH 14
900 
901 /* XGMAC management interrupt status register */
902 #define FCN_XM_MGT_INT_REG_MAC_B0 0x0f
903 #define FCN_XM_PRMBLE_ERR 2
904 #define FCN_XM_PRMBLE_WIDTH 1
905 #define FCN_XM_RMTFLT_LBN 1
906 #define FCN_XM_RMTFLT_WIDTH 1
907 #define FCN_XM_LCLFLT_LBN 0
908 #define FCN_XM_LCLFLT_WIDTH 1
909 
910 /* XAUI XGXS core status register */
911 #define FCN_XX_ALIGN_DONE_LBN 20
912 #define FCN_XX_ALIGN_DONE_WIDTH 1
913 #define FCN_XX_CORE_STAT_REG_MAC 0x16
914 #define FCN_XX_SYNC_STAT_LBN 16
915 #define FCN_XX_SYNC_STAT_WIDTH 4
916 #define FCN_XX_SYNC_STAT_DECODE_SYNCED 0xf
917 #define FCN_XX_COMMA_DET_LBN 12
918 #define FCN_XX_COMMA_DET_WIDTH 4
919 #define FCN_XX_COMMA_DET_RESET 0xf
920 #define FCN_XX_CHARERR_LBN 4
921 #define FCN_XX_CHARERR_WIDTH 4
922 #define FCN_XX_CHARERR_RESET 0xf
923 #define FCN_XX_DISPERR_LBN 0
924 #define FCN_XX_DISPERR_WIDTH 4
925 #define FCN_XX_DISPERR_RESET 0xf
926 
927 /* XGXS/XAUI powerdown/reset register */
928 #define FCN_XX_PWR_RST_REG_MAC 0x10
929 #define FCN_XX_PWRDND_EN_LBN 15
930 #define FCN_XX_PWRDND_EN_WIDTH 1
931 #define FCN_XX_PWRDNC_EN_LBN 14
932 #define FCN_XX_PWRDNC_EN_WIDTH 1
933 #define FCN_XX_PWRDNB_EN_LBN 13
934 #define FCN_XX_PWRDNB_EN_WIDTH 1
935 #define FCN_XX_PWRDNA_EN_LBN 12
936 #define FCN_XX_PWRDNA_EN_WIDTH 1
937 #define FCN_XX_RSTPLLCD_EN_LBN 9
938 #define FCN_XX_RSTPLLCD_EN_WIDTH 1
939 #define FCN_XX_RSTPLLAB_EN_LBN 8
940 #define FCN_XX_RSTPLLAB_EN_WIDTH 1
941 #define FCN_XX_RESETD_EN_LBN 7
942 #define FCN_XX_RESETD_EN_WIDTH 1
943 #define FCN_XX_RESETC_EN_LBN 6
944 #define FCN_XX_RESETC_EN_WIDTH 1
945 #define FCN_XX_RESETB_EN_LBN 5
946 #define FCN_XX_RESETB_EN_WIDTH 1
947 #define FCN_XX_RESETA_EN_LBN 4
948 #define FCN_XX_RESETA_EN_WIDTH 1
949 #define FCN_XX_RSTXGXSRX_EN_LBN 2
950 #define FCN_XX_RSTXGXSRX_EN_WIDTH 1
951 #define FCN_XX_RSTXGXSTX_EN_LBN 1
952 #define FCN_XX_RSTXGXSTX_EN_WIDTH 1
953 #define FCN_XX_RST_XX_EN_LBN 0
954 #define FCN_XX_RST_XX_EN_WIDTH 1
955 
956 
957 /* XGXS/XAUI powerdown/reset control register */
958 #define FCN_XX_SD_CTL_REG_MAC 0x11
959 #define FCN_XX_TERMADJ1_LBN 17
960 #define FCN_XX_TERMADJ1_WIDTH 1
961 #define FCN_XX_TERMADJ0_LBN 16
962 #define FCN_XX_TERMADJ0_WIDTH 1
963 #define FCN_XX_HIDRVD_LBN 15
964 #define FCN_XX_HIDRVD_WIDTH 1
965 #define FCN_XX_LODRVD_LBN 14
966 #define FCN_XX_LODRVD_WIDTH 1
967 #define FCN_XX_HIDRVC_LBN 13
968 #define FCN_XX_HIDRVC_WIDTH 1
969 #define FCN_XX_LODRVC_LBN 12
970 #define FCN_XX_LODRVC_WIDTH 1
971 #define FCN_XX_HIDRVB_LBN 11
972 #define FCN_XX_HIDRVB_WIDTH 1
973 #define FCN_XX_LODRVB_LBN 10
974 #define FCN_XX_LODRVB_WIDTH 1
975 #define FCN_XX_HIDRVA_LBN 9
976 #define FCN_XX_HIDRVA_WIDTH 1
977 #define FCN_XX_LODRVA_LBN 8
978 #define FCN_XX_LODRVA_WIDTH 1
979 #define FCN_XX_LPBKD_LBN 3
980 #define FCN_XX_LPBKD_WIDTH 1
981 #define FCN_XX_LPBKC_LBN 2
982 #define FCN_XX_LPBKC_WIDTH 1
983 #define FCN_XX_LPBKB_LBN 1
984 #define FCN_XX_LPBKB_WIDTH 1
985 #define FCN_XX_LPBKA_LBN 0
986 #define FCN_XX_LPBKA_WIDTH 1
987 
988 #define FCN_XX_TXDRV_CTL_REG_MAC 0x12
989 #define FCN_XX_DEQD_LBN 28
990 #define FCN_XX_DEQD_WIDTH 4
991 #define FCN_XX_DEQC_LBN 24
992 #define FCN_XX_DEQC_WIDTH 4
993 #define FCN_XX_DEQB_LBN 20
994 #define FCN_XX_DEQB_WIDTH 4
995 #define FCN_XX_DEQA_LBN 16
996 #define FCN_XX_DEQA_WIDTH 4
997 #define FCN_XX_DTXD_LBN 12
998 #define FCN_XX_DTXD_WIDTH 4
999 #define FCN_XX_DTXC_LBN 8
1000 #define FCN_XX_DTXC_WIDTH 4
1001 #define FCN_XX_DTXB_LBN 4
1002 #define FCN_XX_DTXB_WIDTH 4
1003 #define FCN_XX_DTXA_LBN 0
1004 #define FCN_XX_DTXA_WIDTH 4
1005 
1006 /* Receive filter table */
1007 #define FCN_RX_FILTER_TBL0 0xF00000
1008 
1009 /* Receive descriptor pointer table */
1010 #define FCN_RX_DESC_PTR_TBL_KER_A1 0x11800
1011 #define FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000
1012 #define FCN_RX_ISCSI_DDIG_EN_LBN 88
1013 #define FCN_RX_ISCSI_DDIG_EN_WIDTH 1
1014 #define FCN_RX_ISCSI_HDIG_EN_LBN 87
1015 #define FCN_RX_ISCSI_HDIG_EN_WIDTH 1
1016 #define FCN_RX_DESCQ_BUF_BASE_ID_LBN 36
1017 #define FCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20
1018 #define FCN_RX_DESCQ_EVQ_ID_LBN 24
1019 #define FCN_RX_DESCQ_EVQ_ID_WIDTH 12
1020 #define FCN_RX_DESCQ_OWNER_ID_LBN 10
1021 #define FCN_RX_DESCQ_OWNER_ID_WIDTH 14
1022 #define FCN_RX_DESCQ_SIZE_LBN 3
1023 #define FCN_RX_DESCQ_SIZE_WIDTH 2
1024 #define FCN_RX_DESCQ_SIZE_4K 3
1025 #define FCN_RX_DESCQ_SIZE_2K 2
1026 #define FCN_RX_DESCQ_SIZE_1K 1
1027 #define FCN_RX_DESCQ_SIZE_512 0
1028 #define FCN_RX_DESCQ_TYPE_LBN 2
1029 #define FCN_RX_DESCQ_TYPE_WIDTH 1
1030 #define FCN_RX_DESCQ_JUMBO_LBN 1
1031 #define FCN_RX_DESCQ_JUMBO_WIDTH 1
1032 #define FCN_RX_DESCQ_EN_LBN 0
1033 #define FCN_RX_DESCQ_EN_WIDTH 1
1034 
1035 /* Transmit descriptor pointer table */
1036 #define FCN_TX_DESC_PTR_TBL_KER_A1 0x11900
1037 #define FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000
1038 #define FCN_TX_NON_IP_DROP_DIS_B0_LBN 91
1039 #define FCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1
1040 #define FCN_TX_DESCQ_EN_LBN 88
1041 #define FCN_TX_DESCQ_EN_WIDTH 1
1042 #define FCN_TX_ISCSI_DDIG_EN_LBN 87
1043 #define FCN_TX_ISCSI_DDIG_EN_WIDTH 1
1044 #define FCN_TX_ISCSI_HDIG_EN_LBN 86
1045 #define FCN_TX_ISCSI_HDIG_EN_WIDTH 1
1046 #define FCN_TX_DESCQ_BUF_BASE_ID_LBN 36
1047 #define FCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20
1048 #define FCN_TX_DESCQ_EVQ_ID_LBN 24
1049 #define FCN_TX_DESCQ_EVQ_ID_WIDTH 12
1050 #define FCN_TX_DESCQ_OWNER_ID_LBN 10
1051 #define FCN_TX_DESCQ_OWNER_ID_WIDTH 14
1052 #define FCN_TX_DESCQ_SIZE_LBN 3
1053 #define FCN_TX_DESCQ_SIZE_WIDTH 2
1054 #define FCN_TX_DESCQ_SIZE_4K 3
1055 #define FCN_TX_DESCQ_SIZE_2K 2
1056 #define FCN_TX_DESCQ_SIZE_1K 1
1057 #define FCN_TX_DESCQ_SIZE_512 0
1058 #define FCN_TX_DESCQ_TYPE_LBN 1
1059 #define FCN_TX_DESCQ_TYPE_WIDTH 2
1060 #define FCN_TX_DESCQ_FLUSH_LBN 0
1061 #define FCN_TX_DESCQ_FLUSH_WIDTH 1
1062 
1063 /* Event queue pointer */
1064 #define FCN_EVQ_PTR_TBL_KER_A1 0x11a00
1065 #define FCN_EVQ_PTR_TBL_KER_B0 0xf60000
1066 #define FCN_EVQ_EN_LBN 23
1067 #define FCN_EVQ_EN_WIDTH 1
1068 #define FCN_EVQ_SIZE_LBN 20
1069 #define FCN_EVQ_SIZE_WIDTH 3
1070 #define FCN_EVQ_SIZE_32K 6
1071 #define FCN_EVQ_SIZE_16K 5
1072 #define FCN_EVQ_SIZE_8K 4
1073 #define FCN_EVQ_SIZE_4K 3
1074 #define FCN_EVQ_SIZE_2K 2
1075 #define FCN_EVQ_SIZE_1K 1
1076 #define FCN_EVQ_SIZE_512 0
1077 #define FCN_EVQ_BUF_BASE_ID_LBN 0
1078 #define FCN_EVQ_BUF_BASE_ID_WIDTH 20
1079 
1080 /* RSS indirection table */
1081 #define FCN_RX_RSS_INDIR_TBL_B0 0xFB0000
1082 
1083 /* Event queue read pointer */
1084 #define FCN_EVQ_RPTR_REG_KER_A1 0x11b00
1085 #define FCN_EVQ_RPTR_REG_KER_B0 0xfa0000
1086 #define FCN_EVQ_RPTR_LBN 0
1087 #define FCN_EVQ_RPTR_WIDTH 14
1088 #define FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 )
1089 #define FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 )
1090 #define FCN_EVQ_RPTR_DWORD_LBN 0
1091 #define FCN_EVQ_RPTR_DWORD_WIDTH 14
1092 
1093 /* Special buffer descriptors */
1094 #define FCN_BUF_FULL_TBL_KER_A1 0x18000
1095 #define FCN_BUF_FULL_TBL_KER_B0 0x800000
1096 #define FCN_IP_DAT_BUF_SIZE_LBN 50
1097 #define FCN_IP_DAT_BUF_SIZE_WIDTH 1
1098 #define FCN_IP_DAT_BUF_SIZE_8K 1
1099 #define FCN_IP_DAT_BUF_SIZE_4K 0
1100 #define FCN_BUF_ADR_FBUF_LBN 14
1101 #define FCN_BUF_ADR_FBUF_WIDTH 34
1102 #define FCN_BUF_OWNER_ID_FBUF_LBN 0
1103 #define FCN_BUF_OWNER_ID_FBUF_WIDTH 14
1104 
1105 /** Offset of a GMAC register within Falcon */
1106 #define FALCON_GMAC_REG( efab, mac_reg ) \
1107  ( FALCON_GMAC_REGBANK + \
1108  ( (mac_reg) * FALCON_GMAC_REG_SIZE ) )
1109 
1110 /** Offset of an XMAC register within Falcon */
1111 #define FALCON_XMAC_REG( efab_port, mac_reg ) \
1112  ( FALCON_XMAC_REGBANK + \
1113  ( (mac_reg) * FALCON_XMAC_REG_SIZE ) )
1114 
1115 #define FCN_MAC_DATA_LBN 0
1116 #define FCN_MAC_DATA_WIDTH 32
1117 
1118 /* Transmit descriptor */
1119 #define FCN_TX_KER_PORT_LBN 63
1120 #define FCN_TX_KER_PORT_WIDTH 1
1121 #define FCN_TX_KER_BYTE_CNT_LBN 48
1122 #define FCN_TX_KER_BYTE_CNT_WIDTH 14
1123 #define FCN_TX_KER_BUF_ADR_LBN 0
1124 #define FCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
1125 
1126 
1127 /* Receive descriptor */
1128 #define FCN_RX_KER_BUF_SIZE_LBN 48
1129 #define FCN_RX_KER_BUF_SIZE_WIDTH 14
1130 #define FCN_RX_KER_BUF_ADR_LBN 0
1131 #define FCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 )
1132 
1133 /* Event queue entries */
1134 #define FCN_EV_CODE_LBN 60
1135 #define FCN_EV_CODE_WIDTH 4
1136 #define FCN_RX_IP_EV_DECODE 0
1137 #define FCN_TX_IP_EV_DECODE 2
1138 #define FCN_DRIVER_EV_DECODE 5
1139 
1140 /* Receive events */
1141 #define FCN_RX_EV_PKT_OK_LBN 56
1142 #define FCN_RX_EV_PKT_OK_WIDTH 1
1143 #define FCN_RX_PORT_LBN 30
1144 #define FCN_RX_PORT_WIDTH 1
1145 #define FCN_RX_EV_BYTE_CNT_LBN 16
1146 #define FCN_RX_EV_BYTE_CNT_WIDTH 14
1147 #define FCN_RX_EV_DESC_PTR_LBN 0
1148 #define FCN_RX_EV_DESC_PTR_WIDTH 12
1149 
1150 /* Transmit events */
1151 #define FCN_TX_EV_DESC_PTR_LBN 0
1152 #define FCN_TX_EV_DESC_PTR_WIDTH 12
1153 
1154 /*******************************************************************************
1155  *
1156  *
1157  * Low-level hardware access
1158  *
1159  *
1160  *******************************************************************************/
1161 
1162 #define FCN_REVISION_REG(efab, reg) \
1163  ( ( efab->pci_revision == FALCON_REV_B0 ) ? reg ## _B0 : reg ## _A1 )
1164 
1165 #define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val) \
1166  if ( efab->pci_revision == FALCON_REV_B0 ) \
1167  EFAB_SET_OWORD_FIELD ( reg, field ## _B0, val ); \
1168  else \
1169  EFAB_SET_OWORD_FIELD ( reg, field ## _A1, val );
1170 
1171 #if FALCON_USE_IO_BAR
1172 
1173 /* Write dword via the I/O BAR */
1174 static inline void _falcon_writel ( struct efab_nic *efab, uint32_t value,
1175  unsigned int reg ) {
1176  outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
1177  outl ( value, efab->iobase + FCN_IOM_IND_DAT_REG );
1178 }
1179 
1180 /* Read dword via the I/O BAR */
1181 static inline uint32_t _falcon_readl ( struct efab_nic *efab,
1182  unsigned int reg ) {
1183  outl ( reg, efab->iobase + FCN_IOM_IND_ADR_REG );
1184  return inl ( efab->iobase + FCN_IOM_IND_DAT_REG );
1185 }
1186 
1187 #else /* FALCON_USE_IO_BAR */
1188 
1189 #define _falcon_writel( efab, value, reg ) \
1190  writel ( (value), (efab)->membase + (reg) )
1191 #define _falcon_readl( efab, reg ) readl ( (efab)->membase + (reg) )
1192 
1193 #endif /* FALCON_USE_IO_BAR */
1194 
1195 /**
1196  * Write to a Falcon register
1197  *
1198  */
1199 static inline void
1200 falcon_write ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
1201 {
1202 
1203  EFAB_REGDUMP ( "Writing register %x with " EFAB_OWORD_FMT "\n",
1204  reg, EFAB_OWORD_VAL ( *value ) );
1205 
1206  _falcon_writel ( efab, value->u32[0], reg + 0 );
1207  _falcon_writel ( efab, value->u32[1], reg + 4 );
1208  _falcon_writel ( efab, value->u32[2], reg + 8 );
1209  wmb();
1210  _falcon_writel ( efab, value->u32[3], reg + 12 );
1211  wmb();
1212 }
1213 
1214 /**
1215  * Write to Falcon SRAM
1216  *
1217  */
1218 static inline void
1220  unsigned int index )
1221 {
1222  unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
1223  ( index * sizeof ( *value ) ) );
1224 
1225  EFAB_REGDUMP ( "Writing SRAM register %x with " EFAB_QWORD_FMT "\n",
1226  reg, EFAB_QWORD_VAL ( *value ) );
1227 
1228  _falcon_writel ( efab, value->u32[0], reg + 0 );
1229  _falcon_writel ( efab, value->u32[1], reg + 4 );
1230  wmb();
1231 }
1232 
1233 /**
1234  * Write dword to Falcon register that allows partial writes
1235  *
1236  */
1237 static inline void
1238 falcon_writel ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
1239 {
1240  EFAB_REGDUMP ( "Writing partial register %x with " EFAB_DWORD_FMT "\n",
1241  reg, EFAB_DWORD_VAL ( *value ) );
1242  _falcon_writel ( efab, value->u32[0], reg );
1243 }
1244 
1245 /**
1246  * Read from a Falcon register
1247  *
1248  */
1249 static inline void
1250 falcon_read ( struct efab_nic *efab, efab_oword_t *value, unsigned int reg )
1251 {
1252  value->u32[0] = _falcon_readl ( efab, reg + 0 );
1253  wmb();
1254  value->u32[1] = _falcon_readl ( efab, reg + 4 );
1255  value->u32[2] = _falcon_readl ( efab, reg + 8 );
1256  value->u32[3] = _falcon_readl ( efab, reg + 12 );
1257 
1258  EFAB_REGDUMP ( "Read from register %x, got " EFAB_OWORD_FMT "\n",
1259  reg, EFAB_OWORD_VAL ( *value ) );
1260 }
1261 
1262 /**
1263  * Read from Falcon SRAM
1264  *
1265  */
1266 static inline void
1268  unsigned int index )
1269 {
1270  unsigned int reg = ( FCN_REVISION_REG ( efab, FCN_BUF_FULL_TBL_KER ) +
1271  ( index * sizeof ( *value ) ) );
1272 
1273  value->u32[0] = _falcon_readl ( efab, reg + 0 );
1274  value->u32[1] = _falcon_readl ( efab, reg + 4 );
1275  EFAB_REGDUMP ( "Read from SRAM register %x, got " EFAB_QWORD_FMT "\n",
1276  reg, EFAB_QWORD_VAL ( *value ) );
1277 }
1278 
1279 /**
1280  * Read dword from a portion of a Falcon register
1281  *
1282  */
1283 static inline void
1284 falcon_readl ( struct efab_nic *efab, efab_dword_t *value, unsigned int reg )
1285 {
1286  value->u32[0] = _falcon_readl ( efab, reg );
1287  EFAB_REGDUMP ( "Read from register %x, got " EFAB_DWORD_FMT "\n",
1288  reg, EFAB_DWORD_VAL ( *value ) );
1289 }
1290 
1291 #define FCN_DUMP_REG( efab, _reg ) do { \
1292  efab_oword_t reg; \
1293  falcon_read ( efab, &reg, _reg ); \
1294  EFAB_LOG ( #_reg " = " EFAB_OWORD_FMT "\n", \
1295  EFAB_OWORD_VAL ( reg ) ); \
1296  } while ( 0 );
1297 
1298 #define FCN_DUMP_MAC_REG( efab, _mac_reg ) do { \
1299  efab_dword_t reg; \
1300  efab->mac_op->mac_readl ( efab, &reg, _mac_reg ); \
1301  EFAB_LOG ( #_mac_reg " = " EFAB_DWORD_FMT "\n", \
1302  EFAB_DWORD_VAL ( reg ) ); \
1303  } while ( 0 );
1304 
1305 /**
1306  * See if an event is present
1307  *
1308  * @v event Falcon event structure
1309  * @ret True An event is pending
1310  * @ret False No event is pending
1311  *
1312  * We check both the high and low dword of the event for all ones. We
1313  * wrote all ones when we cleared the event, and no valid event can
1314  * have all ones in either its high or low dwords. This approach is
1315  * robust against reordering.
1316  *
1317  * Note that using a single 64-bit comparison is incorrect; even
1318  * though the CPU read will be atomic, the DMA write may not be.
1319  */
1320 static inline int
1322 {
1323  return ( ! ( EFAB_DWORD_IS_ALL_ONES ( event->dword[0] ) |
1324  EFAB_DWORD_IS_ALL_ONES ( event->dword[1] ) ) );
1325 }
1326 
1327 static void
1328 falcon_eventq_read_ack ( struct efab_nic *efab, struct efab_ev_queue *ev_queue )
1329 {
1330  efab_dword_t reg;
1331 
1332  EFAB_POPULATE_DWORD_1 ( reg, FCN_EVQ_RPTR_DWORD, ev_queue->read_ptr );
1333  falcon_writel ( efab, &reg,
1334  FCN_REVISION_REG ( efab, FCN_EVQ_RPTR_REG_KER_DWORD ) );
1335 }
1336 
1337 #if 0
1338 /**
1339  * Dump register contents (for debugging)
1340  *
1341  * Marked as static inline so that it will not be compiled in if not
1342  * used.
1343  */
1344 static inline void
1345 falcon_dump_regs ( struct efab_nic *efab )
1346 {
1347  FCN_DUMP_REG ( efab, FCN_INT_EN_REG_KER );
1358  FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
1359  FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
1360  FCN_DUMP_REG ( efab, FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
1373 }
1374 #endif
1375 
1376 static void
1377 falcon_interrupts ( struct efab_nic *efab, int enabled, int force )
1378 {
1379  efab_oword_t int_en_reg_ker;
1380 
1381  EFAB_POPULATE_OWORD_2 ( int_en_reg_ker,
1382  FCN_KER_INT_KER, force,
1383  FCN_DRV_INT_EN_KER, enabled );
1384  falcon_write ( efab, &int_en_reg_ker, FCN_INT_EN_REG_KER );
1385 }
1386 
1387 /*******************************************************************************
1388  *
1389  *
1390  * SPI access
1391  *
1392  *
1393  *******************************************************************************/
1394 
1395 
1396 /** Maximum length for a single SPI transaction */
1397 #define FALCON_SPI_MAX_LEN 16
1398 
1399 static int
1400 falcon_spi_wait ( struct efab_nic *efab )
1401 {
1402  efab_oword_t reg;
1403  int count;
1404 
1405  count = 0;
1406  do {
1407  udelay ( 100 );
1408  falcon_read ( efab, &reg, FCN_EE_SPI_HCMD_REG );
1409  if ( EFAB_OWORD_FIELD ( reg, FCN_EE_SPI_HCMD_CMD_EN ) == 0 )
1410  return 0;
1411  } while ( ++count < 1000 );
1412 
1413  EFAB_ERR ( "Timed out waiting for SPI\n" );
1414  return -ETIMEDOUT;
1415 }
1416 
1417 static int
1419  unsigned int command, int address,
1420  const void* data_out, void *data_in, size_t len )
1421 {
1422  struct efab_nic *efab = container_of ( bus, struct efab_nic, spi_bus );
1423  int address_len, rc, device_id, read_cmd;
1424  efab_oword_t reg;
1425 
1426  /* falcon_init_spi_device() should have reduced the block size
1427  * down so this constraint holds */
1428  assert ( len <= FALCON_SPI_MAX_LEN );
1429 
1430  /* Is this the FLASH or EEPROM device? */
1431  if ( device == &efab->spi_flash )
1433  else if ( device == &efab->spi_eeprom )
1435  else {
1436  EFAB_ERR ( "Unknown device %p\n", device );
1437  return -EINVAL;
1438  }
1439 
1440  EFAB_TRACE ( "Executing spi command %d on device %d at %d for %zd bytes\n",
1442 
1443  /* The bus must be idle */
1444  rc = falcon_spi_wait ( efab );
1445  if ( rc )
1446  goto fail1;
1447 
1448  /* Copy data out */
1449  if ( data_out ) {
1450  memcpy ( &reg, data_out, len );
1452  }
1453 
1454  /* Program address register */
1455  if ( address >= 0 ) {
1456  EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
1457  falcon_write ( efab, &reg, FCN_EE_SPI_HADR_REG );
1458  }
1459 
1460  /* Issue command */
1461  address_len = ( address >= 0 ) ? device->address_len / 8 : 0;
1462  read_cmd = ( data_in ? FCN_EE_SPI_READ : FCN_EE_SPI_WRITE );
1464  FCN_EE_SPI_HCMD_CMD_EN, 1,
1465  FCN_EE_SPI_HCMD_SF_SEL, device_id,
1466  FCN_EE_SPI_HCMD_DABCNT, len,
1467  FCN_EE_SPI_HCMD_READ, read_cmd,
1468  FCN_EE_SPI_HCMD_DUBCNT, 0,
1469  FCN_EE_SPI_HCMD_ADBCNT, address_len,
1470  FCN_EE_SPI_HCMD_ENC, command );
1471  falcon_write ( efab, &reg, FCN_EE_SPI_HCMD_REG );
1472 
1473  /* Wait for the command to complete */
1474  rc = falcon_spi_wait ( efab );
1475  if ( rc )
1476  goto fail2;
1477 
1478  /* Copy data in */
1479  if ( data_in ) {
1480  falcon_read ( efab, &reg, FCN_EE_SPI_HDATA_REG );
1481  memcpy ( data_in, &reg, len );
1482  }
1483 
1484  return 0;
1485 
1486 fail2:
1487 fail1:
1488  EFAB_ERR ( "Failed SPI command %d to device %d address 0x%x len 0x%zx\n",
1490 
1491  return rc;
1492 }
1493 
1494 /*******************************************************************************
1495  *
1496  *
1497  * Falcon bit-bashed I2C interface
1498  *
1499  *
1500  *******************************************************************************/
1501 
1502 static void
1503 falcon_i2c_bit_write ( struct bit_basher *basher, unsigned int bit_id,
1504  unsigned long data )
1505 {
1506  struct efab_nic *efab = container_of ( basher, struct efab_nic,
1507  i2c_bb.basher );
1508  efab_oword_t reg;
1509 
1510  falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
1511  switch ( bit_id ) {
1512  case I2C_BIT_SCL:
1513  EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO0_OEN, ( data ? 0 : 1 ) );
1514  break;
1515  case I2C_BIT_SDA:
1516  EFAB_SET_OWORD_FIELD ( reg, FCN_GPIO3_OEN, ( data ? 0 : 1 ) );
1517  break;
1518  default:
1519  EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
1520  break;
1521  }
1522 
1524 }
1525 
1526 static int
1527 falcon_i2c_bit_read ( struct bit_basher *basher, unsigned int bit_id )
1528 {
1529  struct efab_nic *efab = container_of ( basher, struct efab_nic,
1530  i2c_bb.basher );
1531  efab_oword_t reg;
1532 
1533  falcon_read ( efab, &reg, FCN_GPIO_CTL_REG_KER );
1534  switch ( bit_id ) {
1535  case I2C_BIT_SCL:
1536  return EFAB_OWORD_FIELD ( reg, FCN_GPIO0_IN );
1537  break;
1538  case I2C_BIT_SDA:
1539  return EFAB_OWORD_FIELD ( reg, FCN_GPIO3_IN );
1540  break;
1541  default:
1542  EFAB_ERR ( "%s bit=%d\n", __func__, bit_id );
1543  break;
1544  }
1545 
1546  return -1;
1547 }
1548 
1551  .write = falcon_i2c_bit_write,
1552 };
1553 
1554 
1555 /*******************************************************************************
1556  *
1557  *
1558  * MDIO access
1559  *
1560  *
1561  *******************************************************************************/
1562 
1563 static int
1564 falcon_gmii_wait ( struct efab_nic *efab )
1565 {
1566  efab_dword_t md_stat;
1567  int count;
1568 
1569  /* wait up to 10ms */
1570  for (count = 0; count < 1000; count++) {
1571  falcon_readl ( efab, &md_stat, FCN_MD_STAT_REG_KER );
1572  if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSY ) == 0 ) {
1573  if ( EFAB_DWORD_FIELD ( md_stat, FCN_MD_LNFL ) != 0 ||
1574  EFAB_DWORD_FIELD ( md_stat, FCN_MD_BSERR ) != 0 ) {
1575  EFAB_ERR ( "Error from GMII access "
1576  EFAB_DWORD_FMT"\n",
1577  EFAB_DWORD_VAL ( md_stat ));
1578  return -EIO;
1579  }
1580  return 0;
1581  }
1582  udelay(10);
1583  }
1584 
1585  EFAB_ERR ( "Timed out waiting for GMII\n" );
1586  return -ETIMEDOUT;
1587 }
1588 
1589 static void
1590 falcon_mdio_write ( struct efab_nic *efab, int device,
1591  int location, int value )
1592 {
1593  efab_oword_t reg;
1594 
1595  EFAB_TRACE ( "Writing GMII %d register %02x with %04x\n",
1596  device, location, value );
1597 
1598  /* Check MII not currently being accessed */
1599  if ( falcon_gmii_wait ( efab ) )
1600  return;
1601 
1602  /* Write the address/ID register */
1603  EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
1605 
1606  if ( efab->phy_10g ) {
1607  /* clause45 */
1609  FCN_MD_PRT_ADR, efab->phy_addr,
1610  FCN_MD_DEV_ADR, device );
1611  }
1612  else {
1613  /* clause22 */
1614  assert ( device == 0 );
1615 
1617  FCN_MD_PRT_ADR, efab->phy_addr,
1618  FCN_MD_DEV_ADR, location );
1619  }
1620  falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
1621 
1622 
1623  /* Write data */
1624  EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_TXD, value );
1625  falcon_write ( efab, &reg, FCN_MD_TXD_REG_KER );
1626 
1628  FCN_MD_WRC, 1,
1629  FCN_MD_GC, ( efab->phy_10g ? 0 : 1 ) );
1630  falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
1631 
1632  /* Wait for data to be written */
1633  if ( falcon_gmii_wait ( efab ) ) {
1634  /* Abort the write operation */
1636  FCN_MD_WRC, 0,
1637  FCN_MD_GC, 1);
1638  falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
1639  udelay(10);
1640  }
1641 }
1642 
1643 static int
1644 falcon_mdio_read ( struct efab_nic *efab, int device, int location )
1645 {
1646  efab_oword_t reg;
1647  int value;
1648 
1649  /* Check MII not currently being accessed */
1650  if ( falcon_gmii_wait ( efab ) )
1651  return -1;
1652 
1653  if ( efab->phy_10g ) {
1654  /* clause45 */
1655  EFAB_POPULATE_OWORD_1 ( reg, FCN_MD_PHY_ADR, location );
1657 
1659  FCN_MD_PRT_ADR, efab->phy_addr,
1660  FCN_MD_DEV_ADR, device );
1661  falcon_write ( efab, &reg, FCN_MD_ID_REG_KER);
1662 
1663  /* request data to be read */
1665  FCN_MD_RDC, 1,
1666  FCN_MD_GC, 0 );
1667  }
1668  else {
1669  /* clause22 */
1670  assert ( device == 0 );
1671 
1673  FCN_MD_PRT_ADR, efab->phy_addr,
1674  FCN_MD_DEV_ADR, location );
1675  falcon_write ( efab, &reg, FCN_MD_ID_REG_KER );
1676 
1677  /* Request data to be read */
1679  FCN_MD_RIC, 1,
1680  FCN_MD_GC, 1 );
1681  }
1682 
1683  falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
1684 
1685  /* Wait for data to become available */
1686  if ( falcon_gmii_wait ( efab ) ) {
1687  /* Abort the read operation */
1689  FCN_MD_RIC, 0,
1690  FCN_MD_GC, 1 );
1691  falcon_write ( efab, &reg, FCN_MD_CS_REG_KER );
1692  udelay ( 10 );
1693  value = -1;
1694  }
1695  else {
1696  /* Read the data */
1697  falcon_read ( efab, &reg, FCN_MD_RXD_REG_KER );
1698  value = EFAB_OWORD_FIELD ( reg, FCN_MD_RXD );
1699  }
1700 
1701  EFAB_TRACE ( "Read from GMII %d register %02x, got %04x\n",
1702  device, location, value );
1703 
1704  return value;
1705 }
1706 
1707 /*******************************************************************************
1708  *
1709  *
1710  * MAC wrapper
1711  *
1712  *
1713  *******************************************************************************/
1714 
1715 static void
1717 {
1718  efab_oword_t reg;
1719  int link_speed;
1720 
1721  if ( efab->link_options & LPA_EF_10000 ) {
1722  link_speed = 0x3;
1723  } else if ( efab->link_options & LPA_EF_1000 ) {
1724  link_speed = 0x2;
1725  } else if ( efab->link_options & LPA_100 ) {
1726  link_speed = 0x1;
1727  } else {
1728  link_speed = 0x0;
1729  }
1731  FCN_MAC_XOFF_VAL, 0xffff /* datasheet */,
1732  FCN_MAC_BCAD_ACPT, 1,
1733  FCN_MAC_UC_PROM, 0,
1734  FCN_MAC_LINK_STATUS, 1,
1735  FCN_MAC_SPEED, link_speed );
1736 
1738 }
1739 
1740 /*******************************************************************************
1741  *
1742  *
1743  * GMAC handling
1744  *
1745  *
1746  *******************************************************************************/
1747 
1748 /* GMAC configuration register 1 */
1749 #define GM_CFG1_REG_MAC 0x00
1750 #define GM_SW_RST_LBN 31
1751 #define GM_SW_RST_WIDTH 1
1752 #define GM_RX_FC_EN_LBN 5
1753 #define GM_RX_FC_EN_WIDTH 1
1754 #define GM_TX_FC_EN_LBN 4
1755 #define GM_TX_FC_EN_WIDTH 1
1756 #define GM_RX_EN_LBN 2
1757 #define GM_RX_EN_WIDTH 1
1758 #define GM_TX_EN_LBN 0
1759 #define GM_TX_EN_WIDTH 1
1760 
1761 /* GMAC configuration register 2 */
1762 #define GM_CFG2_REG_MAC 0x01
1763 #define GM_PAMBL_LEN_LBN 12
1764 #define GM_PAMBL_LEN_WIDTH 4
1765 #define GM_IF_MODE_LBN 8
1766 #define GM_IF_MODE_WIDTH 2
1767 #define GM_PAD_CRC_EN_LBN 2
1768 #define GM_PAD_CRC_EN_WIDTH 1
1769 #define GM_FD_LBN 0
1770 #define GM_FD_WIDTH 1
1771 
1772 /* GMAC maximum frame length register */
1773 #define GM_MAX_FLEN_REG_MAC 0x04
1774 #define GM_MAX_FLEN_LBN 0
1775 #define GM_MAX_FLEN_WIDTH 16
1776 
1777 /* GMAC MII management configuration register */
1778 #define GM_MII_MGMT_CFG_REG_MAC 0x08
1779 #define GM_MGMT_CLK_SEL_LBN 0
1780 #define GM_MGMT_CLK_SEL_WIDTH 3
1781 
1782 /* GMAC MII management command register */
1783 #define GM_MII_MGMT_CMD_REG_MAC 0x09
1784 #define GM_MGMT_SCAN_CYC_LBN 1
1785 #define GM_MGMT_SCAN_CYC_WIDTH 1
1786 #define GM_MGMT_RD_CYC_LBN 0
1787 #define GM_MGMT_RD_CYC_WIDTH 1
1788 
1789 /* GMAC MII management address register */
1790 #define GM_MII_MGMT_ADR_REG_MAC 0x0a
1791 #define GM_MGMT_PHY_ADDR_LBN 8
1792 #define GM_MGMT_PHY_ADDR_WIDTH 5
1793 #define GM_MGMT_REG_ADDR_LBN 0
1794 #define GM_MGMT_REG_ADDR_WIDTH 5
1795 
1796 /* GMAC MII management control register */
1797 #define GM_MII_MGMT_CTL_REG_MAC 0x0b
1798 #define GM_MGMT_CTL_LBN 0
1799 #define GM_MGMT_CTL_WIDTH 16
1800 
1801 /* GMAC MII management status register */
1802 #define GM_MII_MGMT_STAT_REG_MAC 0x0c
1803 #define GM_MGMT_STAT_LBN 0
1804 #define GM_MGMT_STAT_WIDTH 16
1805 
1806 /* GMAC MII management indicators register */
1807 #define GM_MII_MGMT_IND_REG_MAC 0x0d
1808 #define GM_MGMT_BUSY_LBN 0
1809 #define GM_MGMT_BUSY_WIDTH 1
1810 
1811 /* GMAC station address register 1 */
1812 #define GM_ADR1_REG_MAC 0x10
1813 #define GM_HWADDR_5_LBN 24
1814 #define GM_HWADDR_5_WIDTH 8
1815 #define GM_HWADDR_4_LBN 16
1816 #define GM_HWADDR_4_WIDTH 8
1817 #define GM_HWADDR_3_LBN 8
1818 #define GM_HWADDR_3_WIDTH 8
1819 #define GM_HWADDR_2_LBN 0
1820 #define GM_HWADDR_2_WIDTH 8
1821 
1822 /* GMAC station address register 2 */
1823 #define GM_ADR2_REG_MAC 0x11
1824 #define GM_HWADDR_1_LBN 24
1825 #define GM_HWADDR_1_WIDTH 8
1826 #define GM_HWADDR_0_LBN 16
1827 #define GM_HWADDR_0_WIDTH 8
1828 
1829 /* GMAC FIFO configuration register 0 */
1830 #define GMF_CFG0_REG_MAC 0x12
1831 #define GMF_FTFENREQ_LBN 12
1832 #define GMF_FTFENREQ_WIDTH 1
1833 #define GMF_STFENREQ_LBN 11
1834 #define GMF_STFENREQ_WIDTH 1
1835 #define GMF_FRFENREQ_LBN 10
1836 #define GMF_FRFENREQ_WIDTH 1
1837 #define GMF_SRFENREQ_LBN 9
1838 #define GMF_SRFENREQ_WIDTH 1
1839 #define GMF_WTMENREQ_LBN 8
1840 #define GMF_WTMENREQ_WIDTH 1
1841 
1842 /* GMAC FIFO configuration register 1 */
1843 #define GMF_CFG1_REG_MAC 0x13
1844 #define GMF_CFGFRTH_LBN 16
1845 #define GMF_CFGFRTH_WIDTH 5
1846 #define GMF_CFGXOFFRTX_LBN 0
1847 #define GMF_CFGXOFFRTX_WIDTH 16
1848 
1849 /* GMAC FIFO configuration register 2 */
1850 #define GMF_CFG2_REG_MAC 0x14
1851 #define GMF_CFGHWM_LBN 16
1852 #define GMF_CFGHWM_WIDTH 6
1853 #define GMF_CFGLWM_LBN 0
1854 #define GMF_CFGLWM_WIDTH 6
1855 
1856 /* GMAC FIFO configuration register 3 */
1857 #define GMF_CFG3_REG_MAC 0x15
1858 #define GMF_CFGHWMFT_LBN 16
1859 #define GMF_CFGHWMFT_WIDTH 6
1860 #define GMF_CFGFTTH_LBN 0
1861 #define GMF_CFGFTTH_WIDTH 6
1862 
1863 /* GMAC FIFO configuration register 4 */
1864 #define GMF_CFG4_REG_MAC 0x16
1865 #define GMF_HSTFLTRFRM_PAUSE_LBN 12
1866 #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12
1867 
1868 /* GMAC FIFO configuration register 5 */
1869 #define GMF_CFG5_REG_MAC 0x17
1870 #define GMF_CFGHDPLX_LBN 22
1871 #define GMF_CFGHDPLX_WIDTH 1
1872 #define GMF_CFGBYTMODE_LBN 19
1873 #define GMF_CFGBYTMODE_WIDTH 1
1874 #define GMF_HSTDRPLT64_LBN 18
1875 #define GMF_HSTDRPLT64_WIDTH 1
1876 #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12
1877 #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
1878 
1879 static void
1881  unsigned int mac_reg )
1882 {
1883  efab_oword_t temp;
1884 
1885  EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
1886  EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
1887  falcon_write ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
1888 }
1889 
1890 static void
1892  unsigned int mac_reg )
1893 {
1894  efab_oword_t temp;
1895 
1896  falcon_read ( efab, &temp, FALCON_GMAC_REG ( efab, mac_reg ) );
1897  EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
1898  EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
1899 }
1900 
1901 static void
1902 mentormac_reset ( struct efab_nic *efab )
1903 {
1904  efab_dword_t reg;
1905 
1906  /* Take into reset */
1907  EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 1 );
1909  udelay ( 1000 );
1910 
1911  /* Take out of reset */
1912  EFAB_POPULATE_DWORD_1 ( reg, GM_SW_RST, 0 );
1914  udelay ( 1000 );
1915 
1916  /* Configure GMII interface so PHY is accessible. Note that
1917  * GMII interface is connected only to port 0, and that on
1918  * Falcon this is a no-op.
1919  */
1920  EFAB_POPULATE_DWORD_1 ( reg, GM_MGMT_CLK_SEL, 0x4 );
1922  udelay ( 10 );
1923 }
1924 
1925 static void
1926 mentormac_init ( struct efab_nic *efab )
1927 {
1928  int pause, if_mode, full_duplex, bytemode, half_duplex;
1929  efab_dword_t reg;
1930 
1931  /* Configuration register 1 */
1932  pause = ( efab->link_options & LPA_PAUSE_CAP ) ? 1 : 0;
1933  if ( ! ( efab->link_options & LPA_EF_DUPLEX ) ) {
1934  /* Half-duplex operation requires TX flow control */
1935  pause = 1;
1936  }
1938  GM_TX_EN, 1,
1939  GM_TX_FC_EN, pause,
1940  GM_RX_EN, 1,
1941  GM_RX_FC_EN, 1 );
1943  udelay ( 10 );
1944 
1945  /* Configuration register 2 */
1946  if_mode = ( efab->link_options & LPA_EF_1000 ) ? 2 : 1;
1947  full_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 1 : 0;
1949  GM_IF_MODE, if_mode,
1950  GM_PAD_CRC_EN, 1,
1951  GM_FD, full_duplex,
1952  GM_PAMBL_LEN, 0x7 /* ? */ );
1954  udelay ( 10 );
1955 
1956  /* Max frame len register */
1957  EFAB_POPULATE_DWORD_1 ( reg, GM_MAX_FLEN,
1960  udelay ( 10 );
1961 
1962  /* FIFO configuration register 0 */
1964  GMF_FTFENREQ, 1,
1965  GMF_STFENREQ, 1,
1966  GMF_FRFENREQ, 1,
1967  GMF_SRFENREQ, 1,
1968  GMF_WTMENREQ, 1 );
1970  udelay ( 10 );
1971 
1972  /* FIFO configuration register 1 */
1974  GMF_CFGFRTH, 0x12,
1975  GMF_CFGXOFFRTX, 0xffff );
1977  udelay ( 10 );
1978 
1979  /* FIFO configuration register 2 */
1981  GMF_CFGHWM, 0x3f,
1982  GMF_CFGLWM, 0xa );
1984  udelay ( 10 );
1985 
1986  /* FIFO configuration register 3 */
1988  GMF_CFGHWMFT, 0x1c,
1989  GMF_CFGFTTH, 0x08 );
1991  udelay ( 10 );
1992 
1993  /* FIFO configuration register 4 */
1994  EFAB_POPULATE_DWORD_1 ( reg, GMF_HSTFLTRFRM_PAUSE, 1 );
1996  udelay ( 10 );
1997 
1998  /* FIFO configuration register 5 */
1999  bytemode = ( efab->link_options & LPA_EF_1000 ) ? 1 : 0;
2000  half_duplex = ( efab->link_options & LPA_EF_DUPLEX ) ? 0 : 1;
2002  EFAB_SET_DWORD_FIELD ( reg, GMF_CFGBYTMODE, bytemode );
2003  EFAB_SET_DWORD_FIELD ( reg, GMF_CFGHDPLX, half_duplex );
2004  EFAB_SET_DWORD_FIELD ( reg, GMF_HSTDRPLT64, half_duplex );
2005  EFAB_SET_DWORD_FIELD ( reg, GMF_HSTFLTRFRMDC_PAUSE, 0 );
2007  udelay ( 10 );
2008 
2009  /* MAC address */
2011  GM_HWADDR_5, efab->mac_addr[5],
2012  GM_HWADDR_4, efab->mac_addr[4],
2013  GM_HWADDR_3, efab->mac_addr[3],
2014  GM_HWADDR_2, efab->mac_addr[2] );
2016  udelay ( 10 );
2018  GM_HWADDR_1, efab->mac_addr[1],
2019  GM_HWADDR_0, efab->mac_addr[0] );
2021  udelay ( 10 );
2022 }
2023 
2024 static int
2025 falcon_init_gmac ( struct efab_nic *efab )
2026 {
2027  /* Reset the MAC */
2028  mentormac_reset ( efab );
2029 
2030  /* Initialise PHY */
2031  efab->phy_op->init ( efab );
2032 
2033  /* check the link is up */
2034  if ( !efab->link_up )
2035  return -EAGAIN;
2036 
2037  /* Initialise MAC */
2038  mentormac_init ( efab );
2039 
2040  /* reconfigure the MAC wrapper */
2042 
2043  return 0;
2044 }
2045 
2048 };
2049 
2050 
2051 /*******************************************************************************
2052  *
2053  *
2054  * XMAC handling
2055  *
2056  *
2057  *******************************************************************************/
2058 
2059 /**
2060  * Write dword to a Falcon XMAC register
2061  *
2062  */
2063 static void
2065  unsigned int mac_reg )
2066 {
2067  efab_oword_t temp;
2068 
2069  EFAB_POPULATE_OWORD_1 ( temp, FCN_MAC_DATA,
2070  EFAB_DWORD_FIELD ( *value, FCN_MAC_DATA ) );
2071  falcon_write ( efab, &temp,
2072  FALCON_XMAC_REG ( efab, mac_reg ) );
2073 }
2074 
2075 /**
2076  * Read dword from a Falcon XMAC register
2077  *
2078  */
2079 static void
2081  unsigned int mac_reg )
2082 {
2083  efab_oword_t temp;
2084 
2085  falcon_read ( efab, &temp,
2086  FALCON_XMAC_REG ( efab, mac_reg ) );
2087  EFAB_POPULATE_DWORD_1 ( *value, FCN_MAC_DATA,
2088  EFAB_OWORD_FIELD ( temp, FCN_MAC_DATA ) );
2089 }
2090 
2091 /**
2092  * Configure Falcon XAUI output
2093  */
2094 static void
2095 falcon_setup_xaui ( struct efab_nic *efab )
2096 {
2097  efab_dword_t sdctl, txdrv;
2098 
2099  falcon_xmac_readl ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
2100  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT );
2101  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVD, XX_SD_CTL_DRV_DEFAULT );
2102  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT );
2103  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVC, XX_SD_CTL_DRV_DEFAULT );
2104  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT );
2105  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVB, XX_SD_CTL_DRV_DEFAULT );
2106  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT );
2107  EFAB_SET_DWORD_FIELD ( sdctl, FCN_XX_LODRVA, XX_SD_CTL_DRV_DEFAULT );
2108  falcon_xmac_writel ( efab, &sdctl, FCN_XX_SD_CTL_REG_MAC );
2109 
2110  EFAB_POPULATE_DWORD_8 ( txdrv,
2111  FCN_XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
2112  FCN_XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
2113  FCN_XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
2114  FCN_XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
2115  FCN_XX_DTXD, XX_TXDRV_DTX_DEFAULT,
2116  FCN_XX_DTXC, XX_TXDRV_DTX_DEFAULT,
2117  FCN_XX_DTXB, XX_TXDRV_DTX_DEFAULT,
2118  FCN_XX_DTXA, XX_TXDRV_DTX_DEFAULT);
2120 }
2121 
2122 static int
2124 {
2125  efab_dword_t reg;
2126 
2127  if ( efab->pci_revision < FALCON_REV_B0 )
2128  return 1;
2129  /* The ISR latches, so clear it and re-read */
2132 
2133  if ( EFAB_DWORD_FIELD ( reg, FCN_XM_LCLFLT ) ||
2134  EFAB_DWORD_FIELD ( reg, FCN_XM_RMTFLT ) ) {
2135  EFAB_TRACE ( "MGT_INT: "EFAB_DWORD_FMT"\n",
2136  EFAB_DWORD_VAL ( reg ) );
2137  return 0;
2138  }
2139 
2140  return 1;
2141 }
2142 
2143 static void
2144 falcon_mask_status_intr ( struct efab_nic *efab, int enable )
2145 {
2146  efab_dword_t reg;
2147 
2148  if ( efab->pci_revision < FALCON_REV_B0 )
2149  return;
2150 
2151  /* Flush the ISR */
2152  if ( enable )
2154 
2156  FCN_XM_MSK_RMTFLT, !enable,
2157  FCN_XM_MSK_LCLFLT, !enable);
2159 }
2160 
2161 /**
2162  * Reset 10G MAC connected to port
2163  *
2164  */
2165 static int
2166 falcon_reset_xmac ( struct efab_nic *efab )
2167 {
2168  efab_dword_t reg;
2169  int count;
2170 
2171  EFAB_POPULATE_DWORD_1 ( reg, FCN_XM_CORE_RST, 1 );
2173 
2174  for ( count = 0 ; count < 1000 ; count++ ) {
2175  udelay ( 10 );
2176  falcon_xmac_readl ( efab, &reg,
2178  if ( EFAB_DWORD_FIELD ( reg, FCN_XM_CORE_RST ) == 0 )
2179  return 0;
2180  }
2181  return -ETIMEDOUT;
2182 }
2183 
2184 
2185 static int
2186 falcon_reset_xaui ( struct efab_nic *efab )
2187 {
2188  efab_dword_t reg;
2189  int count;
2190 
2191  if (!efab->is_asic)
2192  return 0;
2193 
2194  EFAB_POPULATE_DWORD_1 ( reg, FCN_XX_RST_XX_EN, 1 );
2196 
2197  /* Give some time for the link to establish */
2198  for (count = 0; count < 1000; count++) { /* wait up to 10ms */
2200  if ( EFAB_DWORD_FIELD ( reg, FCN_XX_RST_XX_EN ) == 0 ) {
2201  falcon_setup_xaui ( efab );
2202  return 0;
2203  }
2204  udelay(10);
2205  }
2206  EFAB_ERR ( "timed out waiting for XAUI/XGXS reset\n" );
2207  return -ETIMEDOUT;
2208 }
2209 
2210 static int
2212 {
2213  efab_dword_t reg;
2214  int align_done, lane_status, sync;
2215  int has_phyxs;
2216  int link_ok = 1;
2217 
2218  /* Read Falcon XAUI side */
2219  if ( efab->is_asic ) {
2220  /* Read link status */
2222  align_done = EFAB_DWORD_FIELD ( reg, FCN_XX_ALIGN_DONE );
2223 
2224  sync = EFAB_DWORD_FIELD ( reg, FCN_XX_SYNC_STAT );
2226 
2227  link_ok = align_done && sync;
2228  }
2229 
2230  /* Clear link status ready for next read */
2231  EFAB_SET_DWORD_FIELD ( reg, FCN_XX_COMMA_DET, FCN_XX_COMMA_DET_RESET );
2232  EFAB_SET_DWORD_FIELD ( reg, FCN_XX_CHARERR, FCN_XX_CHARERR_RESET);
2233  EFAB_SET_DWORD_FIELD ( reg, FCN_XX_DISPERR, FCN_XX_DISPERR_RESET);
2235 
2236  has_phyxs = ( efab->phy_op->mmds & ( 1 << MDIO_MMD_PHYXS ) );
2237  if ( link_ok && has_phyxs ) {
2238  lane_status = falcon_mdio_read ( efab, MDIO_MMD_PHYXS,
2240  link_ok = ( lane_status & ( 1 << MDIO_PHYXS_LANE_ALIGNED_LBN ) );
2241 
2242  if (!link_ok )
2243  EFAB_LOG ( "XGXS lane status: %x\n", lane_status );
2244  }
2245 
2246  return link_ok;
2247 }
2248 
2249 /**
2250  * Initialise XMAC
2251  *
2252  */
2253 static void
2255 {
2256  efab_dword_t reg;
2257  int max_frame_len;
2258 
2259  /* Configure MAC - cut-thru mode is hard wired on */
2261  FCN_XM_RX_JUMBO_MODE, 1,
2262  FCN_XM_TX_STAT_EN, 1,
2263  FCN_XM_RX_STAT_EN, 1);
2265 
2266  /* Configure TX */
2268  FCN_XM_TXEN, 1,
2269  FCN_XM_TX_PRMBL, 1,
2270  FCN_XM_AUTO_PAD, 1,
2271  FCN_XM_TXCRC, 1,
2272  FCN_XM_FCNTL, 1,
2273  FCN_XM_IPG, 0x3 );
2275 
2276  /* Configure RX */
2278  FCN_XM_RXEN, 1,
2279  FCN_XM_AUTO_DEPAD, 0,
2280  FCN_XM_ACPT_ALL_MCAST, 1,
2281  FCN_XM_PASS_CRC_ERR, 1 );
2283 
2284  /* Set frame length */
2285  max_frame_len = EFAB_MAX_FRAME_LEN ( ETH_FRAME_LEN );
2287  FCN_XM_MAX_RX_FRM_SIZE, max_frame_len );
2290  FCN_XM_MAX_TX_FRM_SIZE, max_frame_len,
2291  FCN_XM_TX_JUMBO_MODE, 1 );
2293 
2294  /* Enable flow control receipt */
2296  FCN_XM_PAUSE_TIME, 0xfffe,
2297  FCN_XM_DIS_FCNTL, 0 );
2299 
2300  /* Set MAC address */
2302  FCN_XM_ADR_0, efab->mac_addr[0],
2303  FCN_XM_ADR_1, efab->mac_addr[1],
2304  FCN_XM_ADR_2, efab->mac_addr[2],
2305  FCN_XM_ADR_3, efab->mac_addr[3] );
2308  FCN_XM_ADR_4, efab->mac_addr[4],
2309  FCN_XM_ADR_5, efab->mac_addr[5] );
2311 }
2312 
2313 static int
2314 falcon_init_xmac ( struct efab_nic *efab )
2315 {
2316  int count, rc;
2317 
2318  /* Mask the PHY management interrupt */
2319  falcon_mask_status_intr ( efab, 0 );
2320 
2321  /* Initialise the PHY to instantiate the clock. */
2322  rc = efab->phy_op->init ( efab );
2323  if ( rc ) {
2324  EFAB_ERR ( "unable to initialise PHY\n" );
2325  goto fail1;
2326  }
2327 
2328  falcon_reset_xaui ( efab );
2329 
2330  /* Give the PHY and MAC time to faff */
2331  mdelay ( 100 );
2332 
2333  /* Reset and reconfigure the XMAC */
2334  rc = falcon_reset_xmac ( efab );
2335  if ( rc )
2336  goto fail2;
2337  falcon_reconfigure_xmac ( efab );
2339  /**
2340  * Now wait for the link to come up. This may take a while
2341  * for some slower PHY's.
2342  */
2343  for (count=0; count<50; count++) {
2344  int link_ok = 1;
2345 
2346  /* Wait a while for the link to come up. */
2347  mdelay ( 100 );
2348  if ((count % 5) == 0)
2349  putchar ( '.' );
2350 
2351  /* Does the PHY think the wire-side link is up? */
2352  link_ok = mdio_clause45_links_ok ( efab );
2353  /* Ensure the XAUI link to the PHY is good */
2354  if ( link_ok ) {
2355  link_ok = falcon_xaui_link_ok ( efab );
2356  if ( !link_ok )
2357  falcon_reset_xaui ( efab );
2358  }
2359 
2360  /* Check fault indication */
2361  if ( link_ok )
2362  link_ok = falcon_xgmii_status ( efab );
2363 
2364  efab->link_up = link_ok;
2365  if ( link_ok ) {
2366  /* unmask the status interrupt */
2367  falcon_mask_status_intr ( efab, 1 );
2368  return 0;
2369  }
2370  }
2371 
2372  /* Link failed to come up, but initialisation was fine. */
2373  rc = -ETIMEDOUT;
2374 
2375 fail2:
2376 fail1:
2377  return rc;
2378 }
2379 
2382 };
2383 
2384 /*******************************************************************************
2385  *
2386  *
2387  * Null PHY handling
2388  *
2389  *
2390  *******************************************************************************/
2391 
2392 static int
2394 {
2395  /* CX4 is always 10000FD only */
2397 
2398  /* There is no PHY! */
2399  return 0;
2400 }
2401 
2404  .mmds = 0,
2405 };
2406 
2407 
2408 /*******************************************************************************
2409  *
2410  *
2411  * Alaska PHY
2412  *
2413  *
2414  *******************************************************************************/
2415 
2416 /**
2417  * Initialise Alaska PHY
2418  *
2419  */
2420 static int
2421 alaska_init ( struct efab_nic *efab )
2422 {
2423  unsigned int advertised, lpa;
2424 
2425  /* Read link up status */
2426  efab->link_up = gmii_link_ok ( efab );
2427 
2428  if ( ! efab->link_up )
2429  return -EIO;
2430 
2431  /* Determine link options from PHY. */
2432  advertised = gmii_autoneg_advertised ( efab );
2433  lpa = gmii_autoneg_lpa ( efab );
2434  efab->link_options = gmii_nway_result ( advertised & lpa );
2435 
2436  return 0;
2437 }
2438 
2440  .init = alaska_init,
2441 };
2442 
2443 /*******************************************************************************
2444  *
2445  *
2446  * xfp
2447  *
2448  *
2449  *******************************************************************************/
2450 
2451 #define XFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \
2452  MDIO_MMDREG_DEVS0_PMAPMD | \
2453  MDIO_MMDREG_DEVS0_PHYXS )
2454 
2455 static int
2457 {
2458  int rc;
2459 
2460  /* Optical link is always 10000FD only */
2462 
2463  /* Reset the PHY */
2465  if ( rc )
2466  return rc;
2467 
2468  return 0;
2469 }
2470 
2473  .mmds = XFP_REQUIRED_DEVS,
2474 };
2475 
2476 /*******************************************************************************
2477  *
2478  *
2479  * txc43128
2480  *
2481  *
2482  *******************************************************************************/
2483 
2484 /* Command register */
2485 #define TXC_GLRGS_GLCMD (0xc004)
2486 #define TXC_GLCMD_LMTSWRST_LBN (14)
2487 
2488 /* Amplitude on lanes 0+1, 2+3 */
2489 #define TXC_ALRGS_ATXAMP0 (0xc041)
2490 #define TXC_ALRGS_ATXAMP1 (0xc042)
2491 /* Bit position of value for lane 0+2, 1+3 */
2492 #define TXC_ATXAMP_LANE02_LBN (3)
2493 #define TXC_ATXAMP_LANE13_LBN (11)
2494 
2495 #define TXC_ATXAMP_1280_mV (0)
2496 #define TXC_ATXAMP_1200_mV (8)
2497 #define TXC_ATXAMP_1120_mV (12)
2498 #define TXC_ATXAMP_1060_mV (14)
2499 #define TXC_ATXAMP_0820_mV (25)
2500 #define TXC_ATXAMP_0720_mV (26)
2501 #define TXC_ATXAMP_0580_mV (27)
2502 #define TXC_ATXAMP_0440_mV (28)
2503 
2504 #define TXC_ATXAMP_0820_BOTH ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \
2505  (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) )
2506 
2507 #define TXC_ATXAMP_DEFAULT (0x6060) /* From databook */
2508 
2509 /* Preemphasis on lanes 0+1, 2+3 */
2510 #define TXC_ALRGS_ATXPRE0 (0xc043)
2511 #define TXC_ALRGS_ATXPRE1 (0xc044)
2512 
2513 #define TXC_ATXPRE_NONE (0)
2514 #define TXC_ATXPRE_DEFAULT (0x1010) /* From databook */
2515 
2516 #define TXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \
2517  MDIO_MMDREG_DEVS0_PMAPMD | \
2518  MDIO_MMDREG_DEVS0_PHYXS )
2519 
2520 static int
2522 {
2523  int val;
2524  int tries = 50;
2525 
2527  val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
2529 
2530  while ( tries--) {
2532  if ( ~val & ( 1 << TXC_GLCMD_LMTSWRST_LBN ) )
2533  return 0;
2534  udelay(1);
2535  }
2536 
2537  EFAB_ERR ( "logic reset failed\n" );
2538 
2539  return -ETIMEDOUT;
2540 }
2541 
2542 static int
2544 {
2545  int rc;
2546 
2547  /* CX4 is always 10000FD only */
2549 
2550  /* reset the phy */
2552  if ( rc )
2553  goto fail1;
2554 
2555  rc = mdio_clause45_check_mmds ( efab );
2556  if ( rc )
2557  goto fail2;
2558 
2559  /* Turn amplitude down and preemphasis off on the host side
2560  * (PHY<->MAC) as this is believed less likely to upset falcon
2561  * and no adverse effects have been noted. It probably also
2562  * saves a picowatt or two */
2563 
2564  /* Turn off preemphasis */
2566  TXC_ATXPRE_NONE );
2568  TXC_ATXPRE_NONE );
2569 
2570  /* Turn down the amplitude */
2575 
2576  /* Set the line side amplitude and preemphasis to the databook
2577  * defaults as an erratum causes them to be 0 on at least some
2578  * PHY rev.s */
2587 
2588  rc = falcon_txc_logic_reset ( efab );
2589  if ( rc )
2590  goto fail3;
2591 
2592  return 0;
2593 
2594 fail3:
2595 fail2:
2596 fail1:
2597  return rc;
2598 }
2599 
2602  .mmds = TXC_REQUIRED_DEVS,
2603 };
2604 
2605 /*******************************************************************************
2606  *
2607  *
2608  * tenxpress
2609  *
2610  *
2611  *******************************************************************************/
2612 
2613 
2614 #define TENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD | \
2615  MDIO_MMDREG_DEVS0_PCS | \
2616  MDIO_MMDREG_DEVS0_PHYXS )
2617 
2618 #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
2619 #define CLK312_EN_LBN 3
2620 #define CLK312_EN_WIDTH 1
2621 
2622 #define PCS_CLOCK_CTRL_REG 0xd801
2623 #define PLL312_RST_N_LBN 2
2624 
2625 /* Special Software reset register */
2626 #define PMA_PMD_EXT_CTRL_REG 49152
2627 #define PMA_PMD_EXT_SSR_LBN 15
2628 
2629 /* Boot status register */
2630 #define PCS_BOOT_STATUS_REG 0xd000
2631 #define PCS_BOOT_FATAL_ERR_LBN 0
2632 #define PCS_BOOT_PROGRESS_LBN 1
2633 #define PCS_BOOT_PROGRESS_WIDTH 2
2634 #define PCS_BOOT_COMPLETE_LBN 3
2635 
2636 #define PCS_SOFT_RST2_REG 0xd806
2637 #define SERDES_RST_N_LBN 13
2638 #define XGXS_RST_N_LBN 12
2639 
2640 static int
2642 {
2643  int count;
2644  uint32_t boot_stat;
2645 
2646  /* Check that the C11 CPU has booted */
2647  for (count=0; count<10; count++) {
2648  boot_stat = falcon_mdio_read ( efab, MDIO_MMD_PCS,
2650  if ( boot_stat & ( 1 << PCS_BOOT_COMPLETE_LBN ) )
2651  return 0;
2652 
2653  udelay(10);
2654  }
2655 
2656  EFAB_ERR ( "C11 failed to boot\n" );
2657  return -ETIMEDOUT;
2658 }
2659 
2660 static int
2662 {
2663  int rc, reg;
2664 
2665  /* 10XPRESS is always 10000FD (at the moment) */
2667 
2668  /* Wait for the blocks to come out of reset */
2669  rc = mdio_clause45_wait_reset_mmds ( efab );
2670  if ( rc )
2671  goto fail1;
2672 
2673  rc = mdio_clause45_check_mmds ( efab );
2674  if ( rc )
2675  goto fail2;
2676 
2677  /* Turn on the clock */
2678  reg = (1 << CLK312_EN_LBN);
2680 
2681  /* Wait 200ms for the PHY to boot */
2682  mdelay(200);
2683 
2684  rc = falcon_tenxpress_check_c11 ( efab );
2685  if ( rc )
2686  goto fail3;
2687 
2688  return 0;
2689 
2690 fail3:
2691 fail2:
2692 fail1:
2693  return rc;
2694 }
2695 
2698  .mmds = TENXPRESS_REQUIRED_DEVS,
2699 };
2700 
2701 /*******************************************************************************
2702  *
2703  *
2704  * PM8358
2705  *
2706  *
2707  *******************************************************************************/
2708 
2709 /* The PM8358 just presents a DTE XS */
2710 #define PM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS)
2711 
2712 /* PHY-specific definitions */
2713 /* Master ID and Global Performance Monitor Update */
2714 #define PMC_MASTER_REG (0xd000)
2715 /* Analog Tx Rx settings under software control */
2716 #define PMC_MASTER_ANLG_CTRL (1<< 11)
2717 
2718 /* Master Configuration register 2 */
2719 #define PMC_MCONF2_REG (0xd002)
2720 /* Drive Tx off centre of data eye (1) vs. clock edge (0) */
2721 #define PMC_MCONF2_TEDGE (1 << 2)
2722 /* Drive Rx off centre of data eye (1) vs. clock edge (0) */
2723 #define PMC_MCONF2_REDGE (1 << 3)
2724 
2725 /* Analog Rx settings */
2726 #define PMC_ANALOG_RX_CFG0 (0xd025)
2727 #define PMC_ANALOG_RX_CFG1 (0xd02d)
2728 #define PMC_ANALOG_RX_CFG2 (0xd035)
2729 #define PMC_ANALOG_RX_CFG3 (0xd03d)
2730 
2731 
2732 #define PMC_ANALOG_RX_TERM (1 << 15) /* Bit 15 of RX CFG: 0 for 100 ohms float,
2733  1 for 50 to 1.2V */
2734 #define PMC_ANALOG_RX_EQ_MASK (3 << 8)
2735 #define PMC_ANALOG_RX_EQ_NONE (0 << 8)
2736 #define PMC_ANALOG_RX_EQ_HALF (1 << 8)
2737 #define PMC_ANALOG_RX_EQ_FULL (2 << 8)
2738 #define PMC_ANALOG_RX_EQ_RSVD (3 << 8)
2739 
2740 static int
2742 {
2743  int rc, reg, i;
2744 
2745  /* This is a XAUI retimer part */
2747 
2749  if ( rc )
2750  return rc;
2751 
2752  /* Enable software control of analogue settings */
2756 
2757  /* Turn rx eq on for all channels */
2758  for (i=0; i< 3; i++) {
2759  /* The analog CFG registers are evenly spaced 8 apart */
2761  reg = falcon_mdio_read ( efab, MDIO_MMD_DTEXS, addr );
2764  }
2765 
2766  /* Set TEDGE, clear REDGE */
2770 
2771  return 0;
2772 }
2773 
2776  .mmds = PM8358_REQUIRED_DEVS,
2777 };
2778 
2779 /*******************************************************************************
2780  *
2781  *
2782  * SFE4001 support
2783  *
2784  *
2785  *******************************************************************************/
2786 
2787 #define MAX_TEMP_THRESH 90
2788 
2789 /* I2C Expander */
2790 #define PCA9539 0x74
2791 
2792 #define P0_IN 0x00
2793 #define P0_OUT 0x02
2794 #define P0_CONFIG 0x06
2795 
2796 #define P0_EN_1V0X_LBN 0
2797 #define P0_EN_1V0X_WIDTH 1
2798 #define P0_EN_1V2_LBN 1
2799 #define P0_EN_1V2_WIDTH 1
2800 #define P0_EN_2V5_LBN 2
2801 #define P0_EN_2V5_WIDTH 1
2802 #define P0_EN_3V3X_LBN 3
2803 #define P0_EN_3V3X_WIDTH 1
2804 #define P0_EN_5V_LBN 4
2805 #define P0_EN_5V_WIDTH 1
2806 #define P0_X_TRST_LBN 6
2807 #define P0_X_TRST_WIDTH 1
2808 
2809 #define P1_IN 0x01
2810 #define P1_CONFIG 0x07
2811 
2812 #define P1_AFE_PWD_LBN 0
2813 #define P1_AFE_PWD_WIDTH 1
2814 #define P1_DSP_PWD25_LBN 1
2815 #define P1_DSP_PWD25_WIDTH 1
2816 #define P1_SPARE_LBN 4
2817 #define P1_SPARE_WIDTH 4
2818 
2819 /* Temperature Sensor */
2820 #define MAX6647 0x4e
2821 
2822 #define RSL 0x02
2823 #define RLHN 0x05
2824 #define WLHO 0x0b
2825 
2826 static struct i2c_device i2c_pca9539 = {
2827  .dev_addr = PCA9539,
2828  .dev_addr_len = 1,
2829  .word_addr_len = 1,
2830 };
2831 
2832 
2833 static struct i2c_device i2c_max6647 = {
2834  .dev_addr = MAX6647,
2835  .dev_addr_len = 1,
2836  .word_addr_len = 1,
2837 };
2838 
2839 static int
2840 sfe4001_init ( struct efab_nic *efab )
2841 {
2842  struct i2c_interface *i2c = &efab->i2c_bb.i2c;
2843  efab_dword_t reg;
2844  uint8_t in, cfg, out;
2845  int count, rc;
2846 
2847  EFAB_LOG ( "Initialise SFE4001 board\n" );
2848 
2849  /* Ensure XGXS and XAUI SerDes are held in reset */
2851  FCN_XX_PWRDNA_EN, 1,
2852  FCN_XX_PWRDNB_EN, 1,
2853  FCN_XX_RSTPLLAB_EN, 1,
2854  FCN_XX_RESETA_EN, 1,
2855  FCN_XX_RESETB_EN, 1,
2856  FCN_XX_RSTXGXSRX_EN, 1,
2857  FCN_XX_RSTXGXSTX_EN, 1 );
2859  udelay(10);
2860 
2861  /* Set DSP over-temperature alert threshold */
2862  cfg = MAX_TEMP_THRESH;
2863  rc = i2c->write ( i2c, &i2c_max6647, WLHO, &cfg, EFAB_BYTE );
2864  if ( rc )
2865  goto fail1;
2866 
2867  /* Read it back and verify */
2868  rc = i2c->read ( i2c, &i2c_max6647, RLHN, &in, EFAB_BYTE );
2869  if ( rc )
2870  goto fail2;
2871 
2872  if ( in != MAX_TEMP_THRESH ) {
2873  EFAB_ERR ( "Unable to verify MAX6647 limit (requested=%d "
2874  "confirmed=%d)\n", cfg, in );
2875  rc = -EIO;
2876  goto fail3;
2877  }
2878 
2879  /* Clear any previous over-temperature alert */
2880  rc = i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
2881  if ( rc )
2882  goto fail4;
2883 
2884  /* Enable port 0 and 1 outputs on IO expander */
2885  cfg = 0x00;
2886  rc = i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
2887  if ( rc )
2888  goto fail5;
2889  cfg = 0xff & ~(1 << P1_SPARE_LBN);
2890  rc = i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
2891  if ( rc )
2892  goto fail6;
2893 
2894  /* Turn all power off then wait 1 sec. This ensures PHY is reset */
2895  out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) |
2896  (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) |
2897  (0 << P0_EN_1V0X_LBN));
2898 
2899  rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
2900  if ( rc )
2901  goto fail7;
2902 
2903  mdelay(1000);
2904 
2905  for (count=0; count<20; count++) {
2906  /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */
2907  out = 0xff & ~( (1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) |
2908  (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) |
2909  (1 << P0_X_TRST_LBN) );
2910 
2911  rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
2912  if ( rc )
2913  goto fail8;
2914 
2915  mdelay ( 10 );
2916 
2917  /* Turn on the 1V power rail */
2918  out &= ~( 1 << P0_EN_1V0X_LBN );
2919  rc = i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
2920  if ( rc )
2921  goto fail9;
2922 
2923  EFAB_LOG ( "Waiting for power...(attempt %d)\n", count);
2924  mdelay ( 1000 );
2925 
2926  /* Check DSP is powered */
2927  rc = i2c->read ( i2c, &i2c_pca9539, P1_IN, &in, EFAB_BYTE );
2928  if ( rc )
2929  goto fail10;
2930 
2931  if ( in & ( 1 << P1_AFE_PWD_LBN ) )
2932  return 0;
2933  }
2934 
2935  rc = -ETIMEDOUT;
2936 
2937 fail10:
2938 fail9:
2939 fail8:
2940 fail7:
2941  /* Turn off power rails */
2942  out = 0xff;
2943  (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
2944  /* Disable port 1 outputs on IO expander */
2945  out = 0xff;
2946  (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
2947 fail6:
2948  /* Disable port 0 outputs */
2949  out = 0xff;
2950  (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &out, EFAB_BYTE );
2951 fail5:
2952 fail4:
2953 fail3:
2954 fail2:
2955 fail1:
2956  EFAB_ERR ( "Failed initialising SFE4001 board\n" );
2957  return rc;
2958 }
2959 
2960 static void
2961 sfe4001_fini ( struct efab_nic *efab )
2962 {
2963  struct i2c_interface *i2c = &efab->i2c_bb.i2c;
2964  uint8_t in, cfg, out;
2965 
2966  EFAB_ERR ( "Turning off SFE4001\n" );
2967 
2968  /* Turn off all power rails */
2969  out = 0xff;
2970  (void) i2c->write ( i2c, &i2c_pca9539, P0_OUT, &out, EFAB_BYTE );
2971 
2972  /* Disable port 1 outputs on IO expander */
2973  cfg = 0xff;
2974  (void) i2c->write ( i2c, &i2c_pca9539, P1_CONFIG, &cfg, EFAB_BYTE );
2975 
2976  /* Disable port 0 outputs on IO expander */
2977  cfg = 0xff;
2978  (void) i2c->write ( i2c, &i2c_pca9539, P0_CONFIG, &cfg, EFAB_BYTE );
2979 
2980  /* Clear any over-temperature alert */
2981  (void) i2c->read ( i2c, &i2c_max6647, RSL, &in, EFAB_BYTE );
2982 }
2983 
2985  .init = sfe4001_init,
2986  .fini = sfe4001_fini,
2987 };
2988 
2989 static int sfe4002_init ( struct efab_nic *efab __attribute__((unused)) )
2990 {
2991  return 0;
2992 }
2993 static void sfe4002_fini ( struct efab_nic *efab __attribute__((unused)) )
2994 {
2995 }
2996 
2998  .init = sfe4002_init,
2999  .fini = sfe4002_fini,
3000 };
3001 
3002 static int sfe4003_init ( struct efab_nic *efab __attribute__((unused)) )
3003 {
3004  return 0;
3005 }
3006 static void sfe4003_fini ( struct efab_nic *efab __attribute__((unused)) )
3007 {
3008 }
3009 
3011  .init = sfe4003_init,
3012  .fini = sfe4003_fini,
3013 };
3014 
3015 /*******************************************************************************
3016  *
3017  *
3018  * Hardware initialisation
3019  *
3020  *
3021  *******************************************************************************/
3022 
3023 static void
3025 {
3026  /* We don't bother cleaning up the buffer table entries -
3027  * we're hardly limited */
3028  free_dma ( p, EFAB_BUF_ALIGN );
3029 }
3030 
3031 static void*
3033  struct efab_special_buffer *entry )
3034 {
3035  void* buffer;
3036  int remaining;
3037  efab_qword_t buf_desc;
3038  unsigned long dma_addr;
3039 
3040  /* Allocate the buffer, aligned on a buffer address boundary */
3042  if ( ! buffer )
3043  return NULL;
3044 
3045  /* Push buffer table entries to back the buffer */
3046  entry->id = efab->buffer_head;
3047  entry->dma_addr = dma_addr = virt_to_bus ( buffer );
3048  assert ( ( dma_addr & ( EFAB_BUF_ALIGN - 1 ) ) == 0 );
3049 
3050  remaining = bytes;
3051  while ( remaining > 0 ) {
3052  EFAB_POPULATE_QWORD_3 ( buf_desc,
3053  FCN_IP_DAT_BUF_SIZE, FCN_IP_DAT_BUF_SIZE_4K,
3054  FCN_BUF_ADR_FBUF, ( dma_addr >> 12 ),
3055  FCN_BUF_OWNER_ID_FBUF, 0 );
3056 
3057  falcon_write_sram ( efab, &buf_desc, efab->buffer_head );
3058 
3059  ++efab->buffer_head;
3060  dma_addr += EFAB_BUF_ALIGN;
3061  remaining -= EFAB_BUF_ALIGN;
3062  }
3063 
3064  EFAB_TRACE ( "Allocated 0x%x bytes at %p backed by buffer table "
3065  "entries 0x%x..0x%x\n", bytes, buffer, entry->id,
3066  efab->buffer_head - 1 );
3067 
3068  return buffer;
3069 }
3070 
3071 static void
3073 {
3074  efab_oword_t blanko, temp;
3075  int offset;
3076 
3077  EFAB_ZERO_OWORD ( blanko );
3078 
3079  /* Clear the address region register */
3080  EFAB_POPULATE_OWORD_4 ( temp,
3081  FCN_ADR_REGION0, 0,
3082  FCN_ADR_REGION1, ( 1 << 16 ),
3083  FCN_ADR_REGION2, ( 2 << 16 ),
3084  FCN_ADR_REGION3, ( 3 << 16 ) );
3085  falcon_write ( efab, &temp, FCN_ADR_REGION_REG_KER );
3086 
3087  EFAB_TRACE ( "Clearing filter and RSS tables\n" );
3088 
3089  for ( offset = FCN_RX_FILTER_TBL0 ;
3091  offset += 0x10 ) {
3092  falcon_write ( efab, &blanko, offset );
3093  }
3094 
3095  EFAB_TRACE ( "Wiping buffer tables\n" );
3096 
3097  /* Notice the 8 byte access mode */
3098  for ( offset = 0x2800000 ;
3099  offset < 0x3000000 ;
3100  offset += 0x8) {
3101  _falcon_writel ( efab, 0, offset );
3102  _falcon_writel ( efab, 0, offset + 4 );
3103  wmb();
3104  }
3105 }
3106 
3107 static int
3108 falcon_reset ( struct efab_nic *efab )
3109 {
3110  efab_oword_t glb_ctl_reg_ker;
3111 
3112  /* Initiate software reset */
3113  EFAB_POPULATE_OWORD_6 ( glb_ctl_reg_ker,
3114  FCN_PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
3115  FCN_PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
3116  FCN_PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
3117  FCN_EE_RST_CTL, EXCLUDE_FROM_RESET,
3118  FCN_EXT_PHY_RST_DUR, 0x7, /* 10ms */
3119  FCN_SWRST, 1 );
3120 
3121  falcon_write ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
3122 
3123  /* Allow 50ms for reset */
3124  mdelay ( 50 );
3125 
3126  /* Check for device reset complete */
3127  falcon_read ( efab, &glb_ctl_reg_ker, FCN_GLB_CTL_REG_KER );
3128  if ( EFAB_OWORD_FIELD ( glb_ctl_reg_ker, FCN_SWRST ) != 0 ) {
3129  EFAB_ERR ( "Reset failed\n" );
3130  return -ETIMEDOUT;
3131  }
3132 
3133  if ( ( efab->pci_revision == FALCON_REV_B0 ) && !efab->is_asic ) {
3134  clear_b0_fpga_memories ( efab );
3135  }
3136 
3137  return 0;
3138 }
3139 
3140 /** Offset of MAC address within EEPROM or Flash */
3141 #define FALCON_MAC_ADDRESS_OFFSET 0x310
3142 
3143 /*
3144  * Falcon EEPROM structure
3145  */
3146 #define SF_NV_CONFIG_BASE 0x300
3147 #define SF_NV_CONFIG_EXTRA 0xA0
3148 
3158 };
3159 
3164  union {
3166  } ver_specific;
3167 };
3168 
3169 #define BOARD_TYPE(_rev) (_rev >> 8)
3170 
3171 static void
3172 falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci )
3173 {
3174  efab_oword_t altera_build, nic_stat;
3175  int fpga_version;
3176  uint8_t revision;
3177 
3178  /* PCI revision */
3180  efab->pci_revision = revision;
3181 
3182  /* Asic vs FPGA */
3183  falcon_read ( efab, &altera_build, FCN_ALTERA_BUILD_REG_KER );
3184  fpga_version = EFAB_OWORD_FIELD ( altera_build, FCN_VER_ALL );
3185  efab->is_asic = (fpga_version == 0);
3186 
3187  /* MAC and PCI type */
3188  falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
3189  if ( efab->pci_revision == FALCON_REV_B0 ) {
3190  efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
3191  }
3192  else if ( efab->is_asic ) {
3193  efab->phy_10g = EFAB_OWORD_FIELD ( nic_stat, FCN_STRAP_10G );
3194  }
3195  else {
3196  int minor = EFAB_OWORD_FIELD ( altera_build, FCN_VER_MINOR );
3197  efab->phy_10g = ( minor == 0x14 );
3198  }
3199 }
3200 
3201 static void
3202 falcon_init_spi_device ( struct efab_nic *efab, struct spi_device *spi )
3203 {
3204  /* Falcon's SPI interface only supports reads/writes of up to 16 bytes.
3205  * Reduce the nvs block size down to satisfy this - which means callers
3206  * should use the nvs_* functions rather than spi_*. */
3207  if ( spi->nvs.block_size > FALCON_SPI_MAX_LEN )
3209 
3210  spi->bus = &efab->spi_bus;
3211  efab->spi = spi;
3212 }
3213 
3214 static int
3215 falcon_probe_spi ( struct efab_nic *efab )
3216 {
3217  efab_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
3218  int has_flash, has_eeprom, ad9bit;
3219 
3220  falcon_read ( efab, &nic_stat, FCN_NIC_STAT_REG );
3221  falcon_read ( efab, &gpio_ctl, FCN_GPIO_CTL_REG_KER );
3222  falcon_read ( efab, &ee_vpd_cfg, FCN_EE_VPD_CFG_REG );
3223 
3224  /* determine if FLASH / EEPROM is present */
3225  if ( ( efab->pci_revision >= FALCON_REV_B0 ) || efab->is_asic ) {
3226  has_flash = EFAB_OWORD_FIELD ( nic_stat, FCN_SF_PRST );
3227  has_eeprom = EFAB_OWORD_FIELD ( nic_stat, FCN_EE_PRST );
3228  } else {
3229  has_flash = EFAB_OWORD_FIELD ( gpio_ctl, FCN_FLASH_PRESENT );
3230  has_eeprom = EFAB_OWORD_FIELD ( gpio_ctl, FCN_EEPROM_PRESENT );
3231  }
3232  ad9bit = EFAB_OWORD_FIELD ( ee_vpd_cfg, FCN_EE_VPD_EN_AD9_MODE );
3233 
3234  /* Configure the SPI and I2C bus */
3235  efab->spi_bus.rw = falcon_spi_rw;
3237 
3238  /* Configure the EEPROM SPI device. Generally, an Atmel 25040
3239  * (or similar) is used, but this is only possible if there is also
3240  * a flash device present to store the boot-time chip configuration.
3241  */
3242  if ( has_eeprom ) {
3243  if ( has_flash && ad9bit )
3244  init_at25040 ( &efab->spi_eeprom );
3245  else
3246  init_mc25xx640 ( &efab->spi_eeprom );
3247  falcon_init_spi_device ( efab, &efab->spi_eeprom );
3248  }
3249 
3250  /* Configure the FLASH SPI device */
3251  if ( has_flash ) {
3252  init_at25f1024 ( &efab->spi_flash );
3253  falcon_init_spi_device ( efab, &efab->spi_flash );
3254  }
3255 
3256  EFAB_LOG ( "flash is %s, EEPROM is %s%s\n",
3257  ( has_flash ? "present" : "absent" ),
3258  ( has_eeprom ? "present " : "absent" ),
3259  ( has_eeprom ? (ad9bit ? "(9bit)" : "(16bit)") : "") );
3260 
3261  /* The device MUST have flash or eeprom */
3262  if ( ! efab->spi ) {
3263  EFAB_ERR ( "Device appears to have no flash or eeprom\n" );
3264  return -EIO;
3265  }
3266 
3267  /* If the device has EEPROM attached, then advertise NVO space */
3268  if ( has_eeprom ) {
3269  nvo_init ( &efab->nvo, &efab->spi_eeprom.nvs, 0x100, 0xf0,
3270  NULL, &efab->netdev->refcnt );
3271  }
3272 
3273  return 0;
3274 }
3275 
3276 static int
3278 {
3279  struct nvs_device *nvs = &efab->spi->nvs;
3280  struct falcon_nv_extra nv;
3281  int rc, board_revision;
3282 
3283  /* Read the MAC address */
3285  efab->mac_addr, ETH_ALEN );
3286  if ( rc )
3287  return rc;
3288 
3289  /* Poke through the NVRAM structure for the PHY type. */
3291  &nv, sizeof ( nv ) );
3292  if ( rc )
3293  return rc;
3294 
3295  /* Handle each supported NVRAM version */
3296  if ( ( le16_to_cpu ( nv.magicnumber ) == FCN_NV_MAGIC_NUMBER ) &&
3297  ( le16_to_cpu ( nv.structure_version ) >= 2 ) ) {
3298  struct falcon_nv_config_ver2* ver2 = &nv.ver_specific.ver2;
3299 
3300  /* Get the PHY type */
3301  efab->phy_addr = le16_to_cpu ( ver2->port0_phy_addr );
3302  efab->phy_type = le16_to_cpu ( ver2->port0_phy_type );
3304  }
3305  else {
3306  EFAB_ERR ( "NVram is not recognised\n" );
3307  return -EINVAL;
3308  }
3309 
3310  efab->board_type = BOARD_TYPE ( board_revision );
3311 
3312  EFAB_TRACE ( "Falcon board %d phy %d @ addr %d\n",
3313  efab->board_type, efab->phy_type, efab->phy_addr );
3314 
3315  /* Patch in the board operations */
3316  switch ( efab->board_type ) {
3317  case EFAB_BOARD_SFE4001:
3318  efab->board_op = &sfe4001_ops;
3319  break;
3320  case EFAB_BOARD_SFE4002:
3321  efab->board_op = &sfe4002_ops;
3322  break;
3323  case EFAB_BOARD_SFE4003:
3324  efab->board_op = &sfe4003_ops;
3325  break;
3326  default:
3327  EFAB_ERR ( "Unrecognised board type\n" );
3328  return -EINVAL;
3329  }
3330 
3331  /* Patch in MAC operations */
3332  if ( efab->phy_10g )
3333  efab->mac_op = &falcon_xmac_operations;
3334  else
3335  efab->mac_op = &falcon_gmac_operations;
3336 
3337  /* Hook in the PHY ops */
3338  switch ( efab->phy_type ) {
3339  case PHY_TYPE_10XPRESS:
3341  break;
3342  case PHY_TYPE_CX4:
3343  efab->phy_op = &falcon_xaui_phy_ops;
3344  break;
3345  case PHY_TYPE_XFP:
3346  efab->phy_op = &falcon_xfp_phy_ops;
3347  break;
3348  case PHY_TYPE_CX4_RTMR:
3349  efab->phy_op = &falcon_txc_phy_ops;
3350  break;
3351  case PHY_TYPE_PM8358:
3352  efab->phy_op = &falcon_pm8358_phy_ops;
3353  break;
3354  case PHY_TYPE_1GIG_ALASKA:
3355  efab->phy_op = &falcon_alaska_phy_ops;
3356  break;
3357  default:
3358  EFAB_ERR ( "Unknown PHY type: %d\n", efab->phy_type );
3359  return -EINVAL;
3360  }
3361 
3362  return 0;
3363 }
3364 
3365 static int
3366 falcon_init_sram ( struct efab_nic *efab )
3367 {
3368  efab_oword_t reg;
3369  int count;
3370 
3371  /* use card in internal SRAM mode */
3372  falcon_read ( efab, &reg, FCN_NIC_STAT_REG );
3373  EFAB_SET_OWORD_FIELD ( reg, FCN_ONCHIP_SRAM, 1 );
3374  falcon_write ( efab, &reg, FCN_NIC_STAT_REG );
3375 
3376  /* Deactivate any external SRAM that might be present */
3378  FCN_GPIO1_OEN, 1,
3379  FCN_GPIO1_OUT, 1 );
3381 
3382  /* Initiate SRAM reset */
3384  FCN_SRAM_OOB_BT_INIT_EN, 1,
3385  FCN_SRM_NUM_BANKS_AND_BANK_SIZE, 0 );
3386  falcon_write ( efab, &reg, FCN_SRM_CFG_REG_KER );
3387 
3388  /* Wait for SRAM reset to complete */
3389  count = 0;
3390  do {
3391  /* SRAM reset is slow; expect around 16ms */
3392  mdelay ( 20 );
3393 
3394  /* Check for reset complete */
3395  falcon_read ( efab, &reg, FCN_SRM_CFG_REG_KER );
3396  if ( !EFAB_OWORD_FIELD ( reg, FCN_SRAM_OOB_BT_INIT_EN ) )
3397  return 0;
3398  } while (++count < 20); /* wait up to 0.4 sec */
3399 
3400  EFAB_ERR ( "timed out waiting for SRAM reset\n");
3401  return -ETIMEDOUT;
3402 }
3403 
3404 static void
3405 falcon_setup_nic ( struct efab_nic *efab )
3406 {
3407  efab_dword_t timer_cmd;
3408  efab_oword_t reg;
3409  int tx_fc, xoff_thresh, xon_thresh;
3410 
3411  /* bug5129: Clear the parity enables on the TX data fifos as
3412  * they produce false parity errors because of timing issues
3413  */
3414  falcon_read ( efab, &reg, FCN_SPARE_REG_KER );
3415  EFAB_SET_OWORD_FIELD ( reg, FCN_MEM_PERR_EN_TX_DATA, 0 );
3416  falcon_write ( efab, &reg, FCN_SPARE_REG_KER );
3417 
3418  /* Set up TX and RX descriptor caches in SRAM */
3419  EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR, 0x130000 );
3421  EFAB_POPULATE_OWORD_1 ( reg, FCN_TX_DC_SIZE, 1 /* 16 descriptors */ );
3423  EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_RX_DC_BASE_ADR, 0x100000 );
3425  EFAB_POPULATE_OWORD_1 ( reg, FCN_RX_DC_SIZE, 2 /* 32 descriptors */ );
3427 
3428  /* Set number of RSS CPUs
3429  * bug7244: Increase filter depth to reduce RX_RESET likelihood
3430  */
3432  FCN_NUM_KER, 0,
3433  FCN_UDP_FULL_SRCH_LIMIT, 8,
3434  FCN_UDP_WILD_SRCH_LIMIT, 8,
3435  FCN_TCP_WILD_SRCH_LIMIT, 8,
3436  FCN_TCP_FULL_SRCH_LIMIT, 8);
3438  udelay ( 1000 );
3439 
3440  /* Setup RX. Wait for descriptor is broken and must
3441  * be disabled. RXDP recovery shouldn't be needed, but is.
3442  * disable ISCSI parsing because we don't need it
3443  */
3445  EFAB_SET_OWORD_FIELD ( reg, FCN_RX_NODESC_WAIT_DIS, 1 );
3446  EFAB_SET_OWORD_FIELD ( reg, FCN_RX_RECOVERY_EN, 1 );
3447  EFAB_SET_OWORD_FIELD ( reg, FCN_RX_ISCSI_DIS, 1 );
3449 
3450  /* Determine recommended flow control settings. *
3451  * Flow control is qualified on B0 and A1/1G, not on A1/10G */
3452  if ( efab->pci_revision == FALCON_REV_B0 ) {
3453  tx_fc = 1;
3454  xoff_thresh = 54272; /* ~80Kb - 3*max MTU */
3455  xon_thresh = 27648; /* ~3*max MTU */
3456  }
3457  else if ( !efab->phy_10g ) {
3458  tx_fc = 1;
3459  xoff_thresh = 2048;
3460  xon_thresh = 512;
3461  }
3462  else {
3463  tx_fc = xoff_thresh = xon_thresh = 0;
3464  }
3465 
3466  /* Setup TX and RX */
3467  falcon_read ( efab, &reg, FCN_TX_CFG2_REG_KER );
3468  EFAB_SET_OWORD_FIELD ( reg, FCN_TX_DIS_NON_IP_EV, 1 );
3469  falcon_write ( efab, &reg, FCN_TX_CFG2_REG_KER );
3470 
3471  falcon_read ( efab, &reg, FCN_RX_CFG_REG_KER );
3472  EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_USR_BUF_SIZE,
3473  (3*4096) / 32 );
3474  if ( efab->pci_revision == FALCON_REV_B0)
3475  EFAB_SET_OWORD_FIELD ( reg, FCN_RX_INGR_EN_B0, 1 );
3476  EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XON_MAC_TH,
3477  xon_thresh / 256);
3478  EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_TH,
3479  xoff_thresh / 256);
3480  EFAB_SET_OWORD_FIELD_VER ( efab, reg, FCN_RX_XOFF_MAC_EN, tx_fc);
3481  falcon_write ( efab, &reg, FCN_RX_CFG_REG_KER );
3482 
3483  /* Set timer register */
3484  EFAB_POPULATE_DWORD_2 ( timer_cmd,
3485  FCN_TIMER_MODE, FCN_TIMER_MODE_DIS,
3486  FCN_TIMER_VAL, 0 );
3487  falcon_writel ( efab, &timer_cmd, FCN_TIMER_CMD_REG_KER );
3488 }
3489 
3490 static void
3492 {
3493  struct efab_ev_queue *ev_queue = &efab->ev_queue;
3494  struct efab_rx_queue *rx_queue = &efab->rx_queue;
3495  struct efab_tx_queue *tx_queue = &efab->tx_queue;
3496 
3497  efab_oword_t reg;
3498  int jumbo;
3499 
3500  /* Initialise the ptrs */
3501  tx_queue->read_ptr = tx_queue->write_ptr = 0;
3502  rx_queue->read_ptr = rx_queue->write_ptr = 0;
3503  ev_queue->read_ptr = 0;
3504 
3505  /* Push the event queue to the hardware */
3507  FCN_EVQ_EN, 1,
3508  FCN_EVQ_SIZE, FQS(FCN_EVQ, EFAB_EVQ_SIZE),
3509  FCN_EVQ_BUF_BASE_ID, ev_queue->entry.id );
3510  falcon_write ( efab, &reg,
3511  FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
3512 
3513  /* Push the tx queue to the hardware */
3515  FCN_TX_DESCQ_EN, 1,
3516  FCN_TX_ISCSI_DDIG_EN, 0,
3517  FCN_TX_ISCSI_DDIG_EN, 0,
3518  FCN_TX_DESCQ_BUF_BASE_ID, tx_queue->entry.id,
3519  FCN_TX_DESCQ_EVQ_ID, 0,
3520  FCN_TX_DESCQ_SIZE, FQS(FCN_TX_DESCQ, EFAB_TXD_SIZE),
3521  FCN_TX_DESCQ_TYPE, 0 /* kernel queue */,
3522  FCN_TX_NON_IP_DROP_DIS_B0, 1 );
3523  falcon_write ( efab, &reg,
3524  FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
3525 
3526  /* Push the rx queue to the hardware */
3527  jumbo = ( efab->pci_revision == FALCON_REV_B0 ) ? 0 : 1;
3529  FCN_RX_ISCSI_DDIG_EN, 0,
3530  FCN_RX_ISCSI_HDIG_EN, 0,
3531  FCN_RX_DESCQ_BUF_BASE_ID, rx_queue->entry.id,
3532  FCN_RX_DESCQ_EVQ_ID, 0,
3533  FCN_RX_DESCQ_SIZE, FQS(FCN_RX_DESCQ, EFAB_RXD_SIZE),
3534  FCN_RX_DESCQ_TYPE, 0 /* kernel queue */,
3535  FCN_RX_DESCQ_JUMBO, jumbo,
3536  FCN_RX_DESCQ_EN, 1 );
3537  falcon_write ( efab, &reg,
3538  FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
3539 
3540  /* Program INT_ADR_REG_KER */
3542  FCN_INT_ADR_KER, virt_to_bus ( &efab->int_ker ) );
3543  falcon_write ( efab, &reg, FCN_INT_ADR_REG_KER );
3544 
3545  /* Ack the event queue */
3546  falcon_eventq_read_ack ( efab, ev_queue );
3547 }
3548 
3549 static void
3551 {
3552  efab_oword_t cmd;
3553 
3554  /* Disable interrupts */
3555  falcon_interrupts ( efab, 0, 0 );
3556 
3557  /* Flush the dma queues */
3559  FCN_TX_FLUSH_DESCQ_CMD, 1,
3560  FCN_TX_FLUSH_DESCQ, 0 );
3561  falcon_write ( efab, &cmd,
3562  FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
3563 
3565  FCN_RX_FLUSH_DESCQ_CMD, 1,
3566  FCN_RX_FLUSH_DESCQ, 0 );
3567  falcon_write ( efab, &cmd,
3568  FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
3569 
3570  mdelay ( 100 );
3571 
3572  /* Remove descriptor rings from card */
3573  EFAB_ZERO_OWORD ( cmd );
3574  falcon_write ( efab, &cmd,
3575  FCN_REVISION_REG ( efab, FCN_TX_DESC_PTR_TBL_KER ) );
3576  falcon_write ( efab, &cmd,
3577  FCN_REVISION_REG ( efab, FCN_RX_DESC_PTR_TBL_KER ) );
3578  falcon_write ( efab, &cmd,
3579  FCN_REVISION_REG ( efab, FCN_EVQ_PTR_TBL_KER ) );
3580 }
3581 
3582 /*******************************************************************************
3583  *
3584  *
3585  * Hardware rx path
3586  *
3587  *
3588  *******************************************************************************/
3589 
3590 static void
3592 {
3594  FCN_RX_KER_BUF_SIZE, EFAB_RX_BUF_SIZE,
3595  FCN_RX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
3596 }
3597 
3598 static void
3599 falcon_notify_rx_desc ( struct efab_nic *efab, struct efab_rx_queue *rx_queue )
3600 {
3601  efab_dword_t reg;
3602  int ptr = rx_queue->write_ptr % EFAB_RXD_SIZE;
3603 
3604  EFAB_POPULATE_DWORD_1 ( reg, FCN_RX_DESC_WPTR_DWORD, ptr );
3606 }
3607 
3608 
3609 /*******************************************************************************
3610  *
3611  *
3612  * Hardware tx path
3613  *
3614  *
3615  *******************************************************************************/
3616 
3617 static void
3619 {
3621  FCN_TX_KER_BYTE_CNT, iob_len ( iob ),
3622  FCN_TX_KER_BUF_ADR, virt_to_bus ( iob->data ) );
3623 }
3624 
3625 static void
3627  struct efab_tx_queue *tx_queue )
3628 {
3629  efab_dword_t reg;
3630  int ptr = tx_queue->write_ptr % EFAB_TXD_SIZE;
3631 
3632  EFAB_POPULATE_DWORD_1 ( reg, FCN_TX_DESC_WPTR_DWORD, ptr );
3634 }
3635 
3636 
3637 /*******************************************************************************
3638  *
3639  *
3640  * Software receive interface
3641  *
3642  *
3643  *******************************************************************************/
3644 
3645 static int
3647  struct efab_rx_queue *rx_queue )
3648 {
3649  int fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
3650  int space = EFAB_NUM_RX_DESC - fill_level - 1;
3651  int pushed = 0;
3652 
3653  while ( space ) {
3654  int buf_id = rx_queue->write_ptr % EFAB_NUM_RX_DESC;
3655  int desc_id = rx_queue->write_ptr % EFAB_RXD_SIZE;
3656  struct io_buffer *iob;
3658 
3659  assert ( rx_queue->buf[buf_id] == NULL );
3660  iob = alloc_iob ( EFAB_RX_BUF_SIZE );
3661  if ( !iob )
3662  break;
3663 
3664  EFAB_TRACE ( "pushing rx_buf[%d] iob %p data %p\n",
3665  buf_id, iob, iob->data );
3666 
3667  rx_queue->buf[buf_id] = iob;
3668  rxd = rx_queue->ring + desc_id;
3669  falcon_build_rx_desc ( rxd, iob );
3670  ++rx_queue->write_ptr;
3671  ++pushed;
3672  --space;
3673  }
3674 
3675  if ( pushed ) {
3676  /* Push the ptr to hardware */
3677  falcon_notify_rx_desc ( efab, rx_queue );
3678 
3679  fill_level = rx_queue->write_ptr - rx_queue->read_ptr;
3680  EFAB_TRACE ( "pushed %d rx buffers to fill level %d\n",
3681  pushed, fill_level );
3682  }
3683 
3684  if ( fill_level == 0 )
3685  return -ENOMEM;
3686  return 0;
3687 }
3688 
3689 static void
3690 efab_receive ( struct efab_nic *efab, unsigned int id, int len, int drop )
3691 {
3692  struct efab_rx_queue *rx_queue = &efab->rx_queue;
3693  struct io_buffer *iob;
3694  unsigned int read_ptr = rx_queue->read_ptr % EFAB_RXD_SIZE;
3695  unsigned int buf_ptr = rx_queue->read_ptr % EFAB_NUM_RX_DESC;
3696 
3697  assert ( id == read_ptr );
3698 
3699  /* Pop this rx buffer out of the software ring */
3700  iob = rx_queue->buf[buf_ptr];
3701  rx_queue->buf[buf_ptr] = NULL;
3702 
3703  EFAB_TRACE ( "popping rx_buf[%d] iob %p data %p with %d bytes %s\n",
3704  id, iob, iob->data, len, drop ? "bad" : "ok" );
3705 
3706  /* Pass the packet up if required */
3707  if ( drop )
3708  free_iob ( iob );
3709  else {
3710  iob_put ( iob, len );
3711  netdev_rx ( efab->netdev, iob );
3712  }
3713 
3714  ++rx_queue->read_ptr;
3715 }
3716 
3717 /*******************************************************************************
3718  *
3719  *
3720  * Software transmit interface
3721  *
3722  *
3723  *******************************************************************************/
3724 
3725 static int
3726 efab_transmit ( struct net_device *netdev, struct io_buffer *iob )
3727 {
3728  struct efab_nic *efab = netdev_priv ( netdev );
3729  struct efab_tx_queue *tx_queue = &efab->tx_queue;
3730  int fill_level, space;
3732  int buf_id;
3733 
3734  fill_level = tx_queue->write_ptr - tx_queue->read_ptr;
3735  space = EFAB_TXD_SIZE - fill_level - 1;
3736  if ( space < 1 )
3737  return -ENOBUFS;
3738 
3739  /* Save the iobuffer for later completion */
3740  buf_id = tx_queue->write_ptr % EFAB_TXD_SIZE;
3741  assert ( tx_queue->buf[buf_id] == NULL );
3742  tx_queue->buf[buf_id] = iob;
3743 
3744  EFAB_TRACE ( "tx_buf[%d] for iob %p data %p len %zd\n",
3745  buf_id, iob, iob->data, iob_len ( iob ) );
3746 
3747  /* Form the descriptor, and push it to hardware */
3748  txd = tx_queue->ring + buf_id;
3749  falcon_build_tx_desc ( txd, iob );
3750  ++tx_queue->write_ptr;
3751  falcon_notify_tx_desc ( efab, tx_queue );
3752 
3753  return 0;
3754 }
3755 
3756 static int
3757 efab_transmit_done ( struct efab_nic *efab, int id )
3758 {
3759  struct efab_tx_queue *tx_queue = &efab->tx_queue;
3760  unsigned int read_ptr, stop;
3761 
3762  /* Complete all buffers from read_ptr up to and including id */
3763  read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
3764  stop = ( id + 1 ) % EFAB_TXD_SIZE;
3765 
3766  while ( read_ptr != stop ) {
3767  struct io_buffer *iob = tx_queue->buf[read_ptr];
3768  assert ( iob );
3769 
3770  /* Complete the tx buffer */
3771  if ( iob )
3772  netdev_tx_complete ( efab->netdev, iob );
3773  tx_queue->buf[read_ptr] = NULL;
3774 
3775  ++tx_queue->read_ptr;
3776  read_ptr = tx_queue->read_ptr % EFAB_TXD_SIZE;
3777  }
3778 
3779  return 0;
3780 }
3781 
3782 /*******************************************************************************
3783  *
3784  *
3785  * Hardware event path
3786  *
3787  *
3788  *******************************************************************************/
3789 
3790 static void
3792 {
3793  efab_dword_t reg;
3794 
3795  if ( efab->pci_revision == FALCON_REV_B0 ) {
3796  /* read the ISR */
3797  falcon_readl( efab, &reg, INT_ISR0_B0 );
3798  }
3799  else {
3800  /* write to the INT_ACK register */
3801  EFAB_ZERO_DWORD ( reg );
3803  mb();
3804  falcon_readl ( efab, &reg,
3806  }
3807 }
3808 
3809 static void
3811 {
3812  int ev_code, desc_ptr, len, drop;
3813 
3814  /* Decode event */
3815  ev_code = EFAB_QWORD_FIELD ( *evt, FCN_EV_CODE );
3816  switch ( ev_code ) {
3817  case FCN_TX_IP_EV_DECODE:
3818  desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_TX_EV_DESC_PTR );
3819  efab_transmit_done ( efab, desc_ptr );
3820  break;
3821 
3822  case FCN_RX_IP_EV_DECODE:
3823  desc_ptr = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_DESC_PTR );
3824  len = EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_BYTE_CNT );
3825  drop = !EFAB_QWORD_FIELD ( *evt, FCN_RX_EV_PKT_OK );
3826 
3827  efab_receive ( efab, desc_ptr, len, drop );
3828  break;
3829 
3830  default:
3831  EFAB_TRACE ( "Unknown event type %d\n", ev_code );
3832  break;
3833  }
3834 }
3835 
3836 /*******************************************************************************
3837  *
3838  *
3839  * Software (polling) interrupt handler
3840  *
3841  *
3842  *******************************************************************************/
3843 
3844 static void
3846 {
3847  struct efab_nic *efab = netdev_priv ( netdev );
3848  struct efab_ev_queue *ev_queue = &efab->ev_queue;
3849  struct efab_rx_queue *rx_queue = &efab->rx_queue;
3850  falcon_event_t *evt;
3851 
3852  /* Read the event queue by directly looking for events
3853  * (we don't even bother to read the eventq write ptr) */
3854  evt = ev_queue->ring + ev_queue->read_ptr;
3855  while ( falcon_event_present ( evt ) ) {
3856 
3857  EFAB_TRACE ( "Event at index 0x%x address %p is "
3858  EFAB_QWORD_FMT "\n", ev_queue->read_ptr,
3859  evt, EFAB_QWORD_VAL ( *evt ) );
3860 
3861  falcon_handle_event ( efab, evt );
3862 
3863  /* Clear the event */
3864  EFAB_SET_QWORD ( *evt );
3865 
3866  /* Move to the next event. We don't ack the event
3867  * queue until the end */
3868  ev_queue->read_ptr = ( ( ev_queue->read_ptr + 1 ) %
3869  EFAB_EVQ_SIZE );
3870  evt = ev_queue->ring + ev_queue->read_ptr;
3871  }
3872 
3873  /* Push more buffers if needed */
3874  (void) efab_fill_rx_queue ( efab, rx_queue );
3875 
3876  /* Clear any pending interrupts */
3877  falcon_clear_interrupts ( efab );
3878 
3879  /* Ack the event queue */
3880  falcon_eventq_read_ack ( efab, ev_queue );
3881 }
3882 
3883 static void
3884 efab_irq ( struct net_device *netdev, int enable )
3885 {
3886  struct efab_nic *efab = netdev_priv ( netdev );
3887  struct efab_ev_queue *ev_queue = &efab->ev_queue;
3888 
3889  switch ( enable ) {
3890  case 0:
3891  falcon_interrupts ( efab, 0, 0 );
3892  break;
3893  case 1:
3894  falcon_interrupts ( efab, 1, 0 );
3895  falcon_eventq_read_ack ( efab, ev_queue );
3896  break;
3897  case 2:
3898  falcon_interrupts ( efab, 1, 1 );
3899  break;
3900  }
3901 }
3902 
3903 /*******************************************************************************
3904  *
3905  *
3906  * Software open/close
3907  *
3908  *
3909  *******************************************************************************/
3910 
3911 static void
3913 {
3914  struct efab_ev_queue *ev_queue = &efab->ev_queue;
3915  struct efab_rx_queue *rx_queue = &efab->rx_queue;
3916  struct efab_tx_queue *tx_queue = &efab->tx_queue;
3917  int i;
3918 
3919  for ( i = 0; i < EFAB_NUM_RX_DESC; i++ ) {
3920  if ( rx_queue->buf[i] )
3921  free_iob ( rx_queue->buf[i] );
3922  }
3923 
3924  for ( i = 0; i < EFAB_TXD_SIZE; i++ ) {
3925  if ( tx_queue->buf[i] )
3926  netdev_tx_complete ( efab->netdev, tx_queue->buf[i] );
3927  }
3928 
3929  if ( rx_queue->ring )
3930  falcon_free_special_buffer ( rx_queue->ring );
3931 
3932  if ( tx_queue->ring )
3933  falcon_free_special_buffer ( tx_queue->ring );
3934 
3935  if ( ev_queue->ring )
3936  falcon_free_special_buffer ( ev_queue->ring );
3937 
3938  memset ( rx_queue, 0, sizeof ( *rx_queue ) );
3939  memset ( tx_queue, 0, sizeof ( *tx_queue ) );
3940  memset ( ev_queue, 0, sizeof ( *ev_queue ) );
3941 
3942  /* Ensure subsequent buffer allocations start at id 0 */
3943  efab->buffer_head = 0;
3944 }
3945 
3946 static int
3948 {
3949  struct efab_ev_queue *ev_queue = &efab->ev_queue;
3950  struct efab_rx_queue *rx_queue = &efab->rx_queue;
3951  struct efab_tx_queue *tx_queue = &efab->tx_queue;
3952  size_t bytes;
3953 
3954  /* Allocate the hardware event queue */
3955  bytes = sizeof ( falcon_event_t ) * EFAB_TXD_SIZE;
3956  ev_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
3957  &ev_queue->entry );
3958  if ( !ev_queue->ring )
3959  goto fail1;
3960 
3961  /* Initialise the hardware event queue */
3962  memset ( ev_queue->ring, 0xff, bytes );
3963 
3964  /* Allocate the hardware tx queue */
3965  bytes = sizeof ( falcon_tx_desc_t ) * EFAB_TXD_SIZE;
3966  tx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
3967  &tx_queue->entry );
3968  if ( ! tx_queue->ring )
3969  goto fail2;
3970 
3971  /* Allocate the hardware rx queue */
3972  bytes = sizeof ( falcon_rx_desc_t ) * EFAB_RXD_SIZE;
3973  rx_queue->ring = falcon_alloc_special_buffer ( efab, bytes,
3974  &rx_queue->entry );
3975  if ( ! rx_queue->ring )
3976  goto fail3;
3977 
3978  return 0;
3979 
3980 fail3:
3981  falcon_free_special_buffer ( tx_queue->ring );
3982  tx_queue->ring = NULL;
3983 fail2:
3984  falcon_free_special_buffer ( ev_queue->ring );
3985  ev_queue->ring = NULL;
3986 fail1:
3987  return -ENOMEM;
3988 }
3989 
3990 static int
3991 efab_init_mac ( struct efab_nic *efab )
3992 {
3993  int count, rc;
3994 
3995  /* This can take several seconds */
3996  EFAB_LOG ( "Waiting for link..\n" );
3997  for ( count=0; count<5; count++ ) {
3998  rc = efab->mac_op->init ( efab );
3999  if ( rc ) {
4000  EFAB_ERR ( "Failed reinitialising MAC, error %s\n",
4001  strerror ( rc ));
4002  return rc;
4003  }
4004 
4005  /* Sleep for 2s to wait for the link to settle, either
4006  * because we want to use it, or because we're about
4007  * to reset the mac anyway
4008  */
4009  mdelay ( 2000 );
4010 
4011  if ( ! efab->link_up ) {
4012  EFAB_ERR ( "!\n" );
4013  continue;
4014  }
4015 
4016  EFAB_LOG ( "\n%dMbps %s-duplex\n",
4017  ( efab->link_options & LPA_EF_10000 ? 10000 :
4018  ( efab->link_options & LPA_EF_1000 ? 1000 :
4019  ( efab->link_options & LPA_100 ? 100 : 10 ) ) ),
4020  ( efab->link_options & LPA_EF_DUPLEX ?
4021  "full" : "half" ) );
4022 
4023  /* TODO: Move link state handling to the poll() routine */
4024  netdev_link_up ( efab->netdev );
4025  return 0;
4026  }
4027 
4028  EFAB_ERR ( "timed initialising MAC\n" );
4029  return -ETIMEDOUT;
4030 }
4031 
4032 static void
4034 {
4035  struct efab_nic *efab = netdev_priv ( netdev );
4036 
4037  falcon_fini_resources ( efab );
4038  efab_free_resources ( efab );
4039  efab->board_op->fini ( efab );
4040  falcon_reset ( efab );
4041 }
4042 
4043 static int
4045 {
4046  struct efab_nic *efab = netdev_priv ( netdev );
4047  struct efab_rx_queue *rx_queue = &efab->rx_queue;
4048  int rc;
4049 
4050  rc = falcon_reset ( efab );
4051  if ( rc )
4052  goto fail1;
4053 
4054  rc = efab->board_op->init ( efab );
4055  if ( rc )
4056  goto fail2;
4057 
4058  rc = falcon_init_sram ( efab );
4059  if ( rc )
4060  goto fail3;
4061 
4062  /* Configure descriptor caches before pushing hardware queues */
4063  falcon_setup_nic ( efab );
4064 
4065  rc = efab_alloc_resources ( efab );
4066  if ( rc )
4067  goto fail4;
4068 
4069  falcon_init_resources ( efab );
4070 
4071  /* Push rx buffers */
4072  rc = efab_fill_rx_queue ( efab, rx_queue );
4073  if ( rc )
4074  goto fail5;
4075 
4076  /* Try and bring the interface up */
4077  rc = efab_init_mac ( efab );
4078  if ( rc )
4079  goto fail6;
4080 
4081  return 0;
4082 
4083 fail6:
4084 fail5:
4085  efab_free_resources ( efab );
4086 fail4:
4087 fail3:
4088  efab->board_op->fini ( efab );
4089 fail2:
4090  falcon_reset ( efab );
4091 fail1:
4092  return rc;
4093 }
4094 
4096  .open = efab_open,
4097  .close = efab_close,
4098  .transmit = efab_transmit,
4099  .poll = efab_poll,
4100  .irq = efab_irq,
4101 };
4102 
4103 static void
4104 efab_remove ( struct pci_device *pci )
4105 {
4106  struct net_device *netdev = pci_get_drvdata ( pci );
4107  struct efab_nic *efab = netdev_priv ( netdev );
4108 
4109  if ( efab->membase ) {
4110  falcon_reset ( efab );
4111 
4112  iounmap ( efab->membase );
4113  efab->membase = NULL;
4114  }
4115 
4116  if ( efab->nvo.nvs ) {
4117  unregister_nvo ( &efab->nvo );
4118  efab->nvo.nvs = NULL;
4119  }
4120 
4122  netdev_nullify ( netdev );
4123  netdev_put ( netdev );
4124 }
4125 
4126 static int
4127 efab_probe ( struct pci_device *pci )
4128 {
4129  struct net_device *netdev;
4130  struct efab_nic *efab;
4131  unsigned long mmio_start, mmio_len;
4132  int rc;
4133 
4134  /* Create the network adapter */
4135  netdev = alloc_etherdev ( sizeof ( struct efab_nic ) );
4136  if ( ! netdev ) {
4137  rc = -ENOMEM;
4138  goto fail1;
4139  }
4140 
4141  /* Initialise the network adapter, and initialise private storage */
4143  pci_set_drvdata ( pci, netdev );
4144  netdev->dev = &pci->dev;
4145 
4146  efab = netdev_priv ( netdev );
4147  memset ( efab, 0, sizeof ( *efab ) );
4148  efab->netdev = netdev;
4149 
4150  /* Get iobase/membase */
4151  mmio_start = pci_bar_start ( pci, PCI_BASE_ADDRESS_2 );
4152  mmio_len = pci_bar_size ( pci, PCI_BASE_ADDRESS_2 );
4153  efab->membase = ioremap ( mmio_start, mmio_len );
4154  EFAB_TRACE ( "BAR of %lx bytes at phys %lx mapped at %p\n",
4155  mmio_len, mmio_start, efab->membase );
4156 
4157  /* Enable the PCI device */
4158  adjust_pci_device ( pci );
4159  efab->iobase = pci->ioaddr & ~3;
4160 
4161  /* Determine the NIC variant */
4162  falcon_probe_nic_variant ( efab, pci );
4163 
4164  /* Read the SPI interface and determine the MAC address,
4165  * and the board and phy variant. Hook in the op tables */
4166  rc = falcon_probe_spi ( efab );
4167  if ( rc )
4168  goto fail2;
4169  rc = falcon_probe_nvram ( efab );
4170  if ( rc )
4171  goto fail3;
4172 
4173  memcpy ( netdev->hw_addr, efab->mac_addr, ETH_ALEN );
4174 
4175  rc = register_netdev ( netdev );
4176  if ( rc )
4177  goto fail4;
4178  netdev_link_up ( netdev );
4179 
4180  /* Advertise non-volatile storage */
4181  if ( efab->nvo.nvs ) {
4182  rc = register_nvo ( &efab->nvo, netdev_settings ( netdev ) );
4183  if ( rc )
4184  goto fail5;
4185  }
4186 
4187  EFAB_LOG ( "Found %s EtherFabric %s %s revision %d\n", pci->id->name,
4188  efab->is_asic ? "ASIC" : "FPGA",
4189  efab->phy_10g ? "10G" : "1G",
4190  efab->pci_revision );
4191 
4192  return 0;
4193 
4194 fail5:
4196 fail4:
4197 fail3:
4198 fail2:
4199  iounmap ( efab->membase );
4200  efab->membase = NULL;
4201  netdev_put ( netdev );
4202 fail1:
4203  return rc;
4204 }
4205 
4206 
4207 static struct pci_device_id efab_nics[] = {
4208  PCI_ROM(0x1924, 0x0703, "falcon", "EtherFabric Falcon", 0),
4209  PCI_ROM(0x1924, 0x0710, "falconb0", "EtherFabric FalconB0", 0),
4210 };
4211 
4212 struct pci_driver etherfabric_driver __pci_driver = {
4213  .ids = efab_nics,
4214  .id_count = sizeof ( efab_nics ) / sizeof ( efab_nics[0] ),
4215  .probe = efab_probe,
4216  .remove = efab_remove,
4217 };
4218 
4219 /*
4220  * Local variables:
4221  * c-basic-offset: 8
4222  * c-indent-level: 8
4223  * tab-width: 8
4224  * End:
4225  */
#define FCN_RX_CFG_REG_KER
Definition: etherfabric.c:652
struct nvo_block nvo
#define XX_TXDRV_DEQ_DEFAULT
Definition: etherfabric.c:804
#define FCN_XX_SD_CTL_REG_MAC
Definition: etherfabric.c:958
static void falcon_reconfigure_mac_wrapper(struct efab_nic *efab)
Definition: etherfabric.c:1716
#define MII_ADVERTISE
Definition: atl1e.h:875
#define LPA_PAUSE_CAP
Definition: mii.h:104
#define P1_IN
Definition: etherfabric.c:2809
#define LPA_10HALF
Definition: mii.h:95
#define __attribute__(x)
Definition: compiler.h:10
static void efab_free_resources(struct efab_nic *efab)
Definition: etherfabric.c:3912
#define FCN_SRM_CFG_REG_KER
Definition: etherfabric.c:638
#define EINVAL
Invalid argument.
Definition: errno.h:428
static void falcon_readl(struct efab_nic *efab, efab_dword_t *value, unsigned int reg)
Read dword from a portion of a Falcon register.
Definition: etherfabric.c:1284
#define MII_LPA
Definition: atl1e.h:876
#define P0_EN_3V3X_LBN
Definition: etherfabric.c:2802
#define FCN_DUMP_MAC_REG(efab, _mac_reg)
Definition: etherfabric.c:1298
static void * netdev_priv(struct net_device *netdev)
Get driver private area for this network device.
Definition: netdevice.h:566
iPXE I/O API
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
static unsigned int gmii_autoneg_lpa(struct efab_nic *efab)
Retrieve GMII autonegotiation link partner abilities.
Definition: etherfabric.c:130
unsigned short uint16_t
Definition: stdint.h:11
#define FCN_MD_TXD_REG_KER
Definition: etherfabric.c:744
static void netdev_tx_complete(struct net_device *netdev, struct io_buffer *iobuf)
Complete network transmission.
Definition: netdevice.h:746
#define FCN_TX_IP_EV_DECODE
Definition: etherfabric.c:1137
struct efab_special_buffer entry
wmb()
static void falcon_xmac_readl(struct efab_nic *efab, efab_dword_t *value, unsigned int mac_reg)
Read dword from a Falcon XMAC register.
Definition: etherfabric.c:2080
static int sfe4003_init(struct efab_nic *efab)
Definition: etherfabric.c:3002
#define TXC_ALRGS_ATXAMP0
Definition: etherfabric.c:2489
static int falcon_reset_xaui(struct efab_nic *efab)
Definition: etherfabric.c:2186
#define MDIO_MMD_DTEXS
Definition: etherfabric.c:211
#define FALCON_SPI_MAX_LEN
Maximum length for a single SPI transaction.
Definition: etherfabric.c:1397
#define iob_put(iobuf, len)
Definition: iobuf.h:116
struct efab_ev_queue ev_queue
#define FCN_EE_VPD_CFG_REG
Definition: etherfabric.c:489
#define MDIO45_RESET_TRIES
Definition: etherfabric.c:261
#define FCN_XX_PWR_RST_REG_MAC
Definition: etherfabric.c:928
int(* rw)(struct spi_bus *bus, struct spi_device *device, unsigned int command, int address, const void *data_out, void *data_in, size_t len)
Read/write data via SPI bus.
Definition: spi.h:152
#define EFAB_DWORD_IS_ALL_ONES(dword)
Definition: etherfabric.h:263
#define FALCON_MAC_ADDRESS_OFFSET
Offset of MAC address within EEPROM or Flash.
Definition: etherfabric.c:3141
#define TXC_ALRGS_ATXPRE1
Definition: etherfabric.c:2511
static int falcon_spi_wait(struct efab_nic *efab)
Definition: etherfabric.c:1400
A PCI driver.
Definition: pci.h:224
#define FCN_EE_SPI_HADR_REG
Definition: etherfabric.c:471
static struct efab_mac_operations falcon_gmac_operations
Definition: etherfabric.c:2046
uint8_t mac_addr[ETH_ALEN]
MAC address.
#define FCN_RX_DESC_UPD_REG_KER_DWORD
Definition: etherfabric.c:701
static int falcon_tenxpress_check_c11(struct efab_nic *efab)
Definition: etherfabric.c:2641
uint16_t structure_version
Definition: etherfabric.c:3162
#define EFAB_OWORD_FIELD
Definition: etherfabric.h:274
#define TXC_ALRGS_ATXAMP1
Definition: etherfabric.c:2490
__be32 in[4]
Definition: CIB_PRM.h:35
int(* write)(struct i2c_interface *i2c, struct i2c_device *i2cdev, unsigned int offset, const uint8_t *data, unsigned int len)
Write data to I2C device.
Definition: i2c.h:81
#define PMC_MCONF2_REDGE
Definition: etherfabric.c:2723
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
struct efab_special_buffer entry
#define INT_ISR0_B0
Definition: etherfabric.c:431
#define P0_CONFIG
Definition: etherfabric.c:2794
#define EFAB_POPULATE_DWORD_5(dword,...)
Definition: etherfabric.h:449
static struct efab_phy_operations falcon_xaui_phy_ops
Definition: etherfabric.c:2402
#define PMC_ANALOG_RX_CFG0
Definition: etherfabric.c:2726
uint16_t device_id
Definition: ib_mad.h:19
A quadword (i.e.
Definition: etherfabric.h:111
#define FCN_RX_IP_EV_DECODE
Definition: etherfabric.c:1136
#define FCN_XM_ADR_HI_REG_MAC
Definition: etherfabric.c:830
#define FCN_XM_RX_PARAM_REG_MAC
Definition: etherfabric.c:897
unsigned long ioaddr
I/O address.
Definition: pci.h:200
Serial clock.
Definition: i2c.h:114
#define FCN_IP_DAT_BUF_SIZE_4K
Definition: etherfabric.c:1099
static int falcon_pm8358_phy_init(struct efab_nic *efab)
Definition: etherfabric.c:2741
Error codes.
#define MAX_TEMP_THRESH
Definition: etherfabric.c:2787
Bit-bashing operations.
Definition: bitbash.h:15
static unsigned int gmii_autoneg_advertised(struct efab_nic *efab)
Retrieve GMII autonegotiation advertised abilities.
Definition: etherfabric.c:113
#define FCN_XX_CHARERR_RESET
Definition: etherfabric.c:922
static void efab_poll(struct net_device *netdev)
Definition: etherfabric.c:3845
#define EFAB_RX_BUF_SIZE
A command-line command.
Definition: command.h:9
#define MDIO_MMDREG_DEVS0_DTEXS
Definition: etherfabric.c:239
unsigned int iobase
#define FCN_XM_RX_CFG_REG_MAC
Definition: etherfabric.c:863
I/O buffers.
static int gmii_link_ok(struct efab_nic *efab)
Check GMII PHY link status.
Definition: etherfabric.c:173
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
A non-volatile storage device.
Definition: nvs.h:15
#define FCN_DUMP_REG(efab, _reg)
Definition: etherfabric.c:1291
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:226
#define FCN_SRM_RX_DC_CFG_REG_KER
Definition: etherfabric.c:628
#define TXC_ATXAMP_0820_BOTH
Definition: etherfabric.c:2504
uint64_t address
Base address.
Definition: ena.h:24
int register_nvo(struct nvo_block *nvo, struct settings *parent)
Register non-volatile stored options.
Definition: nvo.c:293
#define FCN_EE_SPI_READ
Definition: etherfabric.c:461
#define FCN_XM_MGT_INT_REG_MAC_B0
Definition: etherfabric.c:902
#define EFAB_REGDUMP(...)
Definition: etherfabric.c:46
#define TXC_GLRGS_GLCMD
Definition: etherfabric.c:2485
#define XFP_REQUIRED_DEVS
Definition: etherfabric.c:2451
An SPI bus.
Definition: spi.h:126
static void mentormac_reset(struct efab_nic *efab)
Definition: etherfabric.c:1902
#define FALCON_REV_B0
Definition: etherfabric.c:531
#define XX_SD_CTL_DRV_DEFAULT
Definition: etherfabric.c:806
#define XX_TXDRV_DTX_DEFAULT
Definition: etherfabric.c:805
#define PCA9539
Definition: etherfabric.c:2790
static void falcon_notify_rx_desc(struct efab_nic *efab, struct efab_rx_queue *rx_queue)
Definition: etherfabric.c:3599
#define EFAB_SET_OWORD_FIELD_VER(efab, reg, field, val)
Definition: etherfabric.c:1165
#define PMC_MCONF2_REG
Definition: etherfabric.c:2719
struct efab_phy_operations * phy_op
static void falcon_write(struct efab_nic *efab, efab_oword_t *value, unsigned int reg)
Write to a Falcon register.
Definition: etherfabric.c:1200
struct net_device * netdev
#define LPA_OTHER
Definition: etherfabric.c:102
efab_qword_t falcon_rx_desc_t
#define EFAB_POPULATE_DWORD_3(dword,...)
Definition: etherfabric.h:453
#define FCN_XM_MGT_INT_MSK_REG_MAC_B0
Definition: etherfabric.c:872
#define P0_EN_1V0X_LBN
Definition: etherfabric.c:2796
static struct i2c_device i2c_pca9539
Definition: etherfabric.c:2826
#define EFAB_SET_OWORD_FIELD
Definition: etherfabric.h:531
unsigned int write_ptr
#define FCN_XX_SYNC_STAT_DECODE_SYNCED
Definition: etherfabric.c:916
#define MAX6647
Definition: etherfabric.c:2820
void putchar(int character)
Write a single character to each console device.
Definition: console.c:27
static void falcon_reconfigure_xmac(struct efab_nic *efab)
Initialise XMAC.
Definition: etherfabric.c:2254
#define FCN_EE_SPI_FLASH
Definition: etherfabric.c:456
iPXE timers
static void falcon_build_tx_desc(falcon_tx_desc_t *txd, struct io_buffer *iob)
Definition: etherfabric.c:3618
unsigned int write_ptr
A doubleword (i.e.
Definition: etherfabric.h:102
#define PCS_BOOT_STATUS_REG
Definition: etherfabric.c:2630
#define FCN_MD_STAT_REG_KER
Definition: etherfabric.c:777
An I2C interface.
Definition: i2c.h:57
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
unsigned int dev_addr
Address of this device.
Definition: i2c.h:31
#define LPA_100HALF
Definition: mii.h:99
struct io_buffer * buf[EFAB_TXD_SIZE]
#define EFAB_SET_DWORD_FIELD(dword, field, value)
Definition: etherfabric.h:521
#define PM8358_REQUIRED_DEVS
Definition: etherfabric.c:2710
static struct efab_phy_operations falcon_alaska_phy_ops
Definition: etherfabric.c:2439
static struct efab_mac_operations falcon_xmac_operations
Definition: etherfabric.c:2380
#define FCN_INT_EN_REG_KER
Definition: etherfabric.c:411
#define GM_MAX_FLEN_REG_MAC
Definition: etherfabric.c:1773
#define LPA_EF_1000HALF
Definition: etherfabric.c:92
#define FCN_TIMER_CMD_REG_KER
Definition: etherfabric.c:614
static void * falcon_alloc_special_buffer(struct efab_nic *efab, int bytes, struct efab_special_buffer *entry)
Definition: etherfabric.c:3032
static void falcon_init_spi_device(struct efab_nic *efab, struct spi_device *spi)
Definition: etherfabric.c:3202
#define LPA_EF_1000
Definition: etherfabric.c:96
static int alaska_init(struct efab_nic *efab)
Initialise Alaska PHY.
Definition: etherfabric.c:2421
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
static struct efab_phy_operations falcon_pm8358_phy_ops
Definition: etherfabric.c:2774
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
#define EFAB_RXD_SIZE
#define EFAB_DWORD_VAL(dword)
printk parameters for printing an efab_dword_t
Definition: etherfabric.h:139
uint16_t checksum
Definition: etherfabric.c:3163
static void falcon_clear_interrupts(struct efab_nic *efab)
Definition: etherfabric.c:3791
#define LPA_EF_1000FULL
Definition: etherfabric.c:91
struct device dev
Generic device.
Definition: pci.h:189
static struct settings * netdev_settings(struct net_device *netdev)
Get per-netdevice configuration settings block.
Definition: netdevice.h:577
unsigned int read_ptr
#define EFAB_QWORD_FIELD
Definition: etherfabric.h:275
static struct efab_phy_operations falcon_tenxpress_phy_ops
Definition: etherfabric.c:2696
#define EFAB_BYTE
Definition: etherfabric.c:56
#define FCN_MAC1_CTRL_REG_KER
Definition: etherfabric.c:791
static void efab_receive(struct efab_nic *efab, unsigned int id, int len, int drop)
Definition: etherfabric.c:3690
#define EFAB_POPULATE_DWORD_7(dword,...)
Definition: etherfabric.h:445
efab_oword_t int_ker
INT_REG_KER.
Dynamic memory allocation.
#define EFAB_POPULATE_OWORD_2(oword,...)
Definition: etherfabric.h:399
static void falcon_writel(struct efab_nic *efab, efab_dword_t *value, unsigned int reg)
Write dword to Falcon register that allows partial writes.
Definition: etherfabric.c:1238
device address_len
Definition: threewire.h:73
static void falcon_gmac_writel(struct efab_nic *efab, efab_dword_t *value, unsigned int mac_reg)
Definition: etherfabric.c:1880
static void falcon_notify_tx_desc(struct efab_nic *efab, struct efab_tx_queue *tx_queue)
Definition: etherfabric.c:3626
uint8_t status
Status.
Definition: ena.h:16
struct efab_tx_queue tx_queue
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:498
struct spi_device spi_eeprom
#define FCN_XX_TXDRV_CTL_REG_MAC
Definition: etherfabric.c:988
int(* init)(struct efab_nic *efab)
#define FCN_GLB_CTL_REG_KER
Definition: etherfabric.c:575
Serial data.
Definition: i2c.h:116
#define FQS(_prefix, _x)
Definition: etherfabric.c:65
#define FCN_TX_CFG2_REG_KER
Definition: etherfabric.c:726
#define FCN_XM_GLB_CFG_REG_MAC
Definition: etherfabric.c:837
static void falcon_read(struct efab_nic *efab, efab_oword_t *value, unsigned int reg)
Read from a Falcon register.
Definition: etherfabric.c:1250
static struct pci_device_id efab_nics[]
Definition: etherfabric.c:4207
uint32_t minor
Minor version.
Definition: netvsc.h:16
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:338
#define PMC_MASTER_REG
Definition: etherfabric.c:2714
#define EFAB_QWORD_FMT
Format string for printing an efab_qword_t.
Definition: etherfabric.h:133
#define ENOMEM
Not enough space.
Definition: errno.h:534
A hardware device.
Definition: device.h:73
static void efab_close(struct net_device *netdev)
Definition: etherfabric.c:4033
static void falcon_mdio_write(struct efab_nic *efab, int device, int location, int value)
Definition: etherfabric.c:1590
#define RLHN
Definition: etherfabric.c:2823
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define FCN_NV_MAGIC_NUMBER
Definition: etherfabric.c:572
#define TXC_ATXPRE_DEFAULT
Definition: etherfabric.c:2514
falcon_rx_desc_t * ring
#define LPA_100FULL
Definition: mii.h:101
#define FCN_EE_SPI_HDATA_REG
Definition: etherfabric.c:478
static int falcon_txc_logic_reset(struct efab_nic *efab)
Definition: etherfabric.c:2521
static int falcon_mdio_read(struct efab_nic *efab, int device, int location)
Definition: etherfabric.c:1644
#define MDIO_MMDREG_STAT2
Definition: etherfabric.c:221
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define FCN_RX_FILTER_TBL0
Definition: etherfabric.c:1007
Etherfabric bitfield access.
#define EFAB_ZERO_DWORD(dword)
Definition: etherfabric.h:459
static int falcon_i2c_bit_read(struct bit_basher *basher, unsigned int bit_id)
Definition: etherfabric.c:1527
#define MDIO_MMDREG_CTRL1
Definition: etherfabric.c:218
#define P0_X_TRST_LBN
Definition: etherfabric.c:2806
unsigned int block_size
Data block size (in words)
Definition: nvs.h:36
Assertions.
#define EFAB_MAX_FRAME_LEN(mtu)
Definition: etherfabric.c:73
#define MDIO_PHYXS_LANE_STATE
Definition: etherfabric.c:253
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:555
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
int sync(unsigned long timeout)
Wait for pending operations to complete.
Definition: sync.c:73
#define LPA_10FULL
Definition: mii.h:97
static void falcon_interrupts(struct efab_nic *efab, int enabled, int force)
Definition: etherfabric.c:1377
Ethernet protocol.
static struct efab_phy_operations falcon_txc_phy_ops
Definition: etherfabric.c:2600
#define FCN_MD_CS_REG_KER
Definition: etherfabric.c:754
static int mdio_clause45_reset_mmd(struct efab_nic *efab, int mmd)
Definition: etherfabric.c:304
#define GMF_CFG5_REG_MAC
Definition: etherfabric.c:1869
#define FCN_RX_SELF_RST_REG_KER
Definition: etherfabric.c:710
#define EFAB_OWORD_VAL(oword)
printk parameters for printing an efab_oword_t
Definition: etherfabric.h:148
#define ETH_FRAME_LEN
Definition: if_ether.h:11
struct i2c_interface i2c
I2C interface.
Definition: i2c.h:93
#define MDIO_MMD_PHYXS
Definition: etherfabric.c:209
static int falcon_spi_rw(struct spi_bus *bus, struct spi_device *device, unsigned int command, int address, const void *data_out, void *data_in, size_t len)
Definition: etherfabric.c:1418
#define EFAB_POPULATE_OWORD_7(oword,...)
Definition: etherfabric.h:389
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:768
#define PCI_BASE_ADDRESS_2
Definition: pci.h:63
static int mdio_clause45_links_ok(struct efab_nic *efab)
Definition: etherfabric.c:327
#define LPA_100
Definition: mii.h:112
static void falcon_init_resources(struct efab_nic *efab)
Definition: etherfabric.c:3491
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
static struct net_device * netdev
Definition: gdbudp.c:52
static int falcon_init_xmac(struct efab_nic *efab)
Definition: etherfabric.c:2314
static int falcon_probe_spi(struct efab_nic *efab)
Definition: etherfabric.c:3215
__be32 out[4]
Definition: CIB_PRM.h:36
#define GM_ADR2_REG_MAC
Definition: etherfabric.c:1823
static void falcon_probe_nic_variant(struct efab_nic *efab, struct pci_device *pci)
Definition: etherfabric.c:3172
static int efab_transmit_done(struct efab_nic *efab, int id)
Definition: etherfabric.c:3757
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
#define GMF_CFG1_REG_MAC
Definition: etherfabric.c:1843
static struct net_device_operations efab_operations
Definition: etherfabric.c:4095
#define MII_CTRL1000
Definition: mii.h:24
#define MDIO_PHYXS_LANE_ALIGNED_LBN
Definition: etherfabric.c:254
void * membase
Memory and IO base.
#define EFAB_TRACE(...)
Definition: etherfabric.c:47
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:844
#define TXC_REQUIRED_DEVS
Definition: etherfabric.c:2516
#define FCN_TX_DESC_UPD_REG_KER_DWORD
Definition: etherfabric.c:734
void unregister_nvo(struct nvo_block *nvo)
Unregister non-volatile stored options.
Definition: nvo.c:324
static struct bit_basher_operations falcon_i2c_bit_ops
Definition: etherfabric.c:1549
struct efab_mac_operations * mac_op
#define EFAB_POPULATE_OWORD_4(oword,...)
Definition: etherfabric.h:395
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
static int sfe4001_init(struct efab_nic *efab)
Definition: etherfabric.c:2840
struct bit_basher basher
Bit-bashing interface.
Definition: i2c.h:95
uint32_t revision
Definition: ib_mad.h:20
#define PCS_TEST_SELECT_REG
Definition: etherfabric.c:2618
int(* read)(struct bit_basher *basher, unsigned int bit_id)
Read input bit.
Definition: bitbash.h:51
#define P0_EN_5V_LBN
Definition: etherfabric.c:2804
#define EFAB_POPULATE_DWORD_2(dword,...)
Definition: etherfabric.h:455
void(* fini)(struct efab_nic *efab)
A bit-bashing interface.
Definition: bitbash.h:55
#define GMII_PSSR
Definition: etherfabric.c:88
struct nvs_device * nvs
Underlying non-volatile storage device.
Definition: nvo.h:26
struct spi_bus spi_bus
SPI bus and devices, and the user visible NVO area.
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
#define BMSR_LSTATUS
Definition: mii.h:55
struct refcnt refcnt
Reference counter.
Definition: netdevice.h:350
#define FCN_XM_TX_CFG_REG_MAC
Definition: etherfabric.c:848
static void falcon_fini_resources(struct efab_nic *efab)
Definition: etherfabric.c:3550
#define EFAB_EVQ_SIZE
#define txd
Definition: davicom.c:143
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
void nvo_init(struct nvo_block *nvo, struct nvs_device *nvs, size_t address, size_t len, int(*resize)(struct nvo_block *nvo, size_t len), struct refcnt *refcnt)
Initialise non-volatile stored options.
Definition: nvo.c:273
#define FCN_TX_DC_CFG_REG_KER
Definition: etherfabric.c:739
#define EFAB_POPULATE_QWORD_3(qword,...)
Definition: etherfabric.h:426
#define EFAB_BUF_ALIGN
#define MDIO_MMDREG_STAT2_PRESENT_VAL
Definition: etherfabric.c:248
unsigned int link_options
GMII link options.
#define FCN_RX_DC_CFG_REG_KER
Definition: etherfabric.c:706
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Find the size of a PCI BAR.
Definition: pciextra.c:90
static unsigned int unsigned int reg
Definition: intel.h:245
#define EFAB_SET_QWORD(qword)
Definition: etherfabric.h:434
#define outl(data, io_addr)
Definition: io.h:329
PCI bus.
#define FCN_RX_FILTER_CTL_REG_KER
Definition: etherfabric.c:678
A PCI device.
Definition: pci.h:187
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:667
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
#define EFAB_POPULATE_OWORD_1(oword,...)
Definition: etherfabric.h:401
#define CLK312_EN_LBN
Definition: etherfabric.c:2619
#define FCN_MD_PHY_ADR_REG_KER
Definition: etherfabric.c:765
#define PCS_BOOT_COMPLETE_LBN
Definition: etherfabric.c:2634
#define MDIO_MMD_PCS
Definition: etherfabric.c:207
static void falcon_eventq_read_ack(struct efab_nic *efab, struct efab_ev_queue *ev_queue)
Definition: etherfabric.c:1328
#define _falcon_writel(efab, value, reg)
Definition: etherfabric.c:1189
static void falcon_write_sram(struct efab_nic *efab, efab_qword_t *value, unsigned int index)
Write to Falcon SRAM.
Definition: etherfabric.c:1219
A network device.
Definition: netdevice.h:348
#define FCN_XX_COMMA_DET_RESET
Definition: etherfabric.c:919
int link_up
Link status.
falcon_tx_desc_t * ring
static int mdio_clause45_check_mmds(struct efab_nic *efab)
Definition: etherfabric.c:353
#define PSSR_LSTATUS
Definition: etherfabric.c:106
static void sfe4003_fini(struct efab_nic *efab)
Definition: etherfabric.c:3006
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:511
#define FCN_INT_ADR_REG_KER
Definition: etherfabric.c:426
u32 addr
Definition: sky2.h:8
struct efab_board_operations sfe4002_ops
Definition: etherfabric.c:2997
unsigned char uint8_t
Definition: stdint.h:10
#define FCN_XX_CORE_STAT_REG_MAC
Definition: etherfabric.c:913
static void falcon_xmac_writel(struct efab_nic *efab, efab_dword_t *value, unsigned int mac_reg)
Write dword to a Falcon XMAC register.
Definition: etherfabric.c:2064
#define GMF_CFG4_REG_MAC
Definition: etherfabric.c:1864
#define FCN_IOM_IND_ADR_REG
Definition: etherfabric.c:394
static void falcon_build_rx_desc(falcon_rx_desc_t *rxd, struct io_buffer *iob)
Definition: etherfabric.c:3591
#define SF_NV_CONFIG_EXTRA
Definition: etherfabric.c:3147
#define ETH_ALEN
Definition: if_ether.h:8
static int falcon_xaui_phy_init(struct efab_nic *efab)
Definition: etherfabric.c:2393
A PCI device ID list entry.
Definition: pci.h:151
#define GM_CFG1_REG_MAC
Definition: etherfabric.c:1749
#define EXCLUDE_FROM_RESET
Definition: etherfabric.c:595
#define le16_to_cpu(value)
Definition: byteswap.h:112
int(* read)(struct i2c_interface *i2c, struct i2c_device *i2cdev, unsigned int offset, uint8_t *data, unsigned int len)
Read data from I2C device.
Definition: i2c.h:68
static void falcon_setup_xaui(struct efab_nic *efab)
Configure Falcon XAUI output.
Definition: etherfabric.c:2095
unsigned int uint32_t
Definition: stdint.h:12
struct efab_board_operations sfe4003_ops
Definition: etherfabric.c:3010
#define GMF_CFG3_REG_MAC
Definition: etherfabric.c:1857
const char * name
Name.
Definition: pci.h:153
struct spi_device spi_flash
#define FCN_SRM_TX_DC_CFG_REG_KER
Definition: etherfabric.c:633
#define P1_SPARE_LBN
Definition: etherfabric.c:2816
#define FCN_REVISION_REG(efab, reg)
Definition: etherfabric.c:1162
struct spi_device * spi
An octword (eight-word, i.e.
Definition: etherfabric.h:122
static void falcon_handle_event(struct efab_nic *efab, falcon_event_t *evt)
Definition: etherfabric.c:3810
#define EFAB_NUM_RX_DESC
#define EAGAIN
Resource temporarily unavailable.
Definition: errno.h:318
static void falcon_free_special_buffer(void *p)
Definition: etherfabric.c:3024
#define P0_EN_1V2_LBN
Definition: etherfabric.c:2798
#define FCN_XM_FC_REG_MAC
Definition: etherfabric.c:881
static struct i2c_device i2c_max6647
Definition: etherfabric.c:2833
#define P0_EN_2V5_LBN
Definition: etherfabric.c:2800
static int falcon_reset(struct efab_nic *efab)
Definition: etherfabric.c:3108
void __asmcall int val
Definition: setjmp.h:28
static void sfe4001_fini(struct efab_nic *efab)
Definition: etherfabric.c:2961
Network device operations.
Definition: netdevice.h:213
union falcon_nv_extra::@41 ver_specific
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:470
struct device * dev
Underlying hardware device.
Definition: netdevice.h:360
#define EFAB_DWORD_FMT
Format string for printing an efab_dword_t.
Definition: etherfabric.h:130
static int falcon_init_sram(struct efab_nic *efab)
Definition: etherfabric.c:3366
struct efab_board_operations * board_op
Board, MAC, and PHY operations tables.
#define PMC_MASTER_ANLG_CTRL
Definition: etherfabric.c:2716
unsigned int read_ptr
Network device management.
#define EFAB_LOG(...)
Definition: etherfabric.c:50
static int mdio_clause45_wait_reset_mmds(struct efab_nic *efab)
Definition: etherfabric.c:265
#define FCN_TIMER_MODE_DIS
Definition: etherfabric.c:617
struct nvs_device nvs
NVS device.
Definition: spi.h:88
#define FALCON_XMAC_REG(efab_port, mac_reg)
Offset of an XMAC register within Falcon.
Definition: etherfabric.c:1111
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:348
#define FALCON_GMAC_REG(efab, mac_reg)
Offset of a GMAC register within Falcon.
Definition: etherfabric.c:1106
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Definition: sis900.h:23
#define LPA_100BASE4
Definition: mii.h:103
static int falcon_init_gmac(struct efab_nic *efab)
Definition: etherfabric.c:2025
#define P1_AFE_PWD_LBN
Definition: etherfabric.c:2812
#define FCN_EE_SPI_WRITE
Definition: etherfabric.c:462
struct efab_board_operations sfe4001_ops
Definition: etherfabric.c:2984
#define SF_NV_CONFIG_BASE
Definition: etherfabric.c:3146
#define PMC_ANALOG_RX_EQ_FULL
Definition: etherfabric.c:2737
#define EFAB_POPULATE_QWORD_2(qword,...)
Definition: etherfabric.h:428
static int falcon_gmii_wait(struct efab_nic *efab)
Definition: etherfabric.c:1564
static int efab_fill_rx_queue(struct efab_nic *efab, struct efab_rx_queue *rx_queue)
Definition: etherfabric.c:3646
uint32_t len
Length.
Definition: ena.h:14
#define MDIO_MMDREG_STAT1
Definition: etherfabric.c:219
static unsigned int gmii_nway_result(unsigned int negotiated)
Calculate GMII autonegotiated link technology.
Definition: etherfabric.c:146
static void sfe4002_fini(struct efab_nic *efab)
Definition: etherfabric.c:2993
uint8_t unused[32]
Unused.
Definition: eltorito.h:15
#define FCN_IOM_IND_DAT_REG
Definition: etherfabric.c:397
static unsigned int ctrl
Definition: intel.h:270
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define FCN_MAC0_CTRL_REG_KER
Definition: etherfabric.c:790
falcon_event_t * ring
#define WLHO
Definition: etherfabric.c:2824
Media Independent Interface constants.
static int falcon_tenxpress_phy_init(struct efab_nic *efab)
Definition: etherfabric.c:2661
static void falcon_gmac_readl(struct efab_nic *efab, efab_dword_t *value, unsigned int mac_reg)
Definition: etherfabric.c:1891
#define TXC_ALRGS_ATXPRE0
Definition: etherfabric.c:2510
#define P1_CONFIG
Definition: etherfabric.c:2810
#define MDIO_MMDREG_DEVS0
Definition: etherfabric.c:220
void * data
Start of data.
Definition: iobuf.h:44
efab_qword_t falcon_tx_desc_t
#define PMC_MCONF2_TEDGE
Definition: etherfabric.c:2721
static int falcon_reset_xmac(struct efab_nic *efab)
Reset 10G MAC connected to port.
Definition: etherfabric.c:2166
static int falcon_xaui_link_ok(struct efab_nic *efab)
Definition: etherfabric.c:2211
#define EIO
Input/output error.
Definition: errno.h:433
struct spi_bus * bus
SPI bus to which device is attached.
Definition: spi.h:90
#define MDIO_MMD_PMAPMD
Definition: etherfabric.c:203
#define TXC_ATXAMP_DEFAULT
Definition: etherfabric.c:2507
#define FCN_EE_SPI_EEPROM
Definition: etherfabric.c:455
uint32_t inl(volatile uint32_t *io_addr)
Read 32-bit dword from I/O-mapped device.
uint16_t count
Number of entries.
Definition: ena.h:22
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
static int falcon_txc_phy_init(struct efab_nic *efab)
Definition: etherfabric.c:2543
#define EFAB_POPULATE_DWORD_4(dword,...)
Definition: etherfabric.h:451
static void falcon_mask_status_intr(struct efab_nic *efab, int enable)
Definition: etherfabric.c:2144
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
struct pci_device_id * id
Driver device ID.
Definition: pci.h:220
#define GMF_CFG2_REG_MAC
Definition: etherfabric.c:1850
#define LPA_EF_10000FULL
Definition: etherfabric.c:93
static int falcon_xgmii_status(struct efab_nic *efab)
Definition: etherfabric.c:2123
#define _falcon_readl(efab, reg)
Definition: etherfabric.c:1191
static int efab_init_mac(struct efab_nic *efab)
Definition: etherfabric.c:3991
static int sfe4002_init(struct efab_nic *efab)
Definition: etherfabric.c:2989
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define PCI_REVISION
PCI revision.
Definition: pci.h:43
static int efab_probe(struct pci_device *pci)
Definition: etherfabric.c:4127
#define FCN_ADR_REGION_REG_KER
Definition: etherfabric.c:400
#define EFAB_POPULATE_OWORD_8(oword,...)
Definition: etherfabric.h:387
#define BOARD_TYPE(_rev)
Definition: etherfabric.c:3169
#define FCN_MD_ID_REG_KER
Definition: etherfabric.c:770
#define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1
Definition: etherfabric.c:440
static void falcon_setup_nic(struct efab_nic *efab)
Definition: etherfabric.c:3405
struct efab_special_buffer entry
An SPI device.
Definition: spi.h:86
#define EFAB_ERR(...)
Definition: etherfabric.c:51
int nvs_read(struct nvs_device *nvs, unsigned int address, void *data, size_t len)
Read from non-volatile storage device.
Definition: nvs.c:75
#define EFAB_POPULATE_DWORD_1(dword,...)
Definition: etherfabric.h:457
#define EFAB_ZERO_OWORD(oword)
Definition: etherfabric.h:403
static void mentormac_init(struct efab_nic *efab)
Definition: etherfabric.c:1926
#define TXC_ATXPRE_NONE
Definition: etherfabric.c:2513
#define MDIO_MMDREG_CTRL1_RESET_LBN
Definition: etherfabric.c:225
#define P0_OUT
Definition: etherfabric.c:2793
#define EFAB_OWORD_FMT
Format string for printing an efab_oword_t.
Definition: etherfabric.h:136
static int efab_transmit(struct net_device *netdev, struct io_buffer *iob)
Definition: etherfabric.c:3726
void mb(void)
Memory barrier.
#define FCN_INT_ACK_KER_REG_A1
Definition: etherfabric.c:435
efab_dword_t dword[2]
Definition: etherfabric.h:114
#define FCN_ALTERA_BUILD_REG_KER
Definition: etherfabric.c:598
#define GMF_CFG0_REG_MAC
Definition: etherfabric.c:1830
static void clear_b0_fpga_memories(struct efab_nic *efab)
Definition: etherfabric.c:3072
#define MDIO45_RESET_SPINTIME
Definition: etherfabric.c:262
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
static int efab_alloc_resources(struct efab_nic *efab)
Definition: etherfabric.c:3947
#define GM_ADR1_REG_MAC
Definition: etherfabric.c:1812
#define FCN_RX_RSS_INDIR_TBL_B0
Definition: etherfabric.c:1081
struct pci_driver etherfabric_driver __pci_driver
Definition: etherfabric.c:4212
#define LPA_EF_DUPLEX
Definition: etherfabric.c:98
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
#define FCN_XX_DISPERR_RESET
Definition: etherfabric.c:925
#define FCN_SPARE_REG_KER
Definition: etherfabric.c:609
unsigned int read_ptr
#define MII_BMSR
Definition: atl1e.h:872
#define FCN_MD_RXD_REG_KER
Definition: etherfabric.c:749
#define EFAB_POPULATE_OWORD_3(oword,...)
Definition: etherfabric.h:397
uint8_t bytes[64]
Definition: ib_mad.h:16
#define PMC_ANALOG_RX_EQ_MASK
Definition: etherfabric.c:2734
struct efab_rx_queue rx_queue
#define FCN_GPIO_CTL_REG_KER
Definition: etherfabric.c:535
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
#define GM_MII_MGMT_CFG_REG_MAC
Definition: etherfabric.c:1778
int init_i2c_bit_basher(struct i2c_bit_basher *i2cbit, struct bit_basher_operations *bash_op)
Initialise I2C bit-bashing interface.
Definition: i2c_bit.c:387
static struct efab_phy_operations falcon_xfp_phy_ops
Definition: etherfabric.c:2471
struct io_buffer * buf[EFAB_NUM_RX_DESC]
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
#define EFAB_POPULATE_OWORD_6(oword,...)
Definition: etherfabric.h:391
#define FCN_EE_SPI_HCMD_REG
Definition: etherfabric.c:448
int(* init)(struct efab_nic *efab)
#define ok(success)
Definition: test.h:46
int(* init)(struct efab_nic *efab)
uint16_t magicnumber
Definition: etherfabric.c:3161
#define TXC_GLCMD_LMTSWRST_LBN
Definition: etherfabric.c:2486
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:375
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
static int falcon_xfp_phy_init(struct efab_nic *efab)
Definition: etherfabric.c:2456
static void efab_irq(struct net_device *netdev, int enable)
Definition: etherfabric.c:3884
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
static void efab_remove(struct pci_device *pci)
Definition: etherfabric.c:4104
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define EFAB_POPULATE_DWORD_8(dword,...)
Definition: etherfabric.h:443
#define TENXPRESS_REQUIRED_DEVS
Definition: etherfabric.c:2614
#define EFAB_TXD_SIZE
static int efab_open(struct net_device *netdev)
Definition: etherfabric.c:4044
#define FCN_NIC_STAT_REG
Definition: etherfabric.c:501
uint8_t bus
Bus.
Definition: edd.h:14
#define EFAB_POPULATE_DWORD_6(dword,...)
Definition: etherfabric.h:447
#define FCN_XM_TX_PARAM_REG_MAC
Definition: etherfabric.c:888
#define GM_CFG2_REG_MAC
Definition: etherfabric.c:1762
static void falcon_i2c_bit_write(struct bit_basher *basher, unsigned int bit_id, unsigned long data)
Definition: etherfabric.c:1503
#define EFAB_QWORD_VAL(qword)
printk parameters for printing an efab_qword_t
Definition: etherfabric.h:143
static int falcon_event_present(falcon_event_t *event)
See if an event is present.
Definition: etherfabric.c:1321
#define RSL
Definition: etherfabric.c:2822
An I2C device.
Definition: i2c.h:20
#define LPA_EF_10000
Definition: etherfabric.c:97
struct i2c_bit_basher i2c_bb
int __invalid_queue_size
#define MDIO_MMDREG_STAT1_LINK_LBN
Definition: etherfabric.c:233
#define EFAB_POPULATE_OWORD_5(oword,...)
Definition: etherfabric.h:393
#define EFAB_DWORD_FIELD(dword, field)
Definition: etherfabric.h:229
struct falcon_nv_config_ver2 ver2
Definition: etherfabric.c:3165
#define rxd
Definition: davicom.c:145
static void falcon_read_sram(struct efab_nic *efab, efab_qword_t *value, unsigned int index)
Read from Falcon SRAM.
Definition: etherfabric.c:1267
static int falcon_probe_nvram(struct efab_nic *efab)
Definition: etherfabric.c:3277
#define FCN_XM_ADR_LO_REG_MAC
Definition: etherfabric.c:819
FILE_LICENCE(GPL_ANY)
#define MII_STAT1000
Definition: mii.h:25
void * memset(void *dest, int character, size_t len) __nonnull
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
A persistent I/O buffer.
Definition: iobuf.h:32
efab_qword_t falcon_event_t