71 u32 target,
int delay,
int delaymax,
const char *
msg )
114 DBG (
"mii_rw of reg %d at PHY %d timed out.\n",
119 DBG (
"mii_rw wrote 0x%x to reg %d at PHY %d\n",
123 DBG (
"mii_rw of reg %d at PHY %d failed.\n",
128 DBG (
"mii_rw read from reg %d at PHY %d: 0x%x.\n",
141 if ( !
priv->mac_in_use &&
156 u32 temp1, temp2, temp3;
190 priv->tx_ring[i].flaglen = 0;
191 priv->tx_ring[i].buf = 0;
195 priv->tx_fill_ctr = 0;
213 DBGP (
"nv_alloc_rx\n" );
216 rx_curr_desc =
priv->rx_ring + i;
247 priv->rx_ring[i].flaglen = 0;
248 priv->rx_ring[i].buf = 0;
271 if ( !
priv->rx_ring )
288 DBG (
"RX ring at phys addr: %#08lx\n",
290 DBG (
"TX ring at phys addr: %#08lx\n",
300 DBG (
"Could not allocate descriptor rings\n");
309 DBGP (
"nv_free_rxtx_resources\n" );
356 DBGP (
"nv_start_rx\n" );
366 if (
priv->mac_in_use )
369 DBG (
"nv_start_rx to duplex %d, speed 0x%08x.\n",
380 DBGP (
"nv_stop_rx\n" );
381 if ( !
priv->mac_in_use )
388 "nv_stop_rx: ReceiverStatus remained busy");
391 if ( !
priv->mac_in_use )
401 DBGP (
"nv_start_tx\n" );
403 if (
priv->mac_in_use )
415 DBGP (
"nv_stop_tx");
417 if ( !
priv->mac_in_use )
424 "nv_stop_tx: TransmitterStatus remained busy");
427 if ( !
priv->mac_in_use )
480 int adv_lpa, adv_pause, lpa_pause;
485 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
496 DBG (
"No link detected by phy - falling back to 10HD.\n" );
509 DBG (
"autoneg not completed - falling back to 10HD.\n" );
515 DBG (
"nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", adv, lpa );
524 DBG (
"nv_update_linkspeed: GBit ethernet detected.\n" );
546 DBG (
"bad ability %04x - falling back to 10HD.\n", adv_lpa);
555 DBG (
"changing link setting from %d/%d to %d/%d.\n",
559 priv->linkspeed = newls;
573 phyreg &= ~(0x3FF00);
629 switch ( adv_pause ) {
657 pause_flags =
priv->pause_flags;
686 DBGP (
"forcedeth_open\n" );
729 "open: SetupReg5, Bit 31 remained off\n" );
802 DBGP (
"forcedeth_transmit\n" );
808 DBG (
"Tx overflow\n" );
815 priv->tx_iobuf[
priv->tx_curr] = iobuf;
817 tx_curr_desc =
priv->tx_ring +
priv->tx_curr;
829 DBG (
"forcedeth_transmit: flaglen = %#04x\n",
831 DBG (
"forcedeth_transmit: tx_fill_ctr = %d\n",
860 DBGP (
"nv_process_tx_packets\n" );
862 while (
priv->tx_tail !=
priv->tx_curr ) {
864 tx_curr_desc =
priv->tx_ring +
priv->tx_tail;
872 DBG (
"Transmitted packet.\n" );
873 DBG (
"priv->tx_fill_ctr= %d\n",
priv->tx_fill_ctr );
874 DBG (
"priv->tx_tail = %d\n",
priv->tx_tail );
875 DBG (
"priv->tx_curr = %d\n",
priv->tx_curr );
882 memset ( tx_curr_desc, 0,
sizeof(*tx_curr_desc) );
908 DBGP (
"nv_process_rx_packets\n" );
912 rx_curr_desc =
priv->rx_ring +
priv->rx_curr;
921 curr_iob =
priv->rx_iobuf[
priv->rx_curr];
922 DBG (
"%p %p\n", curr_iob,
priv->rx_iobuf[
priv->rx_curr] );
923 if ( curr_iob ==
NULL )
926 DBG (
"Received packet.\n" );
927 DBG (
"priv->rx_curr = %d\n",
priv->rx_curr );
934 DBG (
" Corrupted packet received!\n" );
946 memset ( rx_curr_desc, 0,
sizeof(*rx_curr_desc) );
988 DBGP (
"forcedeth_poll\n" );
999 DBG (
"forcedeth_poll: status = %#04x\n",
status );
1023 DBGP (
"forcedeth_close\n" );
1050 DBGP (
"forcedeth_irq\n" );
1086 dev->hw_addr[0] = ( orig_mac[0] >> 0 ) & 0xff;
1087 dev->hw_addr[1] = ( orig_mac[0] >> 8 ) & 0xff;
1088 dev->hw_addr[2] = ( orig_mac[0] >> 16 ) & 0xff;
1089 dev->hw_addr[3] = ( orig_mac[0] >> 24 ) & 0xff;
1090 dev->hw_addr[4] = ( orig_mac[1] >> 0 ) & 0xff;
1091 dev->hw_addr[5] = ( orig_mac[1] >> 8 ) & 0xff;
1094 dev->hw_addr[0] = ( orig_mac[1] >> 8 ) & 0xff;
1095 dev->hw_addr[1] = ( orig_mac[1] >> 0 ) & 0xff;
1096 dev->hw_addr[2] = ( orig_mac[0] >> 24 ) & 0xff;
1097 dev->hw_addr[3] = ( orig_mac[0] >> 16 ) & 0xff;
1098 dev->hw_addr[4] = ( orig_mac[0] >> 8 ) & 0xff;
1099 dev->hw_addr[5] = ( orig_mac[0] >> 0 ) & 0xff;
1115 u32 tx_ctrl, mgmt_sema;
1117 for ( i = 0; i < 10; i++ ) {
1128 for ( i = 0; i < 2; i++ ) {
1139 priv->mgmt_sema = 1;
1156 if (
priv->mgmt_sema ) {
1169 u32 data_ready2 = 0;
1170 unsigned long start;
1192 priv->mgmt_version =
1204 unsigned int tries = 0;
1217 if ( tries++ > 100 )
1227 u32 phyinterface, phy_reserved, mii_status;
1228 u32 mii_control, mii_control_1000,
reg;
1235 DBG (
"PHY write to errata reg failed.\n" );
1245 DBG (
"PHY init failed.\n" );
1250 DBG (
"PHY init failed.\n" );
1255 DBG (
"PHY init failed.\n" );
1260 DBG (
"PHY init failed.\n" );
1265 DBG (
"PHY init failed.\n" );
1270 DBG (
"PHY init failed.\n" );
1275 DBG (
"PHY init failed.\n" );
1298 DBG (
"PHY init failed.\n" );
1303 DBG (
"PHY init failed.\n" );
1313 DBG (
"PHY init failed.\n" );
1319 DBG (
"PHY init failed.\n" );
1332 DBG (
"PHY init failed.\n" );
1344 DBG (
"PHY init failed.\n" );
1364 DBG (
"PHY init failed.\n" );
1380 DBG (
"PHY init failed.\n" );
1388 DBG (
"PHY reset failed\n" );
1399 DBG (
"PHY init failed.\n" );
1405 DBG (
"PHY init failed.\n" );
1413 DBG (
"PHY init failed.\n" );
1420 DBG (
"PHY init failed.\n" );
1425 DBG (
"PHY init failed.\n" );
1432 DBG (
"PHY init failed.\n" );
1441 DBG (
"PHY init failed.\n" );
1446 DBG (
"PHY init failed.\n" );
1451 DBG (
"PHY init failed.\n" );
1460 DBG (
"PHY init failed.\n" );
1467 DBG (
"PHY init failed.\n" );
1472 DBG (
"PHY init failed.\n" );
1477 DBG (
"PHY init failed.\n" );
1484 DBG (
"PHY init failed.\n" );
1493 DBG (
"PHY init failed.\n" );
1498 DBG (
"PHY init failed.\n" );
1503 DBG (
"PHY init failed.\n" );
1514 DBG (
"PHY init failed.\n" );
1519 DBG (
"PHY init failed.\n" );
1524 DBG (
"PHY init failed.\n" );
1529 DBG (
"PHY init failed.\n" );
1534 DBG (
"PHY init failed.\n" );
1539 DBG (
"PHY init failed.\n" );
1544 DBG (
"PHY init failed.\n" );
1557 DBG (
"PHY init failed.\n" );
1565 DBG (
"PHY init failed.\n" );
1576 DBG (
"PHY init failed.\n" );
1582 DBG (
"PHY init failed.\n" );
1612 u32 phystate_orig = 0, phystate;
1613 int phyinitialised = 0;
1623 ( (
priv->pci_dev->class & 0xff ) >= 0xA3 ) )
1645 priv->mac_in_use = 1;
1646 if (
priv->mgmt_version > 0 ) {
1650 DBG (
"mgmt unit is running. mac in use\n" );
1653 if (
priv->mac_in_use &&
1658 DBG (
"Phy already initialized by mgmt unit" );
1664 for ( i = 1; i <= 32; i++ ) {
1666 int phyaddr = i & 0x1f;
1669 if ( id1 < 0 || id1 == 0xffff )
1672 if ( id2 < 0 || id2 == 0xffff )
1678 DBG (
"Found PHY: %04x:%04x at address %d\n", id1, id2, phyaddr );
1679 priv->phyaddr = phyaddr;
1680 priv->phy_oui = id1 | id2;
1693 DBG (
"Could not find a valid PHY.\n" );
1698 if ( ! phyinitialised ) {
1711 if ( phystate_orig )
1760 DBG (
"Couldn't find register window\n" );
1767 DBG (
"Cannot remap MMIO\n" );
1796 DBGP (
"forcedeth_probe\n" );
1798 DBG (
"Found %s, vendor = %#04x, device = %#04x\n",
1805 DBG (
"Failed to allocate net device\n" );
1806 goto err_alloc_etherdev;
1820 priv->pci_dev = pdev;
1833 DBG (
"Invalid MAC address detected\n" );
1861 DBG (
"Error registering netdev\n" );
1862 goto err_register_netdev;
1869 err_register_netdev:
1883 u16 phy_reserved, mii_control;
1916 DBGP (
"forcedeth_remove\n" );
#define NVREG_TX_PAUSEFRAME_ENABLE_V1
#define PHY_VITESSE_INIT_REG3
#define PHY_REALTEK_INIT_REG7
static struct net_device_operations forcedeth_operations
#define EINVAL
Invalid argument.
#define NVREG_LINKSPEED_10
#define NVREG_TX_WM_DESC1_DEFAULT
#define DEV_HAS_LARGEDESC
#define NVREG_XMITCTL_MGMT_ST
struct arbelprm_rc_send_wqe rc
static void netdev_tx_complete(struct net_device *netdev, struct io_buffer *iobuf)
Complete network transmission.
static void nv_stop_tx(struct forcedeth_private *priv)
uint32_t low
Low 16 bits of address.
#define NV_PAUSEFRAME_AUTONEG
#define DEV_HAS_PAUSEFRAME_TX_V3
#define iob_put(iobuf, len)
#define NVREG_XMITCTL_START
#define TICKS_PER_SEC
Number of ticks per second.
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
#define DEV_HAS_CORRECT_MACADDR
#define ADVERTISE_1000FULL
void msg(unsigned int row, const char *fmt,...)
Print message centred on specified row.
#define PHY_REALTEK_INIT11
#define PHY_REALTEK_INIT4
static unsigned int unsigned int reg
#define PHY_REALTEK_INIT6
#define NVREG_MIISTAT_MASK_RW
#define NV_PAUSEFRAME_TX_ENABLE
#define NVREG_PFF_PAUSE_RX
#define le32_to_cpu(value)
int(* open)(struct net_device *netdev)
Open network device.
#define PHY_VITESSE_INIT3
#define PHY_VITESSE_INIT5
#define NVREG_ADAPTCTL_RUNNING
#define PHY_MODEL_REALTEK_8211
#define NVREG_XMITCTL_DATA_ERROR
#define NVREG_ADAPTCTL_PHYSHIFT
struct pci_driver forcedeth_driver __pci_driver
#define PHY_REALTEK_INIT9
unsigned long driver_data
Arbitrary driver data.
#define NVREG_RCVSTAT_BUSY
#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
struct pci_device_id * ids
PCI ID table.
#define NVREG_TX_DEFERRAL_MII_STRETCH
#define DEV_NEED_TIMERIRQ
uint8_t size
Entry size (in 32-bit words)
#define NVREG_TXRXCTL_RESET
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
static int phy_reset(struct forcedeth_private *priv, u32 bmcr_setup)
static void nv_init_tx_ring(struct forcedeth_private *priv)
static int phy_init(struct forcedeth_private *priv)
#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE
static int nv_setup_phy(struct forcedeth_private *priv)
nv_setup_phy - Find PHY and initialize it
static void nv_alloc_rx(struct forcedeth_private *priv)
nv_alloc_rx - Allocates iobufs for every Rx descriptor that doesn't have one and isn't in use by the ...
static int reg_delay(struct forcedeth_private *priv, int offset, u32 mask, u32 target, int delay, int delaymax, const char *msg)
static void *__malloc malloc_phys(size_t size, size_t phys_align)
Allocate memory with specified physical alignment.
#define ADVERTISE_100FULL
#define PHY_REALTEK_INIT3
#define PHY_VITESSE_INIT_REG4
#define PCI_BASE_ADDRESS_0
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
#define NVREG_TRANSMITPOLL_MAC_ADDR_REV
#define NVREG_TX_PAUSEFRAME_ENABLE_V2
static void forcedeth_poll(struct net_device *netdev)
poll - Poll for received packets
#define PHY_REALTEK_INIT_MSK1
#define NVREG_LINKSPEED_MASK
#define PHY_REV_REALTEK_8211B
#define PCI_BASE_ADDRESS_5
#define NVREG_SLOTTIME_1000_FULL
#define NVREG_POWERSTATE_POWEREDUP
#define DEV_NEED_PHY_INIT_FIX
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
#define NV_MAC_RESET_DELAY
#define NVREG_XMITCTL_DATA_READY
struct device dev
Generic device.
static struct pci_device_id forcedeth_nics[]
#define NVREG_LINKSPEED_1000
#define NV_PCI_REGSZ_VER3
#define PHY_MARVELL_E3016_INITMASK
static void nv_mgmt_release_sema(struct forcedeth_private *priv)
Dynamic memory allocation.
#define NVREG_MISC1_FORCE
#define NVREG_TXRXCTL_DESC_1
#define PHY_REALTEK_INIT5
static void nv_start_tx(struct forcedeth_private *priv)
uint32_t start
Starting offset.
#define DEV_HAS_STATISTICS_V1
#define DEV_HAS_PAUSEFRAME_TX_V2
#define DEV_HAS_STATISTICS_V2
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
#define ENOMEM
Not enough space.
static void forcedeth_irq(struct net_device *netdev, int action)
irq - enable or disable interrupts
static unsigned long ioaddr
#define PHY_VITESSE_INIT1
#define DEV_HAS_COLLISION_FIX
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
#define NVREG_POLL_DEFAULT_THROUGHPUT
#define NVREG_TX_DEFERRAL_DEFAULT
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
static int forcedeth_probe(struct pci_device *pdev)
probe - Initial configuration of NIC
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
#define PHY_VITESSE_INIT_MSK2
#define PHY_VITESSE_INIT6
#define NVREG_MIICTL_ADDRSHIFT
static void nv_txrx_reset(struct forcedeth_private *priv)
void * priv
Driver private data.
#define NVREG_MISC1_PAUSE_TX
pseudo_bit_t value[0x00020]
#define NVREG_XMITCTL_MGMT_SEMA_MASK
#define NVREG_SLOTTIME_DEFAULT
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
static int nv_mgmt_get_version(struct forcedeth_private *priv)
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define DEV_HAS_TEST_EXTENDED
#define NVREG_POWERSTATE2_POWERUP_MASK
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
#define BMSR_ANEGCOMPLETE
static int netdev_link_ok(struct net_device *netdev)
Check link state of network device.
static struct net_device * netdev
#define NVREG_XMITCTL_HOST_SEMA_MASK
#define NVREG_RCVCTL_START
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
static int nv_setup_mac_addr(struct forcedeth_private *priv)
#define DEV_HAS_POWER_CNTRL
void unregister_netdev(struct net_device *netdev)
Unregister network device.
#define NVREG_TX_DEFERRAL_RGMII_1000
#define NVREG_XMITCTL_TX_PATH_EN
static int forcedeth_transmit(struct net_device *netdev, struct io_buffer *iobuf)
transmit - Transmit a packet
#define cpu_to_le32(value)
#define PHYID2_MODEL_MASK
#define NVREG_RCVCTL_RX_PATH_EN
#define NV_PAUSEFRAME_TX_CAPABLE
#define PHY_REALTEK_INIT_REG3
#define NVREG_TXRXCTL_KICK
#define NVREG_TX_DEFERRAL_RGMII_10_100
static int forcedeth_open(struct net_device *netdev)
open - Called when a network interface is made active
#define NVREG_XMITSTAT_BUSY
#define ADVERTISE_PAUSE_ASYM
#define PHY_REALTEK_INIT_REG4
#define NVREG_MCASTMASKB_NONE
#define NVREG_POWERSTATE2_POWERUP_REV_A3
#define PHY_VITESSE_INIT7
#define NVREG_XMITCTL_SYNC_MASK
#define NV_TXRX_RESET_DELAY
#define NVREG_LINKSPEED_FORCE
static void nv_mac_reset(struct forcedeth_private *priv)
#define NV_PAUSEFRAME_RX_ENABLE
int register_netdev(struct net_device *netdev)
Register network device.
#define DEV_NEED_LOW_POWER_FIX
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
#define PHY_VITESSE_INIT10
static void nv_free_rxtx_resources(struct forcedeth_private *priv)
FILE_LICENCE(GPL2_OR_LATER)
#define DEV_HAS_MGMT_UNIT
#define DEV_NEED_LINKTIMER
static void nv_stop_rx(struct forcedeth_private *priv)
long int random(void)
Generate a pseudo-random number between 0 and 2147483647L or 2147483562?
#define NVREG_RX_DEFERRAL_DEFAULT
#define ENODEV
No such device.
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
#define NVREG_MII_LINKCHANGE
static int nv_mgmt_acquire_sema(struct forcedeth_private *priv)
#define NVREG_TX_PAUSEFRAME_ENABLE_V3
#define PHY_REALTEK_INIT_REG1
#define NVREG_MIICTL_INUSE
static int mii_rw(struct forcedeth_private *priv, int addr, int miireg, int value)
#define NVREG_IRQMASK_THROUGHPUT
#define PHY_VITESSE_INIT2
A PCI device ID list entry.
#define ADVERTISE_1000HALF
#define NVREG_XMITCTL_MGMT_SEMA_FREE
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
#define NVREG_POWERSTATE_VALID
#define NVREG_XMITCTL_HOST_SEMA_ACQ
#define PCI_BASE_ADDRESS_SPACE_IO
I/O BAR.
#define NV_TXSTOP_DELAY1MAX
#define NV_SETUP5_DELAYMAX
Network device operations.
static void nv_init_rx_ring(struct forcedeth_private *priv)
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
struct device * dev
Underlying hardware device.
#define EADDRNOTAVAIL
Address not available.
Network device management.
#define PHY_REALTEK_INIT_REG6
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
#define NVREG_RINGSZ_RXSHIFT
uint16_t vendor
PCI vendor ID.
#define NVREG_MGMTUNITVERSION
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
static void nv_txrx_gate(struct forcedeth_private *priv, int gate)
#define NVREG_TXRXCTL_BIT2
static void forcedeth_link_status(struct net_device *netdev)
check_link - Check for link status change
#define DEV_NEED_TX_LIMIT
uint16_t device
PCI device ID.
static void nv_update_pause(struct forcedeth_private *priv, u32 pause_flags)
#define NV_PAUSEFRAME_RX_REQ
#define NV_PAUSEFRAME_RX_CAPABLE
#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10
static void nv_enable_hw_interrupts(struct forcedeth_private *priv)
#define PHY_VITESSE_INIT_REG1
#define NVREG_MCASTMASKA_NONE
#define NVREG_SLOTTIME_10_100_FULL
#define PHY_REV_REALTEK_8211C
#define PHY_MODEL_MARVELL_E3016
#define PHY_REALTEK_INIT8
#define NVREG_RINGSZ_TXSHIFT
#define ENOBUFS
No buffer space available.
#define NVREG_MIISTAT_LINKCHANGE
static struct tlan_private * priv
Media Independent Interface constants.
static void nv_process_rx_packets(struct net_device *netdev)
nv_process_rx_packets - Checks for received packets, reports them to iPXE with netdev_rx() or netdev_...
static int forcedeth_map_regs(struct forcedeth_private *priv)
forcedeth_map_regs - Find a suitable BAR for the NIC and map the registers in memory
#define PHY_REALTEK_INIT7
uint16_t delay
Forward delay.
#define NVREG_UNKSETUP6_VAL
void * data
Start of data.
#define PHY_REALTEK_INIT_REG5
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
struct pci_device_id * id
Driver device ID.
static int nv_update_linkspeed(struct forcedeth_private *priv)
static void forcedeth_close(struct net_device *netdev)
close - Disable network interface
static void pci_push(void *ioaddr)
#define NVREG_XMITCTL_SYNC_PHY_INIT
static void nv_disable_hw_interrupts(struct forcedeth_private *priv)
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define NV_MIIPHY_DELAYMAX
#define NV_PCI_REGSZ_VER2
#define NVREG_ADAPTCTL_PHYVALID
#define NVREG_MIICTL_WRITE
#define NV_PAUSEFRAME_TX_REQ
#define DEV_HAS_PAUSEFRAME_TX_V1
#define PHY_REALTEK_INIT_REG2
#define PHY_REALTEK_INIT1
static int nv_init_rings(struct forcedeth_private *priv)
nv_init_rings - Allocate and intialize descriptor rings
#define PHY_VITESSE_INIT9
#define NVREG_MIISTAT_ERROR
static void free_phys(void *ptr, size_t size)
Free memory allocated with malloc_phys()
#define NVREG_MIISPEED_BIT8
#define NVREG_TX_PAUSEFRAME_DISABLE
uint16_t offset
Offset to command line.
#define DEV_HAS_STATISTICS_V3
#define NV_PCI_REGSZ_VER1
#define NV_RX_DESCRIPTORVALID
#define ADVERTISE_PAUSE_CAP
#define ADVERTISE_100HALF
static void forcedeth_remove(struct pci_device *pdev)
remove - Device Removal Routine
#define NVREG_LINKSPEED_100
unsigned long currticks(void)
Get current system time in ticks.
#define DBG(...)
Print a debugging message.
#define PHY_MODEL_REALTEK_8201
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
#define NVREG_POWERSTATE2_PHY_RESET
#define NVREG_MAC_RESET_ASSERT
#define NVREG_UNKSETUP5_BIT31
#define NVREG_TXRXCTL_BIT1
static void nv_restore_phy(struct forcedeth_private *priv)
#define NVREG_MGMTUNITCONTROL_INUSE
#define NVREG_XMITCTL_DATA_START
#define NVREG_POWERSTATE2_GATE_CLOCKS
#define NVREG_MIISTAT_MASK_ALL
#define NULL
NULL pointer (VOID *)
#define PHY_REALTEK_INIT10
#define PHY_VITESSE_INIT_REG2
#define NV_RXSTOP_DELAY1MAX
#define PCI_ROM(_vendor, _device, _name, _description, _data)
#define PHY_VITESSE_INIT_MSK1
void iob_pad(struct io_buffer *iobuf, size_t min_len)
Pad I/O buffer.
static void nv_process_tx_packets(struct net_device *netdev)
nv_process_tx_packets - Checks for successfully sent packets, reports them to iPXE with netdev_tx_com...
#define DEV_NEED_TX_LIMIT2
#define NVREG_PFF_PROMISC
static void nv_start_rx(struct forcedeth_private *priv)
#define PHY_REALTEK_INIT2
#define NVREG_SLOTTIME_MASK
#define DEV_HAS_GEAR_MODE
#define PHY_VITESSE_INIT8
#define PHY_VITESSE_INIT4
#define NVREG_IRQSTAT_MASK
void * memset(void *dest, int character, size_t len) __nonnull
#define NVREG_MGMTUNITGETVERSION