pcimsix.c File Reference

PCI MSI-X interrupts. More...

#include <stdint.h>
#include <errno.h>
#include <assert.h>
#include <ipxe/pci.h>
#include <ipxe/pcimsix.h>

Go to the source code of this file.

Functions
	FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
	FILE_SECBOOT (PERMITTED)
static const char *	pci_msix_name (unsigned int cfg)
	Get MSI-X descriptor name (for debugging)
static void *	pci_msix_ioremap (struct pci_device *pci, struct pci_msix *msix, unsigned int cfg)
	Map MSI-X BAR portion.
int	pci_msix_enable (struct pci_device *pci, struct pci_msix *msix)
	Enable MSI-X interrupts.
void	pci_msix_disable (struct pci_device *pci, struct pci_msix *msix)
	Disable MSI-X interrupts.
void	pci_msix_map (struct pci_msix *msix, unsigned int vector, physaddr_t address, uint32_t data)
	Map MSI-X interrupt vector.
void	pci_msix_control (struct pci_msix *msix, unsigned int vector, uint32_t mask)
	Control MSI-X interrupt vector.
void	pci_msix_dump (struct pci_msix *msix, unsigned int vector)
	Dump MSI-X interrupt state (for debugging)

Detailed Description

PCI MSI-X interrupts.

Interrupts as such are not used in iPXE, which operates in polling mode. However, some network cards (such as the Intel 40GbE and 100GbE NICs) will defer writing out completions until the point of asserting an MSI-X interrupt.

From the point of view of the PCI device, asserting an MSI-X interrupt is just a 32-bit DMA write of an opaque value to an opaque target address. The PCI device has no know to know whether or not the target address corresponds to a real APIC.

We can therefore trick the PCI device into believing that it is asserting an MSI-X interrupt, by configuring it to write an opaque 32-bit value to a dummy target address in host memory. This is sufficient to trigger the associated write of the completions to host memory.

When running in a virtual machine, the hypervisor will intercept our attempt to configure MSI-X on the PCI device. The physical hardware will be configured to raise an interrupt under the hypervisor's control, which will then be reflected back into the virtual machine. The opaque value that we write will be assumed to indicate an interrupt vector number (as would normally be the case when configuring MSI-X), and the opaque address will generally be ignored. The reflected interrupt will be ignored (since it is not enabled within the virtual machine), but the device still asserts an MSI-X interrupt and so still triggers the associated write of the completions to host memory.

Note that since the opaque target address will generally be ignored by the hypervisor, we cannot examine the value present at the dummy target address to find out whether or not an interrupt has been raised.

Definition in file pcimsix.c.

Function Documentation

FILE_LICENCE()

FILE_LICENCE

(

GPL2_OR_LATER_OR_UBDL

)

FILE_SECBOOT()

FILE_SECBOOT

(

PERMITTED

)

pci_msix_name()

const char * pci_msix_name ( unsigned int cfg )

static

Get MSI-X descriptor name (for debugging)

Parameters

cfg	Configuration space offset

Return values

name	Descriptor name

Definition at line 77 of file pcimsix.c.

                                                       {
 
        switch ( cfg ) {
        case PCI_MSIX_DESC_TABLE:    return "table";
        case PCI_MSIX_DESC_PBA:                return "PBA";
        default:                        return "<UNKNOWN>";
        }
}

References cfg, PCI_MSIX_DESC_PBA, and PCI_MSIX_DESC_TABLE.

Referenced by pci_msix_ioremap().

pci_msix_ioremap()

void * pci_msix_ioremap ( struct pci_device * pci, struct pci_msix * msix, unsigned int cfg )

static

Map MSI-X BAR portion.

Parameters

pci	PCI device
msix	MSI-X capability
cfg	Configuration space offset

Return values

io	I/O address

Definition at line 94 of file pcimsix.c.

                                                    {
        uint32_t desc;
        unsigned int bar;
        unsigned long start;
        unsigned long offset;
        unsigned long base;
        void *io;
 
        /* Read descriptor */
        pci_read_config_dword ( pci, ( msix->cap + cfg ), &desc );
 
        /* Get BAR */
        bar = PCI_MSIX_DESC_BIR ( desc );
        offset = PCI_MSIX_DESC_OFFSET ( desc );
        start = pci_bar_start ( pci, PCI_BASE_ADDRESS ( bar ) );
        if ( ! start ) {
                DBGC ( msix, "MSI-X %p %s could not find BAR%d\n",
                       msix, pci_msix_name ( cfg ), bar );
                return NULL;
        }
        base = ( start + offset );
        DBGC ( msix, "MSI-X %p %s at %#08lx (BAR%d+%#lx)\n",
               msix, pci_msix_name ( cfg ), base, bar, offset );
 
        /* Map BAR portion */
        io = pci_ioremap ( pci, ( start + offset ), PCI_MSIX_LEN );
        if ( ! io ) {
                DBGC ( msix, "MSI-X %p %s could not map %#08lx\n",
                       msix, pci_msix_name ( cfg ), base );
                return NULL;
        }
 
        return io;
}

References base, pci_msix::cap, cfg, DBGC, desc, NULL, offset, pci_bar_start(), PCI_BASE_ADDRESS, pci_ioremap(), PCI_MSIX_DESC_BIR, PCI_MSIX_DESC_OFFSET, PCI_MSIX_LEN, pci_msix_name(), pci_read_config_dword(), and start.

Referenced by pci_msix_enable().

pci_msix_enable()

int pci_msix_enable	(	struct pci_device *	pci,
		struct pci_msix *	msix )

Enable MSI-X interrupts.

Parameters

pci	PCI device
msix	MSI-X capability

Return values

rc	Return status code

Definition at line 137 of file pcimsix.c.

                                                                      {
        uint16_t ctrl;
        physaddr_t msg;
        unsigned int i;
        int rc;
 
        /* Locate capability */
        msix->cap = pci_find_capability ( pci, PCI_CAP_ID_MSIX );
        if ( ! msix->cap ) {
                DBGC ( msix, "MSI-X %p found no MSI-X capability in "
                       PCI_FMT "\n", msix, PCI_ARGS ( pci ) );
                rc = -ENOENT;
                goto err_cap;
        }
 
        /* Extract interrupt count */
        pci_read_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), &ctrl );
        msix->count = ( PCI_MSIX_CTRL_SIZE ( ctrl ) + 1 );
        DBGC ( msix, "MSI-X %p has %d vectors for " PCI_FMT "\n",
               msix, msix->count, PCI_ARGS ( pci ) );
 
        /* Map MSI-X table */
        msix->table = pci_msix_ioremap ( pci, msix, PCI_MSIX_DESC_TABLE );
        if ( ! msix->table ) {
                rc = -ENOENT;
                goto err_table;
        }
 
        /* Map pending bit array */
        msix->pba = pci_msix_ioremap ( pci, msix, PCI_MSIX_DESC_PBA );
        if ( ! msix->pba ) {
                rc = -ENOENT;
                goto err_pba;
        }
 
        /* Allocate dummy target */
        msix->msg = dma_alloc ( &pci->dma, &msix->map, sizeof ( *msix->msg ),
                                sizeof ( *msix->msg ) );
        if ( ! msix->msg ) {
                rc = -ENOMEM;
                goto err_msg;
        }
 
        /* Map all interrupts to dummy target by default */
        msg = dma ( &msix->map, msix->msg );
        for ( i = 0 ; i < msix->count ; i++ )
                pci_msix_map ( msix, i, msg, 0 );
 
        /* Enable MSI-X */
        ctrl &= ~PCI_MSIX_CTRL_MASK;
        ctrl |= PCI_MSIX_CTRL_ENABLE;
        pci_write_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), ctrl );
 
        return 0;
 
        dma_free ( &msix->map, msix->msg, sizeof ( *msix->msg ) );
 err_msg:
        iounmap ( msix->pba );
 err_pba:
        iounmap ( msix->table );
 err_table:
 err_cap:
        return rc;
}

References pci_msix::cap, pci_msix::count, ctrl, DBGC, dma(), pci_device::dma, dma_alloc(), dma_free(), ENOENT, ENOMEM, iounmap(), pci_msix::map, msg(), pci_msix::msg, pci_msix::pba, PCI_ARGS, PCI_CAP_ID_MSIX, pci_find_capability(), PCI_FMT, PCI_MSIX_CTRL, PCI_MSIX_CTRL_ENABLE, PCI_MSIX_CTRL_MASK, PCI_MSIX_CTRL_SIZE, PCI_MSIX_DESC_PBA, PCI_MSIX_DESC_TABLE, pci_msix_ioremap(), pci_msix_map(), pci_read_config_word(), pci_write_config_word(), rc, and pci_msix::table.

Referenced by gve_probe(), and intelxl_msix_enable().

pci_msix_disable()

void pci_msix_disable	(	struct pci_device *	pci,
		struct pci_msix *	msix )

Disable MSI-X interrupts.

Parameters

pci	PCI device
msix	MSI-X capability

Definition at line 208 of file pcimsix.c.

                                                                        {
        uint16_t ctrl;
 
        /* Disable MSI-X */
        pci_read_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), &ctrl );
        ctrl &= ~PCI_MSIX_CTRL_ENABLE;
        pci_write_config_word ( pci, ( msix->cap + PCI_MSIX_CTRL ), ctrl );
 
        /* Free dummy target */
        dma_free ( &msix->map, msix->msg, sizeof ( *msix->msg ) );
 
        /* Unmap pending bit array */
        iounmap ( msix->pba );
 
        /* Unmap MSI-X table */
        iounmap ( msix->table );
}

References pci_msix::cap, ctrl, dma_free(), iounmap(), pci_msix::map, pci_msix::msg, pci_msix::pba, PCI_MSIX_CTRL, PCI_MSIX_CTRL_ENABLE, pci_read_config_word(), pci_write_config_word(), and pci_msix::table.

Referenced by gve_probe(), gve_remove(), intelxl_msix_disable(), and intelxl_msix_enable().

pci_msix_map()

void pci_msix_map	(	struct pci_msix *	msix,
		unsigned int	vector,
		physaddr_t	address,
		uint32_t	data )

Map MSI-X interrupt vector.

Parameters

msix	MSI-X capability
vector	MSI-X vector
address	Message address
data	Message data

Definition at line 234 of file pcimsix.c.

                                                        {
        void *base;
 
        /* Sanity check */
        assert ( vector < msix->count );
 
        /* Map interrupt vector */
        base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
        writel ( ( address & 0xffffffffUL ), ( base + PCI_MSIX_ADDRESS_LO ) );
        if ( sizeof ( address ) > sizeof ( uint32_t ) ) {
                writel ( ( ( ( uint64_t ) address ) >> 32 ),
                         ( base + PCI_MSIX_ADDRESS_HI ) );
        } else {
                writel ( 0, ( base + PCI_MSIX_ADDRESS_HI ) );
        }
        writel ( data, ( base + PCI_MSIX_DATA ) );
}

References address, assert, base, count, data, PCI_MSIX_ADDRESS_HI, PCI_MSIX_ADDRESS_LO, PCI_MSIX_DATA, PCI_MSIX_VECTOR, pci_msix::table, vector, and writel.

Referenced by pci_msix_enable().

pci_msix_control()

void pci_msix_control	(	struct pci_msix *	msix,
		unsigned int	vector,
		uint32_t	mask )

Control MSI-X interrupt vector.

Parameters

msix	MSI-X capability
vector	MSI-X vector
mask	Control mask

Definition at line 260 of file pcimsix.c.

                                        {
        void *base;
        uint32_t ctrl;
 
        /* Mask/unmask interrupt vector */
        base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
        ctrl = readl ( base + PCI_MSIX_CONTROL );
        ctrl &= ~PCI_MSIX_CONTROL_MASK;
        ctrl |= mask;
        writel ( ctrl, ( base + PCI_MSIX_CONTROL ) );
}

References base, ctrl, PCI_MSIX_CONTROL, PCI_MSIX_CONTROL_MASK, PCI_MSIX_VECTOR, readl, pci_msix::table, vector, and writel.

Referenced by pci_msix_mask(), and pci_msix_unmask().

pci_msix_dump()

void pci_msix_dump	(	struct pci_msix *	msix,
		unsigned int	vector )

Dump MSI-X interrupt state (for debugging)

Parameters

msix	MSI-X capability
vector	MSI-X vector

Definition at line 279 of file pcimsix.c.

                                                                  {
        void *base;
        uint32_t address_hi;
        uint32_t address_lo;
        physaddr_t address;
        uint32_t data;
        uint32_t ctrl;
        uint32_t pba;
 
        /* Do nothing in non-debug builds */
        if ( ! DBG_LOG )
                return;
 
        /* Mask/unmask interrupt vector */
        base = ( msix->table + PCI_MSIX_VECTOR ( vector ) );
        address_hi = readl ( base + PCI_MSIX_ADDRESS_HI );
        address_lo = readl ( base + PCI_MSIX_ADDRESS_LO );
        data = readl ( base + PCI_MSIX_DATA );
        ctrl = readl ( base + PCI_MSIX_CONTROL );
        pba = readl ( msix->pba );
        address = ( ( ( ( uint64_t ) address_hi ) << 32 ) | address_lo );
        DBGC ( msix, "MSI-X %p vector %d %#08x => %#08lx%s%s\n",
               msix, vector, data, address,
               ( ( ctrl & PCI_MSIX_CONTROL_MASK ) ? " (masked)" : "" ),
               ( ( pba & ( 1 << vector ) ) ? " (pending)" : "" ) );
}

References address, base, ctrl, data, DBG_LOG, DBGC, pci_msix::pba, PCI_MSIX_ADDRESS_HI, PCI_MSIX_ADDRESS_LO, PCI_MSIX_CONTROL, PCI_MSIX_CONTROL_MASK, PCI_MSIX_DATA, PCI_MSIX_VECTOR, readl, pci_msix::table, and vector.