iPXE
sky2.c
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00001 /*
00002  * iPXE driver for Marvell Yukon 2 chipset. Derived from Linux sky2 driver
00003  * (v1.22), which was based on earlier sk98lin and skge drivers.
00004  *
00005  * This driver intentionally does not support all the features
00006  * of the original driver such as link fail-over and link management because
00007  * those should be done at higher levels.
00008  *
00009  * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
00010  *
00011  * Modified for iPXE, April 2009 by Joshua Oreman
00012  *
00013  * This program is free software; you can redistribute it and/or modify
00014  * it under the terms of the GNU General Public License as published by
00015  * the Free Software Foundation; either version 2 of the License.
00016  *
00017  * This program is distributed in the hope that it will be useful,
00018  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00019  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
00020  * GNU General Public License for more details.
00021  *
00022  * You should have received a copy of the GNU General Public License
00023  * along with this program; if not, write to the Free Software
00024  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
00025  * 02110-1301, USA.
00026  */
00027 
00028 FILE_LICENCE ( GPL2_ONLY );
00029 
00030 #include <stdint.h>
00031 #include <errno.h>
00032 #include <stdio.h>
00033 #include <unistd.h>
00034 #include <ipxe/ethernet.h>
00035 #include <ipxe/if_ether.h>
00036 #include <ipxe/iobuf.h>
00037 #include <ipxe/malloc.h>
00038 #include <ipxe/pci.h>
00039 #include <byteswap.h>
00040 #include <mii.h>
00041 
00042 #include "sky2.h"
00043 
00044 #define DRV_NAME                "sky2"
00045 #define DRV_VERSION             "1.22"
00046 #define PFX                     DRV_NAME " "
00047 
00048 /*
00049  * The Yukon II chipset takes 64 bit command blocks (called list elements)
00050  * that are organized into three (receive, transmit, status) different rings
00051  * similar to Tigon3.
00052  *
00053  * Each ring start must be aligned to a 4k boundary. You will get mysterious
00054  * "invalid LE" errors if they're not.
00055  *
00056  * The card silently forces each ring size to be at least 128. If you
00057  * act as though one of them is smaller (by setting the below
00058  * #defines) you'll get bad bugs.
00059  */
00060 
00061 #define RX_LE_SIZE              128
00062 #define RX_LE_BYTES             (RX_LE_SIZE*sizeof(struct sky2_rx_le))
00063 #define RX_RING_ALIGN           4096
00064 #define RX_PENDING              (RX_LE_SIZE/6 - 2)
00065 
00066 #define TX_RING_SIZE            128
00067 #define TX_PENDING              (TX_RING_SIZE - 1)
00068 #define TX_RING_ALIGN           4096
00069 #define MAX_SKB_TX_LE           4
00070 
00071 #define STATUS_RING_SIZE        512     /* 2 ports * (TX + RX) */
00072 #define STATUS_LE_BYTES         (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
00073 #define STATUS_RING_ALIGN       4096
00074 #define PHY_RETRIES             1000
00075 
00076 #define SKY2_EEPROM_MAGIC       0x9955aabb
00077 
00078 
00079 #define RING_NEXT(x,s)  (((x)+1) & ((s)-1))
00080 
00081 static struct pci_device_id sky2_id_table[] = {
00082         PCI_ROM(0x1148, 0x9000, "sk9sxx", "Syskonnect SK-9Sxx", 0),
00083         PCI_ROM(0x1148, 0x9e00, "sk9exx", "Syskonnect SK-9Exx", 0),
00084         PCI_ROM(0x1186, 0x4b00, "dge560t", "D-Link DGE-560T", 0),
00085         PCI_ROM(0x1186, 0x4001, "dge550sx", "D-Link DGE-550SX", 0),
00086         PCI_ROM(0x1186, 0x4b02, "dge560sx", "D-Link DGE-560SX", 0),
00087         PCI_ROM(0x1186, 0x4b03, "dge550t", "D-Link DGE-550T", 0),
00088         PCI_ROM(0x11ab, 0x4340, "m88e8021", "Marvell 88E8021", 0),
00089         PCI_ROM(0x11ab, 0x4341, "m88e8022", "Marvell 88E8022", 0),
00090         PCI_ROM(0x11ab, 0x4342, "m88e8061", "Marvell 88E8061", 0),
00091         PCI_ROM(0x11ab, 0x4343, "m88e8062", "Marvell 88E8062", 0),
00092         PCI_ROM(0x11ab, 0x4344, "m88e8021b", "Marvell 88E8021", 0),
00093         PCI_ROM(0x11ab, 0x4345, "m88e8022b", "Marvell 88E8022", 0),
00094         PCI_ROM(0x11ab, 0x4346, "m88e8061b", "Marvell 88E8061", 0),
00095         PCI_ROM(0x11ab, 0x4347, "m88e8062b", "Marvell 88E8062", 0),
00096         PCI_ROM(0x11ab, 0x4350, "m88e8035", "Marvell 88E8035", 0),
00097         PCI_ROM(0x11ab, 0x4351, "m88e8036", "Marvell 88E8036", 0),
00098         PCI_ROM(0x11ab, 0x4352, "m88e8038", "Marvell 88E8038", 0),
00099         PCI_ROM(0x11ab, 0x4353, "m88e8039", "Marvell 88E8039", 0),
00100         PCI_ROM(0x11ab, 0x4354, "m88e8040", "Marvell 88E8040", 0),
00101         PCI_ROM(0x11ab, 0x4355, "m88e8040t", "Marvell 88E8040T", 0),
00102         PCI_ROM(0x11ab, 0x4356, "m88ec033", "Marvel 88EC033", 0),
00103         PCI_ROM(0x11ab, 0x4357, "m88e8042", "Marvell 88E8042", 0),
00104         PCI_ROM(0x11ab, 0x435a, "m88e8048", "Marvell 88E8048", 0),
00105         PCI_ROM(0x11ab, 0x4360, "m88e8052", "Marvell 88E8052", 0),
00106         PCI_ROM(0x11ab, 0x4361, "m88e8050", "Marvell 88E8050", 0),
00107         PCI_ROM(0x11ab, 0x4362, "m88e8053", "Marvell 88E8053", 0),
00108         PCI_ROM(0x11ab, 0x4363, "m88e8055", "Marvell 88E8055", 0),
00109         PCI_ROM(0x11ab, 0x4364, "m88e8056", "Marvell 88E8056", 0),
00110         PCI_ROM(0x11ab, 0x4365, "m88e8070", "Marvell 88E8070", 0),
00111         PCI_ROM(0x11ab, 0x4366, "m88ec036", "Marvell 88EC036", 0),
00112         PCI_ROM(0x11ab, 0x4367, "m88ec032", "Marvell 88EC032", 0),
00113         PCI_ROM(0x11ab, 0x4368, "m88ec034", "Marvell 88EC034", 0),
00114         PCI_ROM(0x11ab, 0x4369, "m88ec042", "Marvell 88EC042", 0),
00115         PCI_ROM(0x11ab, 0x436a, "m88e8058", "Marvell 88E8058", 0),
00116         PCI_ROM(0x11ab, 0x436b, "m88e8071", "Marvell 88E8071", 0),
00117         PCI_ROM(0x11ab, 0x436c, "m88e8072", "Marvell 88E8072", 0),
00118         PCI_ROM(0x11ab, 0x436d, "m88e8055b", "Marvell 88E8055", 0),
00119         PCI_ROM(0x11ab, 0x4370, "m88e8075", "Marvell 88E8075", 0),
00120         PCI_ROM(0x11ab, 0x4380, "m88e8057", "Marvell 88E8057", 0)
00121 };
00122 
00123 /* Avoid conditionals by using array */
00124 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
00125 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
00126 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
00127 
00128 static void sky2_set_multicast(struct net_device *dev);
00129 
00130 /* Access to PHY via serial interconnect */
00131 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
00132 {
00133         int i;
00134 
00135         gma_write16(hw, port, GM_SMI_DATA, val);
00136         gma_write16(hw, port, GM_SMI_CTRL,
00137                     GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
00138 
00139         for (i = 0; i < PHY_RETRIES; i++) {
00140                 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
00141                 if (ctrl == 0xffff)
00142                         goto io_error;
00143 
00144                 if (!(ctrl & GM_SMI_CT_BUSY))
00145                         return 0;
00146 
00147                 udelay(10);
00148         }
00149 
00150         DBG(PFX "%s: phy write timeout\n", hw->dev[port]->name);
00151         return -ETIMEDOUT;
00152 
00153 io_error:
00154         DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
00155         return -EIO;
00156 }
00157 
00158 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
00159 {
00160         int i;
00161 
00162         gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
00163                     | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
00164 
00165         for (i = 0; i < PHY_RETRIES; i++) {
00166                 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
00167                 if (ctrl == 0xffff)
00168                         goto io_error;
00169 
00170                 if (ctrl & GM_SMI_CT_RD_VAL) {
00171                         *val = gma_read16(hw, port, GM_SMI_DATA);
00172                         return 0;
00173                 }
00174 
00175                 udelay(10);
00176         }
00177 
00178         DBG(PFX "%s: phy read timeout\n", hw->dev[port]->name);
00179         return -ETIMEDOUT;
00180 io_error:
00181         DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
00182         return -EIO;
00183 }
00184 
00185 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
00186 {
00187         u16 v = 0;
00188         __gm_phy_read(hw, port, reg, &v);
00189         return v;
00190 }
00191 
00192 
00193 static void sky2_power_on(struct sky2_hw *hw)
00194 {
00195         /* switch power to VCC (WA for VAUX problem) */
00196         sky2_write8(hw, B0_POWER_CTRL,
00197                     PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
00198 
00199         /* disable Core Clock Division, */
00200         sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
00201 
00202         if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
00203                 /* enable bits are inverted */
00204                 sky2_write8(hw, B2_Y2_CLK_GATE,
00205                             Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
00206                             Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
00207                             Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
00208         else
00209                 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
00210 
00211         if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
00212                 u32 reg;
00213 
00214                 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
00215 
00216                 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
00217                 /* set all bits to 0 except bits 15..12 and 8 */
00218                 reg &= P_ASPM_CONTROL_MSK;
00219                 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
00220 
00221                 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
00222                 /* set all bits to 0 except bits 28 & 27 */
00223                 reg &= P_CTL_TIM_VMAIN_AV_MSK;
00224                 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
00225 
00226                 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
00227 
00228                 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
00229                 reg = sky2_read32(hw, B2_GP_IO);
00230                 reg |= GLB_GPIO_STAT_RACE_DIS;
00231                 sky2_write32(hw, B2_GP_IO, reg);
00232 
00233                 sky2_read32(hw, B2_GP_IO);
00234         }
00235 }
00236 
00237 static void sky2_power_aux(struct sky2_hw *hw)
00238 {
00239         if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
00240                 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
00241         else
00242                 /* enable bits are inverted */
00243                 sky2_write8(hw, B2_Y2_CLK_GATE,
00244                             Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
00245                             Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
00246                             Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
00247 
00248         /* switch power to VAUX */
00249         if (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL)
00250                 sky2_write8(hw, B0_POWER_CTRL,
00251                             (PC_VAUX_ENA | PC_VCC_ENA |
00252                              PC_VAUX_ON | PC_VCC_OFF));
00253 }
00254 
00255 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
00256 {
00257         u16 reg;
00258 
00259         /* disable all GMAC IRQ's */
00260         sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
00261 
00262         gma_write16(hw, port, GM_MC_ADDR_H1, 0);        /* clear MC hash */
00263         gma_write16(hw, port, GM_MC_ADDR_H2, 0);
00264         gma_write16(hw, port, GM_MC_ADDR_H3, 0);
00265         gma_write16(hw, port, GM_MC_ADDR_H4, 0);
00266 
00267         reg = gma_read16(hw, port, GM_RX_CTRL);
00268         reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
00269         gma_write16(hw, port, GM_RX_CTRL, reg);
00270 }
00271 
00272 /* flow control to advertise bits */
00273 static const u16 copper_fc_adv[] = {
00274         [FC_NONE]       = 0,
00275         [FC_TX]         = PHY_M_AN_ASP,
00276         [FC_RX]         = PHY_M_AN_PC,
00277         [FC_BOTH]       = PHY_M_AN_PC | PHY_M_AN_ASP,
00278 };
00279 
00280 /* flow control to advertise bits when using 1000BaseX */
00281 static const u16 fiber_fc_adv[] = {
00282         [FC_NONE] = PHY_M_P_NO_PAUSE_X,
00283         [FC_TX]   = PHY_M_P_ASYM_MD_X,
00284         [FC_RX]   = PHY_M_P_SYM_MD_X,
00285         [FC_BOTH] = PHY_M_P_BOTH_MD_X,
00286 };
00287 
00288 /* flow control to GMA disable bits */
00289 static const u16 gm_fc_disable[] = {
00290         [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
00291         [FC_TX]   = GM_GPCR_FC_RX_DIS,
00292         [FC_RX]   = GM_GPCR_FC_TX_DIS,
00293         [FC_BOTH] = 0,
00294 };
00295 
00296 
00297 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
00298 {
00299         struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
00300         u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
00301 
00302         if (sky2->autoneg == AUTONEG_ENABLE &&
00303             !(hw->flags & SKY2_HW_NEWER_PHY)) {
00304                 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
00305 
00306                 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
00307                            PHY_M_EC_MAC_S_MSK);
00308                 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
00309 
00310                 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
00311                 if (hw->chip_id == CHIP_ID_YUKON_EC)
00312                         /* set downshift counter to 3x and enable downshift */
00313                         ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
00314                 else
00315                         /* set master & slave downshift counter to 1x */
00316                         ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
00317 
00318                 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
00319         }
00320 
00321         ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
00322         if (sky2_is_copper(hw)) {
00323                 if (!(hw->flags & SKY2_HW_GIGABIT)) {
00324                         /* enable automatic crossover */
00325                         ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
00326 
00327                         if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
00328                             hw->chip_rev == CHIP_REV_YU_FE2_A0) {
00329                                 u16 spec;
00330 
00331                                 /* Enable Class A driver for FE+ A0 */
00332                                 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
00333                                 spec |= PHY_M_FESC_SEL_CL_A;
00334                                 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
00335                         }
00336                 } else {
00337                         /* disable energy detect */
00338                         ctrl &= ~PHY_M_PC_EN_DET_MSK;
00339 
00340                         /* enable automatic crossover */
00341                         ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
00342 
00343                         /* downshift on PHY 88E1112 and 88E1149 is changed */
00344                         if (sky2->autoneg == AUTONEG_ENABLE
00345                             && (hw->flags & SKY2_HW_NEWER_PHY)) {
00346                                 /* set downshift counter to 3x and enable downshift */
00347                                 ctrl &= ~PHY_M_PC_DSC_MSK;
00348                                 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
00349                         }
00350                 }
00351         } else {
00352                 /* workaround for deviation #4.88 (CRC errors) */
00353                 /* disable Automatic Crossover */
00354 
00355                 ctrl &= ~PHY_M_PC_MDIX_MSK;
00356         }
00357 
00358         gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
00359 
00360         /* special setup for PHY 88E1112 Fiber */
00361         if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
00362                 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
00363 
00364                 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
00365                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
00366                 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
00367                 ctrl &= ~PHY_M_MAC_MD_MSK;
00368                 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
00369                 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
00370 
00371                 if (hw->pmd_type  == 'P') {
00372                         /* select page 1 to access Fiber registers */
00373                         gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
00374 
00375                         /* for SFP-module set SIGDET polarity to low */
00376                         ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
00377                         ctrl |= PHY_M_FIB_SIGD_POL;
00378                         gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
00379                 }
00380 
00381                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
00382         }
00383 
00384         ctrl = PHY_CT_RESET;
00385         ct1000 = 0;
00386         adv = PHY_AN_CSMA;
00387         reg = 0;
00388 
00389         if (sky2->autoneg == AUTONEG_ENABLE) {
00390                 if (sky2_is_copper(hw)) {
00391                         if (sky2->advertising & ADVERTISED_1000baseT_Full)
00392                                 ct1000 |= PHY_M_1000C_AFD;
00393                         if (sky2->advertising & ADVERTISED_1000baseT_Half)
00394                                 ct1000 |= PHY_M_1000C_AHD;
00395                         if (sky2->advertising & ADVERTISED_100baseT_Full)
00396                                 adv |= PHY_M_AN_100_FD;
00397                         if (sky2->advertising & ADVERTISED_100baseT_Half)
00398                                 adv |= PHY_M_AN_100_HD;
00399                         if (sky2->advertising & ADVERTISED_10baseT_Full)
00400                                 adv |= PHY_M_AN_10_FD;
00401                         if (sky2->advertising & ADVERTISED_10baseT_Half)
00402                                 adv |= PHY_M_AN_10_HD;
00403 
00404                         adv |= copper_fc_adv[sky2->flow_mode];
00405                 } else {        /* special defines for FIBER (88E1040S only) */
00406                         if (sky2->advertising & ADVERTISED_1000baseT_Full)
00407                                 adv |= PHY_M_AN_1000X_AFD;
00408                         if (sky2->advertising & ADVERTISED_1000baseT_Half)
00409                                 adv |= PHY_M_AN_1000X_AHD;
00410 
00411                         adv |= fiber_fc_adv[sky2->flow_mode];
00412                 }
00413 
00414                 /* Restart Auto-negotiation */
00415                 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
00416         } else {
00417                 /* forced speed/duplex settings */
00418                 ct1000 = PHY_M_1000C_MSE;
00419 
00420                 /* Disable auto update for duplex flow control and speed */
00421                 reg |= GM_GPCR_AU_ALL_DIS;
00422 
00423                 switch (sky2->speed) {
00424                 case SPEED_1000:
00425                         ctrl |= PHY_CT_SP1000;
00426                         reg |= GM_GPCR_SPEED_1000;
00427                         break;
00428                 case SPEED_100:
00429                         ctrl |= PHY_CT_SP100;
00430                         reg |= GM_GPCR_SPEED_100;
00431                         break;
00432                 }
00433 
00434                 if (sky2->duplex == DUPLEX_FULL) {
00435                         reg |= GM_GPCR_DUP_FULL;
00436                         ctrl |= PHY_CT_DUP_MD;
00437                 } else if (sky2->speed < SPEED_1000)
00438                         sky2->flow_mode = FC_NONE;
00439 
00440 
00441                 reg |= gm_fc_disable[sky2->flow_mode];
00442 
00443                 /* Forward pause packets to GMAC? */
00444                 if (sky2->flow_mode & FC_RX)
00445                         sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
00446                 else
00447                         sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
00448         }
00449 
00450         gma_write16(hw, port, GM_GP_CTRL, reg);
00451 
00452         if (hw->flags & SKY2_HW_GIGABIT)
00453                 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
00454 
00455         gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
00456         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
00457 
00458         /* Setup Phy LED's */
00459         ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
00460         ledover = 0;
00461 
00462         switch (hw->chip_id) {
00463         case CHIP_ID_YUKON_FE:
00464                 /* on 88E3082 these bits are at 11..9 (shifted left) */
00465                 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
00466 
00467                 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
00468 
00469                 /* delete ACT LED control bits */
00470                 ctrl &= ~PHY_M_FELP_LED1_MSK;
00471                 /* change ACT LED control to blink mode */
00472                 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
00473                 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
00474                 break;
00475 
00476         case CHIP_ID_YUKON_FE_P:
00477                 /* Enable Link Partner Next Page */
00478                 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
00479                 ctrl |= PHY_M_PC_ENA_LIP_NP;
00480 
00481                 /* disable Energy Detect and enable scrambler */
00482                 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
00483                 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
00484 
00485                 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
00486                 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
00487                         PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
00488                         PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
00489 
00490                 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
00491                 break;
00492 
00493         case CHIP_ID_YUKON_XL:
00494                 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
00495 
00496                 /* select page 3 to access LED control register */
00497                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
00498 
00499                 /* set LED Function Control register */
00500                 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
00501                              (PHY_M_LEDC_LOS_CTRL(1) |  /* LINK/ACT */
00502                               PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
00503                               PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
00504                               PHY_M_LEDC_STA0_CTRL(7)));        /* 1000 Mbps */
00505 
00506                 /* set Polarity Control register */
00507                 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
00508                              (PHY_M_POLC_LS1_P_MIX(4) |
00509                               PHY_M_POLC_IS0_P_MIX(4) |
00510                               PHY_M_POLC_LOS_CTRL(2) |
00511                               PHY_M_POLC_INIT_CTRL(2) |
00512                               PHY_M_POLC_STA1_CTRL(2) |
00513                               PHY_M_POLC_STA0_CTRL(2)));
00514 
00515                 /* restore page register */
00516                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
00517                 break;
00518 
00519         case CHIP_ID_YUKON_EC_U:
00520         case CHIP_ID_YUKON_EX:
00521         case CHIP_ID_YUKON_SUPR:
00522                 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
00523 
00524                 /* select page 3 to access LED control register */
00525                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
00526 
00527                 /* set LED Function Control register */
00528                 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
00529                              (PHY_M_LEDC_LOS_CTRL(1) |  /* LINK/ACT */
00530                               PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
00531                               PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
00532                               PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
00533 
00534                 /* set Blink Rate in LED Timer Control Register */
00535                 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
00536                              ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
00537                 /* restore page register */
00538                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
00539                 break;
00540 
00541         default:
00542                 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
00543                 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
00544 
00545                 /* turn off the Rx LED (LED_RX) */
00546                 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
00547         }
00548 
00549         if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
00550                 /* apply fixes in PHY AFE */
00551                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
00552 
00553                 /* increase differential signal amplitude in 10BASE-T */
00554                 gm_phy_write(hw, port, 0x18, 0xaa99);
00555                 gm_phy_write(hw, port, 0x17, 0x2011);
00556 
00557                 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
00558                         /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
00559                         gm_phy_write(hw, port, 0x18, 0xa204);
00560                         gm_phy_write(hw, port, 0x17, 0x2002);
00561                 }
00562 
00563                 /* set page register to 0 */
00564                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
00565         } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
00566                    hw->chip_rev == CHIP_REV_YU_FE2_A0) {
00567                 /* apply workaround for integrated resistors calibration */
00568                 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
00569                 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
00570         } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
00571                    hw->chip_id < CHIP_ID_YUKON_SUPR) {
00572                 /* no effect on Yukon-XL */
00573                 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
00574 
00575                 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
00576                         /* turn on 100 Mbps LED (LED_LINK100) */
00577                         ledover |= PHY_M_LED_MO_100(MO_LED_ON);
00578                 }
00579 
00580                 if (ledover)
00581                         gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
00582 
00583         }
00584 
00585         /* Enable phy interrupt on auto-negotiation complete (or link up) */
00586         if (sky2->autoneg == AUTONEG_ENABLE)
00587                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
00588         else
00589                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
00590 }
00591 
00592 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
00593 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
00594 
00595 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
00596 {
00597         u32 reg1;
00598 
00599         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
00600         reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
00601         reg1 &= ~phy_power[port];
00602 
00603         if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
00604                 reg1 |= coma_mode[port];
00605 
00606         sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
00607         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
00608         sky2_pci_read32(hw, PCI_DEV_REG1);
00609 
00610         if (hw->chip_id == CHIP_ID_YUKON_FE)
00611                 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
00612         else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
00613                 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
00614 }
00615 
00616 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
00617 {
00618         u32 reg1;
00619         u16 ctrl;
00620 
00621         /* release GPHY Control reset */
00622         sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
00623 
00624         /* release GMAC reset */
00625         sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
00626 
00627         if (hw->flags & SKY2_HW_NEWER_PHY) {
00628                 /* select page 2 to access MAC control register */
00629                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
00630 
00631                 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
00632                 /* allow GMII Power Down */
00633                 ctrl &= ~PHY_M_MAC_GMIF_PUP;
00634                 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
00635 
00636                 /* set page register back to 0 */
00637                 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
00638         }
00639 
00640         /* setup General Purpose Control Register */
00641         gma_write16(hw, port, GM_GP_CTRL,
00642                     GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
00643 
00644         if (hw->chip_id != CHIP_ID_YUKON_EC) {
00645                 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
00646                         /* select page 2 to access MAC control register */
00647                         gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
00648 
00649                         ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
00650                         /* enable Power Down */
00651                         ctrl |= PHY_M_PC_POW_D_ENA;
00652                         gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
00653 
00654                         /* set page register back to 0 */
00655                         gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
00656                 }
00657 
00658                 /* set IEEE compatible Power Down Mode (dev. #4.99) */
00659                 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
00660         }
00661 
00662         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
00663         reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
00664         reg1 |= phy_power[port];                /* set PHY to PowerDown/COMA Mode */
00665         sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
00666         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
00667 }
00668 
00669 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
00670 {
00671         if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
00672               hw->chip_rev != CHIP_REV_YU_EX_A0) ||
00673              hw->chip_id == CHIP_ID_YUKON_FE_P ||
00674              hw->chip_id == CHIP_ID_YUKON_SUPR) {
00675                 /* disable jumbo frames on devices that support them */
00676                 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
00677                              TX_JUMBO_DIS | TX_STFW_ENA);
00678         } else {
00679                 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
00680         }
00681 }
00682 
00683 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
00684 {
00685         u16 reg;
00686         u32 rx_reg;
00687         int i;
00688         const u8 *addr = hw->dev[port]->ll_addr;
00689 
00690         sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
00691         sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
00692 
00693         sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
00694 
00695         if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
00696                 /* WA DEV_472 -- looks like crossed wires on port 2 */
00697                 /* clear GMAC 1 Control reset */
00698                 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
00699                 do {
00700                         sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
00701                         sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
00702                 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
00703                          gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
00704                          gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
00705         }
00706 
00707         sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
00708 
00709         /* Enable Transmit FIFO Underrun */
00710         sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
00711 
00712         sky2_phy_power_up(hw, port);
00713         sky2_phy_init(hw, port);
00714 
00715         /* MIB clear */
00716         reg = gma_read16(hw, port, GM_PHY_ADDR);
00717         gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
00718 
00719         for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
00720                 gma_read16(hw, port, i);
00721         gma_write16(hw, port, GM_PHY_ADDR, reg);
00722 
00723         /* transmit control */
00724         gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
00725 
00726         /* receive control reg: unicast + multicast + no FCS  */
00727         gma_write16(hw, port, GM_RX_CTRL,
00728                     GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
00729 
00730         /* transmit flow control */
00731         gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
00732 
00733         /* transmit parameter */
00734         gma_write16(hw, port, GM_TX_PARAM,
00735                     TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
00736                     TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
00737                     TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
00738                     TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
00739 
00740         /* serial mode register */
00741         reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
00742                 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
00743 
00744         gma_write16(hw, port, GM_SERIAL_MODE, reg);
00745 
00746         /* virtual address for data */
00747         gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
00748 
00749         /* physical address: used for pause frames */
00750         gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
00751 
00752         /* ignore counter overflows */
00753         gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
00754         gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
00755         gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
00756 
00757         /* Configure Rx MAC FIFO */
00758         sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
00759         rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
00760         if (hw->chip_id == CHIP_ID_YUKON_EX ||
00761             hw->chip_id == CHIP_ID_YUKON_FE_P)
00762                 rx_reg |= GMF_RX_OVER_ON;
00763 
00764         sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
00765 
00766         if (hw->chip_id == CHIP_ID_YUKON_XL) {
00767                 /* Hardware errata - clear flush mask */
00768                 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
00769         } else {
00770                 /* Flush Rx MAC FIFO on any flow control or error */
00771                 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
00772         }
00773 
00774         /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug  */
00775         reg = RX_GMF_FL_THR_DEF + 1;
00776         /* Another magic mystery workaround from sk98lin */
00777         if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
00778             hw->chip_rev == CHIP_REV_YU_FE2_A0)
00779                 reg = 0x178;
00780         sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
00781 
00782         /* Configure Tx MAC FIFO */
00783         sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
00784         sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
00785 
00786         /* On chips without ram buffer, pause is controlled by MAC level */
00787         if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
00788                 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
00789                 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
00790 
00791                 sky2_set_tx_stfwd(hw, port);
00792         }
00793 
00794         if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
00795             hw->chip_rev == CHIP_REV_YU_FE2_A0) {
00796                 /* disable dynamic watermark */
00797                 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
00798                 reg &= ~TX_DYN_WM_ENA;
00799                 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
00800         }
00801 }
00802 
00803 /* Assign Ram Buffer allocation to queue */
00804 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
00805 {
00806         u32 end;
00807 
00808         /* convert from K bytes to qwords used for hw register */
00809         start *= 1024/8;
00810         space *= 1024/8;
00811         end = start + space - 1;
00812 
00813         sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
00814         sky2_write32(hw, RB_ADDR(q, RB_START), start);
00815         sky2_write32(hw, RB_ADDR(q, RB_END), end);
00816         sky2_write32(hw, RB_ADDR(q, RB_WP), start);
00817         sky2_write32(hw, RB_ADDR(q, RB_RP), start);
00818 
00819         if (q == Q_R1 || q == Q_R2) {
00820                 u32 tp = space - space/4;
00821 
00822                 /* On receive queue's set the thresholds
00823                  * give receiver priority when > 3/4 full
00824                  * send pause when down to 2K
00825                  */
00826                 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
00827                 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
00828 
00829                 tp = space - 2048/8;
00830                 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
00831                 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
00832         } else {
00833                 /* Enable store & forward on Tx queue's because
00834                  * Tx FIFO is only 1K on Yukon
00835                  */
00836                 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
00837         }
00838 
00839         sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
00840         sky2_read8(hw, RB_ADDR(q, RB_CTRL));
00841 }
00842 
00843 /* Setup Bus Memory Interface */
00844 static void sky2_qset(struct sky2_hw *hw, u16 q)
00845 {
00846         sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
00847         sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
00848         sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
00849         sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
00850 }
00851 
00852 /* Setup prefetch unit registers. This is the interface between
00853  * hardware and driver list elements
00854  */
00855 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
00856                                       u64 addr, u32 last)
00857 {
00858         sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
00859         sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
00860         sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
00861         sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
00862         sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
00863         sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
00864 
00865         sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
00866 }
00867 
00868 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
00869 {
00870         struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
00871 
00872         sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
00873         le->ctrl = 0;
00874         return le;
00875 }
00876 
00877 static void tx_init(struct sky2_port *sky2)
00878 {
00879         struct sky2_tx_le *le;
00880 
00881         sky2->tx_prod = sky2->tx_cons = 0;
00882 
00883         le = get_tx_le(sky2);
00884         le->addr = 0;
00885         le->opcode = OP_ADDR64 | HW_OWNER;
00886 }
00887 
00888 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
00889                                             struct sky2_tx_le *le)
00890 {
00891         return sky2->tx_ring + (le - sky2->tx_le);
00892 }
00893 
00894 /* Update chip's next pointer */
00895 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
00896 {
00897         /* Make sure write' to descriptors are complete before we tell hardware */
00898         wmb();
00899         sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
00900         DBGIO(PFX "queue %#x idx <- %d\n", q, idx);
00901 }
00902 
00903 
00904 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
00905 {
00906         struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
00907 
00908         sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
00909         le->ctrl = 0;
00910         return le;
00911 }
00912 
00913 /* Build description to hardware for one receive segment */
00914 static void sky2_rx_add(struct sky2_port *sky2,  u8 op,
00915                         u32 map, unsigned len)
00916 {
00917         struct sky2_rx_le *le;
00918 
00919         le = sky2_next_rx(sky2);
00920         le->addr = cpu_to_le32(map);
00921         le->length = cpu_to_le16(len);
00922         le->opcode = op | HW_OWNER;
00923 }
00924 
00925 /* Build description to hardware for one possibly fragmented skb */
00926 static void sky2_rx_submit(struct sky2_port *sky2,
00927                            const struct rx_ring_info *re)
00928 {
00929         sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
00930 }
00931 
00932 
00933 static void sky2_rx_map_iob(struct pci_device *pdev __unused,
00934                             struct rx_ring_info *re,
00935                             unsigned size __unused)
00936 {
00937         struct io_buffer *iob = re->iob;
00938         re->data_addr = virt_to_bus(iob->data);
00939 }
00940 
00941 /* Diable the checksum offloading.
00942  */
00943 static void rx_set_checksum(struct sky2_port *sky2)
00944 {
00945         struct sky2_rx_le *le = sky2_next_rx(sky2);
00946 
00947         le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
00948         le->ctrl = 0;
00949         le->opcode = OP_TCPSTART | HW_OWNER;
00950 
00951         sky2_write32(sky2->hw,
00952                      Q_ADDR(rxqaddr[sky2->port], Q_CSR),
00953                      BMU_DIS_RX_CHKSUM);
00954 }
00955 
00956 /*
00957  * The RX Stop command will not work for Yukon-2 if the BMU does not
00958  * reach the end of packet and since we can't make sure that we have
00959  * incoming data, we must reset the BMU while it is not doing a DMA
00960  * transfer. Since it is possible that the RX path is still active,
00961  * the RX RAM buffer will be stopped first, so any possible incoming
00962  * data will not trigger a DMA. After the RAM buffer is stopped, the
00963  * BMU is polled until any DMA in progress is ended and only then it
00964  * will be reset.
00965  */
00966 static void sky2_rx_stop(struct sky2_port *sky2)
00967 {
00968         struct sky2_hw *hw = sky2->hw;
00969         unsigned rxq = rxqaddr[sky2->port];
00970         int i;
00971 
00972         /* disable the RAM Buffer receive queue */
00973         sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
00974 
00975         for (i = 0; i < 0xffff; i++)
00976                 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
00977                     == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
00978                         goto stopped;
00979 
00980         DBG(PFX "%s: receiver stop failed\n", sky2->netdev->name);
00981 stopped:
00982         sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
00983 
00984         /* reset the Rx prefetch unit */
00985         sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
00986         wmb();
00987 }
00988 
00989 /* Clean out receive buffer area, assumes receiver hardware stopped */
00990 static void sky2_rx_clean(struct sky2_port *sky2)
00991 {
00992         unsigned i;
00993 
00994         memset(sky2->rx_le, 0, RX_LE_BYTES);
00995         for (i = 0; i < RX_PENDING; i++) {
00996                 struct rx_ring_info *re = sky2->rx_ring + i;
00997 
00998                 if (re->iob) {
00999                         free_iob(re->iob);
01000                         re->iob = NULL;
01001                 }
01002         }
01003 }
01004 
01005 /*
01006  * Allocate an iob for receiving.
01007  */
01008 static struct io_buffer *sky2_rx_alloc(struct sky2_port *sky2)
01009 {
01010         struct io_buffer *iob;
01011 
01012         iob = alloc_iob(sky2->rx_data_size + ETH_DATA_ALIGN);
01013         if (!iob)
01014                 return NULL;
01015 
01016         /*
01017          * Cards with a RAM buffer hang in the rx FIFO if the
01018          * receive buffer isn't aligned to (Linux module comments say
01019          * 64 bytes, Linux module code says 8 bytes). Since io_buffers
01020          * are always 2kb-aligned under iPXE, just leave it be
01021          * without ETH_DATA_ALIGN in those cases.
01022          *
01023          * XXX This causes unaligned access to the IP header,
01024          * which is undesirable, but it's less undesirable than the
01025          * card hanging.
01026          */
01027         if (!(sky2->hw->flags & SKY2_HW_RAM_BUFFER)) {
01028                 iob_reserve(iob, ETH_DATA_ALIGN);
01029         }
01030 
01031         return iob;
01032 }
01033 
01034 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
01035 {
01036         sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
01037 }
01038 
01039 /*
01040  * Allocate and setup receiver buffer pool.
01041  * Normal case this ends up creating one list element for skb
01042  * in the receive ring. One element is used for checksum
01043  * enable/disable, and one extra to avoid wrap.
01044  */
01045 static int sky2_rx_start(struct sky2_port *sky2)
01046 {
01047         struct sky2_hw *hw = sky2->hw;
01048         struct rx_ring_info *re;
01049         unsigned rxq = rxqaddr[sky2->port];
01050         unsigned i, size, thresh;
01051 
01052         sky2->rx_put = sky2->rx_next = 0;
01053         sky2_qset(hw, rxq);
01054 
01055         /* On PCI express lowering the watermark gives better performance */
01056         if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
01057                 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
01058 
01059         /* These chips have no ram buffer?
01060          * MAC Rx RAM Read is controlled by hardware */
01061         if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
01062             (hw->chip_rev == CHIP_REV_YU_EC_U_A1
01063              || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
01064                 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
01065 
01066         sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
01067 
01068         if (!(hw->flags & SKY2_HW_NEW_LE))
01069                 rx_set_checksum(sky2);
01070 
01071         /* Space needed for frame data + headers rounded up */
01072         size = (ETH_FRAME_LEN + 8) & ~7;
01073 
01074         /* Stopping point for hardware truncation */
01075         thresh = (size - 8) / sizeof(u32);
01076 
01077         sky2->rx_data_size = size;
01078 
01079         /* Fill Rx ring */
01080         for (i = 0; i < RX_PENDING; i++) {
01081                 re = sky2->rx_ring + i;
01082 
01083                 re->iob = sky2_rx_alloc(sky2);
01084                 if (!re->iob)
01085                         goto nomem;
01086 
01087                 sky2_rx_map_iob(hw->pdev, re, sky2->rx_data_size);
01088                 sky2_rx_submit(sky2, re);
01089         }
01090 
01091         /*
01092          * The receiver hangs if it receives frames larger than the
01093          * packet buffer. As a workaround, truncate oversize frames, but
01094          * the register is limited to 9 bits, so if you do frames > 2052
01095          * you better get the MTU right!
01096          */
01097         if (thresh > 0x1ff)
01098                 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
01099         else {
01100                 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
01101                 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
01102         }
01103 
01104         /* Tell chip about available buffers */
01105         sky2_rx_update(sky2, rxq);
01106         return 0;
01107 nomem:
01108         sky2_rx_clean(sky2);
01109         return -ENOMEM;
01110 }
01111 
01112 /* Free the le and ring buffers */
01113 static void sky2_free_rings(struct sky2_port *sky2)
01114 {
01115         free_dma(sky2->rx_le, RX_LE_BYTES);
01116         free(sky2->rx_ring);
01117 
01118         free_dma(sky2->tx_le, TX_RING_SIZE * sizeof(struct sky2_tx_le));
01119         free(sky2->tx_ring);
01120 
01121         sky2->tx_le = NULL;
01122         sky2->rx_le = NULL;
01123 
01124         sky2->rx_ring = NULL;
01125         sky2->tx_ring = NULL;
01126 }
01127 
01128 /* Bring up network interface. */
01129 static int sky2_up(struct net_device *dev)
01130 {
01131         struct sky2_port *sky2 = netdev_priv(dev);
01132         struct sky2_hw *hw = sky2->hw;
01133         unsigned port = sky2->port;
01134         u32 imask, ramsize;
01135         int err = -ENOMEM;
01136 
01137         netdev_link_down(dev);
01138 
01139         /* must be power of 2 */
01140         sky2->tx_le = malloc_dma(TX_RING_SIZE * sizeof(struct sky2_tx_le), TX_RING_ALIGN);
01141         sky2->tx_le_map = virt_to_bus(sky2->tx_le);
01142         if (!sky2->tx_le)
01143                 goto err_out;
01144         memset(sky2->tx_le, 0, TX_RING_SIZE * sizeof(struct sky2_tx_le));
01145 
01146         sky2->tx_ring = zalloc(TX_RING_SIZE * sizeof(struct tx_ring_info));
01147         if (!sky2->tx_ring)
01148                 goto err_out;
01149 
01150         tx_init(sky2);
01151 
01152         sky2->rx_le = malloc_dma(RX_LE_BYTES, RX_RING_ALIGN);
01153         sky2->rx_le_map = virt_to_bus(sky2->rx_le);
01154         if (!sky2->rx_le)
01155                 goto err_out;
01156         memset(sky2->rx_le, 0, RX_LE_BYTES);
01157 
01158         sky2->rx_ring = zalloc(RX_PENDING * sizeof(struct rx_ring_info));
01159         if (!sky2->rx_ring)
01160                 goto err_out;
01161 
01162         sky2_mac_init(hw, port);
01163 
01164         /* Register is number of 4K blocks on internal RAM buffer. */
01165         ramsize = sky2_read8(hw, B2_E_0) * 4;
01166         if (ramsize > 0) {
01167                 u32 rxspace;
01168 
01169                 hw->flags |= SKY2_HW_RAM_BUFFER;
01170                 DBG2(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
01171                 if (ramsize < 16)
01172                         rxspace = ramsize / 2;
01173                 else
01174                         rxspace = 8 + (2*(ramsize - 16))/3;
01175 
01176                 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
01177                 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
01178 
01179                 /* Make sure SyncQ is disabled */
01180                 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
01181                             RB_RST_SET);
01182         }
01183 
01184         sky2_qset(hw, txqaddr[port]);
01185 
01186         /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
01187         if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
01188                 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
01189 
01190         /* Set almost empty threshold */
01191         if (hw->chip_id == CHIP_ID_YUKON_EC_U
01192             && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
01193                 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
01194 
01195         sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
01196                            TX_RING_SIZE - 1);
01197 
01198         err = sky2_rx_start(sky2);
01199         if (err)
01200                 goto err_out;
01201 
01202         /* Enable interrupts from phy/mac for port */
01203         imask = sky2_read32(hw, B0_IMSK);
01204         imask |= portirq_msk[port];
01205         sky2_write32(hw, B0_IMSK, imask);
01206 
01207         DBGIO(PFX "%s: le bases: st %p [%x], rx %p [%x], tx %p [%x]\n",
01208               dev->name, hw->st_le, hw->st_dma, sky2->rx_le, sky2->rx_le_map,
01209               sky2->tx_le, sky2->tx_le_map);
01210 
01211         sky2_set_multicast(dev);
01212         return 0;
01213 
01214 err_out:
01215         sky2_free_rings(sky2);
01216         return err;
01217 }
01218 
01219 /* Modular subtraction in ring */
01220 static inline int tx_dist(unsigned tail, unsigned head)
01221 {
01222         return (head - tail) & (TX_RING_SIZE - 1);
01223 }
01224 
01225 /* Number of list elements available for next tx */
01226 static inline int tx_avail(const struct sky2_port *sky2)
01227 {
01228         return TX_PENDING - tx_dist(sky2->tx_cons, sky2->tx_prod);
01229 }
01230 
01231 
01232 /*
01233  * Put one packet in ring for transmit.
01234  * A single packet can generate multiple list elements, and
01235  * the number of ring elements will probably be less than the number
01236  * of list elements used.
01237  */
01238 static int sky2_xmit_frame(struct net_device *dev, struct io_buffer *iob)
01239 {
01240         struct sky2_port *sky2 = netdev_priv(dev);
01241         struct sky2_hw *hw = sky2->hw;
01242         struct sky2_tx_le *le = NULL;
01243         struct tx_ring_info *re;
01244         unsigned len;
01245         u32 mapping;
01246         u8 ctrl;
01247 
01248         if (tx_avail(sky2) < 1)
01249                 return -EBUSY;
01250 
01251         len = iob_len(iob);
01252         mapping = virt_to_bus(iob->data);
01253 
01254         DBGIO(PFX "%s: tx queued, slot %d, len %d\n", dev->name,
01255               sky2->tx_prod, len);
01256 
01257         ctrl = 0;
01258 
01259         le = get_tx_le(sky2);
01260         le->addr = cpu_to_le32((u32) mapping);
01261         le->length = cpu_to_le16(len);
01262         le->ctrl = ctrl;
01263         le->opcode = (OP_PACKET | HW_OWNER);
01264 
01265         re = tx_le_re(sky2, le);
01266         re->iob = iob;
01267 
01268         le->ctrl |= EOP;
01269 
01270         sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
01271 
01272         return 0;
01273 }
01274 
01275 /*
01276  * Free ring elements from starting at tx_cons until "done"
01277  *
01278  * NB: the hardware will tell us about partial completion of multi-part
01279  *     buffers so make sure not to free iob too early.
01280  */
01281 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
01282 {
01283         struct net_device *dev = sky2->netdev;
01284         unsigned idx;
01285 
01286         assert(done < TX_RING_SIZE);
01287 
01288         for (idx = sky2->tx_cons; idx != done;
01289              idx = RING_NEXT(idx, TX_RING_SIZE)) {
01290                 struct sky2_tx_le *le = sky2->tx_le + idx;
01291                 struct tx_ring_info *re = sky2->tx_ring + idx;
01292 
01293                 if (le->ctrl & EOP) {
01294                         DBGIO(PFX "%s: tx done %d\n", dev->name, idx);
01295                         netdev_tx_complete(dev, re->iob);
01296                 }
01297         }
01298 
01299         sky2->tx_cons = idx;
01300         mb();
01301 }
01302 
01303 /* Cleanup all untransmitted buffers, assume transmitter not running */
01304 static void sky2_tx_clean(struct net_device *dev)
01305 {
01306         struct sky2_port *sky2 = netdev_priv(dev);
01307 
01308         sky2_tx_complete(sky2, sky2->tx_prod);
01309 }
01310 
01311 /* Network shutdown */
01312 static void sky2_down(struct net_device *dev)
01313 {
01314         struct sky2_port *sky2 = netdev_priv(dev);
01315         struct sky2_hw *hw = sky2->hw;
01316         unsigned port = sky2->port;
01317         u16 ctrl;
01318         u32 imask;
01319 
01320         /* Never really got started! */
01321         if (!sky2->tx_le)
01322                 return;
01323 
01324         DBG2(PFX "%s: disabling interface\n", dev->name);
01325 
01326         /* Disable port IRQ */
01327         imask = sky2_read32(hw, B0_IMSK);
01328         imask &= ~portirq_msk[port];
01329         sky2_write32(hw, B0_IMSK, imask);
01330 
01331         sky2_gmac_reset(hw, port);
01332 
01333         /* Stop transmitter */
01334         sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
01335         sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
01336 
01337         sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
01338                      RB_RST_SET | RB_DIS_OP_MD);
01339 
01340         ctrl = gma_read16(hw, port, GM_GP_CTRL);
01341         ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
01342         gma_write16(hw, port, GM_GP_CTRL, ctrl);
01343 
01344         sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
01345 
01346         /* Workaround shared GMAC reset */
01347         if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
01348               && port == 0 && hw->dev[1]))
01349                 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
01350 
01351         /* Disable Force Sync bit and Enable Alloc bit */
01352         sky2_write8(hw, SK_REG(port, TXA_CTRL),
01353                     TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
01354 
01355         /* Stop Interval Timer and Limit Counter of Tx Arbiter */
01356         sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
01357         sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
01358 
01359         /* Reset the PCI FIFO of the async Tx queue */
01360         sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
01361                      BMU_RST_SET | BMU_FIFO_RST);
01362 
01363         /* Reset the Tx prefetch units */
01364         sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
01365                      PREF_UNIT_RST_SET);
01366 
01367         sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
01368 
01369         sky2_rx_stop(sky2);
01370 
01371         sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
01372         sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
01373 
01374         sky2_phy_power_down(hw, port);
01375 
01376         /* turn off LED's */
01377         sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
01378 
01379         sky2_tx_clean(dev);
01380         sky2_rx_clean(sky2);
01381 
01382         sky2_free_rings(sky2);
01383 
01384         return;
01385 }
01386 
01387 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
01388 {
01389         if (hw->flags & SKY2_HW_FIBRE_PHY)
01390                 return SPEED_1000;
01391 
01392         if (!(hw->flags & SKY2_HW_GIGABIT)) {
01393                 if (aux & PHY_M_PS_SPEED_100)
01394                         return SPEED_100;
01395                 else
01396                         return SPEED_10;
01397         }
01398 
01399         switch (aux & PHY_M_PS_SPEED_MSK) {
01400         case PHY_M_PS_SPEED_1000:
01401                 return SPEED_1000;
01402         case PHY_M_PS_SPEED_100:
01403                 return SPEED_100;
01404         default:
01405                 return SPEED_10;
01406         }
01407 }
01408 
01409 static void sky2_link_up(struct sky2_port *sky2)
01410 {
01411         struct sky2_hw *hw = sky2->hw;
01412         unsigned port = sky2->port;
01413         u16 reg;
01414         static const char *fc_name[] = {
01415                 [FC_NONE]       = "none",
01416                 [FC_TX]         = "tx",
01417                 [FC_RX]         = "rx",
01418                 [FC_BOTH]       = "both",
01419         };
01420 
01421         /* enable Rx/Tx */
01422         reg = gma_read16(hw, port, GM_GP_CTRL);
01423         reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
01424         gma_write16(hw, port, GM_GP_CTRL, reg);
01425 
01426         gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
01427 
01428         netdev_link_up(sky2->netdev);
01429 
01430         /* Turn on link LED */
01431         sky2_write8(hw, SK_REG(port, LNK_LED_REG),
01432                     LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
01433 
01434         DBG(PFX "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
01435             sky2->netdev->name, sky2->speed,
01436             sky2->duplex == DUPLEX_FULL ? "full" : "half",
01437             fc_name[sky2->flow_status]);
01438 }
01439 
01440 static void sky2_link_down(struct sky2_port *sky2)
01441 {
01442         struct sky2_hw *hw = sky2->hw;
01443         unsigned port = sky2->port;
01444         u16 reg;
01445 
01446         gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
01447 
01448         reg = gma_read16(hw, port, GM_GP_CTRL);
01449         reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
01450         gma_write16(hw, port, GM_GP_CTRL, reg);
01451 
01452         netdev_link_down(sky2->netdev);
01453 
01454         /* Turn on link LED */
01455         sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
01456 
01457         DBG(PFX "%s: Link is down.\n", sky2->netdev->name);
01458 
01459         sky2_phy_init(hw, port);
01460 }
01461 
01462 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
01463 {
01464         struct sky2_hw *hw = sky2->hw;
01465         unsigned port = sky2->port;
01466         u16 advert, lpa;
01467 
01468         advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
01469         lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
01470         if (lpa & PHY_M_AN_RF) {
01471                 DBG(PFX "%s: remote fault\n", sky2->netdev->name);
01472                 return -1;
01473         }
01474 
01475         if (!(aux & PHY_M_PS_SPDUP_RES)) {
01476                 DBG(PFX "%s: speed/duplex mismatch\n", sky2->netdev->name);
01477                 return -1;
01478         }
01479 
01480         sky2->speed = sky2_phy_speed(hw, aux);
01481         sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
01482 
01483         /* Since the pause result bits seem to in different positions on
01484          * different chips. look at registers.
01485          */
01486 
01487         sky2->flow_status = FC_NONE;
01488         if (advert & ADVERTISE_PAUSE_CAP) {
01489                 if (lpa & LPA_PAUSE_CAP)
01490                         sky2->flow_status = FC_BOTH;
01491                 else if (advert & ADVERTISE_PAUSE_ASYM)
01492                         sky2->flow_status = FC_RX;
01493         } else if (advert & ADVERTISE_PAUSE_ASYM) {
01494                 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
01495                         sky2->flow_status = FC_TX;
01496         }
01497 
01498         if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
01499             && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
01500                 sky2->flow_status = FC_NONE;
01501 
01502         if (sky2->flow_status & FC_TX)
01503                 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
01504         else
01505                 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
01506 
01507         return 0;
01508 }
01509 
01510 /* Interrupt from PHY */
01511 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
01512 {
01513         struct net_device *dev = hw->dev[port];
01514         struct sky2_port *sky2 = netdev_priv(dev);
01515         u16 istatus, phystat;
01516 
01517         istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
01518         phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
01519 
01520         DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
01521               sky2->netdev->name, istatus, phystat);
01522 
01523         if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
01524                 if (sky2_autoneg_done(sky2, phystat) == 0)
01525                         sky2_link_up(sky2);
01526                 return;
01527         }
01528 
01529         if (istatus & PHY_M_IS_LSP_CHANGE)
01530                 sky2->speed = sky2_phy_speed(hw, phystat);
01531 
01532         if (istatus & PHY_M_IS_DUP_CHANGE)
01533                 sky2->duplex =
01534                     (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
01535 
01536         if (istatus & PHY_M_IS_LST_CHANGE) {
01537                 if (phystat & PHY_M_PS_LINK_UP)
01538                         sky2_link_up(sky2);
01539                 else
01540                         sky2_link_down(sky2);
01541         }
01542 }
01543 
01544 /* Normal packet - take iob from ring element and put in a new one  */
01545 static struct io_buffer *receive_new(struct sky2_port *sky2,
01546                                      struct rx_ring_info *re,
01547                                      unsigned int length)
01548 {
01549         struct io_buffer *iob, *niob;
01550         unsigned hdr_space = sky2->rx_data_size;
01551 
01552         /* Don't be tricky about reusing pages (yet) */
01553         niob = sky2_rx_alloc(sky2);
01554         if (!niob)
01555                 return NULL;
01556 
01557         iob = re->iob;
01558 
01559         re->iob = niob;
01560         sky2_rx_map_iob(sky2->hw->pdev, re, hdr_space);
01561 
01562         iob_put(iob, length);
01563         return iob;
01564 }
01565 
01566 /*
01567  * Receive one packet.
01568  * For larger packets, get new buffer.
01569  */
01570 static struct io_buffer *sky2_receive(struct net_device *dev,
01571                                       u16 length, u32 status)
01572 {
01573         struct sky2_port *sky2 = netdev_priv(dev);
01574         struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
01575         struct io_buffer *iob = NULL;
01576         u16 count = (status & GMR_FS_LEN) >> 16;
01577 
01578         DBGIO(PFX "%s: rx slot %d status 0x%x len %d\n",
01579               dev->name, sky2->rx_next, status, length);
01580 
01581         sky2->rx_next = (sky2->rx_next + 1) % RX_PENDING;
01582 
01583         /* This chip has hardware problems that generates bogus status.
01584          * So do only marginal checking and expect higher level protocols
01585          * to handle crap frames.
01586          */
01587         if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
01588             sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
01589             length == count)
01590                 goto okay;
01591 
01592         if (status & GMR_FS_ANY_ERR)
01593                 goto error;
01594 
01595         if (!(status & GMR_FS_RX_OK))
01596                 goto resubmit;
01597 
01598         /* if length reported by DMA does not match PHY, packet was truncated */
01599         if (length != count)
01600                 goto len_error;
01601 
01602 okay:
01603         iob = receive_new(sky2, re, length);
01604 resubmit:
01605         sky2_rx_submit(sky2, re);
01606 
01607         return iob;
01608 
01609 len_error:
01610         /* Truncation of overlength packets
01611            causes PHY length to not match MAC length */
01612         DBG2(PFX "%s: rx length error: status %#x length %d\n",
01613              dev->name, status, length);
01614 
01615         /* Pass NULL as iob because we want to keep our iob in the
01616            ring for the next packet. */
01617         netdev_rx_err(dev, NULL, -EINVAL);
01618         goto resubmit;
01619 
01620 error:
01621         if (status & GMR_FS_RX_FF_OV) {
01622                 DBG2(PFX "%s: FIFO overflow error\n", dev->name);
01623                 netdev_rx_err(dev, NULL, -EBUSY);
01624                 goto resubmit;
01625         }
01626 
01627         DBG2(PFX "%s: rx error, status 0x%x length %d\n",
01628              dev->name, status, length);
01629         netdev_rx_err(dev, NULL, -EIO);
01630 
01631         goto resubmit;
01632 }
01633 
01634 /* Transmit complete */
01635 static inline void sky2_tx_done(struct net_device *dev, u16 last)
01636 {
01637         struct sky2_port *sky2 = netdev_priv(dev);
01638 
01639         sky2_tx_complete(sky2, last);
01640 }
01641 
01642 /* Process status response ring */
01643 static void sky2_status_intr(struct sky2_hw *hw, u16 idx)
01644 {
01645         unsigned rx[2] = { 0, 0 };
01646 
01647         rmb();
01648         do {
01649                 struct sky2_status_le *le  = hw->st_le + hw->st_idx;
01650                 unsigned port;
01651                 struct net_device *dev;
01652                 struct io_buffer *iob;
01653                 u32 status;
01654                 u16 length;
01655                 u8 opcode = le->opcode;
01656 
01657                 if (!(opcode & HW_OWNER))
01658                         break;
01659 
01660                 port = le->css & CSS_LINK_BIT;
01661                 dev = hw->dev[port];
01662                 length = le16_to_cpu(le->length);
01663                 status = le32_to_cpu(le->status);
01664 
01665                 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
01666 
01667                 le->opcode = 0;
01668                 switch (opcode & ~HW_OWNER) {
01669                 case OP_RXSTAT:
01670                         ++rx[port];
01671                         iob = sky2_receive(dev, length, status);
01672                         if (!iob) {
01673                                 netdev_rx_err(dev, NULL, -ENOMEM);
01674                                 break;
01675                         }
01676 
01677                         netdev_rx(dev, iob);
01678                         break;
01679 
01680                 case OP_RXCHKS:
01681                         DBG2(PFX "status OP_RXCHKS but checksum offloading disabled\n");
01682                         break;
01683 
01684                 case OP_TXINDEXLE:
01685                         /* TX index reports status for both ports */
01686                         assert(TX_RING_SIZE <= 0x1000);
01687                         sky2_tx_done(hw->dev[0], status & 0xfff);
01688                         if (hw->dev[1])
01689                                 sky2_tx_done(hw->dev[1],
01690                                      ((status >> 24) & 0xff)
01691                                              | (u16)(length & 0xf) << 8);
01692                         break;
01693 
01694                 default:
01695                         DBG(PFX "unknown status opcode 0x%x\n", opcode);
01696                 }
01697         } while (hw->st_idx != idx);
01698 
01699         /* Fully processed status ring so clear irq */
01700         sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
01701 
01702         if (rx[0])
01703                 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
01704 
01705         if (rx[1])
01706                 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
01707 }
01708 
01709 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
01710 {
01711         struct net_device *dev = hw->dev[port];
01712 
01713         DBGIO(PFX "%s: hw error interrupt status 0x%x\n", dev->name, status);
01714 
01715         if (status & Y2_IS_PAR_RD1) {
01716                 DBG(PFX "%s: ram data read parity error\n", dev->name);
01717                 /* Clear IRQ */
01718                 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
01719         }
01720 
01721         if (status & Y2_IS_PAR_WR1) {
01722                 DBG(PFX "%s: ram data write parity error\n", dev->name);
01723                 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
01724         }
01725 
01726         if (status & Y2_IS_PAR_MAC1) {
01727                 DBG(PFX "%s: MAC parity error\n", dev->name);
01728                 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
01729         }
01730 
01731         if (status & Y2_IS_PAR_RX1) {
01732                 DBG(PFX "%s: RX parity error\n", dev->name);
01733                 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
01734         }
01735 
01736         if (status & Y2_IS_TCP_TXA1) {
01737                 DBG(PFX "%s: TCP segmentation error\n", dev->name);
01738                 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
01739         }
01740 }
01741 
01742 static void sky2_hw_intr(struct sky2_hw *hw)
01743 {
01744         u32 status = sky2_read32(hw, B0_HWE_ISRC);
01745         u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
01746 
01747         status &= hwmsk;
01748 
01749         if (status & Y2_IS_TIST_OV)
01750                 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
01751 
01752         if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
01753                 u16 pci_err;
01754 
01755                 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
01756                 pci_err = sky2_pci_read16(hw, PCI_STATUS);
01757                 DBG(PFX "PCI hardware error (0x%x)\n", pci_err);
01758 
01759                 sky2_pci_write16(hw, PCI_STATUS,
01760                                  pci_err | PCI_STATUS_ERROR_BITS);
01761                 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
01762         }
01763 
01764         if (status & Y2_IS_PCI_EXP) {
01765                 /* PCI-Express uncorrectable Error occurred */
01766                 u32 err;
01767 
01768                 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
01769                 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
01770                 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
01771                              0xfffffffful);
01772                 DBG(PFX "PCI-Express error (0x%x)\n", err);
01773 
01774                 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
01775                 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
01776         }
01777 
01778         if (status & Y2_HWE_L1_MASK)
01779                 sky2_hw_error(hw, 0, status);
01780         status >>= 8;
01781         if (status & Y2_HWE_L1_MASK)
01782                 sky2_hw_error(hw, 1, status);
01783 }
01784 
01785 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
01786 {
01787         struct net_device *dev = hw->dev[port];
01788         u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
01789 
01790         DBGIO(PFX "%s: mac interrupt status 0x%x\n", dev->name, status);
01791 
01792         if (status & GM_IS_RX_CO_OV)
01793                 gma_read16(hw, port, GM_RX_IRQ_SRC);
01794 
01795         if (status & GM_IS_TX_CO_OV)
01796                 gma_read16(hw, port, GM_TX_IRQ_SRC);
01797 
01798         if (status & GM_IS_RX_FF_OR) {
01799                 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
01800         }
01801 
01802         if (status & GM_IS_TX_FF_UR) {
01803                 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
01804         }
01805 }
01806 
01807 /* This should never happen it is a bug. */
01808 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
01809                           u16 q, unsigned ring_size __unused)
01810 {
01811         struct net_device *dev = hw->dev[port];
01812         struct sky2_port *sky2 = netdev_priv(dev);
01813         int idx;
01814         const u64 *le = (q == Q_R1 || q == Q_R2)
01815                 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
01816 
01817         idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
01818         DBG(PFX "%s: descriptor error q=%#x get=%d [%llx] last=%d put=%d should be %d\n",
01819             dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
01820             (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_LAST_IDX)),
01821             (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)),
01822             le == (u64 *)sky2->rx_le? sky2->rx_put : sky2->tx_prod);
01823 
01824         sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
01825 }
01826 
01827 /* Hardware/software error handling */
01828 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
01829 {
01830         DBG(PFX "error interrupt status=%#x\n", status);
01831 
01832         if (status & Y2_IS_HW_ERR)
01833                 sky2_hw_intr(hw);
01834 
01835         if (status & Y2_IS_IRQ_MAC1)
01836                 sky2_mac_intr(hw, 0);
01837 
01838         if (status & Y2_IS_IRQ_MAC2)
01839                 sky2_mac_intr(hw, 1);
01840 
01841         if (status & Y2_IS_CHK_RX1)
01842                 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
01843 
01844         if (status & Y2_IS_CHK_RX2)
01845                 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
01846 
01847         if (status & Y2_IS_CHK_TXA1)
01848                 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
01849 
01850         if (status & Y2_IS_CHK_TXA2)
01851                 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
01852 }
01853 
01854 static void sky2_poll(struct net_device *dev)
01855 {
01856         struct sky2_port *sky2 = netdev_priv(dev);
01857         struct sky2_hw *hw = sky2->hw;
01858         u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
01859         u16 idx;
01860 
01861         if (status & Y2_IS_ERROR)
01862                 sky2_err_intr(hw, status);
01863 
01864         if (status & Y2_IS_IRQ_PHY1)
01865                 sky2_phy_intr(hw, 0);
01866 
01867         if (status & Y2_IS_IRQ_PHY2)
01868                 sky2_phy_intr(hw, 1);
01869 
01870         while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
01871                 sky2_status_intr(hw, idx);
01872         }
01873 
01874         /* Bug/Errata workaround?
01875          * Need to kick the TX irq moderation timer.
01876          */
01877         if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
01878                 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
01879                 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
01880         }
01881         sky2_read32(hw, B0_Y2_SP_LISR);
01882 }
01883 
01884 /* Chip internal frequency for clock calculations */
01885 static u32 sky2_mhz(const struct sky2_hw *hw)
01886 {
01887         switch (hw->chip_id) {
01888         case CHIP_ID_YUKON_EC:
01889         case CHIP_ID_YUKON_EC_U:
01890         case CHIP_ID_YUKON_EX:
01891         case CHIP_ID_YUKON_SUPR:
01892         case CHIP_ID_YUKON_UL_2:
01893                 return 125;
01894 
01895         case CHIP_ID_YUKON_FE:
01896                 return 100;
01897 
01898         case CHIP_ID_YUKON_FE_P:
01899                 return 50;
01900 
01901         case CHIP_ID_YUKON_XL:
01902                 return 156;
01903 
01904         default:
01905                 DBG(PFX "unknown chip ID!\n");
01906                 return 100;     /* bogus */
01907         }
01908 }
01909 
01910 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
01911 {
01912         return sky2_mhz(hw) * us;
01913 }
01914 
01915 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
01916 {
01917         return clk / sky2_mhz(hw);
01918 }
01919 
01920 static int sky2_init(struct sky2_hw *hw)
01921 {
01922         u8 t8;
01923 
01924         /* Enable all clocks and check for bad PCI access */
01925         sky2_pci_write32(hw, PCI_DEV_REG3, 0);
01926 
01927         sky2_write8(hw, B0_CTST, CS_RST_CLR);
01928 
01929         hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
01930         hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
01931 
01932         switch(hw->chip_id) {
01933         case CHIP_ID_YUKON_XL:
01934                 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
01935                 break;
01936 
01937         case CHIP_ID_YUKON_EC_U:
01938                 hw->flags = SKY2_HW_GIGABIT
01939                         | SKY2_HW_NEWER_PHY
01940                         | SKY2_HW_ADV_POWER_CTL;
01941                 break;
01942 
01943         case CHIP_ID_YUKON_EX:
01944                 hw->flags = SKY2_HW_GIGABIT
01945                         | SKY2_HW_NEWER_PHY
01946                         | SKY2_HW_NEW_LE
01947                         | SKY2_HW_ADV_POWER_CTL;
01948                 break;
01949 
01950         case CHIP_ID_YUKON_EC:
01951                 /* This rev is really old, and requires untested workarounds */
01952                 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
01953                         DBG(PFX "unsupported revision Yukon-EC rev A1\n");
01954                         return -EOPNOTSUPP;
01955                 }
01956                 hw->flags = SKY2_HW_GIGABIT;
01957                 break;
01958 
01959         case CHIP_ID_YUKON_FE:
01960                 break;
01961 
01962         case CHIP_ID_YUKON_FE_P:
01963                 hw->flags = SKY2_HW_NEWER_PHY
01964                         | SKY2_HW_NEW_LE
01965                         | SKY2_HW_AUTO_TX_SUM
01966                         | SKY2_HW_ADV_POWER_CTL;
01967                 break;
01968 
01969         case CHIP_ID_YUKON_SUPR:
01970                 hw->flags = SKY2_HW_GIGABIT
01971                         | SKY2_HW_NEWER_PHY
01972                         | SKY2_HW_NEW_LE
01973                         | SKY2_HW_AUTO_TX_SUM
01974                         | SKY2_HW_ADV_POWER_CTL;
01975                 break;
01976 
01977         case CHIP_ID_YUKON_UL_2:
01978                 hw->flags = SKY2_HW_GIGABIT
01979                         | SKY2_HW_ADV_POWER_CTL;
01980                 break;
01981 
01982         default:
01983                 DBG(PFX "unsupported chip type 0x%x\n", hw->chip_id);
01984                 return -EOPNOTSUPP;
01985         }
01986 
01987         hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
01988         if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
01989                 hw->flags |= SKY2_HW_FIBRE_PHY;
01990 
01991         hw->ports = 1;
01992         t8 = sky2_read8(hw, B2_Y2_HW_RES);
01993         if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
01994                 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
01995                         ++hw->ports;
01996         }
01997 
01998         return 0;
01999 }
02000 
02001 static void sky2_reset(struct sky2_hw *hw)
02002 {
02003         u16 status;
02004         int i, cap;
02005         u32 hwe_mask = Y2_HWE_ALL_MASK;
02006 
02007         /* disable ASF */
02008         if (hw->chip_id == CHIP_ID_YUKON_EX) {
02009                 status = sky2_read16(hw, HCU_CCSR);
02010                 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
02011                             HCU_CCSR_UC_STATE_MSK);
02012                 sky2_write16(hw, HCU_CCSR, status);
02013         } else
02014                 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
02015         sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
02016 
02017         /* do a SW reset */
02018         sky2_write8(hw, B0_CTST, CS_RST_SET);
02019         sky2_write8(hw, B0_CTST, CS_RST_CLR);
02020 
02021         /* allow writes to PCI config */
02022         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
02023 
02024         /* clear PCI errors, if any */
02025         status = sky2_pci_read16(hw, PCI_STATUS);
02026         status |= PCI_STATUS_ERROR_BITS;
02027         sky2_pci_write16(hw, PCI_STATUS, status);
02028 
02029         sky2_write8(hw, B0_CTST, CS_MRST_CLR);
02030 
02031         cap = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
02032         if (cap) {
02033                 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
02034                              0xfffffffful);
02035 
02036                 /* If an error bit is stuck on ignore it */
02037                 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
02038                         DBG(PFX "ignoring stuck error report bit\n");
02039                 else
02040                         hwe_mask |= Y2_IS_PCI_EXP;
02041         }
02042 
02043         sky2_power_on(hw);
02044         sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
02045 
02046         for (i = 0; i < hw->ports; i++) {
02047                 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
02048                 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
02049 
02050                 if (hw->chip_id == CHIP_ID_YUKON_EX ||
02051                     hw->chip_id == CHIP_ID_YUKON_SUPR)
02052                         sky2_write16(hw, SK_REG(i, GMAC_CTRL),
02053                                      GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
02054                                      | GMC_BYP_RETR_ON);
02055         }
02056 
02057         /* Clear I2C IRQ noise */
02058         sky2_write32(hw, B2_I2C_IRQ, 1);
02059 
02060         /* turn off hardware timer (unused) */
02061         sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
02062         sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
02063 
02064         sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
02065 
02066         /* Turn off descriptor polling */
02067         sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
02068 
02069         /* Turn off receive timestamp */
02070         sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
02071         sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
02072 
02073         /* enable the Tx Arbiters */
02074         for (i = 0; i < hw->ports; i++)
02075                 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
02076 
02077         /* Initialize ram interface */
02078         for (i = 0; i < hw->ports; i++) {
02079                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
02080 
02081                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
02082                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
02083                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
02084                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
02085                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
02086                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
02087                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
02088                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
02089                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
02090                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
02091                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
02092                 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
02093         }
02094 
02095         sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
02096 
02097         for (i = 0; i < hw->ports; i++)
02098                 sky2_gmac_reset(hw, i);
02099 
02100         memset(hw->st_le, 0, STATUS_LE_BYTES);
02101         hw->st_idx = 0;
02102 
02103         sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
02104         sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
02105 
02106         sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
02107         sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
02108 
02109         /* Set the list last index */
02110         sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
02111 
02112         sky2_write16(hw, STAT_TX_IDX_TH, 10);
02113         sky2_write8(hw, STAT_FIFO_WM, 16);
02114 
02115         /* set Status-FIFO ISR watermark */
02116         if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
02117                 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
02118         else
02119                 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
02120 
02121         sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
02122         sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
02123         sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
02124 
02125         /* enable status unit */
02126         sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
02127 
02128         sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
02129         sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
02130         sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
02131 }
02132 
02133 static u32 sky2_supported_modes(const struct sky2_hw *hw)
02134 {
02135         if (sky2_is_copper(hw)) {
02136                 u32 modes = SUPPORTED_10baseT_Half
02137                         | SUPPORTED_10baseT_Full
02138                         | SUPPORTED_100baseT_Half
02139                         | SUPPORTED_100baseT_Full
02140                         | SUPPORTED_Autoneg | SUPPORTED_TP;
02141 
02142                 if (hw->flags & SKY2_HW_GIGABIT)
02143                         modes |= SUPPORTED_1000baseT_Half
02144                                 | SUPPORTED_1000baseT_Full;
02145                 return modes;
02146         } else
02147                 return  SUPPORTED_1000baseT_Half
02148                         | SUPPORTED_1000baseT_Full
02149                         | SUPPORTED_Autoneg
02150                         | SUPPORTED_FIBRE;
02151 }
02152 
02153 static void sky2_set_multicast(struct net_device *dev)
02154 {
02155         struct sky2_port *sky2 = netdev_priv(dev);
02156         struct sky2_hw *hw = sky2->hw;
02157         unsigned port = sky2->port;
02158         u16 reg;
02159         u8 filter[8];
02160 
02161         reg = gma_read16(hw, port, GM_RX_CTRL);
02162         reg |= GM_RXCR_UCF_ENA;
02163 
02164         memset(filter, 0xff, sizeof(filter));
02165 
02166         gma_write16(hw, port, GM_MC_ADDR_H1,
02167                     (u16) filter[0] | ((u16) filter[1] << 8));
02168         gma_write16(hw, port, GM_MC_ADDR_H2,
02169                     (u16) filter[2] | ((u16) filter[3] << 8));
02170         gma_write16(hw, port, GM_MC_ADDR_H3,
02171                     (u16) filter[4] | ((u16) filter[5] << 8));
02172         gma_write16(hw, port, GM_MC_ADDR_H4,
02173                     (u16) filter[6] | ((u16) filter[7] << 8));
02174 
02175         gma_write16(hw, port, GM_RX_CTRL, reg);
02176 }
02177 
02178 /* Initialize network device */
02179 static struct net_device *sky2_init_netdev(struct sky2_hw *hw,
02180                                                      unsigned port)
02181 {
02182         struct sky2_port *sky2;
02183         struct net_device *dev = alloc_etherdev(sizeof(*sky2));
02184 
02185         if (!dev) {
02186                 DBG(PFX "etherdev alloc failed\n");
02187                 return NULL;
02188         }
02189 
02190         dev->dev = &hw->pdev->dev;
02191 
02192         sky2 = netdev_priv(dev);
02193         sky2->netdev = dev;
02194         sky2->hw = hw;
02195 
02196         /* Auto speed and flow control */
02197         sky2->autoneg = AUTONEG_ENABLE;
02198         sky2->flow_mode = FC_BOTH;
02199 
02200         sky2->duplex = -1;
02201         sky2->speed = -1;
02202         sky2->advertising = sky2_supported_modes(hw);
02203 
02204         hw->dev[port] = dev;
02205 
02206         sky2->port = port;
02207 
02208         /* read the mac address */
02209         memcpy(dev->hw_addr, (void *)(hw->regs + B2_MAC_1 + port * 8), ETH_ALEN);
02210 
02211         return dev;
02212 }
02213 
02214 static void sky2_show_addr(struct net_device *dev)
02215 {
02216         DBG2(PFX "%s: addr %s\n", dev->name, netdev_addr(dev));
02217 }
02218 
02219 #if DBGLVL_MAX
02220 /* This driver supports yukon2 chipset only */
02221 static const char *sky2_name(u8 chipid, char *buf, int sz)
02222 {
02223         const char *name[] = {
02224                 "XL",           /* 0xb3 */
02225                 "EC Ultra",     /* 0xb4 */
02226                 "Extreme",      /* 0xb5 */
02227                 "EC",           /* 0xb6 */
02228                 "FE",           /* 0xb7 */
02229                 "FE+",          /* 0xb8 */
02230                 "Supreme",      /* 0xb9 */
02231                 "UL 2",         /* 0xba */
02232         };
02233 
02234         if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_UL_2)
02235                 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
02236         else
02237                 snprintf(buf, sz, "(chip %#x)", chipid);
02238         return buf;
02239 }
02240 #endif
02241 
02242 static void sky2_net_irq(struct net_device *dev, int enable)
02243 {
02244         struct sky2_port *sky2 = netdev_priv(dev);
02245         struct sky2_hw *hw = sky2->hw;
02246 
02247         u32 imask = sky2_read32(hw, B0_IMSK);
02248         if (enable)
02249                 imask |= portirq_msk[sky2->port];
02250         else
02251                 imask &= ~portirq_msk[sky2->port];
02252         sky2_write32(hw, B0_IMSK, imask);
02253 }
02254 
02255 static struct net_device_operations sky2_operations = {
02256         .open     = sky2_up,
02257         .close    = sky2_down,
02258         .transmit = sky2_xmit_frame,
02259         .poll     = sky2_poll,
02260         .irq      = sky2_net_irq
02261 };
02262 
02263 static int sky2_probe(struct pci_device *pdev)
02264 {
02265         struct net_device *dev;
02266         struct sky2_hw *hw;
02267         int err;
02268         char buf1[16] __unused; /* only for debugging */
02269 
02270         adjust_pci_device(pdev);
02271 
02272         err = -ENOMEM;
02273         hw = zalloc(sizeof(*hw));
02274         if (!hw) {
02275                 DBG(PFX "cannot allocate hardware struct\n");
02276                 goto err_out;
02277         }
02278 
02279         hw->pdev = pdev;
02280 
02281         hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0), 0x4000);
02282         if (!hw->regs) {
02283                 DBG(PFX "cannot map device registers\n");
02284                 goto err_out_free_hw;
02285         }
02286 
02287         /* ring for status responses */
02288         hw->st_le = malloc_dma(STATUS_LE_BYTES, STATUS_RING_ALIGN);
02289         if (!hw->st_le)
02290                 goto err_out_iounmap;
02291         hw->st_dma = virt_to_bus(hw->st_le);
02292         memset(hw->st_le, 0, STATUS_LE_BYTES);
02293 
02294         err = sky2_init(hw);
02295         if (err)
02296                 goto err_out_iounmap;
02297 
02298 #if DBGLVL_MAX
02299         DBG2(PFX "Yukon-2 %s chip revision %d\n",
02300              sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
02301 #endif
02302 
02303         sky2_reset(hw);
02304 
02305         dev = sky2_init_netdev(hw, 0);
02306         if (!dev) {
02307                 err = -ENOMEM;
02308                 goto err_out_free_pci;
02309         }
02310 
02311         netdev_init(dev, &sky2_operations);
02312 
02313         err = register_netdev(dev);
02314         if (err) {
02315                 DBG(PFX "cannot register net device\n");
02316                 goto err_out_free_netdev;
02317         }
02318 
02319         sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
02320 
02321         sky2_show_addr(dev);
02322 
02323         if (hw->ports > 1) {
02324                 struct net_device *dev1;
02325 
02326                 dev1 = sky2_init_netdev(hw, 1);
02327                 if (!dev1)
02328                         DBG(PFX "allocation for second device failed\n");
02329                 else if ((err = register_netdev(dev1))) {
02330                         DBG(PFX "register of second port failed (%d)\n", err);
02331                         hw->dev[1] = NULL;
02332                         netdev_nullify(dev1);
02333                         netdev_put(dev1);
02334                 } else
02335                         sky2_show_addr(dev1);
02336         }
02337 
02338         pci_set_drvdata(pdev, hw);
02339 
02340         return 0;
02341 
02342 err_out_free_netdev:
02343         netdev_nullify(dev);
02344         netdev_put(dev);
02345 err_out_free_pci:
02346         sky2_write8(hw, B0_CTST, CS_RST_SET);
02347         free_dma(hw->st_le, STATUS_LE_BYTES);
02348 err_out_iounmap:
02349         iounmap((void *)hw->regs);
02350 err_out_free_hw:
02351         free(hw);
02352 err_out:
02353         pci_set_drvdata(pdev, NULL);
02354         return err;
02355 }
02356 
02357 static void sky2_remove(struct pci_device *pdev)
02358 {
02359         struct sky2_hw *hw = pci_get_drvdata(pdev);
02360         int i;
02361 
02362         if (!hw)
02363                 return;
02364 
02365         for (i = hw->ports-1; i >= 0; --i)
02366                 unregister_netdev(hw->dev[i]);
02367 
02368         sky2_write32(hw, B0_IMSK, 0);
02369 
02370         sky2_power_aux(hw);
02371 
02372         sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
02373         sky2_write8(hw, B0_CTST, CS_RST_SET);
02374         sky2_read8(hw, B0_CTST);
02375 
02376         free_dma(hw->st_le, STATUS_LE_BYTES);
02377 
02378         for (i = hw->ports-1; i >= 0; --i) {
02379                 netdev_nullify(hw->dev[i]);
02380                 netdev_put(hw->dev[i]);
02381         }
02382 
02383         iounmap((void *)hw->regs);
02384         free(hw);
02385 
02386         pci_set_drvdata(pdev, NULL);
02387 }
02388 
02389 struct pci_driver sky2_driver __pci_driver = {
02390         .ids      = sky2_id_table,
02391         .id_count = (sizeof (sky2_id_table) / sizeof (sky2_id_table[0])),
02392         .probe    = sky2_probe,
02393         .remove   = sky2_remove
02394 };