iPXE
Functions
ath5k_attach.c File Reference
#include <ipxe/pci.h>
#include <unistd.h>
#include <stdlib.h>
#include "ath5k.h"
#include "reg.h"
#include "base.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (MIT)
 
static int ath5k_hw_post (struct ath5k_hw *ah)
 ath5k_hw_post - Power On Self Test helper function More...
 
int ath5k_hw_attach (struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **hw)
 ath5k_hw_attach - Check if hw is supported and init the needed structs More...
 
void ath5k_hw_detach (struct ath5k_hw *ah)
 ath5k_hw_detach - Free the ath5k_hw struct More...
 

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( MIT  )

◆ ath5k_hw_post()

static int ath5k_hw_post ( struct ath5k_hw ah)
static

ath5k_hw_post - Power On Self Test helper function

@ah: The &struct ath5k_hw

Definition at line 40 of file ath5k_attach.c.

41 {
42 
43  static const u32 static_pattern[4] = {
44  0x55555555, 0xaaaaaaaa,
45  0x66666666, 0x99999999
46  };
47  static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
48  int i, c;
49  u16 cur_reg;
50  u32 var_pattern;
51  u32 init_val;
52  u32 cur_val;
53 
54  for (c = 0; c < 2; c++) {
55 
56  cur_reg = regs[c];
57 
58  /* Save previous value */
59  init_val = ath5k_hw_reg_read(ah, cur_reg);
60 
61  for (i = 0; i < 256; i++) {
62  var_pattern = i << 16 | i;
63  ath5k_hw_reg_write(ah, var_pattern, cur_reg);
64  cur_val = ath5k_hw_reg_read(ah, cur_reg);
65 
66  if (cur_val != var_pattern) {
67  DBG("ath5k: POST failed!\n");
68  return -EAGAIN;
69  }
70 
71  /* Found on ndiswrapper dumps */
72  var_pattern = 0x0039080f;
73  ath5k_hw_reg_write(ah, var_pattern, cur_reg);
74  }
75 
76  for (i = 0; i < 4; i++) {
77  var_pattern = static_pattern[i];
78  ath5k_hw_reg_write(ah, var_pattern, cur_reg);
79  cur_val = ath5k_hw_reg_read(ah, cur_reg);
80 
81  if (cur_val != var_pattern) {
82  DBG("ath5k: POST failed!\n");
83  return -EAGAIN;
84  }
85 
86  /* Found on ndiswrapper dumps */
87  var_pattern = 0x003b080f;
88  ath5k_hw_reg_write(ah, var_pattern, cur_reg);
89  }
90 
91  /* Restore previous value */
92  ath5k_hw_reg_write(ah, init_val, cur_reg);
93 
94  }
95 
96  return 0;
97 
98 }
uint16_t u16
Definition: stdint.h:21
static __always_inline void off_t int c
Definition: efi_uaccess.h:87
#define AR5K_STA_ID0
Definition: reg.h:1122
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define EAGAIN
Resource temporarily unavailable.
Definition: errno.h:318
struct i386_regs regs
Definition: registers.h:15
#define AR5K_PHY(_n)
Definition: reg.h:1861
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
uint32_t u32
Definition: stdint.h:23

References ah, AR5K_PHY, AR5K_STA_ID0, ath5k_hw_reg_read(), ath5k_hw_reg_write(), c, DBG, EAGAIN, and regs.

Referenced by ath5k_hw_attach().

◆ ath5k_hw_attach()

int ath5k_hw_attach ( struct ath5k_softc sc,
u8  mac_version,
struct ath5k_hw **  hw 
)

ath5k_hw_attach - Check if hw is supported and init the needed structs

@sc: The &struct ath5k_softc we got from the driver's attach function @mac_version: The mac version id (check out ath5k.h) based on pci id @hw: Returned newly allocated hardware structure, on success

Check if the device is supported, perform a POST and initialize the needed structs. Returns -ENOMEM if we don't have memory for the needed structs, -ENODEV if the device is not supported or prints an error msg if something else went wrong.

Definition at line 112 of file ath5k_attach.c.

114 {
115  struct ath5k_hw *ah;
116  struct pci_device *pdev = sc->pdev;
117  int ret;
118  u32 srev;
119 
120  ah = zalloc(sizeof(struct ath5k_hw));
121  if (ah == NULL) {
122  ret = -ENOMEM;
123  DBG("ath5k: out of memory\n");
124  goto err;
125  }
126 
127  ah->ah_sc = sc;
128  ah->ah_iobase = sc->iobase;
129 
130  /*
131  * HW information
132  */
133  ah->ah_turbo = 0;
134  ah->ah_txpower.txp_tpc = 0;
135  ah->ah_imr = 0;
136  ah->ah_atim_window = 0;
137  ah->ah_aifs = AR5K_TUNE_AIFS;
138  ah->ah_cw_min = AR5K_TUNE_CWMIN;
139  ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
140  ah->ah_software_retry = 0;
141  ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
142 
143  /*
144  * Set the mac version based on the pci id
145  */
146  ah->ah_version = mac_version;
147 
148  /*Fill the ath5k_hw struct with the needed functions*/
150  if (ret)
151  goto err_free;
152 
153  /* Bring device out of sleep and reset it's units */
154  ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, 1);
155  if (ret)
156  goto err_free;
157 
158  /* Get MAC, PHY and RADIO revisions */
159  srev = ath5k_hw_reg_read(ah, AR5K_SREV);
160  ah->ah_mac_srev = srev;
161  ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
162  ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
163  ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID);
164  ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, CHANNEL_5GHZ);
165  ah->ah_phy = AR5K_PHY(0);
166 
167  /* Try to identify radio chip based on it's srev */
168  switch (ah->ah_radio_5ghz_revision & 0xf0) {
169  case AR5K_SREV_RAD_5111:
170  ah->ah_radio = AR5K_RF5111;
171  ah->ah_single_chip = 0;
172  ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
173  CHANNEL_2GHZ);
174  break;
175  case AR5K_SREV_RAD_5112:
176  case AR5K_SREV_RAD_2112:
177  ah->ah_radio = AR5K_RF5112;
178  ah->ah_single_chip = 0;
179  ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
180  CHANNEL_2GHZ);
181  break;
182  case AR5K_SREV_RAD_2413:
183  ah->ah_radio = AR5K_RF2413;
184  ah->ah_single_chip = 1;
185  break;
186  case AR5K_SREV_RAD_5413:
187  ah->ah_radio = AR5K_RF5413;
188  ah->ah_single_chip = 1;
189  break;
190  case AR5K_SREV_RAD_2316:
191  ah->ah_radio = AR5K_RF2316;
192  ah->ah_single_chip = 1;
193  break;
194  case AR5K_SREV_RAD_2317:
195  ah->ah_radio = AR5K_RF2317;
196  ah->ah_single_chip = 1;
197  break;
198  case AR5K_SREV_RAD_5424:
199  if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
200  ah->ah_mac_version == AR5K_SREV_AR2417) {
201  ah->ah_radio = AR5K_RF2425;
202  } else {
203  ah->ah_radio = AR5K_RF5413;
204  }
205  ah->ah_single_chip = 1;
206  break;
207  default:
208  /* Identify radio based on mac/phy srev */
209  if (ah->ah_version == AR5K_AR5210) {
210  ah->ah_radio = AR5K_RF5110;
211  ah->ah_single_chip = 0;
212  } else if (ah->ah_version == AR5K_AR5211) {
213  ah->ah_radio = AR5K_RF5111;
214  ah->ah_single_chip = 0;
215  ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
216  CHANNEL_2GHZ);
217  } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
218  ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
219  ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
220  ah->ah_radio = AR5K_RF2425;
221  ah->ah_single_chip = 1;
222  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
223  } else if (srev == AR5K_SREV_AR5213A &&
224  ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
225  ah->ah_radio = AR5K_RF5112;
226  ah->ah_single_chip = 0;
227  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
228  } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
229  ah->ah_radio = AR5K_RF2316;
230  ah->ah_single_chip = 1;
231  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
232  } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
233  ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
234  ah->ah_radio = AR5K_RF5413;
235  ah->ah_single_chip = 1;
236  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
237  } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
238  ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
239  ah->ah_radio = AR5K_RF2413;
240  ah->ah_single_chip = 1;
241  ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
242  } else {
243  DBG("ath5k: Couldn't identify radio revision.\n");
244  ret = -ENOTSUP;
245  goto err_free;
246  }
247  }
248 
249  /* Return on unsuported chips (unsupported eeprom etc) */
250  if ((srev >= AR5K_SREV_AR5416) &&
251  (srev < AR5K_SREV_AR2425)) {
252  DBG("ath5k: Device not yet supported.\n");
253  ret = -ENOTSUP;
254  goto err_free;
255  }
256 
257  /*
258  * Write PCI-E power save settings
259  */
260  if ((ah->ah_version == AR5K_AR5212) &&
262  ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
263  ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
264  /* Shut off RX when elecidle is asserted */
265  ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
266  ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
267  /* TODO: EEPROM work */
268  ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
269  /* Shut off PLL and CLKREQ active in L1 */
270  ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
271  /* Preserce other settings */
272  ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
273  ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
274  ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
275  /* Reset SERDES to load new settings */
277  mdelay(1);
278  }
279 
280  /*
281  * POST
282  */
283  ret = ath5k_hw_post(ah);
284  if (ret)
285  goto err_free;
286 
287  /* Enable pci core retry fix on Hainan (5213A) and later chips */
288  if (srev >= AR5K_SREV_AR5213A)
290 
291  /*
292  * Get card capabilities, calibration values etc
293  * TODO: EEPROM work
294  */
295  ret = ath5k_eeprom_init(ah);
296  if (ret) {
297  DBG("ath5k: unable to init EEPROM\n");
298  goto err_free;
299  }
300 
301  /* Get misc capabilities */
303  if (ret) {
304  DBG("ath5k: unable to get device capabilities: 0x%04x\n",
305  sc->pdev->device);
306  goto err_free;
307  }
308 
309  if (srev >= AR5K_SREV_AR2414) {
310  ah->ah_combined_mic = 1;
313  }
314 
315  /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
316  memset(ah->ah_bssid, 0xff, ETH_ALEN);
317  ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
319 
321 
322  *hw = ah;
323  return 0;
324 err_free:
325  free(ah);
326 err:
327  return ret;
328 }
#define AR5K_SREV
Definition: reg.h:957
static int ath5k_hw_post(struct ath5k_hw *ah)
ath5k_hw_post - Power On Self Test helper function
Definition: ath5k_attach.c:40
#define AR5K_SREV_RAD_5413
Definition: ath5k.h:318
#define AR5K_SREV_RAD_2112
Definition: ath5k.h:314
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:36
#define AR5K_PHY_CHIP_ID
Definition: reg.h:1927
#define AR5K_SREV_PHY_2413
Definition: ath5k.h:329
u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
Definition: ath5k_phy.c:1372
#define AR5K_SREV_REV
Definition: reg.h:958
#define AR5K_PCIE_SERDES
Definition: reg.h:1014
#define AR5K_SREV_AR5414
Definition: ath5k.h:300
#define AR5K_TUNE_ANT_DIVERSITY
Definition: ath5k.h:194
#define AR5K_SREV_PHY_5212B
Definition: ath5k.h:328
#define AR5K_INIT_TX_RETRY
Definition: ath5k.h:228
#define AR5K_PCICFG
Definition: reg.h:880
#define AR5K_REG_MS(_val, _flags)
Definition: ath5k.h:88
#define AR5K_SREV_RAD_5112
Definition: ath5k.h:311
#define AR5K_SREV_AR2417
Definition: ath5k.h:305
#define AR5K_TUNE_CWMIN
Definition: ath5k.h:184
void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
ath5k_hw_set_associd - Set BSSID for association
Definition: ath5k_pcu.c:228
Definition: hw.c:16
#define AR5K_SREV_RAD_2413
Definition: ath5k.h:317
#define AR5K_SREV_RAD_5424
Definition: ath5k.h:321
int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
Definition: ath5k_desc.c:522
ath5k_hw_get_isr - Get interrupt status
Definition: ath5k.h:953
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define AR5K_SREV_RAD_2317
Definition: ath5k.h:320
#define AR5K_PCICFG_RETRY_FIX
Definition: reg.h:898
uint16_t device
Device ID.
Definition: pci.h:204
#define AR5K_SREV_RAD_2425
Definition: ath5k.h:322
#define AR5K_PCIE_SERDES_RESET
Definition: reg.h:1015
int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
Definition: ath5k_caps.c:36
int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
Definition: ath5k_phy.c:158
#define AR5K_SREV_PHY_2425
Definition: ath5k.h:331
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
#define AR5K_SREV_RAD_5112B
Definition: ath5k.h:313
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
#define AR5K_SREV_RAD_2316
Definition: ath5k.h:319
A PCI device.
Definition: pci.h:187
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
Definition: ath5k.h:1222
#define ETH_ALEN
Definition: if_ether.h:8
int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial)
Definition: ath5k_reset.c:282
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:96
#define AR5K_SREV_AR5213A
Definition: ath5k.h:295
struct pci_device * pdev
Definition: base.h:89
#define AR5K_SREV_AR2425
Definition: ath5k.h:304
#define AR5K_TUNE_AIFS
Definition: ath5k.h:181
#define AR5K_SREV_AR5416
Definition: ath5k.h:302
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define AR5K_SREV_AR2415
Definition: ath5k.h:301
int ath5k_hw_set_opmode(struct ath5k_hw *ah)
ath5k_hw_set_opmode - Set PCU operating mode
Definition: ath5k_pcu.c:48
#define AR5K_PHY(_n)
Definition: reg.h:1861
#define AR5K_SREV_PHY_5413
Definition: ath5k.h:330
void * iobase
Definition: base.h:90
#define AR5K_SREV_VER
Definition: reg.h:960
#define CHANNEL_5GHZ
Definition: ath5k.h:633
#define AR5K_SREV_RAD_5111
Definition: ath5k.h:308
uint8_t ah
Definition: registers.h:85
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
Definition: ath5k.h:1214
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define CHANNEL_B
Definition: ath5k.h:639
#define CHANNEL_2GHZ
Definition: ath5k.h:632
#define AR5K_MISC_MODE
Definition: reg.h:1745
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
int ath5k_eeprom_init(struct ath5k_hw *ah)
uint32_t u32
Definition: stdint.h:23
#define AR5K_SREV_AR2414
Definition: ath5k.h:297
#define AR5K_MISC_MODE_COMBINED_MIC
Definition: reg.h:1748
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
Definition: ath5k.h:104
void * memset(void *dest, int character, size_t len) __nonnull

References ah, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_INIT_TX_RETRY, AR5K_MISC_MODE, AR5K_MISC_MODE_COMBINED_MIC, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX, AR5K_PCIE_SERDES, AR5K_PCIE_SERDES_RESET, AR5K_PHY, AR5K_PHY_CHIP_ID, AR5K_REG_ENABLE_BITS, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_SREV, AR5K_SREV_AR2414, AR5K_SREV_AR2415, AR5K_SREV_AR2417, AR5K_SREV_AR2425, AR5K_SREV_AR5213A, AR5K_SREV_AR5414, AR5K_SREV_AR5416, AR5K_SREV_PHY_2413, AR5K_SREV_PHY_2425, AR5K_SREV_PHY_5212B, AR5K_SREV_PHY_5413, AR5K_SREV_RAD_2112, AR5K_SREV_RAD_2316, AR5K_SREV_RAD_2317, AR5K_SREV_RAD_2413, AR5K_SREV_RAD_2425, AR5K_SREV_RAD_5111, AR5K_SREV_RAD_5112, AR5K_SREV_RAD_5112B, AR5K_SREV_RAD_5413, AR5K_SREV_RAD_5424, AR5K_SREV_REV, AR5K_SREV_VER, AR5K_TUNE_AIFS, AR5K_TUNE_ANT_DIVERSITY, AR5K_TUNE_CWMIN, ath5k_eeprom_init(), ath5k_hw_init_desc_functions(), ath5k_hw_nic_wakeup(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_rfgain_opt_init(), ath5k_hw_set_associd(), ath5k_hw_set_capabilities(), ath5k_hw_set_opmode(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_B, DBG, pci_device::device, ENOMEM, ENOTSUP, ETH_ALEN, free, ath5k_softc::iobase, mdelay(), memset(), NULL, PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, and zalloc().

Referenced by ath5k_probe().

◆ ath5k_hw_detach()

void ath5k_hw_detach ( struct ath5k_hw ah)

ath5k_hw_detach - Free the ath5k_hw struct

@ah: The &struct ath5k_hw

Definition at line 335 of file ath5k_attach.c.

336 {
337  free(ah->ah_rf_banks);
339  free(ah);
340 }
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
void ath5k_eeprom_detach(struct ath5k_hw *ah)
uint8_t ah
Definition: registers.h:85

References ah, ath5k_eeprom_detach(), and free.

Referenced by ath5k_probe(), and ath5k_remove().