38 static inline int min(
int x,
int y)
40 return (x < y) ? x : y;
43 static inline int max(
int x,
int y)
45 return (x > y) ? x : y;
58 u32 mask,
data, last_bit, bits_shifted, first_bit;
64 rfb =
ah->ah_rf_banks;
66 for (i = 0; i <
ah->ah_rf_regs_count; i++) {
67 if (rf_regs[i].
index == reg_id) {
74 DBG(
"ath5k: RF register not found!\n");
91 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
92 DBG(
"ath5k: RF invalid values at offset %d\n",
offset);
96 entry = ((first_bit - 1) / 8) +
offset;
97 position = (first_bit - 1) % 8;
102 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
103 position = 0, entry++) {
105 last_bit = (position + bits_left > 8) ? 8 :
106 position + bits_left;
108 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
113 rfb[entry] |= ((
data << position) << (col * 8)) & mask;
114 data >>= (8 - position);
116 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
118 bits_shifted += last_bit - position;
121 bits_left -= 8 - position;
161 switch (
ah->ah_radio) {
164 ah->ah_gain.g_low = 20;
165 ah->ah_gain.g_high = 35;
170 ah->ah_gain.g_low = 20;
171 ah->ah_gain.g_high = 85;
230 g_step = &go->
go_step[
ah->ah_gain.g_step_idx];
232 if (
ah->ah_rf_banks ==
NULL)
235 ah->ah_gain.g_f_corr = 0;
249 ah->ah_gain.g_f_corr =
step * 2;
252 ah->ah_gain.g_f_corr = (
step - 5) * 2;
255 ah->ah_gain.g_f_corr =
step;
258 ah->ah_gain.g_f_corr = 0;
262 return ah->ah_gain.g_f_corr;
274 if (
ah->ah_rf_banks ==
NULL)
286 level[1] = (
step == 63) ? 50 :
step + 4;
287 level[2] = (
step != 63) ? 64 : level[0];
288 level[3] = level[2] + 50 ;
290 ah->ah_gain.g_high = level[3] -
292 ah->ah_gain.g_low = level[0] +
302 level[0] = level[2] = 0;
305 level[1] = level[3] = 83;
307 level[1] = level[3] = 107;
308 ah->ah_gain.g_high = 55;
312 return (
ah->ah_gain.g_current >= level[0] &&
313 ah->ah_gain.g_current <= level[1]) ||
314 (
ah->ah_gain.g_current >= level[2] &&
315 ah->ah_gain.g_current <= level[3]);
326 switch (
ah->ah_radio) {
337 g_step = &go->
go_step[
ah->ah_gain.g_step_idx];
339 if (
ah->ah_gain.g_current >=
ah->ah_gain.g_high) {
342 if (
ah->ah_gain.g_step_idx == 0)
345 for (
ah->ah_gain.g_target =
ah->ah_gain.g_current;
346 ah->ah_gain.g_target >=
ah->ah_gain.g_high &&
347 ah->ah_gain.g_step_idx > 0;
348 g_step = &go->
go_step[
ah->ah_gain.g_step_idx])
349 ah->ah_gain.g_target -= 2 *
357 if (
ah->ah_gain.g_current <=
ah->ah_gain.g_low) {
363 for (
ah->ah_gain.g_target =
ah->ah_gain.g_current;
364 ah->ah_gain.g_target <=
ah->ah_gain.g_low &&
366 g_step = &go->
go_step[
ah->ah_gain.g_step_idx])
367 ah->ah_gain.g_target -= 2 *
376 DBG2(
"ath5k RF adjust: ret %d, gain step %d, current gain %d, " 377 "target gain %d\n", ret,
ah->ah_gain.g_step_idx,
378 ah->ah_gain.g_current,
ah->ah_gain.g_target);
394 if (
ah->ah_rf_banks ==
NULL ||
416 ah->ah_gain.g_current +=
419 ah->ah_gain.g_current +=
427 ah->ah_gain.g_current =
428 ah->ah_gain.g_current >=
ah->ah_gain.g_f_corr ?
429 (
ah->ah_gain.g_current-
ah->ah_gain.g_f_corr) :
446 return ah->ah_gain.g_state;
455 unsigned int i,
size;
457 switch (
ah->ah_radio) {
495 for (i = 0; i <
size; i++) {
524 int obdb = -1, bank = -1;
527 switch (
ah->ah_radio) {
591 if (
ah->ah_rf_banks ==
NULL) {
592 ah->ah_rf_banks =
malloc(
sizeof(
u32) *
ah->ah_rf_banks_size);
593 if (
ah->ah_rf_banks ==
NULL) {
599 rfb =
ah->ah_rf_banks;
601 for (i = 0; i <
ah->ah_rf_banks_size; i++) {
603 DBG(
"ath5k: invalid RF register bank\n");
608 if (bank != ini_rfb[i].rfb_bank) {
610 ah->ah_offset[bank] = i;
650 obdb =
channel->center_freq >= 5725 ? 3 :
651 (
channel->center_freq >= 5500 ? 2 :
652 (
channel->center_freq >= 5260 ? 1 :
653 (
channel->center_freq > 4000 ? 0 : -1)));
665 g_step = &go->
go_step[
ah->ah_gain.g_step_idx];
814 for (i = 0; i <
ah->ah_rf_banks_size; i++) {
834 if ((freq >=
ah->ah_capabilities.cap_range.range_2ghz_min) &&
835 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
838 if ((freq >=
ah->ah_capabilities.cap_range.range_5ghz_min) &&
839 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
919 unsigned int ath5k_channel = ath5k_freq_to_channel(
channel->center_freq);
931 &ath5k_channel_2ghz);
935 ath5k_channel = ath5k_channel_2ghz.
a2_athchan;
940 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
943 (clock << 1) | (1 << 10) | 1;
947 << 2) | (clock << 1) | (1 << 10) | 1;
971 if (!((
c - 2224) % 5)) {
972 data0 = ((2 * (
c - 704)) - 3040) / 10;
974 }
else if (!((
c - 2192) % 5)) {
975 data0 = ((2 * (
c - 672)) - 3040) / 10;
981 }
else if ((
c - (
c % 5)) != 2 ||
c > 5435) {
982 if (!(
c % 20) &&
c >= 5120) {
985 }
else if (!(
c % 10)) {
988 }
else if (!(
c % 5)) {
1022 }
else if ((
c - (
c % 5)) != 2 ||
c > 5435) {
1023 if (!(
c % 20) &&
c < 5120)
1057 DBG(
"ath5k: channel frequency (%d MHz) out of supported " 1058 "range\n",
channel->center_freq);
1065 switch (
ah->ah_radio) {
1081 DBG(
"ath5k: setting channel failed: %s\n",
strerror(ret));
1086 if (
channel->center_freq == 2484) {
1143 DBG(
"ath5k: noise floor calibration timeout (%d MHz)\n", freq);
1148 for (i = 20; i > 0; i--) {
1160 DBG2(
"ath5k: noise floor %d\n", noise_floor);
1163 DBG(
"ath5k: noise floor calibration failed (%d MHz)\n", freq);
1167 ah->ah_noise_floor = noise_floor;
1180 u32 phy_sig, phy_agc, phy_sat, beacon;
1257 DBG(
"ath5k: calibration timeout (%d MHz)\n",
1281 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1284 if (!
ah->ah_calibration ||
1289 for (i = 0; i <= 10; i++) {
1295 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1296 q_coffd = q_pwr >> 7;
1299 if (i_coffd == 0 || q_coffd == 0)
1302 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
1310 q_coff = (((
s32)i_pwr / q_coffd) - 128) & 0x1f;
1397 for (i = 0; i < 8; i++)
1406 ((srev & 0x0f) << 4), 8);
1450 if ((x_left == x_right) || (y_left == y_right))
1459 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1462 result = y_left + (ratio * (target - x_left) / 100);
1477 const s16 *pwrL,
const s16 *pwrR)
1480 s16 min_pwrL, min_pwrR;
1483 if (pwrL[0] == pwrL[1])
1491 stepL[0], stepL[1]);
1497 if (pwrR[0] == pwrR[1])
1505 stepR[0], stepR[1]);
1512 return max(min_pwrL, min_pwrR);
1529 const s16 *pwr,
const u8 *vpd,
1533 u8 idx[2] = { 0, 1 };
1552 for (i = 0; (i <= (
u16) (pmax - pmin)) &&
1558 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
1564 pwr[idx[0]], pwr[idx[1]],
1565 vpd[idx[0]], vpd[idx[1]]);
1609 if (target < pcinfo[0].
freq) {
1617 if (target > pcinfo[
max].
freq) {
1618 idx_l = idx_r =
max;
1626 for (i = 0; i <=
max; i++) {
1631 if (pcinfo[i].
freq == target) {
1639 if (target < pcinfo[i].
freq) {
1647 *pcinfo_l = &pcinfo[idx_l];
1648 *pcinfo_r = &pcinfo[idx_r];
1687 if (target < rpinfo[0].
freq) {
1692 if (target > rpinfo[
max].
freq) {
1693 idx_l = idx_r =
max;
1697 for (i = 0; i <=
max; i++) {
1699 if (rpinfo[i].
freq == target) {
1704 if (target < rpinfo[i].
freq) {
1713 rates->freq = target;
1715 rates->target_power_6to24 =
1721 rates->target_power_36 =
1727 rates->target_power_48 =
1733 rates->target_power_54 =
1754 s16 max_chan_pwr =
ah->ah_txpower.txp_max_pwr / 4;
1788 for (i = 0; i < ee->
ee_ctls; i++) {
1789 if (ctl_val[i] == ctl_mode) {
1797 if (ctl_idx == 0xFF)
1813 if (target <= rep[rep_idx].
freq)
1814 edge_pwr = (
s16) rep[rep_idx].
edge;
1818 ah->ah_txpower.txp_max_pwr = 4*
min(edge_pwr, max_chan_pwr);
1838 u8 *pcdac_out =
ah->ah_txpower.txp_pd_table;
1839 u8 *pcdac_tmp =
ah->ah_txpower.tmpL[0];
1840 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
1841 s16 min_pwr, max_pwr;
1844 min_pwr = table_min[0];
1845 pcdac_0 = pcdac_tmp[0];
1847 max_pwr = table_max[0];
1848 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
1852 for (i = 0; i < min_pwr; i++)
1853 pcdac_out[pcdac_i++] = pcdac_0;
1857 for (i = 0 ; pwr_idx <= max_pwr &&
1859 pcdac_out[pcdac_i++] = pcdac_tmp[i];
1865 pcdac_out[pcdac_i++] = pcdac_n;
1882 s16 *table_max,
u8 pdcurves)
1884 u8 *pcdac_out =
ah->ah_txpower.txp_pd_table;
1891 s16 mid_pwr_idx = 0;
1906 pcdac_low_pwr =
ah->ah_txpower.tmpL[1];
1907 pcdac_high_pwr =
ah->ah_txpower.tmpL[0];
1908 mid_pwr_idx = table_max[1] - table_min[1] - 1;
1909 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
1914 if (table_max[0] - table_min[1] > 126)
1915 min_pwr_idx = table_max[0] - 126;
1917 min_pwr_idx = table_min[1];
1921 pcdac_tmp = pcdac_high_pwr;
1925 pcdac_low_pwr =
ah->ah_txpower.tmpL[1];
1926 pcdac_high_pwr =
ah->ah_txpower.tmpL[0];
1927 min_pwr_idx = table_min[0];
1928 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
1929 pcdac_tmp = pcdac_high_pwr;
1934 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
1938 for (i = 63; i >= 0; i--) {
1942 if (edge_flag == 0x40 &&
1943 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
1945 pcdac_tmp = pcdac_low_pwr;
1946 pwr = mid_pwr_idx/2;
1953 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
1955 pcdac_out[i] = pcdac_out[i + 1];
1961 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
1966 if (pcdac_out[i] > 126)
1978 u8 *pcdac_out =
ah->ah_txpower.txp_pd_table;
1986 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
1987 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2006 s16 *pwr_min,
s16 *pwr_max,
u8 pdcurves)
2009 u8 *pdadc_out =
ah->ah_txpower.txp_pd_table;
2012 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2022 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2023 pdadc_tmp =
ah->ah_txpower.tmpL[pdg];
2025 if (pdg == pdcurves - 1)
2028 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2032 gain_boundaries[pdg] =
2033 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2046 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2050 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2051 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2057 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2058 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2059 pdadc_out[pdadc_i++] = (
tmp < 0) ? 0 : (
u8)
tmp;
2064 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2066 table_size = pwr_max[pdg] - pwr_min[pdg];
2067 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2070 while (pdadc_0 < max_idx)
2071 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2074 if (pdadc_n <= max_idx)
2078 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2079 pwr_step = pdadc_tmp[table_size - 1] -
2080 pdadc_tmp[table_size - 2];
2085 while ((pdadc_0 < (
s16) pdadc_n) &&
2087 s16 tmp = pdadc_tmp[table_size - 1] +
2088 (pdadc_0 - max_idx) * pwr_step;
2089 pdadc_out[pdadc_i++] = (
tmp > 127) ? 127 : (
u8)
tmp;
2095 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2100 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2119 ah->ah_txpower.txp_min_idx = pwr_min[0];
2126 u8 pdcurves,
u8 *pdg_to_idx)
2128 u8 *pdadc_out =
ah->ah_txpower.txp_pd_table;
2169 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2170 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2171 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2172 ((pdadc_out[4*i + 3] & 0xff) << 24),
2213 for (pdg = 0; pdg < ee->
ee_pd_gains[ee_mode]; pdg++) {
2219 u8 idx = pdg_curve_to_idx[pdg];
2226 tmpL =
ah->ah_txpower.tmpL[pdg];
2227 tmpR =
ah->ah_txpower.tmpR[pdg];
2260 if (!(ee->
ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2272 if (table_max[pdg] - table_min[pdg] > 126)
2273 table_min[pdg] = table_max[pdg] - 126;
2289 if (pcinfo_L == pcinfo_R)
2307 for (i = 0; (i < (
u16) (table_max[pdg] - table_min[pdg])) &&
2351 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2362 ah->ah_txpower.txp_min_idx = 0;
2363 ah->ah_txpower.txp_offset = 0;
2379 ah->ah_txpower.txp_offset = table_min[0];
2422 max_pwr =
min(max_pwr, (
u16)
ah->ah_txpower.txp_max_pwr) / 2;
2425 rates =
ah->ah_txpower.txp_rates_power_table;
2428 for (i = 0; i < 5; i++)
2461 for (i = 8; i <= 15; i++)
2462 rates[i] -=
ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2464 ah->ah_txpower.txp_min_pwr =
rates[7];
2465 ah->ah_txpower.txp_max_pwr =
rates[0];
2466 ah->ah_txpower.txp_ofdm =
rates[7];
2475 u8 ee_mode,
u8 txpower)
2482 DBG(
"ath5k: invalid tx power %d\n", txpower);
2489 memset(&
ah->ah_txpower, 0,
sizeof(
ah->ah_txpower));
2491 ah->ah_txpower.txp_min_pwr = 0;
2495 switch (
ah->ah_radio) {
2555 if (
ah->ah_txpower.txp_tpc) {
2576 DBG2(
"ath5k: changing txpower to %d\n", txpower);
#define AR5K_PHY_SHIFT_5GHZ
#define AR5K_PHY_IQRES_CAL_CORR
static const struct ath5k_rf_reg rf_regs_2413[]
#define AR5K_PHY_AGCCTL_NF
#define AR5K_PHY_PAPD_PROBE_GAINF_S
#define EINVAL
Invalid argument.
u8 ee_pd_gains[AR5K_EEPROM_N_MODES]
static const struct ath5k_rf_reg rf_regs_5112a[]
#define AR5K_PHY_TPC_RG1_PDGAIN_2
#define AR5K_PHY_FRAME_CTL
int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode)
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4
static __always_inline void off_t int c
#define AR5K_PHY_SIG_FIRPWR
static void ath5k_create_power_curve(s16 pmin, s16 pmax, const s16 *pwr, const u8 *vpd, u8 num_points, u8 *vpd_table, u8 type)
#define AR5K_PHY_TXPOWER_RATE_MAX
struct ath5k_pdgain_info * pd_curves
static unsigned int unsigned int reg
static const struct ath5k_rf_reg rf_regs_5112[]
#define AR5K_PHY_PAPD_PROBE_TXPOWER
#define AR5K_PHY_AGCCOARSE
#define AR5K_EEPROM_MODE_11G
struct option_descriptor set[0]
#define AR5K_REG_WAIT(_i)
static void ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16 *table_min, s16 *table_max)
u8 ee_ctl[AR5K_EEPROM_MAX_CTLS]
#define AR5K_EEPROM_MODE_11A
#define AR5K_PHY_AGC_DISABLE
u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS]
#define AR5K_BEACON_ENABLE
#define AR5K_PHY_PAPD_PROBE
#define AR5K_PHY_IQ_CORR_ENABLE
#define AR5K_PHY_PAPD_PROBE_TYPE
static void ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 pdcurves, u8 *pdg_to_idx)
#define AR5K_TXPOWER_CCK(_r, _v)
#define AR5K_INI_RFGAIN_5GHZ
uint32_t type
Operating system type.
static u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
static const struct ath5k_rf_reg rf_regs_2425[]
uint8_t size
Entry size (in 32-bit words)
#define AR5K_PHY_SHIFT_2GHZ
#define AR5K_GAIN_CCK_PROBE_CORR
static void ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16 *table_min, s16 *table_max, u8 pdcurves)
#define AR5K_PHY_PAPD_PROBE_TYPE_CCK
static const struct ath5k_ini_rfbuffer rfb_5413[]
#define AR5K_MAX_RF_BANKS
static int min(int x, int y)
static const struct ath5k_ini_rfbuffer rfb_2417[]
#define AR5K_PHY_AGCCTL_CAL
u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES]
u16 ee_x_gain[AR5K_EEPROM_N_MODES]
#define AR5K_REG_MS(_val, _flags)
static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
#define AR5K_PHY_TPC_RG1_PDGAIN_3
#define AR5K_PHY_NF_ACTIVE
static int max(int x, int y)
#define AR5K_GAIN_CHECK_ADJUST(_g)
#define AR5K_PHY_TXPOWER_RATE1
static const struct ath5k_gain_opt rfgain_opt_5111
ath5k_hw_get_isr - Get interrupt status
const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT]
static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
static const struct ath5k_ini_rfgain rfgain_2425[]
#define AR5K_PHY_NF_RVAL(_n)
u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]
#define AR5K_EEPROM_N_PD_GAINS
#define AR5K_TUNE_DEFAULT_TXPOWER
#define AR5K_EEPROM_POWER_TABLE_SIZE
static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel)
static const struct ath5k_ini_rfgain rfgain_2316[]
static int ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
#define ENOMEM
Not enough space.
#define AR5K_PHY_AGCCOARSE_LO
static const struct ath5k_rf_reg rf_regs_5413[]
struct ath5k_rfb_field field
#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN
#define AR5K_PHY_TPC_RG1_PDGAIN_1
#define AR5K_PHY_PCDAC_TXPOWER(_n)
static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs, u32 val, u8 reg_id, int set)
int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel)
#define AR5K_PHY_NF_AVAL(_n)
#define AR5K_PHY_PAPD_PROBE_TX_NEXT
void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
static s16 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, s16 y_left, s16 y_right)
struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)
static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
static const struct ath5k_ini_rfbuffer rfb_2316[]
static void ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, struct ath5k_rate_pcal_info *rate_info, u8 ee_mode)
static void ath5k_setup_pcdac_table(struct ath5k_hw *ah)
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
s8 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS]
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1
uint32_t channel
RNDIS channel.
int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
#define AR5K_TXPOWER_OFDM(_r, _v)
static const struct ath5k_ini_rfbuffer rfb_5112[]
u8 ee_n_piers[AR5K_EEPROM_N_MODES]
#define AR5K_PHY_TXPOWER_RATE3
static const struct ath5k_ini_rfgain rfgain_5112[]
static int ath5k_setup_channel_powertable(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 type)
static const struct ath5k_rf_reg rf_regs_2316[]
char * strerror(int errno)
Retrieve string representation of error number.
static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel)
unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
static const struct ath5k_ini_rfgain rfgain_2413[]
#define AR5K_RF_BUFFER_CONTROL_5
static void ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, struct net80211_channel *channel, struct ath5k_chan_pcal_info **pcinfo_l, struct ath5k_chan_pcal_info **pcinfo_r)
static const struct ath5k_ini_rfbuffer rfb_2425[]
static void ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
#define AR5K_EEPROM_N_EDGES
#define AR5K_DEFAULT_ANTENNA
#define AR5K_PHY_RFSTG_DISABLE
#define AR5K_EEPROM_MODE_11B
int ath5k_hw_phy_disable(struct ath5k_hw *ah)
static const struct ath5k_gain_opt rfgain_opt_5112
static const struct ath5k_rf_reg rf_regs_5111[]
struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
u16 ee_i_gain[AR5K_EEPROM_N_MODES]
static void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
static u32 ath5k_hw_rf5110_chan2athchan(struct net80211_channel *channel)
static const struct ath5k_ini_rfbuffer rfb_2413[]
#define AR5K_TUNE_TPC_TXPOWER
void * malloc(size_t size)
Allocate memory.
u8 rates[0]
Rates data, one rate per byte.
#define EAGAIN
Resource temporarily unavailable.
static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
#define AR5K_PHY_ACT_DISABLE
#define AR5K_RF_BUFFER_CONTROL_3
int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
static void ath5k_get_rate_pcal_data(struct ath5k_hw *ah, struct net80211_channel *channel, struct ath5k_rate_pcal_info *rates)
static s16 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, const s16 *pwrL, const s16 *pwrR)
#define AR5K_TUNE_NOISE_FLOOR
struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN]
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)
#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN
u16 ee_xpd[AR5K_EEPROM_N_MODES]
#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP
#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX
struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN]
static const struct ath5k_ini_rfbuffer rfb_5112a[]
#define AR5K_SREV_RAD_5112A
#define AR5K_PHY_IQ_CORR_Q_I_COFF_S
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3
#define AR5K_DIAG_SW_5210
#define AR5K_INI_RFGAIN_2GHZ
static const struct ath5k_ini_rfgain rfgain_5111[]
void step(void)
Single-step a single process.
struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX]
#define AR5K_PHY_IQRES_CAL_PWR_I
uint8_t data[48]
Additional event data.
int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
uint16_t offset
Offset to command line.
#define AR5K_PHY_CCKTXCTL_WORLD
#define AR5K_SREV_PHY_5212A
#define AR5K_PHY_TXPOWER_RATE4
static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, struct net80211_channel *channel)
int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower)
u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB]
static u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2
static const struct ath5k_ini_rfbuffer rfb_2317[]
struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES *AR5K_EEPROM_MAX_CTLS]
#define AR5K_DIAG_SW_DIS_TX
#define DBG(...)
Print a debugging message.
#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN
#define AR5K_PHY_ADCSAT_THR
#define AR5K_PHY_AGCCOARSE_HI
static const struct ath5k_ini_rfgain rfgain_5413[]
#define AR5K_PHY_FRAME_CTL_TX_CLIP
static void ath5k_get_max_ctl_power(struct ath5k_hw *ah, struct net80211_channel *channel)
u16 ee_cck_ofdm_gain_delta
#define AR5K_PHY_PDADC_TXPOWER(_n)
#define AR5K_PHY_ADCSAT_ICNT
#define AR5K_PHY_CCKTXCTL
#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE
#define NULL
NULL pointer (VOID *)
int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower)
#define AR5K_PHY_IQRES_CAL_PWR_Q
#define AR5K_PHY_TXPOWER_RATE2
struct bofm_section_header done
#define AR5K_CTL_NO_REGDOMAIN
#define AR5K_PHY_ACT_ENABLE
static const struct ath5k_ini_rfbuffer rfb_5111[]
static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, struct ath5k_athchan_2ghz *athchan)
#define AR5K_TUNE_MAX_TXPOWER
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)
void * memset(void *dest, int character, size_t len) __nonnull
#define AR5K_PHY_CCKTXCTL_JAPAN
#define AR5K_RF_BUFFER_CONTROL_0
#define AR5K_DIAG_SW_DIS_RX_5210
#define AR5K_REG_SM(_val, _flags)