iPXE
depca.c
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1 /* #warning "depca.c: FIXME: fix relocation" */
2 
3 FILE_LICENCE ( GPL_ANY );
4 
5 #if 0
6 /* Not fixed for relocation yet. Probably won't work relocated above 16MB */
7 #ifdef ALLMULTI
8 #error multicast support is not yet implemented
9 #endif
10 /* Etherboot: depca.h merged, comments from Linux driver retained */
11 /* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux.
12 
13  Written 1994, 1995 by David C. Davies.
14 
15 
16  Copyright 1994 David C. Davies
17  and
18  United States Government
19  (as represented by the Director, National Security Agency).
20 
21  Copyright 1995 Digital Equipment Corporation.
22 
23 
24  This software may be used and distributed according to the terms of
25  the GNU Public License, incorporated herein by reference.
26 
27  This driver is written for the Digital Equipment Corporation series
28  of DEPCA and EtherWORKS ethernet cards:
29 
30  DEPCA (the original)
31  DE100
32  DE101
33  DE200 Turbo
34  DE201 Turbo
35  DE202 Turbo (TP BNC)
36  DE210
37  DE422 (EISA)
38 
39  The driver has been tested on DE100, DE200 and DE202 cards in a
40  relatively busy network. The DE422 has been tested a little.
41 
42  This driver will NOT work for the DE203, DE204 and DE205 series of
43  cards, since they have a new custom ASIC in place of the AMD LANCE
44  chip. See the 'ewrk3.c' driver in the Linux source tree for running
45  those cards.
46 
47  I have benchmarked the driver with a DE100 at 595kB/s to (542kB/s from)
48  a DECstation 5000/200.
49 
50  The author may be reached at davies@maniac.ultranet.com
51 
52  =========================================================================
53 
54  The driver was originally based on the 'lance.c' driver from Donald
55  Becker which is included with the standard driver distribution for
56  linux. V0.4 is a complete re-write with only the kernel interface
57  remaining from the original code.
58 
59  1) Lance.c code in /linux/drivers/net/
60  2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook",
61  AMD, 1992 [(800) 222-9323].
62  3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)",
63  AMD, Pub. #17881, May 1993.
64  4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA",
65  AMD, Pub. #16907, May 1992
66  5) "DEC EtherWORKS LC Ethernet Controller Owners Manual",
67  Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003
68  6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual",
69  Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003
70  7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR
71  Digital Equipment Corporation, 1989
72  8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual",
73  Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001
74 
75 
76  Peter Bauer's depca.c (V0.5) was referred to when debugging V0.1 of this
77  driver.
78 
79  The original DEPCA card requires that the ethernet ROM address counter
80  be enabled to count and has an 8 bit NICSR. The ROM counter enabling is
81  only done when a 0x08 is read as the first address octet (to minimise
82  the chances of writing over some other hardware's I/O register). The
83  NICSR accesses have been changed to byte accesses for all the cards
84  supported by this driver, since there is only one useful bit in the MSB
85  (remote boot timeout) and it is not used. Also, there is a maximum of
86  only 48kB network RAM for this card. My thanks to Torbjorn Lindh for
87  help debugging all this (and holding my feet to the fire until I got it
88  right).
89 
90  The DE200 series boards have on-board 64kB RAM for use as a shared
91  memory network buffer. Only the DE100 cards make use of a 2kB buffer
92  mode which has not been implemented in this driver (only the 32kB and
93  64kB modes are supported [16kB/48kB for the original DEPCA]).
94 
95  At the most only 2 DEPCA cards can be supported on the ISA bus because
96  there is only provision for two I/O base addresses on each card (0x300
97  and 0x200). The I/O address is detected by searching for a byte sequence
98  in the Ethernet station address PROM at the expected I/O address for the
99  Ethernet PROM. The shared memory base address is 'autoprobed' by
100  looking for the self test PROM and detecting the card name. When a
101  second DEPCA is detected, information is placed in the base_addr
102  variable of the next device structure (which is created if necessary),
103  thus enabling ethif_probe initialization for the device. More than 2
104  EISA cards can be supported, but care will be needed assigning the
105  shared memory to ensure that each slot has the correct IRQ, I/O address
106  and shared memory address assigned.
107 
108  ************************************************************************
109 
110  NOTE: If you are using two ISA DEPCAs, it is important that you assign
111  the base memory addresses correctly. The driver autoprobes I/O 0x300
112  then 0x200. The base memory address for the first device must be less
113  than that of the second so that the auto probe will correctly assign the
114  I/O and memory addresses on the same card. I can't think of a way to do
115  this unambiguously at the moment, since there is nothing on the cards to
116  tie I/O and memory information together.
117 
118  I am unable to test 2 cards together for now, so this code is
119  unchecked. All reports, good or bad, are welcome.
120 
121  ************************************************************************
122 
123  The board IRQ setting must be at an unused IRQ which is auto-probed
124  using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are
125  {2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is
126  really IRQ9 in machines with 16 IRQ lines.
127 
128  No 16MB memory limitation should exist with this driver as DMA is not
129  used and the common memory area is in low memory on the network card (my
130  current system has 20MB and I've not had problems yet).
131 
132  The ability to load this driver as a loadable module has been added. To
133  utilise this ability, you have to do <8 things:
134 
135  0) have a copy of the loadable modules code installed on your system.
136  1) copy depca.c from the /linux/drivers/net directory to your favourite
137  temporary directory.
138  2) if you wish, edit the source code near line 1530 to reflect the I/O
139  address and IRQ you're using (see also 5).
140  3) compile depca.c, but include -DMODULE in the command line to ensure
141  that the correct bits are compiled (see end of source code).
142  4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
143  kernel with the depca configuration turned off and reboot.
144  5) insmod depca.o [irq=7] [io=0x200] [mem=0xd0000] [adapter_name=DE100]
145  [Alan Cox: Changed the code to allow command line irq/io assignments]
146  [Dave Davies: Changed the code to allow command line mem/name
147  assignments]
148  6) run the net startup bits for your eth?? interface manually
149  (usually /etc/rc.inet[12] at boot time).
150  7) enjoy!
151 
152  Note that autoprobing is not allowed in loadable modules - the system is
153  already up and running and you're messing with interrupts.
154 
155  To unload a module, turn off the associated interface
156  'ifconfig eth?? down' then 'rmmod depca'.
157 
158  To assign a base memory address for the shared memory when running as a
159  loadable module, see 5 above. To include the adapter name (if you have
160  no PROM but know the card name) also see 5 above. Note that this last
161  option will not work with kernel built-in depca's.
162 
163  The shared memory assignment for a loadable module makes sense to avoid
164  the 'memory autoprobe' picking the wrong shared memory (for the case of
165  2 depca's in a PC).
166 
167  ************************************************************************
168  Support for MCA EtherWORKS cards added 11-3-98.
169  Verified to work with up to 2 DE212 cards in a system (although not
170  fully stress-tested).
171 
172  Currently known bugs/limitations:
173 
174  Note: with the MCA stuff as a module, it trusts the MCA configuration,
175  not the command line for IRQ and memory address. You can
176  specify them if you want, but it will throw your values out.
177  You still have to pass the IO address it was configured as
178  though.
179 
180  ************************************************************************
181  TO DO:
182  ------
183 
184 
185  Revision History
186  ----------------
187 
188  Version Date Description
189 
190  0.1 25-jan-94 Initial writing.
191  0.2 27-jan-94 Added LANCE TX hardware buffer chaining.
192  0.3 1-feb-94 Added multiple DEPCA support.
193  0.31 4-feb-94 Added DE202 recognition.
194  0.32 19-feb-94 Tidy up. Improve multi-DEPCA support.
195  0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable.
196  Add jabber packet fix from murf@perftech.com
197  and becker@super.org
198  0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access.
199  0.35 8-mar-94 Added DE201 recognition. Tidied up.
200  0.351 30-apr-94 Added EISA support. Added DE422 recognition.
201  0.36 16-may-94 DE422 fix released.
202  0.37 22-jul-94 Added MODULE support
203  0.38 15-aug-94 Added DBR ROM switch in depca_close().
204  Multi DEPCA bug fix.
205  0.38axp 15-sep-94 Special version for Alpha AXP Linux V1.0.
206  0.381 12-dec-94 Added DE101 recognition, fix multicast bug.
207  0.382 9-feb-95 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
208  0.383 22-feb-95 Fix for conflict with VESA SCSI reported by
209  <stromain@alf.dec.com>
210  0.384 17-mar-95 Fix a ring full bug reported by <bkm@star.rl.ac.uk>
211  0.385 3-apr-95 Fix a recognition bug reported by
212  <ryan.niemi@lastfrontier.com>
213  0.386 21-apr-95 Fix the last fix...sorry, must be galloping senility
214  0.40 25-May-95 Rewrite for portability & updated.
215  ALPHA support from <jestabro@amt.tay1.dec.com>
216  0.41 26-Jun-95 Added verify_area() calls in depca_ioctl() from
217  suggestion by <heiko@colossus.escape.de>
218  0.42 27-Dec-95 Add 'mem' shared memory assignment for loadable
219  modules.
220  Add 'adapter_name' for loadable modules when no PROM.
221  Both above from a suggestion by
222  <pchen@woodruffs121.residence.gatech.edu>.
223  Add new multicasting code.
224  0.421 22-Apr-96 Fix alloc_device() bug <jari@markkus2.fimr.fi>
225  0.422 29-Apr-96 Fix depca_hw_init() bug <jari@markkus2.fimr.fi>
226  0.423 7-Jun-96 Fix module load bug <kmg@barco.be>
227  0.43 16-Aug-96 Update alloc_device() to conform to de4x5.c
228  0.44 1-Sep-97 Fix *_probe() to test check_region() first - bug
229  reported by <mmogilvi@elbert.uccs.edu>
230  0.45 3-Nov-98 Added support for MCA EtherWORKS (DE210/DE212) cards
231  by <tymm@computer.org>
232  0.451 5-Nov-98 Fixed mca stuff cuz I'm a dummy. <tymm@computer.org>
233  0.5 14-Nov-98 Re-spin for 2.1.x kernels.
234  0.51 27-Jun-99 Correct received packet length for CRC from
235  report by <worm@dkik.dk>
236 
237  =========================================================================
238 */
239 
240 #include "etherboot.h"
241 #include "nic.h"
242 #include <ipxe/isa.h>
243 #include <ipxe/ethernet.h>
244 
245 /*
246 ** I/O addresses. Note that the 2k buffer option is not supported in
247 ** this driver.
248 */
249 #define DEPCA_NICSR 0x00 /* Network interface CSR */
250 #define DEPCA_RBI 0x02 /* RAM buffer index (2k buffer mode) */
251 #define DEPCA_DATA 0x04 /* LANCE registers' data port */
252 #define DEPCA_ADDR 0x06 /* LANCE registers' address port */
253 #define DEPCA_HBASE 0x08 /* EISA high memory base address reg. */
254 #define DEPCA_PROM 0x0c /* Ethernet address ROM data port */
255 #define DEPCA_CNFG 0x0c /* EISA Configuration port */
256 #define DEPCA_RBSA 0x0e /* RAM buffer starting address (2k buff.) */
257 
258 /*
259 ** These are LANCE registers addressable through nic->ioaddr + DEPCA_ADDR
260 */
261 #define CSR0 0
262 #define CSR1 1
263 #define CSR2 2
264 #define CSR3 3
265 
266 /*
267 ** NETWORK INTERFACE CSR (NI_CSR) bit definitions
268 */
269 
270 #define TO 0x0100 /* Time Out for remote boot */
271 #define SHE 0x0080 /* SHadow memory Enable */
272 #define BS 0x0040 /* Bank Select */
273 #define BUF 0x0020 /* BUFfer size (1->32k, 0->64k) */
274 #define RBE 0x0010 /* Remote Boot Enable (1->net boot) */
275 #define AAC 0x0008 /* Address ROM Address Counter (1->enable) */
276 #define _128KB 0x0008 /* 128kB Network RAM (1->enable) */
277 #define IM 0x0004 /* Interrupt Mask (1->mask) */
278 #define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */
279 #define LED 0x0001 /* LED control */
280 
281 /*
282 ** Control and Status Register 0 (CSR0) bit definitions
283 */
284 
285 #define ERR 0x8000 /* Error summary */
286 #define BABL 0x4000 /* Babble transmitter timeout error */
287 #define CERR 0x2000 /* Collision Error */
288 #define MISS 0x1000 /* Missed packet */
289 #define MERR 0x0800 /* Memory Error */
290 #define RINT 0x0400 /* Receiver Interrupt */
291 #define TINT 0x0200 /* Transmit Interrupt */
292 #define IDON 0x0100 /* Initialization Done */
293 #define INTR 0x0080 /* Interrupt Flag */
294 #define INEA 0x0040 /* Interrupt Enable */
295 #define RXON 0x0020 /* Receiver on */
296 #define TXON 0x0010 /* Transmitter on */
297 #define TDMD 0x0008 /* Transmit Demand */
298 #define STOP 0x0004 /* Stop */
299 #define STRT 0x0002 /* Start */
300 #define INIT 0x0001 /* Initialize */
301 #define INTM 0xff00 /* Interrupt Mask */
302 #define INTE 0xfff0 /* Interrupt Enable */
303 
304 /*
305 ** CONTROL AND STATUS REGISTER 3 (CSR3)
306 */
307 
308 #define BSWP 0x0004 /* Byte SWaP */
309 #define ACON 0x0002 /* ALE control */
310 #define BCON 0x0001 /* Byte CONtrol */
311 
312 /*
313 ** Initialization Block Mode Register
314 */
315 
316 #define PROM 0x8000 /* Promiscuous Mode */
317 #define EMBA 0x0080 /* Enable Modified Back-off Algorithm */
318 #define INTL 0x0040 /* Internal Loopback */
319 #define DRTY 0x0020 /* Disable Retry */
320 #define COLL 0x0010 /* Force Collision */
321 #define DTCR 0x0008 /* Disable Transmit CRC */
322 #define LOOP 0x0004 /* Loopback */
323 #define DTX 0x0002 /* Disable the Transmitter */
324 #define DRX 0x0001 /* Disable the Receiver */
325 
326 /*
327 ** Receive Message Descriptor 1 (RMD1) bit definitions.
328 */
329 
330 #define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
331 #define R_ERR 0x4000 /* Error Summary */
332 #define R_FRAM 0x2000 /* Framing Error */
333 #define R_OFLO 0x1000 /* Overflow Error */
334 #define R_CRC 0x0800 /* CRC Error */
335 #define R_BUFF 0x0400 /* Buffer Error */
336 #define R_STP 0x0200 /* Start of Packet */
337 #define R_ENP 0x0100 /* End of Packet */
338 
339 /*
340 ** Transmit Message Descriptor 1 (TMD1) bit definitions.
341 */
342 
343 #define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */
344 #define T_ERR 0x4000 /* Error Summary */
345 #define T_ADD_FCS 0x2000 /* More the 1 retry needed to Xmit */
346 #define T_MORE 0x1000 /* >1 retry to transmit packet */
347 #define T_ONE 0x0800 /* 1 try needed to transmit the packet */
348 #define T_DEF 0x0400 /* Deferred */
349 #define T_STP 0x02000000 /* Start of Packet */
350 #define T_ENP 0x01000000 /* End of Packet */
351 #define T_FLAGS 0xff000000 /* TX Flags Field */
352 
353 /*
354 ** Transmit Message Descriptor 3 (TMD3) bit definitions.
355 */
356 
357 #define TMD3_BUFF 0x8000 /* BUFFer error */
358 #define TMD3_UFLO 0x4000 /* UnderFLOw error */
359 #define TMD3_RES 0x2000 /* REServed */
360 #define TMD3_LCOL 0x1000 /* Late COLlision */
361 #define TMD3_LCAR 0x0800 /* Loss of CARrier */
362 #define TMD3_RTRY 0x0400 /* ReTRY error */
363 
364 /*
365 ** Ethernet PROM defines
366 */
367 #define PROBE_LENGTH 32
368 
369 /*
370 ** Set the number of Tx and Rx buffers. Ensure that the memory requested
371 ** here is <= to the amount of shared memory set up by the board switches.
372 ** The number of descriptors MUST BE A POWER OF 2.
373 **
374 ** total_memory = NUM_RX_DESC*(8+RX_BUFF_SZ) + NUM_TX_DESC*(8+TX_BUFF_SZ)
375 */
376 #define NUM_RX_DESC 2 /* Number of RX descriptors */
377 #define NUM_TX_DESC 2 /* Number of TX descriptors */
378 #define RX_BUFF_SZ 1536 /* Buffer size for each Rx buffer */
379 #define TX_BUFF_SZ 1536 /* Buffer size for each Tx buffer */
380 
381 /*
382 ** ISA Bus defines
383 */
384 #ifndef DEPCA_MODEL
385 #define DEPCA_MODEL DEPCA
386 #endif
387 
388 static enum {
389  DEPCA, DE100, DE101, DE200, DE201, DE202, DE210, DE212, DE422, unknown
390 } adapter = DEPCA_MODEL;
391 
392 /*
393 ** Name <-> Adapter mapping
394 */
395 
396 static char *adapter_name[] = {
397  "DEPCA",
398  "DE100","DE101",
399  "DE200","DE201","DE202",
400  "DE210","DE212",
401  "DE422",
402  ""
403 };
404 
405 #ifndef DEPCA_RAM_BASE
406 #define DEPCA_RAM_BASE 0xd0000
407 #endif
408 
409 /*
410 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
411 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
412 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
413 ** and hence the RX descriptor ring's first entry.
414 */
415 #define ALIGN4 ((u32)4 - 1) /* 1 longword align */
416 #define ALIGN8 ((u32)8 - 1) /* 2 longword (quadword) align */
417 #define ALIGN ALIGN8 /* Keep the LANCE happy... */
418 
419 /*
420 ** The DEPCA Rx and Tx ring descriptors.
421 */
422 struct depca_rx_desc {
423  volatile s32 base;
424  s16 buf_length; /* This length is negative 2's complement! */
425  s16 msg_length; /* This length is "normal". */
426 };
427 
428 struct depca_tx_desc {
429  volatile s32 base;
430  s16 length; /* This length is negative 2's complement! */
431  s16 misc; /* Errors and TDR info */
432 };
433 
434 #define LA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM
435  to LANCE memory address space */
436 
437 /*
438 ** The Lance initialization block, described in databook, in common memory.
439 */
440 struct depca_init {
441  u16 mode; /* Mode register */
442  u8 phys_addr[ETH_ALEN]; /* Physical ethernet address */
443  u8 mcast_table[8]; /* Multicast Hash Table. */
444  u32 rx_ring; /* Rx ring base pointer & ring length */
445  u32 tx_ring; /* Tx ring base pointer & ring length */
446 };
447 
448 struct depca_private {
449  struct depca_rx_desc *rx_ring;
450  struct depca_tx_desc *tx_ring;
451  struct depca_init init_block; /* Shadow init block */
452  char *rx_memcpy[NUM_RX_DESC];
453  char *tx_memcpy[NUM_TX_DESC];
454  u32 bus_offset; /* ISA bus address offset */
455  u32 sh_mem; /* address of shared mem */
456  u32 dma_buffs; /* Rx & Tx buffer start */
457  int rx_cur, tx_cur; /* Next free ring entry */
458  int txRingMask, rxRingMask;
459  s32 rx_rlen, tx_rlen;
460  /* log2([rt]xRingMask+1) for the descriptors */
461 };
462 
463 static Address mem_start = DEPCA_RAM_BASE;
464 static Address mem_len, offset;
465 static struct depca_private lp;
466 
467 /*
468 ** Miscellaneous defines...
469 */
470 #define STOP_DEPCA(ioaddr) \
471  outw(CSR0, ioaddr + DEPCA_ADDR);\
472  outw(STOP, ioaddr + DEPCA_DATA)
473 
474 /* Initialize the lance Rx and Tx descriptor rings. */
475 static void depca_init_ring(struct nic *nic)
476 {
477  int i;
478  u32 p;
479 
480  lp.rx_cur = lp.tx_cur = 0;
481  /* Initialize the base addresses and length of each buffer in the ring */
482  for (i = 0; i <= lp.rxRingMask; i++) {
483  writel((p = lp.dma_buffs + i * RX_BUFF_SZ) | R_OWN, &lp.rx_ring[i].base);
484  writew(-RX_BUFF_SZ, &lp.rx_ring[i].buf_length);
485  lp.rx_memcpy[i] = (char *) (p + lp.bus_offset);
486  }
487  for (i = 0; i <= lp.txRingMask; i++) {
488  writel((p = lp.dma_buffs + (i + lp.txRingMask + 1) * TX_BUFF_SZ) & 0x00ffffff, &lp.tx_ring[i].base);
489  lp.tx_memcpy[i] = (char *) (p + lp.bus_offset);
490  }
491 
492  /* Set up the initialization block */
493  lp.init_block.rx_ring = ((u32) ((u32) lp.rx_ring) & LA_MASK) | lp.rx_rlen;
494  lp.init_block.tx_ring = ((u32) ((u32) lp.tx_ring) & LA_MASK) | lp.tx_rlen;
495  for (i = 0; i < ETH_ALEN; i++)
496  lp.init_block.phys_addr[i] = nic->node_addr[i];
497  lp.init_block.mode = 0x0000; /* Enable the Tx and Rx */
498  memset(lp.init_block.mcast_table, 0, sizeof(lp.init_block.mcast_table));
499 }
500 
501 static inline void LoadCSRs(struct nic *nic)
502 {
503  outw(CSR1, nic->ioaddr + DEPCA_ADDR); /* initialisation block address LSW */
504  outw((u16) (lp.sh_mem & LA_MASK), nic->ioaddr + DEPCA_DATA);
505  outw(CSR2, nic->ioaddr + DEPCA_ADDR); /* initialisation block address MSW */
506  outw((u16) ((lp.sh_mem & LA_MASK) >> 16), nic->ioaddr + DEPCA_DATA);
507  outw(CSR3, nic->ioaddr + DEPCA_ADDR); /* ALE control */
508  outw(ACON, nic->ioaddr + DEPCA_DATA);
509  outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* Point back to CSR0 */
510 }
511 
512 static inline int InitRestartDepca(struct nic *nic)
513 {
514  int i;
515 
516  /* Copy the shadow init_block to shared memory */
517  memcpy_toio((char *)lp.sh_mem, &lp.init_block, sizeof(struct depca_init));
518  outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* point back to CSR0 */
519  outw(INIT, nic->ioaddr + DEPCA_DATA); /* initialise DEPCA */
520 
521  for (i = 0; i < 100 && !(inw(nic->ioaddr + DEPCA_DATA) & IDON); i++)
522  ;
523  if (i < 100) {
524  /* clear IDON by writing a 1, and start LANCE */
525  outw(IDON | STRT, nic->ioaddr + DEPCA_DATA);
526  } else {
527  printf("DEPCA not initialised\n");
528  return (1);
529  }
530  return (0);
531 }
532 
533 /**************************************************************************
534 RESET - Reset adapter
535 ***************************************************************************/
536 static void depca_reset(struct nic *nic)
537 {
538  s16 nicsr;
539  int i, j;
540 
541  STOP_DEPCA(nic->ioaddr);
542  nicsr = inb(nic->ioaddr + DEPCA_NICSR);
543  nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM);
544  outb(nicsr, nic->ioaddr + DEPCA_NICSR);
545  if (inw(nic->ioaddr + DEPCA_DATA) != STOP)
546  {
547  printf("depca: Cannot stop NIC\n");
548  return;
549  }
550 
551  /* Initialisation block */
552  lp.sh_mem = mem_start;
553  mem_start += sizeof(struct depca_init);
554  /* Tx & Rx descriptors (aligned to a quadword boundary) */
555  mem_start = (mem_start + ALIGN) & ~ALIGN;
556  lp.rx_ring = (struct depca_rx_desc *) mem_start;
557  mem_start += (sizeof(struct depca_rx_desc) * NUM_RX_DESC);
558  lp.tx_ring = (struct depca_tx_desc *) mem_start;
559  mem_start += (sizeof(struct depca_tx_desc) * NUM_TX_DESC);
560 
561  lp.bus_offset = mem_start & 0x00ff0000;
562  /* LANCE re-mapped start address */
563  lp.dma_buffs = mem_start & LA_MASK;
564 
565  /* Finish initialising the ring information. */
566  lp.rxRingMask = NUM_RX_DESC - 1;
567  lp.txRingMask = NUM_TX_DESC - 1;
568 
569  /* Calculate Tx/Rx RLEN size for the descriptors. */
570  for (i = 0, j = lp.rxRingMask; j > 0; i++) {
571  j >>= 1;
572  }
573  lp.rx_rlen = (s32) (i << 29);
574  for (i = 0, j = lp.txRingMask; j > 0; i++) {
575  j >>= 1;
576  }
577  lp.tx_rlen = (s32) (i << 29);
578 
579  /* Load the initialisation block */
580  depca_init_ring(nic);
581  LoadCSRs(nic);
582  InitRestartDepca(nic);
583 }
584 
585 /**************************************************************************
586 POLL - Wait for a frame
587 ***************************************************************************/
588 static int depca_poll(struct nic *nic, int retrieve)
589 {
590  int entry;
591  u32 status;
592 
593  entry = lp.rx_cur;
594  if ((status = readl(&lp.rx_ring[entry].base) & R_OWN))
595  return (0);
596 
597  if ( ! retrieve ) return 1;
598 
599  memcpy(nic->packet, lp.rx_memcpy[entry], nic->packetlen = lp.rx_ring[entry].msg_length);
600  lp.rx_ring[entry].base |= R_OWN;
601  lp.rx_cur = (++lp.rx_cur) & lp.rxRingMask;
602  return (1);
603 }
604 
605 /**************************************************************************
606 TRANSMIT - Transmit a frame
607 ***************************************************************************/
608 static void depca_transmit(
609  struct nic *nic,
610  const char *d, /* Destination */
611  unsigned int t, /* Type */
612  unsigned int s, /* size */
613  const char *p) /* Packet */
614 {
615  int entry, len;
616  char *mem;
617 
618  /* send the packet to destination */
619  /*
620  ** Caution: the right order is important here... dont
621  ** setup the ownership rights until all the other
622  ** information is in place
623  */
624  mem = lp.tx_memcpy[entry = lp.tx_cur];
625  memcpy_toio(mem, d, ETH_ALEN);
626  memcpy_toio(mem + ETH_ALEN, nic->node_addr, ETH_ALEN);
627  mem[ETH_ALEN * 2] = t >> 8;
628  mem[ETH_ALEN * 2 + 1] = t;
629  memcpy_toio(mem + ETH_HLEN, p, s);
630  s += ETH_HLEN;
631  len = (s < ETH_ZLEN ? ETH_ZLEN : s);
632  /* clean out flags */
633  writel(readl(&lp.tx_ring[entry].base) & ~T_FLAGS, &lp.tx_ring[entry].base);
634  /* clears other error flags */
635  writew(0x0000, &lp.tx_ring[entry].misc);
636  /* packet length in buffer */
637  writew(-len, &lp.tx_ring[entry].length);
638  /* start and end of packet, ownership */
639  writel(readl(&lp.tx_ring[entry].base) | (T_STP|T_ENP|T_OWN), &lp.tx_ring[entry].base);
640  /* update current pointers */
641  lp.tx_cur = (++lp.tx_cur) & lp.txRingMask;
642 }
643 
644 /**************************************************************************
645 DISABLE - Turn off ethernet interface
646 ***************************************************************************/
647 static void depca_disable ( struct nic *nic ) {
648  depca_reset(nic);
649 
650  STOP_DEPCA(nic->ioaddr);
651 }
652 
653 /**************************************************************************
654 IRQ - Interrupt Control
655 ***************************************************************************/
656 static void depca_irq(struct nic *nic __unused, irq_action_t action __unused)
657 {
658  switch ( action ) {
659  case DISABLE :
660  break;
661  case ENABLE :
662  break;
663  case FORCE :
664  break;
665  }
666 }
667 
668 /*
669 ** Look for a special sequence in the Ethernet station address PROM that
670 ** is common across all DEPCA products. Note that the original DEPCA needs
671 ** its ROM address counter to be initialized and enabled. Only enable
672 ** if the first address octet is a 0x08 - this minimises the chances of
673 ** messing around with some other hardware, but it assumes that this DEPCA
674 ** card initialized itself correctly.
675 **
676 ** Search the Ethernet address ROM for the signature. Since the ROM address
677 ** counter can start at an arbitrary point, the search must include the entire
678 ** probe sequence length plus the (length_of_the_signature - 1).
679 ** Stop the search IMMEDIATELY after the signature is found so that the
680 ** PROM address counter is correctly positioned at the start of the
681 ** ethernet address for later read out.
682 */
683 
684 
685 /*
686  * Ugly, ugly, ugly. I can't quite make out where the split should be
687  * between probe1 and probe()...
688  *
689  */
690 static u8 nicsr;
691 
692 
693 static int depca_probe1 ( isa_probe_addr_t ioaddr ) {
694  u8 data;
695  /* This is only correct for little endian machines, but then
696  Etherboot doesn't work on anything but a PC */
697  u8 sig[] = { 0xFF, 0x00, 0x55, 0xAA, 0xFF, 0x00, 0x55, 0xAA };
698  int i, j;
699 
700  data = inb(ioaddr + DEPCA_PROM); /* clear counter on DEPCA */
701  data = inb(ioaddr + DEPCA_PROM); /* read data */
702  if (data == 0x8) {
703  nicsr = inb(ioaddr + DEPCA_NICSR);
704  nicsr |= AAC;
705  outb(nicsr, ioaddr + DEPCA_NICSR);
706  }
707  for (i = 0, j = 0; j < (int)sizeof(sig) && i < PROBE_LENGTH+((int)sizeof(sig))-1; ++i) {
708  data = inb(ioaddr + DEPCA_PROM);
709  if (data == sig[j]) /* track signature */
710  ++j;
711  else
712  j = (data == sig[0]) ? 1 : 0;
713  }
714  if (j != sizeof(sig))
715  return (0);
716  /* put the card in its initial state */
717  STOP_DEPCA(ioaddr);
718  nicsr = ((inb(ioaddr + DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM);
719  outb(nicsr, ioaddr + DEPCA_NICSR);
720  if (inw(ioaddr + DEPCA_DATA) != STOP)
721  return (0);
722  memcpy((char *)mem_start, sig, sizeof(sig));
723  if (memcmp((char *)mem_start, sig, sizeof(sig)) != 0)
724  return (0);
725 
726  return 1;
727 }
728 
729 static struct nic_operations depca_operations = {
731  .poll = depca_poll,
732  .transmit = depca_transmit,
733  .irq = depca_irq,
734 
735 };
736 
737 /**************************************************************************
738 PROBE - Look for an adapter, this routine's visible to the outside
739 ***************************************************************************/
740 static int depca_probe ( struct nic *nic, struct isa_device *isa ) {
741 
742  int i, j;
743  long sum, chksum;
744 
745  nic->irqno = 0;
746  nic->ioaddr = isa->ioaddr;
747 
748  for (i = 0, j = 0, sum = 0; j < 3; j++) {
749  sum <<= 1;
750  if (sum > 0xFFFF)
751  sum -= 0xFFFF;
752  sum += (u8)(nic->node_addr[i++] = inb(nic->ioaddr + DEPCA_PROM));
753  sum += (u16)((nic->node_addr[i++] = inb(nic->ioaddr + DEPCA_PROM)) << 8);
754  if (sum > 0xFFFF)
755  sum -= 0xFFFF;
756  }
757  if (sum == 0xFFFF)
758  sum = 0;
759  chksum = (u8)inb(nic->ioaddr + DEPCA_PROM);
760  chksum |= (u16)(inb(nic->ioaddr + DEPCA_PROM) << 8);
761  mem_len = (adapter == DEPCA) ? (48 << 10) : (64 << 10);
762  offset = 0;
763  if (nicsr & BUF) {
764  offset = 0x8000;
765  nicsr &= ~BS;
766  mem_len -= (32 << 10);
767  }
768  if (adapter != DEPCA) /* enable shadow RAM */
769  outb(nicsr |= SHE, nic->ioaddr + DEPCA_NICSR);
770  DBG ( "%s base %4.4x, memory [%4.4lx-%4.4lx] addr %s",
771  adapter_name[adapter], nic->ioaddr, mem_start,
772  mem_start + mem_len, eth_ntoa ( nic->node_addr ) );
773  if (sum != chksum)
774  printf(" (bad checksum)");
775  putchar('\n');
776 
777  depca_reset(nic);
778 
779  /* point to NIC specific routines */
780  nic->nic_op = &depca_operations;
781  return 1;
782 }
783 
784 static isa_probe_addr_t depca_probe_addrs[] = {
785  0x300, 0x200,
786 };
787 
788 ISA_DRIVER ( depca_driver, depca_probe_addrs, depca_probe1,
789  GENERIC_ISAPNP_VENDOR, 0x80f7 );
790 
791 DRIVER ( "depce", nic_driver, isa_driver, depca_driver,
792  depca_probe, depca_disable );
793 
794 ISA_ROM ( "depca", "Digital DE100 and DE200" );
795 
796 #endif
797 
798 /*
799  * Local variables:
800  * c-basic-offset: 8
801  * c-indent-level: 8
802  * tab-width: 8
803  * End:
804  */
unsigned char irqno
Definition: nic.h:56
#define DRIVER(_name_text, _unused2, _unused3, _name, _probe, _disable)
Definition: nic.h:211
#define u16
Definition: vga.h:20
uint16_t u16
Definition: stdint.h:21
uint16_t length
Length.
Definition: intel.h:14
Definition: nic.h:35
uint16_t ioaddr
I/O address.
Definition: isa.h:16
int16_t s16
Definition: stdint.h:20
An ISA device.
Definition: isa.h:12
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
uint16_t inw(volatile uint16_t *io_addr)
Read 16-bit word from I/O-mapped device.
Definition: pcmcia.h:18
u8 sig
Definition: CIB_PRM.h:43
#define outw(data, io_addr)
Definition: io.h:319
int32_t s32
Definition: stdint.h:22
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
void putchar(int character)
Write a single character to each console device.
Definition: console.c:27
Definition: davicom.c:55
#define NUM_RX_DESC
Definition: igbvf.h:281
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
static unsigned int mem_start
Definition: eepro.c:305
Definition: davicom.c:55
uint8_t status
Status.
Definition: ena.h:16
static unsigned long ioaddr
Definition: davicom.c:129
void * memcpy(void *dest, const void *src, size_t len) __nonnull
unsigned int ioaddr
Definition: nic.h:55
#define ETH_HLEN
Definition: if_ether.h:9
Ethernet protocol.
uint16_t isa_probe_addr_t
Definition: isa.h:31
#define GENERIC_ISAPNP_VENDOR
Definition: isa_ids.h:38
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define u32
Definition: vga.h:21
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
#define u8
Definition: igbvf_osdep.h:38
irq_action_t
Definition: nic.h:34
unsigned int packetlen
Definition: nic.h:54
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
#define ALIGN
Definition: relocate.c:29
uint8_t inb(volatile uint8_t *io_addr)
Read byte from I/O-mapped device.
FILE_LICENCE(GPL_ANY)
#define ETH_ALEN
Definition: if_ether.h:8
#define ETH_ZLEN
Definition: if_ether.h:10
unsigned long Address
Definition: etherboot.h:21
Definition: nic.h:37
Definition: nic.h:49
#define ISA_ROM(IMAGE, DESCRIPTION)
Definition: isa.h:92
uint16_t base
Base address.
Definition: edd.h:14
#define rx_ring
Definition: epic100.c:97
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
Definition: nic.h:36
unsigned char * packet
Definition: nic.h:53
unsigned char * node_addr
Definition: nic.h:52
#define outb(data, io_addr)
Definition: io.h:309
#define tx_ring
Definition: epic100.c:98
Definition: davicom.c:55
uint32_t len
Length.
Definition: ena.h:14
#define writew
Definition: w89c840.c:159
An ISA driver.
Definition: isa.h:34
return
Definition: natsemi.h:326
#define ISA_DRIVER(_name, _probe_addrs, _probe_addr, _vendor_id, _prod_id)
Definition: nic.h:179
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
struct nic_operations * nic_op
Definition: nic.h:50
int(* connect)(struct nic *)
Definition: nic.h:63
#define NUM_TX_DESC
Definition: igbvf.h:280
int memcmp(const void *first, const void *second, size_t len)
Compare memory regions.
Definition: string.c:98
Definition: davicom.c:55
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
void * memset(void *dest, int character, size_t len) __nonnull
static unsigned int unsigned int mem
Definition: intel.h:271