iPXE
ice.c
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2022 Michael Brown <mbrown@fensystems.co.uk>.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  *
19  * You can also choose to distribute this program under the terms of
20  * the Unmodified Binary Distribution Licence (as given in the file
21  * COPYING.UBDL), provided that you have satisfied its requirements.
22  */
23 
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25 
26 #include <stdint.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include <errno.h>
30 #include <byteswap.h>
31 #include <ipxe/netdevice.h>
32 #include <ipxe/ethernet.h>
33 #include <ipxe/if_ether.h>
34 #include <ipxe/iobuf.h>
35 #include <ipxe/pci.h>
36 #include "ice.h"
37 
38 /** @file
39  *
40  * Intel 100 Gigabit Ethernet network card driver
41  *
42  */
43 
44 /**
45  * Magic MAC address
46  *
47  * Used as the source address and promiscuous unicast destination
48  * address in the "add switch rules" command.
49  */
50 static uint8_t ice_magic_mac[ETH_HLEN] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 };
51 
52 /******************************************************************************
53  *
54  * Admin queue
55  *
56  ******************************************************************************
57  */
58 
59 /**
60  * Get firmware version
61  *
62  * @v intelxl Intel device
63  * @ret rc Return status code
64  */
65 static int ice_admin_version ( struct intelxl_nic *intelxl ) {
66  struct ice_admin_descriptor *cmd;
68  unsigned int api;
69  int rc;
70 
71  /* Populate descriptor */
72  cmd = ice_admin_command_descriptor ( intelxl );
74  version = &cmd->params.version;
75 
76  /* Issue command */
77  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
78  return rc;
79  api = version->api.major;
80  DBGC ( intelxl, "ICE %p firmware v%d/%d.%d.%d API v%d/%d.%d.%d\n",
81  intelxl, version->firmware.branch, version->firmware.major,
82  version->firmware.minor, version->firmware.patch,
83  version->api.branch, version->api.major, version->api.minor,
84  version->api.patch );
85 
86  /* Check for API compatibility */
87  if ( api > INTELXL_ADMIN_API_MAJOR ) {
88  DBGC ( intelxl, "ICE %p unsupported API v%d\n", intelxl, api );
89  return -ENOTSUP;
90  }
91 
92  return 0;
93 }
94 
95 /**
96  * Get MAC address
97  *
98  * @v netdev Network device
99  * @ret rc Return status code
100  */
101 static int ice_admin_mac_read ( struct net_device *netdev ) {
102  struct intelxl_nic *intelxl = netdev->priv;
103  struct ice_admin_descriptor *cmd;
106  union ice_admin_buffer *buf;
107  unsigned int i;
108  int rc;
109 
110  /* Populate descriptor */
111  cmd = ice_admin_command_descriptor ( intelxl );
112  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_READ );
113  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
114  cmd->len = cpu_to_le16 ( sizeof ( buf->mac_read ) );
115  read = &cmd->params.mac_read;
116  buf = ice_admin_command_buffer ( intelxl );
117 
118  /* Issue command */
119  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
120  return rc;
121 
122  /* Check that MAC address is present in response */
123  if ( ! ( read->valid & INTELXL_ADMIN_MAC_READ_VALID_LAN ) ) {
124  DBGC ( intelxl, "ICE %p has no MAC address\n", intelxl );
125  return -ENOENT;
126  }
127 
128  /* Identify MAC address */
129  for ( i = 0 ; i < read->count ; i++ ) {
130 
131  /* Check for a LAN MAC address */
132  mac = &buf->mac_read.mac[i];
133  if ( mac->type != ICE_ADMIN_MAC_READ_TYPE_LAN )
134  continue;
135 
136  /* Check that address is valid */
137  if ( ! is_valid_ether_addr ( mac->mac ) ) {
138  DBGC ( intelxl, "ICE %p has invalid MAC address "
139  "(%s)\n", intelxl, eth_ntoa ( mac->mac ) );
140  return -EINVAL;
141  }
142 
143  /* Copy MAC address */
144  DBGC ( intelxl, "ICE %p has MAC address %s\n",
145  intelxl, eth_ntoa ( mac->mac ) );
146  memcpy ( netdev->hw_addr, mac->mac, ETH_ALEN );
147 
148  return 0;
149  }
150 
151  /* Missing LAN MAC address */
152  DBGC ( intelxl, "ICE %p has no LAN MAC address\n",
153  intelxl );
154  return -ENOENT;
155 }
156 
157 /**
158  * Set MAC address
159  *
160  * @v netdev Network device
161  * @ret rc Return status code
162  */
163 static int ice_admin_mac_write ( struct net_device *netdev ) {
164  struct intelxl_nic *intelxl = netdev->priv;
165  struct ice_admin_descriptor *cmd;
167  int rc;
168 
169  /* Populate descriptor */
170  cmd = ice_admin_command_descriptor ( intelxl );
172  write = &cmd->params.mac_write;
173  memcpy ( write->mac, netdev->ll_addr, ETH_ALEN );
174 
175  /* Issue command */
176  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
177  return rc;
178 
179  return 0;
180 }
181 
182 /**
183  * Get switch configuration
184  *
185  * @v intelxl Intel device
186  * @ret rc Return status code
187  */
188 static int ice_admin_switch ( struct intelxl_nic *intelxl ) {
189  struct ice_admin_descriptor *cmd;
190  struct ice_admin_switch_params *sw;
191  union ice_admin_buffer *buf;
192  uint16_t next = 0;
193  uint16_t seid;
194  uint16_t type;
195  int rc;
196 
197  /* Get each configuration in turn */
198  do {
199  /* Populate descriptor */
200  cmd = ice_admin_command_descriptor ( intelxl );
201  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
202  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
203  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
204  sw = &cmd->params.sw;
205  sw->next = next;
206  buf = ice_admin_command_buffer ( intelxl );
207 
208  /* Issue command */
209  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
210  return rc;
211  seid = le16_to_cpu ( buf->sw.cfg[0].seid );
212 
213  /* Dump raw configuration */
214  DBGC2 ( intelxl, "ICE %p SEID %#04x:\n", intelxl, seid );
215  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg[0],
216  sizeof ( buf->sw.cfg[0] ) );
217 
218  /* Parse response */
219  type = ( seid & ICE_ADMIN_SWITCH_TYPE_MASK );
220  if ( type == ICE_ADMIN_SWITCH_TYPE_VSI ) {
221  intelxl->vsi = ( seid & ~ICE_ADMIN_SWITCH_TYPE_MASK );
222  DBGC ( intelxl, "ICE %p VSI %#04x uplink %#04x func "
223  "%#04x\n", intelxl, intelxl->vsi,
224  le16_to_cpu ( buf->sw.cfg[0].uplink ),
225  le16_to_cpu ( buf->sw.cfg[0].func ) );
226  }
227 
228  } while ( ( next = sw->next ) );
229 
230  /* Check that we found a VSI */
231  if ( ! intelxl->vsi ) {
232  DBGC ( intelxl, "ICE %p has no VSI\n", intelxl );
233  return -ENOENT;
234  }
235 
236  return 0;
237 }
238 
239 /**
240  * Add switch rules
241  *
242  * @v intelxl Intel device
243  * @v mac MAC address
244  * @ret rc Return status code
245  */
246 static int ice_admin_rules ( struct intelxl_nic *intelxl, uint8_t *mac ) {
247  struct ice_admin_descriptor *cmd;
248  struct ice_admin_rules_params *rules;
249  union ice_admin_buffer *buf;
250  int rc;
251 
252  /* Populate descriptor */
253  cmd = ice_admin_command_descriptor ( intelxl );
254  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_ADD_RULES );
256  cmd->len = cpu_to_le16 ( sizeof ( buf->rules ) );
257  rules = &cmd->params.rules;
258  rules->count = cpu_to_le16 ( 1 );
259  buf = ice_admin_command_buffer ( intelxl );
261  buf->rules.port = cpu_to_le16 ( intelxl->port );
262  buf->rules.action =
264  ICE_ADMIN_RULES_ACTION_VSI ( intelxl->vsi ) );
265  buf->rules.len = cpu_to_le16 ( sizeof ( buf->rules.hdr ) );
266  memcpy ( buf->rules.hdr.eth.h_dest, mac, ETH_ALEN );
269 
270  /* Issue command */
271  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
272  return rc;
273 
274  return 0;
275 }
276 
277 /**
278  * Check if scheduler node is a parent (i.e. non-leaf) node
279  *
280  * @v branch Scheduler topology branch
281  * @v node Scheduler topology node
282  * @ret child Any child node, or NULL if not found
283  */
284 static struct ice_admin_schedule_node *
286  struct ice_admin_schedule_node *node ) {
287  unsigned int count = le16_to_cpu ( branch->count );
288  struct ice_admin_schedule_node *child;
289  unsigned int i;
290 
291  /* Find a child element, if any */
292  for ( i = 0 ; i < count ; i++ ) {
293  child = &branch->node[i];
294  if ( child->parent == node->teid )
295  return child;
296  }
297 
298  return NULL;
299 }
300 
301 /**
302  * Query default scheduling tree topology
303  *
304  * @v intelxl Intel device
305  * @ret rc Return status code
306  */
307 static int ice_admin_schedule ( struct intelxl_nic *intelxl ) {
308  struct ice_admin_descriptor *cmd;
309  struct ice_admin_schedule_params *sched;
310  struct ice_admin_schedule_branch *branch;
312  union ice_admin_buffer *buf;
313  int i;
314  int rc;
315 
316  /* Populate descriptor */
317  cmd = ice_admin_command_descriptor ( intelxl );
318  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_SCHEDULE );
319  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
320  cmd->len = cpu_to_le16 ( sizeof ( buf->sched ) );
321  sched = &cmd->params.sched;
322  buf = ice_admin_command_buffer ( intelxl );
323 
324  /* Issue command */
325  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
326  return rc;
327 
328  /* Sanity checks */
329  if ( ! sched->branches ) {
330  DBGC ( intelxl, "ICE %p topology has no branches\n", intelxl );
331  return -EINVAL;
332  }
333  branch = buf->sched.branch;
334 
335  /* Identify leaf node */
336  for ( i = ( le16_to_cpu ( branch->count ) - 1 ) ; i >= 0 ; i-- ) {
337  node = &branch->node[i];
338  if ( ! ice_admin_schedule_is_parent ( branch, node ) ) {
339  intelxl->teid = le32_to_cpu ( node->teid );
340  DBGC2 ( intelxl, "ICE %p TEID %#08x type %d\n",
341  intelxl, intelxl->teid, node->config.type );
342  break;
343  }
344  }
345  if ( ! intelxl->teid ) {
346  DBGC ( intelxl, "ICE %p found no leaf TEID\n", intelxl );
347  return -EINVAL;
348  }
349 
350  return 0;
351 }
352 
353 /**
354  * Restart autonegotiation
355  *
356  * @v intelxl Intel device
357  * @ret rc Return status code
358  */
359 static int ice_admin_autoneg ( struct intelxl_nic *intelxl ) {
360  struct ice_admin_descriptor *cmd;
361  struct ice_admin_autoneg_params *autoneg;
362  int rc;
363 
364  /* Populate descriptor */
365  cmd = ice_admin_command_descriptor ( intelxl );
366  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
367  autoneg = &cmd->params.autoneg;
370 
371  /* Issue command */
372  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
373  return rc;
374 
375  return 0;
376 }
377 
378 /**
379  * Get link status
380  *
381  * @v netdev Network device
382  * @ret rc Return status code
383  */
384 static int ice_admin_link ( struct net_device *netdev ) {
385  struct intelxl_nic *intelxl = netdev->priv;
386  struct ice_admin_descriptor *cmd;
387  struct ice_admin_link_params *link;
388  union ice_admin_buffer *buf;
389  int rc;
390 
391  /* Populate descriptor */
392  cmd = ice_admin_command_descriptor ( intelxl );
393  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
394  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
395  cmd->len = cpu_to_le16 ( sizeof ( buf->link ) );
396  link = &cmd->params.link;
398  buf = ice_admin_command_buffer ( intelxl );
399 
400  /* Issue command */
401  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
402  return rc;
403  DBGC ( intelxl, "ICE %p speed %#02x status %#02x\n",
404  intelxl, le16_to_cpu ( buf->link.speed ), buf->link.status );
405 
406  /* Update network device */
407  if ( buf->link.status & INTELXL_ADMIN_LINK_UP ) {
409  } else {
411  }
412 
413  return 0;
414 }
415 
416 /**
417  * Handle admin event
418  *
419  * @v netdev Network device
420  * @v xlevt Event descriptor
421  * @v xlbuf Data buffer
422  */
423 static void ice_admin_event ( struct net_device *netdev,
424  struct intelxl_admin_descriptor *xlevt,
425  union intelxl_admin_buffer *xlbuf __unused ) {
426  struct intelxl_nic *intelxl = netdev->priv;
427  struct ice_admin_descriptor *evt =
428  container_of ( xlevt, struct ice_admin_descriptor, xl );
429 
430  /* Ignore unrecognised events */
431  if ( evt->opcode != cpu_to_le16 ( INTELXL_ADMIN_LINK ) ) {
432  DBGC ( intelxl, "INTELXL %p unrecognised event opcode "
433  "%#04x\n", intelxl, le16_to_cpu ( evt->opcode ) );
434  return;
435  }
436 
437  /* Update link status */
439 }
440 
441 /**
442  * Add transmit queue
443  *
444  * @v intelxl Intel device
445  * @v ring Descriptor ring
446  * @ret rc Return status code
447  */
448 static int ice_admin_add_txq ( struct intelxl_nic *intelxl,
449  struct intelxl_ring *ring ) {
450  struct ice_admin_descriptor *cmd;
451  struct ice_admin_add_txq_params *add_txq;
452  union ice_admin_buffer *buf;
453  struct ice_context_tx *ctx;
454  struct ice_schedule_tx *sched;
456  int rc;
457 
458  /* Populate descriptor */
459  cmd = ice_admin_command_descriptor ( intelxl );
460  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_ADD_TXQ );
462  cmd->len = cpu_to_le16 ( sizeof ( buf->add_txq ) );
463  add_txq = &cmd->params.add_txq;
464  add_txq->count = 1;
465  buf = ice_admin_command_buffer ( intelxl );
466  buf->add_txq.parent = cpu_to_le32 ( intelxl->teid );
467  buf->add_txq.count = 1;
468  ctx = &buf->add_txq.ctx;
469  address = dma ( &ring->map, ring->desc.raw );
470  ctx->base_port =
471  cpu_to_le64 ( ICE_TXQ_BASE_PORT ( address, intelxl->port ) );
472  ctx->pf_type = cpu_to_le16 ( ICE_TXQ_PF_TYPE ( intelxl->pf ) );
473  ctx->vsi = cpu_to_le16 ( intelxl->vsi );
476  sched = &buf->add_txq.sched;
481 
482  /* Issue command */
483  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
484  return rc;
485  DBGC ( intelxl, "ICE %p added TEID %#04x\n",
486  intelxl, le32_to_cpu ( buf->add_txq.teid ) );
487 
488  return 0;
489 }
490 
491 /**
492  * Disable transmit queue
493  *
494  * @v intelxl Intel device
495  * @v ring Descriptor ring
496  * @ret rc Return status code
497  */
498 static int ice_admin_disable_txq ( struct intelxl_nic *intelxl ) {
499  struct ice_admin_descriptor *cmd;
500  struct ice_admin_disable_txq_params *disable_txq;
501  union ice_admin_buffer *buf;
502  int rc;
503 
504  /* Populate descriptor */
505  cmd = ice_admin_command_descriptor ( intelxl );
506  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_DISABLE_TXQ );
508  cmd->len = cpu_to_le16 ( sizeof ( buf->disable_txq ) );
509  disable_txq = &cmd->params.disable_txq;
510  disable_txq->flags = ICE_TXQ_FL_FLUSH;
511  disable_txq->count = 1;
512  disable_txq->timeout = ICE_TXQ_TIMEOUT;
513  buf = ice_admin_command_buffer ( intelxl );
514  buf->disable_txq.parent = cpu_to_le32 ( intelxl->teid );
515  buf->disable_txq.count = 1;
516 
517  /* Issue command */
518  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
519  return rc;
520 
521  return 0;
522 }
523 
524 /******************************************************************************
525  *
526  * Network device interface
527  *
528  ******************************************************************************
529  */
530 
531 /**
532  * Dump transmit queue context (for debugging)
533  *
534  * @v intelxl Intel device
535  */
536 static void ice_dump_tx ( struct intelxl_nic *intelxl ) {
537  uint32_t ctx[ sizeof ( struct ice_context_tx ) / sizeof ( uint32_t ) ];
538  uint32_t stat;
539  unsigned int i;
540 
541  /* Do nothing unless debug output is enabled */
542  if ( ! DBG_EXTRA )
543  return;
544 
545  /* Trigger reading of transmit context */
548  intelxl->regs + ICE_GLCOMM_QTX_CNTX_CTL );
549 
550  /* Wait for operation to complete */
551  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
552 
553  /* Check if operation is complete */
554  stat = readl ( intelxl->regs + ICE_GLCOMM_QTX_CNTX_STAT );
555  if ( ! ( stat & ICE_GLCOMM_QTX_CNTX_BUSY ) )
556  break;
557 
558  /* Delay */
559  mdelay ( 1 );
560  }
561 
562  /* Read context registers */
563  for ( i = 0 ; i < ( sizeof ( ctx ) / sizeof ( ctx[0] ) ) ; i++ ) {
564  ctx[i] = cpu_to_le32 ( readl ( intelxl->regs +
565  ICE_GLCOMM_QTX_CNTX_DATA ( i )));
566  }
567 
568  /* Dump context */
569  DBGC2 ( intelxl, "ICE %p TX context:\n", intelxl );
570  DBGC2_HDA ( intelxl, 0, ctx, sizeof ( ctx ) );
571 }
572 
573 /**
574  * Dump receive queue context (for debugging)
575  *
576  * @v intelxl Intel device
577  */
578 static void ice_dump_rx ( struct intelxl_nic *intelxl ) {
579  uint32_t ctx[ sizeof ( struct intelxl_context_rx ) /
580  sizeof ( uint32_t ) ];
581  unsigned int i;
582 
583  /* Do nothing unless debug output is enabled */
584  if ( ! DBG_EXTRA )
585  return;
586 
587  /* Read context registers */
588  for ( i = 0 ; i < ( sizeof ( ctx ) / sizeof ( ctx[0] ) ) ; i++ ) {
589  ctx[i] = cpu_to_le32 ( readl ( intelxl->regs +
590  ICE_QRX_CONTEXT ( i ) ) );
591  }
592 
593  /* Dump context */
594  DBGC2 ( intelxl, "ICE %p RX context:\n", intelxl );
595  DBGC2_HDA ( intelxl, 0, ctx, sizeof ( ctx ) );
596 }
597 
598 /**
599  * Create transmit queue
600  *
601  * @v intelxl Intel device
602  * @v ring Descriptor ring
603  * @ret rc Return status code
604  */
605 static int ice_create_tx ( struct intelxl_nic *intelxl,
606  struct intelxl_ring *ring ) {
607  int rc;
608 
609  /* Allocate descriptor ring */
610  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
611  goto err_alloc;
612 
613  /* Add transmit queue */
614  if ( ( rc = ice_admin_add_txq ( intelxl, ring ) ) != 0 )
615  goto err_add_txq;
616 
617  return 0;
618 
619  err_add_txq:
620  intelxl_free_ring ( intelxl, ring );
621  err_alloc:
622  return rc;
623 }
624 
625 /**
626  * Destroy transmit queue
627  *
628  * @v intelxl Intel device
629  * @v ring Descriptor ring
630  * @ret rc Return status code
631  */
632 static void ice_destroy_tx ( struct intelxl_nic *intelxl,
633  struct intelxl_ring *ring ) {
634  int rc;
635 
636  /* Disable transmit queue */
637  if ( ( rc = ice_admin_disable_txq ( intelxl ) ) != 0 ) {
638  /* Leak memory; there's nothing else we can do */
639  return;
640  }
641 
642  /* Free descriptor ring */
643  intelxl_free_ring ( intelxl, ring );
644 }
645 
646 /**
647  * Program receive queue context
648  *
649  * @v intelxl Intel device
650  * @v address Descriptor ring base address
651  * @ret rc Return status code
652  */
653 static int ice_context_rx ( struct intelxl_nic *intelxl,
654  physaddr_t address ) {
655  union {
656  struct intelxl_context_rx rx;
657  uint32_t raw[ sizeof ( struct intelxl_context_rx ) /
658  sizeof ( uint32_t ) ];
659  } ctx;
661  unsigned int i;
662 
663  /* Initialise context */
664  memset ( &ctx, 0, sizeof ( ctx ) );
666  ctx.rx.base_count = cpu_to_le64 ( base_count );
667  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
669  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
670 
671  /* Write context registers */
672  for ( i = 0 ; i < ( sizeof ( ctx ) / sizeof ( ctx.raw[0] ) ) ; i++ ) {
673  writel ( le32_to_cpu ( ctx.raw[i] ),
674  ( intelxl->regs + ICE_QRX_CONTEXT ( i ) ) );
675  }
676 
677  return 0;
678 }
679 
680 /**
681  * Open network device
682  *
683  * @v netdev Network device
684  * @ret rc Return status code
685  */
686 static int ice_open ( struct net_device *netdev ) {
687  struct intelxl_nic *intelxl = netdev->priv;
688  int rc;
689 
690  /* Calculate maximum frame size */
691  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
692  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
693 
694  /* Set MAC address */
695  if ( ( rc = ice_admin_mac_write ( netdev ) ) != 0 )
696  goto err_mac_write;
697 
698  /* Set maximum frame size */
699  if ( ( rc = intelxl_admin_mac_config ( intelxl ) ) != 0 )
700  goto err_mac_config;
701 
702  /* Create receive descriptor ring */
703  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
704  goto err_create_rx;
705 
706  /* Create transmit descriptor ring */
707  if ( ( rc = ice_create_tx ( intelxl, &intelxl->tx ) ) != 0 )
708  goto err_create_tx;
709 
710  /* Restart autonegotiation */
711  ice_admin_autoneg ( intelxl );
712 
713  /* Update link state */
715 
716  return 0;
717 
718  ice_destroy_tx ( intelxl, &intelxl->tx );
719  err_create_tx:
720  intelxl_destroy_ring ( intelxl, &intelxl->rx );
721  err_create_rx:
722  err_mac_config:
723  err_mac_write:
724  return rc;
725 }
726 
727 /**
728  * Close network device
729  *
730  * @v netdev Network device
731  */
732 static void ice_close ( struct net_device *netdev ) {
733  struct intelxl_nic *intelxl = netdev->priv;
734 
735  /* Dump contexts (for debugging) */
736  ice_dump_tx ( intelxl );
737  ice_dump_rx ( intelxl );
738 
739  /* Destroy transmit descriptor ring */
740  ice_destroy_tx ( intelxl, &intelxl->tx );
741 
742  /* Destroy receive descriptor ring */
743  intelxl_destroy_ring ( intelxl, &intelxl->rx );
744 
745  /* Discard any unused receive buffers */
746  intelxl_empty_rx ( intelxl );
747 }
748 
749 /** Network device operations */
751  .open = ice_open,
752  .close = ice_close,
753  .transmit = intelxl_transmit,
754  .poll = intelxl_poll,
755 };
756 
757 /******************************************************************************
758  *
759  * PCI interface
760  *
761  ******************************************************************************
762  */
763 
764 /**
765  * Probe PCI device
766  *
767  * @v pci PCI device
768  * @ret rc Return status code
769  */
770 static int ice_probe ( struct pci_device *pci ) {
771  struct net_device *netdev;
772  struct intelxl_nic *intelxl;
773  uint32_t pffunc_rid;
774  uint32_t pfgen_portnum;
775  int rc;
776 
777  /* Allocate and initialise net device */
778  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
779  if ( ! netdev ) {
780  rc = -ENOMEM;
781  goto err_alloc;
782  }
785  intelxl = netdev->priv;
786  pci_set_drvdata ( pci, netdev );
787  netdev->dev = &pci->dev;
788  memset ( intelxl, 0, sizeof ( *intelxl ) );
789  intelxl->intr = ICE_GLINT_DYN_CTL;
790  intelxl->handle = ice_admin_event;
796  sizeof ( intelxl->tx.desc.tx[0] ), NULL );
798  sizeof ( intelxl->rx.desc.rx[0] ),
799  ice_context_rx );
800 
801  /* Fix up PCI device */
802  adjust_pci_device ( pci );
803 
804  /* Map registers */
805  intelxl->regs = pci_ioremap ( pci, pci->membase, ICE_BAR_SIZE );
806  if ( ! intelxl->regs ) {
807  rc = -ENODEV;
808  goto err_ioremap;
809  }
810 
811  /* Configure DMA */
812  intelxl->dma = &pci->dma;
813  dma_set_mask_64bit ( intelxl->dma );
814  netdev->dma = intelxl->dma;
815 
816  /* Locate PCI Express capability */
817  intelxl->exp = pci_find_capability ( pci, PCI_CAP_ID_EXP );
818  if ( ! intelxl->exp ) {
819  DBGC ( intelxl, "ICE %p missing PCIe capability\n",
820  intelxl );
821  rc = -ENXIO;
822  goto err_exp;
823  }
824 
825  /* Reset the function via PCIe FLR */
826  pci_reset ( pci, intelxl->exp );
827 
828  /* Get function and port number */
829  pffunc_rid = readl ( intelxl->regs + ICE_PFFUNC_RID );
830  intelxl->pf = ICE_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
831  pfgen_portnum = readl ( intelxl->regs + ICE_PFGEN_PORTNUM );
832  intelxl->port = ICE_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
833  DBGC ( intelxl, "ICE %p PF %d using port %d\n",
834  intelxl, intelxl->pf, intelxl->port );
835 
836  /* Enable MSI-X dummy interrupt */
837  if ( ( rc = intelxl_msix_enable ( intelxl, pci,
838  INTELXL_MSIX_VECTOR ) ) != 0 )
839  goto err_msix;
840 
841  /* Open admin queues */
842  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
843  goto err_open_admin;
844 
845  /* Get firmware version */
846  if ( ( rc = ice_admin_version ( intelxl ) ) != 0 )
847  goto err_admin_version;
848 
849  /* Clear PXE mode */
850  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
851  goto err_admin_clear_pxe;
852 
853  /* Get switch configuration */
854  if ( ( rc = ice_admin_switch ( intelxl ) ) != 0 )
855  goto err_admin_switch;
856 
857  /* Add broadcast address */
858  if ( ( rc = ice_admin_rules ( intelxl, eth_broadcast ) ) != 0 )
859  goto err_admin_rules_broadcast;
860 
861  /* Add promiscuous unicast address */
862  if ( ( rc = ice_admin_rules ( intelxl, ice_magic_mac ) ) != 0 )
863  goto err_admin_rules_magic;
864 
865  /* Query scheduler topology */
866  if ( ( rc = ice_admin_schedule ( intelxl ) ) != 0 )
867  goto err_admin_schedule;
868 
869  /* Get MAC address */
870  if ( ( rc = ice_admin_mac_read ( netdev ) ) != 0 )
871  goto err_admin_mac_read;
872 
873  /* Configure queue register addresses */
874  intelxl->tx.tail = ICE_QTX_COMM_DBELL;
875  intelxl->rx.reg = ICE_QRX_CTRL;
876  intelxl->rx.tail = ICE_QRX_TAIL;
877 
878  /* Configure interrupt causes */
880  intelxl->regs + ICE_QINT_TQCTL );
882  intelxl->regs + ICE_QINT_RQCTL );
883 
884  /* Set a default value for the queue context flex extension,
885  * since this register erroneously retains its value across at
886  * least a PCIe FLR.
887  */
890  intelxl->regs + ICE_QRX_FLXP_CNTXT );
891 
892  /* Register network device */
893  if ( ( rc = register_netdev ( netdev ) ) != 0 )
894  goto err_register_netdev;
895 
896  /* Set initial link state */
898 
899  return 0;
900 
902  err_register_netdev:
903  err_admin_mac_read:
904  err_admin_schedule:
905  err_admin_rules_magic:
906  err_admin_rules_broadcast:
907  err_admin_switch:
908  err_admin_clear_pxe:
909  err_admin_version:
910  intelxl_close_admin ( intelxl );
911  err_open_admin:
912  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
913  err_msix:
914  pci_reset ( pci, intelxl->exp );
915  err_exp:
916  iounmap ( intelxl->regs );
917  err_ioremap:
919  netdev_put ( netdev );
920  err_alloc:
921  return rc;
922 }
923 
924 /**
925  * Remove PCI device
926  *
927  * @v pci PCI device
928  */
929 static void ice_remove ( struct pci_device *pci ) {
930  struct net_device *netdev = pci_get_drvdata ( pci );
931  struct intelxl_nic *intelxl = netdev->priv;
932 
933  /* Unregister network device */
935 
936  /* Close admin queues */
937  intelxl_close_admin ( intelxl );
938 
939  /* Disable MSI-X dummy interrupt */
940  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
941 
942  /* Reset the NIC */
943  pci_reset ( pci, intelxl->exp );
944 
945  /* Free network device */
946  iounmap ( intelxl->regs );
948  netdev_put ( netdev );
949 }
950 
951 /** PCI device IDs */
952 static struct pci_device_id ice_nics[] = {
953  PCI_ROM ( 0x8086, 0x124c, "e823l-bp", "E823-L backplane", 0 ),
954  PCI_ROM ( 0x8086, 0x124d, "e823l-sfp", "E823-L SFP", 0 ),
955  PCI_ROM ( 0x8086, 0x124e, "e823l-10gt", "E823-L 10GBASE-T", 0 ),
956  PCI_ROM ( 0x8086, 0x124f, "e823l-1g", "E823-L 1GbE", 0 ),
957  PCI_ROM ( 0x8086, 0x151d, "e823l-qsfp", "E823-L QSFP", 0 ),
958  PCI_ROM ( 0x8086, 0x1591, "e810c-bp", "E810-C backplane", 0 ),
959  PCI_ROM ( 0x8086, 0x1592, "e810c-qsfp", "E810-C QSFP", 0 ),
960  PCI_ROM ( 0x8086, 0x1593, "e810c-sfp", "E810-C SFP", 0 ),
961  PCI_ROM ( 0x8086, 0x1599, "e810-xxv-bp", "E810-XXV backplane", 0 ),
962  PCI_ROM ( 0x8086, 0x159a, "e810-xxv-qsfp", "E810-XXV QSFP", 0 ),
963  PCI_ROM ( 0x8086, 0x159b, "e810-xxv-sfp", "E810-XXV SFP", 0 ),
964  PCI_ROM ( 0x8086, 0x188a, "e823c-bp", "E823-C backplane", 0 ),
965  PCI_ROM ( 0x8086, 0x188b, "e823c-qsfp", "E823-C QSFP", 0 ),
966  PCI_ROM ( 0x8086, 0x188c, "e823c-sfp", "E823-C SFP", 0 ),
967  PCI_ROM ( 0x8086, 0x188d, "e823c-10gt", "E823-C 10GBASE-T", 0 ),
968  PCI_ROM ( 0x8086, 0x188e, "e823c-1g", "E823-C 1GbE", 0 ),
969  PCI_ROM ( 0x8086, 0x1890, "e822c-bp", "E822-C backplane", 0 ),
970  PCI_ROM ( 0x8086, 0x1891, "e822c-qsfp", "E822-C QSFP", 0 ),
971  PCI_ROM ( 0x8086, 0x1892, "e822c-sfp", "E822-C SFP", 0 ),
972  PCI_ROM ( 0x8086, 0x1893, "e822c-10gt", "E822-C 10GBASE-T", 0 ),
973  PCI_ROM ( 0x8086, 0x1894, "e822c-1g", "E822-C 1GbE", 0 ),
974  PCI_ROM ( 0x8086, 0x1897, "e822l-bp", "E822-L backplane", 0 ),
975  PCI_ROM ( 0x8086, 0x1898, "e822l-sfp", "E822-L SFP", 0 ),
976  PCI_ROM ( 0x8086, 0x1899, "e822l-10gt", "E822-L 10GBASE-T", 0 ),
977  PCI_ROM ( 0x8086, 0x189a, "e822l-1g", "E822-L 1GbE", 0 ),
978 };
979 
980 /** PCI driver */
981 struct pci_driver ice_driver __pci_driver = {
982  .ids = ice_nics,
983  .id_count = ( sizeof ( ice_nics ) / sizeof ( ice_nics[0] ) ),
984  .probe = ice_probe,
985  .remove = ice_remove,
986 };
Receive queue context.
Definition: intelxl.h:567
Admin queue data buffer.
Definition: ice.h:458
uint16_t h_protocol
Protocol ID.
Definition: if_ether.h:36
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1510
#define ICE_SCHEDULE_EXCESS
Transmit scheduler configuration excess bandwidth section is valid.
Definition: ice.h:275
union ice_admin_rules_buffer::@46 hdr
Header data.
void * regs
Registers.
Definition: intelxl.h:921
#define EINVAL
Invalid argument.
Definition: errno.h:428
uint16_t len
Header length.
Definition: ice.h:236
struct option_descriptor read[1]
Definition: nvo_cmd.c:115
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:337
unsigned long membase
Memory base.
Definition: pci.h:215
struct dma_device * dma
DMA device.
Definition: intelxl.h:923
Admin queue Get Version command parameters.
Definition: ice.h:122
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:591
unsigned short uint16_t
Definition: stdint.h:11
MAC Address description.
Definition: ice.h:146
struct dma_device dma
DMA device.
Definition: pci.h:210
struct ice_schedule_tx sched
Scheduler configuration.
Definition: ice.h:376
#define ICE_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: ice.h:555
uint8_t flags
Flags.
Definition: ice.h:315
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1317
#define ICE_ADMIN_DISABLE_TXQ
Admin queue Disable Transmit Queues command.
Definition: ice.h:396
#define ICE_TXQ_FL_FLUSH
Disable queue and flush pipe.
Definition: ice.h:413
#define ICE_TXQ_PF_TYPE(pf)
Transmit queue PF number.
Definition: ice.h:384
A PCI driver.
Definition: pci.h:245
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:39
Intel 100 Gigabit Ethernet network card driver.
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:343
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:38
uint32_t next
Next descriptor address.
Definition: myson.h:18
uint8_t count
Number of queues.
Definition: ice.h:364
static int ice_admin_link(struct net_device *netdev)
Get link status.
Definition: ice.c:384
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:206
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:326
Error codes.
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:972
uint16_t count
Number of nodes.
Definition: ice.h:295
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:36
struct ice_admin_schedule_node node[0]
Nodes.
Definition: ice.h:299
static void ice_close(struct net_device *netdev)
Close network device.
Definition: ice.c:732
Admin queue register offsets.
Definition: intelxl.h:63
I/O buffers.
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:247
uint64_t address
Base address.
Definition: ena.h:24
uint32_t type
Operating system type.
Definition: ena.h:12
union ice_admin_schedule_buffer sched
Query Default Scheduling Tree Topology data buffer.
Definition: ice.h:468
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:415
#define ICE_ADMIN_ADD_RULES
Admin queue Add Switch Rules command.
Definition: ice.h:211
uint32_t parent
Parent TEID.
Definition: ice.h:421
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define ICE_ADMIN_RULES_RECIPE_PROMISC
Switch rule promiscuous recipe ID.
Definition: ice.h:247
uint8_t eth_broadcast[ETH_ALEN]
Ethernet broadcast MAC address.
Definition: ethernet.c:47
Admin queue Add Transmit Queues command parameters.
Definition: ice.h:352
uint16_t uplink
Uplink switching element ID.
Definition: ice.h:193
#define DBGC(...)
Definition: compiler.h:505
static int ice_admin_rules(struct intelxl_nic *intelxl, uint8_t *mac)
Add switch rules.
Definition: ice.c:246
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:578
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:951
#define ENOENT
No such file or directory.
Definition: errno.h:514
#define ICE_ADMIN_RULES_ACTION_VALID
Switch rule action valid.
Definition: ice.h:250
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:474
unsigned long long uint64_t
Definition: stdint.h:13
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:510
struct dma_device * dma
DMA device.
Definition: netdevice.h:366
uint8_t sections
Valid sections.
Definition: ice.h:48
#define cpu_to_le64(value)
Definition: byteswap.h:108
#define ICE_QRX_FLXP_CNTXT_RXDID_PRIO_MAX
Maximum priority.
Definition: ice.h:99
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
uint16_t port
Source port.
Definition: ice.h:230
#define ICE_ADMIN_SCHEDULE
Admin queue Query Default Scheduling Tree Topology command.
Definition: ice.h:256
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:600
static int ice_admin_mac_read(struct net_device *netdev)
Get MAC address.
Definition: ice.c:101
static int ice_admin_add_txq(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Add transmit queue.
Definition: ice.c:448
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:26
#define ICE_QRX_FLXP_CNTXT
Queue Context Flex Extension Register.
Definition: ice.h:94
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
Admin queue Query Default Scheduling Tree Topology node.
Definition: ice.h:281
size_t mfs
Maximum frame size.
Definition: intelxl.h:925
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:894
static struct net_device_operations ice_operations
Network device operations.
Definition: ice.c:750
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:124
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:759
#define ICE_GLCOMM_QTX_CNTX_STAT
Transmit Comm Scheduler Queue Context Status Register.
Definition: ice.h:90
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:154
static int ice_create_tx(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create transmit queue.
Definition: ice.c:605
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:594
struct device dev
Generic device.
Definition: pci.h:208
uint16_t func
PF/VF number.
Definition: ice.h:195
static void ice_destroy_tx(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy transmit queue.
Definition: ice.c:632
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:946
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
Admin queue Query Default Scheduling Tree Topology command parameters.
Definition: ice.h:259
#define ICE_TXQ_BASE_PORT(addr, port)
Transmit queue base address and port number.
Definition: ice.h:380
#define INTELXL_ADMIN_MAC_READ_VALID_LAN
LAN MAC address is valid.
Definition: intelxl.h:160
#define ICE_QRX_FLXP_CNTXT_RXDID_IDX_LEGACY_32
32-byte legacy
Definition: ice.h:96
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:510
#define ICE_TXQ_FL_LEGACY
Transmit queue uses legacy mode.
Definition: ice.h:393
Admin queue Add Switch Rules command parameters.
Definition: ice.h:214
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:357
uint8_t h_dest[ETH_ALEN]
Destination MAC address.
Definition: if_ether.h:32
uint16_t opcode
Opcode.
Definition: ice.h:488
#define ENOMEM
Not enough space.
Definition: errno.h:534
uint8_t count
Number of queue groups.
Definition: ice.h:354
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define ICE_SCHEDULE_GENERIC
Transmit scheduler configuration generic section is valid.
Definition: ice.h:269
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:961
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:475
#define ICE_QTX_COMM_DBELL
Transmit Comm Scheduler Queue Doorbell Register.
Definition: ice.h:77
u32 version
Driver version.
Definition: ath9k_hw.c:1983
static int ice_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: ice.c:188
struct ice_admin_version api
API version.
Definition: ice.h:130
#define ETH_HLEN
Definition: if_ether.h:9
#define ICE_QRX_CONTEXT(x)
Receive Queue Context Registers.
Definition: ice.h:71
#define ICE_QINT_TQCTL
Transmit Queue Interrupt Cause Control Register.
Definition: ice.h:551
struct ice_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
Definition: ice.h:462
#define INTELXL_MAX_PKT_LEN
Maximum packet length (excluding CRC)
Definition: intelxl.h:826
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:567
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
Ethernet protocol.
Admin queue version number.
Definition: ice.h:110
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:936
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:808
void * priv
Driver private data.
Definition: netdevice.h:431
uint16_t seid
Switching element ID and flags.
Definition: ice.h:191
static void ice_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *xlevt, union intelxl_admin_buffer *xlbuf __unused)
Handle admin event.
Definition: ice.c:423
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:780
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define ICE_SCHEDULE_WEIGHT
Transmit scheduler configuration default weight.
Definition: ice.h:278
void * raw
Raw data.
Definition: intelxl.h:763
uint16_t excess_weight
Excess bandwidth weight.
Definition: ice.h:60
Admin queue Get Switch Configuration command parameters.
Definition: ice.h:177
static struct net_device * netdev
Definition: gdbudp.c:52
#define ICE_ADMIN_SWITCH_TYPE_MASK
Switching element ID type mask.
Definition: ice.h:199
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:817
Admin queue Manage MAC Address Read command parameters.
Definition: ice.h:134
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:87
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1283
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:899
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:489
union intelxl_ring::@65 desc
Descriptors.
#define ICE_ADMIN_RULES_ACTION_VSI(x)
Switch rule VSI number.
Definition: ice.h:253
unsigned int reg
Register block.
Definition: intelxl.h:773
#define ICE_QRX_CTRL
Global Receive Queue Control Register.
Definition: ice.h:68
#define cpu_to_le32(value)
Definition: byteswap.h:107
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:1013
#define DBGC2_HDA(...)
Definition: compiler.h:523
struct pci_driver ice_driver __pci_driver
PCI driver.
Definition: ice.c:981
#define INTELXL_ADMIN_MAC_READ
Admin queue Manage MAC Address Read command.
Definition: intelxl.h:149
static void ice_dump_rx(struct intelxl_nic *intelxl)
Dump receive queue context (for debugging)
Definition: ice.c:578
static struct ice_admin_schedule_node * ice_admin_schedule_is_parent(struct ice_admin_schedule_branch *branch, struct ice_admin_schedule_node *node)
Check if scheduler node is a parent (i.e.
Definition: ice.c:285
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:761
#define ICE_GLCOMM_QTX_CNTX_CTL
Transmit Comm Scheduler Queue Context Control Register.
Definition: ice.h:83
struct ice_admin_link_buffer link
Get Link Status data buffer.
Definition: ice.h:470
Admin queue Query Default Scheduling Tree Topology branch.
Definition: ice.h:291
#define ICE_GLINT_DYN_CTL
Global Interrupt Dynamic Control Register.
Definition: ice.h:565
static void ice_dump_tx(struct intelxl_nic *intelxl)
Dump transmit queue context (for debugging)
Definition: ice.c:536
PCI bus.
static int ice_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: ice.c:359
#define ICE_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: ice.h:562
A PCI device.
Definition: pci.h:206
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:722
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
device nvs write
Definition: threewire.h:61
unsigned int intr
Interrupt control register.
Definition: intelxl.h:944
Admin queue Manage MAC Address Write command parameters.
Definition: ice.h:165
A network device.
Definition: netdevice.h:352
uint64_t base_count
Base address and queue count.
Definition: intelxl.h:573
#define ENODEV
No such device.
Definition: errno.h:509
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:523
#define INTELXL_ADMIN_MAC_WRITE
Admin queue Manage MAC Address Write command.
Definition: intelxl.h:175
#define ICE_SCHEDULE_COMMIT
Transmit scheduler configuration committed bandwidth section is valid.
Definition: ice.h:272
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:766
unsigned char uint8_t
Definition: stdint.h:10
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:445
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:105
unsigned int port
Port number.
Definition: intelxl.h:932
struct ice_admin_switch_config cfg[1]
Switch configuration.
Definition: ice.h:207
static int ice_admin_schedule(struct intelxl_nic *intelxl)
Query default scheduling tree topology.
Definition: ice.c:307
struct ice_context_tx ctx
Transmit queue context.
Definition: ice.h:374
uint8_t h_source[ETH_ALEN]
Source MAC address.
Definition: if_ether.h:34
An Intel 40 Gigabit network card.
Definition: intelxl.h:919
#define ETH_ALEN
Definition: if_ether.h:8
struct ethhdr eth
Ethernet header.
Definition: ice.h:240
A PCI device ID list entry.
Definition: pci.h:170
static int ice_admin_mac_write(struct net_device *netdev)
Set MAC address.
Definition: ice.c:163
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:795
uint32_t node
NUMA node register offset.
Definition: ena.h:18
struct ice_admin_disable_txq_buffer disable_txq
Disable Transmit Queue data buffer.
Definition: ice.h:474
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:77
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:959
Transmit queue context.
Definition: ice.h:26
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:97
Admin queue descriptor.
Definition: ice.h:478
uint32_t teid
Transmit element ID.
Definition: intelxl.h:940
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:295
Network device operations.
Definition: netdevice.h:213
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:916
struct device * dev
Underlying hardware device.
Definition: netdevice.h:364
static int ice_admin_disable_txq(struct intelxl_nic *intelxl)
Disable transmit queue.
Definition: ice.c:498
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:597
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:524
Network device management.
unsigned long physaddr_t
Definition: stdint.h:20
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
uint32_t action
Action.
Definition: ice.h:232
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:367
unsigned int pf
Physical function number.
Definition: intelxl.h:928
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Admin queue descriptor.
Definition: intelxl.h:415
#define ENXIO
No such device or address.
Definition: errno.h:599
static int ice_probe(struct pci_device *pci)
Probe PCI device.
Definition: ice.c:770
static struct pci_device_id ice_nics[]
PCI device IDs.
Definition: ice.c:952
#define ICE_QINT_RQCTL_ITR_INDX_NONE
No throttling.
Definition: ice.h:560
#define ICE_QINT_RQCTL
Receive Queue Interrupt Cause Control Register.
Definition: ice.h:558
static int ice_open(struct net_device *netdev)
Open network device.
Definition: ice.c:686
#define ICE_ADMIN_MAC_READ_TYPE_LAN
LAN MAC address type.
Definition: ice.h:156
struct ice_admin_rules_buffer rules
Add Switch Rules data buffer.
Definition: ice.h:466
#define ICE_PFFUNC_RID
Function Requester ID Information Register.
Definition: ice.h:539
#define DBGC2(...)
Definition: compiler.h:522
Transmit scheduler configuration.
Definition: ice.h:44
#define ICE_TXQ_FL_TSO
Transmit queue uses TSO.
Definition: ice.h:390
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:258
#define ICE_GLCOMM_QTX_CNTX_BUSY
In progress.
Definition: ice.h:91
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:365
#define ICE_GLCOMM_QTX_CNTX_CTL_EXEC
Execute.
Definition: ice.h:87
Admin queue Restart Autonegotiation command parameters.
Definition: ice.h:311
#define ICE_TXQ_TIMEOUT
Disable queue timeout.
Definition: ice.h:416
struct ice_admin_mac_read_address mac[4]
MAC addresses.
Definition: ice.h:161
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:362
struct ice_admin_schedule_branch branch[0]
Branches.
Definition: ice.h:305
#define ICE_ADMIN_SWITCH_TYPE_VSI
Virtual Station Interface element type.
Definition: ice.h:202
uint16_t count
Number of entries.
Definition: ena.h:22
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
static uint8_t ice_magic_mac[ETH_HLEN]
Magic MAC address.
Definition: ice.c:50
#define cpu_to_le16(value)
Definition: byteswap.h:106
static void ice_remove(struct pci_device *pci)
Remove PCI device.
Definition: ice.c:929
#define ICE_GLCOMM_QTX_CNTX_DATA(x)
Transmit Comm Scheduler Queue Context Data Registers.
Definition: ice.h:80
void iounmap(volatile const void *io_addr)
Unmap I/O address.
Descriptor ring.
Definition: intelxl.h:755
#define ICE_BAR_SIZE
BAR size.
Definition: ice.h:16
unsigned int tail
Tail register.
Definition: intelxl.h:775
#define ICE_QRX_TAIL
Receive Queue Tail Register.
Definition: ice.h:74
struct intelxl_admin_descriptor xl
Original 40 Gigabit Ethernet descriptor.
Definition: ice.h:482
__be32 raw[7]
Definition: CIB_PRM.h:28
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:340
uint32_t teid
Queue TEID.
Definition: ice.h:372
#define DBG_EXTRA
Definition: compiler.h:319
#define ICE_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: ice.h:540
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:387
static int ice_context_rx(struct intelxl_nic *intelxl, physaddr_t address)
Program receive queue context.
Definition: ice.c:653
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:409
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:946
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
#define ICE_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: ice.h:546
static __always_inline physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
Definition: dma.h:436
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
uint16_t commit_weight
Committeed bandwidth weight.
Definition: ice.h:56
struct ice_admin_add_txq_buffer add_txq
Add Transmit Queue data buffer.
Definition: ice.h:472
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:603
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:442
static int ice_admin_version(struct intelxl_nic *intelxl)
Get firmware version.
Definition: ice.c:65
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:587
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:381
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define ICE_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: ice.h:545
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:953
String functions.
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:301
Admin queue Disable Transmit Queues command parameters.
Definition: ice.h:399
uint32_t parent
Parent TEID.
Definition: ice.h:283
#define ICE_ADMIN_ADD_TXQ
Admin queue Add Transmit Queues command.
Definition: ice.h:349
#define htons(value)
Definition: byteswap.h:135
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1384
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.
Definition: intelxl.c:729
struct ice_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: ice.h:464
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1630
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:974
#define ETH_P_8021Q
Definition: if_ether.h:21
Admin queue data buffer.
Definition: intelxl.h:401
#define ICE_QINT_TQCTL_ITR_INDX_NONE
No throttling.
Definition: ice.h:553
#define ICE_TXQ_LEN(count)
Transmit queue length.
Definition: ice.h:387
#define ICE_GLCOMM_QTX_CNTX_CTL_CMD_READ
Read context.
Definition: ice.h:85
uint16_t recipe
Receipt ID.
Definition: ice.h:228
void * memset(void *dest, int character, size_t len) __nonnull
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:62
uint32_t parent
Parent TEID.
Definition: ice.h:362
uint8_t count
Number of queues.
Definition: ice.h:423